changelog
- Wed, 28 Feb 2018 11:08:51 +0800
- by fujie [Wed, 28 Feb 2018 11:08:51 +0800] rev 8026
- Unnecessary volatile barriers were removed.
- Wed, 28 Feb 2018 09:37:24 +0800
- by fujie [Wed, 28 Feb 2018 09:37:24 +0800] rev 8025
- Volatile barriers were added aggressively in interpreter.
- Wed, 28 Feb 2018 08:32:45 +0800
- by fujie [Wed, 28 Feb 2018 08:32:45 +0800] rev 8024
- Code for debugging shouldn't be generated in release version.
- Wed, 07 Feb 2018 13:00:31 +0800
- by aoqi [Wed, 07 Feb 2018 13:00:31 +0800] rev 8023
- #6578 On MIPS, add the end of the previous instruction to the implicit exception table when the node is a null check
Reviewed-by: fujie
Summary: the last instruction of the previous node (usually a instruction sequence) is the instruction which access memory on MIPS.
For example:
StoreB
NullCheck
=>
daddiu at,zero,1 ;wrong implicit exception dispatch position
sb at,18(s3) ;right implicit exception dispatch position
- Wed, 07 Feb 2018 15:44:45 +0800
- by fujie [Wed, 07 Feb 2018 15:44:45 +0800] rev 8022
- Follows 5e952d5ef68a, the cost of sync is high.
- Thu, 01 Feb 2018 09:25:24 +0800
- by aoqi [Thu, 01 Feb 2018 09:25:24 +0800] rev 8021
- [Code Reorganization] delete a trailing whitespace to pass jcheck
- Thu, 01 Feb 2018 09:22:45 +0800
- by aoqi [Thu, 01 Feb 2018 09:22:45 +0800] rev 8020
- #6549 adds store store barrier and acquire barrier
- Tue, 12 Dec 2017 10:30:27 +0800
- by aoqi [Tue, 12 Dec 2017 10:30:27 +0800] rev 8019
- #6345 sync is controled by UseSyncLevel instead of Use3A2000
Reviewed-by: fujie
- Thu, 07 Dec 2017 16:21:29 +0800
- by aoqi [Thu, 07 Dec 2017 16:21:29 +0800] rev 8018
- #6440 3A1000 and 3B1500 cases in read_cpu_info are more strict.
- Thu, 07 Dec 2017 16:07:58 +0800
- by aoqi [Thu, 07 Dec 2017 16:07:58 +0800] rev 8017
- #6439 3B1500 is not gs464v but gs464.
- Tue, 28 Nov 2017 15:50:12 +0800
- by aoqi [Tue, 28 Nov 2017 15:50:12 +0800] rev 8016
- #6408 cpuinfo support 2K1000 and gs264
Reviewed-by: chenhaoxuan
- Tue, 28 Nov 2017 15:31:16 +0800
- by aoqi [Tue, 28 Nov 2017 15:31:16 +0800] rev 8015
- #6313 disable DSP support on Loongson CPUs, added asserts when DSP instructions are generated.
- Fri, 01 Dec 2017 13:52:28 +0800
- by fujie [Fri, 01 Dec 2017 13:52:28 +0800] rev 8014
- Tuning G1 for MIPS.
- Thu, 30 Nov 2017 15:30:54 +0800
- by aoqi [Thu, 30 Nov 2017 15:30:54 +0800] rev 8013
- Added tag mips64el-jdk8u60-b32 for changeset 04ff2f6cd0eb
- Thu, 23 Nov 2017 14:26:38 +0800
- by aoqi [Thu, 23 Nov 2017 14:26:38 +0800] rev 8012
- fixed assembler, code cleanup and code style fix
- Mon, 13 Nov 2017 16:02:23 +0800
- by aoqi [Mon, 13 Nov 2017 16:02:23 +0800] rev 8011
- #6395 added help output of pns on Linux/mips
- Mon, 13 Nov 2017 15:58:57 +0800
- by aoqi [Mon, 13 Nov 2017 15:58:57 +0800] rev 8010
- #6394 match CompareAndSwapL
- Mon, 13 Nov 2017 15:49:42 +0800
- by aoqi [Mon, 13 Nov 2017 15:49:42 +0800] rev 8009
- #5963 wrong frame offset (SP) in StackOverflowError handler
Summary: push/pop before/after bang_stack_with_offset is removed. compiler/6865265/StackOverflowBug.java passed.
This patch also includes code cleanup and code style fix.
- Thu, 16 Nov 2017 17:27:00 +0800
- by fujie [Thu, 16 Nov 2017 17:27:00 +0800] rev 8008
- [G1] G1 runs OK for SPECjvm2008.
- Wed, 08 Nov 2017 10:07:02 +0800
- by fujie [Wed, 08 Nov 2017 10:07:02 +0800] rev 8007
- #6283 Fix the Eclipse startup failure (Could not reserve enough space for the card marking array).
http://10.2.5.21:8000/issues/6283
- Wed, 08 Nov 2017 09:28:23 +0800
- by fujie [Wed, 08 Nov 2017 09:28:23 +0800] rev 8006
- [GC] 17 out of 18 jtreg tests for g1 have passed (the same as x86 with jdk8u60-b32).
- Wed, 25 Oct 2017 17:43:22 +0800
- by fujie [Wed, 25 Oct 2017 17:43:22 +0800] rev 8005
- [G1] gen_write_ref_array_{pre/post}_barrier is OK.
- Wed, 25 Oct 2017 17:02:26 +0800
- by fujie [Wed, 25 Oct 2017 17:02:26 +0800] rev 8004
- [G1] compiler.compiler is OK.
---------------- 3A3000@1.4GHz -----------------------
Benchmark: compiler.compiler
Run mode: timed run
Test type: multi
Threads: 4
Warmup: 120s
Iterations: 1
Run length: 240s
Warmup (120s) begins: Wed Oct 25 16:48:20 CST 2017
Warmup (120s) ends: Wed Oct 25 16:50:24 CST 2017
Warmup (120s) result: 45.64 ops/m
Iteration 1 (240s) begins: Wed Oct 25 16:50:24 CST 2017
Iteration 1 (240s) ends: Wed Oct 25 16:54:29 CST 2017
Iteration 1 (240s) result: 65.94 ops/m
Valid run!
Score on compiler.compiler: 65.94 ops/m
- Wed, 25 Oct 2017 11:25:31 +0800
- by fujie [Wed, 25 Oct 2017 11:25:31 +0800] rev 8003
- store_heap_oop --> do_oop_store
- Tue, 24 Oct 2017 15:06:31 +0800
- by fujie [Tue, 24 Oct 2017 15:06:31 +0800] rev 8002
- Refine the oop store.
- Tue, 24 Oct 2017 14:04:09 +0800
- by fujie [Tue, 24 Oct 2017 14:04:09 +0800] rev 8001
- [Assembler] Complex address modes support for Assembler::lea(Register rt, Address src), Assembler::sd(Register rt, Address dst) and Assembler::sw(Register rt, Address dst)
- Mon, 23 Oct 2017 17:07:19 +0800
- by fujie [Mon, 23 Oct 2017 17:07:19 +0800] rev 8000
- [G1] Initial porting of MacroAssembler::g1_write_barrier_{pre/post}
- Fri, 03 Nov 2017 15:51:07 +0800
- by wangxue [Fri, 03 Nov 2017 15:51:07 +0800] rev 7999
- #6244 fixed the block of PopAndStepTest.java
Reviewed-by: aoqi
- Thu, 19 Oct 2017 09:49:23 +0800
- by wangxue [Thu, 19 Oct 2017 09:49:23 +0800] rev 7998
- #6173 Fixed the subtraction in TemplateTable::ineg().
Reviewed-by: aoqi
Summary: The result of using subu32 and using dsubu in TemplateTable::ineg() to calculate 0 - 0x80000000 is different.
- Mon, 06 Nov 2017 16:51:47 +0800
- by aoqi [Mon, 06 Nov 2017 16:51:47 +0800] rev 7997
- [Code Reorganization] remove trailing whitespace to pass jcheck test
