Wed, 15 Feb 2012 21:37:49 -0800
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
Summary: For C2 moved saving EBP after ESP adjustment. For C1 generated 5 byte nop instruction first if needed.
Reviewed-by: never, twisti, azeemj
1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "assembler_x86.inline.hpp"
27 #include "gc_interface/collectedHeap.inline.hpp"
28 #include "interpreter/interpreter.hpp"
29 #include "memory/cardTableModRefBS.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/methodHandles.hpp"
32 #include "runtime/biasedLocking.hpp"
33 #include "runtime/interfaceSupport.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #ifndef SERIALGC
39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
41 #include "gc_implementation/g1/heapRegion.hpp"
42 #endif
44 // Implementation of AddressLiteral
46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
47 _is_lval = false;
48 _target = target;
49 switch (rtype) {
50 case relocInfo::oop_type:
51 // Oops are a special case. Normally they would be their own section
52 // but in cases like icBuffer they are literals in the code stream that
53 // we don't have a section for. We use none so that we get a literal address
54 // which is always patchable.
55 break;
56 case relocInfo::external_word_type:
57 _rspec = external_word_Relocation::spec(target);
58 break;
59 case relocInfo::internal_word_type:
60 _rspec = internal_word_Relocation::spec(target);
61 break;
62 case relocInfo::opt_virtual_call_type:
63 _rspec = opt_virtual_call_Relocation::spec();
64 break;
65 case relocInfo::static_call_type:
66 _rspec = static_call_Relocation::spec();
67 break;
68 case relocInfo::runtime_call_type:
69 _rspec = runtime_call_Relocation::spec();
70 break;
71 case relocInfo::poll_type:
72 case relocInfo::poll_return_type:
73 _rspec = Relocation::spec_simple(rtype);
74 break;
75 case relocInfo::none:
76 break;
77 default:
78 ShouldNotReachHere();
79 break;
80 }
81 }
83 // Implementation of Address
85 #ifdef _LP64
87 Address Address::make_array(ArrayAddress adr) {
88 // Not implementable on 64bit machines
89 // Should have been handled higher up the call chain.
90 ShouldNotReachHere();
91 return Address();
92 }
94 // exceedingly dangerous constructor
95 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
96 _base = noreg;
97 _index = noreg;
98 _scale = no_scale;
99 _disp = disp;
100 switch (rtype) {
101 case relocInfo::external_word_type:
102 _rspec = external_word_Relocation::spec(loc);
103 break;
104 case relocInfo::internal_word_type:
105 _rspec = internal_word_Relocation::spec(loc);
106 break;
107 case relocInfo::runtime_call_type:
108 // HMM
109 _rspec = runtime_call_Relocation::spec();
110 break;
111 case relocInfo::poll_type:
112 case relocInfo::poll_return_type:
113 _rspec = Relocation::spec_simple(rtype);
114 break;
115 case relocInfo::none:
116 break;
117 default:
118 ShouldNotReachHere();
119 }
120 }
121 #else // LP64
123 Address Address::make_array(ArrayAddress adr) {
124 AddressLiteral base = adr.base();
125 Address index = adr.index();
126 assert(index._disp == 0, "must not have disp"); // maybe it can?
127 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
128 array._rspec = base._rspec;
129 return array;
130 }
132 // exceedingly dangerous constructor
133 Address::Address(address loc, RelocationHolder spec) {
134 _base = noreg;
135 _index = noreg;
136 _scale = no_scale;
137 _disp = (intptr_t) loc;
138 _rspec = spec;
139 }
141 #endif // _LP64
145 // Convert the raw encoding form into the form expected by the constructor for
146 // Address. An index of 4 (rsp) corresponds to having no index, so convert
147 // that to noreg for the Address constructor.
148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
149 RelocationHolder rspec;
150 if (disp_is_oop) {
151 rspec = Relocation::spec_simple(relocInfo::oop_type);
152 }
153 bool valid_index = index != rsp->encoding();
154 if (valid_index) {
155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
156 madr._rspec = rspec;
157 return madr;
158 } else {
159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
160 madr._rspec = rspec;
161 return madr;
162 }
163 }
165 // Implementation of Assembler
167 int AbstractAssembler::code_fill_byte() {
168 return (u_char)'\xF4'; // hlt
169 }
171 // make this go away someday
172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
173 if (rtype == relocInfo::none)
174 emit_long(data);
175 else emit_data(data, Relocation::spec_simple(rtype), format);
176 }
178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
179 assert(imm_operand == 0, "default format must be immediate in this file");
180 assert(inst_mark() != NULL, "must be inside InstructionMark");
181 if (rspec.type() != relocInfo::none) {
182 #ifdef ASSERT
183 check_relocation(rspec, format);
184 #endif
185 // Do not use AbstractAssembler::relocate, which is not intended for
186 // embedded words. Instead, relocate to the enclosing instruction.
188 // hack. call32 is too wide for mask so use disp32
189 if (format == call32_operand)
190 code_section()->relocate(inst_mark(), rspec, disp32_operand);
191 else
192 code_section()->relocate(inst_mark(), rspec, format);
193 }
194 emit_long(data);
195 }
197 static int encode(Register r) {
198 int enc = r->encoding();
199 if (enc >= 8) {
200 enc -= 8;
201 }
202 return enc;
203 }
205 static int encode(XMMRegister r) {
206 int enc = r->encoding();
207 if (enc >= 8) {
208 enc -= 8;
209 }
210 return enc;
211 }
213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
214 assert(dst->has_byte_register(), "must have byte register");
215 assert(isByte(op1) && isByte(op2), "wrong opcode");
216 assert(isByte(imm8), "not a byte");
217 assert((op1 & 0x01) == 0, "should be 8bit operation");
218 emit_byte(op1);
219 emit_byte(op2 | encode(dst));
220 emit_byte(imm8);
221 }
224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
225 assert(isByte(op1) && isByte(op2), "wrong opcode");
226 assert((op1 & 0x01) == 1, "should be 32bit operation");
227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
228 if (is8bit(imm32)) {
229 emit_byte(op1 | 0x02); // set sign bit
230 emit_byte(op2 | encode(dst));
231 emit_byte(imm32 & 0xFF);
232 } else {
233 emit_byte(op1);
234 emit_byte(op2 | encode(dst));
235 emit_long(imm32);
236 }
237 }
239 // Force generation of a 4 byte immediate value even if it fits into 8bit
240 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
241 assert(isByte(op1) && isByte(op2), "wrong opcode");
242 assert((op1 & 0x01) == 1, "should be 32bit operation");
243 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
244 emit_byte(op1);
245 emit_byte(op2 | encode(dst));
246 emit_long(imm32);
247 }
249 // immediate-to-memory forms
250 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
251 assert((op1 & 0x01) == 1, "should be 32bit operation");
252 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
253 if (is8bit(imm32)) {
254 emit_byte(op1 | 0x02); // set sign bit
255 emit_operand(rm, adr, 1);
256 emit_byte(imm32 & 0xFF);
257 } else {
258 emit_byte(op1);
259 emit_operand(rm, adr, 4);
260 emit_long(imm32);
261 }
262 }
264 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
265 LP64_ONLY(ShouldNotReachHere());
266 assert(isByte(op1) && isByte(op2), "wrong opcode");
267 assert((op1 & 0x01) == 1, "should be 32bit operation");
268 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
269 InstructionMark im(this);
270 emit_byte(op1);
271 emit_byte(op2 | encode(dst));
272 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
273 }
276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
277 assert(isByte(op1) && isByte(op2), "wrong opcode");
278 emit_byte(op1);
279 emit_byte(op2 | encode(dst) << 3 | encode(src));
280 }
283 void Assembler::emit_operand(Register reg, Register base, Register index,
284 Address::ScaleFactor scale, int disp,
285 RelocationHolder const& rspec,
286 int rip_relative_correction) {
287 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
289 // Encode the registers as needed in the fields they are used in
291 int regenc = encode(reg) << 3;
292 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
293 int baseenc = base->is_valid() ? encode(base) : 0;
295 if (base->is_valid()) {
296 if (index->is_valid()) {
297 assert(scale != Address::no_scale, "inconsistent address");
298 // [base + index*scale + disp]
299 if (disp == 0 && rtype == relocInfo::none &&
300 base != rbp LP64_ONLY(&& base != r13)) {
301 // [base + index*scale]
302 // [00 reg 100][ss index base]
303 assert(index != rsp, "illegal addressing mode");
304 emit_byte(0x04 | regenc);
305 emit_byte(scale << 6 | indexenc | baseenc);
306 } else if (is8bit(disp) && rtype == relocInfo::none) {
307 // [base + index*scale + imm8]
308 // [01 reg 100][ss index base] imm8
309 assert(index != rsp, "illegal addressing mode");
310 emit_byte(0x44 | regenc);
311 emit_byte(scale << 6 | indexenc | baseenc);
312 emit_byte(disp & 0xFF);
313 } else {
314 // [base + index*scale + disp32]
315 // [10 reg 100][ss index base] disp32
316 assert(index != rsp, "illegal addressing mode");
317 emit_byte(0x84 | regenc);
318 emit_byte(scale << 6 | indexenc | baseenc);
319 emit_data(disp, rspec, disp32_operand);
320 }
321 } else if (base == rsp LP64_ONLY(|| base == r12)) {
322 // [rsp + disp]
323 if (disp == 0 && rtype == relocInfo::none) {
324 // [rsp]
325 // [00 reg 100][00 100 100]
326 emit_byte(0x04 | regenc);
327 emit_byte(0x24);
328 } else if (is8bit(disp) && rtype == relocInfo::none) {
329 // [rsp + imm8]
330 // [01 reg 100][00 100 100] disp8
331 emit_byte(0x44 | regenc);
332 emit_byte(0x24);
333 emit_byte(disp & 0xFF);
334 } else {
335 // [rsp + imm32]
336 // [10 reg 100][00 100 100] disp32
337 emit_byte(0x84 | regenc);
338 emit_byte(0x24);
339 emit_data(disp, rspec, disp32_operand);
340 }
341 } else {
342 // [base + disp]
343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
344 if (disp == 0 && rtype == relocInfo::none &&
345 base != rbp LP64_ONLY(&& base != r13)) {
346 // [base]
347 // [00 reg base]
348 emit_byte(0x00 | regenc | baseenc);
349 } else if (is8bit(disp) && rtype == relocInfo::none) {
350 // [base + disp8]
351 // [01 reg base] disp8
352 emit_byte(0x40 | regenc | baseenc);
353 emit_byte(disp & 0xFF);
354 } else {
355 // [base + disp32]
356 // [10 reg base] disp32
357 emit_byte(0x80 | regenc | baseenc);
358 emit_data(disp, rspec, disp32_operand);
359 }
360 }
361 } else {
362 if (index->is_valid()) {
363 assert(scale != Address::no_scale, "inconsistent address");
364 // [index*scale + disp]
365 // [00 reg 100][ss index 101] disp32
366 assert(index != rsp, "illegal addressing mode");
367 emit_byte(0x04 | regenc);
368 emit_byte(scale << 6 | indexenc | 0x05);
369 emit_data(disp, rspec, disp32_operand);
370 } else if (rtype != relocInfo::none ) {
371 // [disp] (64bit) RIP-RELATIVE (32bit) abs
372 // [00 000 101] disp32
374 emit_byte(0x05 | regenc);
375 // Note that the RIP-rel. correction applies to the generated
376 // disp field, but _not_ to the target address in the rspec.
378 // disp was created by converting the target address minus the pc
379 // at the start of the instruction. That needs more correction here.
380 // intptr_t disp = target - next_ip;
381 assert(inst_mark() != NULL, "must be inside InstructionMark");
382 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
383 int64_t adjusted = disp;
384 // Do rip-rel adjustment for 64bit
385 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
386 assert(is_simm32(adjusted),
387 "must be 32bit offset (RIP relative address)");
388 emit_data((int32_t) adjusted, rspec, disp32_operand);
390 } else {
391 // 32bit never did this, did everything as the rip-rel/disp code above
392 // [disp] ABSOLUTE
393 // [00 reg 100][00 100 101] disp32
394 emit_byte(0x04 | regenc);
395 emit_byte(0x25);
396 emit_data(disp, rspec, disp32_operand);
397 }
398 }
399 }
401 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
402 Address::ScaleFactor scale, int disp,
403 RelocationHolder const& rspec) {
404 emit_operand((Register)reg, base, index, scale, disp, rspec);
405 }
407 // Secret local extension to Assembler::WhichOperand:
408 #define end_pc_operand (_WhichOperand_limit)
410 address Assembler::locate_operand(address inst, WhichOperand which) {
411 // Decode the given instruction, and return the address of
412 // an embedded 32-bit operand word.
414 // If "which" is disp32_operand, selects the displacement portion
415 // of an effective address specifier.
416 // If "which" is imm64_operand, selects the trailing immediate constant.
417 // If "which" is call32_operand, selects the displacement of a call or jump.
418 // Caller is responsible for ensuring that there is such an operand,
419 // and that it is 32/64 bits wide.
421 // If "which" is end_pc_operand, find the end of the instruction.
423 address ip = inst;
424 bool is_64bit = false;
426 debug_only(bool has_disp32 = false);
427 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
429 again_after_prefix:
430 switch (0xFF & *ip++) {
432 // These convenience macros generate groups of "case" labels for the switch.
433 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
434 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
435 case (x)+4: case (x)+5: case (x)+6: case (x)+7
436 #define REP16(x) REP8((x)+0): \
437 case REP8((x)+8)
439 case CS_segment:
440 case SS_segment:
441 case DS_segment:
442 case ES_segment:
443 case FS_segment:
444 case GS_segment:
445 // Seems dubious
446 LP64_ONLY(assert(false, "shouldn't have that prefix"));
447 assert(ip == inst+1, "only one prefix allowed");
448 goto again_after_prefix;
450 case 0x67:
451 case REX:
452 case REX_B:
453 case REX_X:
454 case REX_XB:
455 case REX_R:
456 case REX_RB:
457 case REX_RX:
458 case REX_RXB:
459 NOT_LP64(assert(false, "64bit prefixes"));
460 goto again_after_prefix;
462 case REX_W:
463 case REX_WB:
464 case REX_WX:
465 case REX_WXB:
466 case REX_WR:
467 case REX_WRB:
468 case REX_WRX:
469 case REX_WRXB:
470 NOT_LP64(assert(false, "64bit prefixes"));
471 is_64bit = true;
472 goto again_after_prefix;
474 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
475 case 0x88: // movb a, r
476 case 0x89: // movl a, r
477 case 0x8A: // movb r, a
478 case 0x8B: // movl r, a
479 case 0x8F: // popl a
480 debug_only(has_disp32 = true);
481 break;
483 case 0x68: // pushq #32
484 if (which == end_pc_operand) {
485 return ip + 4;
486 }
487 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
488 return ip; // not produced by emit_operand
490 case 0x66: // movw ... (size prefix)
491 again_after_size_prefix2:
492 switch (0xFF & *ip++) {
493 case REX:
494 case REX_B:
495 case REX_X:
496 case REX_XB:
497 case REX_R:
498 case REX_RB:
499 case REX_RX:
500 case REX_RXB:
501 case REX_W:
502 case REX_WB:
503 case REX_WX:
504 case REX_WXB:
505 case REX_WR:
506 case REX_WRB:
507 case REX_WRX:
508 case REX_WRXB:
509 NOT_LP64(assert(false, "64bit prefix found"));
510 goto again_after_size_prefix2;
511 case 0x8B: // movw r, a
512 case 0x89: // movw a, r
513 debug_only(has_disp32 = true);
514 break;
515 case 0xC7: // movw a, #16
516 debug_only(has_disp32 = true);
517 tail_size = 2; // the imm16
518 break;
519 case 0x0F: // several SSE/SSE2 variants
520 ip--; // reparse the 0x0F
521 goto again_after_prefix;
522 default:
523 ShouldNotReachHere();
524 }
525 break;
527 case REP8(0xB8): // movl/q r, #32/#64(oop?)
528 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
529 // these asserts are somewhat nonsensical
530 #ifndef _LP64
531 assert(which == imm_operand || which == disp32_operand, "");
532 #else
533 assert((which == call32_operand || which == imm_operand) && is_64bit ||
534 which == narrow_oop_operand && !is_64bit, "");
535 #endif // _LP64
536 return ip;
538 case 0x69: // imul r, a, #32
539 case 0xC7: // movl a, #32(oop?)
540 tail_size = 4;
541 debug_only(has_disp32 = true); // has both kinds of operands!
542 break;
544 case 0x0F: // movx..., etc.
545 switch (0xFF & *ip++) {
546 case 0x3A: // pcmpestri
547 tail_size = 1;
548 case 0x38: // ptest, pmovzxbw
549 ip++; // skip opcode
550 debug_only(has_disp32 = true); // has both kinds of operands!
551 break;
553 case 0x70: // pshufd r, r/a, #8
554 debug_only(has_disp32 = true); // has both kinds of operands!
555 case 0x73: // psrldq r, #8
556 tail_size = 1;
557 break;
559 case 0x12: // movlps
560 case 0x28: // movaps
561 case 0x2E: // ucomiss
562 case 0x2F: // comiss
563 case 0x54: // andps
564 case 0x55: // andnps
565 case 0x56: // orps
566 case 0x57: // xorps
567 case 0x6E: // movd
568 case 0x7E: // movd
569 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
570 debug_only(has_disp32 = true);
571 break;
573 case 0xAD: // shrd r, a, %cl
574 case 0xAF: // imul r, a
575 case 0xBE: // movsbl r, a (movsxb)
576 case 0xBF: // movswl r, a (movsxw)
577 case 0xB6: // movzbl r, a (movzxb)
578 case 0xB7: // movzwl r, a (movzxw)
579 case REP16(0x40): // cmovl cc, r, a
580 case 0xB0: // cmpxchgb
581 case 0xB1: // cmpxchg
582 case 0xC1: // xaddl
583 case 0xC7: // cmpxchg8
584 case REP16(0x90): // setcc a
585 debug_only(has_disp32 = true);
586 // fall out of the switch to decode the address
587 break;
589 case 0xC4: // pinsrw r, a, #8
590 debug_only(has_disp32 = true);
591 case 0xC5: // pextrw r, r, #8
592 tail_size = 1; // the imm8
593 break;
595 case 0xAC: // shrd r, a, #8
596 debug_only(has_disp32 = true);
597 tail_size = 1; // the imm8
598 break;
600 case REP16(0x80): // jcc rdisp32
601 if (which == end_pc_operand) return ip + 4;
602 assert(which == call32_operand, "jcc has no disp32 or imm");
603 return ip;
604 default:
605 ShouldNotReachHere();
606 }
607 break;
609 case 0x81: // addl a, #32; addl r, #32
610 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
611 // on 32bit in the case of cmpl, the imm might be an oop
612 tail_size = 4;
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 break;
616 case 0x83: // addl a, #8; addl r, #8
617 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
618 debug_only(has_disp32 = true); // has both kinds of operands!
619 tail_size = 1;
620 break;
622 case 0x9B:
623 switch (0xFF & *ip++) {
624 case 0xD9: // fnstcw a
625 debug_only(has_disp32 = true);
626 break;
627 default:
628 ShouldNotReachHere();
629 }
630 break;
632 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
633 case REP4(0x10): // adc...
634 case REP4(0x20): // and...
635 case REP4(0x30): // xor...
636 case REP4(0x08): // or...
637 case REP4(0x18): // sbb...
638 case REP4(0x28): // sub...
639 case 0xF7: // mull a
640 case 0x8D: // lea r, a
641 case 0x87: // xchg r, a
642 case REP4(0x38): // cmp...
643 case 0x85: // test r, a
644 debug_only(has_disp32 = true); // has both kinds of operands!
645 break;
647 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
648 case 0xC6: // movb a, #8
649 case 0x80: // cmpb a, #8
650 case 0x6B: // imul r, a, #8
651 debug_only(has_disp32 = true); // has both kinds of operands!
652 tail_size = 1; // the imm8
653 break;
655 case 0xC4: // VEX_3bytes
656 case 0xC5: // VEX_2bytes
657 assert((UseAVX > 0), "shouldn't have VEX prefix");
658 assert(ip == inst+1, "no prefixes allowed");
659 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
660 // but they have prefix 0x0F and processed when 0x0F processed above.
661 //
662 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
663 // instructions (these instructions are not supported in 64-bit mode).
664 // To distinguish them bits [7:6] are set in the VEX second byte since
665 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
666 // those VEX bits REX and vvvv bits are inverted.
667 //
668 // Fortunately C2 doesn't generate these instructions so we don't need
669 // to check for them in product version.
671 // Check second byte
672 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
674 // First byte
675 if ((0xFF & *inst) == VEX_3bytes) {
676 ip++; // third byte
677 is_64bit = ((VEX_W & *ip) == VEX_W);
678 }
679 ip++; // opcode
680 // To find the end of instruction (which == end_pc_operand).
681 switch (0xFF & *ip) {
682 case 0x61: // pcmpestri r, r/a, #8
683 case 0x70: // pshufd r, r/a, #8
684 case 0x73: // psrldq r, #8
685 tail_size = 1; // the imm8
686 break;
687 default:
688 break;
689 }
690 ip++; // skip opcode
691 debug_only(has_disp32 = true); // has both kinds of operands!
692 break;
694 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
695 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
696 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
697 case 0xDD: // fld_d a; fst_d a; fstp_d a
698 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
699 case 0xDF: // fild_d a; fistp_d a
700 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
701 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
702 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
703 debug_only(has_disp32 = true);
704 break;
706 case 0xE8: // call rdisp32
707 case 0xE9: // jmp rdisp32
708 if (which == end_pc_operand) return ip + 4;
709 assert(which == call32_operand, "call has no disp32 or imm");
710 return ip;
712 case 0xF0: // Lock
713 assert(os::is_MP(), "only on MP");
714 goto again_after_prefix;
716 case 0xF3: // For SSE
717 case 0xF2: // For SSE2
718 switch (0xFF & *ip++) {
719 case REX:
720 case REX_B:
721 case REX_X:
722 case REX_XB:
723 case REX_R:
724 case REX_RB:
725 case REX_RX:
726 case REX_RXB:
727 case REX_W:
728 case REX_WB:
729 case REX_WX:
730 case REX_WXB:
731 case REX_WR:
732 case REX_WRB:
733 case REX_WRX:
734 case REX_WRXB:
735 NOT_LP64(assert(false, "found 64bit prefix"));
736 ip++;
737 default:
738 ip++;
739 }
740 debug_only(has_disp32 = true); // has both kinds of operands!
741 break;
743 default:
744 ShouldNotReachHere();
746 #undef REP8
747 #undef REP16
748 }
750 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
751 #ifdef _LP64
752 assert(which != imm_operand, "instruction is not a movq reg, imm64");
753 #else
754 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
755 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
756 #endif // LP64
757 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
759 // parse the output of emit_operand
760 int op2 = 0xFF & *ip++;
761 int base = op2 & 0x07;
762 int op3 = -1;
763 const int b100 = 4;
764 const int b101 = 5;
765 if (base == b100 && (op2 >> 6) != 3) {
766 op3 = 0xFF & *ip++;
767 base = op3 & 0x07; // refetch the base
768 }
769 // now ip points at the disp (if any)
771 switch (op2 >> 6) {
772 case 0:
773 // [00 reg 100][ss index base]
774 // [00 reg 100][00 100 esp]
775 // [00 reg base]
776 // [00 reg 100][ss index 101][disp32]
777 // [00 reg 101] [disp32]
779 if (base == b101) {
780 if (which == disp32_operand)
781 return ip; // caller wants the disp32
782 ip += 4; // skip the disp32
783 }
784 break;
786 case 1:
787 // [01 reg 100][ss index base][disp8]
788 // [01 reg 100][00 100 esp][disp8]
789 // [01 reg base] [disp8]
790 ip += 1; // skip the disp8
791 break;
793 case 2:
794 // [10 reg 100][ss index base][disp32]
795 // [10 reg 100][00 100 esp][disp32]
796 // [10 reg base] [disp32]
797 if (which == disp32_operand)
798 return ip; // caller wants the disp32
799 ip += 4; // skip the disp32
800 break;
802 case 3:
803 // [11 reg base] (not a memory addressing mode)
804 break;
805 }
807 if (which == end_pc_operand) {
808 return ip + tail_size;
809 }
811 #ifdef _LP64
812 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
813 #else
814 assert(which == imm_operand, "instruction has only an imm field");
815 #endif // LP64
816 return ip;
817 }
819 address Assembler::locate_next_instruction(address inst) {
820 // Secretly share code with locate_operand:
821 return locate_operand(inst, end_pc_operand);
822 }
825 #ifdef ASSERT
826 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
827 address inst = inst_mark();
828 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
829 address opnd;
831 Relocation* r = rspec.reloc();
832 if (r->type() == relocInfo::none) {
833 return;
834 } else if (r->is_call() || format == call32_operand) {
835 // assert(format == imm32_operand, "cannot specify a nonzero format");
836 opnd = locate_operand(inst, call32_operand);
837 } else if (r->is_data()) {
838 assert(format == imm_operand || format == disp32_operand
839 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
840 opnd = locate_operand(inst, (WhichOperand)format);
841 } else {
842 assert(format == imm_operand, "cannot specify a format");
843 return;
844 }
845 assert(opnd == pc(), "must put operand where relocs can find it");
846 }
847 #endif // ASSERT
849 void Assembler::emit_operand32(Register reg, Address adr) {
850 assert(reg->encoding() < 8, "no extended registers");
851 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
852 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
853 adr._rspec);
854 }
856 void Assembler::emit_operand(Register reg, Address adr,
857 int rip_relative_correction) {
858 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
859 adr._rspec,
860 rip_relative_correction);
861 }
863 void Assembler::emit_operand(XMMRegister reg, Address adr) {
864 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
865 adr._rspec);
866 }
868 // MMX operations
869 void Assembler::emit_operand(MMXRegister reg, Address adr) {
870 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
871 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
872 }
874 // work around gcc (3.2.1-7a) bug
875 void Assembler::emit_operand(Address adr, MMXRegister reg) {
876 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
877 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
878 }
881 void Assembler::emit_farith(int b1, int b2, int i) {
882 assert(isByte(b1) && isByte(b2), "wrong opcode");
883 assert(0 <= i && i < 8, "illegal stack offset");
884 emit_byte(b1);
885 emit_byte(b2 + i);
886 }
889 // Now the Assembler instructions (identical for 32/64 bits)
891 void Assembler::adcl(Address dst, int32_t imm32) {
892 InstructionMark im(this);
893 prefix(dst);
894 emit_arith_operand(0x81, rdx, dst, imm32);
895 }
897 void Assembler::adcl(Address dst, Register src) {
898 InstructionMark im(this);
899 prefix(dst, src);
900 emit_byte(0x11);
901 emit_operand(src, dst);
902 }
904 void Assembler::adcl(Register dst, int32_t imm32) {
905 prefix(dst);
906 emit_arith(0x81, 0xD0, dst, imm32);
907 }
909 void Assembler::adcl(Register dst, Address src) {
910 InstructionMark im(this);
911 prefix(src, dst);
912 emit_byte(0x13);
913 emit_operand(dst, src);
914 }
916 void Assembler::adcl(Register dst, Register src) {
917 (void) prefix_and_encode(dst->encoding(), src->encoding());
918 emit_arith(0x13, 0xC0, dst, src);
919 }
921 void Assembler::addl(Address dst, int32_t imm32) {
922 InstructionMark im(this);
923 prefix(dst);
924 emit_arith_operand(0x81, rax, dst, imm32);
925 }
927 void Assembler::addl(Address dst, Register src) {
928 InstructionMark im(this);
929 prefix(dst, src);
930 emit_byte(0x01);
931 emit_operand(src, dst);
932 }
934 void Assembler::addl(Register dst, int32_t imm32) {
935 prefix(dst);
936 emit_arith(0x81, 0xC0, dst, imm32);
937 }
939 void Assembler::addl(Register dst, Address src) {
940 InstructionMark im(this);
941 prefix(src, dst);
942 emit_byte(0x03);
943 emit_operand(dst, src);
944 }
946 void Assembler::addl(Register dst, Register src) {
947 (void) prefix_and_encode(dst->encoding(), src->encoding());
948 emit_arith(0x03, 0xC0, dst, src);
949 }
951 void Assembler::addr_nop_4() {
952 assert(UseAddressNop, "no CPU support");
953 // 4 bytes: NOP DWORD PTR [EAX+0]
954 emit_byte(0x0F);
955 emit_byte(0x1F);
956 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
957 emit_byte(0); // 8-bits offset (1 byte)
958 }
960 void Assembler::addr_nop_5() {
961 assert(UseAddressNop, "no CPU support");
962 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
963 emit_byte(0x0F);
964 emit_byte(0x1F);
965 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
966 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
967 emit_byte(0); // 8-bits offset (1 byte)
968 }
970 void Assembler::addr_nop_7() {
971 assert(UseAddressNop, "no CPU support");
972 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
973 emit_byte(0x0F);
974 emit_byte(0x1F);
975 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
976 emit_long(0); // 32-bits offset (4 bytes)
977 }
979 void Assembler::addr_nop_8() {
980 assert(UseAddressNop, "no CPU support");
981 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
982 emit_byte(0x0F);
983 emit_byte(0x1F);
984 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
985 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
986 emit_long(0); // 32-bits offset (4 bytes)
987 }
989 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
991 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
992 emit_byte(0x58);
993 emit_byte(0xC0 | encode);
994 }
996 void Assembler::addsd(XMMRegister dst, Address src) {
997 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
998 InstructionMark im(this);
999 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1000 emit_byte(0x58);
1001 emit_operand(dst, src);
1002 }
1004 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1005 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1006 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1007 emit_byte(0x58);
1008 emit_byte(0xC0 | encode);
1009 }
1011 void Assembler::addss(XMMRegister dst, Address src) {
1012 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1013 InstructionMark im(this);
1014 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1015 emit_byte(0x58);
1016 emit_operand(dst, src);
1017 }
1019 void Assembler::andl(Address dst, int32_t imm32) {
1020 InstructionMark im(this);
1021 prefix(dst);
1022 emit_byte(0x81);
1023 emit_operand(rsp, dst, 4);
1024 emit_long(imm32);
1025 }
1027 void Assembler::andl(Register dst, int32_t imm32) {
1028 prefix(dst);
1029 emit_arith(0x81, 0xE0, dst, imm32);
1030 }
1032 void Assembler::andl(Register dst, Address src) {
1033 InstructionMark im(this);
1034 prefix(src, dst);
1035 emit_byte(0x23);
1036 emit_operand(dst, src);
1037 }
1039 void Assembler::andl(Register dst, Register src) {
1040 (void) prefix_and_encode(dst->encoding(), src->encoding());
1041 emit_arith(0x23, 0xC0, dst, src);
1042 }
1044 void Assembler::andpd(XMMRegister dst, Address src) {
1045 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1046 InstructionMark im(this);
1047 simd_prefix(dst, dst, src, VEX_SIMD_66);
1048 emit_byte(0x54);
1049 emit_operand(dst, src);
1050 }
1052 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
1053 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1054 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1055 emit_byte(0x54);
1056 emit_byte(0xC0 | encode);
1057 }
1059 void Assembler::andps(XMMRegister dst, Address src) {
1060 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1061 InstructionMark im(this);
1062 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
1063 emit_byte(0x54);
1064 emit_operand(dst, src);
1065 }
1067 void Assembler::andps(XMMRegister dst, XMMRegister src) {
1068 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1069 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
1070 emit_byte(0x54);
1071 emit_byte(0xC0 | encode);
1072 }
1074 void Assembler::bsfl(Register dst, Register src) {
1075 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1076 emit_byte(0x0F);
1077 emit_byte(0xBC);
1078 emit_byte(0xC0 | encode);
1079 }
1081 void Assembler::bsrl(Register dst, Register src) {
1082 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1083 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1084 emit_byte(0x0F);
1085 emit_byte(0xBD);
1086 emit_byte(0xC0 | encode);
1087 }
1089 void Assembler::bswapl(Register reg) { // bswap
1090 int encode = prefix_and_encode(reg->encoding());
1091 emit_byte(0x0F);
1092 emit_byte(0xC8 | encode);
1093 }
1095 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1096 // suspect disp32 is always good
1097 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1099 if (L.is_bound()) {
1100 const int long_size = 5;
1101 int offs = (int)( target(L) - pc() );
1102 assert(offs <= 0, "assembler error");
1103 InstructionMark im(this);
1104 // 1110 1000 #32-bit disp
1105 emit_byte(0xE8);
1106 emit_data(offs - long_size, rtype, operand);
1107 } else {
1108 InstructionMark im(this);
1109 // 1110 1000 #32-bit disp
1110 L.add_patch_at(code(), locator());
1112 emit_byte(0xE8);
1113 emit_data(int(0), rtype, operand);
1114 }
1115 }
1117 void Assembler::call(Register dst) {
1118 int encode = prefix_and_encode(dst->encoding());
1119 emit_byte(0xFF);
1120 emit_byte(0xD0 | encode);
1121 }
1124 void Assembler::call(Address adr) {
1125 InstructionMark im(this);
1126 prefix(adr);
1127 emit_byte(0xFF);
1128 emit_operand(rdx, adr);
1129 }
1131 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1132 assert(entry != NULL, "call most probably wrong");
1133 InstructionMark im(this);
1134 emit_byte(0xE8);
1135 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
1136 assert(is_simm32(disp), "must be 32bit offset (call2)");
1137 // Technically, should use call32_operand, but this format is
1138 // implied by the fact that we're emitting a call instruction.
1140 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1141 emit_data((int) disp, rspec, operand);
1142 }
1144 void Assembler::cdql() {
1145 emit_byte(0x99);
1146 }
1148 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1149 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1150 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1151 emit_byte(0x0F);
1152 emit_byte(0x40 | cc);
1153 emit_byte(0xC0 | encode);
1154 }
1157 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1158 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1159 prefix(src, dst);
1160 emit_byte(0x0F);
1161 emit_byte(0x40 | cc);
1162 emit_operand(dst, src);
1163 }
1165 void Assembler::cmpb(Address dst, int imm8) {
1166 InstructionMark im(this);
1167 prefix(dst);
1168 emit_byte(0x80);
1169 emit_operand(rdi, dst, 1);
1170 emit_byte(imm8);
1171 }
1173 void Assembler::cmpl(Address dst, int32_t imm32) {
1174 InstructionMark im(this);
1175 prefix(dst);
1176 emit_byte(0x81);
1177 emit_operand(rdi, dst, 4);
1178 emit_long(imm32);
1179 }
1181 void Assembler::cmpl(Register dst, int32_t imm32) {
1182 prefix(dst);
1183 emit_arith(0x81, 0xF8, dst, imm32);
1184 }
1186 void Assembler::cmpl(Register dst, Register src) {
1187 (void) prefix_and_encode(dst->encoding(), src->encoding());
1188 emit_arith(0x3B, 0xC0, dst, src);
1189 }
1192 void Assembler::cmpl(Register dst, Address src) {
1193 InstructionMark im(this);
1194 prefix(src, dst);
1195 emit_byte(0x3B);
1196 emit_operand(dst, src);
1197 }
1199 void Assembler::cmpw(Address dst, int imm16) {
1200 InstructionMark im(this);
1201 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1202 emit_byte(0x66);
1203 emit_byte(0x81);
1204 emit_operand(rdi, dst, 2);
1205 emit_word(imm16);
1206 }
1208 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1209 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1210 // The ZF is set if the compared values were equal, and cleared otherwise.
1211 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1212 if (Atomics & 2) {
1213 // caveat: no instructionmark, so this isn't relocatable.
1214 // Emit a synthetic, non-atomic, CAS equivalent.
1215 // Beware. The synthetic form sets all ICCs, not just ZF.
1216 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1217 cmpl(rax, adr);
1218 movl(rax, adr);
1219 if (reg != rax) {
1220 Label L ;
1221 jcc(Assembler::notEqual, L);
1222 movl(adr, reg);
1223 bind(L);
1224 }
1225 } else {
1226 InstructionMark im(this);
1227 prefix(adr, reg);
1228 emit_byte(0x0F);
1229 emit_byte(0xB1);
1230 emit_operand(reg, adr);
1231 }
1232 }
1234 void Assembler::comisd(XMMRegister dst, Address src) {
1235 // NOTE: dbx seems to decode this as comiss even though the
1236 // 0x66 is there. Strangly ucomisd comes out correct
1237 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1238 InstructionMark im(this);
1239 simd_prefix(dst, src, VEX_SIMD_66);
1240 emit_byte(0x2F);
1241 emit_operand(dst, src);
1242 }
1244 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1245 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1246 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1247 emit_byte(0x2F);
1248 emit_byte(0xC0 | encode);
1249 }
1251 void Assembler::comiss(XMMRegister dst, Address src) {
1252 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1253 InstructionMark im(this);
1254 simd_prefix(dst, src, VEX_SIMD_NONE);
1255 emit_byte(0x2F);
1256 emit_operand(dst, src);
1257 }
1259 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1260 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1262 emit_byte(0x2F);
1263 emit_byte(0xC0 | encode);
1264 }
1266 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1267 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1268 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1269 emit_byte(0xE6);
1270 emit_byte(0xC0 | encode);
1271 }
1273 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1274 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1275 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1276 emit_byte(0x5B);
1277 emit_byte(0xC0 | encode);
1278 }
1280 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1281 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1283 emit_byte(0x5A);
1284 emit_byte(0xC0 | encode);
1285 }
1287 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1288 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1289 InstructionMark im(this);
1290 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1291 emit_byte(0x5A);
1292 emit_operand(dst, src);
1293 }
1295 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1298 emit_byte(0x2A);
1299 emit_byte(0xC0 | encode);
1300 }
1302 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1303 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1304 InstructionMark im(this);
1305 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1306 emit_byte(0x2A);
1307 emit_operand(dst, src);
1308 }
1310 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1311 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1312 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1313 emit_byte(0x2A);
1314 emit_byte(0xC0 | encode);
1315 }
1317 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1318 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1319 InstructionMark im(this);
1320 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1321 emit_byte(0x2A);
1322 emit_operand(dst, src);
1323 }
1325 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1326 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1327 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1328 emit_byte(0x5A);
1329 emit_byte(0xC0 | encode);
1330 }
1332 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1334 InstructionMark im(this);
1335 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1336 emit_byte(0x5A);
1337 emit_operand(dst, src);
1338 }
1341 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1342 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1343 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1344 emit_byte(0x2C);
1345 emit_byte(0xC0 | encode);
1346 }
1348 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1349 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1350 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1351 emit_byte(0x2C);
1352 emit_byte(0xC0 | encode);
1353 }
1355 void Assembler::decl(Address dst) {
1356 // Don't use it directly. Use MacroAssembler::decrement() instead.
1357 InstructionMark im(this);
1358 prefix(dst);
1359 emit_byte(0xFF);
1360 emit_operand(rcx, dst);
1361 }
1363 void Assembler::divsd(XMMRegister dst, Address src) {
1364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1365 InstructionMark im(this);
1366 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1367 emit_byte(0x5E);
1368 emit_operand(dst, src);
1369 }
1371 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1373 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1374 emit_byte(0x5E);
1375 emit_byte(0xC0 | encode);
1376 }
1378 void Assembler::divss(XMMRegister dst, Address src) {
1379 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1380 InstructionMark im(this);
1381 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1382 emit_byte(0x5E);
1383 emit_operand(dst, src);
1384 }
1386 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1387 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1388 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1389 emit_byte(0x5E);
1390 emit_byte(0xC0 | encode);
1391 }
1393 void Assembler::emms() {
1394 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1395 emit_byte(0x0F);
1396 emit_byte(0x77);
1397 }
1399 void Assembler::hlt() {
1400 emit_byte(0xF4);
1401 }
1403 void Assembler::idivl(Register src) {
1404 int encode = prefix_and_encode(src->encoding());
1405 emit_byte(0xF7);
1406 emit_byte(0xF8 | encode);
1407 }
1409 void Assembler::divl(Register src) { // Unsigned
1410 int encode = prefix_and_encode(src->encoding());
1411 emit_byte(0xF7);
1412 emit_byte(0xF0 | encode);
1413 }
1415 void Assembler::imull(Register dst, Register src) {
1416 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1417 emit_byte(0x0F);
1418 emit_byte(0xAF);
1419 emit_byte(0xC0 | encode);
1420 }
1423 void Assembler::imull(Register dst, Register src, int value) {
1424 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1425 if (is8bit(value)) {
1426 emit_byte(0x6B);
1427 emit_byte(0xC0 | encode);
1428 emit_byte(value & 0xFF);
1429 } else {
1430 emit_byte(0x69);
1431 emit_byte(0xC0 | encode);
1432 emit_long(value);
1433 }
1434 }
1436 void Assembler::incl(Address dst) {
1437 // Don't use it directly. Use MacroAssembler::increment() instead.
1438 InstructionMark im(this);
1439 prefix(dst);
1440 emit_byte(0xFF);
1441 emit_operand(rax, dst);
1442 }
1444 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1445 InstructionMark im(this);
1446 assert((0 <= cc) && (cc < 16), "illegal cc");
1447 if (L.is_bound()) {
1448 address dst = target(L);
1449 assert(dst != NULL, "jcc most probably wrong");
1451 const int short_size = 2;
1452 const int long_size = 6;
1453 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
1454 if (maybe_short && is8bit(offs - short_size)) {
1455 // 0111 tttn #8-bit disp
1456 emit_byte(0x70 | cc);
1457 emit_byte((offs - short_size) & 0xFF);
1458 } else {
1459 // 0000 1111 1000 tttn #32-bit disp
1460 assert(is_simm32(offs - long_size),
1461 "must be 32bit offset (call4)");
1462 emit_byte(0x0F);
1463 emit_byte(0x80 | cc);
1464 emit_long(offs - long_size);
1465 }
1466 } else {
1467 // Note: could eliminate cond. jumps to this jump if condition
1468 // is the same however, seems to be rather unlikely case.
1469 // Note: use jccb() if label to be bound is very close to get
1470 // an 8-bit displacement
1471 L.add_patch_at(code(), locator());
1472 emit_byte(0x0F);
1473 emit_byte(0x80 | cc);
1474 emit_long(0);
1475 }
1476 }
1478 void Assembler::jccb(Condition cc, Label& L) {
1479 if (L.is_bound()) {
1480 const int short_size = 2;
1481 address entry = target(L);
1482 #ifdef ASSERT
1483 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size);
1484 intptr_t delta = short_branch_delta();
1485 if (delta != 0) {
1486 dist += (dist < 0 ? (-delta) :delta);
1487 }
1488 assert(is8bit(dist), "Dispacement too large for a short jmp");
1489 #endif
1490 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1491 // 0111 tttn #8-bit disp
1492 emit_byte(0x70 | cc);
1493 emit_byte((offs - short_size) & 0xFF);
1494 } else {
1495 InstructionMark im(this);
1496 L.add_patch_at(code(), locator());
1497 emit_byte(0x70 | cc);
1498 emit_byte(0);
1499 }
1500 }
1502 void Assembler::jmp(Address adr) {
1503 InstructionMark im(this);
1504 prefix(adr);
1505 emit_byte(0xFF);
1506 emit_operand(rsp, adr);
1507 }
1509 void Assembler::jmp(Label& L, bool maybe_short) {
1510 if (L.is_bound()) {
1511 address entry = target(L);
1512 assert(entry != NULL, "jmp most probably wrong");
1513 InstructionMark im(this);
1514 const int short_size = 2;
1515 const int long_size = 5;
1516 intptr_t offs = entry - _code_pos;
1517 if (maybe_short && is8bit(offs - short_size)) {
1518 emit_byte(0xEB);
1519 emit_byte((offs - short_size) & 0xFF);
1520 } else {
1521 emit_byte(0xE9);
1522 emit_long(offs - long_size);
1523 }
1524 } else {
1525 // By default, forward jumps are always 32-bit displacements, since
1526 // we can't yet know where the label will be bound. If you're sure that
1527 // the forward jump will not run beyond 256 bytes, use jmpb to
1528 // force an 8-bit displacement.
1529 InstructionMark im(this);
1530 L.add_patch_at(code(), locator());
1531 emit_byte(0xE9);
1532 emit_long(0);
1533 }
1534 }
1536 void Assembler::jmp(Register entry) {
1537 int encode = prefix_and_encode(entry->encoding());
1538 emit_byte(0xFF);
1539 emit_byte(0xE0 | encode);
1540 }
1542 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1543 InstructionMark im(this);
1544 emit_byte(0xE9);
1545 assert(dest != NULL, "must have a target");
1546 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1547 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1548 emit_data(disp, rspec.reloc(), call32_operand);
1549 }
1551 void Assembler::jmpb(Label& L) {
1552 if (L.is_bound()) {
1553 const int short_size = 2;
1554 address entry = target(L);
1555 assert(entry != NULL, "jmp most probably wrong");
1556 #ifdef ASSERT
1557 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size);
1558 intptr_t delta = short_branch_delta();
1559 if (delta != 0) {
1560 dist += (dist < 0 ? (-delta) :delta);
1561 }
1562 assert(is8bit(dist), "Dispacement too large for a short jmp");
1563 #endif
1564 intptr_t offs = entry - _code_pos;
1565 emit_byte(0xEB);
1566 emit_byte((offs - short_size) & 0xFF);
1567 } else {
1568 InstructionMark im(this);
1569 L.add_patch_at(code(), locator());
1570 emit_byte(0xEB);
1571 emit_byte(0);
1572 }
1573 }
1575 void Assembler::ldmxcsr( Address src) {
1576 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1577 InstructionMark im(this);
1578 prefix(src);
1579 emit_byte(0x0F);
1580 emit_byte(0xAE);
1581 emit_operand(as_Register(2), src);
1582 }
1584 void Assembler::leal(Register dst, Address src) {
1585 InstructionMark im(this);
1586 #ifdef _LP64
1587 emit_byte(0x67); // addr32
1588 prefix(src, dst);
1589 #endif // LP64
1590 emit_byte(0x8D);
1591 emit_operand(dst, src);
1592 }
1594 void Assembler::lock() {
1595 if (Atomics & 1) {
1596 // Emit either nothing, a NOP, or a NOP: prefix
1597 emit_byte(0x90) ;
1598 } else {
1599 emit_byte(0xF0);
1600 }
1601 }
1603 void Assembler::lzcntl(Register dst, Register src) {
1604 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1605 emit_byte(0xF3);
1606 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1607 emit_byte(0x0F);
1608 emit_byte(0xBD);
1609 emit_byte(0xC0 | encode);
1610 }
1612 // Emit mfence instruction
1613 void Assembler::mfence() {
1614 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1615 emit_byte( 0x0F );
1616 emit_byte( 0xAE );
1617 emit_byte( 0xF0 );
1618 }
1620 void Assembler::mov(Register dst, Register src) {
1621 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1622 }
1624 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1626 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1627 emit_byte(0x28);
1628 emit_byte(0xC0 | encode);
1629 }
1631 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1632 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1633 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1634 emit_byte(0x28);
1635 emit_byte(0xC0 | encode);
1636 }
1638 void Assembler::movb(Register dst, Address src) {
1639 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1640 InstructionMark im(this);
1641 prefix(src, dst, true);
1642 emit_byte(0x8A);
1643 emit_operand(dst, src);
1644 }
1647 void Assembler::movb(Address dst, int imm8) {
1648 InstructionMark im(this);
1649 prefix(dst);
1650 emit_byte(0xC6);
1651 emit_operand(rax, dst, 1);
1652 emit_byte(imm8);
1653 }
1656 void Assembler::movb(Address dst, Register src) {
1657 assert(src->has_byte_register(), "must have byte register");
1658 InstructionMark im(this);
1659 prefix(dst, src, true);
1660 emit_byte(0x88);
1661 emit_operand(src, dst);
1662 }
1664 void Assembler::movdl(XMMRegister dst, Register src) {
1665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1666 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1667 emit_byte(0x6E);
1668 emit_byte(0xC0 | encode);
1669 }
1671 void Assembler::movdl(Register dst, XMMRegister src) {
1672 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1673 // swap src/dst to get correct prefix
1674 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1675 emit_byte(0x7E);
1676 emit_byte(0xC0 | encode);
1677 }
1679 void Assembler::movdl(XMMRegister dst, Address src) {
1680 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1681 InstructionMark im(this);
1682 simd_prefix(dst, src, VEX_SIMD_66);
1683 emit_byte(0x6E);
1684 emit_operand(dst, src);
1685 }
1687 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1688 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1689 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1690 emit_byte(0x6F);
1691 emit_byte(0xC0 | encode);
1692 }
1694 void Assembler::movdqu(XMMRegister dst, Address src) {
1695 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1696 InstructionMark im(this);
1697 simd_prefix(dst, src, VEX_SIMD_F3);
1698 emit_byte(0x6F);
1699 emit_operand(dst, src);
1700 }
1702 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1703 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1704 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1705 emit_byte(0x6F);
1706 emit_byte(0xC0 | encode);
1707 }
1709 void Assembler::movdqu(Address dst, XMMRegister src) {
1710 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1711 InstructionMark im(this);
1712 simd_prefix(dst, src, VEX_SIMD_F3);
1713 emit_byte(0x7F);
1714 emit_operand(src, dst);
1715 }
1717 // Uses zero extension on 64bit
1719 void Assembler::movl(Register dst, int32_t imm32) {
1720 int encode = prefix_and_encode(dst->encoding());
1721 emit_byte(0xB8 | encode);
1722 emit_long(imm32);
1723 }
1725 void Assembler::movl(Register dst, Register src) {
1726 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1727 emit_byte(0x8B);
1728 emit_byte(0xC0 | encode);
1729 }
1731 void Assembler::movl(Register dst, Address src) {
1732 InstructionMark im(this);
1733 prefix(src, dst);
1734 emit_byte(0x8B);
1735 emit_operand(dst, src);
1736 }
1738 void Assembler::movl(Address dst, int32_t imm32) {
1739 InstructionMark im(this);
1740 prefix(dst);
1741 emit_byte(0xC7);
1742 emit_operand(rax, dst, 4);
1743 emit_long(imm32);
1744 }
1746 void Assembler::movl(Address dst, Register src) {
1747 InstructionMark im(this);
1748 prefix(dst, src);
1749 emit_byte(0x89);
1750 emit_operand(src, dst);
1751 }
1753 // New cpus require to use movsd and movss to avoid partial register stall
1754 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1755 // The selection is done in MacroAssembler::movdbl() and movflt().
1756 void Assembler::movlpd(XMMRegister dst, Address src) {
1757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1758 InstructionMark im(this);
1759 simd_prefix(dst, dst, src, VEX_SIMD_66);
1760 emit_byte(0x12);
1761 emit_operand(dst, src);
1762 }
1764 void Assembler::movq( MMXRegister dst, Address src ) {
1765 assert( VM_Version::supports_mmx(), "" );
1766 emit_byte(0x0F);
1767 emit_byte(0x6F);
1768 emit_operand(dst, src);
1769 }
1771 void Assembler::movq( Address dst, MMXRegister src ) {
1772 assert( VM_Version::supports_mmx(), "" );
1773 emit_byte(0x0F);
1774 emit_byte(0x7F);
1775 // workaround gcc (3.2.1-7a) bug
1776 // In that version of gcc with only an emit_operand(MMX, Address)
1777 // gcc will tail jump and try and reverse the parameters completely
1778 // obliterating dst in the process. By having a version available
1779 // that doesn't need to swap the args at the tail jump the bug is
1780 // avoided.
1781 emit_operand(dst, src);
1782 }
1784 void Assembler::movq(XMMRegister dst, Address src) {
1785 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1786 InstructionMark im(this);
1787 simd_prefix(dst, src, VEX_SIMD_F3);
1788 emit_byte(0x7E);
1789 emit_operand(dst, src);
1790 }
1792 void Assembler::movq(Address dst, XMMRegister src) {
1793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1794 InstructionMark im(this);
1795 simd_prefix(dst, src, VEX_SIMD_66);
1796 emit_byte(0xD6);
1797 emit_operand(src, dst);
1798 }
1800 void Assembler::movsbl(Register dst, Address src) { // movsxb
1801 InstructionMark im(this);
1802 prefix(src, dst);
1803 emit_byte(0x0F);
1804 emit_byte(0xBE);
1805 emit_operand(dst, src);
1806 }
1808 void Assembler::movsbl(Register dst, Register src) { // movsxb
1809 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1810 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1811 emit_byte(0x0F);
1812 emit_byte(0xBE);
1813 emit_byte(0xC0 | encode);
1814 }
1816 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1818 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1819 emit_byte(0x10);
1820 emit_byte(0xC0 | encode);
1821 }
1823 void Assembler::movsd(XMMRegister dst, Address src) {
1824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1825 InstructionMark im(this);
1826 simd_prefix(dst, src, VEX_SIMD_F2);
1827 emit_byte(0x10);
1828 emit_operand(dst, src);
1829 }
1831 void Assembler::movsd(Address dst, XMMRegister src) {
1832 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1833 InstructionMark im(this);
1834 simd_prefix(dst, src, VEX_SIMD_F2);
1835 emit_byte(0x11);
1836 emit_operand(src, dst);
1837 }
1839 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1840 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1841 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1842 emit_byte(0x10);
1843 emit_byte(0xC0 | encode);
1844 }
1846 void Assembler::movss(XMMRegister dst, Address src) {
1847 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1848 InstructionMark im(this);
1849 simd_prefix(dst, src, VEX_SIMD_F3);
1850 emit_byte(0x10);
1851 emit_operand(dst, src);
1852 }
1854 void Assembler::movss(Address dst, XMMRegister src) {
1855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1856 InstructionMark im(this);
1857 simd_prefix(dst, src, VEX_SIMD_F3);
1858 emit_byte(0x11);
1859 emit_operand(src, dst);
1860 }
1862 void Assembler::movswl(Register dst, Address src) { // movsxw
1863 InstructionMark im(this);
1864 prefix(src, dst);
1865 emit_byte(0x0F);
1866 emit_byte(0xBF);
1867 emit_operand(dst, src);
1868 }
1870 void Assembler::movswl(Register dst, Register src) { // movsxw
1871 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1872 emit_byte(0x0F);
1873 emit_byte(0xBF);
1874 emit_byte(0xC0 | encode);
1875 }
1877 void Assembler::movw(Address dst, int imm16) {
1878 InstructionMark im(this);
1880 emit_byte(0x66); // switch to 16-bit mode
1881 prefix(dst);
1882 emit_byte(0xC7);
1883 emit_operand(rax, dst, 2);
1884 emit_word(imm16);
1885 }
1887 void Assembler::movw(Register dst, Address src) {
1888 InstructionMark im(this);
1889 emit_byte(0x66);
1890 prefix(src, dst);
1891 emit_byte(0x8B);
1892 emit_operand(dst, src);
1893 }
1895 void Assembler::movw(Address dst, Register src) {
1896 InstructionMark im(this);
1897 emit_byte(0x66);
1898 prefix(dst, src);
1899 emit_byte(0x89);
1900 emit_operand(src, dst);
1901 }
1903 void Assembler::movzbl(Register dst, Address src) { // movzxb
1904 InstructionMark im(this);
1905 prefix(src, dst);
1906 emit_byte(0x0F);
1907 emit_byte(0xB6);
1908 emit_operand(dst, src);
1909 }
1911 void Assembler::movzbl(Register dst, Register src) { // movzxb
1912 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1913 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1914 emit_byte(0x0F);
1915 emit_byte(0xB6);
1916 emit_byte(0xC0 | encode);
1917 }
1919 void Assembler::movzwl(Register dst, Address src) { // movzxw
1920 InstructionMark im(this);
1921 prefix(src, dst);
1922 emit_byte(0x0F);
1923 emit_byte(0xB7);
1924 emit_operand(dst, src);
1925 }
1927 void Assembler::movzwl(Register dst, Register src) { // movzxw
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1929 emit_byte(0x0F);
1930 emit_byte(0xB7);
1931 emit_byte(0xC0 | encode);
1932 }
1934 void Assembler::mull(Address src) {
1935 InstructionMark im(this);
1936 prefix(src);
1937 emit_byte(0xF7);
1938 emit_operand(rsp, src);
1939 }
1941 void Assembler::mull(Register src) {
1942 int encode = prefix_and_encode(src->encoding());
1943 emit_byte(0xF7);
1944 emit_byte(0xE0 | encode);
1945 }
1947 void Assembler::mulsd(XMMRegister dst, Address src) {
1948 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1949 InstructionMark im(this);
1950 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1951 emit_byte(0x59);
1952 emit_operand(dst, src);
1953 }
1955 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1956 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1957 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1958 emit_byte(0x59);
1959 emit_byte(0xC0 | encode);
1960 }
1962 void Assembler::mulss(XMMRegister dst, Address src) {
1963 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1964 InstructionMark im(this);
1965 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1966 emit_byte(0x59);
1967 emit_operand(dst, src);
1968 }
1970 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1971 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1972 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1973 emit_byte(0x59);
1974 emit_byte(0xC0 | encode);
1975 }
1977 void Assembler::negl(Register dst) {
1978 int encode = prefix_and_encode(dst->encoding());
1979 emit_byte(0xF7);
1980 emit_byte(0xD8 | encode);
1981 }
1983 void Assembler::nop(int i) {
1984 #ifdef ASSERT
1985 assert(i > 0, " ");
1986 // The fancy nops aren't currently recognized by debuggers making it a
1987 // pain to disassemble code while debugging. If asserts are on clearly
1988 // speed is not an issue so simply use the single byte traditional nop
1989 // to do alignment.
1991 for (; i > 0 ; i--) emit_byte(0x90);
1992 return;
1994 #endif // ASSERT
1996 if (UseAddressNop && VM_Version::is_intel()) {
1997 //
1998 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1999 // 1: 0x90
2000 // 2: 0x66 0x90
2001 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2002 // 4: 0x0F 0x1F 0x40 0x00
2003 // 5: 0x0F 0x1F 0x44 0x00 0x00
2004 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2005 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2006 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2007 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2008 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2009 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2011 // The rest coding is Intel specific - don't use consecutive address nops
2013 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2014 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2015 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2016 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2018 while(i >= 15) {
2019 // For Intel don't generate consecutive addess nops (mix with regular nops)
2020 i -= 15;
2021 emit_byte(0x66); // size prefix
2022 emit_byte(0x66); // size prefix
2023 emit_byte(0x66); // size prefix
2024 addr_nop_8();
2025 emit_byte(0x66); // size prefix
2026 emit_byte(0x66); // size prefix
2027 emit_byte(0x66); // size prefix
2028 emit_byte(0x90); // nop
2029 }
2030 switch (i) {
2031 case 14:
2032 emit_byte(0x66); // size prefix
2033 case 13:
2034 emit_byte(0x66); // size prefix
2035 case 12:
2036 addr_nop_8();
2037 emit_byte(0x66); // size prefix
2038 emit_byte(0x66); // size prefix
2039 emit_byte(0x66); // size prefix
2040 emit_byte(0x90); // nop
2041 break;
2042 case 11:
2043 emit_byte(0x66); // size prefix
2044 case 10:
2045 emit_byte(0x66); // size prefix
2046 case 9:
2047 emit_byte(0x66); // size prefix
2048 case 8:
2049 addr_nop_8();
2050 break;
2051 case 7:
2052 addr_nop_7();
2053 break;
2054 case 6:
2055 emit_byte(0x66); // size prefix
2056 case 5:
2057 addr_nop_5();
2058 break;
2059 case 4:
2060 addr_nop_4();
2061 break;
2062 case 3:
2063 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2064 emit_byte(0x66); // size prefix
2065 case 2:
2066 emit_byte(0x66); // size prefix
2067 case 1:
2068 emit_byte(0x90); // nop
2069 break;
2070 default:
2071 assert(i == 0, " ");
2072 }
2073 return;
2074 }
2075 if (UseAddressNop && VM_Version::is_amd()) {
2076 //
2077 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2078 // 1: 0x90
2079 // 2: 0x66 0x90
2080 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2081 // 4: 0x0F 0x1F 0x40 0x00
2082 // 5: 0x0F 0x1F 0x44 0x00 0x00
2083 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2084 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2085 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2086 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2087 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2088 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2090 // The rest coding is AMD specific - use consecutive address nops
2092 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2093 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2094 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2095 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2096 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2097 // Size prefixes (0x66) are added for larger sizes
2099 while(i >= 22) {
2100 i -= 11;
2101 emit_byte(0x66); // size prefix
2102 emit_byte(0x66); // size prefix
2103 emit_byte(0x66); // size prefix
2104 addr_nop_8();
2105 }
2106 // Generate first nop for size between 21-12
2107 switch (i) {
2108 case 21:
2109 i -= 1;
2110 emit_byte(0x66); // size prefix
2111 case 20:
2112 case 19:
2113 i -= 1;
2114 emit_byte(0x66); // size prefix
2115 case 18:
2116 case 17:
2117 i -= 1;
2118 emit_byte(0x66); // size prefix
2119 case 16:
2120 case 15:
2121 i -= 8;
2122 addr_nop_8();
2123 break;
2124 case 14:
2125 case 13:
2126 i -= 7;
2127 addr_nop_7();
2128 break;
2129 case 12:
2130 i -= 6;
2131 emit_byte(0x66); // size prefix
2132 addr_nop_5();
2133 break;
2134 default:
2135 assert(i < 12, " ");
2136 }
2138 // Generate second nop for size between 11-1
2139 switch (i) {
2140 case 11:
2141 emit_byte(0x66); // size prefix
2142 case 10:
2143 emit_byte(0x66); // size prefix
2144 case 9:
2145 emit_byte(0x66); // size prefix
2146 case 8:
2147 addr_nop_8();
2148 break;
2149 case 7:
2150 addr_nop_7();
2151 break;
2152 case 6:
2153 emit_byte(0x66); // size prefix
2154 case 5:
2155 addr_nop_5();
2156 break;
2157 case 4:
2158 addr_nop_4();
2159 break;
2160 case 3:
2161 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2162 emit_byte(0x66); // size prefix
2163 case 2:
2164 emit_byte(0x66); // size prefix
2165 case 1:
2166 emit_byte(0x90); // nop
2167 break;
2168 default:
2169 assert(i == 0, " ");
2170 }
2171 return;
2172 }
2174 // Using nops with size prefixes "0x66 0x90".
2175 // From AMD Optimization Guide:
2176 // 1: 0x90
2177 // 2: 0x66 0x90
2178 // 3: 0x66 0x66 0x90
2179 // 4: 0x66 0x66 0x66 0x90
2180 // 5: 0x66 0x66 0x90 0x66 0x90
2181 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2182 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2183 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2184 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2185 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2186 //
2187 while(i > 12) {
2188 i -= 4;
2189 emit_byte(0x66); // size prefix
2190 emit_byte(0x66);
2191 emit_byte(0x66);
2192 emit_byte(0x90); // nop
2193 }
2194 // 1 - 12 nops
2195 if(i > 8) {
2196 if(i > 9) {
2197 i -= 1;
2198 emit_byte(0x66);
2199 }
2200 i -= 3;
2201 emit_byte(0x66);
2202 emit_byte(0x66);
2203 emit_byte(0x90);
2204 }
2205 // 1 - 8 nops
2206 if(i > 4) {
2207 if(i > 6) {
2208 i -= 1;
2209 emit_byte(0x66);
2210 }
2211 i -= 3;
2212 emit_byte(0x66);
2213 emit_byte(0x66);
2214 emit_byte(0x90);
2215 }
2216 switch (i) {
2217 case 4:
2218 emit_byte(0x66);
2219 case 3:
2220 emit_byte(0x66);
2221 case 2:
2222 emit_byte(0x66);
2223 case 1:
2224 emit_byte(0x90);
2225 break;
2226 default:
2227 assert(i == 0, " ");
2228 }
2229 }
2231 void Assembler::notl(Register dst) {
2232 int encode = prefix_and_encode(dst->encoding());
2233 emit_byte(0xF7);
2234 emit_byte(0xD0 | encode );
2235 }
2237 void Assembler::orl(Address dst, int32_t imm32) {
2238 InstructionMark im(this);
2239 prefix(dst);
2240 emit_arith_operand(0x81, rcx, dst, imm32);
2241 }
2243 void Assembler::orl(Register dst, int32_t imm32) {
2244 prefix(dst);
2245 emit_arith(0x81, 0xC8, dst, imm32);
2246 }
2248 void Assembler::orl(Register dst, Address src) {
2249 InstructionMark im(this);
2250 prefix(src, dst);
2251 emit_byte(0x0B);
2252 emit_operand(dst, src);
2253 }
2255 void Assembler::orl(Register dst, Register src) {
2256 (void) prefix_and_encode(dst->encoding(), src->encoding());
2257 emit_arith(0x0B, 0xC0, dst, src);
2258 }
2260 void Assembler::packuswb(XMMRegister dst, Address src) {
2261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2262 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2263 InstructionMark im(this);
2264 simd_prefix(dst, dst, src, VEX_SIMD_66);
2265 emit_byte(0x67);
2266 emit_operand(dst, src);
2267 }
2269 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2270 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2271 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2272 emit_byte(0x67);
2273 emit_byte(0xC0 | encode);
2274 }
2276 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2277 assert(VM_Version::supports_sse4_2(), "");
2278 InstructionMark im(this);
2279 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2280 emit_byte(0x61);
2281 emit_operand(dst, src);
2282 emit_byte(imm8);
2283 }
2285 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2286 assert(VM_Version::supports_sse4_2(), "");
2287 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2288 emit_byte(0x61);
2289 emit_byte(0xC0 | encode);
2290 emit_byte(imm8);
2291 }
2293 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2294 assert(VM_Version::supports_sse4_1(), "");
2295 InstructionMark im(this);
2296 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2297 emit_byte(0x30);
2298 emit_operand(dst, src);
2299 }
2301 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2302 assert(VM_Version::supports_sse4_1(), "");
2303 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2304 emit_byte(0x30);
2305 emit_byte(0xC0 | encode);
2306 }
2308 // generic
2309 void Assembler::pop(Register dst) {
2310 int encode = prefix_and_encode(dst->encoding());
2311 emit_byte(0x58 | encode);
2312 }
2314 void Assembler::popcntl(Register dst, Address src) {
2315 assert(VM_Version::supports_popcnt(), "must support");
2316 InstructionMark im(this);
2317 emit_byte(0xF3);
2318 prefix(src, dst);
2319 emit_byte(0x0F);
2320 emit_byte(0xB8);
2321 emit_operand(dst, src);
2322 }
2324 void Assembler::popcntl(Register dst, Register src) {
2325 assert(VM_Version::supports_popcnt(), "must support");
2326 emit_byte(0xF3);
2327 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2328 emit_byte(0x0F);
2329 emit_byte(0xB8);
2330 emit_byte(0xC0 | encode);
2331 }
2333 void Assembler::popf() {
2334 emit_byte(0x9D);
2335 }
2337 #ifndef _LP64 // no 32bit push/pop on amd64
2338 void Assembler::popl(Address dst) {
2339 // NOTE: this will adjust stack by 8byte on 64bits
2340 InstructionMark im(this);
2341 prefix(dst);
2342 emit_byte(0x8F);
2343 emit_operand(rax, dst);
2344 }
2345 #endif
2347 void Assembler::prefetch_prefix(Address src) {
2348 prefix(src);
2349 emit_byte(0x0F);
2350 }
2352 void Assembler::prefetchnta(Address src) {
2353 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2354 InstructionMark im(this);
2355 prefetch_prefix(src);
2356 emit_byte(0x18);
2357 emit_operand(rax, src); // 0, src
2358 }
2360 void Assembler::prefetchr(Address src) {
2361 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2362 InstructionMark im(this);
2363 prefetch_prefix(src);
2364 emit_byte(0x0D);
2365 emit_operand(rax, src); // 0, src
2366 }
2368 void Assembler::prefetcht0(Address src) {
2369 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2370 InstructionMark im(this);
2371 prefetch_prefix(src);
2372 emit_byte(0x18);
2373 emit_operand(rcx, src); // 1, src
2374 }
2376 void Assembler::prefetcht1(Address src) {
2377 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2378 InstructionMark im(this);
2379 prefetch_prefix(src);
2380 emit_byte(0x18);
2381 emit_operand(rdx, src); // 2, src
2382 }
2384 void Assembler::prefetcht2(Address src) {
2385 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2386 InstructionMark im(this);
2387 prefetch_prefix(src);
2388 emit_byte(0x18);
2389 emit_operand(rbx, src); // 3, src
2390 }
2392 void Assembler::prefetchw(Address src) {
2393 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2394 InstructionMark im(this);
2395 prefetch_prefix(src);
2396 emit_byte(0x0D);
2397 emit_operand(rcx, src); // 1, src
2398 }
2400 void Assembler::prefix(Prefix p) {
2401 a_byte(p);
2402 }
2404 void Assembler::por(XMMRegister dst, XMMRegister src) {
2405 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2406 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2407 emit_byte(0xEB);
2408 emit_byte(0xC0 | encode);
2409 }
2411 void Assembler::por(XMMRegister dst, Address src) {
2412 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2413 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2414 InstructionMark im(this);
2415 simd_prefix(dst, dst, src, VEX_SIMD_66);
2416 emit_byte(0xEB);
2417 emit_operand(dst, src);
2418 }
2420 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2421 assert(isByte(mode), "invalid value");
2422 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2423 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2424 emit_byte(0x70);
2425 emit_byte(0xC0 | encode);
2426 emit_byte(mode & 0xFF);
2428 }
2430 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2431 assert(isByte(mode), "invalid value");
2432 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2433 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2434 InstructionMark im(this);
2435 simd_prefix(dst, src, VEX_SIMD_66);
2436 emit_byte(0x70);
2437 emit_operand(dst, src);
2438 emit_byte(mode & 0xFF);
2439 }
2441 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2442 assert(isByte(mode), "invalid value");
2443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2444 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
2445 emit_byte(0x70);
2446 emit_byte(0xC0 | encode);
2447 emit_byte(mode & 0xFF);
2448 }
2450 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2451 assert(isByte(mode), "invalid value");
2452 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2453 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2454 InstructionMark im(this);
2455 simd_prefix(dst, src, VEX_SIMD_F2);
2456 emit_byte(0x70);
2457 emit_operand(dst, src);
2458 emit_byte(mode & 0xFF);
2459 }
2461 void Assembler::psrlq(XMMRegister dst, int shift) {
2462 // Shift 64 bit value logically right by specified number of bits.
2463 // HMM Table D-1 says sse2 or mmx.
2464 // Do not confuse it with psrldq SSE2 instruction which
2465 // shifts 128 bit value in xmm register by number of bytes.
2466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2467 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
2468 emit_byte(0x73);
2469 emit_byte(0xC0 | encode);
2470 emit_byte(shift);
2471 }
2473 void Assembler::psrldq(XMMRegister dst, int shift) {
2474 // Shift 128 bit value in xmm register by number of bytes.
2475 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2476 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2477 emit_byte(0x73);
2478 emit_byte(0xC0 | encode);
2479 emit_byte(shift);
2480 }
2482 void Assembler::ptest(XMMRegister dst, Address src) {
2483 assert(VM_Version::supports_sse4_1(), "");
2484 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2485 InstructionMark im(this);
2486 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2487 emit_byte(0x17);
2488 emit_operand(dst, src);
2489 }
2491 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2492 assert(VM_Version::supports_sse4_1(), "");
2493 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2494 emit_byte(0x17);
2495 emit_byte(0xC0 | encode);
2496 }
2498 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2499 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2500 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2501 InstructionMark im(this);
2502 simd_prefix(dst, dst, src, VEX_SIMD_66);
2503 emit_byte(0x60);
2504 emit_operand(dst, src);
2505 }
2507 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2508 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2509 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2510 emit_byte(0x60);
2511 emit_byte(0xC0 | encode);
2512 }
2514 void Assembler::punpckldq(XMMRegister dst, Address src) {
2515 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2516 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2517 InstructionMark im(this);
2518 simd_prefix(dst, dst, src, VEX_SIMD_66);
2519 emit_byte(0x62);
2520 emit_operand(dst, src);
2521 }
2523 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2524 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2525 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2526 emit_byte(0x62);
2527 emit_byte(0xC0 | encode);
2528 }
2530 void Assembler::push(int32_t imm32) {
2531 // in 64bits we push 64bits onto the stack but only
2532 // take a 32bit immediate
2533 emit_byte(0x68);
2534 emit_long(imm32);
2535 }
2537 void Assembler::push(Register src) {
2538 int encode = prefix_and_encode(src->encoding());
2540 emit_byte(0x50 | encode);
2541 }
2543 void Assembler::pushf() {
2544 emit_byte(0x9C);
2545 }
2547 #ifndef _LP64 // no 32bit push/pop on amd64
2548 void Assembler::pushl(Address src) {
2549 // Note this will push 64bit on 64bit
2550 InstructionMark im(this);
2551 prefix(src);
2552 emit_byte(0xFF);
2553 emit_operand(rsi, src);
2554 }
2555 #endif
2557 void Assembler::pxor(XMMRegister dst, Address src) {
2558 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2559 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2560 InstructionMark im(this);
2561 simd_prefix(dst, dst, src, VEX_SIMD_66);
2562 emit_byte(0xEF);
2563 emit_operand(dst, src);
2564 }
2566 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2567 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2568 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2569 emit_byte(0xEF);
2570 emit_byte(0xC0 | encode);
2571 }
2573 void Assembler::rcll(Register dst, int imm8) {
2574 assert(isShiftCount(imm8), "illegal shift count");
2575 int encode = prefix_and_encode(dst->encoding());
2576 if (imm8 == 1) {
2577 emit_byte(0xD1);
2578 emit_byte(0xD0 | encode);
2579 } else {
2580 emit_byte(0xC1);
2581 emit_byte(0xD0 | encode);
2582 emit_byte(imm8);
2583 }
2584 }
2586 // copies data from [esi] to [edi] using rcx pointer sized words
2587 // generic
2588 void Assembler::rep_mov() {
2589 emit_byte(0xF3);
2590 // MOVSQ
2591 LP64_ONLY(prefix(REX_W));
2592 emit_byte(0xA5);
2593 }
2595 // sets rcx pointer sized words with rax, value at [edi]
2596 // generic
2597 void Assembler::rep_set() { // rep_set
2598 emit_byte(0xF3);
2599 // STOSQ
2600 LP64_ONLY(prefix(REX_W));
2601 emit_byte(0xAB);
2602 }
2604 // scans rcx pointer sized words at [edi] for occurance of rax,
2605 // generic
2606 void Assembler::repne_scan() { // repne_scan
2607 emit_byte(0xF2);
2608 // SCASQ
2609 LP64_ONLY(prefix(REX_W));
2610 emit_byte(0xAF);
2611 }
2613 #ifdef _LP64
2614 // scans rcx 4 byte words at [edi] for occurance of rax,
2615 // generic
2616 void Assembler::repne_scanl() { // repne_scan
2617 emit_byte(0xF2);
2618 // SCASL
2619 emit_byte(0xAF);
2620 }
2621 #endif
2623 void Assembler::ret(int imm16) {
2624 if (imm16 == 0) {
2625 emit_byte(0xC3);
2626 } else {
2627 emit_byte(0xC2);
2628 emit_word(imm16);
2629 }
2630 }
2632 void Assembler::sahf() {
2633 #ifdef _LP64
2634 // Not supported in 64bit mode
2635 ShouldNotReachHere();
2636 #endif
2637 emit_byte(0x9E);
2638 }
2640 void Assembler::sarl(Register dst, int imm8) {
2641 int encode = prefix_and_encode(dst->encoding());
2642 assert(isShiftCount(imm8), "illegal shift count");
2643 if (imm8 == 1) {
2644 emit_byte(0xD1);
2645 emit_byte(0xF8 | encode);
2646 } else {
2647 emit_byte(0xC1);
2648 emit_byte(0xF8 | encode);
2649 emit_byte(imm8);
2650 }
2651 }
2653 void Assembler::sarl(Register dst) {
2654 int encode = prefix_and_encode(dst->encoding());
2655 emit_byte(0xD3);
2656 emit_byte(0xF8 | encode);
2657 }
2659 void Assembler::sbbl(Address dst, int32_t imm32) {
2660 InstructionMark im(this);
2661 prefix(dst);
2662 emit_arith_operand(0x81, rbx, dst, imm32);
2663 }
2665 void Assembler::sbbl(Register dst, int32_t imm32) {
2666 prefix(dst);
2667 emit_arith(0x81, 0xD8, dst, imm32);
2668 }
2671 void Assembler::sbbl(Register dst, Address src) {
2672 InstructionMark im(this);
2673 prefix(src, dst);
2674 emit_byte(0x1B);
2675 emit_operand(dst, src);
2676 }
2678 void Assembler::sbbl(Register dst, Register src) {
2679 (void) prefix_and_encode(dst->encoding(), src->encoding());
2680 emit_arith(0x1B, 0xC0, dst, src);
2681 }
2683 void Assembler::setb(Condition cc, Register dst) {
2684 assert(0 <= cc && cc < 16, "illegal cc");
2685 int encode = prefix_and_encode(dst->encoding(), true);
2686 emit_byte(0x0F);
2687 emit_byte(0x90 | cc);
2688 emit_byte(0xC0 | encode);
2689 }
2691 void Assembler::shll(Register dst, int imm8) {
2692 assert(isShiftCount(imm8), "illegal shift count");
2693 int encode = prefix_and_encode(dst->encoding());
2694 if (imm8 == 1 ) {
2695 emit_byte(0xD1);
2696 emit_byte(0xE0 | encode);
2697 } else {
2698 emit_byte(0xC1);
2699 emit_byte(0xE0 | encode);
2700 emit_byte(imm8);
2701 }
2702 }
2704 void Assembler::shll(Register dst) {
2705 int encode = prefix_and_encode(dst->encoding());
2706 emit_byte(0xD3);
2707 emit_byte(0xE0 | encode);
2708 }
2710 void Assembler::shrl(Register dst, int imm8) {
2711 assert(isShiftCount(imm8), "illegal shift count");
2712 int encode = prefix_and_encode(dst->encoding());
2713 emit_byte(0xC1);
2714 emit_byte(0xE8 | encode);
2715 emit_byte(imm8);
2716 }
2718 void Assembler::shrl(Register dst) {
2719 int encode = prefix_and_encode(dst->encoding());
2720 emit_byte(0xD3);
2721 emit_byte(0xE8 | encode);
2722 }
2724 // copies a single word from [esi] to [edi]
2725 void Assembler::smovl() {
2726 emit_byte(0xA5);
2727 }
2729 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2731 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2732 emit_byte(0x51);
2733 emit_byte(0xC0 | encode);
2734 }
2736 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2737 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2738 InstructionMark im(this);
2739 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2740 emit_byte(0x51);
2741 emit_operand(dst, src);
2742 }
2744 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2745 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2746 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2747 emit_byte(0x51);
2748 emit_byte(0xC0 | encode);
2749 }
2751 void Assembler::sqrtss(XMMRegister dst, Address src) {
2752 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2753 InstructionMark im(this);
2754 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2755 emit_byte(0x51);
2756 emit_operand(dst, src);
2757 }
2759 void Assembler::stmxcsr( Address dst) {
2760 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2761 InstructionMark im(this);
2762 prefix(dst);
2763 emit_byte(0x0F);
2764 emit_byte(0xAE);
2765 emit_operand(as_Register(3), dst);
2766 }
2768 void Assembler::subl(Address dst, int32_t imm32) {
2769 InstructionMark im(this);
2770 prefix(dst);
2771 emit_arith_operand(0x81, rbp, dst, imm32);
2772 }
2774 void Assembler::subl(Address dst, Register src) {
2775 InstructionMark im(this);
2776 prefix(dst, src);
2777 emit_byte(0x29);
2778 emit_operand(src, dst);
2779 }
2781 void Assembler::subl(Register dst, int32_t imm32) {
2782 prefix(dst);
2783 emit_arith(0x81, 0xE8, dst, imm32);
2784 }
2786 // Force generation of a 4 byte immediate value even if it fits into 8bit
2787 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2788 prefix(dst);
2789 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2790 }
2792 void Assembler::subl(Register dst, Address src) {
2793 InstructionMark im(this);
2794 prefix(src, dst);
2795 emit_byte(0x2B);
2796 emit_operand(dst, src);
2797 }
2799 void Assembler::subl(Register dst, Register src) {
2800 (void) prefix_and_encode(dst->encoding(), src->encoding());
2801 emit_arith(0x2B, 0xC0, dst, src);
2802 }
2804 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2805 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2806 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2807 emit_byte(0x5C);
2808 emit_byte(0xC0 | encode);
2809 }
2811 void Assembler::subsd(XMMRegister dst, Address src) {
2812 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2813 InstructionMark im(this);
2814 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2815 emit_byte(0x5C);
2816 emit_operand(dst, src);
2817 }
2819 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2820 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2822 emit_byte(0x5C);
2823 emit_byte(0xC0 | encode);
2824 }
2826 void Assembler::subss(XMMRegister dst, Address src) {
2827 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2828 InstructionMark im(this);
2829 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2830 emit_byte(0x5C);
2831 emit_operand(dst, src);
2832 }
2834 void Assembler::testb(Register dst, int imm8) {
2835 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2836 (void) prefix_and_encode(dst->encoding(), true);
2837 emit_arith_b(0xF6, 0xC0, dst, imm8);
2838 }
2840 void Assembler::testl(Register dst, int32_t imm32) {
2841 // not using emit_arith because test
2842 // doesn't support sign-extension of
2843 // 8bit operands
2844 int encode = dst->encoding();
2845 if (encode == 0) {
2846 emit_byte(0xA9);
2847 } else {
2848 encode = prefix_and_encode(encode);
2849 emit_byte(0xF7);
2850 emit_byte(0xC0 | encode);
2851 }
2852 emit_long(imm32);
2853 }
2855 void Assembler::testl(Register dst, Register src) {
2856 (void) prefix_and_encode(dst->encoding(), src->encoding());
2857 emit_arith(0x85, 0xC0, dst, src);
2858 }
2860 void Assembler::testl(Register dst, Address src) {
2861 InstructionMark im(this);
2862 prefix(src, dst);
2863 emit_byte(0x85);
2864 emit_operand(dst, src);
2865 }
2867 void Assembler::ucomisd(XMMRegister dst, Address src) {
2868 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2869 InstructionMark im(this);
2870 simd_prefix(dst, src, VEX_SIMD_66);
2871 emit_byte(0x2E);
2872 emit_operand(dst, src);
2873 }
2875 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2877 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2878 emit_byte(0x2E);
2879 emit_byte(0xC0 | encode);
2880 }
2882 void Assembler::ucomiss(XMMRegister dst, Address src) {
2883 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2884 InstructionMark im(this);
2885 simd_prefix(dst, src, VEX_SIMD_NONE);
2886 emit_byte(0x2E);
2887 emit_operand(dst, src);
2888 }
2890 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2891 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2892 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
2893 emit_byte(0x2E);
2894 emit_byte(0xC0 | encode);
2895 }
2898 void Assembler::xaddl(Address dst, Register src) {
2899 InstructionMark im(this);
2900 prefix(dst, src);
2901 emit_byte(0x0F);
2902 emit_byte(0xC1);
2903 emit_operand(src, dst);
2904 }
2906 void Assembler::xchgl(Register dst, Address src) { // xchg
2907 InstructionMark im(this);
2908 prefix(src, dst);
2909 emit_byte(0x87);
2910 emit_operand(dst, src);
2911 }
2913 void Assembler::xchgl(Register dst, Register src) {
2914 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2915 emit_byte(0x87);
2916 emit_byte(0xc0 | encode);
2917 }
2919 void Assembler::xorl(Register dst, int32_t imm32) {
2920 prefix(dst);
2921 emit_arith(0x81, 0xF0, dst, imm32);
2922 }
2924 void Assembler::xorl(Register dst, Address src) {
2925 InstructionMark im(this);
2926 prefix(src, dst);
2927 emit_byte(0x33);
2928 emit_operand(dst, src);
2929 }
2931 void Assembler::xorl(Register dst, Register src) {
2932 (void) prefix_and_encode(dst->encoding(), src->encoding());
2933 emit_arith(0x33, 0xC0, dst, src);
2934 }
2936 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2937 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2938 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2939 emit_byte(0x57);
2940 emit_byte(0xC0 | encode);
2941 }
2943 void Assembler::xorpd(XMMRegister dst, Address src) {
2944 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2945 InstructionMark im(this);
2946 simd_prefix(dst, dst, src, VEX_SIMD_66);
2947 emit_byte(0x57);
2948 emit_operand(dst, src);
2949 }
2952 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2953 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2954 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
2955 emit_byte(0x57);
2956 emit_byte(0xC0 | encode);
2957 }
2959 void Assembler::xorps(XMMRegister dst, Address src) {
2960 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2961 InstructionMark im(this);
2962 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
2963 emit_byte(0x57);
2964 emit_operand(dst, src);
2965 }
2967 // AVX 3-operands non destructive source instructions (encoded with VEX prefix)
2969 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
2970 assert(VM_Version::supports_avx(), "");
2971 InstructionMark im(this);
2972 vex_prefix(dst, nds, src, VEX_SIMD_F2);
2973 emit_byte(0x58);
2974 emit_operand(dst, src);
2975 }
2977 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2978 assert(VM_Version::supports_avx(), "");
2979 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
2980 emit_byte(0x58);
2981 emit_byte(0xC0 | encode);
2982 }
2984 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
2985 assert(VM_Version::supports_avx(), "");
2986 InstructionMark im(this);
2987 vex_prefix(dst, nds, src, VEX_SIMD_F3);
2988 emit_byte(0x58);
2989 emit_operand(dst, src);
2990 }
2992 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2993 assert(VM_Version::supports_avx(), "");
2994 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
2995 emit_byte(0x58);
2996 emit_byte(0xC0 | encode);
2997 }
2999 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) {
3000 assert(VM_Version::supports_avx(), "");
3001 InstructionMark im(this);
3002 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
3003 emit_byte(0x54);
3004 emit_operand(dst, src);
3005 }
3007 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) {
3008 assert(VM_Version::supports_avx(), "");
3009 InstructionMark im(this);
3010 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
3011 emit_byte(0x54);
3012 emit_operand(dst, src);
3013 }
3015 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3016 assert(VM_Version::supports_avx(), "");
3017 InstructionMark im(this);
3018 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3019 emit_byte(0x5E);
3020 emit_operand(dst, src);
3021 }
3023 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3024 assert(VM_Version::supports_avx(), "");
3025 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3026 emit_byte(0x5E);
3027 emit_byte(0xC0 | encode);
3028 }
3030 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3031 assert(VM_Version::supports_avx(), "");
3032 InstructionMark im(this);
3033 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3034 emit_byte(0x5E);
3035 emit_operand(dst, src);
3036 }
3038 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3039 assert(VM_Version::supports_avx(), "");
3040 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3041 emit_byte(0x5E);
3042 emit_byte(0xC0 | encode);
3043 }
3045 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3046 assert(VM_Version::supports_avx(), "");
3047 InstructionMark im(this);
3048 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3049 emit_byte(0x59);
3050 emit_operand(dst, src);
3051 }
3053 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3054 assert(VM_Version::supports_avx(), "");
3055 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3056 emit_byte(0x59);
3057 emit_byte(0xC0 | encode);
3058 }
3060 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3061 InstructionMark im(this);
3062 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3063 emit_byte(0x59);
3064 emit_operand(dst, src);
3065 }
3067 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3068 assert(VM_Version::supports_avx(), "");
3069 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3070 emit_byte(0x59);
3071 emit_byte(0xC0 | encode);
3072 }
3075 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3076 assert(VM_Version::supports_avx(), "");
3077 InstructionMark im(this);
3078 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3079 emit_byte(0x5C);
3080 emit_operand(dst, src);
3081 }
3083 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3084 assert(VM_Version::supports_avx(), "");
3085 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3086 emit_byte(0x5C);
3087 emit_byte(0xC0 | encode);
3088 }
3090 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3091 assert(VM_Version::supports_avx(), "");
3092 InstructionMark im(this);
3093 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3094 emit_byte(0x5C);
3095 emit_operand(dst, src);
3096 }
3098 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3099 assert(VM_Version::supports_avx(), "");
3100 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3101 emit_byte(0x5C);
3102 emit_byte(0xC0 | encode);
3103 }
3105 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) {
3106 assert(VM_Version::supports_avx(), "");
3107 InstructionMark im(this);
3108 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
3109 emit_byte(0x57);
3110 emit_operand(dst, src);
3111 }
3113 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) {
3114 assert(VM_Version::supports_avx(), "");
3115 InstructionMark im(this);
3116 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
3117 emit_byte(0x57);
3118 emit_operand(dst, src);
3119 }
3122 #ifndef _LP64
3123 // 32bit only pieces of the assembler
3125 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3126 // NO PREFIX AS NEVER 64BIT
3127 InstructionMark im(this);
3128 emit_byte(0x81);
3129 emit_byte(0xF8 | src1->encoding());
3130 emit_data(imm32, rspec, 0);
3131 }
3133 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3134 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3135 InstructionMark im(this);
3136 emit_byte(0x81);
3137 emit_operand(rdi, src1);
3138 emit_data(imm32, rspec, 0);
3139 }
3141 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3142 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3143 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3144 void Assembler::cmpxchg8(Address adr) {
3145 InstructionMark im(this);
3146 emit_byte(0x0F);
3147 emit_byte(0xc7);
3148 emit_operand(rcx, adr);
3149 }
3151 void Assembler::decl(Register dst) {
3152 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3153 emit_byte(0x48 | dst->encoding());
3154 }
3156 #endif // _LP64
3158 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3160 void Assembler::fabs() {
3161 emit_byte(0xD9);
3162 emit_byte(0xE1);
3163 }
3165 void Assembler::fadd(int i) {
3166 emit_farith(0xD8, 0xC0, i);
3167 }
3169 void Assembler::fadd_d(Address src) {
3170 InstructionMark im(this);
3171 emit_byte(0xDC);
3172 emit_operand32(rax, src);
3173 }
3175 void Assembler::fadd_s(Address src) {
3176 InstructionMark im(this);
3177 emit_byte(0xD8);
3178 emit_operand32(rax, src);
3179 }
3181 void Assembler::fadda(int i) {
3182 emit_farith(0xDC, 0xC0, i);
3183 }
3185 void Assembler::faddp(int i) {
3186 emit_farith(0xDE, 0xC0, i);
3187 }
3189 void Assembler::fchs() {
3190 emit_byte(0xD9);
3191 emit_byte(0xE0);
3192 }
3194 void Assembler::fcom(int i) {
3195 emit_farith(0xD8, 0xD0, i);
3196 }
3198 void Assembler::fcomp(int i) {
3199 emit_farith(0xD8, 0xD8, i);
3200 }
3202 void Assembler::fcomp_d(Address src) {
3203 InstructionMark im(this);
3204 emit_byte(0xDC);
3205 emit_operand32(rbx, src);
3206 }
3208 void Assembler::fcomp_s(Address src) {
3209 InstructionMark im(this);
3210 emit_byte(0xD8);
3211 emit_operand32(rbx, src);
3212 }
3214 void Assembler::fcompp() {
3215 emit_byte(0xDE);
3216 emit_byte(0xD9);
3217 }
3219 void Assembler::fcos() {
3220 emit_byte(0xD9);
3221 emit_byte(0xFF);
3222 }
3224 void Assembler::fdecstp() {
3225 emit_byte(0xD9);
3226 emit_byte(0xF6);
3227 }
3229 void Assembler::fdiv(int i) {
3230 emit_farith(0xD8, 0xF0, i);
3231 }
3233 void Assembler::fdiv_d(Address src) {
3234 InstructionMark im(this);
3235 emit_byte(0xDC);
3236 emit_operand32(rsi, src);
3237 }
3239 void Assembler::fdiv_s(Address src) {
3240 InstructionMark im(this);
3241 emit_byte(0xD8);
3242 emit_operand32(rsi, src);
3243 }
3245 void Assembler::fdiva(int i) {
3246 emit_farith(0xDC, 0xF8, i);
3247 }
3249 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3250 // is erroneous for some of the floating-point instructions below.
3252 void Assembler::fdivp(int i) {
3253 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3254 }
3256 void Assembler::fdivr(int i) {
3257 emit_farith(0xD8, 0xF8, i);
3258 }
3260 void Assembler::fdivr_d(Address src) {
3261 InstructionMark im(this);
3262 emit_byte(0xDC);
3263 emit_operand32(rdi, src);
3264 }
3266 void Assembler::fdivr_s(Address src) {
3267 InstructionMark im(this);
3268 emit_byte(0xD8);
3269 emit_operand32(rdi, src);
3270 }
3272 void Assembler::fdivra(int i) {
3273 emit_farith(0xDC, 0xF0, i);
3274 }
3276 void Assembler::fdivrp(int i) {
3277 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3278 }
3280 void Assembler::ffree(int i) {
3281 emit_farith(0xDD, 0xC0, i);
3282 }
3284 void Assembler::fild_d(Address adr) {
3285 InstructionMark im(this);
3286 emit_byte(0xDF);
3287 emit_operand32(rbp, adr);
3288 }
3290 void Assembler::fild_s(Address adr) {
3291 InstructionMark im(this);
3292 emit_byte(0xDB);
3293 emit_operand32(rax, adr);
3294 }
3296 void Assembler::fincstp() {
3297 emit_byte(0xD9);
3298 emit_byte(0xF7);
3299 }
3301 void Assembler::finit() {
3302 emit_byte(0x9B);
3303 emit_byte(0xDB);
3304 emit_byte(0xE3);
3305 }
3307 void Assembler::fist_s(Address adr) {
3308 InstructionMark im(this);
3309 emit_byte(0xDB);
3310 emit_operand32(rdx, adr);
3311 }
3313 void Assembler::fistp_d(Address adr) {
3314 InstructionMark im(this);
3315 emit_byte(0xDF);
3316 emit_operand32(rdi, adr);
3317 }
3319 void Assembler::fistp_s(Address adr) {
3320 InstructionMark im(this);
3321 emit_byte(0xDB);
3322 emit_operand32(rbx, adr);
3323 }
3325 void Assembler::fld1() {
3326 emit_byte(0xD9);
3327 emit_byte(0xE8);
3328 }
3330 void Assembler::fld_d(Address adr) {
3331 InstructionMark im(this);
3332 emit_byte(0xDD);
3333 emit_operand32(rax, adr);
3334 }
3336 void Assembler::fld_s(Address adr) {
3337 InstructionMark im(this);
3338 emit_byte(0xD9);
3339 emit_operand32(rax, adr);
3340 }
3343 void Assembler::fld_s(int index) {
3344 emit_farith(0xD9, 0xC0, index);
3345 }
3347 void Assembler::fld_x(Address adr) {
3348 InstructionMark im(this);
3349 emit_byte(0xDB);
3350 emit_operand32(rbp, adr);
3351 }
3353 void Assembler::fldcw(Address src) {
3354 InstructionMark im(this);
3355 emit_byte(0xd9);
3356 emit_operand32(rbp, src);
3357 }
3359 void Assembler::fldenv(Address src) {
3360 InstructionMark im(this);
3361 emit_byte(0xD9);
3362 emit_operand32(rsp, src);
3363 }
3365 void Assembler::fldlg2() {
3366 emit_byte(0xD9);
3367 emit_byte(0xEC);
3368 }
3370 void Assembler::fldln2() {
3371 emit_byte(0xD9);
3372 emit_byte(0xED);
3373 }
3375 void Assembler::fldz() {
3376 emit_byte(0xD9);
3377 emit_byte(0xEE);
3378 }
3380 void Assembler::flog() {
3381 fldln2();
3382 fxch();
3383 fyl2x();
3384 }
3386 void Assembler::flog10() {
3387 fldlg2();
3388 fxch();
3389 fyl2x();
3390 }
3392 void Assembler::fmul(int i) {
3393 emit_farith(0xD8, 0xC8, i);
3394 }
3396 void Assembler::fmul_d(Address src) {
3397 InstructionMark im(this);
3398 emit_byte(0xDC);
3399 emit_operand32(rcx, src);
3400 }
3402 void Assembler::fmul_s(Address src) {
3403 InstructionMark im(this);
3404 emit_byte(0xD8);
3405 emit_operand32(rcx, src);
3406 }
3408 void Assembler::fmula(int i) {
3409 emit_farith(0xDC, 0xC8, i);
3410 }
3412 void Assembler::fmulp(int i) {
3413 emit_farith(0xDE, 0xC8, i);
3414 }
3416 void Assembler::fnsave(Address dst) {
3417 InstructionMark im(this);
3418 emit_byte(0xDD);
3419 emit_operand32(rsi, dst);
3420 }
3422 void Assembler::fnstcw(Address src) {
3423 InstructionMark im(this);
3424 emit_byte(0x9B);
3425 emit_byte(0xD9);
3426 emit_operand32(rdi, src);
3427 }
3429 void Assembler::fnstsw_ax() {
3430 emit_byte(0xdF);
3431 emit_byte(0xE0);
3432 }
3434 void Assembler::fprem() {
3435 emit_byte(0xD9);
3436 emit_byte(0xF8);
3437 }
3439 void Assembler::fprem1() {
3440 emit_byte(0xD9);
3441 emit_byte(0xF5);
3442 }
3444 void Assembler::frstor(Address src) {
3445 InstructionMark im(this);
3446 emit_byte(0xDD);
3447 emit_operand32(rsp, src);
3448 }
3450 void Assembler::fsin() {
3451 emit_byte(0xD9);
3452 emit_byte(0xFE);
3453 }
3455 void Assembler::fsqrt() {
3456 emit_byte(0xD9);
3457 emit_byte(0xFA);
3458 }
3460 void Assembler::fst_d(Address adr) {
3461 InstructionMark im(this);
3462 emit_byte(0xDD);
3463 emit_operand32(rdx, adr);
3464 }
3466 void Assembler::fst_s(Address adr) {
3467 InstructionMark im(this);
3468 emit_byte(0xD9);
3469 emit_operand32(rdx, adr);
3470 }
3472 void Assembler::fstp_d(Address adr) {
3473 InstructionMark im(this);
3474 emit_byte(0xDD);
3475 emit_operand32(rbx, adr);
3476 }
3478 void Assembler::fstp_d(int index) {
3479 emit_farith(0xDD, 0xD8, index);
3480 }
3482 void Assembler::fstp_s(Address adr) {
3483 InstructionMark im(this);
3484 emit_byte(0xD9);
3485 emit_operand32(rbx, adr);
3486 }
3488 void Assembler::fstp_x(Address adr) {
3489 InstructionMark im(this);
3490 emit_byte(0xDB);
3491 emit_operand32(rdi, adr);
3492 }
3494 void Assembler::fsub(int i) {
3495 emit_farith(0xD8, 0xE0, i);
3496 }
3498 void Assembler::fsub_d(Address src) {
3499 InstructionMark im(this);
3500 emit_byte(0xDC);
3501 emit_operand32(rsp, src);
3502 }
3504 void Assembler::fsub_s(Address src) {
3505 InstructionMark im(this);
3506 emit_byte(0xD8);
3507 emit_operand32(rsp, src);
3508 }
3510 void Assembler::fsuba(int i) {
3511 emit_farith(0xDC, 0xE8, i);
3512 }
3514 void Assembler::fsubp(int i) {
3515 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
3516 }
3518 void Assembler::fsubr(int i) {
3519 emit_farith(0xD8, 0xE8, i);
3520 }
3522 void Assembler::fsubr_d(Address src) {
3523 InstructionMark im(this);
3524 emit_byte(0xDC);
3525 emit_operand32(rbp, src);
3526 }
3528 void Assembler::fsubr_s(Address src) {
3529 InstructionMark im(this);
3530 emit_byte(0xD8);
3531 emit_operand32(rbp, src);
3532 }
3534 void Assembler::fsubra(int i) {
3535 emit_farith(0xDC, 0xE0, i);
3536 }
3538 void Assembler::fsubrp(int i) {
3539 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
3540 }
3542 void Assembler::ftan() {
3543 emit_byte(0xD9);
3544 emit_byte(0xF2);
3545 emit_byte(0xDD);
3546 emit_byte(0xD8);
3547 }
3549 void Assembler::ftst() {
3550 emit_byte(0xD9);
3551 emit_byte(0xE4);
3552 }
3554 void Assembler::fucomi(int i) {
3555 // make sure the instruction is supported (introduced for P6, together with cmov)
3556 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3557 emit_farith(0xDB, 0xE8, i);
3558 }
3560 void Assembler::fucomip(int i) {
3561 // make sure the instruction is supported (introduced for P6, together with cmov)
3562 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3563 emit_farith(0xDF, 0xE8, i);
3564 }
3566 void Assembler::fwait() {
3567 emit_byte(0x9B);
3568 }
3570 void Assembler::fxch(int i) {
3571 emit_farith(0xD9, 0xC8, i);
3572 }
3574 void Assembler::fyl2x() {
3575 emit_byte(0xD9);
3576 emit_byte(0xF1);
3577 }
3579 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
3580 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
3581 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
3582 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
3584 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
3585 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
3586 if (pre > 0) {
3587 emit_byte(simd_pre[pre]);
3588 }
3589 if (rex_w) {
3590 prefixq(adr, xreg);
3591 } else {
3592 prefix(adr, xreg);
3593 }
3594 if (opc > 0) {
3595 emit_byte(0x0F);
3596 int opc2 = simd_opc[opc];
3597 if (opc2 > 0) {
3598 emit_byte(opc2);
3599 }
3600 }
3601 }
3603 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
3604 if (pre > 0) {
3605 emit_byte(simd_pre[pre]);
3606 }
3607 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
3608 prefix_and_encode(dst_enc, src_enc);
3609 if (opc > 0) {
3610 emit_byte(0x0F);
3611 int opc2 = simd_opc[opc];
3612 if (opc2 > 0) {
3613 emit_byte(opc2);
3614 }
3615 }
3616 return encode;
3617 }
3620 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
3621 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
3622 prefix(VEX_3bytes);
3624 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
3625 byte1 = (~byte1) & 0xE0;
3626 byte1 |= opc;
3627 a_byte(byte1);
3629 int byte2 = ((~nds_enc) & 0xf) << 3;
3630 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
3631 emit_byte(byte2);
3632 } else {
3633 prefix(VEX_2bytes);
3635 int byte1 = vex_r ? VEX_R : 0;
3636 byte1 = (~byte1) & 0x80;
3637 byte1 |= ((~nds_enc) & 0xf) << 3;
3638 byte1 |= (vector256 ? 4 : 0) | pre;
3639 emit_byte(byte1);
3640 }
3641 }
3643 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
3644 bool vex_r = (xreg_enc >= 8);
3645 bool vex_b = adr.base_needs_rex();
3646 bool vex_x = adr.index_needs_rex();
3647 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
3648 }
3650 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
3651 bool vex_r = (dst_enc >= 8);
3652 bool vex_b = (src_enc >= 8);
3653 bool vex_x = false;
3654 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
3655 return (((dst_enc & 7) << 3) | (src_enc & 7));
3656 }
3659 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
3660 if (UseAVX > 0) {
3661 int xreg_enc = xreg->encoding();
3662 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3663 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
3664 } else {
3665 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
3666 rex_prefix(adr, xreg, pre, opc, rex_w);
3667 }
3668 }
3670 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
3671 int dst_enc = dst->encoding();
3672 int src_enc = src->encoding();
3673 if (UseAVX > 0) {
3674 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3675 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
3676 } else {
3677 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
3678 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
3679 }
3680 }
3682 #ifndef _LP64
3684 void Assembler::incl(Register dst) {
3685 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3686 emit_byte(0x40 | dst->encoding());
3687 }
3689 void Assembler::lea(Register dst, Address src) {
3690 leal(dst, src);
3691 }
3693 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3694 InstructionMark im(this);
3695 emit_byte(0xC7);
3696 emit_operand(rax, dst);
3697 emit_data((int)imm32, rspec, 0);
3698 }
3700 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3701 InstructionMark im(this);
3702 int encode = prefix_and_encode(dst->encoding());
3703 emit_byte(0xB8 | encode);
3704 emit_data((int)imm32, rspec, 0);
3705 }
3707 void Assembler::popa() { // 32bit
3708 emit_byte(0x61);
3709 }
3711 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
3712 InstructionMark im(this);
3713 emit_byte(0x68);
3714 emit_data(imm32, rspec, 0);
3715 }
3717 void Assembler::pusha() { // 32bit
3718 emit_byte(0x60);
3719 }
3721 void Assembler::set_byte_if_not_zero(Register dst) {
3722 emit_byte(0x0F);
3723 emit_byte(0x95);
3724 emit_byte(0xE0 | dst->encoding());
3725 }
3727 void Assembler::shldl(Register dst, Register src) {
3728 emit_byte(0x0F);
3729 emit_byte(0xA5);
3730 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3731 }
3733 void Assembler::shrdl(Register dst, Register src) {
3734 emit_byte(0x0F);
3735 emit_byte(0xAD);
3736 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3737 }
3739 #else // LP64
3741 void Assembler::set_byte_if_not_zero(Register dst) {
3742 int enc = prefix_and_encode(dst->encoding(), true);
3743 emit_byte(0x0F);
3744 emit_byte(0x95);
3745 emit_byte(0xE0 | enc);
3746 }
3748 // 64bit only pieces of the assembler
3749 // This should only be used by 64bit instructions that can use rip-relative
3750 // it cannot be used by instructions that want an immediate value.
3752 bool Assembler::reachable(AddressLiteral adr) {
3753 int64_t disp;
3754 // None will force a 64bit literal to the code stream. Likely a placeholder
3755 // for something that will be patched later and we need to certain it will
3756 // always be reachable.
3757 if (adr.reloc() == relocInfo::none) {
3758 return false;
3759 }
3760 if (adr.reloc() == relocInfo::internal_word_type) {
3761 // This should be rip relative and easily reachable.
3762 return true;
3763 }
3764 if (adr.reloc() == relocInfo::virtual_call_type ||
3765 adr.reloc() == relocInfo::opt_virtual_call_type ||
3766 adr.reloc() == relocInfo::static_call_type ||
3767 adr.reloc() == relocInfo::static_stub_type ) {
3768 // This should be rip relative within the code cache and easily
3769 // reachable until we get huge code caches. (At which point
3770 // ic code is going to have issues).
3771 return true;
3772 }
3773 if (adr.reloc() != relocInfo::external_word_type &&
3774 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
3775 adr.reloc() != relocInfo::poll_type && // relocs to identify them
3776 adr.reloc() != relocInfo::runtime_call_type ) {
3777 return false;
3778 }
3780 // Stress the correction code
3781 if (ForceUnreachable) {
3782 // Must be runtimecall reloc, see if it is in the codecache
3783 // Flipping stuff in the codecache to be unreachable causes issues
3784 // with things like inline caches where the additional instructions
3785 // are not handled.
3786 if (CodeCache::find_blob(adr._target) == NULL) {
3787 return false;
3788 }
3789 }
3790 // For external_word_type/runtime_call_type if it is reachable from where we
3791 // are now (possibly a temp buffer) and where we might end up
3792 // anywhere in the codeCache then we are always reachable.
3793 // This would have to change if we ever save/restore shared code
3794 // to be more pessimistic.
3795 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
3796 if (!is_simm32(disp)) return false;
3797 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
3798 if (!is_simm32(disp)) return false;
3800 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
3802 // Because rip relative is a disp + address_of_next_instruction and we
3803 // don't know the value of address_of_next_instruction we apply a fudge factor
3804 // to make sure we will be ok no matter the size of the instruction we get placed into.
3805 // We don't have to fudge the checks above here because they are already worst case.
3807 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
3808 // + 4 because better safe than sorry.
3809 const int fudge = 12 + 4;
3810 if (disp < 0) {
3811 disp -= fudge;
3812 } else {
3813 disp += fudge;
3814 }
3815 return is_simm32(disp);
3816 }
3818 // Check if the polling page is not reachable from the code cache using rip-relative
3819 // addressing.
3820 bool Assembler::is_polling_page_far() {
3821 intptr_t addr = (intptr_t)os::get_polling_page();
3822 return ForceUnreachable ||
3823 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
3824 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
3825 }
3827 void Assembler::emit_data64(jlong data,
3828 relocInfo::relocType rtype,
3829 int format) {
3830 if (rtype == relocInfo::none) {
3831 emit_long64(data);
3832 } else {
3833 emit_data64(data, Relocation::spec_simple(rtype), format);
3834 }
3835 }
3837 void Assembler::emit_data64(jlong data,
3838 RelocationHolder const& rspec,
3839 int format) {
3840 assert(imm_operand == 0, "default format must be immediate in this file");
3841 assert(imm_operand == format, "must be immediate");
3842 assert(inst_mark() != NULL, "must be inside InstructionMark");
3843 // Do not use AbstractAssembler::relocate, which is not intended for
3844 // embedded words. Instead, relocate to the enclosing instruction.
3845 code_section()->relocate(inst_mark(), rspec, format);
3846 #ifdef ASSERT
3847 check_relocation(rspec, format);
3848 #endif
3849 emit_long64(data);
3850 }
3852 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
3853 if (reg_enc >= 8) {
3854 prefix(REX_B);
3855 reg_enc -= 8;
3856 } else if (byteinst && reg_enc >= 4) {
3857 prefix(REX);
3858 }
3859 return reg_enc;
3860 }
3862 int Assembler::prefixq_and_encode(int reg_enc) {
3863 if (reg_enc < 8) {
3864 prefix(REX_W);
3865 } else {
3866 prefix(REX_WB);
3867 reg_enc -= 8;
3868 }
3869 return reg_enc;
3870 }
3872 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
3873 if (dst_enc < 8) {
3874 if (src_enc >= 8) {
3875 prefix(REX_B);
3876 src_enc -= 8;
3877 } else if (byteinst && src_enc >= 4) {
3878 prefix(REX);
3879 }
3880 } else {
3881 if (src_enc < 8) {
3882 prefix(REX_R);
3883 } else {
3884 prefix(REX_RB);
3885 src_enc -= 8;
3886 }
3887 dst_enc -= 8;
3888 }
3889 return dst_enc << 3 | src_enc;
3890 }
3892 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
3893 if (dst_enc < 8) {
3894 if (src_enc < 8) {
3895 prefix(REX_W);
3896 } else {
3897 prefix(REX_WB);
3898 src_enc -= 8;
3899 }
3900 } else {
3901 if (src_enc < 8) {
3902 prefix(REX_WR);
3903 } else {
3904 prefix(REX_WRB);
3905 src_enc -= 8;
3906 }
3907 dst_enc -= 8;
3908 }
3909 return dst_enc << 3 | src_enc;
3910 }
3912 void Assembler::prefix(Register reg) {
3913 if (reg->encoding() >= 8) {
3914 prefix(REX_B);
3915 }
3916 }
3918 void Assembler::prefix(Address adr) {
3919 if (adr.base_needs_rex()) {
3920 if (adr.index_needs_rex()) {
3921 prefix(REX_XB);
3922 } else {
3923 prefix(REX_B);
3924 }
3925 } else {
3926 if (adr.index_needs_rex()) {
3927 prefix(REX_X);
3928 }
3929 }
3930 }
3932 void Assembler::prefixq(Address adr) {
3933 if (adr.base_needs_rex()) {
3934 if (adr.index_needs_rex()) {
3935 prefix(REX_WXB);
3936 } else {
3937 prefix(REX_WB);
3938 }
3939 } else {
3940 if (adr.index_needs_rex()) {
3941 prefix(REX_WX);
3942 } else {
3943 prefix(REX_W);
3944 }
3945 }
3946 }
3949 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
3950 if (reg->encoding() < 8) {
3951 if (adr.base_needs_rex()) {
3952 if (adr.index_needs_rex()) {
3953 prefix(REX_XB);
3954 } else {
3955 prefix(REX_B);
3956 }
3957 } else {
3958 if (adr.index_needs_rex()) {
3959 prefix(REX_X);
3960 } else if (byteinst && reg->encoding() >= 4 ) {
3961 prefix(REX);
3962 }
3963 }
3964 } else {
3965 if (adr.base_needs_rex()) {
3966 if (adr.index_needs_rex()) {
3967 prefix(REX_RXB);
3968 } else {
3969 prefix(REX_RB);
3970 }
3971 } else {
3972 if (adr.index_needs_rex()) {
3973 prefix(REX_RX);
3974 } else {
3975 prefix(REX_R);
3976 }
3977 }
3978 }
3979 }
3981 void Assembler::prefixq(Address adr, Register src) {
3982 if (src->encoding() < 8) {
3983 if (adr.base_needs_rex()) {
3984 if (adr.index_needs_rex()) {
3985 prefix(REX_WXB);
3986 } else {
3987 prefix(REX_WB);
3988 }
3989 } else {
3990 if (adr.index_needs_rex()) {
3991 prefix(REX_WX);
3992 } else {
3993 prefix(REX_W);
3994 }
3995 }
3996 } else {
3997 if (adr.base_needs_rex()) {
3998 if (adr.index_needs_rex()) {
3999 prefix(REX_WRXB);
4000 } else {
4001 prefix(REX_WRB);
4002 }
4003 } else {
4004 if (adr.index_needs_rex()) {
4005 prefix(REX_WRX);
4006 } else {
4007 prefix(REX_WR);
4008 }
4009 }
4010 }
4011 }
4013 void Assembler::prefix(Address adr, XMMRegister reg) {
4014 if (reg->encoding() < 8) {
4015 if (adr.base_needs_rex()) {
4016 if (adr.index_needs_rex()) {
4017 prefix(REX_XB);
4018 } else {
4019 prefix(REX_B);
4020 }
4021 } else {
4022 if (adr.index_needs_rex()) {
4023 prefix(REX_X);
4024 }
4025 }
4026 } else {
4027 if (adr.base_needs_rex()) {
4028 if (adr.index_needs_rex()) {
4029 prefix(REX_RXB);
4030 } else {
4031 prefix(REX_RB);
4032 }
4033 } else {
4034 if (adr.index_needs_rex()) {
4035 prefix(REX_RX);
4036 } else {
4037 prefix(REX_R);
4038 }
4039 }
4040 }
4041 }
4043 void Assembler::prefixq(Address adr, XMMRegister src) {
4044 if (src->encoding() < 8) {
4045 if (adr.base_needs_rex()) {
4046 if (adr.index_needs_rex()) {
4047 prefix(REX_WXB);
4048 } else {
4049 prefix(REX_WB);
4050 }
4051 } else {
4052 if (adr.index_needs_rex()) {
4053 prefix(REX_WX);
4054 } else {
4055 prefix(REX_W);
4056 }
4057 }
4058 } else {
4059 if (adr.base_needs_rex()) {
4060 if (adr.index_needs_rex()) {
4061 prefix(REX_WRXB);
4062 } else {
4063 prefix(REX_WRB);
4064 }
4065 } else {
4066 if (adr.index_needs_rex()) {
4067 prefix(REX_WRX);
4068 } else {
4069 prefix(REX_WR);
4070 }
4071 }
4072 }
4073 }
4075 void Assembler::adcq(Register dst, int32_t imm32) {
4076 (void) prefixq_and_encode(dst->encoding());
4077 emit_arith(0x81, 0xD0, dst, imm32);
4078 }
4080 void Assembler::adcq(Register dst, Address src) {
4081 InstructionMark im(this);
4082 prefixq(src, dst);
4083 emit_byte(0x13);
4084 emit_operand(dst, src);
4085 }
4087 void Assembler::adcq(Register dst, Register src) {
4088 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4089 emit_arith(0x13, 0xC0, dst, src);
4090 }
4092 void Assembler::addq(Address dst, int32_t imm32) {
4093 InstructionMark im(this);
4094 prefixq(dst);
4095 emit_arith_operand(0x81, rax, dst,imm32);
4096 }
4098 void Assembler::addq(Address dst, Register src) {
4099 InstructionMark im(this);
4100 prefixq(dst, src);
4101 emit_byte(0x01);
4102 emit_operand(src, dst);
4103 }
4105 void Assembler::addq(Register dst, int32_t imm32) {
4106 (void) prefixq_and_encode(dst->encoding());
4107 emit_arith(0x81, 0xC0, dst, imm32);
4108 }
4110 void Assembler::addq(Register dst, Address src) {
4111 InstructionMark im(this);
4112 prefixq(src, dst);
4113 emit_byte(0x03);
4114 emit_operand(dst, src);
4115 }
4117 void Assembler::addq(Register dst, Register src) {
4118 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4119 emit_arith(0x03, 0xC0, dst, src);
4120 }
4122 void Assembler::andq(Address dst, int32_t imm32) {
4123 InstructionMark im(this);
4124 prefixq(dst);
4125 emit_byte(0x81);
4126 emit_operand(rsp, dst, 4);
4127 emit_long(imm32);
4128 }
4130 void Assembler::andq(Register dst, int32_t imm32) {
4131 (void) prefixq_and_encode(dst->encoding());
4132 emit_arith(0x81, 0xE0, dst, imm32);
4133 }
4135 void Assembler::andq(Register dst, Address src) {
4136 InstructionMark im(this);
4137 prefixq(src, dst);
4138 emit_byte(0x23);
4139 emit_operand(dst, src);
4140 }
4142 void Assembler::andq(Register dst, Register src) {
4143 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4144 emit_arith(0x23, 0xC0, dst, src);
4145 }
4147 void Assembler::bsfq(Register dst, Register src) {
4148 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4149 emit_byte(0x0F);
4150 emit_byte(0xBC);
4151 emit_byte(0xC0 | encode);
4152 }
4154 void Assembler::bsrq(Register dst, Register src) {
4155 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4156 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4157 emit_byte(0x0F);
4158 emit_byte(0xBD);
4159 emit_byte(0xC0 | encode);
4160 }
4162 void Assembler::bswapq(Register reg) {
4163 int encode = prefixq_and_encode(reg->encoding());
4164 emit_byte(0x0F);
4165 emit_byte(0xC8 | encode);
4166 }
4168 void Assembler::cdqq() {
4169 prefix(REX_W);
4170 emit_byte(0x99);
4171 }
4173 void Assembler::clflush(Address adr) {
4174 prefix(adr);
4175 emit_byte(0x0F);
4176 emit_byte(0xAE);
4177 emit_operand(rdi, adr);
4178 }
4180 void Assembler::cmovq(Condition cc, Register dst, Register src) {
4181 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4182 emit_byte(0x0F);
4183 emit_byte(0x40 | cc);
4184 emit_byte(0xC0 | encode);
4185 }
4187 void Assembler::cmovq(Condition cc, Register dst, Address src) {
4188 InstructionMark im(this);
4189 prefixq(src, dst);
4190 emit_byte(0x0F);
4191 emit_byte(0x40 | cc);
4192 emit_operand(dst, src);
4193 }
4195 void Assembler::cmpq(Address dst, int32_t imm32) {
4196 InstructionMark im(this);
4197 prefixq(dst);
4198 emit_byte(0x81);
4199 emit_operand(rdi, dst, 4);
4200 emit_long(imm32);
4201 }
4203 void Assembler::cmpq(Register dst, int32_t imm32) {
4204 (void) prefixq_and_encode(dst->encoding());
4205 emit_arith(0x81, 0xF8, dst, imm32);
4206 }
4208 void Assembler::cmpq(Address dst, Register src) {
4209 InstructionMark im(this);
4210 prefixq(dst, src);
4211 emit_byte(0x3B);
4212 emit_operand(src, dst);
4213 }
4215 void Assembler::cmpq(Register dst, Register src) {
4216 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4217 emit_arith(0x3B, 0xC0, dst, src);
4218 }
4220 void Assembler::cmpq(Register dst, Address src) {
4221 InstructionMark im(this);
4222 prefixq(src, dst);
4223 emit_byte(0x3B);
4224 emit_operand(dst, src);
4225 }
4227 void Assembler::cmpxchgq(Register reg, Address adr) {
4228 InstructionMark im(this);
4229 prefixq(adr, reg);
4230 emit_byte(0x0F);
4231 emit_byte(0xB1);
4232 emit_operand(reg, adr);
4233 }
4235 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
4236 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4237 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
4238 emit_byte(0x2A);
4239 emit_byte(0xC0 | encode);
4240 }
4242 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
4243 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4244 InstructionMark im(this);
4245 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
4246 emit_byte(0x2A);
4247 emit_operand(dst, src);
4248 }
4250 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
4251 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4252 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
4253 emit_byte(0x2A);
4254 emit_byte(0xC0 | encode);
4255 }
4257 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
4258 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4259 InstructionMark im(this);
4260 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
4261 emit_byte(0x2A);
4262 emit_operand(dst, src);
4263 }
4265 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
4266 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4267 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
4268 emit_byte(0x2C);
4269 emit_byte(0xC0 | encode);
4270 }
4272 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
4273 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4274 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
4275 emit_byte(0x2C);
4276 emit_byte(0xC0 | encode);
4277 }
4279 void Assembler::decl(Register dst) {
4280 // Don't use it directly. Use MacroAssembler::decrementl() instead.
4281 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
4282 int encode = prefix_and_encode(dst->encoding());
4283 emit_byte(0xFF);
4284 emit_byte(0xC8 | encode);
4285 }
4287 void Assembler::decq(Register dst) {
4288 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4289 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4290 int encode = prefixq_and_encode(dst->encoding());
4291 emit_byte(0xFF);
4292 emit_byte(0xC8 | encode);
4293 }
4295 void Assembler::decq(Address dst) {
4296 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4297 InstructionMark im(this);
4298 prefixq(dst);
4299 emit_byte(0xFF);
4300 emit_operand(rcx, dst);
4301 }
4303 void Assembler::fxrstor(Address src) {
4304 prefixq(src);
4305 emit_byte(0x0F);
4306 emit_byte(0xAE);
4307 emit_operand(as_Register(1), src);
4308 }
4310 void Assembler::fxsave(Address dst) {
4311 prefixq(dst);
4312 emit_byte(0x0F);
4313 emit_byte(0xAE);
4314 emit_operand(as_Register(0), dst);
4315 }
4317 void Assembler::idivq(Register src) {
4318 int encode = prefixq_and_encode(src->encoding());
4319 emit_byte(0xF7);
4320 emit_byte(0xF8 | encode);
4321 }
4323 void Assembler::imulq(Register dst, Register src) {
4324 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4325 emit_byte(0x0F);
4326 emit_byte(0xAF);
4327 emit_byte(0xC0 | encode);
4328 }
4330 void Assembler::imulq(Register dst, Register src, int value) {
4331 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4332 if (is8bit(value)) {
4333 emit_byte(0x6B);
4334 emit_byte(0xC0 | encode);
4335 emit_byte(value & 0xFF);
4336 } else {
4337 emit_byte(0x69);
4338 emit_byte(0xC0 | encode);
4339 emit_long(value);
4340 }
4341 }
4343 void Assembler::incl(Register dst) {
4344 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4345 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4346 int encode = prefix_and_encode(dst->encoding());
4347 emit_byte(0xFF);
4348 emit_byte(0xC0 | encode);
4349 }
4351 void Assembler::incq(Register dst) {
4352 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4353 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4354 int encode = prefixq_and_encode(dst->encoding());
4355 emit_byte(0xFF);
4356 emit_byte(0xC0 | encode);
4357 }
4359 void Assembler::incq(Address dst) {
4360 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4361 InstructionMark im(this);
4362 prefixq(dst);
4363 emit_byte(0xFF);
4364 emit_operand(rax, dst);
4365 }
4367 void Assembler::lea(Register dst, Address src) {
4368 leaq(dst, src);
4369 }
4371 void Assembler::leaq(Register dst, Address src) {
4372 InstructionMark im(this);
4373 prefixq(src, dst);
4374 emit_byte(0x8D);
4375 emit_operand(dst, src);
4376 }
4378 void Assembler::mov64(Register dst, int64_t imm64) {
4379 InstructionMark im(this);
4380 int encode = prefixq_and_encode(dst->encoding());
4381 emit_byte(0xB8 | encode);
4382 emit_long64(imm64);
4383 }
4385 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
4386 InstructionMark im(this);
4387 int encode = prefixq_and_encode(dst->encoding());
4388 emit_byte(0xB8 | encode);
4389 emit_data64(imm64, rspec);
4390 }
4392 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4393 InstructionMark im(this);
4394 int encode = prefix_and_encode(dst->encoding());
4395 emit_byte(0xB8 | encode);
4396 emit_data((int)imm32, rspec, narrow_oop_operand);
4397 }
4399 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4400 InstructionMark im(this);
4401 prefix(dst);
4402 emit_byte(0xC7);
4403 emit_operand(rax, dst, 4);
4404 emit_data((int)imm32, rspec, narrow_oop_operand);
4405 }
4407 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
4408 InstructionMark im(this);
4409 int encode = prefix_and_encode(src1->encoding());
4410 emit_byte(0x81);
4411 emit_byte(0xF8 | encode);
4412 emit_data((int)imm32, rspec, narrow_oop_operand);
4413 }
4415 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
4416 InstructionMark im(this);
4417 prefix(src1);
4418 emit_byte(0x81);
4419 emit_operand(rax, src1, 4);
4420 emit_data((int)imm32, rspec, narrow_oop_operand);
4421 }
4423 void Assembler::lzcntq(Register dst, Register src) {
4424 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
4425 emit_byte(0xF3);
4426 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4427 emit_byte(0x0F);
4428 emit_byte(0xBD);
4429 emit_byte(0xC0 | encode);
4430 }
4432 void Assembler::movdq(XMMRegister dst, Register src) {
4433 // table D-1 says MMX/SSE2
4434 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4435 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
4436 emit_byte(0x6E);
4437 emit_byte(0xC0 | encode);
4438 }
4440 void Assembler::movdq(Register dst, XMMRegister src) {
4441 // table D-1 says MMX/SSE2
4442 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4443 // swap src/dst to get correct prefix
4444 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
4445 emit_byte(0x7E);
4446 emit_byte(0xC0 | encode);
4447 }
4449 void Assembler::movq(Register dst, Register src) {
4450 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4451 emit_byte(0x8B);
4452 emit_byte(0xC0 | encode);
4453 }
4455 void Assembler::movq(Register dst, Address src) {
4456 InstructionMark im(this);
4457 prefixq(src, dst);
4458 emit_byte(0x8B);
4459 emit_operand(dst, src);
4460 }
4462 void Assembler::movq(Address dst, Register src) {
4463 InstructionMark im(this);
4464 prefixq(dst, src);
4465 emit_byte(0x89);
4466 emit_operand(src, dst);
4467 }
4469 void Assembler::movsbq(Register dst, Address src) {
4470 InstructionMark im(this);
4471 prefixq(src, dst);
4472 emit_byte(0x0F);
4473 emit_byte(0xBE);
4474 emit_operand(dst, src);
4475 }
4477 void Assembler::movsbq(Register dst, Register src) {
4478 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4479 emit_byte(0x0F);
4480 emit_byte(0xBE);
4481 emit_byte(0xC0 | encode);
4482 }
4484 void Assembler::movslq(Register dst, int32_t imm32) {
4485 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
4486 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
4487 // as a result we shouldn't use until tested at runtime...
4488 ShouldNotReachHere();
4489 InstructionMark im(this);
4490 int encode = prefixq_and_encode(dst->encoding());
4491 emit_byte(0xC7 | encode);
4492 emit_long(imm32);
4493 }
4495 void Assembler::movslq(Address dst, int32_t imm32) {
4496 assert(is_simm32(imm32), "lost bits");
4497 InstructionMark im(this);
4498 prefixq(dst);
4499 emit_byte(0xC7);
4500 emit_operand(rax, dst, 4);
4501 emit_long(imm32);
4502 }
4504 void Assembler::movslq(Register dst, Address src) {
4505 InstructionMark im(this);
4506 prefixq(src, dst);
4507 emit_byte(0x63);
4508 emit_operand(dst, src);
4509 }
4511 void Assembler::movslq(Register dst, Register src) {
4512 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4513 emit_byte(0x63);
4514 emit_byte(0xC0 | encode);
4515 }
4517 void Assembler::movswq(Register dst, Address src) {
4518 InstructionMark im(this);
4519 prefixq(src, dst);
4520 emit_byte(0x0F);
4521 emit_byte(0xBF);
4522 emit_operand(dst, src);
4523 }
4525 void Assembler::movswq(Register dst, Register src) {
4526 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4527 emit_byte(0x0F);
4528 emit_byte(0xBF);
4529 emit_byte(0xC0 | encode);
4530 }
4532 void Assembler::movzbq(Register dst, Address src) {
4533 InstructionMark im(this);
4534 prefixq(src, dst);
4535 emit_byte(0x0F);
4536 emit_byte(0xB6);
4537 emit_operand(dst, src);
4538 }
4540 void Assembler::movzbq(Register dst, Register src) {
4541 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4542 emit_byte(0x0F);
4543 emit_byte(0xB6);
4544 emit_byte(0xC0 | encode);
4545 }
4547 void Assembler::movzwq(Register dst, Address src) {
4548 InstructionMark im(this);
4549 prefixq(src, dst);
4550 emit_byte(0x0F);
4551 emit_byte(0xB7);
4552 emit_operand(dst, src);
4553 }
4555 void Assembler::movzwq(Register dst, Register src) {
4556 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4557 emit_byte(0x0F);
4558 emit_byte(0xB7);
4559 emit_byte(0xC0 | encode);
4560 }
4562 void Assembler::negq(Register dst) {
4563 int encode = prefixq_and_encode(dst->encoding());
4564 emit_byte(0xF7);
4565 emit_byte(0xD8 | encode);
4566 }
4568 void Assembler::notq(Register dst) {
4569 int encode = prefixq_and_encode(dst->encoding());
4570 emit_byte(0xF7);
4571 emit_byte(0xD0 | encode);
4572 }
4574 void Assembler::orq(Address dst, int32_t imm32) {
4575 InstructionMark im(this);
4576 prefixq(dst);
4577 emit_byte(0x81);
4578 emit_operand(rcx, dst, 4);
4579 emit_long(imm32);
4580 }
4582 void Assembler::orq(Register dst, int32_t imm32) {
4583 (void) prefixq_and_encode(dst->encoding());
4584 emit_arith(0x81, 0xC8, dst, imm32);
4585 }
4587 void Assembler::orq(Register dst, Address src) {
4588 InstructionMark im(this);
4589 prefixq(src, dst);
4590 emit_byte(0x0B);
4591 emit_operand(dst, src);
4592 }
4594 void Assembler::orq(Register dst, Register src) {
4595 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4596 emit_arith(0x0B, 0xC0, dst, src);
4597 }
4599 void Assembler::popa() { // 64bit
4600 movq(r15, Address(rsp, 0));
4601 movq(r14, Address(rsp, wordSize));
4602 movq(r13, Address(rsp, 2 * wordSize));
4603 movq(r12, Address(rsp, 3 * wordSize));
4604 movq(r11, Address(rsp, 4 * wordSize));
4605 movq(r10, Address(rsp, 5 * wordSize));
4606 movq(r9, Address(rsp, 6 * wordSize));
4607 movq(r8, Address(rsp, 7 * wordSize));
4608 movq(rdi, Address(rsp, 8 * wordSize));
4609 movq(rsi, Address(rsp, 9 * wordSize));
4610 movq(rbp, Address(rsp, 10 * wordSize));
4611 // skip rsp
4612 movq(rbx, Address(rsp, 12 * wordSize));
4613 movq(rdx, Address(rsp, 13 * wordSize));
4614 movq(rcx, Address(rsp, 14 * wordSize));
4615 movq(rax, Address(rsp, 15 * wordSize));
4617 addq(rsp, 16 * wordSize);
4618 }
4620 void Assembler::popcntq(Register dst, Address src) {
4621 assert(VM_Version::supports_popcnt(), "must support");
4622 InstructionMark im(this);
4623 emit_byte(0xF3);
4624 prefixq(src, dst);
4625 emit_byte(0x0F);
4626 emit_byte(0xB8);
4627 emit_operand(dst, src);
4628 }
4630 void Assembler::popcntq(Register dst, Register src) {
4631 assert(VM_Version::supports_popcnt(), "must support");
4632 emit_byte(0xF3);
4633 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4634 emit_byte(0x0F);
4635 emit_byte(0xB8);
4636 emit_byte(0xC0 | encode);
4637 }
4639 void Assembler::popq(Address dst) {
4640 InstructionMark im(this);
4641 prefixq(dst);
4642 emit_byte(0x8F);
4643 emit_operand(rax, dst);
4644 }
4646 void Assembler::pusha() { // 64bit
4647 // we have to store original rsp. ABI says that 128 bytes
4648 // below rsp are local scratch.
4649 movq(Address(rsp, -5 * wordSize), rsp);
4651 subq(rsp, 16 * wordSize);
4653 movq(Address(rsp, 15 * wordSize), rax);
4654 movq(Address(rsp, 14 * wordSize), rcx);
4655 movq(Address(rsp, 13 * wordSize), rdx);
4656 movq(Address(rsp, 12 * wordSize), rbx);
4657 // skip rsp
4658 movq(Address(rsp, 10 * wordSize), rbp);
4659 movq(Address(rsp, 9 * wordSize), rsi);
4660 movq(Address(rsp, 8 * wordSize), rdi);
4661 movq(Address(rsp, 7 * wordSize), r8);
4662 movq(Address(rsp, 6 * wordSize), r9);
4663 movq(Address(rsp, 5 * wordSize), r10);
4664 movq(Address(rsp, 4 * wordSize), r11);
4665 movq(Address(rsp, 3 * wordSize), r12);
4666 movq(Address(rsp, 2 * wordSize), r13);
4667 movq(Address(rsp, wordSize), r14);
4668 movq(Address(rsp, 0), r15);
4669 }
4671 void Assembler::pushq(Address src) {
4672 InstructionMark im(this);
4673 prefixq(src);
4674 emit_byte(0xFF);
4675 emit_operand(rsi, src);
4676 }
4678 void Assembler::rclq(Register dst, int imm8) {
4679 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4680 int encode = prefixq_and_encode(dst->encoding());
4681 if (imm8 == 1) {
4682 emit_byte(0xD1);
4683 emit_byte(0xD0 | encode);
4684 } else {
4685 emit_byte(0xC1);
4686 emit_byte(0xD0 | encode);
4687 emit_byte(imm8);
4688 }
4689 }
4690 void Assembler::sarq(Register dst, int imm8) {
4691 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4692 int encode = prefixq_and_encode(dst->encoding());
4693 if (imm8 == 1) {
4694 emit_byte(0xD1);
4695 emit_byte(0xF8 | encode);
4696 } else {
4697 emit_byte(0xC1);
4698 emit_byte(0xF8 | encode);
4699 emit_byte(imm8);
4700 }
4701 }
4703 void Assembler::sarq(Register dst) {
4704 int encode = prefixq_and_encode(dst->encoding());
4705 emit_byte(0xD3);
4706 emit_byte(0xF8 | encode);
4707 }
4709 void Assembler::sbbq(Address dst, int32_t imm32) {
4710 InstructionMark im(this);
4711 prefixq(dst);
4712 emit_arith_operand(0x81, rbx, dst, imm32);
4713 }
4715 void Assembler::sbbq(Register dst, int32_t imm32) {
4716 (void) prefixq_and_encode(dst->encoding());
4717 emit_arith(0x81, 0xD8, dst, imm32);
4718 }
4720 void Assembler::sbbq(Register dst, Address src) {
4721 InstructionMark im(this);
4722 prefixq(src, dst);
4723 emit_byte(0x1B);
4724 emit_operand(dst, src);
4725 }
4727 void Assembler::sbbq(Register dst, Register src) {
4728 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4729 emit_arith(0x1B, 0xC0, dst, src);
4730 }
4732 void Assembler::shlq(Register dst, int imm8) {
4733 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4734 int encode = prefixq_and_encode(dst->encoding());
4735 if (imm8 == 1) {
4736 emit_byte(0xD1);
4737 emit_byte(0xE0 | encode);
4738 } else {
4739 emit_byte(0xC1);
4740 emit_byte(0xE0 | encode);
4741 emit_byte(imm8);
4742 }
4743 }
4745 void Assembler::shlq(Register dst) {
4746 int encode = prefixq_and_encode(dst->encoding());
4747 emit_byte(0xD3);
4748 emit_byte(0xE0 | encode);
4749 }
4751 void Assembler::shrq(Register dst, int imm8) {
4752 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4753 int encode = prefixq_and_encode(dst->encoding());
4754 emit_byte(0xC1);
4755 emit_byte(0xE8 | encode);
4756 emit_byte(imm8);
4757 }
4759 void Assembler::shrq(Register dst) {
4760 int encode = prefixq_and_encode(dst->encoding());
4761 emit_byte(0xD3);
4762 emit_byte(0xE8 | encode);
4763 }
4765 void Assembler::subq(Address dst, int32_t imm32) {
4766 InstructionMark im(this);
4767 prefixq(dst);
4768 emit_arith_operand(0x81, rbp, dst, imm32);
4769 }
4771 void Assembler::subq(Address dst, Register src) {
4772 InstructionMark im(this);
4773 prefixq(dst, src);
4774 emit_byte(0x29);
4775 emit_operand(src, dst);
4776 }
4778 void Assembler::subq(Register dst, int32_t imm32) {
4779 (void) prefixq_and_encode(dst->encoding());
4780 emit_arith(0x81, 0xE8, dst, imm32);
4781 }
4783 // Force generation of a 4 byte immediate value even if it fits into 8bit
4784 void Assembler::subq_imm32(Register dst, int32_t imm32) {
4785 (void) prefixq_and_encode(dst->encoding());
4786 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4787 }
4789 void Assembler::subq(Register dst, Address src) {
4790 InstructionMark im(this);
4791 prefixq(src, dst);
4792 emit_byte(0x2B);
4793 emit_operand(dst, src);
4794 }
4796 void Assembler::subq(Register dst, Register src) {
4797 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4798 emit_arith(0x2B, 0xC0, dst, src);
4799 }
4801 void Assembler::testq(Register dst, int32_t imm32) {
4802 // not using emit_arith because test
4803 // doesn't support sign-extension of
4804 // 8bit operands
4805 int encode = dst->encoding();
4806 if (encode == 0) {
4807 prefix(REX_W);
4808 emit_byte(0xA9);
4809 } else {
4810 encode = prefixq_and_encode(encode);
4811 emit_byte(0xF7);
4812 emit_byte(0xC0 | encode);
4813 }
4814 emit_long(imm32);
4815 }
4817 void Assembler::testq(Register dst, Register src) {
4818 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4819 emit_arith(0x85, 0xC0, dst, src);
4820 }
4822 void Assembler::xaddq(Address dst, Register src) {
4823 InstructionMark im(this);
4824 prefixq(dst, src);
4825 emit_byte(0x0F);
4826 emit_byte(0xC1);
4827 emit_operand(src, dst);
4828 }
4830 void Assembler::xchgq(Register dst, Address src) {
4831 InstructionMark im(this);
4832 prefixq(src, dst);
4833 emit_byte(0x87);
4834 emit_operand(dst, src);
4835 }
4837 void Assembler::xchgq(Register dst, Register src) {
4838 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4839 emit_byte(0x87);
4840 emit_byte(0xc0 | encode);
4841 }
4843 void Assembler::xorq(Register dst, Register src) {
4844 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4845 emit_arith(0x33, 0xC0, dst, src);
4846 }
4848 void Assembler::xorq(Register dst, Address src) {
4849 InstructionMark im(this);
4850 prefixq(src, dst);
4851 emit_byte(0x33);
4852 emit_operand(dst, src);
4853 }
4855 #endif // !LP64
4857 static Assembler::Condition reverse[] = {
4858 Assembler::noOverflow /* overflow = 0x0 */ ,
4859 Assembler::overflow /* noOverflow = 0x1 */ ,
4860 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
4861 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
4862 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
4863 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
4864 Assembler::above /* belowEqual = 0x6 */ ,
4865 Assembler::belowEqual /* above = 0x7 */ ,
4866 Assembler::positive /* negative = 0x8 */ ,
4867 Assembler::negative /* positive = 0x9 */ ,
4868 Assembler::noParity /* parity = 0xa */ ,
4869 Assembler::parity /* noParity = 0xb */ ,
4870 Assembler::greaterEqual /* less = 0xc */ ,
4871 Assembler::less /* greaterEqual = 0xd */ ,
4872 Assembler::greater /* lessEqual = 0xe */ ,
4873 Assembler::lessEqual /* greater = 0xf, */
4875 };
4878 // Implementation of MacroAssembler
4880 // First all the versions that have distinct versions depending on 32/64 bit
4881 // Unless the difference is trivial (1 line or so).
4883 #ifndef _LP64
4885 // 32bit versions
4887 Address MacroAssembler::as_Address(AddressLiteral adr) {
4888 return Address(adr.target(), adr.rspec());
4889 }
4891 Address MacroAssembler::as_Address(ArrayAddress adr) {
4892 return Address::make_array(adr);
4893 }
4895 int MacroAssembler::biased_locking_enter(Register lock_reg,
4896 Register obj_reg,
4897 Register swap_reg,
4898 Register tmp_reg,
4899 bool swap_reg_contains_mark,
4900 Label& done,
4901 Label* slow_case,
4902 BiasedLockingCounters* counters) {
4903 assert(UseBiasedLocking, "why call this otherwise?");
4904 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4905 assert_different_registers(lock_reg, obj_reg, swap_reg);
4907 if (PrintBiasedLockingStatistics && counters == NULL)
4908 counters = BiasedLocking::counters();
4910 bool need_tmp_reg = false;
4911 if (tmp_reg == noreg) {
4912 need_tmp_reg = true;
4913 tmp_reg = lock_reg;
4914 } else {
4915 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4916 }
4917 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4918 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4919 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4920 Address saved_mark_addr(lock_reg, 0);
4922 // Biased locking
4923 // See whether the lock is currently biased toward our thread and
4924 // whether the epoch is still valid
4925 // Note that the runtime guarantees sufficient alignment of JavaThread
4926 // pointers to allow age to be placed into low bits
4927 // First check to see whether biasing is even enabled for this object
4928 Label cas_label;
4929 int null_check_offset = -1;
4930 if (!swap_reg_contains_mark) {
4931 null_check_offset = offset();
4932 movl(swap_reg, mark_addr);
4933 }
4934 if (need_tmp_reg) {
4935 push(tmp_reg);
4936 }
4937 movl(tmp_reg, swap_reg);
4938 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4939 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4940 if (need_tmp_reg) {
4941 pop(tmp_reg);
4942 }
4943 jcc(Assembler::notEqual, cas_label);
4944 // The bias pattern is present in the object's header. Need to check
4945 // whether the bias owner and the epoch are both still current.
4946 // Note that because there is no current thread register on x86 we
4947 // need to store off the mark word we read out of the object to
4948 // avoid reloading it and needing to recheck invariants below. This
4949 // store is unfortunate but it makes the overall code shorter and
4950 // simpler.
4951 movl(saved_mark_addr, swap_reg);
4952 if (need_tmp_reg) {
4953 push(tmp_reg);
4954 }
4955 get_thread(tmp_reg);
4956 xorl(swap_reg, tmp_reg);
4957 if (swap_reg_contains_mark) {
4958 null_check_offset = offset();
4959 }
4960 movl(tmp_reg, klass_addr);
4961 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset()));
4962 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4963 if (need_tmp_reg) {
4964 pop(tmp_reg);
4965 }
4966 if (counters != NULL) {
4967 cond_inc32(Assembler::zero,
4968 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4969 }
4970 jcc(Assembler::equal, done);
4972 Label try_revoke_bias;
4973 Label try_rebias;
4975 // At this point we know that the header has the bias pattern and
4976 // that we are not the bias owner in the current epoch. We need to
4977 // figure out more details about the state of the header in order to
4978 // know what operations can be legally performed on the object's
4979 // header.
4981 // If the low three bits in the xor result aren't clear, that means
4982 // the prototype header is no longer biased and we have to revoke
4983 // the bias on this object.
4984 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4985 jcc(Assembler::notZero, try_revoke_bias);
4987 // Biasing is still enabled for this data type. See whether the
4988 // epoch of the current bias is still valid, meaning that the epoch
4989 // bits of the mark word are equal to the epoch bits of the
4990 // prototype header. (Note that the prototype header's epoch bits
4991 // only change at a safepoint.) If not, attempt to rebias the object
4992 // toward the current thread. Note that we must be absolutely sure
4993 // that the current epoch is invalid in order to do this because
4994 // otherwise the manipulations it performs on the mark word are
4995 // illegal.
4996 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4997 jcc(Assembler::notZero, try_rebias);
4999 // The epoch of the current bias is still valid but we know nothing
5000 // about the owner; it might be set or it might be clear. Try to
5001 // acquire the bias of the object using an atomic operation. If this
5002 // fails we will go in to the runtime to revoke the object's bias.
5003 // Note that we first construct the presumed unbiased header so we
5004 // don't accidentally blow away another thread's valid bias.
5005 movl(swap_reg, saved_mark_addr);
5006 andl(swap_reg,
5007 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5008 if (need_tmp_reg) {
5009 push(tmp_reg);
5010 }
5011 get_thread(tmp_reg);
5012 orl(tmp_reg, swap_reg);
5013 if (os::is_MP()) {
5014 lock();
5015 }
5016 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
5017 if (need_tmp_reg) {
5018 pop(tmp_reg);
5019 }
5020 // If the biasing toward our thread failed, this means that
5021 // another thread succeeded in biasing it toward itself and we
5022 // need to revoke that bias. The revocation will occur in the
5023 // interpreter runtime in the slow case.
5024 if (counters != NULL) {
5025 cond_inc32(Assembler::zero,
5026 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
5027 }
5028 if (slow_case != NULL) {
5029 jcc(Assembler::notZero, *slow_case);
5030 }
5031 jmp(done);
5033 bind(try_rebias);
5034 // At this point we know the epoch has expired, meaning that the
5035 // current "bias owner", if any, is actually invalid. Under these
5036 // circumstances _only_, we are allowed to use the current header's
5037 // value as the comparison value when doing the cas to acquire the
5038 // bias in the current epoch. In other words, we allow transfer of
5039 // the bias from one thread to another directly in this situation.
5040 //
5041 // FIXME: due to a lack of registers we currently blow away the age
5042 // bits in this situation. Should attempt to preserve them.
5043 if (need_tmp_reg) {
5044 push(tmp_reg);
5045 }
5046 get_thread(tmp_reg);
5047 movl(swap_reg, klass_addr);
5048 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset()));
5049 movl(swap_reg, saved_mark_addr);
5050 if (os::is_MP()) {
5051 lock();
5052 }
5053 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
5054 if (need_tmp_reg) {
5055 pop(tmp_reg);
5056 }
5057 // If the biasing toward our thread failed, then another thread
5058 // succeeded in biasing it toward itself and we need to revoke that
5059 // bias. The revocation will occur in the runtime in the slow case.
5060 if (counters != NULL) {
5061 cond_inc32(Assembler::zero,
5062 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
5063 }
5064 if (slow_case != NULL) {
5065 jcc(Assembler::notZero, *slow_case);
5066 }
5067 jmp(done);
5069 bind(try_revoke_bias);
5070 // The prototype mark in the klass doesn't have the bias bit set any
5071 // more, indicating that objects of this data type are not supposed
5072 // to be biased any more. We are going to try to reset the mark of
5073 // this object to the prototype value and fall through to the
5074 // CAS-based locking scheme. Note that if our CAS fails, it means
5075 // that another thread raced us for the privilege of revoking the
5076 // bias of this particular object, so it's okay to continue in the
5077 // normal locking code.
5078 //
5079 // FIXME: due to a lack of registers we currently blow away the age
5080 // bits in this situation. Should attempt to preserve them.
5081 movl(swap_reg, saved_mark_addr);
5082 if (need_tmp_reg) {
5083 push(tmp_reg);
5084 }
5085 movl(tmp_reg, klass_addr);
5086 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset()));
5087 if (os::is_MP()) {
5088 lock();
5089 }
5090 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
5091 if (need_tmp_reg) {
5092 pop(tmp_reg);
5093 }
5094 // Fall through to the normal CAS-based lock, because no matter what
5095 // the result of the above CAS, some thread must have succeeded in
5096 // removing the bias bit from the object's header.
5097 if (counters != NULL) {
5098 cond_inc32(Assembler::zero,
5099 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
5100 }
5102 bind(cas_label);
5104 return null_check_offset;
5105 }
5106 void MacroAssembler::call_VM_leaf_base(address entry_point,
5107 int number_of_arguments) {
5108 call(RuntimeAddress(entry_point));
5109 increment(rsp, number_of_arguments * wordSize);
5110 }
5112 void MacroAssembler::cmpoop(Address src1, jobject obj) {
5113 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
5114 }
5116 void MacroAssembler::cmpoop(Register src1, jobject obj) {
5117 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
5118 }
5120 void MacroAssembler::extend_sign(Register hi, Register lo) {
5121 // According to Intel Doc. AP-526, "Integer Divide", p.18.
5122 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
5123 cdql();
5124 } else {
5125 movl(hi, lo);
5126 sarl(hi, 31);
5127 }
5128 }
5130 void MacroAssembler::jC2(Register tmp, Label& L) {
5131 // set parity bit if FPU flag C2 is set (via rax)
5132 save_rax(tmp);
5133 fwait(); fnstsw_ax();
5134 sahf();
5135 restore_rax(tmp);
5136 // branch
5137 jcc(Assembler::parity, L);
5138 }
5140 void MacroAssembler::jnC2(Register tmp, Label& L) {
5141 // set parity bit if FPU flag C2 is set (via rax)
5142 save_rax(tmp);
5143 fwait(); fnstsw_ax();
5144 sahf();
5145 restore_rax(tmp);
5146 // branch
5147 jcc(Assembler::noParity, L);
5148 }
5150 // 32bit can do a case table jump in one instruction but we no longer allow the base
5151 // to be installed in the Address class
5152 void MacroAssembler::jump(ArrayAddress entry) {
5153 jmp(as_Address(entry));
5154 }
5156 // Note: y_lo will be destroyed
5157 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5158 // Long compare for Java (semantics as described in JVM spec.)
5159 Label high, low, done;
5161 cmpl(x_hi, y_hi);
5162 jcc(Assembler::less, low);
5163 jcc(Assembler::greater, high);
5164 // x_hi is the return register
5165 xorl(x_hi, x_hi);
5166 cmpl(x_lo, y_lo);
5167 jcc(Assembler::below, low);
5168 jcc(Assembler::equal, done);
5170 bind(high);
5171 xorl(x_hi, x_hi);
5172 increment(x_hi);
5173 jmp(done);
5175 bind(low);
5176 xorl(x_hi, x_hi);
5177 decrementl(x_hi);
5179 bind(done);
5180 }
5182 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5183 mov_literal32(dst, (int32_t)src.target(), src.rspec());
5184 }
5186 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5187 // leal(dst, as_Address(adr));
5188 // see note in movl as to why we must use a move
5189 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
5190 }
5192 void MacroAssembler::leave() {
5193 mov(rsp, rbp);
5194 pop(rbp);
5195 }
5197 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
5198 // Multiplication of two Java long values stored on the stack
5199 // as illustrated below. Result is in rdx:rax.
5200 //
5201 // rsp ---> [ ?? ] \ \
5202 // .... | y_rsp_offset |
5203 // [ y_lo ] / (in bytes) | x_rsp_offset
5204 // [ y_hi ] | (in bytes)
5205 // .... |
5206 // [ x_lo ] /
5207 // [ x_hi ]
5208 // ....
5209 //
5210 // Basic idea: lo(result) = lo(x_lo * y_lo)
5211 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
5212 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
5213 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
5214 Label quick;
5215 // load x_hi, y_hi and check if quick
5216 // multiplication is possible
5217 movl(rbx, x_hi);
5218 movl(rcx, y_hi);
5219 movl(rax, rbx);
5220 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
5221 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
5222 // do full multiplication
5223 // 1st step
5224 mull(y_lo); // x_hi * y_lo
5225 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
5226 // 2nd step
5227 movl(rax, x_lo);
5228 mull(rcx); // x_lo * y_hi
5229 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
5230 // 3rd step
5231 bind(quick); // note: rbx, = 0 if quick multiply!
5232 movl(rax, x_lo);
5233 mull(y_lo); // x_lo * y_lo
5234 addl(rdx, rbx); // correct hi(x_lo * y_lo)
5235 }
5237 void MacroAssembler::lneg(Register hi, Register lo) {
5238 negl(lo);
5239 adcl(hi, 0);
5240 negl(hi);
5241 }
5243 void MacroAssembler::lshl(Register hi, Register lo) {
5244 // Java shift left long support (semantics as described in JVM spec., p.305)
5245 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
5246 // shift value is in rcx !
5247 assert(hi != rcx, "must not use rcx");
5248 assert(lo != rcx, "must not use rcx");
5249 const Register s = rcx; // shift count
5250 const int n = BitsPerWord;
5251 Label L;
5252 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
5253 cmpl(s, n); // if (s < n)
5254 jcc(Assembler::less, L); // else (s >= n)
5255 movl(hi, lo); // x := x << n
5256 xorl(lo, lo);
5257 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
5258 bind(L); // s (mod n) < n
5259 shldl(hi, lo); // x := x << s
5260 shll(lo);
5261 }
5264 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
5265 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
5266 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
5267 assert(hi != rcx, "must not use rcx");
5268 assert(lo != rcx, "must not use rcx");
5269 const Register s = rcx; // shift count
5270 const int n = BitsPerWord;
5271 Label L;
5272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
5273 cmpl(s, n); // if (s < n)
5274 jcc(Assembler::less, L); // else (s >= n)
5275 movl(lo, hi); // x := x >> n
5276 if (sign_extension) sarl(hi, 31);
5277 else xorl(hi, hi);
5278 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
5279 bind(L); // s (mod n) < n
5280 shrdl(lo, hi); // x := x >> s
5281 if (sign_extension) sarl(hi);
5282 else shrl(hi);
5283 }
5285 void MacroAssembler::movoop(Register dst, jobject obj) {
5286 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
5287 }
5289 void MacroAssembler::movoop(Address dst, jobject obj) {
5290 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
5291 }
5293 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5294 if (src.is_lval()) {
5295 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
5296 } else {
5297 movl(dst, as_Address(src));
5298 }
5299 }
5301 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5302 movl(as_Address(dst), src);
5303 }
5305 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5306 movl(dst, as_Address(src));
5307 }
5309 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5310 void MacroAssembler::movptr(Address dst, intptr_t src) {
5311 movl(dst, src);
5312 }
5315 void MacroAssembler::pop_callee_saved_registers() {
5316 pop(rcx);
5317 pop(rdx);
5318 pop(rdi);
5319 pop(rsi);
5320 }
5322 void MacroAssembler::pop_fTOS() {
5323 fld_d(Address(rsp, 0));
5324 addl(rsp, 2 * wordSize);
5325 }
5327 void MacroAssembler::push_callee_saved_registers() {
5328 push(rsi);
5329 push(rdi);
5330 push(rdx);
5331 push(rcx);
5332 }
5334 void MacroAssembler::push_fTOS() {
5335 subl(rsp, 2 * wordSize);
5336 fstp_d(Address(rsp, 0));
5337 }
5340 void MacroAssembler::pushoop(jobject obj) {
5341 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
5342 }
5345 void MacroAssembler::pushptr(AddressLiteral src) {
5346 if (src.is_lval()) {
5347 push_literal32((int32_t)src.target(), src.rspec());
5348 } else {
5349 pushl(as_Address(src));
5350 }
5351 }
5353 void MacroAssembler::set_word_if_not_zero(Register dst) {
5354 xorl(dst, dst);
5355 set_byte_if_not_zero(dst);
5356 }
5358 static void pass_arg0(MacroAssembler* masm, Register arg) {
5359 masm->push(arg);
5360 }
5362 static void pass_arg1(MacroAssembler* masm, Register arg) {
5363 masm->push(arg);
5364 }
5366 static void pass_arg2(MacroAssembler* masm, Register arg) {
5367 masm->push(arg);
5368 }
5370 static void pass_arg3(MacroAssembler* masm, Register arg) {
5371 masm->push(arg);
5372 }
5374 #ifndef PRODUCT
5375 extern "C" void findpc(intptr_t x);
5376 #endif
5378 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
5379 // In order to get locks to work, we need to fake a in_VM state
5380 JavaThread* thread = JavaThread::current();
5381 JavaThreadState saved_state = thread->thread_state();
5382 thread->set_thread_state(_thread_in_vm);
5383 if (ShowMessageBoxOnError) {
5384 JavaThread* thread = JavaThread::current();
5385 JavaThreadState saved_state = thread->thread_state();
5386 thread->set_thread_state(_thread_in_vm);
5387 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5388 ttyLocker ttyl;
5389 BytecodeCounter::print();
5390 }
5391 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5392 // This is the value of eip which points to where verify_oop will return.
5393 if (os::message_box(msg, "Execution stopped, print registers?")) {
5394 ttyLocker ttyl;
5395 tty->print_cr("eip = 0x%08x", eip);
5396 #ifndef PRODUCT
5397 if ((WizardMode || Verbose) && PrintMiscellaneous) {
5398 tty->cr();
5399 findpc(eip);
5400 tty->cr();
5401 }
5402 #endif
5403 tty->print_cr("rax = 0x%08x", rax);
5404 tty->print_cr("rbx = 0x%08x", rbx);
5405 tty->print_cr("rcx = 0x%08x", rcx);
5406 tty->print_cr("rdx = 0x%08x", rdx);
5407 tty->print_cr("rdi = 0x%08x", rdi);
5408 tty->print_cr("rsi = 0x%08x", rsi);
5409 tty->print_cr("rbp = 0x%08x", rbp);
5410 tty->print_cr("rsp = 0x%08x", rsp);
5411 BREAKPOINT;
5412 assert(false, "start up GDB");
5413 }
5414 } else {
5415 ttyLocker ttyl;
5416 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
5417 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
5418 }
5419 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5420 }
5422 void MacroAssembler::stop(const char* msg) {
5423 ExternalAddress message((address)msg);
5424 // push address of message
5425 pushptr(message.addr());
5426 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5427 pusha(); // push registers
5428 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
5429 hlt();
5430 }
5432 void MacroAssembler::warn(const char* msg) {
5433 push_CPU_state();
5435 ExternalAddress message((address) msg);
5436 // push address of message
5437 pushptr(message.addr());
5439 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
5440 addl(rsp, wordSize); // discard argument
5441 pop_CPU_state();
5442 }
5444 #else // _LP64
5446 // 64 bit versions
5448 Address MacroAssembler::as_Address(AddressLiteral adr) {
5449 // amd64 always does this as a pc-rel
5450 // we can be absolute or disp based on the instruction type
5451 // jmp/call are displacements others are absolute
5452 assert(!adr.is_lval(), "must be rval");
5453 assert(reachable(adr), "must be");
5454 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
5456 }
5458 Address MacroAssembler::as_Address(ArrayAddress adr) {
5459 AddressLiteral base = adr.base();
5460 lea(rscratch1, base);
5461 Address index = adr.index();
5462 assert(index._disp == 0, "must not have disp"); // maybe it can?
5463 Address array(rscratch1, index._index, index._scale, index._disp);
5464 return array;
5465 }
5467 int MacroAssembler::biased_locking_enter(Register lock_reg,
5468 Register obj_reg,
5469 Register swap_reg,
5470 Register tmp_reg,
5471 bool swap_reg_contains_mark,
5472 Label& done,
5473 Label* slow_case,
5474 BiasedLockingCounters* counters) {
5475 assert(UseBiasedLocking, "why call this otherwise?");
5476 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
5477 assert(tmp_reg != noreg, "tmp_reg must be supplied");
5478 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5479 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5480 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5481 Address saved_mark_addr(lock_reg, 0);
5483 if (PrintBiasedLockingStatistics && counters == NULL)
5484 counters = BiasedLocking::counters();
5486 // Biased locking
5487 // See whether the lock is currently biased toward our thread and
5488 // whether the epoch is still valid
5489 // Note that the runtime guarantees sufficient alignment of JavaThread
5490 // pointers to allow age to be placed into low bits
5491 // First check to see whether biasing is even enabled for this object
5492 Label cas_label;
5493 int null_check_offset = -1;
5494 if (!swap_reg_contains_mark) {
5495 null_check_offset = offset();
5496 movq(swap_reg, mark_addr);
5497 }
5498 movq(tmp_reg, swap_reg);
5499 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5500 cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
5501 jcc(Assembler::notEqual, cas_label);
5502 // The bias pattern is present in the object's header. Need to check
5503 // whether the bias owner and the epoch are both still current.
5504 load_prototype_header(tmp_reg, obj_reg);
5505 orq(tmp_reg, r15_thread);
5506 xorq(tmp_reg, swap_reg);
5507 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
5508 if (counters != NULL) {
5509 cond_inc32(Assembler::zero,
5510 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5511 }
5512 jcc(Assembler::equal, done);
5514 Label try_revoke_bias;
5515 Label try_rebias;
5517 // At this point we know that the header has the bias pattern and
5518 // that we are not the bias owner in the current epoch. We need to
5519 // figure out more details about the state of the header in order to
5520 // know what operations can be legally performed on the object's
5521 // header.
5523 // If the low three bits in the xor result aren't clear, that means
5524 // the prototype header is no longer biased and we have to revoke
5525 // the bias on this object.
5526 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5527 jcc(Assembler::notZero, try_revoke_bias);
5529 // Biasing is still enabled for this data type. See whether the
5530 // epoch of the current bias is still valid, meaning that the epoch
5531 // bits of the mark word are equal to the epoch bits of the
5532 // prototype header. (Note that the prototype header's epoch bits
5533 // only change at a safepoint.) If not, attempt to rebias the object
5534 // toward the current thread. Note that we must be absolutely sure
5535 // that the current epoch is invalid in order to do this because
5536 // otherwise the manipulations it performs on the mark word are
5537 // illegal.
5538 testq(tmp_reg, markOopDesc::epoch_mask_in_place);
5539 jcc(Assembler::notZero, try_rebias);
5541 // The epoch of the current bias is still valid but we know nothing
5542 // about the owner; it might be set or it might be clear. Try to
5543 // acquire the bias of the object using an atomic operation. If this
5544 // fails we will go in to the runtime to revoke the object's bias.
5545 // Note that we first construct the presumed unbiased header so we
5546 // don't accidentally blow away another thread's valid bias.
5547 andq(swap_reg,
5548 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5549 movq(tmp_reg, swap_reg);
5550 orq(tmp_reg, r15_thread);
5551 if (os::is_MP()) {
5552 lock();
5553 }
5554 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5555 // If the biasing toward our thread failed, this means that
5556 // another thread succeeded in biasing it toward itself and we
5557 // need to revoke that bias. The revocation will occur in the
5558 // interpreter runtime in the slow case.
5559 if (counters != NULL) {
5560 cond_inc32(Assembler::zero,
5561 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5562 }
5563 if (slow_case != NULL) {
5564 jcc(Assembler::notZero, *slow_case);
5565 }
5566 jmp(done);
5568 bind(try_rebias);
5569 // At this point we know the epoch has expired, meaning that the
5570 // current "bias owner", if any, is actually invalid. Under these
5571 // circumstances _only_, we are allowed to use the current header's
5572 // value as the comparison value when doing the cas to acquire the
5573 // bias in the current epoch. In other words, we allow transfer of
5574 // the bias from one thread to another directly in this situation.
5575 //
5576 // FIXME: due to a lack of registers we currently blow away the age
5577 // bits in this situation. Should attempt to preserve them.
5578 load_prototype_header(tmp_reg, obj_reg);
5579 orq(tmp_reg, r15_thread);
5580 if (os::is_MP()) {
5581 lock();
5582 }
5583 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5584 // If the biasing toward our thread failed, then another thread
5585 // succeeded in biasing it toward itself and we need to revoke that
5586 // bias. The revocation will occur in the runtime in the slow case.
5587 if (counters != NULL) {
5588 cond_inc32(Assembler::zero,
5589 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
5590 }
5591 if (slow_case != NULL) {
5592 jcc(Assembler::notZero, *slow_case);
5593 }
5594 jmp(done);
5596 bind(try_revoke_bias);
5597 // The prototype mark in the klass doesn't have the bias bit set any
5598 // more, indicating that objects of this data type are not supposed
5599 // to be biased any more. We are going to try to reset the mark of
5600 // this object to the prototype value and fall through to the
5601 // CAS-based locking scheme. Note that if our CAS fails, it means
5602 // that another thread raced us for the privilege of revoking the
5603 // bias of this particular object, so it's okay to continue in the
5604 // normal locking code.
5605 //
5606 // FIXME: due to a lack of registers we currently blow away the age
5607 // bits in this situation. Should attempt to preserve them.
5608 load_prototype_header(tmp_reg, obj_reg);
5609 if (os::is_MP()) {
5610 lock();
5611 }
5612 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5613 // Fall through to the normal CAS-based lock, because no matter what
5614 // the result of the above CAS, some thread must have succeeded in
5615 // removing the bias bit from the object's header.
5616 if (counters != NULL) {
5617 cond_inc32(Assembler::zero,
5618 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
5619 }
5621 bind(cas_label);
5623 return null_check_offset;
5624 }
5626 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
5627 Label L, E;
5629 #ifdef _WIN64
5630 // Windows always allocates space for it's register args
5631 assert(num_args <= 4, "only register arguments supported");
5632 subq(rsp, frame::arg_reg_save_area_bytes);
5633 #endif
5635 // Align stack if necessary
5636 testl(rsp, 15);
5637 jcc(Assembler::zero, L);
5639 subq(rsp, 8);
5640 {
5641 call(RuntimeAddress(entry_point));
5642 }
5643 addq(rsp, 8);
5644 jmp(E);
5646 bind(L);
5647 {
5648 call(RuntimeAddress(entry_point));
5649 }
5651 bind(E);
5653 #ifdef _WIN64
5654 // restore stack pointer
5655 addq(rsp, frame::arg_reg_save_area_bytes);
5656 #endif
5658 }
5660 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
5661 assert(!src2.is_lval(), "should use cmpptr");
5663 if (reachable(src2)) {
5664 cmpq(src1, as_Address(src2));
5665 } else {
5666 lea(rscratch1, src2);
5667 Assembler::cmpq(src1, Address(rscratch1, 0));
5668 }
5669 }
5671 int MacroAssembler::corrected_idivq(Register reg) {
5672 // Full implementation of Java ldiv and lrem; checks for special
5673 // case as described in JVM spec., p.243 & p.271. The function
5674 // returns the (pc) offset of the idivl instruction - may be needed
5675 // for implicit exceptions.
5676 //
5677 // normal case special case
5678 //
5679 // input : rax: dividend min_long
5680 // reg: divisor (may not be eax/edx) -1
5681 //
5682 // output: rax: quotient (= rax idiv reg) min_long
5683 // rdx: remainder (= rax irem reg) 0
5684 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
5685 static const int64_t min_long = 0x8000000000000000;
5686 Label normal_case, special_case;
5688 // check for special case
5689 cmp64(rax, ExternalAddress((address) &min_long));
5690 jcc(Assembler::notEqual, normal_case);
5691 xorl(rdx, rdx); // prepare rdx for possible special case (where
5692 // remainder = 0)
5693 cmpq(reg, -1);
5694 jcc(Assembler::equal, special_case);
5696 // handle normal case
5697 bind(normal_case);
5698 cdqq();
5699 int idivq_offset = offset();
5700 idivq(reg);
5702 // normal and special case exit
5703 bind(special_case);
5705 return idivq_offset;
5706 }
5708 void MacroAssembler::decrementq(Register reg, int value) {
5709 if (value == min_jint) { subq(reg, value); return; }
5710 if (value < 0) { incrementq(reg, -value); return; }
5711 if (value == 0) { ; return; }
5712 if (value == 1 && UseIncDec) { decq(reg) ; return; }
5713 /* else */ { subq(reg, value) ; return; }
5714 }
5716 void MacroAssembler::decrementq(Address dst, int value) {
5717 if (value == min_jint) { subq(dst, value); return; }
5718 if (value < 0) { incrementq(dst, -value); return; }
5719 if (value == 0) { ; return; }
5720 if (value == 1 && UseIncDec) { decq(dst) ; return; }
5721 /* else */ { subq(dst, value) ; return; }
5722 }
5724 void MacroAssembler::incrementq(Register reg, int value) {
5725 if (value == min_jint) { addq(reg, value); return; }
5726 if (value < 0) { decrementq(reg, -value); return; }
5727 if (value == 0) { ; return; }
5728 if (value == 1 && UseIncDec) { incq(reg) ; return; }
5729 /* else */ { addq(reg, value) ; return; }
5730 }
5732 void MacroAssembler::incrementq(Address dst, int value) {
5733 if (value == min_jint) { addq(dst, value); return; }
5734 if (value < 0) { decrementq(dst, -value); return; }
5735 if (value == 0) { ; return; }
5736 if (value == 1 && UseIncDec) { incq(dst) ; return; }
5737 /* else */ { addq(dst, value) ; return; }
5738 }
5740 // 32bit can do a case table jump in one instruction but we no longer allow the base
5741 // to be installed in the Address class
5742 void MacroAssembler::jump(ArrayAddress entry) {
5743 lea(rscratch1, entry.base());
5744 Address dispatch = entry.index();
5745 assert(dispatch._base == noreg, "must be");
5746 dispatch._base = rscratch1;
5747 jmp(dispatch);
5748 }
5750 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5751 ShouldNotReachHere(); // 64bit doesn't use two regs
5752 cmpq(x_lo, y_lo);
5753 }
5755 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5756 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5757 }
5759 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5760 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
5761 movptr(dst, rscratch1);
5762 }
5764 void MacroAssembler::leave() {
5765 // %%% is this really better? Why not on 32bit too?
5766 emit_byte(0xC9); // LEAVE
5767 }
5769 void MacroAssembler::lneg(Register hi, Register lo) {
5770 ShouldNotReachHere(); // 64bit doesn't use two regs
5771 negq(lo);
5772 }
5774 void MacroAssembler::movoop(Register dst, jobject obj) {
5775 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5776 }
5778 void MacroAssembler::movoop(Address dst, jobject obj) {
5779 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5780 movq(dst, rscratch1);
5781 }
5783 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5784 if (src.is_lval()) {
5785 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5786 } else {
5787 if (reachable(src)) {
5788 movq(dst, as_Address(src));
5789 } else {
5790 lea(rscratch1, src);
5791 movq(dst, Address(rscratch1,0));
5792 }
5793 }
5794 }
5796 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5797 movq(as_Address(dst), src);
5798 }
5800 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5801 movq(dst, as_Address(src));
5802 }
5804 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5805 void MacroAssembler::movptr(Address dst, intptr_t src) {
5806 mov64(rscratch1, src);
5807 movq(dst, rscratch1);
5808 }
5810 // These are mostly for initializing NULL
5811 void MacroAssembler::movptr(Address dst, int32_t src) {
5812 movslq(dst, src);
5813 }
5815 void MacroAssembler::movptr(Register dst, int32_t src) {
5816 mov64(dst, (intptr_t)src);
5817 }
5819 void MacroAssembler::pushoop(jobject obj) {
5820 movoop(rscratch1, obj);
5821 push(rscratch1);
5822 }
5824 void MacroAssembler::pushptr(AddressLiteral src) {
5825 lea(rscratch1, src);
5826 if (src.is_lval()) {
5827 push(rscratch1);
5828 } else {
5829 pushq(Address(rscratch1, 0));
5830 }
5831 }
5833 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
5834 bool clear_pc) {
5835 // we must set sp to zero to clear frame
5836 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
5837 // must clear fp, so that compiled frames are not confused; it is
5838 // possible that we need it only for debugging
5839 if (clear_fp) {
5840 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
5841 }
5843 if (clear_pc) {
5844 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
5845 }
5846 }
5848 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
5849 Register last_java_fp,
5850 address last_java_pc) {
5851 // determine last_java_sp register
5852 if (!last_java_sp->is_valid()) {
5853 last_java_sp = rsp;
5854 }
5856 // last_java_fp is optional
5857 if (last_java_fp->is_valid()) {
5858 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
5859 last_java_fp);
5860 }
5862 // last_java_pc is optional
5863 if (last_java_pc != NULL) {
5864 Address java_pc(r15_thread,
5865 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
5866 lea(rscratch1, InternalAddress(last_java_pc));
5867 movptr(java_pc, rscratch1);
5868 }
5870 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
5871 }
5873 static void pass_arg0(MacroAssembler* masm, Register arg) {
5874 if (c_rarg0 != arg ) {
5875 masm->mov(c_rarg0, arg);
5876 }
5877 }
5879 static void pass_arg1(MacroAssembler* masm, Register arg) {
5880 if (c_rarg1 != arg ) {
5881 masm->mov(c_rarg1, arg);
5882 }
5883 }
5885 static void pass_arg2(MacroAssembler* masm, Register arg) {
5886 if (c_rarg2 != arg ) {
5887 masm->mov(c_rarg2, arg);
5888 }
5889 }
5891 static void pass_arg3(MacroAssembler* masm, Register arg) {
5892 if (c_rarg3 != arg ) {
5893 masm->mov(c_rarg3, arg);
5894 }
5895 }
5897 void MacroAssembler::stop(const char* msg) {
5898 address rip = pc();
5899 pusha(); // get regs on stack
5900 lea(c_rarg0, ExternalAddress((address) msg));
5901 lea(c_rarg1, InternalAddress(rip));
5902 movq(c_rarg2, rsp); // pass pointer to regs array
5903 andq(rsp, -16); // align stack as required by ABI
5904 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
5905 hlt();
5906 }
5908 void MacroAssembler::warn(const char* msg) {
5909 push(rsp);
5910 andq(rsp, -16); // align stack as required by push_CPU_state and call
5912 push_CPU_state(); // keeps alignment at 16 bytes
5913 lea(c_rarg0, ExternalAddress((address) msg));
5914 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
5915 pop_CPU_state();
5916 pop(rsp);
5917 }
5919 #ifndef PRODUCT
5920 extern "C" void findpc(intptr_t x);
5921 #endif
5923 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
5924 // In order to get locks to work, we need to fake a in_VM state
5925 if (ShowMessageBoxOnError ) {
5926 JavaThread* thread = JavaThread::current();
5927 JavaThreadState saved_state = thread->thread_state();
5928 thread->set_thread_state(_thread_in_vm);
5929 #ifndef PRODUCT
5930 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5931 ttyLocker ttyl;
5932 BytecodeCounter::print();
5933 }
5934 #endif
5935 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5936 // XXX correct this offset for amd64
5937 // This is the value of eip which points to where verify_oop will return.
5938 if (os::message_box(msg, "Execution stopped, print registers?")) {
5939 ttyLocker ttyl;
5940 tty->print_cr("rip = 0x%016lx", pc);
5941 #ifndef PRODUCT
5942 tty->cr();
5943 findpc(pc);
5944 tty->cr();
5945 #endif
5946 tty->print_cr("rax = 0x%016lx", regs[15]);
5947 tty->print_cr("rbx = 0x%016lx", regs[12]);
5948 tty->print_cr("rcx = 0x%016lx", regs[14]);
5949 tty->print_cr("rdx = 0x%016lx", regs[13]);
5950 tty->print_cr("rdi = 0x%016lx", regs[8]);
5951 tty->print_cr("rsi = 0x%016lx", regs[9]);
5952 tty->print_cr("rbp = 0x%016lx", regs[10]);
5953 tty->print_cr("rsp = 0x%016lx", regs[11]);
5954 tty->print_cr("r8 = 0x%016lx", regs[7]);
5955 tty->print_cr("r9 = 0x%016lx", regs[6]);
5956 tty->print_cr("r10 = 0x%016lx", regs[5]);
5957 tty->print_cr("r11 = 0x%016lx", regs[4]);
5958 tty->print_cr("r12 = 0x%016lx", regs[3]);
5959 tty->print_cr("r13 = 0x%016lx", regs[2]);
5960 tty->print_cr("r14 = 0x%016lx", regs[1]);
5961 tty->print_cr("r15 = 0x%016lx", regs[0]);
5962 BREAKPOINT;
5963 }
5964 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5965 } else {
5966 ttyLocker ttyl;
5967 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
5968 msg);
5969 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
5970 }
5971 }
5973 #endif // _LP64
5975 // Now versions that are common to 32/64 bit
5977 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5978 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5979 }
5981 void MacroAssembler::addptr(Register dst, Register src) {
5982 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5983 }
5985 void MacroAssembler::addptr(Address dst, Register src) {
5986 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5987 }
5989 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
5990 if (reachable(src)) {
5991 Assembler::addsd(dst, as_Address(src));
5992 } else {
5993 lea(rscratch1, src);
5994 Assembler::addsd(dst, Address(rscratch1, 0));
5995 }
5996 }
5998 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
5999 if (reachable(src)) {
6000 addss(dst, as_Address(src));
6001 } else {
6002 lea(rscratch1, src);
6003 addss(dst, Address(rscratch1, 0));
6004 }
6005 }
6007 void MacroAssembler::align(int modulus) {
6008 if (offset() % modulus != 0) {
6009 nop(modulus - (offset() % modulus));
6010 }
6011 }
6013 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
6014 // Used in sign-masking with aligned address.
6015 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
6016 if (reachable(src)) {
6017 Assembler::andpd(dst, as_Address(src));
6018 } else {
6019 lea(rscratch1, src);
6020 Assembler::andpd(dst, Address(rscratch1, 0));
6021 }
6022 }
6024 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
6025 // Used in sign-masking with aligned address.
6026 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
6027 if (reachable(src)) {
6028 Assembler::andps(dst, as_Address(src));
6029 } else {
6030 lea(rscratch1, src);
6031 Assembler::andps(dst, Address(rscratch1, 0));
6032 }
6033 }
6035 void MacroAssembler::andptr(Register dst, int32_t imm32) {
6036 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
6037 }
6039 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
6040 pushf();
6041 if (os::is_MP())
6042 lock();
6043 incrementl(counter_addr);
6044 popf();
6045 }
6047 // Writes to stack successive pages until offset reached to check for
6048 // stack overflow + shadow pages. This clobbers tmp.
6049 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
6050 movptr(tmp, rsp);
6051 // Bang stack for total size given plus shadow page size.
6052 // Bang one page at a time because large size can bang beyond yellow and
6053 // red zones.
6054 Label loop;
6055 bind(loop);
6056 movl(Address(tmp, (-os::vm_page_size())), size );
6057 subptr(tmp, os::vm_page_size());
6058 subl(size, os::vm_page_size());
6059 jcc(Assembler::greater, loop);
6061 // Bang down shadow pages too.
6062 // The -1 because we already subtracted 1 page.
6063 for (int i = 0; i< StackShadowPages-1; i++) {
6064 // this could be any sized move but this is can be a debugging crumb
6065 // so the bigger the better.
6066 movptr(Address(tmp, (-i*os::vm_page_size())), size );
6067 }
6068 }
6070 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
6071 assert(UseBiasedLocking, "why call this otherwise?");
6073 // Check for biased locking unlock case, which is a no-op
6074 // Note: we do not have to check the thread ID for two reasons.
6075 // First, the interpreter checks for IllegalMonitorStateException at
6076 // a higher level. Second, if the bias was revoked while we held the
6077 // lock, the object could not be rebiased toward another thread, so
6078 // the bias bit would be clear.
6079 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
6080 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
6081 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
6082 jcc(Assembler::equal, done);
6083 }
6085 void MacroAssembler::c2bool(Register x) {
6086 // implements x == 0 ? 0 : 1
6087 // note: must only look at least-significant byte of x
6088 // since C-style booleans are stored in one byte
6089 // only! (was bug)
6090 andl(x, 0xFF);
6091 setb(Assembler::notZero, x);
6092 }
6094 // Wouldn't need if AddressLiteral version had new name
6095 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
6096 Assembler::call(L, rtype);
6097 }
6099 void MacroAssembler::call(Register entry) {
6100 Assembler::call(entry);
6101 }
6103 void MacroAssembler::call(AddressLiteral entry) {
6104 if (reachable(entry)) {
6105 Assembler::call_literal(entry.target(), entry.rspec());
6106 } else {
6107 lea(rscratch1, entry);
6108 Assembler::call(rscratch1);
6109 }
6110 }
6112 // Implementation of call_VM versions
6114 void MacroAssembler::call_VM(Register oop_result,
6115 address entry_point,
6116 bool check_exceptions) {
6117 Label C, E;
6118 call(C, relocInfo::none);
6119 jmp(E);
6121 bind(C);
6122 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
6123 ret(0);
6125 bind(E);
6126 }
6128 void MacroAssembler::call_VM(Register oop_result,
6129 address entry_point,
6130 Register arg_1,
6131 bool check_exceptions) {
6132 Label C, E;
6133 call(C, relocInfo::none);
6134 jmp(E);
6136 bind(C);
6137 pass_arg1(this, arg_1);
6138 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
6139 ret(0);
6141 bind(E);
6142 }
6144 void MacroAssembler::call_VM(Register oop_result,
6145 address entry_point,
6146 Register arg_1,
6147 Register arg_2,
6148 bool check_exceptions) {
6149 Label C, E;
6150 call(C, relocInfo::none);
6151 jmp(E);
6153 bind(C);
6155 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6157 pass_arg2(this, arg_2);
6158 pass_arg1(this, arg_1);
6159 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
6160 ret(0);
6162 bind(E);
6163 }
6165 void MacroAssembler::call_VM(Register oop_result,
6166 address entry_point,
6167 Register arg_1,
6168 Register arg_2,
6169 Register arg_3,
6170 bool check_exceptions) {
6171 Label C, E;
6172 call(C, relocInfo::none);
6173 jmp(E);
6175 bind(C);
6177 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6178 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6179 pass_arg3(this, arg_3);
6181 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6182 pass_arg2(this, arg_2);
6184 pass_arg1(this, arg_1);
6185 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
6186 ret(0);
6188 bind(E);
6189 }
6191 void MacroAssembler::call_VM(Register oop_result,
6192 Register last_java_sp,
6193 address entry_point,
6194 int number_of_arguments,
6195 bool check_exceptions) {
6196 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
6197 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
6198 }
6200 void MacroAssembler::call_VM(Register oop_result,
6201 Register last_java_sp,
6202 address entry_point,
6203 Register arg_1,
6204 bool check_exceptions) {
6205 pass_arg1(this, arg_1);
6206 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
6207 }
6209 void MacroAssembler::call_VM(Register oop_result,
6210 Register last_java_sp,
6211 address entry_point,
6212 Register arg_1,
6213 Register arg_2,
6214 bool check_exceptions) {
6216 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6217 pass_arg2(this, arg_2);
6218 pass_arg1(this, arg_1);
6219 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
6220 }
6222 void MacroAssembler::call_VM(Register oop_result,
6223 Register last_java_sp,
6224 address entry_point,
6225 Register arg_1,
6226 Register arg_2,
6227 Register arg_3,
6228 bool check_exceptions) {
6229 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6230 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6231 pass_arg3(this, arg_3);
6232 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6233 pass_arg2(this, arg_2);
6234 pass_arg1(this, arg_1);
6235 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
6236 }
6238 void MacroAssembler::super_call_VM(Register oop_result,
6239 Register last_java_sp,
6240 address entry_point,
6241 int number_of_arguments,
6242 bool check_exceptions) {
6243 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
6244 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
6245 }
6247 void MacroAssembler::super_call_VM(Register oop_result,
6248 Register last_java_sp,
6249 address entry_point,
6250 Register arg_1,
6251 bool check_exceptions) {
6252 pass_arg1(this, arg_1);
6253 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
6254 }
6256 void MacroAssembler::super_call_VM(Register oop_result,
6257 Register last_java_sp,
6258 address entry_point,
6259 Register arg_1,
6260 Register arg_2,
6261 bool check_exceptions) {
6263 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6264 pass_arg2(this, arg_2);
6265 pass_arg1(this, arg_1);
6266 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
6267 }
6269 void MacroAssembler::super_call_VM(Register oop_result,
6270 Register last_java_sp,
6271 address entry_point,
6272 Register arg_1,
6273 Register arg_2,
6274 Register arg_3,
6275 bool check_exceptions) {
6276 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6277 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6278 pass_arg3(this, arg_3);
6279 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6280 pass_arg2(this, arg_2);
6281 pass_arg1(this, arg_1);
6282 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
6283 }
6285 void MacroAssembler::call_VM_base(Register oop_result,
6286 Register java_thread,
6287 Register last_java_sp,
6288 address entry_point,
6289 int number_of_arguments,
6290 bool check_exceptions) {
6291 // determine java_thread register
6292 if (!java_thread->is_valid()) {
6293 #ifdef _LP64
6294 java_thread = r15_thread;
6295 #else
6296 java_thread = rdi;
6297 get_thread(java_thread);
6298 #endif // LP64
6299 }
6300 // determine last_java_sp register
6301 if (!last_java_sp->is_valid()) {
6302 last_java_sp = rsp;
6303 }
6304 // debugging support
6305 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
6306 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
6307 #ifdef ASSERT
6308 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
6309 // r12 is the heapbase.
6310 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base");)
6311 #endif // ASSERT
6313 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
6314 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
6316 // push java thread (becomes first argument of C function)
6318 NOT_LP64(push(java_thread); number_of_arguments++);
6319 LP64_ONLY(mov(c_rarg0, r15_thread));
6321 // set last Java frame before call
6322 assert(last_java_sp != rbp, "can't use ebp/rbp");
6324 // Only interpreter should have to set fp
6325 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
6327 // do the call, remove parameters
6328 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
6330 // restore the thread (cannot use the pushed argument since arguments
6331 // may be overwritten by C code generated by an optimizing compiler);
6332 // however can use the register value directly if it is callee saved.
6333 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
6334 // rdi & rsi (also r15) are callee saved -> nothing to do
6335 #ifdef ASSERT
6336 guarantee(java_thread != rax, "change this code");
6337 push(rax);
6338 { Label L;
6339 get_thread(rax);
6340 cmpptr(java_thread, rax);
6341 jcc(Assembler::equal, L);
6342 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
6343 bind(L);
6344 }
6345 pop(rax);
6346 #endif
6347 } else {
6348 get_thread(java_thread);
6349 }
6350 // reset last Java frame
6351 // Only interpreter should have to clear fp
6352 reset_last_Java_frame(java_thread, true, false);
6354 #ifndef CC_INTERP
6355 // C++ interp handles this in the interpreter
6356 check_and_handle_popframe(java_thread);
6357 check_and_handle_earlyret(java_thread);
6358 #endif /* CC_INTERP */
6360 if (check_exceptions) {
6361 // check for pending exceptions (java_thread is set upon return)
6362 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
6363 #ifndef _LP64
6364 jump_cc(Assembler::notEqual,
6365 RuntimeAddress(StubRoutines::forward_exception_entry()));
6366 #else
6367 // This used to conditionally jump to forward_exception however it is
6368 // possible if we relocate that the branch will not reach. So we must jump
6369 // around so we can always reach
6371 Label ok;
6372 jcc(Assembler::equal, ok);
6373 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
6374 bind(ok);
6375 #endif // LP64
6376 }
6378 // get oop result if there is one and reset the value in the thread
6379 if (oop_result->is_valid()) {
6380 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
6381 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
6382 verify_oop(oop_result, "broken oop in call_VM_base");
6383 }
6384 }
6386 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
6388 // Calculate the value for last_Java_sp
6389 // somewhat subtle. call_VM does an intermediate call
6390 // which places a return address on the stack just under the
6391 // stack pointer as the user finsihed with it. This allows
6392 // use to retrieve last_Java_pc from last_Java_sp[-1].
6393 // On 32bit we then have to push additional args on the stack to accomplish
6394 // the actual requested call. On 64bit call_VM only can use register args
6395 // so the only extra space is the return address that call_VM created.
6396 // This hopefully explains the calculations here.
6398 #ifdef _LP64
6399 // We've pushed one address, correct last_Java_sp
6400 lea(rax, Address(rsp, wordSize));
6401 #else
6402 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
6403 #endif // LP64
6405 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
6407 }
6409 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
6410 call_VM_leaf_base(entry_point, number_of_arguments);
6411 }
6413 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
6414 pass_arg0(this, arg_0);
6415 call_VM_leaf(entry_point, 1);
6416 }
6418 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
6420 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6421 pass_arg1(this, arg_1);
6422 pass_arg0(this, arg_0);
6423 call_VM_leaf(entry_point, 2);
6424 }
6426 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
6427 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6428 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6429 pass_arg2(this, arg_2);
6430 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6431 pass_arg1(this, arg_1);
6432 pass_arg0(this, arg_0);
6433 call_VM_leaf(entry_point, 3);
6434 }
6436 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
6437 pass_arg0(this, arg_0);
6438 MacroAssembler::call_VM_leaf_base(entry_point, 1);
6439 }
6441 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
6443 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6444 pass_arg1(this, arg_1);
6445 pass_arg0(this, arg_0);
6446 MacroAssembler::call_VM_leaf_base(entry_point, 2);
6447 }
6449 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
6450 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6451 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6452 pass_arg2(this, arg_2);
6453 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6454 pass_arg1(this, arg_1);
6455 pass_arg0(this, arg_0);
6456 MacroAssembler::call_VM_leaf_base(entry_point, 3);
6457 }
6459 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
6460 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
6461 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6462 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6463 pass_arg3(this, arg_3);
6464 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6465 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6466 pass_arg2(this, arg_2);
6467 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6468 pass_arg1(this, arg_1);
6469 pass_arg0(this, arg_0);
6470 MacroAssembler::call_VM_leaf_base(entry_point, 4);
6471 }
6473 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
6474 }
6476 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
6477 }
6479 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
6480 if (reachable(src1)) {
6481 cmpl(as_Address(src1), imm);
6482 } else {
6483 lea(rscratch1, src1);
6484 cmpl(Address(rscratch1, 0), imm);
6485 }
6486 }
6488 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
6489 assert(!src2.is_lval(), "use cmpptr");
6490 if (reachable(src2)) {
6491 cmpl(src1, as_Address(src2));
6492 } else {
6493 lea(rscratch1, src2);
6494 cmpl(src1, Address(rscratch1, 0));
6495 }
6496 }
6498 void MacroAssembler::cmp32(Register src1, int32_t imm) {
6499 Assembler::cmpl(src1, imm);
6500 }
6502 void MacroAssembler::cmp32(Register src1, Address src2) {
6503 Assembler::cmpl(src1, src2);
6504 }
6506 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6507 ucomisd(opr1, opr2);
6509 Label L;
6510 if (unordered_is_less) {
6511 movl(dst, -1);
6512 jcc(Assembler::parity, L);
6513 jcc(Assembler::below , L);
6514 movl(dst, 0);
6515 jcc(Assembler::equal , L);
6516 increment(dst);
6517 } else { // unordered is greater
6518 movl(dst, 1);
6519 jcc(Assembler::parity, L);
6520 jcc(Assembler::above , L);
6521 movl(dst, 0);
6522 jcc(Assembler::equal , L);
6523 decrementl(dst);
6524 }
6525 bind(L);
6526 }
6528 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6529 ucomiss(opr1, opr2);
6531 Label L;
6532 if (unordered_is_less) {
6533 movl(dst, -1);
6534 jcc(Assembler::parity, L);
6535 jcc(Assembler::below , L);
6536 movl(dst, 0);
6537 jcc(Assembler::equal , L);
6538 increment(dst);
6539 } else { // unordered is greater
6540 movl(dst, 1);
6541 jcc(Assembler::parity, L);
6542 jcc(Assembler::above , L);
6543 movl(dst, 0);
6544 jcc(Assembler::equal , L);
6545 decrementl(dst);
6546 }
6547 bind(L);
6548 }
6551 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
6552 if (reachable(src1)) {
6553 cmpb(as_Address(src1), imm);
6554 } else {
6555 lea(rscratch1, src1);
6556 cmpb(Address(rscratch1, 0), imm);
6557 }
6558 }
6560 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
6561 #ifdef _LP64
6562 if (src2.is_lval()) {
6563 movptr(rscratch1, src2);
6564 Assembler::cmpq(src1, rscratch1);
6565 } else if (reachable(src2)) {
6566 cmpq(src1, as_Address(src2));
6567 } else {
6568 lea(rscratch1, src2);
6569 Assembler::cmpq(src1, Address(rscratch1, 0));
6570 }
6571 #else
6572 if (src2.is_lval()) {
6573 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6574 } else {
6575 cmpl(src1, as_Address(src2));
6576 }
6577 #endif // _LP64
6578 }
6580 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
6581 assert(src2.is_lval(), "not a mem-mem compare");
6582 #ifdef _LP64
6583 // moves src2's literal address
6584 movptr(rscratch1, src2);
6585 Assembler::cmpq(src1, rscratch1);
6586 #else
6587 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6588 #endif // _LP64
6589 }
6591 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6592 if (reachable(adr)) {
6593 if (os::is_MP())
6594 lock();
6595 cmpxchgptr(reg, as_Address(adr));
6596 } else {
6597 lea(rscratch1, adr);
6598 if (os::is_MP())
6599 lock();
6600 cmpxchgptr(reg, Address(rscratch1, 0));
6601 }
6602 }
6604 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6605 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6606 }
6608 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6609 if (reachable(src)) {
6610 Assembler::comisd(dst, as_Address(src));
6611 } else {
6612 lea(rscratch1, src);
6613 Assembler::comisd(dst, Address(rscratch1, 0));
6614 }
6615 }
6617 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6618 if (reachable(src)) {
6619 Assembler::comiss(dst, as_Address(src));
6620 } else {
6621 lea(rscratch1, src);
6622 Assembler::comiss(dst, Address(rscratch1, 0));
6623 }
6624 }
6627 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6628 Condition negated_cond = negate_condition(cond);
6629 Label L;
6630 jcc(negated_cond, L);
6631 atomic_incl(counter_addr);
6632 bind(L);
6633 }
6635 int MacroAssembler::corrected_idivl(Register reg) {
6636 // Full implementation of Java idiv and irem; checks for
6637 // special case as described in JVM spec., p.243 & p.271.
6638 // The function returns the (pc) offset of the idivl
6639 // instruction - may be needed for implicit exceptions.
6640 //
6641 // normal case special case
6642 //
6643 // input : rax,: dividend min_int
6644 // reg: divisor (may not be rax,/rdx) -1
6645 //
6646 // output: rax,: quotient (= rax, idiv reg) min_int
6647 // rdx: remainder (= rax, irem reg) 0
6648 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
6649 const int min_int = 0x80000000;
6650 Label normal_case, special_case;
6652 // check for special case
6653 cmpl(rax, min_int);
6654 jcc(Assembler::notEqual, normal_case);
6655 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
6656 cmpl(reg, -1);
6657 jcc(Assembler::equal, special_case);
6659 // handle normal case
6660 bind(normal_case);
6661 cdql();
6662 int idivl_offset = offset();
6663 idivl(reg);
6665 // normal and special case exit
6666 bind(special_case);
6668 return idivl_offset;
6669 }
6673 void MacroAssembler::decrementl(Register reg, int value) {
6674 if (value == min_jint) {subl(reg, value) ; return; }
6675 if (value < 0) { incrementl(reg, -value); return; }
6676 if (value == 0) { ; return; }
6677 if (value == 1 && UseIncDec) { decl(reg) ; return; }
6678 /* else */ { subl(reg, value) ; return; }
6679 }
6681 void MacroAssembler::decrementl(Address dst, int value) {
6682 if (value == min_jint) {subl(dst, value) ; return; }
6683 if (value < 0) { incrementl(dst, -value); return; }
6684 if (value == 0) { ; return; }
6685 if (value == 1 && UseIncDec) { decl(dst) ; return; }
6686 /* else */ { subl(dst, value) ; return; }
6687 }
6689 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6690 assert (shift_value > 0, "illegal shift value");
6691 Label _is_positive;
6692 testl (reg, reg);
6693 jcc (Assembler::positive, _is_positive);
6694 int offset = (1 << shift_value) - 1 ;
6696 if (offset == 1) {
6697 incrementl(reg);
6698 } else {
6699 addl(reg, offset);
6700 }
6702 bind (_is_positive);
6703 sarl(reg, shift_value);
6704 }
6706 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
6707 if (reachable(src)) {
6708 Assembler::divsd(dst, as_Address(src));
6709 } else {
6710 lea(rscratch1, src);
6711 Assembler::divsd(dst, Address(rscratch1, 0));
6712 }
6713 }
6715 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
6716 if (reachable(src)) {
6717 Assembler::divss(dst, as_Address(src));
6718 } else {
6719 lea(rscratch1, src);
6720 Assembler::divss(dst, Address(rscratch1, 0));
6721 }
6722 }
6724 // !defined(COMPILER2) is because of stupid core builds
6725 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6726 void MacroAssembler::empty_FPU_stack() {
6727 if (VM_Version::supports_mmx()) {
6728 emms();
6729 } else {
6730 for (int i = 8; i-- > 0; ) ffree(i);
6731 }
6732 }
6733 #endif // !LP64 || C1 || !C2
6736 // Defines obj, preserves var_size_in_bytes
6737 void MacroAssembler::eden_allocate(Register obj,
6738 Register var_size_in_bytes,
6739 int con_size_in_bytes,
6740 Register t1,
6741 Label& slow_case) {
6742 assert(obj == rax, "obj must be in rax, for cmpxchg");
6743 assert_different_registers(obj, var_size_in_bytes, t1);
6744 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
6745 jmp(slow_case);
6746 } else {
6747 Register end = t1;
6748 Label retry;
6749 bind(retry);
6750 ExternalAddress heap_top((address) Universe::heap()->top_addr());
6751 movptr(obj, heap_top);
6752 if (var_size_in_bytes == noreg) {
6753 lea(end, Address(obj, con_size_in_bytes));
6754 } else {
6755 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
6756 }
6757 // if end < obj then we wrapped around => object too long => slow case
6758 cmpptr(end, obj);
6759 jcc(Assembler::below, slow_case);
6760 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
6761 jcc(Assembler::above, slow_case);
6762 // Compare obj with the top addr, and if still equal, store the new top addr in
6763 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
6764 // it otherwise. Use lock prefix for atomicity on MPs.
6765 locked_cmpxchgptr(end, heap_top);
6766 jcc(Assembler::notEqual, retry);
6767 }
6768 }
6770 void MacroAssembler::enter() {
6771 push(rbp);
6772 mov(rbp, rsp);
6773 }
6775 // A 5 byte nop that is safe for patching (see patch_verified_entry)
6776 void MacroAssembler::fat_nop() {
6777 if (UseAddressNop) {
6778 addr_nop_5();
6779 } else {
6780 emit_byte(0x26); // es:
6781 emit_byte(0x2e); // cs:
6782 emit_byte(0x64); // fs:
6783 emit_byte(0x65); // gs:
6784 emit_byte(0x90);
6785 }
6786 }
6788 void MacroAssembler::fcmp(Register tmp) {
6789 fcmp(tmp, 1, true, true);
6790 }
6792 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
6793 assert(!pop_right || pop_left, "usage error");
6794 if (VM_Version::supports_cmov()) {
6795 assert(tmp == noreg, "unneeded temp");
6796 if (pop_left) {
6797 fucomip(index);
6798 } else {
6799 fucomi(index);
6800 }
6801 if (pop_right) {
6802 fpop();
6803 }
6804 } else {
6805 assert(tmp != noreg, "need temp");
6806 if (pop_left) {
6807 if (pop_right) {
6808 fcompp();
6809 } else {
6810 fcomp(index);
6811 }
6812 } else {
6813 fcom(index);
6814 }
6815 // convert FPU condition into eflags condition via rax,
6816 save_rax(tmp);
6817 fwait(); fnstsw_ax();
6818 sahf();
6819 restore_rax(tmp);
6820 }
6821 // condition codes set as follows:
6822 //
6823 // CF (corresponds to C0) if x < y
6824 // PF (corresponds to C2) if unordered
6825 // ZF (corresponds to C3) if x = y
6826 }
6828 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
6829 fcmp2int(dst, unordered_is_less, 1, true, true);
6830 }
6832 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
6833 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
6834 Label L;
6835 if (unordered_is_less) {
6836 movl(dst, -1);
6837 jcc(Assembler::parity, L);
6838 jcc(Assembler::below , L);
6839 movl(dst, 0);
6840 jcc(Assembler::equal , L);
6841 increment(dst);
6842 } else { // unordered is greater
6843 movl(dst, 1);
6844 jcc(Assembler::parity, L);
6845 jcc(Assembler::above , L);
6846 movl(dst, 0);
6847 jcc(Assembler::equal , L);
6848 decrementl(dst);
6849 }
6850 bind(L);
6851 }
6853 void MacroAssembler::fld_d(AddressLiteral src) {
6854 fld_d(as_Address(src));
6855 }
6857 void MacroAssembler::fld_s(AddressLiteral src) {
6858 fld_s(as_Address(src));
6859 }
6861 void MacroAssembler::fld_x(AddressLiteral src) {
6862 Assembler::fld_x(as_Address(src));
6863 }
6865 void MacroAssembler::fldcw(AddressLiteral src) {
6866 Assembler::fldcw(as_Address(src));
6867 }
6869 void MacroAssembler::fpop() {
6870 ffree();
6871 fincstp();
6872 }
6874 void MacroAssembler::fremr(Register tmp) {
6875 save_rax(tmp);
6876 { Label L;
6877 bind(L);
6878 fprem();
6879 fwait(); fnstsw_ax();
6880 #ifdef _LP64
6881 testl(rax, 0x400);
6882 jcc(Assembler::notEqual, L);
6883 #else
6884 sahf();
6885 jcc(Assembler::parity, L);
6886 #endif // _LP64
6887 }
6888 restore_rax(tmp);
6889 // Result is in ST0.
6890 // Note: fxch & fpop to get rid of ST1
6891 // (otherwise FPU stack could overflow eventually)
6892 fxch(1);
6893 fpop();
6894 }
6897 void MacroAssembler::incrementl(AddressLiteral dst) {
6898 if (reachable(dst)) {
6899 incrementl(as_Address(dst));
6900 } else {
6901 lea(rscratch1, dst);
6902 incrementl(Address(rscratch1, 0));
6903 }
6904 }
6906 void MacroAssembler::incrementl(ArrayAddress dst) {
6907 incrementl(as_Address(dst));
6908 }
6910 void MacroAssembler::incrementl(Register reg, int value) {
6911 if (value == min_jint) {addl(reg, value) ; return; }
6912 if (value < 0) { decrementl(reg, -value); return; }
6913 if (value == 0) { ; return; }
6914 if (value == 1 && UseIncDec) { incl(reg) ; return; }
6915 /* else */ { addl(reg, value) ; return; }
6916 }
6918 void MacroAssembler::incrementl(Address dst, int value) {
6919 if (value == min_jint) {addl(dst, value) ; return; }
6920 if (value < 0) { decrementl(dst, -value); return; }
6921 if (value == 0) { ; return; }
6922 if (value == 1 && UseIncDec) { incl(dst) ; return; }
6923 /* else */ { addl(dst, value) ; return; }
6924 }
6926 void MacroAssembler::jump(AddressLiteral dst) {
6927 if (reachable(dst)) {
6928 jmp_literal(dst.target(), dst.rspec());
6929 } else {
6930 lea(rscratch1, dst);
6931 jmp(rscratch1);
6932 }
6933 }
6935 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
6936 if (reachable(dst)) {
6937 InstructionMark im(this);
6938 relocate(dst.reloc());
6939 const int short_size = 2;
6940 const int long_size = 6;
6941 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
6942 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
6943 // 0111 tttn #8-bit disp
6944 emit_byte(0x70 | cc);
6945 emit_byte((offs - short_size) & 0xFF);
6946 } else {
6947 // 0000 1111 1000 tttn #32-bit disp
6948 emit_byte(0x0F);
6949 emit_byte(0x80 | cc);
6950 emit_long(offs - long_size);
6951 }
6952 } else {
6953 #ifdef ASSERT
6954 warning("reversing conditional branch");
6955 #endif /* ASSERT */
6956 Label skip;
6957 jccb(reverse[cc], skip);
6958 lea(rscratch1, dst);
6959 Assembler::jmp(rscratch1);
6960 bind(skip);
6961 }
6962 }
6964 void MacroAssembler::ldmxcsr(AddressLiteral src) {
6965 if (reachable(src)) {
6966 Assembler::ldmxcsr(as_Address(src));
6967 } else {
6968 lea(rscratch1, src);
6969 Assembler::ldmxcsr(Address(rscratch1, 0));
6970 }
6971 }
6973 int MacroAssembler::load_signed_byte(Register dst, Address src) {
6974 int off;
6975 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6976 off = offset();
6977 movsbl(dst, src); // movsxb
6978 } else {
6979 off = load_unsigned_byte(dst, src);
6980 shll(dst, 24);
6981 sarl(dst, 24);
6982 }
6983 return off;
6984 }
6986 // Note: load_signed_short used to be called load_signed_word.
6987 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
6988 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
6989 // The term "word" in HotSpot means a 32- or 64-bit machine word.
6990 int MacroAssembler::load_signed_short(Register dst, Address src) {
6991 int off;
6992 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6993 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
6994 // version but this is what 64bit has always done. This seems to imply
6995 // that users are only using 32bits worth.
6996 off = offset();
6997 movswl(dst, src); // movsxw
6998 } else {
6999 off = load_unsigned_short(dst, src);
7000 shll(dst, 16);
7001 sarl(dst, 16);
7002 }
7003 return off;
7004 }
7006 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
7007 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
7008 // and "3.9 Partial Register Penalties", p. 22).
7009 int off;
7010 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
7011 off = offset();
7012 movzbl(dst, src); // movzxb
7013 } else {
7014 xorl(dst, dst);
7015 off = offset();
7016 movb(dst, src);
7017 }
7018 return off;
7019 }
7021 // Note: load_unsigned_short used to be called load_unsigned_word.
7022 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
7023 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
7024 // and "3.9 Partial Register Penalties", p. 22).
7025 int off;
7026 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
7027 off = offset();
7028 movzwl(dst, src); // movzxw
7029 } else {
7030 xorl(dst, dst);
7031 off = offset();
7032 movw(dst, src);
7033 }
7034 return off;
7035 }
7037 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
7038 switch (size_in_bytes) {
7039 #ifndef _LP64
7040 case 8:
7041 assert(dst2 != noreg, "second dest register required");
7042 movl(dst, src);
7043 movl(dst2, src.plus_disp(BytesPerInt));
7044 break;
7045 #else
7046 case 8: movq(dst, src); break;
7047 #endif
7048 case 4: movl(dst, src); break;
7049 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
7050 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
7051 default: ShouldNotReachHere();
7052 }
7053 }
7055 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
7056 switch (size_in_bytes) {
7057 #ifndef _LP64
7058 case 8:
7059 assert(src2 != noreg, "second source register required");
7060 movl(dst, src);
7061 movl(dst.plus_disp(BytesPerInt), src2);
7062 break;
7063 #else
7064 case 8: movq(dst, src); break;
7065 #endif
7066 case 4: movl(dst, src); break;
7067 case 2: movw(dst, src); break;
7068 case 1: movb(dst, src); break;
7069 default: ShouldNotReachHere();
7070 }
7071 }
7073 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
7074 if (reachable(dst)) {
7075 movl(as_Address(dst), src);
7076 } else {
7077 lea(rscratch1, dst);
7078 movl(Address(rscratch1, 0), src);
7079 }
7080 }
7082 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
7083 if (reachable(src)) {
7084 movl(dst, as_Address(src));
7085 } else {
7086 lea(rscratch1, src);
7087 movl(dst, Address(rscratch1, 0));
7088 }
7089 }
7091 // C++ bool manipulation
7093 void MacroAssembler::movbool(Register dst, Address src) {
7094 if(sizeof(bool) == 1)
7095 movb(dst, src);
7096 else if(sizeof(bool) == 2)
7097 movw(dst, src);
7098 else if(sizeof(bool) == 4)
7099 movl(dst, src);
7100 else
7101 // unsupported
7102 ShouldNotReachHere();
7103 }
7105 void MacroAssembler::movbool(Address dst, bool boolconst) {
7106 if(sizeof(bool) == 1)
7107 movb(dst, (int) boolconst);
7108 else if(sizeof(bool) == 2)
7109 movw(dst, (int) boolconst);
7110 else if(sizeof(bool) == 4)
7111 movl(dst, (int) boolconst);
7112 else
7113 // unsupported
7114 ShouldNotReachHere();
7115 }
7117 void MacroAssembler::movbool(Address dst, Register src) {
7118 if(sizeof(bool) == 1)
7119 movb(dst, src);
7120 else if(sizeof(bool) == 2)
7121 movw(dst, src);
7122 else if(sizeof(bool) == 4)
7123 movl(dst, src);
7124 else
7125 // unsupported
7126 ShouldNotReachHere();
7127 }
7129 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
7130 movb(as_Address(dst), src);
7131 }
7133 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
7134 if (reachable(src)) {
7135 if (UseXmmLoadAndClearUpper) {
7136 movsd (dst, as_Address(src));
7137 } else {
7138 movlpd(dst, as_Address(src));
7139 }
7140 } else {
7141 lea(rscratch1, src);
7142 if (UseXmmLoadAndClearUpper) {
7143 movsd (dst, Address(rscratch1, 0));
7144 } else {
7145 movlpd(dst, Address(rscratch1, 0));
7146 }
7147 }
7148 }
7150 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
7151 if (reachable(src)) {
7152 movss(dst, as_Address(src));
7153 } else {
7154 lea(rscratch1, src);
7155 movss(dst, Address(rscratch1, 0));
7156 }
7157 }
7159 void MacroAssembler::movptr(Register dst, Register src) {
7160 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
7161 }
7163 void MacroAssembler::movptr(Register dst, Address src) {
7164 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
7165 }
7167 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
7168 void MacroAssembler::movptr(Register dst, intptr_t src) {
7169 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
7170 }
7172 void MacroAssembler::movptr(Address dst, Register src) {
7173 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
7174 }
7176 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
7177 if (reachable(src)) {
7178 Assembler::movsd(dst, as_Address(src));
7179 } else {
7180 lea(rscratch1, src);
7181 Assembler::movsd(dst, Address(rscratch1, 0));
7182 }
7183 }
7185 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
7186 if (reachable(src)) {
7187 Assembler::movss(dst, as_Address(src));
7188 } else {
7189 lea(rscratch1, src);
7190 Assembler::movss(dst, Address(rscratch1, 0));
7191 }
7192 }
7194 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
7195 if (reachable(src)) {
7196 Assembler::mulsd(dst, as_Address(src));
7197 } else {
7198 lea(rscratch1, src);
7199 Assembler::mulsd(dst, Address(rscratch1, 0));
7200 }
7201 }
7203 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
7204 if (reachable(src)) {
7205 Assembler::mulss(dst, as_Address(src));
7206 } else {
7207 lea(rscratch1, src);
7208 Assembler::mulss(dst, Address(rscratch1, 0));
7209 }
7210 }
7212 void MacroAssembler::null_check(Register reg, int offset) {
7213 if (needs_explicit_null_check(offset)) {
7214 // provoke OS NULL exception if reg = NULL by
7215 // accessing M[reg] w/o changing any (non-CC) registers
7216 // NOTE: cmpl is plenty here to provoke a segv
7217 cmpptr(rax, Address(reg, 0));
7218 // Note: should probably use testl(rax, Address(reg, 0));
7219 // may be shorter code (however, this version of
7220 // testl needs to be implemented first)
7221 } else {
7222 // nothing to do, (later) access of M[reg + offset]
7223 // will provoke OS NULL exception if reg = NULL
7224 }
7225 }
7227 void MacroAssembler::os_breakpoint() {
7228 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
7229 // (e.g., MSVC can't call ps() otherwise)
7230 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
7231 }
7233 void MacroAssembler::pop_CPU_state() {
7234 pop_FPU_state();
7235 pop_IU_state();
7236 }
7238 void MacroAssembler::pop_FPU_state() {
7239 NOT_LP64(frstor(Address(rsp, 0));)
7240 LP64_ONLY(fxrstor(Address(rsp, 0));)
7241 addptr(rsp, FPUStateSizeInWords * wordSize);
7242 }
7244 void MacroAssembler::pop_IU_state() {
7245 popa();
7246 LP64_ONLY(addq(rsp, 8));
7247 popf();
7248 }
7250 // Save Integer and Float state
7251 // Warning: Stack must be 16 byte aligned (64bit)
7252 void MacroAssembler::push_CPU_state() {
7253 push_IU_state();
7254 push_FPU_state();
7255 }
7257 void MacroAssembler::push_FPU_state() {
7258 subptr(rsp, FPUStateSizeInWords * wordSize);
7259 #ifndef _LP64
7260 fnsave(Address(rsp, 0));
7261 fwait();
7262 #else
7263 fxsave(Address(rsp, 0));
7264 #endif // LP64
7265 }
7267 void MacroAssembler::push_IU_state() {
7268 // Push flags first because pusha kills them
7269 pushf();
7270 // Make sure rsp stays 16-byte aligned
7271 LP64_ONLY(subq(rsp, 8));
7272 pusha();
7273 }
7275 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
7276 // determine java_thread register
7277 if (!java_thread->is_valid()) {
7278 java_thread = rdi;
7279 get_thread(java_thread);
7280 }
7281 // we must set sp to zero to clear frame
7282 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
7283 if (clear_fp) {
7284 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
7285 }
7287 if (clear_pc)
7288 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
7290 }
7292 void MacroAssembler::restore_rax(Register tmp) {
7293 if (tmp == noreg) pop(rax);
7294 else if (tmp != rax) mov(rax, tmp);
7295 }
7297 void MacroAssembler::round_to(Register reg, int modulus) {
7298 addptr(reg, modulus - 1);
7299 andptr(reg, -modulus);
7300 }
7302 void MacroAssembler::save_rax(Register tmp) {
7303 if (tmp == noreg) push(rax);
7304 else if (tmp != rax) mov(tmp, rax);
7305 }
7307 // Write serialization page so VM thread can do a pseudo remote membar.
7308 // We use the current thread pointer to calculate a thread specific
7309 // offset to write to within the page. This minimizes bus traffic
7310 // due to cache line collision.
7311 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
7312 movl(tmp, thread);
7313 shrl(tmp, os::get_serialize_page_shift_count());
7314 andl(tmp, (os::vm_page_size() - sizeof(int)));
7316 Address index(noreg, tmp, Address::times_1);
7317 ExternalAddress page(os::get_memory_serialize_page());
7319 // Size of store must match masking code above
7320 movl(as_Address(ArrayAddress(page, index)), tmp);
7321 }
7323 // Calls to C land
7324 //
7325 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
7326 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
7327 // has to be reset to 0. This is required to allow proper stack traversal.
7328 void MacroAssembler::set_last_Java_frame(Register java_thread,
7329 Register last_java_sp,
7330 Register last_java_fp,
7331 address last_java_pc) {
7332 // determine java_thread register
7333 if (!java_thread->is_valid()) {
7334 java_thread = rdi;
7335 get_thread(java_thread);
7336 }
7337 // determine last_java_sp register
7338 if (!last_java_sp->is_valid()) {
7339 last_java_sp = rsp;
7340 }
7342 // last_java_fp is optional
7344 if (last_java_fp->is_valid()) {
7345 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
7346 }
7348 // last_java_pc is optional
7350 if (last_java_pc != NULL) {
7351 lea(Address(java_thread,
7352 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
7353 InternalAddress(last_java_pc));
7355 }
7356 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
7357 }
7359 void MacroAssembler::shlptr(Register dst, int imm8) {
7360 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
7361 }
7363 void MacroAssembler::shrptr(Register dst, int imm8) {
7364 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
7365 }
7367 void MacroAssembler::sign_extend_byte(Register reg) {
7368 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
7369 movsbl(reg, reg); // movsxb
7370 } else {
7371 shll(reg, 24);
7372 sarl(reg, 24);
7373 }
7374 }
7376 void MacroAssembler::sign_extend_short(Register reg) {
7377 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
7378 movswl(reg, reg); // movsxw
7379 } else {
7380 shll(reg, 16);
7381 sarl(reg, 16);
7382 }
7383 }
7385 void MacroAssembler::testl(Register dst, AddressLiteral src) {
7386 assert(reachable(src), "Address should be reachable");
7387 testl(dst, as_Address(src));
7388 }
7390 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
7391 if (reachable(src)) {
7392 Assembler::sqrtsd(dst, as_Address(src));
7393 } else {
7394 lea(rscratch1, src);
7395 Assembler::sqrtsd(dst, Address(rscratch1, 0));
7396 }
7397 }
7399 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
7400 if (reachable(src)) {
7401 Assembler::sqrtss(dst, as_Address(src));
7402 } else {
7403 lea(rscratch1, src);
7404 Assembler::sqrtss(dst, Address(rscratch1, 0));
7405 }
7406 }
7408 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
7409 if (reachable(src)) {
7410 Assembler::subsd(dst, as_Address(src));
7411 } else {
7412 lea(rscratch1, src);
7413 Assembler::subsd(dst, Address(rscratch1, 0));
7414 }
7415 }
7417 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
7418 if (reachable(src)) {
7419 Assembler::subss(dst, as_Address(src));
7420 } else {
7421 lea(rscratch1, src);
7422 Assembler::subss(dst, Address(rscratch1, 0));
7423 }
7424 }
7426 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7427 if (reachable(src)) {
7428 Assembler::ucomisd(dst, as_Address(src));
7429 } else {
7430 lea(rscratch1, src);
7431 Assembler::ucomisd(dst, Address(rscratch1, 0));
7432 }
7433 }
7435 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7436 if (reachable(src)) {
7437 Assembler::ucomiss(dst, as_Address(src));
7438 } else {
7439 lea(rscratch1, src);
7440 Assembler::ucomiss(dst, Address(rscratch1, 0));
7441 }
7442 }
7444 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7445 // Used in sign-bit flipping with aligned address.
7446 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
7447 if (reachable(src)) {
7448 Assembler::xorpd(dst, as_Address(src));
7449 } else {
7450 lea(rscratch1, src);
7451 Assembler::xorpd(dst, Address(rscratch1, 0));
7452 }
7453 }
7455 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7456 // Used in sign-bit flipping with aligned address.
7457 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
7458 if (reachable(src)) {
7459 Assembler::xorps(dst, as_Address(src));
7460 } else {
7461 lea(rscratch1, src);
7462 Assembler::xorps(dst, Address(rscratch1, 0));
7463 }
7464 }
7466 // AVX 3-operands instructions
7468 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7469 if (reachable(src)) {
7470 vaddsd(dst, nds, as_Address(src));
7471 } else {
7472 lea(rscratch1, src);
7473 vaddsd(dst, nds, Address(rscratch1, 0));
7474 }
7475 }
7477 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7478 if (reachable(src)) {
7479 vaddss(dst, nds, as_Address(src));
7480 } else {
7481 lea(rscratch1, src);
7482 vaddss(dst, nds, Address(rscratch1, 0));
7483 }
7484 }
7486 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7487 if (reachable(src)) {
7488 vandpd(dst, nds, as_Address(src));
7489 } else {
7490 lea(rscratch1, src);
7491 vandpd(dst, nds, Address(rscratch1, 0));
7492 }
7493 }
7495 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7496 if (reachable(src)) {
7497 vandps(dst, nds, as_Address(src));
7498 } else {
7499 lea(rscratch1, src);
7500 vandps(dst, nds, Address(rscratch1, 0));
7501 }
7502 }
7504 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7505 if (reachable(src)) {
7506 vdivsd(dst, nds, as_Address(src));
7507 } else {
7508 lea(rscratch1, src);
7509 vdivsd(dst, nds, Address(rscratch1, 0));
7510 }
7511 }
7513 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7514 if (reachable(src)) {
7515 vdivss(dst, nds, as_Address(src));
7516 } else {
7517 lea(rscratch1, src);
7518 vdivss(dst, nds, Address(rscratch1, 0));
7519 }
7520 }
7522 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7523 if (reachable(src)) {
7524 vmulsd(dst, nds, as_Address(src));
7525 } else {
7526 lea(rscratch1, src);
7527 vmulsd(dst, nds, Address(rscratch1, 0));
7528 }
7529 }
7531 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7532 if (reachable(src)) {
7533 vmulss(dst, nds, as_Address(src));
7534 } else {
7535 lea(rscratch1, src);
7536 vmulss(dst, nds, Address(rscratch1, 0));
7537 }
7538 }
7540 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7541 if (reachable(src)) {
7542 vsubsd(dst, nds, as_Address(src));
7543 } else {
7544 lea(rscratch1, src);
7545 vsubsd(dst, nds, Address(rscratch1, 0));
7546 }
7547 }
7549 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7550 if (reachable(src)) {
7551 vsubss(dst, nds, as_Address(src));
7552 } else {
7553 lea(rscratch1, src);
7554 vsubss(dst, nds, Address(rscratch1, 0));
7555 }
7556 }
7558 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7559 if (reachable(src)) {
7560 vxorpd(dst, nds, as_Address(src));
7561 } else {
7562 lea(rscratch1, src);
7563 vxorpd(dst, nds, Address(rscratch1, 0));
7564 }
7565 }
7567 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7568 if (reachable(src)) {
7569 vxorps(dst, nds, as_Address(src));
7570 } else {
7571 lea(rscratch1, src);
7572 vxorps(dst, nds, Address(rscratch1, 0));
7573 }
7574 }
7577 //////////////////////////////////////////////////////////////////////////////////
7578 #ifndef SERIALGC
7580 void MacroAssembler::g1_write_barrier_pre(Register obj,
7581 Register pre_val,
7582 Register thread,
7583 Register tmp,
7584 bool tosca_live,
7585 bool expand_call) {
7587 // If expand_call is true then we expand the call_VM_leaf macro
7588 // directly to skip generating the check by
7589 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
7591 #ifdef _LP64
7592 assert(thread == r15_thread, "must be");
7593 #endif // _LP64
7595 Label done;
7596 Label runtime;
7598 assert(pre_val != noreg, "check this code");
7600 if (obj != noreg) {
7601 assert_different_registers(obj, pre_val, tmp);
7602 assert(pre_val != rax, "check this code");
7603 }
7605 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
7606 PtrQueue::byte_offset_of_active()));
7607 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
7608 PtrQueue::byte_offset_of_index()));
7609 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
7610 PtrQueue::byte_offset_of_buf()));
7613 // Is marking active?
7614 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
7615 cmpl(in_progress, 0);
7616 } else {
7617 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
7618 cmpb(in_progress, 0);
7619 }
7620 jcc(Assembler::equal, done);
7622 // Do we need to load the previous value?
7623 if (obj != noreg) {
7624 load_heap_oop(pre_val, Address(obj, 0));
7625 }
7627 // Is the previous value null?
7628 cmpptr(pre_val, (int32_t) NULL_WORD);
7629 jcc(Assembler::equal, done);
7631 // Can we store original value in the thread's buffer?
7632 // Is index == 0?
7633 // (The index field is typed as size_t.)
7635 movptr(tmp, index); // tmp := *index_adr
7636 cmpptr(tmp, 0); // tmp == 0?
7637 jcc(Assembler::equal, runtime); // If yes, goto runtime
7639 subptr(tmp, wordSize); // tmp := tmp - wordSize
7640 movptr(index, tmp); // *index_adr := tmp
7641 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
7643 // Record the previous value
7644 movptr(Address(tmp, 0), pre_val);
7645 jmp(done);
7647 bind(runtime);
7648 // save the live input values
7649 if(tosca_live) push(rax);
7651 if (obj != noreg && obj != rax)
7652 push(obj);
7654 if (pre_val != rax)
7655 push(pre_val);
7657 // Calling the runtime using the regular call_VM_leaf mechanism generates
7658 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
7659 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
7660 //
7661 // If we care generating the pre-barrier without a frame (e.g. in the
7662 // intrinsified Reference.get() routine) then ebp might be pointing to
7663 // the caller frame and so this check will most likely fail at runtime.
7664 //
7665 // Expanding the call directly bypasses the generation of the check.
7666 // So when we do not have have a full interpreter frame on the stack
7667 // expand_call should be passed true.
7669 NOT_LP64( push(thread); )
7671 if (expand_call) {
7672 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
7673 pass_arg1(this, thread);
7674 pass_arg0(this, pre_val);
7675 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
7676 } else {
7677 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
7678 }
7680 NOT_LP64( pop(thread); )
7682 // save the live input values
7683 if (pre_val != rax)
7684 pop(pre_val);
7686 if (obj != noreg && obj != rax)
7687 pop(obj);
7689 if(tosca_live) pop(rax);
7691 bind(done);
7692 }
7694 void MacroAssembler::g1_write_barrier_post(Register store_addr,
7695 Register new_val,
7696 Register thread,
7697 Register tmp,
7698 Register tmp2) {
7699 #ifdef _LP64
7700 assert(thread == r15_thread, "must be");
7701 #endif // _LP64
7703 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
7704 PtrQueue::byte_offset_of_index()));
7705 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
7706 PtrQueue::byte_offset_of_buf()));
7708 BarrierSet* bs = Universe::heap()->barrier_set();
7709 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
7710 Label done;
7711 Label runtime;
7713 // Does store cross heap regions?
7715 movptr(tmp, store_addr);
7716 xorptr(tmp, new_val);
7717 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
7718 jcc(Assembler::equal, done);
7720 // crosses regions, storing NULL?
7722 cmpptr(new_val, (int32_t) NULL_WORD);
7723 jcc(Assembler::equal, done);
7725 // storing region crossing non-NULL, is card already dirty?
7727 ExternalAddress cardtable((address) ct->byte_map_base);
7728 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
7729 #ifdef _LP64
7730 const Register card_addr = tmp;
7732 movq(card_addr, store_addr);
7733 shrq(card_addr, CardTableModRefBS::card_shift);
7735 lea(tmp2, cardtable);
7737 // get the address of the card
7738 addq(card_addr, tmp2);
7739 #else
7740 const Register card_index = tmp;
7742 movl(card_index, store_addr);
7743 shrl(card_index, CardTableModRefBS::card_shift);
7745 Address index(noreg, card_index, Address::times_1);
7746 const Register card_addr = tmp;
7747 lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
7748 #endif
7749 cmpb(Address(card_addr, 0), 0);
7750 jcc(Assembler::equal, done);
7752 // storing a region crossing, non-NULL oop, card is clean.
7753 // dirty card and log.
7755 movb(Address(card_addr, 0), 0);
7757 cmpl(queue_index, 0);
7758 jcc(Assembler::equal, runtime);
7759 subl(queue_index, wordSize);
7760 movptr(tmp2, buffer);
7761 #ifdef _LP64
7762 movslq(rscratch1, queue_index);
7763 addq(tmp2, rscratch1);
7764 movq(Address(tmp2, 0), card_addr);
7765 #else
7766 addl(tmp2, queue_index);
7767 movl(Address(tmp2, 0), card_index);
7768 #endif
7769 jmp(done);
7771 bind(runtime);
7772 // save the live input values
7773 push(store_addr);
7774 push(new_val);
7775 #ifdef _LP64
7776 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
7777 #else
7778 push(thread);
7779 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
7780 pop(thread);
7781 #endif
7782 pop(new_val);
7783 pop(store_addr);
7785 bind(done);
7786 }
7788 #endif // SERIALGC
7789 //////////////////////////////////////////////////////////////////////////////////
7792 void MacroAssembler::store_check(Register obj) {
7793 // Does a store check for the oop in register obj. The content of
7794 // register obj is destroyed afterwards.
7795 store_check_part_1(obj);
7796 store_check_part_2(obj);
7797 }
7799 void MacroAssembler::store_check(Register obj, Address dst) {
7800 store_check(obj);
7801 }
7804 // split the store check operation so that other instructions can be scheduled inbetween
7805 void MacroAssembler::store_check_part_1(Register obj) {
7806 BarrierSet* bs = Universe::heap()->barrier_set();
7807 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7808 shrptr(obj, CardTableModRefBS::card_shift);
7809 }
7811 void MacroAssembler::store_check_part_2(Register obj) {
7812 BarrierSet* bs = Universe::heap()->barrier_set();
7813 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7814 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
7815 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
7817 // The calculation for byte_map_base is as follows:
7818 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
7819 // So this essentially converts an address to a displacement and
7820 // it will never need to be relocated. On 64bit however the value may be too
7821 // large for a 32bit displacement
7823 intptr_t disp = (intptr_t) ct->byte_map_base;
7824 if (is_simm32(disp)) {
7825 Address cardtable(noreg, obj, Address::times_1, disp);
7826 movb(cardtable, 0);
7827 } else {
7828 // By doing it as an ExternalAddress disp could be converted to a rip-relative
7829 // displacement and done in a single instruction given favorable mapping and
7830 // a smarter version of as_Address. Worst case it is two instructions which
7831 // is no worse off then loading disp into a register and doing as a simple
7832 // Address() as above.
7833 // We can't do as ExternalAddress as the only style since if disp == 0 we'll
7834 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
7835 // in some cases we'll get a single instruction version.
7837 ExternalAddress cardtable((address)disp);
7838 Address index(noreg, obj, Address::times_1);
7839 movb(as_Address(ArrayAddress(cardtable, index)), 0);
7840 }
7841 }
7843 void MacroAssembler::subptr(Register dst, int32_t imm32) {
7844 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
7845 }
7847 // Force generation of a 4 byte immediate value even if it fits into 8bit
7848 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
7849 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
7850 }
7852 void MacroAssembler::subptr(Register dst, Register src) {
7853 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
7854 }
7856 // C++ bool manipulation
7857 void MacroAssembler::testbool(Register dst) {
7858 if(sizeof(bool) == 1)
7859 testb(dst, 0xff);
7860 else if(sizeof(bool) == 2) {
7861 // testw implementation needed for two byte bools
7862 ShouldNotReachHere();
7863 } else if(sizeof(bool) == 4)
7864 testl(dst, dst);
7865 else
7866 // unsupported
7867 ShouldNotReachHere();
7868 }
7870 void MacroAssembler::testptr(Register dst, Register src) {
7871 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
7872 }
7874 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
7875 void MacroAssembler::tlab_allocate(Register obj,
7876 Register var_size_in_bytes,
7877 int con_size_in_bytes,
7878 Register t1,
7879 Register t2,
7880 Label& slow_case) {
7881 assert_different_registers(obj, t1, t2);
7882 assert_different_registers(obj, var_size_in_bytes, t1);
7883 Register end = t2;
7884 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
7886 verify_tlab();
7888 NOT_LP64(get_thread(thread));
7890 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
7891 if (var_size_in_bytes == noreg) {
7892 lea(end, Address(obj, con_size_in_bytes));
7893 } else {
7894 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
7895 }
7896 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
7897 jcc(Assembler::above, slow_case);
7899 // update the tlab top pointer
7900 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
7902 // recover var_size_in_bytes if necessary
7903 if (var_size_in_bytes == end) {
7904 subptr(var_size_in_bytes, obj);
7905 }
7906 verify_tlab();
7907 }
7909 // Preserves rbx, and rdx.
7910 Register MacroAssembler::tlab_refill(Label& retry,
7911 Label& try_eden,
7912 Label& slow_case) {
7913 Register top = rax;
7914 Register t1 = rcx;
7915 Register t2 = rsi;
7916 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
7917 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
7918 Label do_refill, discard_tlab;
7920 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
7921 // No allocation in the shared eden.
7922 jmp(slow_case);
7923 }
7925 NOT_LP64(get_thread(thread_reg));
7927 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7928 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7930 // calculate amount of free space
7931 subptr(t1, top);
7932 shrptr(t1, LogHeapWordSize);
7934 // Retain tlab and allocate object in shared space if
7935 // the amount free in the tlab is too large to discard.
7936 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
7937 jcc(Assembler::lessEqual, discard_tlab);
7939 // Retain
7940 // %%% yuck as movptr...
7941 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
7942 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
7943 if (TLABStats) {
7944 // increment number of slow_allocations
7945 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
7946 }
7947 jmp(try_eden);
7949 bind(discard_tlab);
7950 if (TLABStats) {
7951 // increment number of refills
7952 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
7953 // accumulate wastage -- t1 is amount free in tlab
7954 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
7955 }
7957 // if tlab is currently allocated (top or end != null) then
7958 // fill [top, end + alignment_reserve) with array object
7959 testptr(top, top);
7960 jcc(Assembler::zero, do_refill);
7962 // set up the mark word
7963 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
7964 // set the length to the remaining space
7965 subptr(t1, typeArrayOopDesc::header_size(T_INT));
7966 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
7967 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
7968 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
7969 // set klass to intArrayKlass
7970 // dubious reloc why not an oop reloc?
7971 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
7972 // store klass last. concurrent gcs assumes klass length is valid if
7973 // klass field is not null.
7974 store_klass(top, t1);
7976 movptr(t1, top);
7977 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
7978 incr_allocated_bytes(thread_reg, t1, 0);
7980 // refill the tlab with an eden allocation
7981 bind(do_refill);
7982 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7983 shlptr(t1, LogHeapWordSize);
7984 // allocate new tlab, address returned in top
7985 eden_allocate(top, t1, 0, t2, slow_case);
7987 // Check that t1 was preserved in eden_allocate.
7988 #ifdef ASSERT
7989 if (UseTLAB) {
7990 Label ok;
7991 Register tsize = rsi;
7992 assert_different_registers(tsize, thread_reg, t1);
7993 push(tsize);
7994 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7995 shlptr(tsize, LogHeapWordSize);
7996 cmpptr(t1, tsize);
7997 jcc(Assembler::equal, ok);
7998 stop("assert(t1 != tlab size)");
7999 should_not_reach_here();
8001 bind(ok);
8002 pop(tsize);
8003 }
8004 #endif
8005 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
8006 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
8007 addptr(top, t1);
8008 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
8009 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
8010 verify_tlab();
8011 jmp(retry);
8013 return thread_reg; // for use by caller
8014 }
8016 void MacroAssembler::incr_allocated_bytes(Register thread,
8017 Register var_size_in_bytes,
8018 int con_size_in_bytes,
8019 Register t1) {
8020 if (!thread->is_valid()) {
8021 #ifdef _LP64
8022 thread = r15_thread;
8023 #else
8024 assert(t1->is_valid(), "need temp reg");
8025 thread = t1;
8026 get_thread(thread);
8027 #endif
8028 }
8030 #ifdef _LP64
8031 if (var_size_in_bytes->is_valid()) {
8032 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
8033 } else {
8034 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
8035 }
8036 #else
8037 if (var_size_in_bytes->is_valid()) {
8038 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
8039 } else {
8040 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
8041 }
8042 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
8043 #endif
8044 }
8046 static const double pi_4 = 0.7853981633974483;
8048 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
8049 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
8050 // was attempted in this code; unfortunately it appears that the
8051 // switch to 80-bit precision and back causes this to be
8052 // unprofitable compared with simply performing a runtime call if
8053 // the argument is out of the (-pi/4, pi/4) range.
8055 Register tmp = noreg;
8056 if (!VM_Version::supports_cmov()) {
8057 // fcmp needs a temporary so preserve rbx,
8058 tmp = rbx;
8059 push(tmp);
8060 }
8062 Label slow_case, done;
8064 ExternalAddress pi4_adr = (address)&pi_4;
8065 if (reachable(pi4_adr)) {
8066 // x ?<= pi/4
8067 fld_d(pi4_adr);
8068 fld_s(1); // Stack: X PI/4 X
8069 fabs(); // Stack: |X| PI/4 X
8070 fcmp(tmp);
8071 jcc(Assembler::above, slow_case);
8073 // fastest case: -pi/4 <= x <= pi/4
8074 switch(trig) {
8075 case 's':
8076 fsin();
8077 break;
8078 case 'c':
8079 fcos();
8080 break;
8081 case 't':
8082 ftan();
8083 break;
8084 default:
8085 assert(false, "bad intrinsic");
8086 break;
8087 }
8088 jmp(done);
8089 }
8091 // slow case: runtime call
8092 bind(slow_case);
8093 // Preserve registers across runtime call
8094 pusha();
8095 int incoming_argument_and_return_value_offset = -1;
8096 if (num_fpu_regs_in_use > 1) {
8097 // Must preserve all other FPU regs (could alternatively convert
8098 // SharedRuntime::dsin and dcos into assembly routines known not to trash
8099 // FPU state, but can not trust C compiler)
8100 NEEDS_CLEANUP;
8101 // NOTE that in this case we also push the incoming argument to
8102 // the stack and restore it later; we also use this stack slot to
8103 // hold the return value from dsin or dcos.
8104 for (int i = 0; i < num_fpu_regs_in_use; i++) {
8105 subptr(rsp, sizeof(jdouble));
8106 fstp_d(Address(rsp, 0));
8107 }
8108 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
8109 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
8110 }
8111 subptr(rsp, sizeof(jdouble));
8112 fstp_d(Address(rsp, 0));
8113 #ifdef _LP64
8114 movdbl(xmm0, Address(rsp, 0));
8115 #endif // _LP64
8117 // NOTE: we must not use call_VM_leaf here because that requires a
8118 // complete interpreter frame in debug mode -- same bug as 4387334
8119 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
8120 // do proper 64bit abi
8122 NEEDS_CLEANUP;
8123 // Need to add stack banging before this runtime call if it needs to
8124 // be taken; however, there is no generic stack banging routine at
8125 // the MacroAssembler level
8126 switch(trig) {
8127 case 's':
8128 {
8129 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
8130 }
8131 break;
8132 case 'c':
8133 {
8134 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
8135 }
8136 break;
8137 case 't':
8138 {
8139 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
8140 }
8141 break;
8142 default:
8143 assert(false, "bad intrinsic");
8144 break;
8145 }
8146 #ifdef _LP64
8147 movsd(Address(rsp, 0), xmm0);
8148 fld_d(Address(rsp, 0));
8149 #endif // _LP64
8150 addptr(rsp, sizeof(jdouble));
8151 if (num_fpu_regs_in_use > 1) {
8152 // Must save return value to stack and then restore entire FPU stack
8153 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
8154 for (int i = 0; i < num_fpu_regs_in_use; i++) {
8155 fld_d(Address(rsp, 0));
8156 addptr(rsp, sizeof(jdouble));
8157 }
8158 }
8159 popa();
8161 // Come here with result in F-TOS
8162 bind(done);
8164 if (tmp != noreg) {
8165 pop(tmp);
8166 }
8167 }
8170 // Look up the method for a megamorphic invokeinterface call.
8171 // The target method is determined by <intf_klass, itable_index>.
8172 // The receiver klass is in recv_klass.
8173 // On success, the result will be in method_result, and execution falls through.
8174 // On failure, execution transfers to the given label.
8175 void MacroAssembler::lookup_interface_method(Register recv_klass,
8176 Register intf_klass,
8177 RegisterOrConstant itable_index,
8178 Register method_result,
8179 Register scan_temp,
8180 Label& L_no_such_interface) {
8181 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
8182 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
8183 "caller must use same register for non-constant itable index as for method");
8185 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
8186 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
8187 int itentry_off = itableMethodEntry::method_offset_in_bytes();
8188 int scan_step = itableOffsetEntry::size() * wordSize;
8189 int vte_size = vtableEntry::size() * wordSize;
8190 Address::ScaleFactor times_vte_scale = Address::times_ptr;
8191 assert(vte_size == wordSize, "else adjust times_vte_scale");
8193 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize));
8195 // %%% Could store the aligned, prescaled offset in the klassoop.
8196 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
8197 if (HeapWordsPerLong > 1) {
8198 // Round up to align_object_offset boundary
8199 // see code for instanceKlass::start_of_itable!
8200 round_to(scan_temp, BytesPerLong);
8201 }
8203 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
8204 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
8205 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
8207 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
8208 // if (scan->interface() == intf) {
8209 // result = (klass + scan->offset() + itable_index);
8210 // }
8211 // }
8212 Label search, found_method;
8214 for (int peel = 1; peel >= 0; peel--) {
8215 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
8216 cmpptr(intf_klass, method_result);
8218 if (peel) {
8219 jccb(Assembler::equal, found_method);
8220 } else {
8221 jccb(Assembler::notEqual, search);
8222 // (invert the test to fall through to found_method...)
8223 }
8225 if (!peel) break;
8227 bind(search);
8229 // Check that the previous entry is non-null. A null entry means that
8230 // the receiver class doesn't implement the interface, and wasn't the
8231 // same as when the caller was compiled.
8232 testptr(method_result, method_result);
8233 jcc(Assembler::zero, L_no_such_interface);
8234 addptr(scan_temp, scan_step);
8235 }
8237 bind(found_method);
8239 // Got a hit.
8240 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
8241 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
8242 }
8245 void MacroAssembler::check_klass_subtype(Register sub_klass,
8246 Register super_klass,
8247 Register temp_reg,
8248 Label& L_success) {
8249 Label L_failure;
8250 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
8251 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
8252 bind(L_failure);
8253 }
8256 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
8257 Register super_klass,
8258 Register temp_reg,
8259 Label* L_success,
8260 Label* L_failure,
8261 Label* L_slow_path,
8262 RegisterOrConstant super_check_offset) {
8263 assert_different_registers(sub_klass, super_klass, temp_reg);
8264 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
8265 if (super_check_offset.is_register()) {
8266 assert_different_registers(sub_klass, super_klass,
8267 super_check_offset.as_register());
8268 } else if (must_load_sco) {
8269 assert(temp_reg != noreg, "supply either a temp or a register offset");
8270 }
8272 Label L_fallthrough;
8273 int label_nulls = 0;
8274 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
8275 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
8276 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
8277 assert(label_nulls <= 1, "at most one NULL in the batch");
8279 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
8280 int sco_offset = in_bytes(Klass::super_check_offset_offset());
8281 Address super_check_offset_addr(super_klass, sco_offset);
8283 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
8284 // range of a jccb. If this routine grows larger, reconsider at
8285 // least some of these.
8286 #define local_jcc(assembler_cond, label) \
8287 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
8288 else jcc( assembler_cond, label) /*omit semi*/
8290 // Hacked jmp, which may only be used just before L_fallthrough.
8291 #define final_jmp(label) \
8292 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
8293 else jmp(label) /*omit semi*/
8295 // If the pointers are equal, we are done (e.g., String[] elements).
8296 // This self-check enables sharing of secondary supertype arrays among
8297 // non-primary types such as array-of-interface. Otherwise, each such
8298 // type would need its own customized SSA.
8299 // We move this check to the front of the fast path because many
8300 // type checks are in fact trivially successful in this manner,
8301 // so we get a nicely predicted branch right at the start of the check.
8302 cmpptr(sub_klass, super_klass);
8303 local_jcc(Assembler::equal, *L_success);
8305 // Check the supertype display:
8306 if (must_load_sco) {
8307 // Positive movl does right thing on LP64.
8308 movl(temp_reg, super_check_offset_addr);
8309 super_check_offset = RegisterOrConstant(temp_reg);
8310 }
8311 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
8312 cmpptr(super_klass, super_check_addr); // load displayed supertype
8314 // This check has worked decisively for primary supers.
8315 // Secondary supers are sought in the super_cache ('super_cache_addr').
8316 // (Secondary supers are interfaces and very deeply nested subtypes.)
8317 // This works in the same check above because of a tricky aliasing
8318 // between the super_cache and the primary super display elements.
8319 // (The 'super_check_addr' can address either, as the case requires.)
8320 // Note that the cache is updated below if it does not help us find
8321 // what we need immediately.
8322 // So if it was a primary super, we can just fail immediately.
8323 // Otherwise, it's the slow path for us (no success at this point).
8325 if (super_check_offset.is_register()) {
8326 local_jcc(Assembler::equal, *L_success);
8327 cmpl(super_check_offset.as_register(), sc_offset);
8328 if (L_failure == &L_fallthrough) {
8329 local_jcc(Assembler::equal, *L_slow_path);
8330 } else {
8331 local_jcc(Assembler::notEqual, *L_failure);
8332 final_jmp(*L_slow_path);
8333 }
8334 } else if (super_check_offset.as_constant() == sc_offset) {
8335 // Need a slow path; fast failure is impossible.
8336 if (L_slow_path == &L_fallthrough) {
8337 local_jcc(Assembler::equal, *L_success);
8338 } else {
8339 local_jcc(Assembler::notEqual, *L_slow_path);
8340 final_jmp(*L_success);
8341 }
8342 } else {
8343 // No slow path; it's a fast decision.
8344 if (L_failure == &L_fallthrough) {
8345 local_jcc(Assembler::equal, *L_success);
8346 } else {
8347 local_jcc(Assembler::notEqual, *L_failure);
8348 final_jmp(*L_success);
8349 }
8350 }
8352 bind(L_fallthrough);
8354 #undef local_jcc
8355 #undef final_jmp
8356 }
8359 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
8360 Register super_klass,
8361 Register temp_reg,
8362 Register temp2_reg,
8363 Label* L_success,
8364 Label* L_failure,
8365 bool set_cond_codes) {
8366 assert_different_registers(sub_klass, super_klass, temp_reg);
8367 if (temp2_reg != noreg)
8368 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
8369 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
8371 Label L_fallthrough;
8372 int label_nulls = 0;
8373 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
8374 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
8375 assert(label_nulls <= 1, "at most one NULL in the batch");
8377 // a couple of useful fields in sub_klass:
8378 int ss_offset = in_bytes(Klass::secondary_supers_offset());
8379 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
8380 Address secondary_supers_addr(sub_klass, ss_offset);
8381 Address super_cache_addr( sub_klass, sc_offset);
8383 // Do a linear scan of the secondary super-klass chain.
8384 // This code is rarely used, so simplicity is a virtue here.
8385 // The repne_scan instruction uses fixed registers, which we must spill.
8386 // Don't worry too much about pre-existing connections with the input regs.
8388 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
8389 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
8391 // Get super_klass value into rax (even if it was in rdi or rcx).
8392 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
8393 if (super_klass != rax || UseCompressedOops) {
8394 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
8395 mov(rax, super_klass);
8396 }
8397 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
8398 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
8400 #ifndef PRODUCT
8401 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
8402 ExternalAddress pst_counter_addr((address) pst_counter);
8403 NOT_LP64( incrementl(pst_counter_addr) );
8404 LP64_ONLY( lea(rcx, pst_counter_addr) );
8405 LP64_ONLY( incrementl(Address(rcx, 0)) );
8406 #endif //PRODUCT
8408 // We will consult the secondary-super array.
8409 movptr(rdi, secondary_supers_addr);
8410 // Load the array length. (Positive movl does right thing on LP64.)
8411 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
8412 // Skip to start of data.
8413 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
8415 // Scan RCX words at [RDI] for an occurrence of RAX.
8416 // Set NZ/Z based on last compare.
8417 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
8418 // not change flags (only scas instruction which is repeated sets flags).
8419 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
8420 #ifdef _LP64
8421 // This part is tricky, as values in supers array could be 32 or 64 bit wide
8422 // and we store values in objArrays always encoded, thus we need to encode
8423 // the value of rax before repne. Note that rax is dead after the repne.
8424 if (UseCompressedOops) {
8425 encode_heap_oop_not_null(rax); // Changes flags.
8426 // The superclass is never null; it would be a basic system error if a null
8427 // pointer were to sneak in here. Note that we have already loaded the
8428 // Klass::super_check_offset from the super_klass in the fast path,
8429 // so if there is a null in that register, we are already in the afterlife.
8430 testl(rax,rax); // Set Z = 0
8431 repne_scanl();
8432 } else
8433 #endif // _LP64
8434 {
8435 testptr(rax,rax); // Set Z = 0
8436 repne_scan();
8437 }
8438 // Unspill the temp. registers:
8439 if (pushed_rdi) pop(rdi);
8440 if (pushed_rcx) pop(rcx);
8441 if (pushed_rax) pop(rax);
8443 if (set_cond_codes) {
8444 // Special hack for the AD files: rdi is guaranteed non-zero.
8445 assert(!pushed_rdi, "rdi must be left non-NULL");
8446 // Also, the condition codes are properly set Z/NZ on succeed/failure.
8447 }
8449 if (L_failure == &L_fallthrough)
8450 jccb(Assembler::notEqual, *L_failure);
8451 else jcc(Assembler::notEqual, *L_failure);
8453 // Success. Cache the super we found and proceed in triumph.
8454 movptr(super_cache_addr, super_klass);
8456 if (L_success != &L_fallthrough) {
8457 jmp(*L_success);
8458 }
8460 #undef IS_A_TEMP
8462 bind(L_fallthrough);
8463 }
8466 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
8467 if (VM_Version::supports_cmov()) {
8468 cmovl(cc, dst, src);
8469 } else {
8470 Label L;
8471 jccb(negate_condition(cc), L);
8472 movl(dst, src);
8473 bind(L);
8474 }
8475 }
8477 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
8478 if (VM_Version::supports_cmov()) {
8479 cmovl(cc, dst, src);
8480 } else {
8481 Label L;
8482 jccb(negate_condition(cc), L);
8483 movl(dst, src);
8484 bind(L);
8485 }
8486 }
8488 void MacroAssembler::verify_oop(Register reg, const char* s) {
8489 if (!VerifyOops) return;
8491 // Pass register number to verify_oop_subroutine
8492 char* b = new char[strlen(s) + 50];
8493 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
8494 #ifdef _LP64
8495 push(rscratch1); // save r10, trashed by movptr()
8496 #endif
8497 push(rax); // save rax,
8498 push(reg); // pass register argument
8499 ExternalAddress buffer((address) b);
8500 // avoid using pushptr, as it modifies scratch registers
8501 // and our contract is not to modify anything
8502 movptr(rax, buffer.addr());
8503 push(rax);
8504 // call indirectly to solve generation ordering problem
8505 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
8506 call(rax);
8507 // Caller pops the arguments (oop, message) and restores rax, r10
8508 }
8511 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
8512 Register tmp,
8513 int offset) {
8514 intptr_t value = *delayed_value_addr;
8515 if (value != 0)
8516 return RegisterOrConstant(value + offset);
8518 // load indirectly to solve generation ordering problem
8519 movptr(tmp, ExternalAddress((address) delayed_value_addr));
8521 #ifdef ASSERT
8522 { Label L;
8523 testptr(tmp, tmp);
8524 if (WizardMode) {
8525 jcc(Assembler::notZero, L);
8526 char* buf = new char[40];
8527 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
8528 stop(buf);
8529 } else {
8530 jccb(Assembler::notZero, L);
8531 hlt();
8532 }
8533 bind(L);
8534 }
8535 #endif
8537 if (offset != 0)
8538 addptr(tmp, offset);
8540 return RegisterOrConstant(tmp);
8541 }
8544 // registers on entry:
8545 // - rax ('check' register): required MethodType
8546 // - rcx: method handle
8547 // - rdx, rsi, or ?: killable temp
8548 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
8549 Register temp_reg,
8550 Label& wrong_method_type) {
8551 Address type_addr(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg));
8552 // compare method type against that of the receiver
8553 if (UseCompressedOops) {
8554 load_heap_oop(temp_reg, type_addr);
8555 cmpptr(mtype_reg, temp_reg);
8556 } else {
8557 cmpptr(mtype_reg, type_addr);
8558 }
8559 jcc(Assembler::notEqual, wrong_method_type);
8560 }
8563 // A method handle has a "vmslots" field which gives the size of its
8564 // argument list in JVM stack slots. This field is either located directly
8565 // in every method handle, or else is indirectly accessed through the
8566 // method handle's MethodType. This macro hides the distinction.
8567 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
8568 Register temp_reg) {
8569 assert_different_registers(vmslots_reg, mh_reg, temp_reg);
8570 // load mh.type.form.vmslots
8571 Register temp2_reg = vmslots_reg;
8572 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)));
8573 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg)));
8574 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)));
8575 }
8578 // registers on entry:
8579 // - rcx: method handle
8580 // - rdx: killable temp (interpreted only)
8581 // - rax: killable temp (compiled only)
8582 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) {
8583 assert(mh_reg == rcx, "caller must put MH object in rcx");
8584 assert_different_registers(mh_reg, temp_reg);
8586 // pick out the interpreted side of the handler
8587 // NOTE: vmentry is not an oop!
8588 movptr(temp_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmentry_offset_in_bytes, temp_reg)));
8590 // off we go...
8591 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes()));
8593 // for the various stubs which take control at this point,
8594 // see MethodHandles::generate_method_handle_stub
8595 }
8598 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
8599 int extra_slot_offset) {
8600 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
8601 int stackElementSize = Interpreter::stackElementSize;
8602 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
8603 #ifdef ASSERT
8604 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
8605 assert(offset1 - offset == stackElementSize, "correct arithmetic");
8606 #endif
8607 Register scale_reg = noreg;
8608 Address::ScaleFactor scale_factor = Address::no_scale;
8609 if (arg_slot.is_constant()) {
8610 offset += arg_slot.as_constant() * stackElementSize;
8611 } else {
8612 scale_reg = arg_slot.as_register();
8613 scale_factor = Address::times(stackElementSize);
8614 }
8615 offset += wordSize; // return PC is on stack
8616 return Address(rsp, scale_reg, scale_factor, offset);
8617 }
8620 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
8621 if (!VerifyOops) return;
8623 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
8624 // Pass register number to verify_oop_subroutine
8625 char* b = new char[strlen(s) + 50];
8626 sprintf(b, "verify_oop_addr: %s", s);
8628 #ifdef _LP64
8629 push(rscratch1); // save r10, trashed by movptr()
8630 #endif
8631 push(rax); // save rax,
8632 // addr may contain rsp so we will have to adjust it based on the push
8633 // we just did (and on 64 bit we do two pushes)
8634 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
8635 // stores rax into addr which is backwards of what was intended.
8636 if (addr.uses(rsp)) {
8637 lea(rax, addr);
8638 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
8639 } else {
8640 pushptr(addr);
8641 }
8643 ExternalAddress buffer((address) b);
8644 // pass msg argument
8645 // avoid using pushptr, as it modifies scratch registers
8646 // and our contract is not to modify anything
8647 movptr(rax, buffer.addr());
8648 push(rax);
8650 // call indirectly to solve generation ordering problem
8651 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
8652 call(rax);
8653 // Caller pops the arguments (addr, message) and restores rax, r10.
8654 }
8656 void MacroAssembler::verify_tlab() {
8657 #ifdef ASSERT
8658 if (UseTLAB && VerifyOops) {
8659 Label next, ok;
8660 Register t1 = rsi;
8661 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
8663 push(t1);
8664 NOT_LP64(push(thread_reg));
8665 NOT_LP64(get_thread(thread_reg));
8667 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
8668 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
8669 jcc(Assembler::aboveEqual, next);
8670 stop("assert(top >= start)");
8671 should_not_reach_here();
8673 bind(next);
8674 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
8675 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
8676 jcc(Assembler::aboveEqual, ok);
8677 stop("assert(top <= end)");
8678 should_not_reach_here();
8680 bind(ok);
8681 NOT_LP64(pop(thread_reg));
8682 pop(t1);
8683 }
8684 #endif
8685 }
8687 class ControlWord {
8688 public:
8689 int32_t _value;
8691 int rounding_control() const { return (_value >> 10) & 3 ; }
8692 int precision_control() const { return (_value >> 8) & 3 ; }
8693 bool precision() const { return ((_value >> 5) & 1) != 0; }
8694 bool underflow() const { return ((_value >> 4) & 1) != 0; }
8695 bool overflow() const { return ((_value >> 3) & 1) != 0; }
8696 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
8697 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
8698 bool invalid() const { return ((_value >> 0) & 1) != 0; }
8700 void print() const {
8701 // rounding control
8702 const char* rc;
8703 switch (rounding_control()) {
8704 case 0: rc = "round near"; break;
8705 case 1: rc = "round down"; break;
8706 case 2: rc = "round up "; break;
8707 case 3: rc = "chop "; break;
8708 };
8709 // precision control
8710 const char* pc;
8711 switch (precision_control()) {
8712 case 0: pc = "24 bits "; break;
8713 case 1: pc = "reserved"; break;
8714 case 2: pc = "53 bits "; break;
8715 case 3: pc = "64 bits "; break;
8716 };
8717 // flags
8718 char f[9];
8719 f[0] = ' ';
8720 f[1] = ' ';
8721 f[2] = (precision ()) ? 'P' : 'p';
8722 f[3] = (underflow ()) ? 'U' : 'u';
8723 f[4] = (overflow ()) ? 'O' : 'o';
8724 f[5] = (zero_divide ()) ? 'Z' : 'z';
8725 f[6] = (denormalized()) ? 'D' : 'd';
8726 f[7] = (invalid ()) ? 'I' : 'i';
8727 f[8] = '\x0';
8728 // output
8729 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
8730 }
8732 };
8734 class StatusWord {
8735 public:
8736 int32_t _value;
8738 bool busy() const { return ((_value >> 15) & 1) != 0; }
8739 bool C3() const { return ((_value >> 14) & 1) != 0; }
8740 bool C2() const { return ((_value >> 10) & 1) != 0; }
8741 bool C1() const { return ((_value >> 9) & 1) != 0; }
8742 bool C0() const { return ((_value >> 8) & 1) != 0; }
8743 int top() const { return (_value >> 11) & 7 ; }
8744 bool error_status() const { return ((_value >> 7) & 1) != 0; }
8745 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
8746 bool precision() const { return ((_value >> 5) & 1) != 0; }
8747 bool underflow() const { return ((_value >> 4) & 1) != 0; }
8748 bool overflow() const { return ((_value >> 3) & 1) != 0; }
8749 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
8750 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
8751 bool invalid() const { return ((_value >> 0) & 1) != 0; }
8753 void print() const {
8754 // condition codes
8755 char c[5];
8756 c[0] = (C3()) ? '3' : '-';
8757 c[1] = (C2()) ? '2' : '-';
8758 c[2] = (C1()) ? '1' : '-';
8759 c[3] = (C0()) ? '0' : '-';
8760 c[4] = '\x0';
8761 // flags
8762 char f[9];
8763 f[0] = (error_status()) ? 'E' : '-';
8764 f[1] = (stack_fault ()) ? 'S' : '-';
8765 f[2] = (precision ()) ? 'P' : '-';
8766 f[3] = (underflow ()) ? 'U' : '-';
8767 f[4] = (overflow ()) ? 'O' : '-';
8768 f[5] = (zero_divide ()) ? 'Z' : '-';
8769 f[6] = (denormalized()) ? 'D' : '-';
8770 f[7] = (invalid ()) ? 'I' : '-';
8771 f[8] = '\x0';
8772 // output
8773 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
8774 }
8776 };
8778 class TagWord {
8779 public:
8780 int32_t _value;
8782 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
8784 void print() const {
8785 printf("%04x", _value & 0xFFFF);
8786 }
8788 };
8790 class FPU_Register {
8791 public:
8792 int32_t _m0;
8793 int32_t _m1;
8794 int16_t _ex;
8796 bool is_indefinite() const {
8797 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
8798 }
8800 void print() const {
8801 char sign = (_ex < 0) ? '-' : '+';
8802 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
8803 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
8804 };
8806 };
8808 class FPU_State {
8809 public:
8810 enum {
8811 register_size = 10,
8812 number_of_registers = 8,
8813 register_mask = 7
8814 };
8816 ControlWord _control_word;
8817 StatusWord _status_word;
8818 TagWord _tag_word;
8819 int32_t _error_offset;
8820 int32_t _error_selector;
8821 int32_t _data_offset;
8822 int32_t _data_selector;
8823 int8_t _register[register_size * number_of_registers];
8825 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
8826 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
8828 const char* tag_as_string(int tag) const {
8829 switch (tag) {
8830 case 0: return "valid";
8831 case 1: return "zero";
8832 case 2: return "special";
8833 case 3: return "empty";
8834 }
8835 ShouldNotReachHere();
8836 return NULL;
8837 }
8839 void print() const {
8840 // print computation registers
8841 { int t = _status_word.top();
8842 for (int i = 0; i < number_of_registers; i++) {
8843 int j = (i - t) & register_mask;
8844 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
8845 st(j)->print();
8846 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
8847 }
8848 }
8849 printf("\n");
8850 // print control registers
8851 printf("ctrl = "); _control_word.print(); printf("\n");
8852 printf("stat = "); _status_word .print(); printf("\n");
8853 printf("tags = "); _tag_word .print(); printf("\n");
8854 }
8856 };
8858 class Flag_Register {
8859 public:
8860 int32_t _value;
8862 bool overflow() const { return ((_value >> 11) & 1) != 0; }
8863 bool direction() const { return ((_value >> 10) & 1) != 0; }
8864 bool sign() const { return ((_value >> 7) & 1) != 0; }
8865 bool zero() const { return ((_value >> 6) & 1) != 0; }
8866 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
8867 bool parity() const { return ((_value >> 2) & 1) != 0; }
8868 bool carry() const { return ((_value >> 0) & 1) != 0; }
8870 void print() const {
8871 // flags
8872 char f[8];
8873 f[0] = (overflow ()) ? 'O' : '-';
8874 f[1] = (direction ()) ? 'D' : '-';
8875 f[2] = (sign ()) ? 'S' : '-';
8876 f[3] = (zero ()) ? 'Z' : '-';
8877 f[4] = (auxiliary_carry()) ? 'A' : '-';
8878 f[5] = (parity ()) ? 'P' : '-';
8879 f[6] = (carry ()) ? 'C' : '-';
8880 f[7] = '\x0';
8881 // output
8882 printf("%08x flags = %s", _value, f);
8883 }
8885 };
8887 class IU_Register {
8888 public:
8889 int32_t _value;
8891 void print() const {
8892 printf("%08x %11d", _value, _value);
8893 }
8895 };
8897 class IU_State {
8898 public:
8899 Flag_Register _eflags;
8900 IU_Register _rdi;
8901 IU_Register _rsi;
8902 IU_Register _rbp;
8903 IU_Register _rsp;
8904 IU_Register _rbx;
8905 IU_Register _rdx;
8906 IU_Register _rcx;
8907 IU_Register _rax;
8909 void print() const {
8910 // computation registers
8911 printf("rax, = "); _rax.print(); printf("\n");
8912 printf("rbx, = "); _rbx.print(); printf("\n");
8913 printf("rcx = "); _rcx.print(); printf("\n");
8914 printf("rdx = "); _rdx.print(); printf("\n");
8915 printf("rdi = "); _rdi.print(); printf("\n");
8916 printf("rsi = "); _rsi.print(); printf("\n");
8917 printf("rbp, = "); _rbp.print(); printf("\n");
8918 printf("rsp = "); _rsp.print(); printf("\n");
8919 printf("\n");
8920 // control registers
8921 printf("flgs = "); _eflags.print(); printf("\n");
8922 }
8923 };
8926 class CPU_State {
8927 public:
8928 FPU_State _fpu_state;
8929 IU_State _iu_state;
8931 void print() const {
8932 printf("--------------------------------------------------\n");
8933 _iu_state .print();
8934 printf("\n");
8935 _fpu_state.print();
8936 printf("--------------------------------------------------\n");
8937 }
8939 };
8942 static void _print_CPU_state(CPU_State* state) {
8943 state->print();
8944 };
8947 void MacroAssembler::print_CPU_state() {
8948 push_CPU_state();
8949 push(rsp); // pass CPU state
8950 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
8951 addptr(rsp, wordSize); // discard argument
8952 pop_CPU_state();
8953 }
8956 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
8957 static int counter = 0;
8958 FPU_State* fs = &state->_fpu_state;
8959 counter++;
8960 // For leaf calls, only verify that the top few elements remain empty.
8961 // We only need 1 empty at the top for C2 code.
8962 if( stack_depth < 0 ) {
8963 if( fs->tag_for_st(7) != 3 ) {
8964 printf("FPR7 not empty\n");
8965 state->print();
8966 assert(false, "error");
8967 return false;
8968 }
8969 return true; // All other stack states do not matter
8970 }
8972 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
8973 "bad FPU control word");
8975 // compute stack depth
8976 int i = 0;
8977 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
8978 int d = i;
8979 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
8980 // verify findings
8981 if (i != FPU_State::number_of_registers) {
8982 // stack not contiguous
8983 printf("%s: stack not contiguous at ST%d\n", s, i);
8984 state->print();
8985 assert(false, "error");
8986 return false;
8987 }
8988 // check if computed stack depth corresponds to expected stack depth
8989 if (stack_depth < 0) {
8990 // expected stack depth is -stack_depth or less
8991 if (d > -stack_depth) {
8992 // too many elements on the stack
8993 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
8994 state->print();
8995 assert(false, "error");
8996 return false;
8997 }
8998 } else {
8999 // expected stack depth is stack_depth
9000 if (d != stack_depth) {
9001 // wrong stack depth
9002 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
9003 state->print();
9004 assert(false, "error");
9005 return false;
9006 }
9007 }
9008 // everything is cool
9009 return true;
9010 }
9013 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
9014 if (!VerifyFPU) return;
9015 push_CPU_state();
9016 push(rsp); // pass CPU state
9017 ExternalAddress msg((address) s);
9018 // pass message string s
9019 pushptr(msg.addr());
9020 push(stack_depth); // pass stack depth
9021 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
9022 addptr(rsp, 3 * wordSize); // discard arguments
9023 // check for error
9024 { Label L;
9025 testl(rax, rax);
9026 jcc(Assembler::notZero, L);
9027 int3(); // break if error condition
9028 bind(L);
9029 }
9030 pop_CPU_state();
9031 }
9033 void MacroAssembler::load_klass(Register dst, Register src) {
9034 #ifdef _LP64
9035 if (UseCompressedOops) {
9036 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9037 decode_heap_oop_not_null(dst);
9038 } else
9039 #endif
9040 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9041 }
9043 void MacroAssembler::load_prototype_header(Register dst, Register src) {
9044 #ifdef _LP64
9045 if (UseCompressedOops) {
9046 assert (Universe::heap() != NULL, "java heap should be initialized");
9047 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9048 if (Universe::narrow_oop_shift() != 0) {
9049 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9050 if (LogMinObjAlignmentInBytes == Address::times_8) {
9051 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset()));
9052 } else {
9053 // OK to use shift since we don't need to preserve flags.
9054 shlq(dst, LogMinObjAlignmentInBytes);
9055 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset()));
9056 }
9057 } else {
9058 movq(dst, Address(dst, Klass::prototype_header_offset()));
9059 }
9060 } else
9061 #endif
9062 {
9063 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
9064 movptr(dst, Address(dst, Klass::prototype_header_offset()));
9065 }
9066 }
9068 void MacroAssembler::store_klass(Register dst, Register src) {
9069 #ifdef _LP64
9070 if (UseCompressedOops) {
9071 encode_heap_oop_not_null(src);
9072 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
9073 } else
9074 #endif
9075 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
9076 }
9078 void MacroAssembler::load_heap_oop(Register dst, Address src) {
9079 #ifdef _LP64
9080 if (UseCompressedOops) {
9081 movl(dst, src);
9082 decode_heap_oop(dst);
9083 } else
9084 #endif
9085 movptr(dst, src);
9086 }
9088 // Doesn't do verfication, generates fixed size code
9089 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
9090 #ifdef _LP64
9091 if (UseCompressedOops) {
9092 movl(dst, src);
9093 decode_heap_oop_not_null(dst);
9094 } else
9095 #endif
9096 movptr(dst, src);
9097 }
9099 void MacroAssembler::store_heap_oop(Address dst, Register src) {
9100 #ifdef _LP64
9101 if (UseCompressedOops) {
9102 assert(!dst.uses(src), "not enough registers");
9103 encode_heap_oop(src);
9104 movl(dst, src);
9105 } else
9106 #endif
9107 movptr(dst, src);
9108 }
9110 // Used for storing NULLs.
9111 void MacroAssembler::store_heap_oop_null(Address dst) {
9112 #ifdef _LP64
9113 if (UseCompressedOops) {
9114 movl(dst, (int32_t)NULL_WORD);
9115 } else {
9116 movslq(dst, (int32_t)NULL_WORD);
9117 }
9118 #else
9119 movl(dst, (int32_t)NULL_WORD);
9120 #endif
9121 }
9123 #ifdef _LP64
9124 void MacroAssembler::store_klass_gap(Register dst, Register src) {
9125 if (UseCompressedOops) {
9126 // Store to klass gap in destination
9127 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
9128 }
9129 }
9131 #ifdef ASSERT
9132 void MacroAssembler::verify_heapbase(const char* msg) {
9133 assert (UseCompressedOops, "should be compressed");
9134 assert (Universe::heap() != NULL, "java heap should be initialized");
9135 if (CheckCompressedOops) {
9136 Label ok;
9137 push(rscratch1); // cmpptr trashes rscratch1
9138 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
9139 jcc(Assembler::equal, ok);
9140 stop(msg);
9141 bind(ok);
9142 pop(rscratch1);
9143 }
9144 }
9145 #endif
9147 // Algorithm must match oop.inline.hpp encode_heap_oop.
9148 void MacroAssembler::encode_heap_oop(Register r) {
9149 #ifdef ASSERT
9150 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
9151 #endif
9152 verify_oop(r, "broken oop in encode_heap_oop");
9153 if (Universe::narrow_oop_base() == NULL) {
9154 if (Universe::narrow_oop_shift() != 0) {
9155 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9156 shrq(r, LogMinObjAlignmentInBytes);
9157 }
9158 return;
9159 }
9160 testq(r, r);
9161 cmovq(Assembler::equal, r, r12_heapbase);
9162 subq(r, r12_heapbase);
9163 shrq(r, LogMinObjAlignmentInBytes);
9164 }
9166 void MacroAssembler::encode_heap_oop_not_null(Register r) {
9167 #ifdef ASSERT
9168 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
9169 if (CheckCompressedOops) {
9170 Label ok;
9171 testq(r, r);
9172 jcc(Assembler::notEqual, ok);
9173 stop("null oop passed to encode_heap_oop_not_null");
9174 bind(ok);
9175 }
9176 #endif
9177 verify_oop(r, "broken oop in encode_heap_oop_not_null");
9178 if (Universe::narrow_oop_base() != NULL) {
9179 subq(r, r12_heapbase);
9180 }
9181 if (Universe::narrow_oop_shift() != 0) {
9182 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9183 shrq(r, LogMinObjAlignmentInBytes);
9184 }
9185 }
9187 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
9188 #ifdef ASSERT
9189 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
9190 if (CheckCompressedOops) {
9191 Label ok;
9192 testq(src, src);
9193 jcc(Assembler::notEqual, ok);
9194 stop("null oop passed to encode_heap_oop_not_null2");
9195 bind(ok);
9196 }
9197 #endif
9198 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
9199 if (dst != src) {
9200 movq(dst, src);
9201 }
9202 if (Universe::narrow_oop_base() != NULL) {
9203 subq(dst, r12_heapbase);
9204 }
9205 if (Universe::narrow_oop_shift() != 0) {
9206 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9207 shrq(dst, LogMinObjAlignmentInBytes);
9208 }
9209 }
9211 void MacroAssembler::decode_heap_oop(Register r) {
9212 #ifdef ASSERT
9213 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
9214 #endif
9215 if (Universe::narrow_oop_base() == NULL) {
9216 if (Universe::narrow_oop_shift() != 0) {
9217 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9218 shlq(r, LogMinObjAlignmentInBytes);
9219 }
9220 } else {
9221 Label done;
9222 shlq(r, LogMinObjAlignmentInBytes);
9223 jccb(Assembler::equal, done);
9224 addq(r, r12_heapbase);
9225 bind(done);
9226 }
9227 verify_oop(r, "broken oop in decode_heap_oop");
9228 }
9230 void MacroAssembler::decode_heap_oop_not_null(Register r) {
9231 // Note: it will change flags
9232 assert (UseCompressedOops, "should only be used for compressed headers");
9233 assert (Universe::heap() != NULL, "java heap should be initialized");
9234 // Cannot assert, unverified entry point counts instructions (see .ad file)
9235 // vtableStubs also counts instructions in pd_code_size_limit.
9236 // Also do not verify_oop as this is called by verify_oop.
9237 if (Universe::narrow_oop_shift() != 0) {
9238 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9239 shlq(r, LogMinObjAlignmentInBytes);
9240 if (Universe::narrow_oop_base() != NULL) {
9241 addq(r, r12_heapbase);
9242 }
9243 } else {
9244 assert (Universe::narrow_oop_base() == NULL, "sanity");
9245 }
9246 }
9248 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
9249 // Note: it will change flags
9250 assert (UseCompressedOops, "should only be used for compressed headers");
9251 assert (Universe::heap() != NULL, "java heap should be initialized");
9252 // Cannot assert, unverified entry point counts instructions (see .ad file)
9253 // vtableStubs also counts instructions in pd_code_size_limit.
9254 // Also do not verify_oop as this is called by verify_oop.
9255 if (Universe::narrow_oop_shift() != 0) {
9256 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
9257 if (LogMinObjAlignmentInBytes == Address::times_8) {
9258 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
9259 } else {
9260 if (dst != src) {
9261 movq(dst, src);
9262 }
9263 shlq(dst, LogMinObjAlignmentInBytes);
9264 if (Universe::narrow_oop_base() != NULL) {
9265 addq(dst, r12_heapbase);
9266 }
9267 }
9268 } else {
9269 assert (Universe::narrow_oop_base() == NULL, "sanity");
9270 if (dst != src) {
9271 movq(dst, src);
9272 }
9273 }
9274 }
9276 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
9277 assert (UseCompressedOops, "should only be used for compressed headers");
9278 assert (Universe::heap() != NULL, "java heap should be initialized");
9279 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9280 int oop_index = oop_recorder()->find_index(obj);
9281 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9282 mov_narrow_oop(dst, oop_index, rspec);
9283 }
9285 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
9286 assert (UseCompressedOops, "should only be used for compressed headers");
9287 assert (Universe::heap() != NULL, "java heap should be initialized");
9288 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9289 int oop_index = oop_recorder()->find_index(obj);
9290 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9291 mov_narrow_oop(dst, oop_index, rspec);
9292 }
9294 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
9295 assert (UseCompressedOops, "should only be used for compressed headers");
9296 assert (Universe::heap() != NULL, "java heap should be initialized");
9297 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9298 int oop_index = oop_recorder()->find_index(obj);
9299 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9300 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
9301 }
9303 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
9304 assert (UseCompressedOops, "should only be used for compressed headers");
9305 assert (Universe::heap() != NULL, "java heap should be initialized");
9306 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
9307 int oop_index = oop_recorder()->find_index(obj);
9308 RelocationHolder rspec = oop_Relocation::spec(oop_index);
9309 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
9310 }
9312 void MacroAssembler::reinit_heapbase() {
9313 if (UseCompressedOops) {
9314 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
9315 }
9316 }
9317 #endif // _LP64
9320 // C2 compiled method's prolog code.
9321 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) {
9323 // WARNING: Initial instruction MUST be 5 bytes or longer so that
9324 // NativeJump::patch_verified_entry will be able to patch out the entry
9325 // code safely. The push to verify stack depth is ok at 5 bytes,
9326 // the frame allocation can be either 3 or 6 bytes. So if we don't do
9327 // stack bang then we must use the 6 byte frame allocation even if
9328 // we have no frame. :-(
9330 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
9331 // Remove word for return addr
9332 framesize -= wordSize;
9334 // Calls to C2R adapters often do not accept exceptional returns.
9335 // We require that their callers must bang for them. But be careful, because
9336 // some VM calls (such as call site linkage) can use several kilobytes of
9337 // stack. But the stack safety zone should account for that.
9338 // See bugs 4446381, 4468289, 4497237.
9339 if (stack_bang) {
9340 generate_stack_overflow_check(framesize);
9342 // We always push rbp, so that on return to interpreter rbp, will be
9343 // restored correctly and we can correct the stack.
9344 push(rbp);
9345 // Remove word for ebp
9346 framesize -= wordSize;
9348 // Create frame
9349 if (framesize) {
9350 subptr(rsp, framesize);
9351 }
9352 } else {
9353 // Create frame (force generation of a 4 byte immediate value)
9354 subptr_imm32(rsp, framesize);
9356 // Save RBP register now.
9357 framesize -= wordSize;
9358 movptr(Address(rsp, framesize), rbp);
9359 }
9361 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
9362 framesize -= wordSize;
9363 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
9364 }
9366 #ifndef _LP64
9367 // If method sets FPU control word do it now
9368 if (fp_mode_24b) {
9369 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
9370 }
9371 if (UseSSE >= 2 && VerifyFPU) {
9372 verify_FPU(0, "FPU stack must be clean on entry");
9373 }
9374 #endif
9376 #ifdef ASSERT
9377 if (VerifyStackAtCalls) {
9378 Label L;
9379 push(rax);
9380 mov(rax, rsp);
9381 andptr(rax, StackAlignmentInBytes-1);
9382 cmpptr(rax, StackAlignmentInBytes-wordSize);
9383 pop(rax);
9384 jcc(Assembler::equal, L);
9385 stop("Stack is not properly aligned!");
9386 bind(L);
9387 }
9388 #endif
9390 }
9393 // IndexOf for constant substrings with size >= 8 chars
9394 // which don't need to be loaded through stack.
9395 void MacroAssembler::string_indexofC8(Register str1, Register str2,
9396 Register cnt1, Register cnt2,
9397 int int_cnt2, Register result,
9398 XMMRegister vec, Register tmp) {
9399 ShortBranchVerifier sbv(this);
9400 assert(UseSSE42Intrinsics, "SSE4.2 is required");
9402 // This method uses pcmpestri inxtruction with bound registers
9403 // inputs:
9404 // xmm - substring
9405 // rax - substring length (elements count)
9406 // mem - scanned string
9407 // rdx - string length (elements count)
9408 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
9409 // outputs:
9410 // rcx - matched index in string
9411 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
9413 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
9414 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
9415 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
9417 // Note, inline_string_indexOf() generates checks:
9418 // if (substr.count > string.count) return -1;
9419 // if (substr.count == 0) return 0;
9420 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
9422 // Load substring.
9423 movdqu(vec, Address(str2, 0));
9424 movl(cnt2, int_cnt2);
9425 movptr(result, str1); // string addr
9427 if (int_cnt2 > 8) {
9428 jmpb(SCAN_TO_SUBSTR);
9430 // Reload substr for rescan, this code
9431 // is executed only for large substrings (> 8 chars)
9432 bind(RELOAD_SUBSTR);
9433 movdqu(vec, Address(str2, 0));
9434 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
9436 bind(RELOAD_STR);
9437 // We came here after the beginning of the substring was
9438 // matched but the rest of it was not so we need to search
9439 // again. Start from the next element after the previous match.
9441 // cnt2 is number of substring reminding elements and
9442 // cnt1 is number of string reminding elements when cmp failed.
9443 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
9444 subl(cnt1, cnt2);
9445 addl(cnt1, int_cnt2);
9446 movl(cnt2, int_cnt2); // Now restore cnt2
9448 decrementl(cnt1); // Shift to next element
9449 cmpl(cnt1, cnt2);
9450 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
9452 addptr(result, 2);
9454 } // (int_cnt2 > 8)
9456 // Scan string for start of substr in 16-byte vectors
9457 bind(SCAN_TO_SUBSTR);
9458 pcmpestri(vec, Address(result, 0), 0x0d);
9459 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
9460 subl(cnt1, 8);
9461 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
9462 cmpl(cnt1, cnt2);
9463 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
9464 addptr(result, 16);
9465 jmpb(SCAN_TO_SUBSTR);
9467 // Found a potential substr
9468 bind(FOUND_CANDIDATE);
9469 // Matched whole vector if first element matched (tmp(rcx) == 0).
9470 if (int_cnt2 == 8) {
9471 jccb(Assembler::overflow, RET_FOUND); // OF == 1
9472 } else { // int_cnt2 > 8
9473 jccb(Assembler::overflow, FOUND_SUBSTR);
9474 }
9475 // After pcmpestri tmp(rcx) contains matched element index
9476 // Compute start addr of substr
9477 lea(result, Address(result, tmp, Address::times_2));
9479 // Make sure string is still long enough
9480 subl(cnt1, tmp);
9481 cmpl(cnt1, cnt2);
9482 if (int_cnt2 == 8) {
9483 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
9484 } else { // int_cnt2 > 8
9485 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
9486 }
9487 // Left less then substring.
9489 bind(RET_NOT_FOUND);
9490 movl(result, -1);
9491 jmpb(EXIT);
9493 if (int_cnt2 > 8) {
9494 // This code is optimized for the case when whole substring
9495 // is matched if its head is matched.
9496 bind(MATCH_SUBSTR_HEAD);
9497 pcmpestri(vec, Address(result, 0), 0x0d);
9498 // Reload only string if does not match
9499 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
9501 Label CONT_SCAN_SUBSTR;
9502 // Compare the rest of substring (> 8 chars).
9503 bind(FOUND_SUBSTR);
9504 // First 8 chars are already matched.
9505 negptr(cnt2);
9506 addptr(cnt2, 8);
9508 bind(SCAN_SUBSTR);
9509 subl(cnt1, 8);
9510 cmpl(cnt2, -8); // Do not read beyond substring
9511 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
9512 // Back-up strings to avoid reading beyond substring:
9513 // cnt1 = cnt1 - cnt2 + 8
9514 addl(cnt1, cnt2); // cnt2 is negative
9515 addl(cnt1, 8);
9516 movl(cnt2, 8); negptr(cnt2);
9517 bind(CONT_SCAN_SUBSTR);
9518 if (int_cnt2 < (int)G) {
9519 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
9520 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
9521 } else {
9522 // calculate index in register to avoid integer overflow (int_cnt2*2)
9523 movl(tmp, int_cnt2);
9524 addptr(tmp, cnt2);
9525 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
9526 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
9527 }
9528 // Need to reload strings pointers if not matched whole vector
9529 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
9530 addptr(cnt2, 8);
9531 jcc(Assembler::negative, SCAN_SUBSTR);
9532 // Fall through if found full substring
9534 } // (int_cnt2 > 8)
9536 bind(RET_FOUND);
9537 // Found result if we matched full small substring.
9538 // Compute substr offset
9539 subptr(result, str1);
9540 shrl(result, 1); // index
9541 bind(EXIT);
9543 } // string_indexofC8
9545 // Small strings are loaded through stack if they cross page boundary.
9546 void MacroAssembler::string_indexof(Register str1, Register str2,
9547 Register cnt1, Register cnt2,
9548 int int_cnt2, Register result,
9549 XMMRegister vec, Register tmp) {
9550 ShortBranchVerifier sbv(this);
9551 assert(UseSSE42Intrinsics, "SSE4.2 is required");
9552 //
9553 // int_cnt2 is length of small (< 8 chars) constant substring
9554 // or (-1) for non constant substring in which case its length
9555 // is in cnt2 register.
9556 //
9557 // Note, inline_string_indexOf() generates checks:
9558 // if (substr.count > string.count) return -1;
9559 // if (substr.count == 0) return 0;
9560 //
9561 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
9563 // This method uses pcmpestri inxtruction with bound registers
9564 // inputs:
9565 // xmm - substring
9566 // rax - substring length (elements count)
9567 // mem - scanned string
9568 // rdx - string length (elements count)
9569 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
9570 // outputs:
9571 // rcx - matched index in string
9572 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
9574 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
9575 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
9576 FOUND_CANDIDATE;
9578 { //========================================================
9579 // We don't know where these strings are located
9580 // and we can't read beyond them. Load them through stack.
9581 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
9583 movptr(tmp, rsp); // save old SP
9585 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
9586 if (int_cnt2 == 1) { // One char
9587 load_unsigned_short(result, Address(str2, 0));
9588 movdl(vec, result); // move 32 bits
9589 } else if (int_cnt2 == 2) { // Two chars
9590 movdl(vec, Address(str2, 0)); // move 32 bits
9591 } else if (int_cnt2 == 4) { // Four chars
9592 movq(vec, Address(str2, 0)); // move 64 bits
9593 } else { // cnt2 = { 3, 5, 6, 7 }
9594 // Array header size is 12 bytes in 32-bit VM
9595 // + 6 bytes for 3 chars == 18 bytes,
9596 // enough space to load vec and shift.
9597 assert(HeapWordSize*typeArrayKlass::header_size() >= 12,"sanity");
9598 movdqu(vec, Address(str2, (int_cnt2*2)-16));
9599 psrldq(vec, 16-(int_cnt2*2));
9600 }
9601 } else { // not constant substring
9602 cmpl(cnt2, 8);
9603 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
9605 // We can read beyond string if srt+16 does not cross page boundary
9606 // since heaps are aligned and mapped by pages.
9607 assert(os::vm_page_size() < (int)G, "default page should be small");
9608 movl(result, str2); // We need only low 32 bits
9609 andl(result, (os::vm_page_size()-1));
9610 cmpl(result, (os::vm_page_size()-16));
9611 jccb(Assembler::belowEqual, CHECK_STR);
9613 // Move small strings to stack to allow load 16 bytes into vec.
9614 subptr(rsp, 16);
9615 int stk_offset = wordSize-2;
9616 push(cnt2);
9618 bind(COPY_SUBSTR);
9619 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
9620 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
9621 decrement(cnt2);
9622 jccb(Assembler::notZero, COPY_SUBSTR);
9624 pop(cnt2);
9625 movptr(str2, rsp); // New substring address
9626 } // non constant
9628 bind(CHECK_STR);
9629 cmpl(cnt1, 8);
9630 jccb(Assembler::aboveEqual, BIG_STRINGS);
9632 // Check cross page boundary.
9633 movl(result, str1); // We need only low 32 bits
9634 andl(result, (os::vm_page_size()-1));
9635 cmpl(result, (os::vm_page_size()-16));
9636 jccb(Assembler::belowEqual, BIG_STRINGS);
9638 subptr(rsp, 16);
9639 int stk_offset = -2;
9640 if (int_cnt2 < 0) { // not constant
9641 push(cnt2);
9642 stk_offset += wordSize;
9643 }
9644 movl(cnt2, cnt1);
9646 bind(COPY_STR);
9647 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
9648 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
9649 decrement(cnt2);
9650 jccb(Assembler::notZero, COPY_STR);
9652 if (int_cnt2 < 0) { // not constant
9653 pop(cnt2);
9654 }
9655 movptr(str1, rsp); // New string address
9657 bind(BIG_STRINGS);
9658 // Load substring.
9659 if (int_cnt2 < 0) { // -1
9660 movdqu(vec, Address(str2, 0));
9661 push(cnt2); // substr count
9662 push(str2); // substr addr
9663 push(str1); // string addr
9664 } else {
9665 // Small (< 8 chars) constant substrings are loaded already.
9666 movl(cnt2, int_cnt2);
9667 }
9668 push(tmp); // original SP
9670 } // Finished loading
9672 //========================================================
9673 // Start search
9674 //
9676 movptr(result, str1); // string addr
9678 if (int_cnt2 < 0) { // Only for non constant substring
9679 jmpb(SCAN_TO_SUBSTR);
9681 // SP saved at sp+0
9682 // String saved at sp+1*wordSize
9683 // Substr saved at sp+2*wordSize
9684 // Substr count saved at sp+3*wordSize
9686 // Reload substr for rescan, this code
9687 // is executed only for large substrings (> 8 chars)
9688 bind(RELOAD_SUBSTR);
9689 movptr(str2, Address(rsp, 2*wordSize));
9690 movl(cnt2, Address(rsp, 3*wordSize));
9691 movdqu(vec, Address(str2, 0));
9692 // We came here after the beginning of the substring was
9693 // matched but the rest of it was not so we need to search
9694 // again. Start from the next element after the previous match.
9695 subptr(str1, result); // Restore counter
9696 shrl(str1, 1);
9697 addl(cnt1, str1);
9698 decrementl(cnt1); // Shift to next element
9699 cmpl(cnt1, cnt2);
9700 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
9702 addptr(result, 2);
9703 } // non constant
9705 // Scan string for start of substr in 16-byte vectors
9706 bind(SCAN_TO_SUBSTR);
9707 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
9708 pcmpestri(vec, Address(result, 0), 0x0d);
9709 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
9710 subl(cnt1, 8);
9711 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
9712 cmpl(cnt1, cnt2);
9713 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
9714 addptr(result, 16);
9716 bind(ADJUST_STR);
9717 cmpl(cnt1, 8); // Do not read beyond string
9718 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
9719 // Back-up string to avoid reading beyond string.
9720 lea(result, Address(result, cnt1, Address::times_2, -16));
9721 movl(cnt1, 8);
9722 jmpb(SCAN_TO_SUBSTR);
9724 // Found a potential substr
9725 bind(FOUND_CANDIDATE);
9726 // After pcmpestri tmp(rcx) contains matched element index
9728 // Make sure string is still long enough
9729 subl(cnt1, tmp);
9730 cmpl(cnt1, cnt2);
9731 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
9732 // Left less then substring.
9734 bind(RET_NOT_FOUND);
9735 movl(result, -1);
9736 jmpb(CLEANUP);
9738 bind(FOUND_SUBSTR);
9739 // Compute start addr of substr
9740 lea(result, Address(result, tmp, Address::times_2));
9742 if (int_cnt2 > 0) { // Constant substring
9743 // Repeat search for small substring (< 8 chars)
9744 // from new point without reloading substring.
9745 // Have to check that we don't read beyond string.
9746 cmpl(tmp, 8-int_cnt2);
9747 jccb(Assembler::greater, ADJUST_STR);
9748 // Fall through if matched whole substring.
9749 } else { // non constant
9750 assert(int_cnt2 == -1, "should be != 0");
9752 addl(tmp, cnt2);
9753 // Found result if we matched whole substring.
9754 cmpl(tmp, 8);
9755 jccb(Assembler::lessEqual, RET_FOUND);
9757 // Repeat search for small substring (<= 8 chars)
9758 // from new point 'str1' without reloading substring.
9759 cmpl(cnt2, 8);
9760 // Have to check that we don't read beyond string.
9761 jccb(Assembler::lessEqual, ADJUST_STR);
9763 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
9764 // Compare the rest of substring (> 8 chars).
9765 movptr(str1, result);
9767 cmpl(tmp, cnt2);
9768 // First 8 chars are already matched.
9769 jccb(Assembler::equal, CHECK_NEXT);
9771 bind(SCAN_SUBSTR);
9772 pcmpestri(vec, Address(str1, 0), 0x0d);
9773 // Need to reload strings pointers if not matched whole vector
9774 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
9776 bind(CHECK_NEXT);
9777 subl(cnt2, 8);
9778 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
9779 addptr(str1, 16);
9780 addptr(str2, 16);
9781 subl(cnt1, 8);
9782 cmpl(cnt2, 8); // Do not read beyond substring
9783 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
9784 // Back-up strings to avoid reading beyond substring.
9785 lea(str2, Address(str2, cnt2, Address::times_2, -16));
9786 lea(str1, Address(str1, cnt2, Address::times_2, -16));
9787 subl(cnt1, cnt2);
9788 movl(cnt2, 8);
9789 addl(cnt1, 8);
9790 bind(CONT_SCAN_SUBSTR);
9791 movdqu(vec, Address(str2, 0));
9792 jmpb(SCAN_SUBSTR);
9794 bind(RET_FOUND_LONG);
9795 movptr(str1, Address(rsp, wordSize));
9796 } // non constant
9798 bind(RET_FOUND);
9799 // Compute substr offset
9800 subptr(result, str1);
9801 shrl(result, 1); // index
9803 bind(CLEANUP);
9804 pop(rsp); // restore SP
9806 } // string_indexof
9808 // Compare strings.
9809 void MacroAssembler::string_compare(Register str1, Register str2,
9810 Register cnt1, Register cnt2, Register result,
9811 XMMRegister vec1) {
9812 ShortBranchVerifier sbv(this);
9813 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
9815 // Compute the minimum of the string lengths and the
9816 // difference of the string lengths (stack).
9817 // Do the conditional move stuff
9818 movl(result, cnt1);
9819 subl(cnt1, cnt2);
9820 push(cnt1);
9821 cmov32(Assembler::lessEqual, cnt2, result);
9823 // Is the minimum length zero?
9824 testl(cnt2, cnt2);
9825 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
9827 // Load first characters
9828 load_unsigned_short(result, Address(str1, 0));
9829 load_unsigned_short(cnt1, Address(str2, 0));
9831 // Compare first characters
9832 subl(result, cnt1);
9833 jcc(Assembler::notZero, POP_LABEL);
9834 decrementl(cnt2);
9835 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
9837 {
9838 // Check after comparing first character to see if strings are equivalent
9839 Label LSkip2;
9840 // Check if the strings start at same location
9841 cmpptr(str1, str2);
9842 jccb(Assembler::notEqual, LSkip2);
9844 // Check if the length difference is zero (from stack)
9845 cmpl(Address(rsp, 0), 0x0);
9846 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
9848 // Strings might not be equivalent
9849 bind(LSkip2);
9850 }
9852 Address::ScaleFactor scale = Address::times_2;
9853 int stride = 8;
9855 // Advance to next element
9856 addptr(str1, 16/stride);
9857 addptr(str2, 16/stride);
9859 if (UseSSE42Intrinsics) {
9860 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
9861 int pcmpmask = 0x19;
9862 // Setup to compare 16-byte vectors
9863 movl(result, cnt2);
9864 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
9865 jccb(Assembler::zero, COMPARE_TAIL);
9867 lea(str1, Address(str1, result, scale));
9868 lea(str2, Address(str2, result, scale));
9869 negptr(result);
9871 // pcmpestri
9872 // inputs:
9873 // vec1- substring
9874 // rax - negative string length (elements count)
9875 // mem - scaned string
9876 // rdx - string length (elements count)
9877 // pcmpmask - cmp mode: 11000 (string compare with negated result)
9878 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
9879 // outputs:
9880 // rcx - first mismatched element index
9881 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
9883 bind(COMPARE_WIDE_VECTORS);
9884 movdqu(vec1, Address(str1, result, scale));
9885 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
9886 // After pcmpestri cnt1(rcx) contains mismatched element index
9888 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
9889 addptr(result, stride);
9890 subptr(cnt2, stride);
9891 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
9893 // compare wide vectors tail
9894 testl(result, result);
9895 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
9897 movl(cnt2, stride);
9898 movl(result, stride);
9899 negptr(result);
9900 movdqu(vec1, Address(str1, result, scale));
9901 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
9902 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
9904 // Mismatched characters in the vectors
9905 bind(VECTOR_NOT_EQUAL);
9906 addptr(result, cnt1);
9907 movptr(cnt2, result);
9908 load_unsigned_short(result, Address(str1, cnt2, scale));
9909 load_unsigned_short(cnt1, Address(str2, cnt2, scale));
9910 subl(result, cnt1);
9911 jmpb(POP_LABEL);
9913 bind(COMPARE_TAIL); // limit is zero
9914 movl(cnt2, result);
9915 // Fallthru to tail compare
9916 }
9918 // Shift str2 and str1 to the end of the arrays, negate min
9919 lea(str1, Address(str1, cnt2, scale, 0));
9920 lea(str2, Address(str2, cnt2, scale, 0));
9921 negptr(cnt2);
9923 // Compare the rest of the elements
9924 bind(WHILE_HEAD_LABEL);
9925 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
9926 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
9927 subl(result, cnt1);
9928 jccb(Assembler::notZero, POP_LABEL);
9929 increment(cnt2);
9930 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
9932 // Strings are equal up to min length. Return the length difference.
9933 bind(LENGTH_DIFF_LABEL);
9934 pop(result);
9935 jmpb(DONE_LABEL);
9937 // Discard the stored length difference
9938 bind(POP_LABEL);
9939 pop(cnt1);
9941 // That's it
9942 bind(DONE_LABEL);
9943 }
9945 // Compare char[] arrays aligned to 4 bytes or substrings.
9946 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
9947 Register limit, Register result, Register chr,
9948 XMMRegister vec1, XMMRegister vec2) {
9949 ShortBranchVerifier sbv(this);
9950 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
9952 int length_offset = arrayOopDesc::length_offset_in_bytes();
9953 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
9955 // Check the input args
9956 cmpptr(ary1, ary2);
9957 jcc(Assembler::equal, TRUE_LABEL);
9959 if (is_array_equ) {
9960 // Need additional checks for arrays_equals.
9961 testptr(ary1, ary1);
9962 jcc(Assembler::zero, FALSE_LABEL);
9963 testptr(ary2, ary2);
9964 jcc(Assembler::zero, FALSE_LABEL);
9966 // Check the lengths
9967 movl(limit, Address(ary1, length_offset));
9968 cmpl(limit, Address(ary2, length_offset));
9969 jcc(Assembler::notEqual, FALSE_LABEL);
9970 }
9972 // count == 0
9973 testl(limit, limit);
9974 jcc(Assembler::zero, TRUE_LABEL);
9976 if (is_array_equ) {
9977 // Load array address
9978 lea(ary1, Address(ary1, base_offset));
9979 lea(ary2, Address(ary2, base_offset));
9980 }
9982 shll(limit, 1); // byte count != 0
9983 movl(result, limit); // copy
9985 if (UseSSE42Intrinsics) {
9986 // With SSE4.2, use double quad vector compare
9987 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
9989 // Compare 16-byte vectors
9990 andl(result, 0x0000000e); // tail count (in bytes)
9991 andl(limit, 0xfffffff0); // vector count (in bytes)
9992 jccb(Assembler::zero, COMPARE_TAIL);
9994 lea(ary1, Address(ary1, limit, Address::times_1));
9995 lea(ary2, Address(ary2, limit, Address::times_1));
9996 negptr(limit);
9998 bind(COMPARE_WIDE_VECTORS);
9999 movdqu(vec1, Address(ary1, limit, Address::times_1));
10000 movdqu(vec2, Address(ary2, limit, Address::times_1));
10001 pxor(vec1, vec2);
10003 ptest(vec1, vec1);
10004 jccb(Assembler::notZero, FALSE_LABEL);
10005 addptr(limit, 16);
10006 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
10008 testl(result, result);
10009 jccb(Assembler::zero, TRUE_LABEL);
10011 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
10012 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
10013 pxor(vec1, vec2);
10015 ptest(vec1, vec1);
10016 jccb(Assembler::notZero, FALSE_LABEL);
10017 jmpb(TRUE_LABEL);
10019 bind(COMPARE_TAIL); // limit is zero
10020 movl(limit, result);
10021 // Fallthru to tail compare
10022 }
10024 // Compare 4-byte vectors
10025 andl(limit, 0xfffffffc); // vector count (in bytes)
10026 jccb(Assembler::zero, COMPARE_CHAR);
10028 lea(ary1, Address(ary1, limit, Address::times_1));
10029 lea(ary2, Address(ary2, limit, Address::times_1));
10030 negptr(limit);
10032 bind(COMPARE_VECTORS);
10033 movl(chr, Address(ary1, limit, Address::times_1));
10034 cmpl(chr, Address(ary2, limit, Address::times_1));
10035 jccb(Assembler::notEqual, FALSE_LABEL);
10036 addptr(limit, 4);
10037 jcc(Assembler::notZero, COMPARE_VECTORS);
10039 // Compare trailing char (final 2 bytes), if any
10040 bind(COMPARE_CHAR);
10041 testl(result, 0x2); // tail char
10042 jccb(Assembler::zero, TRUE_LABEL);
10043 load_unsigned_short(chr, Address(ary1, 0));
10044 load_unsigned_short(limit, Address(ary2, 0));
10045 cmpl(chr, limit);
10046 jccb(Assembler::notEqual, FALSE_LABEL);
10048 bind(TRUE_LABEL);
10049 movl(result, 1); // return true
10050 jmpb(DONE);
10052 bind(FALSE_LABEL);
10053 xorl(result, result); // return false
10055 // That's it
10056 bind(DONE);
10057 }
10059 #ifdef PRODUCT
10060 #define BLOCK_COMMENT(str) /* nothing */
10061 #else
10062 #define BLOCK_COMMENT(str) block_comment(str)
10063 #endif
10065 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
10066 void MacroAssembler::generate_fill(BasicType t, bool aligned,
10067 Register to, Register value, Register count,
10068 Register rtmp, XMMRegister xtmp) {
10069 ShortBranchVerifier sbv(this);
10070 assert_different_registers(to, value, count, rtmp);
10071 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
10072 Label L_fill_2_bytes, L_fill_4_bytes;
10074 int shift = -1;
10075 switch (t) {
10076 case T_BYTE:
10077 shift = 2;
10078 break;
10079 case T_SHORT:
10080 shift = 1;
10081 break;
10082 case T_INT:
10083 shift = 0;
10084 break;
10085 default: ShouldNotReachHere();
10086 }
10088 if (t == T_BYTE) {
10089 andl(value, 0xff);
10090 movl(rtmp, value);
10091 shll(rtmp, 8);
10092 orl(value, rtmp);
10093 }
10094 if (t == T_SHORT) {
10095 andl(value, 0xffff);
10096 }
10097 if (t == T_BYTE || t == T_SHORT) {
10098 movl(rtmp, value);
10099 shll(rtmp, 16);
10100 orl(value, rtmp);
10101 }
10103 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
10104 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
10105 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
10106 // align source address at 4 bytes address boundary
10107 if (t == T_BYTE) {
10108 // One byte misalignment happens only for byte arrays
10109 testptr(to, 1);
10110 jccb(Assembler::zero, L_skip_align1);
10111 movb(Address(to, 0), value);
10112 increment(to);
10113 decrement(count);
10114 BIND(L_skip_align1);
10115 }
10116 // Two bytes misalignment happens only for byte and short (char) arrays
10117 testptr(to, 2);
10118 jccb(Assembler::zero, L_skip_align2);
10119 movw(Address(to, 0), value);
10120 addptr(to, 2);
10121 subl(count, 1<<(shift-1));
10122 BIND(L_skip_align2);
10123 }
10124 if (UseSSE < 2) {
10125 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
10126 // Fill 32-byte chunks
10127 subl(count, 8 << shift);
10128 jcc(Assembler::less, L_check_fill_8_bytes);
10129 align(16);
10131 BIND(L_fill_32_bytes_loop);
10133 for (int i = 0; i < 32; i += 4) {
10134 movl(Address(to, i), value);
10135 }
10137 addptr(to, 32);
10138 subl(count, 8 << shift);
10139 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
10140 BIND(L_check_fill_8_bytes);
10141 addl(count, 8 << shift);
10142 jccb(Assembler::zero, L_exit);
10143 jmpb(L_fill_8_bytes);
10145 //
10146 // length is too short, just fill qwords
10147 //
10148 BIND(L_fill_8_bytes_loop);
10149 movl(Address(to, 0), value);
10150 movl(Address(to, 4), value);
10151 addptr(to, 8);
10152 BIND(L_fill_8_bytes);
10153 subl(count, 1 << (shift + 1));
10154 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
10155 // fall through to fill 4 bytes
10156 } else {
10157 Label L_fill_32_bytes;
10158 if (!UseUnalignedLoadStores) {
10159 // align to 8 bytes, we know we are 4 byte aligned to start
10160 testptr(to, 4);
10161 jccb(Assembler::zero, L_fill_32_bytes);
10162 movl(Address(to, 0), value);
10163 addptr(to, 4);
10164 subl(count, 1<<shift);
10165 }
10166 BIND(L_fill_32_bytes);
10167 {
10168 assert( UseSSE >= 2, "supported cpu only" );
10169 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
10170 // Fill 32-byte chunks
10171 movdl(xtmp, value);
10172 pshufd(xtmp, xtmp, 0);
10174 subl(count, 8 << shift);
10175 jcc(Assembler::less, L_check_fill_8_bytes);
10176 align(16);
10178 BIND(L_fill_32_bytes_loop);
10180 if (UseUnalignedLoadStores) {
10181 movdqu(Address(to, 0), xtmp);
10182 movdqu(Address(to, 16), xtmp);
10183 } else {
10184 movq(Address(to, 0), xtmp);
10185 movq(Address(to, 8), xtmp);
10186 movq(Address(to, 16), xtmp);
10187 movq(Address(to, 24), xtmp);
10188 }
10190 addptr(to, 32);
10191 subl(count, 8 << shift);
10192 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
10193 BIND(L_check_fill_8_bytes);
10194 addl(count, 8 << shift);
10195 jccb(Assembler::zero, L_exit);
10196 jmpb(L_fill_8_bytes);
10198 //
10199 // length is too short, just fill qwords
10200 //
10201 BIND(L_fill_8_bytes_loop);
10202 movq(Address(to, 0), xtmp);
10203 addptr(to, 8);
10204 BIND(L_fill_8_bytes);
10205 subl(count, 1 << (shift + 1));
10206 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
10207 }
10208 }
10209 // fill trailing 4 bytes
10210 BIND(L_fill_4_bytes);
10211 testl(count, 1<<shift);
10212 jccb(Assembler::zero, L_fill_2_bytes);
10213 movl(Address(to, 0), value);
10214 if (t == T_BYTE || t == T_SHORT) {
10215 addptr(to, 4);
10216 BIND(L_fill_2_bytes);
10217 // fill trailing 2 bytes
10218 testl(count, 1<<(shift-1));
10219 jccb(Assembler::zero, L_fill_byte);
10220 movw(Address(to, 0), value);
10221 if (t == T_BYTE) {
10222 addptr(to, 2);
10223 BIND(L_fill_byte);
10224 // fill trailing byte
10225 testl(count, 1);
10226 jccb(Assembler::zero, L_exit);
10227 movb(Address(to, 0), value);
10228 } else {
10229 BIND(L_fill_byte);
10230 }
10231 } else {
10232 BIND(L_fill_2_bytes);
10233 }
10234 BIND(L_exit);
10235 }
10236 #undef BIND
10237 #undef BLOCK_COMMENT
10240 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10241 switch (cond) {
10242 // Note some conditions are synonyms for others
10243 case Assembler::zero: return Assembler::notZero;
10244 case Assembler::notZero: return Assembler::zero;
10245 case Assembler::less: return Assembler::greaterEqual;
10246 case Assembler::lessEqual: return Assembler::greater;
10247 case Assembler::greater: return Assembler::lessEqual;
10248 case Assembler::greaterEqual: return Assembler::less;
10249 case Assembler::below: return Assembler::aboveEqual;
10250 case Assembler::belowEqual: return Assembler::above;
10251 case Assembler::above: return Assembler::belowEqual;
10252 case Assembler::aboveEqual: return Assembler::below;
10253 case Assembler::overflow: return Assembler::noOverflow;
10254 case Assembler::noOverflow: return Assembler::overflow;
10255 case Assembler::negative: return Assembler::positive;
10256 case Assembler::positive: return Assembler::negative;
10257 case Assembler::parity: return Assembler::noParity;
10258 case Assembler::noParity: return Assembler::parity;
10259 }
10260 ShouldNotReachHere(); return Assembler::overflow;
10261 }
10263 SkipIfEqual::SkipIfEqual(
10264 MacroAssembler* masm, const bool* flag_addr, bool value) {
10265 _masm = masm;
10266 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10267 _masm->jcc(Assembler::equal, _label);
10268 }
10270 SkipIfEqual::~SkipIfEqual() {
10271 _masm->bind(_label);
10272 }