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src/share/vm/c1/c1_LIR.cpp@eef07cd490d4
src/share/vm/c1/c1_LIR.cpp
Wed, 03 Jul 2019 20:42:37 +0800
- author
- aoqi
- date
- Wed, 03 Jul 2019 20:42:37 +0800
- changeset 9637
- eef07cd490d4
- parent 9251
- 1ccc5a3b3671
- child 9806
- 758c07667682
- permissions
- -rw-r--r--
Merge
1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015, 2018. These
27 * modifications are Copyright (c) 2015, 2018, Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #include "precompiled.hpp"
32 #include "c1/c1_InstructionPrinter.hpp"
33 #include "c1/c1_LIR.hpp"
34 #include "c1/c1_LIRAssembler.hpp"
35 #include "c1/c1_ValueStack.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "runtime/sharedRuntime.hpp"
39 Register LIR_OprDesc::as_register() const {
40 return FrameMap::cpu_rnr2reg(cpu_regnr());
41 }
43 Register LIR_OprDesc::as_register_lo() const {
44 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
45 }
47 Register LIR_OprDesc::as_register_hi() const {
48 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
49 }
51 #if defined(X86)
53 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
54 return FrameMap::nr2xmmreg(xmm_regnr());
55 }
57 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
58 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
59 return FrameMap::nr2xmmreg(xmm_regnrLo());
60 }
62 #endif // X86
64 #if defined(SPARC) || defined(PPC) || defined(MIPS)
66 FloatRegister LIR_OprDesc::as_float_reg() const {
67 return FrameMap::nr2floatreg(fpu_regnr());
68 }
70 FloatRegister LIR_OprDesc::as_double_reg() const {
71 return FrameMap::nr2floatreg(fpu_regnrHi());
72 }
74 #endif
76 #ifdef ARM
78 FloatRegister LIR_OprDesc::as_float_reg() const {
79 return as_FloatRegister(fpu_regnr());
80 }
82 FloatRegister LIR_OprDesc::as_double_reg() const {
83 return as_FloatRegister(fpu_regnrLo());
84 }
86 #endif
89 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
91 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
92 ValueTag tag = type->tag();
93 switch (tag) {
94 case metaDataTag : {
95 ClassConstant* c = type->as_ClassConstant();
96 if (c != NULL && !c->value()->is_loaded()) {
97 return LIR_OprFact::metadataConst(NULL);
98 } else if (c != NULL) {
99 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
100 } else {
101 MethodConstant* m = type->as_MethodConstant();
102 assert (m != NULL, "not a class or a method?");
103 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
104 }
105 }
106 case objectTag : {
107 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
108 }
109 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
110 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
111 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
112 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
113 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 }
119 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
120 switch (type->tag()) {
121 case objectTag: return LIR_OprFact::oopConst(NULL);
122 case addressTag:return LIR_OprFact::addressConst(0);
123 case intTag: return LIR_OprFact::intConst(0);
124 case floatTag: return LIR_OprFact::floatConst(0.0);
125 case longTag: return LIR_OprFact::longConst(0);
126 case doubleTag: return LIR_OprFact::doubleConst(0.0);
127 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
128 }
129 return illegalOpr;
130 }
134 //---------------------------------------------------
137 LIR_Address::Scale LIR_Address::scale(BasicType type) {
138 int elem_size = type2aelembytes(type);
139 switch (elem_size) {
140 case 1: return LIR_Address::times_1;
141 case 2: return LIR_Address::times_2;
142 case 4: return LIR_Address::times_4;
143 case 8: return LIR_Address::times_8;
144 }
145 ShouldNotReachHere();
146 return LIR_Address::times_1;
147 }
150 #ifndef PRODUCT
151 void LIR_Address::verify0() const {
152 #if defined(SPARC) || defined(PPC) || defined(MIPS)
153 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
154 assert(disp() == 0 || index()->is_illegal(), "can't have both");
155 #endif
156 #ifdef _LP64
157 assert(base()->is_cpu_register(), "wrong base operand");
158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
159 #ifndef MIPS
160 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
161 "wrong type for addresses");
162 #endif
163 #else
164 assert(base()->is_single_cpu(), "wrong base operand");
165 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
166 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
167 "wrong type for addresses");
168 #endif
169 }
170 #endif
173 //---------------------------------------------------
175 char LIR_OprDesc::type_char(BasicType t) {
176 switch (t) {
177 case T_ARRAY:
178 t = T_OBJECT;
179 case T_BOOLEAN:
180 case T_CHAR:
181 case T_FLOAT:
182 case T_DOUBLE:
183 case T_BYTE:
184 case T_SHORT:
185 case T_INT:
186 case T_LONG:
187 case T_OBJECT:
188 case T_ADDRESS:
189 case T_VOID:
190 return ::type2char(t);
191 case T_METADATA:
192 return 'M';
193 case T_ILLEGAL:
194 return '?';
196 default:
197 ShouldNotReachHere();
198 return '?';
199 }
200 }
202 #ifndef PRODUCT
203 void LIR_OprDesc::validate_type() const {
205 #ifdef ASSERT
206 if (!is_pointer() && !is_illegal()) {
207 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
208 switch (as_BasicType(type_field())) {
209 case T_LONG:
210 assert((kindfield == cpu_register || kindfield == stack_value) &&
211 size_field() == double_size, "must match");
212 break;
213 case T_FLOAT:
214 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
215 assert((kindfield == fpu_register || kindfield == stack_value
216 ARM_ONLY(|| kindfield == cpu_register)
217 PPC_ONLY(|| kindfield == cpu_register) ) &&
218 size_field() == single_size, "must match");
219 break;
220 case T_DOUBLE:
221 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
222 assert((kindfield == fpu_register || kindfield == stack_value
223 ARM_ONLY(|| kindfield == cpu_register)
224 PPC_ONLY(|| kindfield == cpu_register) ) &&
225 size_field() == double_size, "must match");
226 break;
227 case T_BOOLEAN:
228 case T_CHAR:
229 case T_BYTE:
230 case T_SHORT:
231 case T_INT:
232 case T_ADDRESS:
233 case T_OBJECT:
234 case T_METADATA:
235 case T_ARRAY:
236 assert((kindfield == cpu_register || kindfield == stack_value) &&
237 size_field() == single_size, "must match");
238 break;
240 case T_ILLEGAL:
241 // XXX TKR also means unknown right now
242 // assert(is_illegal(), "must match");
243 break;
245 default:
246 ShouldNotReachHere();
247 }
248 }
249 #endif
251 }
252 #endif // PRODUCT
255 bool LIR_OprDesc::is_oop() const {
256 if (is_pointer()) {
257 return pointer()->is_oop_pointer();
258 } else {
259 OprType t= type_field();
260 assert(t != unknown_type, "not set");
261 return t == object_type;
262 }
263 }
265 #ifdef MIPS
266 bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
267 if (!(is_register() && opr->is_register())) return false;
269 if (is_single_cpu()) {
270 if (opr->is_single_cpu()) {
271 return as_register() == opr->as_register();
272 } else if (opr->is_double_cpu()) {
273 Register dst = as_register();
274 Register lo = opr->as_register_lo();
275 #ifdef _LP64
276 if (dst == lo) return true;
277 #else
278 Register hi = opr->as_register_hi();
279 if (dst == lo || dst == hi) return true;
280 #endif
281 }
283 } else if (is_double_cpu()) {
284 Register dst_lo = as_register_lo();
285 #ifndef _LP64
286 Register dst_hi = as_register_hi();
287 #endif
289 if (opr->is_single_cpu()) {
290 Register src = opr->as_register();
291 #ifndef _LP64
292 if (dst_lo == src || dst_hi == src) return true;
293 #else
294 if (dst_lo == src) return true;
295 #endif
296 } else if (opr->is_double_cpu()) {
297 Register src_lo = opr->as_register_lo();
298 #ifndef _LP64
299 Register src_hi = opr->as_register_hi();
300 if (dst_lo == src_lo ||
301 dst_lo == src_hi ||
302 dst_hi == src_lo ||
303 dst_hi == src_hi) return true;
304 #else
305 if (dst_lo == src_lo) return true;
306 #endif
307 }
308 } else if (is_double_fpu()) {
309 if (opr->is_double_fpu()) {
310 return as_double_reg() == opr->as_double_reg();
311 } else if (opr->is_single_fpu()) {
312 return as_double_reg() == opr->as_float_reg();
313 }
314 } else if (is_single_fpu()) {
315 if (opr->is_single_fpu()) {
316 return as_float_reg() == opr->as_float_reg();
317 } else if (opr->is_double_fpu()) {
318 return as_float_reg() == opr->as_double_reg();
319 }
320 }
321 return false;
322 }
323 #endif
325 void LIR_Op2::verify() const {
326 #ifdef ASSERT
327 switch (code()) {
328 case lir_cmove:
329 case lir_xchg:
330 break;
332 default:
333 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
334 "can't produce oops from arith");
335 }
337 if (TwoOperandLIRForm) {
338 switch (code()) {
339 case lir_add:
340 case lir_sub:
341 case lir_mul:
342 case lir_mul_strictfp:
343 case lir_div:
344 case lir_div_strictfp:
345 case lir_rem:
346 case lir_logic_and:
347 case lir_logic_or:
348 case lir_logic_xor:
349 case lir_shl:
350 case lir_shr:
351 assert(in_opr1() == result_opr(), "opr1 and result must match");
352 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
353 break;
355 // special handling for lir_ushr because of write barriers
356 case lir_ushr:
357 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
358 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
359 break;
361 }
362 }
363 #endif
364 }
367 #ifndef MIPS
368 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
369 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
370 , _cond(cond)
371 , _type(type)
372 , _label(block->label())
373 , _block(block)
374 , _ublock(NULL)
375 , _stub(NULL) {
376 }
378 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
379 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
380 , _cond(cond)
381 , _type(type)
382 , _label(stub->entry())
383 , _block(NULL)
384 , _ublock(NULL)
385 , _stub(stub) {
386 }
388 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
389 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
390 , _cond(cond)
391 , _type(type)
392 , _label(block->label())
393 , _block(block)
394 , _ublock(ublock)
395 , _stub(NULL)
396 {
397 }
399 #else
400 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
401 BlockBegin* block):
402 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
403 _cond(cond),
404 _type(type),
405 _label(block->label()),
406 _block(block),
407 _ublock(NULL),
408 _stub(NULL) {
409 }
411 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
412 CodeStub* stub):
413 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
414 _cond(cond),
415 _type(type),
416 _label(stub->entry()),
417 _block(NULL),
418 _ublock(NULL),
419 _stub(stub) {
420 }
423 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BasicType type,
424 BlockBegin *block, BlockBegin *ublock):
425 LIR_Op2(lir_branch, left, right, LIR_OprFact::illegalOpr, (CodeEmitInfo *)(NULL)),
426 _cond(cond),
427 _type(type),
428 _label(block->label()),
429 _block(block),
430 _ublock(ublock),
431 _stub(NULL) {
432 }
434 #endif
435 void LIR_OpBranch::change_block(BlockBegin* b) {
436 assert(_block != NULL, "must have old block");
437 assert(_block->label() == label(), "must be equal");
439 _block = b;
440 _label = b->label();
441 }
443 void LIR_OpBranch::change_ublock(BlockBegin* b) {
444 assert(_ublock != NULL, "must have old block");
445 _ublock = b;
446 }
448 void LIR_OpBranch::negate_cond() {
449 switch (_cond) {
450 case lir_cond_equal: _cond = lir_cond_notEqual; break;
451 case lir_cond_notEqual: _cond = lir_cond_equal; break;
452 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
453 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
454 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
455 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
456 default: ShouldNotReachHere();
457 }
458 }
461 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
462 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
463 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
464 CodeStub* stub)
466 : LIR_Op(code, result, NULL)
467 , _object(object)
468 , _array(LIR_OprFact::illegalOpr)
469 , _klass(klass)
470 , _tmp1(tmp1)
471 , _tmp2(tmp2)
472 , _tmp3(tmp3)
473 , _fast_check(fast_check)
474 , _stub(stub)
475 , _info_for_patch(info_for_patch)
476 , _info_for_exception(info_for_exception)
477 , _profiled_method(NULL)
478 , _profiled_bci(-1)
479 , _should_profile(false)
480 {
481 if (code == lir_checkcast) {
482 assert(info_for_exception != NULL, "checkcast throws exceptions");
483 } else if (code == lir_instanceof) {
484 assert(info_for_exception == NULL, "instanceof throws no exceptions");
485 } else {
486 ShouldNotReachHere();
487 }
488 }
492 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
493 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
494 , _object(object)
495 , _array(array)
496 , _klass(NULL)
497 , _tmp1(tmp1)
498 , _tmp2(tmp2)
499 , _tmp3(tmp3)
500 , _fast_check(false)
501 , _stub(NULL)
502 , _info_for_patch(NULL)
503 , _info_for_exception(info_for_exception)
504 , _profiled_method(NULL)
505 , _profiled_bci(-1)
506 , _should_profile(false)
507 {
508 if (code == lir_store_check) {
509 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
510 assert(info_for_exception != NULL, "store_check throws exceptions");
511 } else {
512 ShouldNotReachHere();
513 }
514 }
517 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
518 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
519 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
520 , _tmp(tmp)
521 , _src(src)
522 , _src_pos(src_pos)
523 , _dst(dst)
524 , _dst_pos(dst_pos)
525 , _flags(flags)
526 , _expected_type(expected_type)
527 , _length(length) {
528 _stub = new ArrayCopyStub(this);
529 }
531 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
532 : LIR_Op(lir_updatecrc32, res, NULL)
533 , _crc(crc)
534 , _val(val) {
535 }
537 //-------------------verify--------------------------
539 void LIR_Op1::verify() const {
540 switch(code()) {
541 case lir_move:
542 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
543 break;
544 case lir_null_check:
545 assert(in_opr()->is_register(), "must be");
546 break;
547 case lir_return:
548 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
549 break;
550 }
551 }
553 void LIR_OpRTCall::verify() const {
554 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
555 }
557 //-------------------visits--------------------------
559 // complete rework of LIR instruction visitor.
560 // The virtual call for each instruction type is replaced by a big
561 // switch that adds the operands for each instruction
563 void LIR_OpVisitState::visit(LIR_Op* op) {
564 // copy information from the LIR_Op
565 reset();
566 set_op(op);
568 switch (op->code()) {
570 // LIR_Op0
571 case lir_word_align: // result and info always invalid
572 case lir_backwardbranch_target: // result and info always invalid
573 case lir_build_frame: // result and info always invalid
574 case lir_fpop_raw: // result and info always invalid
575 case lir_24bit_FPU: // result and info always invalid
576 case lir_reset_FPU: // result and info always invalid
577 case lir_breakpoint: // result and info always invalid
578 case lir_membar: // result and info always invalid
579 case lir_membar_acquire: // result and info always invalid
580 case lir_membar_release: // result and info always invalid
581 case lir_membar_loadload: // result and info always invalid
582 case lir_membar_storestore: // result and info always invalid
583 case lir_membar_loadstore: // result and info always invalid
584 case lir_membar_storeload: // result and info always invalid
585 {
586 assert(op->as_Op0() != NULL, "must be");
587 assert(op->_info == NULL, "info not used by this instruction");
588 assert(op->_result->is_illegal(), "not used");
589 break;
590 }
592 case lir_nop: // may have info, result always invalid
593 case lir_std_entry: // may have result, info always invalid
594 case lir_osr_entry: // may have result, info always invalid
595 case lir_get_thread: // may have result, info always invalid
596 {
597 assert(op->as_Op0() != NULL, "must be");
598 if (op->_info != NULL) do_info(op->_info);
599 if (op->_result->is_valid()) do_output(op->_result);
600 break;
601 }
604 // LIR_OpLabel
605 case lir_label: // result and info always invalid
606 {
607 assert(op->as_OpLabel() != NULL, "must be");
608 assert(op->_info == NULL, "info not used by this instruction");
609 assert(op->_result->is_illegal(), "not used");
610 break;
611 }
614 // LIR_Op1
615 case lir_fxch: // input always valid, result and info always invalid
616 case lir_fld: // input always valid, result and info always invalid
617 case lir_ffree: // input always valid, result and info always invalid
618 case lir_push: // input always valid, result and info always invalid
619 case lir_pop: // input always valid, result and info always invalid
620 case lir_return: // input always valid, result and info always invalid
621 case lir_leal: // input and result always valid, info always invalid
622 case lir_neg: // input and result always valid, info always invalid
623 case lir_monaddr: // input and result always valid, info always invalid
624 case lir_null_check: // input and info always valid, result always invalid
625 case lir_move: // input and result always valid, may have info
626 case lir_pack64: // input and result always valid
627 case lir_unpack64: // input and result always valid
628 case lir_prefetchr: // input always valid, result and info always invalid
629 case lir_prefetchw: // input always valid, result and info always invalid
630 {
631 assert(op->as_Op1() != NULL, "must be");
632 LIR_Op1* op1 = (LIR_Op1*)op;
634 if (op1->_info) do_info(op1->_info);
635 if (op1->_opr->is_valid()) do_input(op1->_opr);
636 if (op1->_result->is_valid()) do_output(op1->_result);
638 break;
639 }
641 case lir_safepoint:
642 {
643 assert(op->as_Op1() != NULL, "must be");
644 LIR_Op1* op1 = (LIR_Op1*)op;
646 assert(op1->_info != NULL, ""); do_info(op1->_info);
647 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
648 assert(op1->_result->is_illegal(), "safepoint does not produce value");
650 break;
651 }
653 // LIR_OpConvert;
654 case lir_convert: // input and result always valid, info always invalid
655 {
656 assert(op->as_OpConvert() != NULL, "must be");
657 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
659 assert(opConvert->_info == NULL, "must be");
660 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
661 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
662 #ifdef PPC
663 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
664 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
665 #endif
666 do_stub(opConvert->_stub);
668 break;
669 }
671 // LIR_OpBranch;
672 case lir_branch: // may have info, input and result register always invalid
673 case lir_cond_float_branch: // may have info, input and result register always invalid
674 {
675 assert(op->as_OpBranch() != NULL, "must be");
676 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
678 #ifdef MIPS
679 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
680 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
681 if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
682 if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
683 if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
684 if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
685 if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
686 #endif
687 if (opBranch->_info != NULL) do_info(opBranch->_info);
688 assert(opBranch->_result->is_illegal(), "not used");
689 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
691 break;
692 }
694 #ifdef MIPS
695 case lir_cmove_mips:
696 {
697 assert(op->as_Op4() != NULL, "must be");
698 LIR_Op4* op4 = (LIR_Op4*)op;
700 assert(op4->_info == NULL, "must be");
701 assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_opr3->is_valid() && op4->_opr4->is_valid() && op4->_result->is_valid(), "used");
703 do_input(op4->_opr1);
704 do_input(op4->_opr2);
705 do_input(op4->_opr3);
706 do_input(op4->_opr4);
707 if (op4->_tmp1->is_valid()) do_temp(op4->_tmp1);
708 if (op4->_tmp2->is_valid()) do_temp(op4->_tmp2);
709 if (op4->_tmp3->is_valid()) do_temp(op4->_tmp3);
710 if (op4->_tmp4->is_valid()) do_temp(op4->_tmp4);
711 if (op4->_tmp5->is_valid()) do_temp(op4->_tmp5);
712 do_output(op4->_result);
714 break;
715 }
716 #endif
718 // LIR_OpAllocObj
719 case lir_alloc_object:
720 {
721 assert(op->as_OpAllocObj() != NULL, "must be");
722 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
724 if (opAllocObj->_info) do_info(opAllocObj->_info);
725 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
726 do_temp(opAllocObj->_opr);
727 }
728 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
729 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
730 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
731 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
732 #ifdef MIPS
733 if (opAllocObj->_tmp5->is_valid()) do_temp(opAllocObj->_tmp5);
734 if (opAllocObj->_tmp6->is_valid()) do_temp(opAllocObj->_tmp6);
735 #endif
736 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
737 do_stub(opAllocObj->_stub);
738 break;
739 }
742 // LIR_OpRoundFP;
743 case lir_roundfp: {
744 assert(op->as_OpRoundFP() != NULL, "must be");
745 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
747 assert(op->_info == NULL, "info not used by this instruction");
748 assert(opRoundFP->_tmp->is_illegal(), "not used");
749 do_input(opRoundFP->_opr);
750 do_output(opRoundFP->_result);
752 break;
753 }
756 // LIR_Op2
757 #ifdef MIPS
758 case lir_null_check_for_branch:
759 #else
760 case lir_cmp:
761 #endif
762 case lir_cmp_l2i:
763 case lir_ucmp_fd2i:
764 case lir_cmp_fd2i:
765 case lir_add:
766 case lir_sub:
767 case lir_mul:
768 case lir_div:
769 case lir_rem:
770 case lir_sqrt:
771 case lir_abs:
772 case lir_logic_and:
773 case lir_logic_or:
774 case lir_logic_xor:
775 case lir_shl:
776 case lir_shr:
777 case lir_ushr:
778 case lir_xadd:
779 case lir_xchg:
780 case lir_assert:
781 {
782 assert(op->as_Op2() != NULL, "must be");
783 LIR_Op2* op2 = (LIR_Op2*)op;
784 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
785 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
787 if (op2->_info) do_info(op2->_info);
788 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
789 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
790 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
791 if (op2->_result->is_valid()) do_output(op2->_result);
792 if (op->code() == lir_xchg || op->code() == lir_xadd) {
793 // on ARM and PPC, return value is loaded first so could
794 // destroy inputs. On other platforms that implement those
795 // (x86, sparc), the extra constrainsts are harmless.
796 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
797 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
798 }
800 break;
801 }
803 // special handling for cmove: right input operand must not be equal
804 // to the result operand, otherwise the backend fails
805 case lir_cmove:
806 {
807 assert(op->as_Op2() != NULL, "must be");
808 LIR_Op2* op2 = (LIR_Op2*)op;
810 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
811 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
812 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
814 do_input(op2->_opr1);
815 do_input(op2->_opr2);
816 do_temp(op2->_opr2);
817 do_output(op2->_result);
819 break;
820 }
822 // vspecial handling for strict operations: register input operands
823 // as temp to guarantee that they do not overlap with other
824 // registers
825 case lir_mul_strictfp:
826 case lir_div_strictfp:
827 {
828 assert(op->as_Op2() != NULL, "must be");
829 LIR_Op2* op2 = (LIR_Op2*)op;
831 assert(op2->_info == NULL, "not used");
832 assert(op2->_opr1->is_valid(), "used");
833 assert(op2->_opr2->is_valid(), "used");
834 assert(op2->_result->is_valid(), "used");
835 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
836 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
838 do_input(op2->_opr1); do_temp(op2->_opr1);
839 do_input(op2->_opr2); do_temp(op2->_opr2);
840 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
841 do_output(op2->_result);
843 break;
844 }
846 case lir_throw: {
847 assert(op->as_Op2() != NULL, "must be");
848 LIR_Op2* op2 = (LIR_Op2*)op;
850 if (op2->_info) do_info(op2->_info);
851 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
852 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
853 assert(op2->_result->is_illegal(), "no result");
854 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
855 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
857 break;
858 }
860 case lir_unwind: {
861 assert(op->as_Op1() != NULL, "must be");
862 LIR_Op1* op1 = (LIR_Op1*)op;
864 assert(op1->_info == NULL, "no info");
865 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
866 assert(op1->_result->is_illegal(), "no result");
868 break;
869 }
872 case lir_tan:
873 case lir_sin:
874 case lir_cos:
875 case lir_log:
876 case lir_log10:
877 case lir_exp: {
878 assert(op->as_Op2() != NULL, "must be");
879 LIR_Op2* op2 = (LIR_Op2*)op;
881 // On x86 tan/sin/cos need two temporary fpu stack slots and
882 // log/log10 need one so handle opr2 and tmp as temp inputs.
883 // Register input operand as temp to guarantee that it doesn't
884 // overlap with the input.
885 assert(op2->_info == NULL, "not used");
886 assert(op2->_tmp5->is_illegal(), "not used");
887 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
888 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
889 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
890 assert(op2->_opr1->is_valid(), "used");
891 do_input(op2->_opr1); do_temp(op2->_opr1);
893 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
894 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
895 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
896 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
897 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
898 if (op2->_result->is_valid()) do_output(op2->_result);
900 break;
901 }
903 case lir_pow: {
904 assert(op->as_Op2() != NULL, "must be");
905 LIR_Op2* op2 = (LIR_Op2*)op;
907 // On x86 pow needs two temporary fpu stack slots: tmp1 and
908 // tmp2. Register input operands as temps to guarantee that it
909 // doesn't overlap with the temporary slots.
910 assert(op2->_info == NULL, "not used");
911 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
912 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
913 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
914 assert(op2->_result->is_valid(), "used");
916 do_input(op2->_opr1); do_temp(op2->_opr1);
917 do_input(op2->_opr2); do_temp(op2->_opr2);
918 do_temp(op2->_tmp1);
919 do_temp(op2->_tmp2);
920 do_temp(op2->_tmp3);
921 do_temp(op2->_tmp4);
922 do_temp(op2->_tmp5);
923 do_output(op2->_result);
925 break;
926 }
928 // LIR_Op3
929 #ifdef MIPS
930 case lir_frem:
931 #endif
932 case lir_idiv:
933 case lir_irem: {
934 assert(op->as_Op3() != NULL, "must be");
935 LIR_Op3* op3= (LIR_Op3*)op;
937 if (op3->_info) do_info(op3->_info);
938 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
940 // second operand is input and temp, so ensure that second operand
941 // and third operand get not the same register
942 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
943 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
944 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
946 if (op3->_result->is_valid()) do_output(op3->_result);
948 break;
949 }
952 // LIR_OpJavaCall
953 case lir_static_call:
954 case lir_optvirtual_call:
955 case lir_icvirtual_call:
956 case lir_virtual_call:
957 case lir_dynamic_call: {
958 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
959 assert(opJavaCall != NULL, "must be");
961 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
963 // only visit register parameters
964 int n = opJavaCall->_arguments->length();
965 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
966 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
967 do_input(*opJavaCall->_arguments->adr_at(i));
968 }
969 }
971 if (opJavaCall->_info) do_info(opJavaCall->_info);
972 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
973 opJavaCall->is_method_handle_invoke()) {
974 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
975 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
976 }
977 do_call();
978 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
980 break;
981 }
984 // LIR_OpRTCall
985 case lir_rtcall: {
986 assert(op->as_OpRTCall() != NULL, "must be");
987 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
989 // only visit register parameters
990 int n = opRTCall->_arguments->length();
991 for (int i = 0; i < n; i++) {
992 if (!opRTCall->_arguments->at(i)->is_pointer()) {
993 do_input(*opRTCall->_arguments->adr_at(i));
994 }
995 }
996 if (opRTCall->_info) do_info(opRTCall->_info);
997 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
998 do_call();
999 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
1001 break;
1002 }
1005 // LIR_OpArrayCopy
1006 case lir_arraycopy: {
1007 assert(op->as_OpArrayCopy() != NULL, "must be");
1008 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
1010 assert(opArrayCopy->_result->is_illegal(), "unused");
1011 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
1012 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
1013 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
1014 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
1015 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
1016 #ifndef MIPS
1017 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
1018 #endif
1019 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
1021 // the implementation of arraycopy always has a call into the runtime
1022 do_call();
1024 break;
1025 }
1028 // LIR_OpUpdateCRC32
1029 case lir_updatecrc32: {
1030 assert(op->as_OpUpdateCRC32() != NULL, "must be");
1031 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
1033 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
1034 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
1035 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
1036 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
1038 break;
1039 }
1042 // LIR_OpLock
1043 case lir_lock:
1044 case lir_unlock: {
1045 assert(op->as_OpLock() != NULL, "must be");
1046 LIR_OpLock* opLock = (LIR_OpLock*)op;
1048 if (opLock->_info) do_info(opLock->_info);
1050 // TODO: check if these operands really have to be temp
1051 // (or if input is sufficient). This may have influence on the oop map!
1052 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
1053 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
1054 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
1056 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
1057 assert(opLock->_result->is_illegal(), "unused");
1059 do_stub(opLock->_stub);
1061 break;
1062 }
1065 // LIR_OpDelay
1066 case lir_delay_slot: {
1067 assert(op->as_OpDelay() != NULL, "must be");
1068 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
1070 visit(opDelay->delay_op());
1071 break;
1072 }
1074 // LIR_OpTypeCheck
1075 case lir_instanceof:
1076 case lir_checkcast:
1077 case lir_store_check: {
1078 assert(op->as_OpTypeCheck() != NULL, "must be");
1079 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
1081 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
1082 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
1083 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
1084 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
1085 do_temp(opTypeCheck->_object);
1086 }
1087 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
1088 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
1089 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
1090 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
1091 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
1092 do_stub(opTypeCheck->_stub);
1093 break;
1094 }
1096 // LIR_OpCompareAndSwap
1097 case lir_cas_long:
1098 case lir_cas_obj:
1099 case lir_cas_int: {
1100 assert(op->as_OpCompareAndSwap() != NULL, "must be");
1101 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
1103 assert(opCompareAndSwap->_addr->is_valid(), "used");
1104 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
1105 assert(opCompareAndSwap->_new_value->is_valid(), "used");
1106 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
1107 do_input(opCompareAndSwap->_addr);
1108 do_temp(opCompareAndSwap->_addr);
1109 do_input(opCompareAndSwap->_cmp_value);
1110 do_temp(opCompareAndSwap->_cmp_value);
1111 do_input(opCompareAndSwap->_new_value);
1112 do_temp(opCompareAndSwap->_new_value);
1113 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
1114 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
1115 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
1117 break;
1118 }
1121 // LIR_OpAllocArray;
1122 case lir_alloc_array: {
1123 assert(op->as_OpAllocArray() != NULL, "must be");
1124 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
1126 if (opAllocArray->_info) do_info(opAllocArray->_info);
1127 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
1128 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
1129 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
1130 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
1131 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
1132 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
1133 #ifdef MIPS
1134 if (opAllocArray->_tmp5->is_valid()) do_temp(opAllocArray->_tmp5);
1135 #endif
1136 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
1137 do_stub(opAllocArray->_stub);
1138 break;
1139 }
1141 // LIR_OpProfileCall:
1142 case lir_profile_call: {
1143 assert(op->as_OpProfileCall() != NULL, "must be");
1144 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
1146 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
1147 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
1148 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
1149 break;
1150 }
1152 // LIR_OpProfileType:
1153 case lir_profile_type: {
1154 assert(op->as_OpProfileType() != NULL, "must be");
1155 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1157 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1158 do_input(opProfileType->_obj);
1159 do_temp(opProfileType->_tmp);
1160 break;
1161 }
1162 default:
1163 ShouldNotReachHere();
1164 }
1165 }
1168 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1169 if (stub != NULL) {
1170 stub->visit(this);
1171 }
1172 }
1174 XHandlers* LIR_OpVisitState::all_xhandler() {
1175 XHandlers* result = NULL;
1177 int i;
1178 for (i = 0; i < info_count(); i++) {
1179 if (info_at(i)->exception_handlers() != NULL) {
1180 result = info_at(i)->exception_handlers();
1181 break;
1182 }
1183 }
1185 #ifdef ASSERT
1186 for (i = 0; i < info_count(); i++) {
1187 assert(info_at(i)->exception_handlers() == NULL ||
1188 info_at(i)->exception_handlers() == result,
1189 "only one xhandler list allowed per LIR-operation");
1190 }
1191 #endif
1193 if (result != NULL) {
1194 return result;
1195 } else {
1196 return new XHandlers();
1197 }
1199 return result;
1200 }
1203 #ifdef ASSERT
1204 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1205 visit(op);
1207 return opr_count(inputMode) == 0 &&
1208 opr_count(outputMode) == 0 &&
1209 opr_count(tempMode) == 0 &&
1210 info_count() == 0 &&
1211 !has_call() &&
1212 !has_slow_case();
1213 }
1214 #endif
1216 //---------------------------------------------------
1219 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1220 masm->emit_call(this);
1221 }
1223 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1224 masm->emit_rtcall(this);
1225 }
1227 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1228 masm->emit_opLabel(this);
1229 }
1231 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1232 masm->emit_arraycopy(this);
1233 masm->append_code_stub(stub());
1234 }
1236 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1237 masm->emit_updatecrc32(this);
1238 }
1240 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1241 masm->emit_op0(this);
1242 }
1244 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1245 masm->emit_op1(this);
1246 }
1248 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1249 masm->emit_alloc_obj(this);
1250 masm->append_code_stub(stub());
1251 }
1253 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1254 masm->emit_opBranch(this);
1255 if (stub()) {
1256 masm->append_code_stub(stub());
1257 }
1258 }
1260 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1261 masm->emit_opConvert(this);
1262 if (stub() != NULL) {
1263 masm->append_code_stub(stub());
1264 }
1265 }
1267 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1268 masm->emit_op2(this);
1269 }
1271 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1272 masm->emit_alloc_array(this);
1273 masm->append_code_stub(stub());
1274 }
1276 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1277 masm->emit_opTypeCheck(this);
1278 if (stub()) {
1279 masm->append_code_stub(stub());
1280 }
1281 }
1283 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1284 masm->emit_compare_and_swap(this);
1285 }
1287 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1288 masm->emit_op3(this);
1289 }
1291 #ifdef MIPS
1292 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1293 masm->emit_op4(this);
1294 }
1295 #endif
1297 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1298 masm->emit_lock(this);
1299 if (stub()) {
1300 masm->append_code_stub(stub());
1301 }
1302 }
1304 #ifdef ASSERT
1305 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1306 masm->emit_assert(this);
1307 }
1308 #endif
1310 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1311 masm->emit_delay(this);
1312 }
1314 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1315 masm->emit_profile_call(this);
1316 }
1318 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1319 masm->emit_profile_type(this);
1320 }
1322 // LIR_List
1323 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1324 : _operations(8)
1325 , _compilation(compilation)
1326 #ifndef PRODUCT
1327 , _block(block)
1328 #endif
1329 #ifdef ASSERT
1330 , _file(NULL)
1331 , _line(0)
1332 #endif
1333 { }
1336 #ifdef ASSERT
1337 void LIR_List::set_file_and_line(const char * file, int line) {
1338 const char * f = strrchr(file, '/');
1339 if (f == NULL) f = strrchr(file, '\\');
1340 if (f == NULL) {
1341 f = file;
1342 } else {
1343 f++;
1344 }
1345 _file = f;
1346 _line = line;
1347 }
1348 #endif
1351 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1352 assert(this == buffer->lir_list(), "wrong lir list");
1353 const int n = _operations.length();
1355 if (buffer->number_of_ops() > 0) {
1356 // increase size of instructions list
1357 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1358 // insert ops from buffer into instructions list
1359 int op_index = buffer->number_of_ops() - 1;
1360 int ip_index = buffer->number_of_insertion_points() - 1;
1361 int from_index = n - 1;
1362 int to_index = _operations.length() - 1;
1363 for (; ip_index >= 0; ip_index --) {
1364 int index = buffer->index_at(ip_index);
1365 // make room after insertion point
1366 while (index < from_index) {
1367 _operations.at_put(to_index --, _operations.at(from_index --));
1368 }
1369 // insert ops from buffer
1370 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1371 _operations.at_put(to_index --, buffer->op_at(op_index --));
1372 }
1373 }
1374 }
1376 buffer->finish();
1377 }
1380 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1381 assert(reg->type() == T_OBJECT, "bad reg");
1382 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1383 }
1385 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1386 assert(reg->type() == T_METADATA, "bad reg");
1387 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1388 }
1390 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1391 append(new LIR_Op1(
1392 lir_move,
1393 LIR_OprFact::address(addr),
1394 src,
1395 addr->type(),
1396 patch_code,
1397 info));
1398 }
1401 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1402 append(new LIR_Op1(
1403 lir_move,
1404 LIR_OprFact::address(address),
1405 dst,
1406 address->type(),
1407 patch_code,
1408 info, lir_move_volatile));
1409 }
1411 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1412 #ifdef MIPS
1413 add(base, offset, base);
1414 offset = 0;
1415 #endif
1416 append(new LIR_Op1(
1417 lir_move,
1418 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1419 dst,
1420 type,
1421 patch_code,
1422 info, lir_move_volatile));
1423 }
1426 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1427 append(new LIR_Op1(
1428 is_store ? lir_prefetchw : lir_prefetchr,
1429 LIR_OprFact::address(addr)));
1430 }
1433 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1434 append(new LIR_Op1(
1435 lir_move,
1436 LIR_OprFact::intConst(v),
1437 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1438 type,
1439 patch_code,
1440 info));
1441 }
1444 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1445 append(new LIR_Op1(
1446 lir_move,
1447 LIR_OprFact::oopConst(o),
1448 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1449 type,
1450 patch_code,
1451 info));
1452 }
1455 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1456 append(new LIR_Op1(
1457 lir_move,
1458 src,
1459 LIR_OprFact::address(addr),
1460 addr->type(),
1461 patch_code,
1462 info));
1463 }
1466 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1467 append(new LIR_Op1(
1468 lir_move,
1469 src,
1470 LIR_OprFact::address(addr),
1471 addr->type(),
1472 patch_code,
1473 info,
1474 lir_move_volatile));
1475 }
1477 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1478 #ifdef MIPS
1479 add(base, offset, base);
1480 offset = 0;
1481 #endif
1482 append(new LIR_Op1(
1483 lir_move,
1484 src,
1485 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1486 type,
1487 patch_code,
1488 info, lir_move_volatile));
1489 }
1491 #ifdef MIPS
1492 void LIR_List::frem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1493 append(new LIR_Op3(
1494 lir_frem,
1495 left,
1496 right,
1497 tmp,
1498 res,
1499 info));
1500 }
1501 #endif
1503 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1504 append(new LIR_Op3(
1505 lir_idiv,
1506 left,
1507 right,
1508 tmp,
1509 res,
1510 info));
1511 }
1514 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1515 append(new LIR_Op3(
1516 lir_idiv,
1517 left,
1518 LIR_OprFact::intConst(right),
1519 tmp,
1520 res,
1521 info));
1522 }
1525 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1526 append(new LIR_Op3(
1527 lir_irem,
1528 left,
1529 right,
1530 tmp,
1531 res,
1532 info));
1533 }
1536 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1537 append(new LIR_Op3(
1538 lir_irem,
1539 left,
1540 LIR_OprFact::intConst(right),
1541 tmp,
1542 res,
1543 info));
1544 }
1547 #ifndef MIPS
1548 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1549 append(new LIR_Op2(
1550 lir_cmp,
1551 condition,
1552 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1553 LIR_OprFact::intConst(c),
1554 info));
1555 }
1557 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1558 append(new LIR_Op2(
1559 lir_cmp,
1560 condition,
1561 reg,
1562 LIR_OprFact::address(addr),
1563 info));
1564 }
1565 #endif
1567 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1568 if (deoptimize_on_null) {
1569 // Emit an explicit null check and deoptimize if opr is null
1570 CodeStub* deopt = new DeoptimizeStub(info);
1571 #ifndef MIPS
1572 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1573 branch(lir_cond_equal, T_OBJECT, deopt);
1574 #else
1575 null_check_for_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1576 branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), T_OBJECT, deopt);
1577 #endif
1578 } else {
1579 // Emit an implicit null check
1580 append(new LIR_Op1(lir_null_check, opr, info));
1581 }
1582 }
1584 #ifndef MIPS
1585 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1586 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1587 append(new LIR_OpAllocObj(
1588 klass,
1589 dst,
1590 t1,
1591 t2,
1592 t3,
1593 t4,
1594 header_size,
1595 object_size,
1596 init_check,
1597 stub));
1598 }
1600 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1601 append(new LIR_OpAllocArray(
1602 klass,
1603 len,
1604 dst,
1605 t1,
1606 t2,
1607 t3,
1608 t4,
1609 type,
1610 stub));
1611 }
1612 #else
1613 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, LIR_Opr t5, LIR_Opr t6,
1614 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1615 append(new LIR_OpAllocObj(
1616 klass,
1617 dst,
1618 t1,
1619 t2,
1620 t3,
1621 t4,
1622 t5,
1623 t6,
1624 header_size,
1625 object_size,
1626 init_check,
1627 stub));
1628 }
1629 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, LIR_Opr t5,
1630 BasicType type, LIR_Opr klass, CodeStub* stub) {
1631 append(new LIR_OpAllocArray(
1632 klass,
1633 len,
1634 dst,
1635 t1,
1636 t2,
1637 t3,
1638 t4,
1639 t5,
1640 type,
1641 stub));
1642 }
1644 #endif
1646 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1647 append(new LIR_Op2(
1648 lir_shl,
1649 value,
1650 count,
1651 dst,
1652 tmp));
1653 }
1655 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1656 append(new LIR_Op2(
1657 lir_shr,
1658 value,
1659 count,
1660 dst,
1661 tmp));
1662 }
1665 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1666 append(new LIR_Op2(
1667 lir_ushr,
1668 value,
1669 count,
1670 dst,
1671 tmp));
1672 }
1674 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1675 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1676 left,
1677 right,
1678 dst));
1679 }
1681 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1682 append(new LIR_OpLock(
1683 lir_lock,
1684 hdr,
1685 obj,
1686 lock,
1687 scratch,
1688 stub,
1689 info));
1690 }
1692 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1693 append(new LIR_OpLock(
1694 lir_unlock,
1695 hdr,
1696 obj,
1697 lock,
1698 scratch,
1699 stub,
1700 NULL));
1701 }
1704 void check_LIR() {
1705 // cannot do the proper checking as PRODUCT and other modes return different results
1706 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1707 }
1711 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1712 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1713 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1714 ciMethod* profiled_method, int profiled_bci) {
1715 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1716 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1717 if (profiled_method != NULL) {
1718 c->set_profiled_method(profiled_method);
1719 c->set_profiled_bci(profiled_bci);
1720 c->set_should_profile(true);
1721 }
1722 append(c);
1723 }
1725 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1726 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1727 if (profiled_method != NULL) {
1728 c->set_profiled_method(profiled_method);
1729 c->set_profiled_bci(profiled_bci);
1730 c->set_should_profile(true);
1731 }
1732 append(c);
1733 }
1736 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1737 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1738 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1739 if (profiled_method != NULL) {
1740 c->set_profiled_method(profiled_method);
1741 c->set_profiled_bci(profiled_bci);
1742 c->set_should_profile(true);
1743 }
1744 append(c);
1745 }
1747 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1748 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1749 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1750 }
1752 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1753 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1754 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1755 }
1757 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1758 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1759 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1760 }
1763 #ifdef PRODUCT
1765 void print_LIR(BlockList* blocks) {
1766 }
1768 #else
1769 // LIR_OprDesc
1770 void LIR_OprDesc::print() const {
1771 print(tty);
1772 }
1774 void LIR_OprDesc::print(outputStream* out) const {
1775 if (is_illegal()) {
1776 return;
1777 }
1779 out->print("[");
1780 if (is_pointer()) {
1781 pointer()->print_value_on(out);
1782 } else if (is_single_stack()) {
1783 out->print("stack:%d", single_stack_ix());
1784 } else if (is_double_stack()) {
1785 out->print("dbl_stack:%d",double_stack_ix());
1786 } else if (is_virtual()) {
1787 out->print("R%d", vreg_number());
1788 } else if (is_single_cpu()) {
1789 out->print("%s", as_register()->name());
1790 } else if (is_double_cpu()) {
1791 out->print("%s", as_register_hi()->name());
1792 out->print("%s", as_register_lo()->name());
1793 #if defined(X86)
1794 } else if (is_single_xmm()) {
1795 out->print("%s", as_xmm_float_reg()->name());
1796 } else if (is_double_xmm()) {
1797 out->print("%s", as_xmm_double_reg()->name());
1798 } else if (is_single_fpu()) {
1799 out->print("fpu%d", fpu_regnr());
1800 } else if (is_double_fpu()) {
1801 out->print("fpu%d", fpu_regnrLo());
1802 #elif defined(ARM)
1803 } else if (is_single_fpu()) {
1804 out->print("s%d", fpu_regnr());
1805 } else if (is_double_fpu()) {
1806 out->print("d%d", fpu_regnrLo() >> 1);
1807 #else
1808 } else if (is_single_fpu()) {
1809 out->print("%s", as_float_reg()->name());
1810 } else if (is_double_fpu()) {
1811 out->print("%s", as_double_reg()->name());
1812 #endif
1814 } else if (is_illegal()) {
1815 out->print("-");
1816 } else {
1817 out->print("Unknown Operand");
1818 }
1819 if (!is_illegal()) {
1820 out->print("|%c", type_char());
1821 }
1822 if (is_register() && is_last_use()) {
1823 out->print("(last_use)");
1824 }
1825 out->print("]");
1826 }
1829 // LIR_Address
1830 void LIR_Const::print_value_on(outputStream* out) const {
1831 switch (type()) {
1832 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1833 case T_INT: out->print("int:%d", as_jint()); break;
1834 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1835 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1836 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1837 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1838 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1839 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1840 }
1841 }
1843 // LIR_Address
1844 void LIR_Address::print_value_on(outputStream* out) const {
1845 out->print("Base:"); _base->print(out);
1846 #ifndef MIPS
1847 if (!_index->is_illegal()) {
1848 out->print(" Index:"); _index->print(out);
1849 switch (scale()) {
1850 case times_1: break;
1851 case times_2: out->print(" * 2"); break;
1852 case times_4: out->print(" * 4"); break;
1853 case times_8: out->print(" * 8"); break;
1854 }
1855 }
1856 #endif
1857 out->print(" Disp: " INTX_FORMAT, _disp);
1858 }
1860 // debug output of block header without InstructionPrinter
1861 // (because phi functions are not necessary for LIR)
1862 static void print_block(BlockBegin* x) {
1863 // print block id
1864 BlockEnd* end = x->end();
1865 tty->print("B%d ", x->block_id());
1867 // print flags
1868 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1869 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1870 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1871 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1872 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1873 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1874 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1876 // print block bci range
1877 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1879 // print predecessors and successors
1880 if (x->number_of_preds() > 0) {
1881 tty->print("preds: ");
1882 for (int i = 0; i < x->number_of_preds(); i ++) {
1883 tty->print("B%d ", x->pred_at(i)->block_id());
1884 }
1885 }
1887 if (x->number_of_sux() > 0) {
1888 tty->print("sux: ");
1889 for (int i = 0; i < x->number_of_sux(); i ++) {
1890 tty->print("B%d ", x->sux_at(i)->block_id());
1891 }
1892 }
1894 // print exception handlers
1895 if (x->number_of_exception_handlers() > 0) {
1896 tty->print("xhandler: ");
1897 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1898 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1899 }
1900 }
1902 tty->cr();
1903 }
1905 void print_LIR(BlockList* blocks) {
1906 tty->print_cr("LIR:");
1907 int i;
1908 for (i = 0; i < blocks->length(); i++) {
1909 BlockBegin* bb = blocks->at(i);
1910 print_block(bb);
1911 tty->print("__id_Instruction___________________________________________"); tty->cr();
1912 bb->lir()->print_instructions();
1913 }
1914 }
1916 void LIR_List::print_instructions() {
1917 for (int i = 0; i < _operations.length(); i++) {
1918 _operations.at(i)->print(); tty->cr();
1919 }
1920 tty->cr();
1921 }
1923 // LIR_Ops printing routines
1924 // LIR_Op
1925 void LIR_Op::print_on(outputStream* out) const {
1926 if (id() != -1 || PrintCFGToFile) {
1927 out->print("%4d ", id());
1928 } else {
1929 out->print(" ");
1930 }
1931 out->print("%s ", name());
1932 print_instr(out);
1933 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1934 #ifdef ASSERT
1935 if (Verbose && _file != NULL) {
1936 out->print(" (%s:%d)", _file, _line);
1937 }
1938 #endif
1939 }
1941 const char * LIR_Op::name() const {
1942 const char* s = NULL;
1943 switch(code()) {
1944 // LIR_Op0
1945 case lir_membar: s = "membar"; break;
1946 case lir_membar_acquire: s = "membar_acquire"; break;
1947 case lir_membar_release: s = "membar_release"; break;
1948 case lir_membar_loadload: s = "membar_loadload"; break;
1949 case lir_membar_storestore: s = "membar_storestore"; break;
1950 case lir_membar_loadstore: s = "membar_loadstore"; break;
1951 case lir_membar_storeload: s = "membar_storeload"; break;
1952 case lir_word_align: s = "word_align"; break;
1953 case lir_label: s = "label"; break;
1954 case lir_nop: s = "nop"; break;
1955 case lir_backwardbranch_target: s = "backbranch"; break;
1956 case lir_std_entry: s = "std_entry"; break;
1957 case lir_osr_entry: s = "osr_entry"; break;
1958 case lir_build_frame: s = "build_frm"; break;
1959 case lir_fpop_raw: s = "fpop_raw"; break;
1960 case lir_24bit_FPU: s = "24bit_FPU"; break;
1961 case lir_reset_FPU: s = "reset_FPU"; break;
1962 case lir_breakpoint: s = "breakpoint"; break;
1963 case lir_get_thread: s = "get_thread"; break;
1964 // LIR_Op1
1965 case lir_fxch: s = "fxch"; break;
1966 case lir_fld: s = "fld"; break;
1967 case lir_ffree: s = "ffree"; break;
1968 case lir_push: s = "push"; break;
1969 case lir_pop: s = "pop"; break;
1970 case lir_null_check: s = "null_check"; break;
1971 case lir_return: s = "return"; break;
1972 case lir_safepoint: s = "safepoint"; break;
1973 case lir_neg: s = "neg"; break;
1974 case lir_leal: s = "leal"; break;
1975 case lir_branch: s = "branch"; break;
1976 case lir_cond_float_branch: s = "flt_cond_br"; break;
1977 case lir_move: s = "move"; break;
1978 case lir_roundfp: s = "roundfp"; break;
1979 case lir_rtcall: s = "rtcall"; break;
1980 case lir_throw: s = "throw"; break;
1981 case lir_unwind: s = "unwind"; break;
1982 case lir_convert: s = "convert"; break;
1983 case lir_alloc_object: s = "alloc_obj"; break;
1984 case lir_monaddr: s = "mon_addr"; break;
1985 case lir_pack64: s = "pack64"; break;
1986 case lir_unpack64: s = "unpack64"; break;
1987 // LIR_Op2
1988 #ifdef MIPS
1989 case lir_null_check_for_branch: s = "null_check_for_branch"; break;
1990 #else
1991 case lir_cmp: s = "cmp"; break;
1992 #endif
1993 case lir_cmp_l2i: s = "cmp_l2i"; break;
1994 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1995 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1996 case lir_cmove: s = "cmove"; break;
1997 case lir_add: s = "add"; break;
1998 case lir_sub: s = "sub"; break;
1999 case lir_mul: s = "mul"; break;
2000 case lir_mul_strictfp: s = "mul_strictfp"; break;
2001 case lir_div: s = "div"; break;
2002 case lir_div_strictfp: s = "div_strictfp"; break;
2003 case lir_rem: s = "rem"; break;
2004 case lir_abs: s = "abs"; break;
2005 case lir_sqrt: s = "sqrt"; break;
2006 case lir_sin: s = "sin"; break;
2007 case lir_cos: s = "cos"; break;
2008 case lir_tan: s = "tan"; break;
2009 case lir_log: s = "log"; break;
2010 case lir_log10: s = "log10"; break;
2011 case lir_exp: s = "exp"; break;
2012 case lir_pow: s = "pow"; break;
2013 case lir_logic_and: s = "logic_and"; break;
2014 case lir_logic_or: s = "logic_or"; break;
2015 case lir_logic_xor: s = "logic_xor"; break;
2016 case lir_shl: s = "shift_left"; break;
2017 case lir_shr: s = "shift_right"; break;
2018 case lir_ushr: s = "ushift_right"; break;
2019 case lir_alloc_array: s = "alloc_array"; break;
2020 case lir_xadd: s = "xadd"; break;
2021 case lir_xchg: s = "xchg"; break;
2022 // LIR_Op3
2023 #ifdef MIPS
2024 case lir_frem: s = "frem"; break;
2025 #endif
2026 case lir_idiv: s = "idiv"; break;
2027 case lir_irem: s = "irem"; break;
2028 #ifdef MIPS
2029 // LIR_Op4
2030 case lir_cmove_mips: s = "cmove_mips"; break;
2031 #endif
2032 // LIR_OpJavaCall
2033 case lir_static_call: s = "static"; break;
2034 case lir_optvirtual_call: s = "optvirtual"; break;
2035 case lir_icvirtual_call: s = "icvirtual"; break;
2036 case lir_virtual_call: s = "virtual"; break;
2037 case lir_dynamic_call: s = "dynamic"; break;
2038 // LIR_OpArrayCopy
2039 case lir_arraycopy: s = "arraycopy"; break;
2040 // LIR_OpUpdateCRC32
2041 case lir_updatecrc32: s = "updatecrc32"; break;
2042 // LIR_OpLock
2043 case lir_lock: s = "lock"; break;
2044 case lir_unlock: s = "unlock"; break;
2045 // LIR_OpDelay
2046 case lir_delay_slot: s = "delay"; break;
2047 // LIR_OpTypeCheck
2048 case lir_instanceof: s = "instanceof"; break;
2049 case lir_checkcast: s = "checkcast"; break;
2050 case lir_store_check: s = "store_check"; break;
2051 // LIR_OpCompareAndSwap
2052 case lir_cas_long: s = "cas_long"; break;
2053 case lir_cas_obj: s = "cas_obj"; break;
2054 case lir_cas_int: s = "cas_int"; break;
2055 // LIR_OpProfileCall
2056 case lir_profile_call: s = "profile_call"; break;
2057 // LIR_OpProfileType
2058 case lir_profile_type: s = "profile_type"; break;
2059 // LIR_OpAssert
2060 #ifdef ASSERT
2061 case lir_assert: s = "assert"; break;
2062 #endif
2063 case lir_none: ShouldNotReachHere();break;
2064 default: s = "illegal_op"; break;
2065 }
2066 return s;
2067 }
2069 // LIR_OpJavaCall
2070 void LIR_OpJavaCall::print_instr(outputStream* out) const {
2071 out->print("call: ");
2072 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
2073 if (receiver()->is_valid()) {
2074 out->print(" [recv: "); receiver()->print(out); out->print("]");
2075 }
2076 if (result_opr()->is_valid()) {
2077 out->print(" [result: "); result_opr()->print(out); out->print("]");
2078 }
2079 }
2081 // LIR_OpLabel
2082 void LIR_OpLabel::print_instr(outputStream* out) const {
2083 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
2084 }
2086 // LIR_OpArrayCopy
2087 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
2088 src()->print(out); out->print(" ");
2089 src_pos()->print(out); out->print(" ");
2090 dst()->print(out); out->print(" ");
2091 dst_pos()->print(out); out->print(" ");
2092 length()->print(out); out->print(" ");
2093 tmp()->print(out); out->print(" ");
2094 }
2096 // LIR_OpUpdateCRC32
2097 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
2098 crc()->print(out); out->print(" ");
2099 val()->print(out); out->print(" ");
2100 result_opr()->print(out); out->print(" ");
2101 }
2103 // LIR_OpCompareAndSwap
2104 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
2105 addr()->print(out); out->print(" ");
2106 cmp_value()->print(out); out->print(" ");
2107 new_value()->print(out); out->print(" ");
2108 tmp1()->print(out); out->print(" ");
2109 tmp2()->print(out); out->print(" ");
2111 }
2113 // LIR_Op0
2114 void LIR_Op0::print_instr(outputStream* out) const {
2115 result_opr()->print(out);
2116 }
2118 // LIR_Op1
2119 const char * LIR_Op1::name() const {
2120 if (code() == lir_move) {
2121 switch (move_kind()) {
2122 case lir_move_normal:
2123 return "move";
2124 case lir_move_unaligned:
2125 return "unaligned move";
2126 case lir_move_volatile:
2127 return "volatile_move";
2128 case lir_move_wide:
2129 return "wide_move";
2130 default:
2131 ShouldNotReachHere();
2132 return "illegal_op";
2133 }
2134 } else {
2135 return LIR_Op::name();
2136 }
2137 }
2140 void LIR_Op1::print_instr(outputStream* out) const {
2141 _opr->print(out); out->print(" ");
2142 result_opr()->print(out); out->print(" ");
2143 print_patch_code(out, patch_code());
2144 }
2147 // LIR_Op1
2148 void LIR_OpRTCall::print_instr(outputStream* out) const {
2149 intx a = (intx)addr();
2150 out->print("%s", Runtime1::name_for_address(addr()));
2151 out->print(" ");
2152 tmp()->print(out);
2153 }
2155 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
2156 switch(code) {
2157 case lir_patch_none: break;
2158 case lir_patch_low: out->print("[patch_low]"); break;
2159 case lir_patch_high: out->print("[patch_high]"); break;
2160 case lir_patch_normal: out->print("[patch_normal]"); break;
2161 default: ShouldNotReachHere();
2162 }
2163 }
2165 // LIR_OpBranch
2166 void LIR_OpBranch::print_instr(outputStream* out) const {
2167 print_condition(out, cond()); out->print(" ");
2168 #ifdef MIPS
2169 in_opr1()->print(out); out->print(" ");
2170 in_opr2()->print(out); out->print(" ");
2171 #endif
2172 if (block() != NULL) {
2173 out->print("[B%d] ", block()->block_id());
2174 } else if (stub() != NULL) {
2175 out->print("[");
2176 stub()->print_name(out);
2177 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
2178 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
2179 } else {
2180 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
2181 }
2182 if (ublock() != NULL) {
2183 out->print("unordered: [B%d] ", ublock()->block_id());
2184 }
2185 }
2187 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
2188 switch(cond) {
2189 case lir_cond_equal: out->print("[EQ]"); break;
2190 case lir_cond_notEqual: out->print("[NE]"); break;
2191 case lir_cond_less: out->print("[LT]"); break;
2192 case lir_cond_lessEqual: out->print("[LE]"); break;
2193 case lir_cond_greaterEqual: out->print("[GE]"); break;
2194 case lir_cond_greater: out->print("[GT]"); break;
2195 case lir_cond_belowEqual: out->print("[BE]"); break;
2196 case lir_cond_aboveEqual: out->print("[AE]"); break;
2197 case lir_cond_always: out->print("[AL]"); break;
2198 default: out->print("[%d]",cond); break;
2199 }
2200 }
2202 // LIR_OpConvert
2203 void LIR_OpConvert::print_instr(outputStream* out) const {
2204 print_bytecode(out, bytecode());
2205 in_opr()->print(out); out->print(" ");
2206 result_opr()->print(out); out->print(" ");
2207 #ifdef PPC
2208 if(tmp1()->is_valid()) {
2209 tmp1()->print(out); out->print(" ");
2210 tmp2()->print(out); out->print(" ");
2211 }
2212 #endif
2213 }
2215 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
2216 switch(code) {
2217 case Bytecodes::_d2f: out->print("[d2f] "); break;
2218 case Bytecodes::_d2i: out->print("[d2i] "); break;
2219 case Bytecodes::_d2l: out->print("[d2l] "); break;
2220 case Bytecodes::_f2d: out->print("[f2d] "); break;
2221 case Bytecodes::_f2i: out->print("[f2i] "); break;
2222 case Bytecodes::_f2l: out->print("[f2l] "); break;
2223 case Bytecodes::_i2b: out->print("[i2b] "); break;
2224 case Bytecodes::_i2c: out->print("[i2c] "); break;
2225 case Bytecodes::_i2d: out->print("[i2d] "); break;
2226 case Bytecodes::_i2f: out->print("[i2f] "); break;
2227 case Bytecodes::_i2l: out->print("[i2l] "); break;
2228 case Bytecodes::_i2s: out->print("[i2s] "); break;
2229 case Bytecodes::_l2i: out->print("[l2i] "); break;
2230 case Bytecodes::_l2f: out->print("[l2f] "); break;
2231 case Bytecodes::_l2d: out->print("[l2d] "); break;
2232 default:
2233 out->print("[?%d]",code);
2234 break;
2235 }
2236 }
2238 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2239 klass()->print(out); out->print(" ");
2240 obj()->print(out); out->print(" ");
2241 tmp1()->print(out); out->print(" ");
2242 tmp2()->print(out); out->print(" ");
2243 tmp3()->print(out); out->print(" ");
2244 tmp4()->print(out); out->print(" ");
2245 #ifdef MIPS
2246 tmp5()->print(out); out->print(" ");
2247 tmp6()->print(out); out->print(" ");
2248 #endif
2249 out->print("[hdr:%d]", header_size()); out->print(" ");
2250 out->print("[obj:%d]", object_size()); out->print(" ");
2251 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2252 }
2254 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2255 _opr->print(out); out->print(" ");
2256 tmp()->print(out); out->print(" ");
2257 result_opr()->print(out); out->print(" ");
2258 }
2260 // LIR_Op2
2261 void LIR_Op2::print_instr(outputStream* out) const {
2262 #ifndef MIPS
2263 if (code() == lir_cmove) {
2264 print_condition(out, condition()); out->print(" ");
2265 }
2266 #endif
2267 in_opr1()->print(out); out->print(" ");
2268 in_opr2()->print(out); out->print(" ");
2269 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2270 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2271 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2272 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2273 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2274 result_opr()->print(out);
2275 }
2277 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2278 klass()->print(out); out->print(" ");
2279 len()->print(out); out->print(" ");
2280 obj()->print(out); out->print(" ");
2281 tmp1()->print(out); out->print(" ");
2282 tmp2()->print(out); out->print(" ");
2283 tmp3()->print(out); out->print(" ");
2284 tmp4()->print(out); out->print(" ");
2285 #ifdef MIPS
2286 tmp5()->print(out); out->print(" ");
2287 #endif
2288 out->print("[type:0x%x]", type()); out->print(" ");
2289 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2290 }
2293 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2294 object()->print(out); out->print(" ");
2295 if (code() == lir_store_check) {
2296 array()->print(out); out->print(" ");
2297 }
2298 if (code() != lir_store_check) {
2299 klass()->print_name_on(out); out->print(" ");
2300 if (fast_check()) out->print("fast_check ");
2301 }
2302 tmp1()->print(out); out->print(" ");
2303 tmp2()->print(out); out->print(" ");
2304 tmp3()->print(out); out->print(" ");
2305 result_opr()->print(out); out->print(" ");
2306 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2307 }
2310 // LIR_Op3
2311 void LIR_Op3::print_instr(outputStream* out) const {
2312 in_opr1()->print(out); out->print(" ");
2313 in_opr2()->print(out); out->print(" ");
2314 in_opr3()->print(out); out->print(" ");
2315 result_opr()->print(out);
2316 }
2318 #ifdef MIPS
2319 // LIR_Op4
2320 void LIR_Op4::print_instr(outputStream* out) const {
2321 print_condition(out, cond()); out->print(" ");
2322 in_opr1()->print(out); out->print(" ");
2323 in_opr2()->print(out); out->print(" ");
2324 in_opr3()->print(out); out->print(" ");
2325 in_opr4()->print(out); out->print(" ");
2326 result_opr()->print(out);
2327 }
2328 #endif
2330 void LIR_OpLock::print_instr(outputStream* out) const {
2331 hdr_opr()->print(out); out->print(" ");
2332 obj_opr()->print(out); out->print(" ");
2333 lock_opr()->print(out); out->print(" ");
2334 if (_scratch->is_valid()) {
2335 _scratch->print(out); out->print(" ");
2336 }
2337 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2338 }
2340 #ifdef ASSERT
2341 void LIR_OpAssert::print_instr(outputStream* out) const {
2342 tty->print_cr("function LIR_OpAssert::print_instr unimplemented yet! ");
2343 Unimplemented();
2344 /*
2345 print_condition(out, condition()); out->print(" ");
2346 in_opr1()->print(out); out->print(" ");
2347 in_opr2()->print(out); out->print(", \"");
2348 out->print("%s", msg()); out->print("\"");
2349 */
2350 }
2351 #endif
2354 void LIR_OpDelay::print_instr(outputStream* out) const {
2355 _op->print_on(out);
2356 }
2359 // LIR_OpProfileCall
2360 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2361 profiled_method()->name()->print_symbol_on(out);
2362 out->print(".");
2363 profiled_method()->holder()->name()->print_symbol_on(out);
2364 out->print(" @ %d ", profiled_bci());
2365 mdo()->print(out); out->print(" ");
2366 recv()->print(out); out->print(" ");
2367 tmp1()->print(out); out->print(" ");
2368 }
2370 // LIR_OpProfileType
2371 void LIR_OpProfileType::print_instr(outputStream* out) const {
2372 out->print("exact = ");
2373 if (exact_klass() == NULL) {
2374 out->print("unknown");
2375 } else {
2376 exact_klass()->print_name_on(out);
2377 }
2378 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2379 out->print(" ");
2380 mdp()->print(out); out->print(" ");
2381 obj()->print(out); out->print(" ");
2382 tmp()->print(out); out->print(" ");
2383 }
2385 #endif // PRODUCT
2387 // Implementation of LIR_InsertionBuffer
2389 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2390 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2392 int i = number_of_insertion_points() - 1;
2393 if (i < 0 || index_at(i) < index) {
2394 append_new(index, 1);
2395 } else {
2396 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2397 assert(count_at(i) > 0, "check");
2398 set_count_at(i, count_at(i) + 1);
2399 }
2400 _ops.push(op);
2402 DEBUG_ONLY(verify());
2403 }
2405 #ifdef ASSERT
2406 void LIR_InsertionBuffer::verify() {
2407 int sum = 0;
2408 int prev_idx = -1;
2410 for (int i = 0; i < number_of_insertion_points(); i++) {
2411 assert(prev_idx < index_at(i), "index must be ordered ascending");
2412 sum += count_at(i);
2413 }
2414 assert(sum == number_of_ops(), "wrong total sum");
2415 }
2416 #endif
