Wed, 03 Jul 2019 20:42:37 +0800
Merge
1 /*
2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 /*
26 * This file has been modified by Loongson Technology in 2015. These
27 * modifications are Copyright (c) 2015 Loongson Technology, and are made
28 * available on the same license terms set forth above.
29 */
31 #ifndef SHARE_VM_C1_C1_DEFS_HPP
32 #define SHARE_VM_C1_C1_DEFS_HPP
34 #include "utilities/globalDefinitions.hpp"
35 #ifdef TARGET_ARCH_x86
36 # include "register_x86.hpp"
37 #endif
38 #ifdef TARGET_ARCH_mips
39 # include "register_mips.hpp"
40 #endif
41 #ifdef TARGET_ARCH_sparc
42 # include "register_sparc.hpp"
43 #endif
44 #ifdef TARGET_ARCH_zero
45 # include "register_zero.hpp"
46 #endif
47 #ifdef TARGET_ARCH_arm
48 # include "register_arm.hpp"
49 #endif
50 #ifdef TARGET_ARCH_ppc
51 # include "register_ppc.hpp"
52 #endif
54 // set frame size and return address offset to these values in blobs
55 // (if the compiled frame uses ebp as link pointer on IA; otherwise,
56 // the frame size must be fixed)
57 enum {
58 no_frame_size = -1
59 };
62 #ifdef TARGET_ARCH_x86
63 # include "c1_Defs_x86.hpp"
64 #endif
65 #ifdef TARGET_ARCH_mips
66 # include "c1_Defs_mips.hpp"
67 #endif
68 #ifdef TARGET_ARCH_sparc
69 # include "c1_Defs_sparc.hpp"
70 #endif
71 #ifdef TARGET_ARCH_arm
72 # include "c1_Defs_arm.hpp"
73 #endif
74 #ifdef TARGET_ARCH_ppc
75 # include "c1_Defs_ppc.hpp"
76 #endif
79 // native word offsets from memory address
80 enum {
81 lo_word_offset_in_bytes = pd_lo_word_offset_in_bytes,
82 hi_word_offset_in_bytes = pd_hi_word_offset_in_bytes
83 };
86 // the processor may require explicit rounding operations to implement the strictFP mode
87 enum {
88 strict_fp_requires_explicit_rounding = pd_strict_fp_requires_explicit_rounding
89 };
92 // for debug info: a float value in a register may be saved in double precision by runtime stubs
93 enum {
94 float_saved_as_double = pd_float_saved_as_double
95 };
97 #endif // SHARE_VM_C1_C1_DEFS_HPP