Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/mips/vm/globals_mips.hpp@e67dc9f1ba90
src/cpu/mips/vm/globals_mips.hpp
Fri, 25 Nov 2016 12:50:45 +0800
- author
- aoqi
- date
- Fri, 25 Nov 2016 12:50:45 +0800
- changeset 179
- e67dc9f1ba90
- parent 10
- 0b0d61d41da1
- child 180
- 5616e477f016
- permissions
- -rw-r--r--
Added flag SetFSFOFN to set FS/FO/FN in FCSR
The default value of SetFSFOFN is 999, which means FS/FO/FN will not be changed, rather than set to 000.
Usage example #1 (FS:0, FO:0, FN:0):
java -XX:SetFSFOFN=000
Usage example #2 (FS:1, FO:0, FN:1):
java -XX:SetFSFOFN=101
ps, when FO is set, sunflow would fail.
This patch includes some [Code Reorganization].
1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_MIPS_VM_GLOBALS_MIPS_HPP
27 #define CPU_MIPS_VM_GLOBALS_MIPS_HPP
29 #include "utilities/globalDefinitions.hpp"
30 #include "utilities/macros.hpp"
32 //
33 // Sets the default values for platform dependent flags used by the runtime system.
34 // (see globals.hpp)
35 //
36 #ifdef CORE
37 define_pd_global(bool, UseSSE, 0);
38 #endif /* CORE */
39 define_pd_global(bool, ConvertSleepToYield, true);
40 define_pd_global(bool, ShareVtableStubs, true);
41 define_pd_global(bool, CountInterpCalls, true);
43 define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
44 define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86.
45 define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast
46 define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this
48 // See 4827828 for this change. There is no globals_core_i486.hpp. I can't
49 // assign a different value for C2 without touching a number of files. Use
50 // #ifdef to minimize the change as it's late in Mantis. -- FIXME.
51 // c1 doesn't have this problem because the fix to 4858033 assures us
52 // the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
53 // the uep and the vep doesn't get real alignment but just slops on by
54 // only assured that the entry instruction meets the 5 byte size requirement.
55 define_pd_global(intx, CodeEntryAlignment, 32);
56 define_pd_global(intx, OptoLoopAlignment, 16);
57 define_pd_global(intx, InlineFrequencyCount, 100);
58 define_pd_global(intx, InlineSmallCode, 4000); // 2016/5/11 Jin: MIPS generates 3x instructions than X86
60 define_pd_global(uintx, TLABSize, 0);
61 define_pd_global(uintx, NewSize, 1024 * K);
62 define_pd_global(intx, PreInflateSpin, 10);
64 define_pd_global(intx, PrefetchCopyIntervalInBytes, -1);
65 define_pd_global(intx, PrefetchScanIntervalInBytes, -1);
66 define_pd_global(intx, PrefetchFieldsAhead, -1);
68 define_pd_global(intx, StackYellowPages, 2);
69 define_pd_global(intx, StackRedPages, 1);
70 define_pd_global(intx, StackShadowPages, 3 DEBUG_ONLY(+1));
72 define_pd_global(bool, RewriteBytecodes, true);
73 define_pd_global(bool, RewriteFrequentPairs, true);
74 #ifdef _ALLBSD_SOURCE
75 define_pd_global(bool, UseMembar, true);
76 #else
77 define_pd_global(bool, UseMembar, false);
78 #endif
79 // GC Ergo Flags
80 define_pd_global(intx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread
82 define_pd_global(uintx, TypeProfileLevel, 111);
84 // Only c2 cares about this at the moment
85 define_pd_global(intx, AllocatePrefetchStyle, 2);
86 define_pd_global(intx, AllocatePrefetchDistance, -1);
88 #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \
89 \
90 product(intx, SetFSFOFN, 999, \
91 "Set the FS/FO/FN bits in FCSR" \
92 "999 means FS/FO/FN will not be changed" \
93 "=XYZ, with X:FS, Y:FO, Z:FN, X, Y and Z in 0=off, 1=on") \
94 \
95 develop(bool, IEEEPrecision, true, \
96 "Enables IEEE precision (for INTEL only)") \
97 \
98 product(intx, FenceInstruction, 0, \
99 "(Unsafe,Unstable) Experimental") \
100 \
101 product(intx, ReadPrefetchInstr, 0, \
102 "Prefetch instruction to prefetch ahead") \
103 \
104 product(bool, UseStoreImmI16, true, \
105 "Use store immediate 16-bits value instruction on x86") \
106 \
107 product(intx, UseAVX, 99, \
108 "Highest supported AVX instructions set on x86/x64") \
109 \
110 diagnostic(bool, UseIncDec, true, \
111 "Use INC, DEC instructions on x86") \
112 \
113 product(bool, UseNewLongLShift, false, \
114 "Use optimized bitwise shift left") \
115 \
116 product(bool, UseAddressNop, false, \
117 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \
118 \
119 product(bool, UseXmmLoadAndClearUpper, true, \
120 "Load low part of XMM register and clear upper part") \
121 \
122 product(bool, UseXmmRegToRegMoveAll, false, \
123 "Copy all XMM register bits when moving value between registers") \
124 \
125 product(bool, UseXmmI2D, false, \
126 "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \
127 \
128 product(bool, UseXmmI2F, false, \
129 "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \
130 \
131 product(bool, UseUnalignedLoadStores, false, \
132 "Use SSE2 MOVDQU instruction for Arraycopy") \
133 \
134 /* assembler */ \
135 product(bool, Use486InstrsOnly, false, \
136 "Use 80486 Compliant instruction subset") \
137 \
138 product(bool, UseCountLeadingZerosInstruction, false, \
139 "Use count leading zeros instruction") \
140 \
141 /* 2014/04/22 Fu: Added to improve the startup performance */ \
142 product(intx, MaxCompileQueueSize, 64, \
143 "The maximum size of compile queue") \
144 \
145 /* 2014/07/07 Fu: Added to implement the size-and-speed scheduling */ \
146 product(intx, FactorOfSizeScheduling, 90, \
147 "The impact factor of size in the size-and-speed scheduling") \
148 \
149 product(intx, MinWatchTime, 800, \
150 "The min time to determine whether to remove a task in queue") \
151 \
152 product(intx, MinUpdateTime, 5, \
153 "The min time to update the speed of a method") \
154 \
155 /* Use Restricted Transactional Memory for lock eliding */ \
156 experimental(bool, UseRTMLocking, false, \
157 "Enable RTM lock eliding for inflated locks in compiled code") \
158 \
159 experimental(bool, UseRTMForStackLocks, false, \
160 "Enable RTM lock eliding for stack locks in compiled code") \
161 \
162 experimental(bool, UseRTMDeopt, false, \
163 "Perform deopt and recompilation based on RTM abort ratio") \
164 \
165 experimental(uintx, RTMRetryCount, 5, \
166 "Number of RTM retries on lock abort or busy") \
167 \
168 experimental(intx, RTMSpinLoopCount, 100, \
169 "Spin count for lock to become free before RTM retry") \
170 \
171 experimental(intx, RTMAbortThreshold, 1000, \
172 "Calculate abort ratio after this number of aborts") \
173 \
174 experimental(intx, RTMLockingThreshold, 10000, \
175 "Lock count at which to do RTM lock eliding without " \
176 "abort ratio calculation") \
177 \
178 experimental(intx, RTMAbortRatio, 50, \
179 "Lock abort ratio at which to stop use RTM lock eliding") \
180 \
181 experimental(intx, RTMTotalCountIncrRate, 64, \
182 "Increment total RTM attempted lock count once every n times") \
183 \
184 experimental(intx, RTMLockingCalculationDelay, 0, \
185 "Number of milliseconds to wait before start calculating aborts " \
186 "for RTM locking") \
187 \
188 experimental(bool, UseRTMXendForLockBusy, true, \
189 "Use RTM Xend instead of Xabort when lock busy") \
190 \
191 product(intx, MaxUpdateTime, 80, \
192 "The max time to update the speed of a method") \
193 \
194 product(intx, InvocationOldThreshold, 12000, \
195 "The invocation counter threshold for an old method") \
196 \
197 product(intx, LoopOldThreshold, 20000, \
198 "The backedge counter threshold for an old method") \
199 \
200 product(bool, UseCountTrailingZerosInstruction, false, \
201 "Use count trailing zeros instruction") \
202 \
203 product(bool, UseBMI1Instructions, false, \
204 "Use BMI instructions")
206 #endif // CPU_MIPS_VM_GLOBALS_MIPS_HPP
