src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp

Thu, 07 Apr 2011 09:53:20 -0700

author
johnc
date
Thu, 07 Apr 2011 09:53:20 -0700
changeset 2781
e1162778c1c8
parent 2344
ac637b7220d1
child 3435
898522ae3c32
permissions
-rw-r--r--

7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
Summary: A referent object that is only weakly reachable at the start of concurrent marking but is re-attached to the strongly reachable object graph during marking may not be marked as live. This can cause the reference object to be processed prematurely and leave dangling pointers to the referent object. Implement a read barrier for the java.lang.ref.Reference::referent field by intrinsifying the Reference.get() method, and intercepting accesses though JNI, reflection, and Unsafe, so that when a non-null referent object is read it is also logged in an SATB buffer.
Reviewed-by: kvn, iveresov, never, tonyp, dholmes

     1 /*
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     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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     5  * This code is free software; you can redistribute it and/or modify it
     6  * under the terms of the GNU General Public License version 2 only, as
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    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    12  * version 2 for more details (a copy is included in the LICENSE file that
    13  * accompanied this code).
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    25 #ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
    26 #define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
    28  private:
    30   //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    31   //
    32   // Sparc load/store emission
    33   //
    34   // The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
    35   // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
    36   // by allowing 32 bit displacements:
    37   //
    38   //    When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
    39   //    When disp >  13 bits long, code is emitted to set the displacement into the O7 register,
    40   //       and then a load or store is emitted with ([O7] + [d]).
    41   //
    43   int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned);
    44   int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide);
    46   int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned);
    47   int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide);
    49   void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
    51   int shift_amount(BasicType t);
    53   static bool is_single_instruction(LIR_Op* op);
    55   // Record the type of the receiver in ReceiverTypeData
    56   void type_profile_helper(Register mdo, int mdo_offset_bias,
    57                            ciMethodData *md, ciProfileData *data,
    58                            Register recv, Register tmp1, Label* update_done);
    59   // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.
    60   void setup_md_access(ciMethod* method, int bci,
    61                        ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);
    62  public:
    63   void   pack64(LIR_Opr src, LIR_Opr dst);
    64   void unpack64(LIR_Opr src, LIR_Opr dst);
    66 enum {
    67 #ifdef _LP64
    68          call_stub_size = 68,
    69 #else
    70          call_stub_size = 20,
    71 #endif // _LP64
    72          exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4),
    73          deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4) };
    75 #endif // CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP

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