Tue, 20 Dec 2011 12:33:05 +0100
7116216: StackOverflow GC crash
Summary: GC crash for explicit stack overflow checks after a C2I transition.
Reviewed-by: coleenp, never
Contributed-by: yang02.wang@sap.com, bertrand.delsart@oracle.com
1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
28 class BiasedLockingCounters;
30 // Contains all the definitions needed for x86 assembly code generation.
32 // Calling convention
33 class Argument VALUE_OBJ_CLASS_SPEC {
34 public:
35 enum {
36 #ifdef _LP64
37 #ifdef _WIN64
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
40 #else
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
43 #endif // _WIN64
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
46 #else
47 n_register_parameters = 0 // 0 registers used to pass arguments
48 #endif // _LP64
49 };
50 };
53 #ifdef _LP64
54 // Symbolically name the register arguments used by the c calling convention.
55 // Windows is different from linux/solaris. So much for standards...
57 #ifdef _WIN64
59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
61 REGISTER_DECLARATION(Register, c_rarg2, r8);
62 REGISTER_DECLARATION(Register, c_rarg3, r9);
64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
69 #else
71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
75 REGISTER_DECLARATION(Register, c_rarg4, r8);
76 REGISTER_DECLARATION(Register, c_rarg5, r9);
78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
87 #endif // _WIN64
89 // Symbolically name the register arguments used by the Java calling convention.
90 // We have control over the convention for java so we can do what we please.
91 // What pleases us is to offset the java calling convention so that when
92 // we call a suitable jni method the arguments are lined up and we don't
93 // have to do little shuffling. A suitable jni method is non-static and a
94 // small number of arguments (two fewer args on windows)
95 //
96 // |-------------------------------------------------------|
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
98 // |-------------------------------------------------------|
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux
101 // |-------------------------------------------------------|
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
103 // |-------------------------------------------------------|
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
108 // Windows runs out of register args here
109 #ifdef _WIN64
110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
112 #else
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
115 #endif /* _WIN64 */
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
133 #else
134 // rscratch1 will apear in 32bit code that is dead but of course must compile
135 // Using noreg ensures if the dead code is incorrectly live and executed it
136 // will cause an assertion failure
137 #define rscratch1 noreg
138 #define rscratch2 noreg
140 #endif // _LP64
142 // JSR 292 fixed register usages:
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
145 // Address is an abstraction used to represent a memory location
146 // using any of the amd64 addressing modes with one object.
147 //
148 // Note: A register location is represented via a Register, not
149 // via an address for efficiency & simplicity reasons.
151 class ArrayAddress;
153 class Address VALUE_OBJ_CLASS_SPEC {
154 public:
155 enum ScaleFactor {
156 no_scale = -1,
157 times_1 = 0,
158 times_2 = 1,
159 times_4 = 2,
160 times_8 = 3,
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
162 };
163 static ScaleFactor times(int size) {
164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
165 if (size == 8) return times_8;
166 if (size == 4) return times_4;
167 if (size == 2) return times_2;
168 return times_1;
169 }
170 static int scale_size(ScaleFactor scale) {
171 assert(scale != no_scale, "");
172 assert(((1 << (int)times_1) == 1 &&
173 (1 << (int)times_2) == 2 &&
174 (1 << (int)times_4) == 4 &&
175 (1 << (int)times_8) == 8), "");
176 return (1 << (int)scale);
177 }
179 private:
180 Register _base;
181 Register _index;
182 ScaleFactor _scale;
183 int _disp;
184 RelocationHolder _rspec;
186 // Easily misused constructors make them private
187 // %%% can we make these go away?
188 NOT_LP64(Address(address loc, RelocationHolder spec);)
189 Address(int disp, address loc, relocInfo::relocType rtype);
190 Address(int disp, address loc, RelocationHolder spec);
192 public:
194 int disp() { return _disp; }
195 // creation
196 Address()
197 : _base(noreg),
198 _index(noreg),
199 _scale(no_scale),
200 _disp(0) {
201 }
203 // No default displacement otherwise Register can be implicitly
204 // converted to 0(Register) which is quite a different animal.
206 Address(Register base, int disp)
207 : _base(base),
208 _index(noreg),
209 _scale(no_scale),
210 _disp(disp) {
211 }
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
214 : _base (base),
215 _index(index),
216 _scale(scale),
217 _disp (disp) {
218 assert(!index->is_valid() == (scale == Address::no_scale),
219 "inconsistent address");
220 }
222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
223 : _base (base),
224 _index(index.register_or_noreg()),
225 _scale(scale),
226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
227 if (!index.is_register()) scale = Address::no_scale;
228 assert(!_index->is_valid() == (scale == Address::no_scale),
229 "inconsistent address");
230 }
232 Address plus_disp(int disp) const {
233 Address a = (*this);
234 a._disp += disp;
235 return a;
236 }
237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
238 Address a = (*this);
239 a._disp += disp.constant_or_zero() * scale_size(scale);
240 if (disp.is_register()) {
241 assert(!a.index()->is_valid(), "competing indexes");
242 a._index = disp.as_register();
243 a._scale = scale;
244 }
245 return a;
246 }
247 bool is_same_address(Address a) const {
248 // disregard _rspec
249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
250 }
252 // The following two overloads are used in connection with the
253 // ByteSize type (see sizes.hpp). They simplify the use of
254 // ByteSize'd arguments in assembly code. Note that their equivalent
255 // for the optimized build are the member functions with int disp
256 // argument since ByteSize is mapped to an int type in that case.
257 //
258 // Note: DO NOT introduce similar overloaded functions for WordSize
259 // arguments as in the optimized mode, both ByteSize and WordSize
260 // are mapped to the same type and thus the compiler cannot make a
261 // distinction anymore (=> compiler errors).
263 #ifdef ASSERT
264 Address(Register base, ByteSize disp)
265 : _base(base),
266 _index(noreg),
267 _scale(no_scale),
268 _disp(in_bytes(disp)) {
269 }
271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
272 : _base(base),
273 _index(index),
274 _scale(scale),
275 _disp(in_bytes(disp)) {
276 assert(!index->is_valid() == (scale == Address::no_scale),
277 "inconsistent address");
278 }
280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
281 : _base (base),
282 _index(index.register_or_noreg()),
283 _scale(scale),
284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
285 if (!index.is_register()) scale = Address::no_scale;
286 assert(!_index->is_valid() == (scale == Address::no_scale),
287 "inconsistent address");
288 }
290 #endif // ASSERT
292 // accessors
293 bool uses(Register reg) const { return _base == reg || _index == reg; }
294 Register base() const { return _base; }
295 Register index() const { return _index; }
296 ScaleFactor scale() const { return _scale; }
297 int disp() const { return _disp; }
299 // Convert the raw encoding form into the form expected by the constructor for
300 // Address. An index of 4 (rsp) corresponds to having no index, so convert
301 // that to noreg for the Address constructor.
302 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
304 static Address make_array(ArrayAddress);
306 private:
307 bool base_needs_rex() const {
308 return _base != noreg && _base->encoding() >= 8;
309 }
311 bool index_needs_rex() const {
312 return _index != noreg &&_index->encoding() >= 8;
313 }
315 relocInfo::relocType reloc() const { return _rspec.type(); }
317 friend class Assembler;
318 friend class MacroAssembler;
319 friend class LIR_Assembler; // base/index/scale/disp
320 };
322 //
323 // AddressLiteral has been split out from Address because operands of this type
324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
325 // the few instructions that need to deal with address literals are unique and the
326 // MacroAssembler does not have to implement every instruction in the Assembler
327 // in order to search for address literals that may need special handling depending
328 // on the instruction and the platform. As small step on the way to merging i486/amd64
329 // directories.
330 //
331 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
332 friend class ArrayAddress;
333 RelocationHolder _rspec;
334 // Typically we use AddressLiterals we want to use their rval
335 // However in some situations we want the lval (effect address) of the item.
336 // We provide a special factory for making those lvals.
337 bool _is_lval;
339 // If the target is far we'll need to load the ea of this to
340 // a register to reach it. Otherwise if near we can do rip
341 // relative addressing.
343 address _target;
345 protected:
346 // creation
347 AddressLiteral()
348 : _is_lval(false),
349 _target(NULL)
350 {}
352 public:
355 AddressLiteral(address target, relocInfo::relocType rtype);
357 AddressLiteral(address target, RelocationHolder const& rspec)
358 : _rspec(rspec),
359 _is_lval(false),
360 _target(target)
361 {}
363 AddressLiteral addr() {
364 AddressLiteral ret = *this;
365 ret._is_lval = true;
366 return ret;
367 }
370 private:
372 address target() { return _target; }
373 bool is_lval() { return _is_lval; }
375 relocInfo::relocType reloc() const { return _rspec.type(); }
376 const RelocationHolder& rspec() const { return _rspec; }
378 friend class Assembler;
379 friend class MacroAssembler;
380 friend class Address;
381 friend class LIR_Assembler;
382 };
384 // Convience classes
385 class RuntimeAddress: public AddressLiteral {
387 public:
389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
391 };
393 class OopAddress: public AddressLiteral {
395 public:
397 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
399 };
401 class ExternalAddress: public AddressLiteral {
402 private:
403 static relocInfo::relocType reloc_for_target(address target) {
404 // Sometimes ExternalAddress is used for values which aren't
405 // exactly addresses, like the card table base.
406 // external_word_type can't be used for values in the first page
407 // so just skip the reloc in that case.
408 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
409 }
411 public:
413 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
415 };
417 class InternalAddress: public AddressLiteral {
419 public:
421 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
423 };
425 // x86 can do array addressing as a single operation since disp can be an absolute
426 // address amd64 can't. We create a class that expresses the concept but does extra
427 // magic on amd64 to get the final result
429 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
430 private:
432 AddressLiteral _base;
433 Address _index;
435 public:
437 ArrayAddress() {};
438 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
439 AddressLiteral base() { return _base; }
440 Address index() { return _index; }
442 };
444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
448 // is what you get. The Assembler is generating code into a CodeBuffer.
450 class Assembler : public AbstractAssembler {
451 friend class AbstractAssembler; // for the non-virtual hack
452 friend class LIR_Assembler; // as_Address()
453 friend class StubGenerator;
455 public:
456 enum Condition { // The x86 condition codes used for conditional jumps/moves.
457 zero = 0x4,
458 notZero = 0x5,
459 equal = 0x4,
460 notEqual = 0x5,
461 less = 0xc,
462 lessEqual = 0xe,
463 greater = 0xf,
464 greaterEqual = 0xd,
465 below = 0x2,
466 belowEqual = 0x6,
467 above = 0x7,
468 aboveEqual = 0x3,
469 overflow = 0x0,
470 noOverflow = 0x1,
471 carrySet = 0x2,
472 carryClear = 0x3,
473 negative = 0x8,
474 positive = 0x9,
475 parity = 0xa,
476 noParity = 0xb
477 };
479 enum Prefix {
480 // segment overrides
481 CS_segment = 0x2e,
482 SS_segment = 0x36,
483 DS_segment = 0x3e,
484 ES_segment = 0x26,
485 FS_segment = 0x64,
486 GS_segment = 0x65,
488 REX = 0x40,
490 REX_B = 0x41,
491 REX_X = 0x42,
492 REX_XB = 0x43,
493 REX_R = 0x44,
494 REX_RB = 0x45,
495 REX_RX = 0x46,
496 REX_RXB = 0x47,
498 REX_W = 0x48,
500 REX_WB = 0x49,
501 REX_WX = 0x4A,
502 REX_WXB = 0x4B,
503 REX_WR = 0x4C,
504 REX_WRB = 0x4D,
505 REX_WRX = 0x4E,
506 REX_WRXB = 0x4F
507 };
509 enum WhichOperand {
510 // input to locate_operand, and format code for relocations
511 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
512 disp32_operand = 1, // embedded 32-bit displacement or address
513 call32_operand = 2, // embedded 32-bit self-relative displacement
514 #ifndef _LP64
515 _WhichOperand_limit = 3
516 #else
517 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
518 _WhichOperand_limit = 4
519 #endif
520 };
524 // NOTE: The general philopsophy of the declarations here is that 64bit versions
525 // of instructions are freely declared without the need for wrapping them an ifdef.
526 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
527 // In the .cpp file the implementations are wrapped so that they are dropped out
528 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
529 // to the size it was prior to merging up the 32bit and 64bit assemblers.
530 //
531 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
532 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
534 private:
537 // 64bit prefixes
538 int prefix_and_encode(int reg_enc, bool byteinst = false);
539 int prefixq_and_encode(int reg_enc);
541 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
542 int prefixq_and_encode(int dst_enc, int src_enc);
544 void prefix(Register reg);
545 void prefix(Address adr);
546 void prefixq(Address adr);
548 void prefix(Address adr, Register reg, bool byteinst = false);
549 void prefixq(Address adr, Register reg);
551 void prefix(Address adr, XMMRegister reg);
553 void prefetch_prefix(Address src);
555 // Helper functions for groups of instructions
556 void emit_arith_b(int op1, int op2, Register dst, int imm8);
558 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
559 // only 32bit??
560 void emit_arith(int op1, int op2, Register dst, jobject obj);
561 void emit_arith(int op1, int op2, Register dst, Register src);
563 void emit_operand(Register reg,
564 Register base, Register index, Address::ScaleFactor scale,
565 int disp,
566 RelocationHolder const& rspec,
567 int rip_relative_correction = 0);
569 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
571 // operands that only take the original 32bit registers
572 void emit_operand32(Register reg, Address adr);
574 void emit_operand(XMMRegister reg,
575 Register base, Register index, Address::ScaleFactor scale,
576 int disp,
577 RelocationHolder const& rspec);
579 void emit_operand(XMMRegister reg, Address adr);
581 void emit_operand(MMXRegister reg, Address adr);
583 // workaround gcc (3.2.1-7) bug
584 void emit_operand(Address adr, MMXRegister reg);
587 // Immediate-to-memory forms
588 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
590 void emit_farith(int b1, int b2, int i);
593 protected:
594 #ifdef ASSERT
595 void check_relocation(RelocationHolder const& rspec, int format);
596 #endif
598 inline void emit_long64(jlong x);
600 void emit_data(jint data, relocInfo::relocType rtype, int format);
601 void emit_data(jint data, RelocationHolder const& rspec, int format);
602 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
603 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
605 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
607 // These are all easily abused and hence protected
609 // 32BIT ONLY SECTION
610 #ifndef _LP64
611 // Make these disappear in 64bit mode since they would never be correct
612 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
613 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
615 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
616 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
618 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
619 #else
620 // 64BIT ONLY SECTION
621 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
623 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
624 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
626 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
627 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
628 #endif // _LP64
630 // These are unique in that we are ensured by the caller that the 32bit
631 // relative in these instructions will always be able to reach the potentially
632 // 64bit address described by entry. Since they can take a 64bit address they
633 // don't have the 32 suffix like the other instructions in this class.
635 void call_literal(address entry, RelocationHolder const& rspec);
636 void jmp_literal(address entry, RelocationHolder const& rspec);
638 // Avoid using directly section
639 // Instructions in this section are actually usable by anyone without danger
640 // of failure but have performance issues that are addressed my enhanced
641 // instructions which will do the proper thing base on the particular cpu.
642 // We protect them because we don't trust you...
644 // Don't use next inc() and dec() methods directly. INC & DEC instructions
645 // could cause a partial flag stall since they don't set CF flag.
646 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
647 // which call inc() & dec() or add() & sub() in accordance with
648 // the product flag UseIncDec value.
650 void decl(Register dst);
651 void decl(Address dst);
652 void decq(Register dst);
653 void decq(Address dst);
655 void incl(Register dst);
656 void incl(Address dst);
657 void incq(Register dst);
658 void incq(Address dst);
660 // New cpus require use of movsd and movss to avoid partial register stall
661 // when loading from memory. But for old Opteron use movlpd instead of movsd.
662 // The selection is done in MacroAssembler::movdbl() and movflt().
664 // Move Scalar Single-Precision Floating-Point Values
665 void movss(XMMRegister dst, Address src);
666 void movss(XMMRegister dst, XMMRegister src);
667 void movss(Address dst, XMMRegister src);
669 // Move Scalar Double-Precision Floating-Point Values
670 void movsd(XMMRegister dst, Address src);
671 void movsd(XMMRegister dst, XMMRegister src);
672 void movsd(Address dst, XMMRegister src);
673 void movlpd(XMMRegister dst, Address src);
675 // New cpus require use of movaps and movapd to avoid partial register stall
676 // when moving between registers.
677 void movaps(XMMRegister dst, XMMRegister src);
678 void movapd(XMMRegister dst, XMMRegister src);
680 // End avoid using directly
683 // Instruction prefixes
684 void prefix(Prefix p);
686 public:
688 // Creation
689 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
691 // Decoding
692 static address locate_operand(address inst, WhichOperand which);
693 static address locate_next_instruction(address inst);
695 // Utilities
696 static bool is_polling_page_far() NOT_LP64({ return false;});
698 // Generic instructions
699 // Does 32bit or 64bit as needed for the platform. In some sense these
700 // belong in macro assembler but there is no need for both varieties to exist
702 void lea(Register dst, Address src);
704 void mov(Register dst, Register src);
706 void pusha();
707 void popa();
709 void pushf();
710 void popf();
712 void push(int32_t imm32);
714 void push(Register src);
716 void pop(Register dst);
718 // These are dummies to prevent surprise implicit conversions to Register
719 void push(void* v);
720 void pop(void* v);
722 // These do register sized moves/scans
723 void rep_mov();
724 void rep_set();
725 void repne_scan();
726 #ifdef _LP64
727 void repne_scanl();
728 #endif
730 // Vanilla instructions in lexical order
732 void adcl(Address dst, int32_t imm32);
733 void adcl(Address dst, Register src);
734 void adcl(Register dst, int32_t imm32);
735 void adcl(Register dst, Address src);
736 void adcl(Register dst, Register src);
738 void adcq(Register dst, int32_t imm32);
739 void adcq(Register dst, Address src);
740 void adcq(Register dst, Register src);
742 void addl(Address dst, int32_t imm32);
743 void addl(Address dst, Register src);
744 void addl(Register dst, int32_t imm32);
745 void addl(Register dst, Address src);
746 void addl(Register dst, Register src);
748 void addq(Address dst, int32_t imm32);
749 void addq(Address dst, Register src);
750 void addq(Register dst, int32_t imm32);
751 void addq(Register dst, Address src);
752 void addq(Register dst, Register src);
754 void addr_nop_4();
755 void addr_nop_5();
756 void addr_nop_7();
757 void addr_nop_8();
759 // Add Scalar Double-Precision Floating-Point Values
760 void addsd(XMMRegister dst, Address src);
761 void addsd(XMMRegister dst, XMMRegister src);
763 // Add Scalar Single-Precision Floating-Point Values
764 void addss(XMMRegister dst, Address src);
765 void addss(XMMRegister dst, XMMRegister src);
767 void andl(Register dst, int32_t imm32);
768 void andl(Register dst, Address src);
769 void andl(Register dst, Register src);
771 void andq(Address dst, int32_t imm32);
772 void andq(Register dst, int32_t imm32);
773 void andq(Register dst, Address src);
774 void andq(Register dst, Register src);
776 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
777 void andpd(XMMRegister dst, Address src);
778 void andpd(XMMRegister dst, XMMRegister src);
780 void bsfl(Register dst, Register src);
781 void bsrl(Register dst, Register src);
783 #ifdef _LP64
784 void bsfq(Register dst, Register src);
785 void bsrq(Register dst, Register src);
786 #endif
788 void bswapl(Register reg);
790 void bswapq(Register reg);
792 void call(Label& L, relocInfo::relocType rtype);
793 void call(Register reg); // push pc; pc <- reg
794 void call(Address adr); // push pc; pc <- adr
796 void cdql();
798 void cdqq();
800 void cld() { emit_byte(0xfc); }
802 void clflush(Address adr);
804 void cmovl(Condition cc, Register dst, Register src);
805 void cmovl(Condition cc, Register dst, Address src);
807 void cmovq(Condition cc, Register dst, Register src);
808 void cmovq(Condition cc, Register dst, Address src);
811 void cmpb(Address dst, int imm8);
813 void cmpl(Address dst, int32_t imm32);
815 void cmpl(Register dst, int32_t imm32);
816 void cmpl(Register dst, Register src);
817 void cmpl(Register dst, Address src);
819 void cmpq(Address dst, int32_t imm32);
820 void cmpq(Address dst, Register src);
822 void cmpq(Register dst, int32_t imm32);
823 void cmpq(Register dst, Register src);
824 void cmpq(Register dst, Address src);
826 // these are dummies used to catch attempting to convert NULL to Register
827 void cmpl(Register dst, void* junk); // dummy
828 void cmpq(Register dst, void* junk); // dummy
830 void cmpw(Address dst, int imm16);
832 void cmpxchg8 (Address adr);
834 void cmpxchgl(Register reg, Address adr);
836 void cmpxchgq(Register reg, Address adr);
838 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
839 void comisd(XMMRegister dst, Address src);
841 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
842 void comiss(XMMRegister dst, Address src);
844 // Identify processor type and features
845 void cpuid() {
846 emit_byte(0x0F);
847 emit_byte(0xA2);
848 }
850 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
851 void cvtsd2ss(XMMRegister dst, XMMRegister src);
853 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
854 void cvtsi2sdl(XMMRegister dst, Register src);
855 void cvtsi2sdq(XMMRegister dst, Register src);
857 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
858 void cvtsi2ssl(XMMRegister dst, Register src);
859 void cvtsi2ssq(XMMRegister dst, Register src);
861 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
862 void cvtdq2pd(XMMRegister dst, XMMRegister src);
864 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
865 void cvtdq2ps(XMMRegister dst, XMMRegister src);
867 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
868 void cvtss2sd(XMMRegister dst, XMMRegister src);
870 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
871 void cvttsd2sil(Register dst, Address src);
872 void cvttsd2sil(Register dst, XMMRegister src);
873 void cvttsd2siq(Register dst, XMMRegister src);
875 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
876 void cvttss2sil(Register dst, XMMRegister src);
877 void cvttss2siq(Register dst, XMMRegister src);
879 // Divide Scalar Double-Precision Floating-Point Values
880 void divsd(XMMRegister dst, Address src);
881 void divsd(XMMRegister dst, XMMRegister src);
883 // Divide Scalar Single-Precision Floating-Point Values
884 void divss(XMMRegister dst, Address src);
885 void divss(XMMRegister dst, XMMRegister src);
887 void emms();
889 void fabs();
891 void fadd(int i);
893 void fadd_d(Address src);
894 void fadd_s(Address src);
896 // "Alternate" versions of x87 instructions place result down in FPU
897 // stack instead of on TOS
899 void fadda(int i); // "alternate" fadd
900 void faddp(int i = 1);
902 void fchs();
904 void fcom(int i);
906 void fcomp(int i = 1);
907 void fcomp_d(Address src);
908 void fcomp_s(Address src);
910 void fcompp();
912 void fcos();
914 void fdecstp();
916 void fdiv(int i);
917 void fdiv_d(Address src);
918 void fdivr_s(Address src);
919 void fdiva(int i); // "alternate" fdiv
920 void fdivp(int i = 1);
922 void fdivr(int i);
923 void fdivr_d(Address src);
924 void fdiv_s(Address src);
926 void fdivra(int i); // "alternate" reversed fdiv
928 void fdivrp(int i = 1);
930 void ffree(int i = 0);
932 void fild_d(Address adr);
933 void fild_s(Address adr);
935 void fincstp();
937 void finit();
939 void fist_s (Address adr);
940 void fistp_d(Address adr);
941 void fistp_s(Address adr);
943 void fld1();
945 void fld_d(Address adr);
946 void fld_s(Address adr);
947 void fld_s(int index);
948 void fld_x(Address adr); // extended-precision (80-bit) format
950 void fldcw(Address src);
952 void fldenv(Address src);
954 void fldlg2();
956 void fldln2();
958 void fldz();
960 void flog();
961 void flog10();
963 void fmul(int i);
965 void fmul_d(Address src);
966 void fmul_s(Address src);
968 void fmula(int i); // "alternate" fmul
970 void fmulp(int i = 1);
972 void fnsave(Address dst);
974 void fnstcw(Address src);
976 void fnstsw_ax();
978 void fprem();
979 void fprem1();
981 void frstor(Address src);
983 void fsin();
985 void fsqrt();
987 void fst_d(Address adr);
988 void fst_s(Address adr);
990 void fstp_d(Address adr);
991 void fstp_d(int index);
992 void fstp_s(Address adr);
993 void fstp_x(Address adr); // extended-precision (80-bit) format
995 void fsub(int i);
996 void fsub_d(Address src);
997 void fsub_s(Address src);
999 void fsuba(int i); // "alternate" fsub
1001 void fsubp(int i = 1);
1003 void fsubr(int i);
1004 void fsubr_d(Address src);
1005 void fsubr_s(Address src);
1007 void fsubra(int i); // "alternate" reversed fsub
1009 void fsubrp(int i = 1);
1011 void ftan();
1013 void ftst();
1015 void fucomi(int i = 1);
1016 void fucomip(int i = 1);
1018 void fwait();
1020 void fxch(int i = 1);
1022 void fxrstor(Address src);
1024 void fxsave(Address dst);
1026 void fyl2x();
1028 void hlt();
1030 void idivl(Register src);
1031 void divl(Register src); // Unsigned division
1033 void idivq(Register src);
1035 void imull(Register dst, Register src);
1036 void imull(Register dst, Register src, int value);
1038 void imulq(Register dst, Register src);
1039 void imulq(Register dst, Register src, int value);
1042 // jcc is the generic conditional branch generator to run-
1043 // time routines, jcc is used for branches to labels. jcc
1044 // takes a branch opcode (cc) and a label (L) and generates
1045 // either a backward branch or a forward branch and links it
1046 // to the label fixup chain. Usage:
1047 //
1048 // Label L; // unbound label
1049 // jcc(cc, L); // forward branch to unbound label
1050 // bind(L); // bind label to the current pc
1051 // jcc(cc, L); // backward branch to bound label
1052 // bind(L); // illegal: a label may be bound only once
1053 //
1054 // Note: The same Label can be used for forward and backward branches
1055 // but it may be bound only once.
1057 void jcc(Condition cc, Label& L, bool maybe_short = true);
1059 // Conditional jump to a 8-bit offset to L.
1060 // WARNING: be very careful using this for forward jumps. If the label is
1061 // not bound within an 8-bit offset of this instruction, a run-time error
1062 // will occur.
1063 void jccb(Condition cc, Label& L);
1065 void jmp(Address entry); // pc <- entry
1067 // Label operations & relative jumps (PPUM Appendix D)
1068 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1070 void jmp(Register entry); // pc <- entry
1072 // Unconditional 8-bit offset jump to L.
1073 // WARNING: be very careful using this for forward jumps. If the label is
1074 // not bound within an 8-bit offset of this instruction, a run-time error
1075 // will occur.
1076 void jmpb(Label& L);
1078 void ldmxcsr( Address src );
1080 void leal(Register dst, Address src);
1082 void leaq(Register dst, Address src);
1084 void lfence() {
1085 emit_byte(0x0F);
1086 emit_byte(0xAE);
1087 emit_byte(0xE8);
1088 }
1090 void lock();
1092 void lzcntl(Register dst, Register src);
1094 #ifdef _LP64
1095 void lzcntq(Register dst, Register src);
1096 #endif
1098 enum Membar_mask_bits {
1099 StoreStore = 1 << 3,
1100 LoadStore = 1 << 2,
1101 StoreLoad = 1 << 1,
1102 LoadLoad = 1 << 0
1103 };
1105 // Serializes memory and blows flags
1106 void membar(Membar_mask_bits order_constraint) {
1107 if (os::is_MP()) {
1108 // We only have to handle StoreLoad
1109 if (order_constraint & StoreLoad) {
1110 // All usable chips support "locked" instructions which suffice
1111 // as barriers, and are much faster than the alternative of
1112 // using cpuid instruction. We use here a locked add [esp],0.
1113 // This is conveniently otherwise a no-op except for blowing
1114 // flags.
1115 // Any change to this code may need to revisit other places in
1116 // the code where this idiom is used, in particular the
1117 // orderAccess code.
1118 lock();
1119 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1120 }
1121 }
1122 }
1124 void mfence();
1126 // Moves
1128 void mov64(Register dst, int64_t imm64);
1130 void movb(Address dst, Register src);
1131 void movb(Address dst, int imm8);
1132 void movb(Register dst, Address src);
1134 void movdl(XMMRegister dst, Register src);
1135 void movdl(Register dst, XMMRegister src);
1136 void movdl(XMMRegister dst, Address src);
1138 // Move Double Quadword
1139 void movdq(XMMRegister dst, Register src);
1140 void movdq(Register dst, XMMRegister src);
1142 // Move Aligned Double Quadword
1143 void movdqa(Address dst, XMMRegister src);
1144 void movdqa(XMMRegister dst, Address src);
1145 void movdqa(XMMRegister dst, XMMRegister src);
1147 // Move Unaligned Double Quadword
1148 void movdqu(Address dst, XMMRegister src);
1149 void movdqu(XMMRegister dst, Address src);
1150 void movdqu(XMMRegister dst, XMMRegister src);
1152 void movl(Register dst, int32_t imm32);
1153 void movl(Address dst, int32_t imm32);
1154 void movl(Register dst, Register src);
1155 void movl(Register dst, Address src);
1156 void movl(Address dst, Register src);
1158 // These dummies prevent using movl from converting a zero (like NULL) into Register
1159 // by giving the compiler two choices it can't resolve
1161 void movl(Address dst, void* junk);
1162 void movl(Register dst, void* junk);
1164 #ifdef _LP64
1165 void movq(Register dst, Register src);
1166 void movq(Register dst, Address src);
1167 void movq(Address dst, Register src);
1168 #endif
1170 void movq(Address dst, MMXRegister src );
1171 void movq(MMXRegister dst, Address src );
1173 #ifdef _LP64
1174 // These dummies prevent using movq from converting a zero (like NULL) into Register
1175 // by giving the compiler two choices it can't resolve
1177 void movq(Address dst, void* dummy);
1178 void movq(Register dst, void* dummy);
1179 #endif
1181 // Move Quadword
1182 void movq(Address dst, XMMRegister src);
1183 void movq(XMMRegister dst, Address src);
1185 void movsbl(Register dst, Address src);
1186 void movsbl(Register dst, Register src);
1188 #ifdef _LP64
1189 void movsbq(Register dst, Address src);
1190 void movsbq(Register dst, Register src);
1192 // Move signed 32bit immediate to 64bit extending sign
1193 void movslq(Address dst, int32_t imm64);
1194 void movslq(Register dst, int32_t imm64);
1196 void movslq(Register dst, Address src);
1197 void movslq(Register dst, Register src);
1198 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1199 #endif
1201 void movswl(Register dst, Address src);
1202 void movswl(Register dst, Register src);
1204 #ifdef _LP64
1205 void movswq(Register dst, Address src);
1206 void movswq(Register dst, Register src);
1207 #endif
1209 void movw(Address dst, int imm16);
1210 void movw(Register dst, Address src);
1211 void movw(Address dst, Register src);
1213 void movzbl(Register dst, Address src);
1214 void movzbl(Register dst, Register src);
1216 #ifdef _LP64
1217 void movzbq(Register dst, Address src);
1218 void movzbq(Register dst, Register src);
1219 #endif
1221 void movzwl(Register dst, Address src);
1222 void movzwl(Register dst, Register src);
1224 #ifdef _LP64
1225 void movzwq(Register dst, Address src);
1226 void movzwq(Register dst, Register src);
1227 #endif
1229 void mull(Address src);
1230 void mull(Register src);
1232 // Multiply Scalar Double-Precision Floating-Point Values
1233 void mulsd(XMMRegister dst, Address src);
1234 void mulsd(XMMRegister dst, XMMRegister src);
1236 // Multiply Scalar Single-Precision Floating-Point Values
1237 void mulss(XMMRegister dst, Address src);
1238 void mulss(XMMRegister dst, XMMRegister src);
1240 void negl(Register dst);
1242 #ifdef _LP64
1243 void negq(Register dst);
1244 #endif
1246 void nop(int i = 1);
1248 void notl(Register dst);
1250 #ifdef _LP64
1251 void notq(Register dst);
1252 #endif
1254 void orl(Address dst, int32_t imm32);
1255 void orl(Register dst, int32_t imm32);
1256 void orl(Register dst, Address src);
1257 void orl(Register dst, Register src);
1259 void orq(Address dst, int32_t imm32);
1260 void orq(Register dst, int32_t imm32);
1261 void orq(Register dst, Address src);
1262 void orq(Register dst, Register src);
1264 // SSE4.2 string instructions
1265 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1266 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1268 #ifndef _LP64 // no 32bit push/pop on amd64
1269 void popl(Address dst);
1270 #endif
1272 #ifdef _LP64
1273 void popq(Address dst);
1274 #endif
1276 void popcntl(Register dst, Address src);
1277 void popcntl(Register dst, Register src);
1279 #ifdef _LP64
1280 void popcntq(Register dst, Address src);
1281 void popcntq(Register dst, Register src);
1282 #endif
1284 // Prefetches (SSE, SSE2, 3DNOW only)
1286 void prefetchnta(Address src);
1287 void prefetchr(Address src);
1288 void prefetcht0(Address src);
1289 void prefetcht1(Address src);
1290 void prefetcht2(Address src);
1291 void prefetchw(Address src);
1293 // POR - Bitwise logical OR
1294 void por(XMMRegister dst, XMMRegister src);
1296 // Shuffle Packed Doublewords
1297 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1298 void pshufd(XMMRegister dst, Address src, int mode);
1300 // Shuffle Packed Low Words
1301 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1302 void pshuflw(XMMRegister dst, Address src, int mode);
1304 // Shift Right by bits Logical Quadword Immediate
1305 void psrlq(XMMRegister dst, int shift);
1307 // Shift Right by bytes Logical DoubleQuadword Immediate
1308 void psrldq(XMMRegister dst, int shift);
1310 // Logical Compare Double Quadword
1311 void ptest(XMMRegister dst, XMMRegister src);
1312 void ptest(XMMRegister dst, Address src);
1314 // Interleave Low Bytes
1315 void punpcklbw(XMMRegister dst, XMMRegister src);
1317 #ifndef _LP64 // no 32bit push/pop on amd64
1318 void pushl(Address src);
1319 #endif
1321 void pushq(Address src);
1323 // Xor Packed Byte Integer Values
1324 void pxor(XMMRegister dst, Address src);
1325 void pxor(XMMRegister dst, XMMRegister src);
1327 void rcll(Register dst, int imm8);
1329 void rclq(Register dst, int imm8);
1331 void ret(int imm16);
1333 void sahf();
1335 void sarl(Register dst, int imm8);
1336 void sarl(Register dst);
1338 void sarq(Register dst, int imm8);
1339 void sarq(Register dst);
1341 void sbbl(Address dst, int32_t imm32);
1342 void sbbl(Register dst, int32_t imm32);
1343 void sbbl(Register dst, Address src);
1344 void sbbl(Register dst, Register src);
1346 void sbbq(Address dst, int32_t imm32);
1347 void sbbq(Register dst, int32_t imm32);
1348 void sbbq(Register dst, Address src);
1349 void sbbq(Register dst, Register src);
1351 void setb(Condition cc, Register dst);
1353 void shldl(Register dst, Register src);
1355 void shll(Register dst, int imm8);
1356 void shll(Register dst);
1358 void shlq(Register dst, int imm8);
1359 void shlq(Register dst);
1361 void shrdl(Register dst, Register src);
1363 void shrl(Register dst, int imm8);
1364 void shrl(Register dst);
1366 void shrq(Register dst, int imm8);
1367 void shrq(Register dst);
1369 void smovl(); // QQQ generic?
1371 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1372 void sqrtsd(XMMRegister dst, Address src);
1373 void sqrtsd(XMMRegister dst, XMMRegister src);
1375 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1376 void sqrtss(XMMRegister dst, Address src);
1377 void sqrtss(XMMRegister dst, XMMRegister src);
1379 void std() { emit_byte(0xfd); }
1381 void stmxcsr( Address dst );
1383 void subl(Address dst, int32_t imm32);
1384 void subl(Address dst, Register src);
1385 void subl(Register dst, int32_t imm32);
1386 void subl(Register dst, Address src);
1387 void subl(Register dst, Register src);
1389 void subq(Address dst, int32_t imm32);
1390 void subq(Address dst, Register src);
1391 void subq(Register dst, int32_t imm32);
1392 void subq(Register dst, Address src);
1393 void subq(Register dst, Register src);
1396 // Subtract Scalar Double-Precision Floating-Point Values
1397 void subsd(XMMRegister dst, Address src);
1398 void subsd(XMMRegister dst, XMMRegister src);
1400 // Subtract Scalar Single-Precision Floating-Point Values
1401 void subss(XMMRegister dst, Address src);
1402 void subss(XMMRegister dst, XMMRegister src);
1404 void testb(Register dst, int imm8);
1406 void testl(Register dst, int32_t imm32);
1407 void testl(Register dst, Register src);
1408 void testl(Register dst, Address src);
1410 void testq(Register dst, int32_t imm32);
1411 void testq(Register dst, Register src);
1414 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1415 void ucomisd(XMMRegister dst, Address src);
1416 void ucomisd(XMMRegister dst, XMMRegister src);
1418 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1419 void ucomiss(XMMRegister dst, Address src);
1420 void ucomiss(XMMRegister dst, XMMRegister src);
1422 void xaddl(Address dst, Register src);
1424 void xaddq(Address dst, Register src);
1426 void xchgl(Register reg, Address adr);
1427 void xchgl(Register dst, Register src);
1429 void xchgq(Register reg, Address adr);
1430 void xchgq(Register dst, Register src);
1432 void xorl(Register dst, int32_t imm32);
1433 void xorl(Register dst, Address src);
1434 void xorl(Register dst, Register src);
1436 void xorq(Register dst, Address src);
1437 void xorq(Register dst, Register src);
1439 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1440 void xorpd(XMMRegister dst, Address src);
1441 void xorpd(XMMRegister dst, XMMRegister src);
1443 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1444 void xorps(XMMRegister dst, Address src);
1445 void xorps(XMMRegister dst, XMMRegister src);
1447 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1448 };
1451 // MacroAssembler extends Assembler by frequently used macros.
1452 //
1453 // Instructions for which a 'better' code sequence exists depending
1454 // on arguments should also go in here.
1456 class MacroAssembler: public Assembler {
1457 friend class LIR_Assembler;
1458 friend class Runtime1; // as_Address()
1460 protected:
1462 Address as_Address(AddressLiteral adr);
1463 Address as_Address(ArrayAddress adr);
1465 // Support for VM calls
1466 //
1467 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1468 // may customize this version by overriding it for its purposes (e.g., to save/restore
1469 // additional registers when doing a VM call).
1470 #ifdef CC_INTERP
1471 // c++ interpreter never wants to use interp_masm version of call_VM
1472 #define VIRTUAL
1473 #else
1474 #define VIRTUAL virtual
1475 #endif
1477 VIRTUAL void call_VM_leaf_base(
1478 address entry_point, // the entry point
1479 int number_of_arguments // the number of arguments to pop after the call
1480 );
1482 // This is the base routine called by the different versions of call_VM. The interpreter
1483 // may customize this version by overriding it for its purposes (e.g., to save/restore
1484 // additional registers when doing a VM call).
1485 //
1486 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1487 // returns the register which contains the thread upon return. If a thread register has been
1488 // specified, the return value will correspond to that register. If no last_java_sp is specified
1489 // (noreg) than rsp will be used instead.
1490 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1491 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1492 Register java_thread, // the thread if computed before ; use noreg otherwise
1493 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1494 address entry_point, // the entry point
1495 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1496 bool check_exceptions // whether to check for pending exceptions after return
1497 );
1499 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1500 // The implementation is only non-empty for the InterpreterMacroAssembler,
1501 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1502 virtual void check_and_handle_popframe(Register java_thread);
1503 virtual void check_and_handle_earlyret(Register java_thread);
1505 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1507 // helpers for FPU flag access
1508 // tmp is a temporary register, if none is available use noreg
1509 void save_rax (Register tmp);
1510 void restore_rax(Register tmp);
1512 public:
1513 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1515 // Support for NULL-checks
1516 //
1517 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1518 // If the accessed location is M[reg + offset] and the offset is known, provide the
1519 // offset. No explicit code generation is needed if the offset is within a certain
1520 // range (0 <= offset <= page_size).
1522 void null_check(Register reg, int offset = -1);
1523 static bool needs_explicit_null_check(intptr_t offset);
1525 // Required platform-specific helpers for Label::patch_instructions.
1526 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1527 void pd_patch_instruction(address branch, address target);
1528 #ifndef PRODUCT
1529 static void pd_print_patched_instruction(address branch);
1530 #endif
1532 // The following 4 methods return the offset of the appropriate move instruction
1534 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1535 int load_unsigned_byte(Register dst, Address src);
1536 int load_unsigned_short(Register dst, Address src);
1538 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1539 int load_signed_byte(Register dst, Address src);
1540 int load_signed_short(Register dst, Address src);
1542 // Support for sign-extension (hi:lo = extend_sign(lo))
1543 void extend_sign(Register hi, Register lo);
1545 // Load and store values by size and signed-ness
1546 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1547 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1549 // Support for inc/dec with optimal instruction selection depending on value
1551 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1552 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1554 void decrementl(Address dst, int value = 1);
1555 void decrementl(Register reg, int value = 1);
1557 void decrementq(Register reg, int value = 1);
1558 void decrementq(Address dst, int value = 1);
1560 void incrementl(Address dst, int value = 1);
1561 void incrementl(Register reg, int value = 1);
1563 void incrementq(Register reg, int value = 1);
1564 void incrementq(Address dst, int value = 1);
1567 // Support optimal SSE move instructions.
1568 void movflt(XMMRegister dst, XMMRegister src) {
1569 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1570 else { movss (dst, src); return; }
1571 }
1572 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1573 void movflt(XMMRegister dst, AddressLiteral src);
1574 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1576 void movdbl(XMMRegister dst, XMMRegister src) {
1577 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1578 else { movsd (dst, src); return; }
1579 }
1581 void movdbl(XMMRegister dst, AddressLiteral src);
1583 void movdbl(XMMRegister dst, Address src) {
1584 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1585 else { movlpd(dst, src); return; }
1586 }
1587 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1589 void incrementl(AddressLiteral dst);
1590 void incrementl(ArrayAddress dst);
1592 // Alignment
1593 void align(int modulus);
1595 // Misc
1596 void fat_nop(); // 5 byte nop
1598 // Stack frame creation/removal
1599 void enter();
1600 void leave();
1602 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1603 // The pointer will be loaded into the thread register.
1604 void get_thread(Register thread);
1607 // Support for VM calls
1608 //
1609 // It is imperative that all calls into the VM are handled via the call_VM macros.
1610 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1611 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1614 void call_VM(Register oop_result,
1615 address entry_point,
1616 bool check_exceptions = true);
1617 void call_VM(Register oop_result,
1618 address entry_point,
1619 Register arg_1,
1620 bool check_exceptions = true);
1621 void call_VM(Register oop_result,
1622 address entry_point,
1623 Register arg_1, Register arg_2,
1624 bool check_exceptions = true);
1625 void call_VM(Register oop_result,
1626 address entry_point,
1627 Register arg_1, Register arg_2, Register arg_3,
1628 bool check_exceptions = true);
1630 // Overloadings with last_Java_sp
1631 void call_VM(Register oop_result,
1632 Register last_java_sp,
1633 address entry_point,
1634 int number_of_arguments = 0,
1635 bool check_exceptions = true);
1636 void call_VM(Register oop_result,
1637 Register last_java_sp,
1638 address entry_point,
1639 Register arg_1, bool
1640 check_exceptions = true);
1641 void call_VM(Register oop_result,
1642 Register last_java_sp,
1643 address entry_point,
1644 Register arg_1, Register arg_2,
1645 bool check_exceptions = true);
1646 void call_VM(Register oop_result,
1647 Register last_java_sp,
1648 address entry_point,
1649 Register arg_1, Register arg_2, Register arg_3,
1650 bool check_exceptions = true);
1652 // These always tightly bind to MacroAssembler::call_VM_base
1653 // bypassing the virtual implementation
1654 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1655 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1656 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1657 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1658 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1660 void call_VM_leaf(address entry_point,
1661 int number_of_arguments = 0);
1662 void call_VM_leaf(address entry_point,
1663 Register arg_1);
1664 void call_VM_leaf(address entry_point,
1665 Register arg_1, Register arg_2);
1666 void call_VM_leaf(address entry_point,
1667 Register arg_1, Register arg_2, Register arg_3);
1669 // These always tightly bind to MacroAssembler::call_VM_leaf_base
1670 // bypassing the virtual implementation
1671 void super_call_VM_leaf(address entry_point);
1672 void super_call_VM_leaf(address entry_point, Register arg_1);
1673 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1674 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
1675 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
1677 // last Java Frame (fills frame anchor)
1678 void set_last_Java_frame(Register thread,
1679 Register last_java_sp,
1680 Register last_java_fp,
1681 address last_java_pc);
1683 // thread in the default location (r15_thread on 64bit)
1684 void set_last_Java_frame(Register last_java_sp,
1685 Register last_java_fp,
1686 address last_java_pc);
1688 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1690 // thread in the default location (r15_thread on 64bit)
1691 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1693 // Stores
1694 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1695 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1697 #ifndef SERIALGC
1699 void g1_write_barrier_pre(Register obj,
1700 Register pre_val,
1701 Register thread,
1702 Register tmp,
1703 bool tosca_live,
1704 bool expand_call);
1706 void g1_write_barrier_post(Register store_addr,
1707 Register new_val,
1708 Register thread,
1709 Register tmp,
1710 Register tmp2);
1712 #endif // SERIALGC
1714 // split store_check(Register obj) to enhance instruction interleaving
1715 void store_check_part_1(Register obj);
1716 void store_check_part_2(Register obj);
1718 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1719 void c2bool(Register x);
1721 // C++ bool manipulation
1723 void movbool(Register dst, Address src);
1724 void movbool(Address dst, bool boolconst);
1725 void movbool(Address dst, Register src);
1726 void testbool(Register dst);
1728 // oop manipulations
1729 void load_klass(Register dst, Register src);
1730 void store_klass(Register dst, Register src);
1732 void load_heap_oop(Register dst, Address src);
1733 void load_heap_oop_not_null(Register dst, Address src);
1734 void store_heap_oop(Address dst, Register src);
1736 // Used for storing NULL. All other oop constants should be
1737 // stored using routines that take a jobject.
1738 void store_heap_oop_null(Address dst);
1740 void load_prototype_header(Register dst, Register src);
1742 #ifdef _LP64
1743 void store_klass_gap(Register dst, Register src);
1745 // This dummy is to prevent a call to store_heap_oop from
1746 // converting a zero (like NULL) into a Register by giving
1747 // the compiler two choices it can't resolve
1749 void store_heap_oop(Address dst, void* dummy);
1751 void encode_heap_oop(Register r);
1752 void decode_heap_oop(Register r);
1753 void encode_heap_oop_not_null(Register r);
1754 void decode_heap_oop_not_null(Register r);
1755 void encode_heap_oop_not_null(Register dst, Register src);
1756 void decode_heap_oop_not_null(Register dst, Register src);
1758 void set_narrow_oop(Register dst, jobject obj);
1759 void set_narrow_oop(Address dst, jobject obj);
1760 void cmp_narrow_oop(Register dst, jobject obj);
1761 void cmp_narrow_oop(Address dst, jobject obj);
1763 // if heap base register is used - reinit it with the correct value
1764 void reinit_heapbase();
1766 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1768 #endif // _LP64
1770 // Int division/remainder for Java
1771 // (as idivl, but checks for special case as described in JVM spec.)
1772 // returns idivl instruction offset for implicit exception handling
1773 int corrected_idivl(Register reg);
1775 // Long division/remainder for Java
1776 // (as idivq, but checks for special case as described in JVM spec.)
1777 // returns idivq instruction offset for implicit exception handling
1778 int corrected_idivq(Register reg);
1780 void int3();
1782 // Long operation macros for a 32bit cpu
1783 // Long negation for Java
1784 void lneg(Register hi, Register lo);
1786 // Long multiplication for Java
1787 // (destroys contents of eax, ebx, ecx and edx)
1788 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1790 // Long shifts for Java
1791 // (semantics as described in JVM spec.)
1792 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1793 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1795 // Long compare for Java
1796 // (semantics as described in JVM spec.)
1797 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1800 // misc
1802 // Sign extension
1803 void sign_extend_short(Register reg);
1804 void sign_extend_byte(Register reg);
1806 // Division by power of 2, rounding towards 0
1807 void division_with_shift(Register reg, int shift_value);
1809 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1810 //
1811 // CF (corresponds to C0) if x < y
1812 // PF (corresponds to C2) if unordered
1813 // ZF (corresponds to C3) if x = y
1814 //
1815 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1816 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1817 void fcmp(Register tmp);
1818 // Variant of the above which allows y to be further down the stack
1819 // and which only pops x and y if specified. If pop_right is
1820 // specified then pop_left must also be specified.
1821 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1823 // Floating-point comparison for Java
1824 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1825 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1826 // (semantics as described in JVM spec.)
1827 void fcmp2int(Register dst, bool unordered_is_less);
1828 // Variant of the above which allows y to be further down the stack
1829 // and which only pops x and y if specified. If pop_right is
1830 // specified then pop_left must also be specified.
1831 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1833 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1834 // tmp is a temporary register, if none is available use noreg
1835 void fremr(Register tmp);
1838 // same as fcmp2int, but using SSE2
1839 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1840 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1842 // Inlined sin/cos generator for Java; must not use CPU instruction
1843 // directly on Intel as it does not have high enough precision
1844 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1845 // number of FPU stack slots in use; all but the topmost will
1846 // require saving if a slow case is necessary. Assumes argument is
1847 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1848 // this code.
1849 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1851 // branch to L if FPU flag C2 is set/not set
1852 // tmp is a temporary register, if none is available use noreg
1853 void jC2 (Register tmp, Label& L);
1854 void jnC2(Register tmp, Label& L);
1856 // Pop ST (ffree & fincstp combined)
1857 void fpop();
1859 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1860 void push_fTOS();
1862 // pops double TOS element from CPU stack and pushes on FPU stack
1863 void pop_fTOS();
1865 void empty_FPU_stack();
1867 void push_IU_state();
1868 void pop_IU_state();
1870 void push_FPU_state();
1871 void pop_FPU_state();
1873 void push_CPU_state();
1874 void pop_CPU_state();
1876 // Round up to a power of two
1877 void round_to(Register reg, int modulus);
1879 // Callee saved registers handling
1880 void push_callee_saved_registers();
1881 void pop_callee_saved_registers();
1883 // allocation
1884 void eden_allocate(
1885 Register obj, // result: pointer to object after successful allocation
1886 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1887 int con_size_in_bytes, // object size in bytes if known at compile time
1888 Register t1, // temp register
1889 Label& slow_case // continuation point if fast allocation fails
1890 );
1891 void tlab_allocate(
1892 Register obj, // result: pointer to object after successful allocation
1893 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1894 int con_size_in_bytes, // object size in bytes if known at compile time
1895 Register t1, // temp register
1896 Register t2, // temp register
1897 Label& slow_case // continuation point if fast allocation fails
1898 );
1899 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
1900 void incr_allocated_bytes(Register thread,
1901 Register var_size_in_bytes, int con_size_in_bytes,
1902 Register t1 = noreg);
1904 // interface method calling
1905 void lookup_interface_method(Register recv_klass,
1906 Register intf_klass,
1907 RegisterOrConstant itable_index,
1908 Register method_result,
1909 Register scan_temp,
1910 Label& no_such_interface);
1912 // Test sub_klass against super_klass, with fast and slow paths.
1914 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1915 // One of the three labels can be NULL, meaning take the fall-through.
1916 // If super_check_offset is -1, the value is loaded up from super_klass.
1917 // No registers are killed, except temp_reg.
1918 void check_klass_subtype_fast_path(Register sub_klass,
1919 Register super_klass,
1920 Register temp_reg,
1921 Label* L_success,
1922 Label* L_failure,
1923 Label* L_slow_path,
1924 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1926 // The rest of the type check; must be wired to a corresponding fast path.
1927 // It does not repeat the fast path logic, so don't use it standalone.
1928 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1929 // Updates the sub's secondary super cache as necessary.
1930 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1931 void check_klass_subtype_slow_path(Register sub_klass,
1932 Register super_klass,
1933 Register temp_reg,
1934 Register temp2_reg,
1935 Label* L_success,
1936 Label* L_failure,
1937 bool set_cond_codes = false);
1939 // Simplified, combined version, good for typical uses.
1940 // Falls through on failure.
1941 void check_klass_subtype(Register sub_klass,
1942 Register super_klass,
1943 Register temp_reg,
1944 Label& L_success);
1946 // method handles (JSR 292)
1947 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1948 Register temp_reg,
1949 Label& wrong_method_type);
1950 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1951 Register temp_reg);
1952 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1953 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1956 //----
1957 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1959 // Debugging
1961 // only if +VerifyOops
1962 void verify_oop(Register reg, const char* s = "broken oop");
1963 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1965 // only if +VerifyFPU
1966 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1968 // prints msg, dumps registers and stops execution
1969 void stop(const char* msg);
1971 // prints msg and continues
1972 void warn(const char* msg);
1974 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1975 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1977 void os_breakpoint();
1979 void untested() { stop("untested"); }
1981 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
1983 void should_not_reach_here() { stop("should not reach here"); }
1985 void print_CPU_state();
1987 // Stack overflow checking
1988 void bang_stack_with_offset(int offset) {
1989 // stack grows down, caller passes positive offset
1990 assert(offset > 0, "must bang with negative offset");
1991 movl(Address(rsp, (-offset)), rax);
1992 }
1994 // Writes to stack successive pages until offset reached to check for
1995 // stack overflow + shadow pages. Also, clobbers tmp
1996 void bang_stack_size(Register size, Register tmp);
1998 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1999 Register tmp,
2000 int offset);
2002 // Support for serializing memory accesses between threads
2003 void serialize_memory(Register thread, Register tmp);
2005 void verify_tlab();
2007 // Biased locking support
2008 // lock_reg and obj_reg must be loaded up with the appropriate values.
2009 // swap_reg must be rax, and is killed.
2010 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2011 // be killed; if not supplied, push/pop will be used internally to
2012 // allocate a temporary (inefficient, avoid if possible).
2013 // Optional slow case is for implementations (interpreter and C1) which branch to
2014 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2015 // Returns offset of first potentially-faulting instruction for null
2016 // check info (currently consumed only by C1). If
2017 // swap_reg_contains_mark is true then returns -1 as it is assumed
2018 // the calling code has already passed any potential faults.
2019 int biased_locking_enter(Register lock_reg, Register obj_reg,
2020 Register swap_reg, Register tmp_reg,
2021 bool swap_reg_contains_mark,
2022 Label& done, Label* slow_case = NULL,
2023 BiasedLockingCounters* counters = NULL);
2024 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2027 Condition negate_condition(Condition cond);
2029 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2030 // operands. In general the names are modified to avoid hiding the instruction in Assembler
2031 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2032 // here in MacroAssembler. The major exception to this rule is call
2034 // Arithmetics
2037 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2038 void addptr(Address dst, Register src);
2040 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2041 void addptr(Register dst, int32_t src);
2042 void addptr(Register dst, Register src);
2043 void addptr(Register dst, RegisterOrConstant src) {
2044 if (src.is_constant()) addptr(dst, (int) src.as_constant());
2045 else addptr(dst, src.as_register());
2046 }
2048 void andptr(Register dst, int32_t src);
2049 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2051 void cmp8(AddressLiteral src1, int imm);
2053 // renamed to drag out the casting of address to int32_t/intptr_t
2054 void cmp32(Register src1, int32_t imm);
2056 void cmp32(AddressLiteral src1, int32_t imm);
2057 // compare reg - mem, or reg - &mem
2058 void cmp32(Register src1, AddressLiteral src2);
2060 void cmp32(Register src1, Address src2);
2062 #ifndef _LP64
2063 void cmpoop(Address dst, jobject obj);
2064 void cmpoop(Register dst, jobject obj);
2065 #endif // _LP64
2067 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2068 void cmpptr(Address src1, AddressLiteral src2);
2070 void cmpptr(Register src1, AddressLiteral src2);
2072 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2073 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2074 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2076 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2077 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2079 // cmp64 to avoild hiding cmpq
2080 void cmp64(Register src1, AddressLiteral src);
2082 void cmpxchgptr(Register reg, Address adr);
2084 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2087 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2090 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2092 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2094 void shlptr(Register dst, int32_t shift);
2095 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2097 void shrptr(Register dst, int32_t shift);
2098 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2100 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2101 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2103 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2105 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2106 void subptr(Register dst, int32_t src);
2107 void subptr(Register dst, Register src);
2108 void subptr(Register dst, RegisterOrConstant src) {
2109 if (src.is_constant()) subptr(dst, (int) src.as_constant());
2110 else subptr(dst, src.as_register());
2111 }
2113 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2114 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2116 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2117 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2119 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2123 // Helper functions for statistics gathering.
2124 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2125 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2126 // Unconditional atomic increment.
2127 void atomic_incl(AddressLiteral counter_addr);
2129 void lea(Register dst, AddressLiteral adr);
2130 void lea(Address dst, AddressLiteral adr);
2131 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2133 void leal32(Register dst, Address src) { leal(dst, src); }
2135 // Import other testl() methods from the parent class or else
2136 // they will be hidden by the following overriding declaration.
2137 using Assembler::testl;
2138 void testl(Register dst, AddressLiteral src);
2140 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2141 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2142 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2144 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2145 void testptr(Register src1, Register src2);
2147 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2148 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2150 // Calls
2152 void call(Label& L, relocInfo::relocType rtype);
2153 void call(Register entry);
2155 // NOTE: this call tranfers to the effective address of entry NOT
2156 // the address contained by entry. This is because this is more natural
2157 // for jumps/calls.
2158 void call(AddressLiteral entry);
2160 // Jumps
2162 // NOTE: these jumps tranfer to the effective address of dst NOT
2163 // the address contained by dst. This is because this is more natural
2164 // for jumps/calls.
2165 void jump(AddressLiteral dst);
2166 void jump_cc(Condition cc, AddressLiteral dst);
2168 // 32bit can do a case table jump in one instruction but we no longer allow the base
2169 // to be installed in the Address class. This jump will tranfers to the address
2170 // contained in the location described by entry (not the address of entry)
2171 void jump(ArrayAddress entry);
2173 // Floating
2175 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2176 void andpd(XMMRegister dst, AddressLiteral src);
2178 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2179 void comiss(XMMRegister dst, AddressLiteral src);
2181 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2182 void comisd(XMMRegister dst, AddressLiteral src);
2184 void fadd_s(Address src) { Assembler::fadd_s(src); }
2185 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2187 void fldcw(Address src) { Assembler::fldcw(src); }
2188 void fldcw(AddressLiteral src);
2190 void fld_s(int index) { Assembler::fld_s(index); }
2191 void fld_s(Address src) { Assembler::fld_s(src); }
2192 void fld_s(AddressLiteral src);
2194 void fld_d(Address src) { Assembler::fld_d(src); }
2195 void fld_d(AddressLiteral src);
2197 void fld_x(Address src) { Assembler::fld_x(src); }
2198 void fld_x(AddressLiteral src);
2200 void fmul_s(Address src) { Assembler::fmul_s(src); }
2201 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2203 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2204 void ldmxcsr(AddressLiteral src);
2206 private:
2207 // these are private because users should be doing movflt/movdbl
2209 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2210 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2211 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2212 void movss(XMMRegister dst, AddressLiteral src);
2214 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2215 void movlpd(XMMRegister dst, AddressLiteral src);
2217 public:
2219 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2220 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2221 void addsd(XMMRegister dst, AddressLiteral src) { Assembler::addsd(dst, as_Address(src)); }
2223 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2224 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2225 void addss(XMMRegister dst, AddressLiteral src) { Assembler::addss(dst, as_Address(src)); }
2227 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2228 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2229 void divsd(XMMRegister dst, AddressLiteral src) { Assembler::divsd(dst, as_Address(src)); }
2231 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2232 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2233 void divss(XMMRegister dst, AddressLiteral src) { Assembler::divss(dst, as_Address(src)); }
2235 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2236 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2237 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2238 void movsd(XMMRegister dst, AddressLiteral src) { Assembler::movsd(dst, as_Address(src)); }
2240 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2241 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2242 void mulsd(XMMRegister dst, AddressLiteral src) { Assembler::mulsd(dst, as_Address(src)); }
2244 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2245 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2246 void mulss(XMMRegister dst, AddressLiteral src) { Assembler::mulss(dst, as_Address(src)); }
2248 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2249 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2250 void sqrtsd(XMMRegister dst, AddressLiteral src) { Assembler::sqrtsd(dst, as_Address(src)); }
2252 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2253 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2254 void sqrtss(XMMRegister dst, AddressLiteral src) { Assembler::sqrtss(dst, as_Address(src)); }
2256 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2257 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2258 void subsd(XMMRegister dst, AddressLiteral src) { Assembler::subsd(dst, as_Address(src)); }
2260 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2261 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2262 void subss(XMMRegister dst, AddressLiteral src) { Assembler::subss(dst, as_Address(src)); }
2264 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2265 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2266 void ucomiss(XMMRegister dst, AddressLiteral src);
2268 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2269 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2270 void ucomisd(XMMRegister dst, AddressLiteral src);
2272 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2273 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2274 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2275 void xorpd(XMMRegister dst, AddressLiteral src);
2277 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2278 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2279 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2280 void xorps(XMMRegister dst, AddressLiteral src);
2282 // Data
2284 void cmov32( Condition cc, Register dst, Address src);
2285 void cmov32( Condition cc, Register dst, Register src);
2287 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2289 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2290 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2292 void movoop(Register dst, jobject obj);
2293 void movoop(Address dst, jobject obj);
2295 void movptr(ArrayAddress dst, Register src);
2296 // can this do an lea?
2297 void movptr(Register dst, ArrayAddress src);
2299 void movptr(Register dst, Address src);
2301 void movptr(Register dst, AddressLiteral src);
2303 void movptr(Register dst, intptr_t src);
2304 void movptr(Register dst, Register src);
2305 void movptr(Address dst, intptr_t src);
2307 void movptr(Address dst, Register src);
2309 void movptr(Register dst, RegisterOrConstant src) {
2310 if (src.is_constant()) movptr(dst, src.as_constant());
2311 else movptr(dst, src.as_register());
2312 }
2314 #ifdef _LP64
2315 // Generally the next two are only used for moving NULL
2316 // Although there are situations in initializing the mark word where
2317 // they could be used. They are dangerous.
2319 // They only exist on LP64 so that int32_t and intptr_t are not the same
2320 // and we have ambiguous declarations.
2322 void movptr(Address dst, int32_t imm32);
2323 void movptr(Register dst, int32_t imm32);
2324 #endif // _LP64
2326 // to avoid hiding movl
2327 void mov32(AddressLiteral dst, Register src);
2328 void mov32(Register dst, AddressLiteral src);
2330 // to avoid hiding movb
2331 void movbyte(ArrayAddress dst, int src);
2333 // Can push value or effective address
2334 void pushptr(AddressLiteral src);
2336 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2337 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2339 void pushoop(jobject obj);
2341 // sign extend as need a l to ptr sized element
2342 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2343 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2345 // IndexOf strings.
2346 // Small strings are loaded through stack if they cross page boundary.
2347 void string_indexof(Register str1, Register str2,
2348 Register cnt1, Register cnt2,
2349 int int_cnt2, Register result,
2350 XMMRegister vec, Register tmp);
2352 // IndexOf for constant substrings with size >= 8 elements
2353 // which don't need to be loaded through stack.
2354 void string_indexofC8(Register str1, Register str2,
2355 Register cnt1, Register cnt2,
2356 int int_cnt2, Register result,
2357 XMMRegister vec, Register tmp);
2359 // Smallest code: we don't need to load through stack,
2360 // check string tail.
2362 // Compare strings.
2363 void string_compare(Register str1, Register str2,
2364 Register cnt1, Register cnt2, Register result,
2365 XMMRegister vec1);
2367 // Compare char[] arrays.
2368 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2369 Register limit, Register result, Register chr,
2370 XMMRegister vec1, XMMRegister vec2);
2372 // Fill primitive arrays
2373 void generate_fill(BasicType t, bool aligned,
2374 Register to, Register value, Register count,
2375 Register rtmp, XMMRegister xtmp);
2377 #undef VIRTUAL
2379 };
2381 /**
2382 * class SkipIfEqual:
2383 *
2384 * Instantiating this class will result in assembly code being output that will
2385 * jump around any code emitted between the creation of the instance and it's
2386 * automatic destruction at the end of a scope block, depending on the value of
2387 * the flag passed to the constructor, which will be checked at run-time.
2388 */
2389 class SkipIfEqual {
2390 private:
2391 MacroAssembler* _masm;
2392 Label _label;
2394 public:
2395 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2396 ~SkipIfEqual();
2397 };
2399 #ifdef ASSERT
2400 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2401 #endif
2403 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP