Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/x86/vm/vm_version_x86_32.cpp@dc7f315e41f7
src/cpu/x86/vm/vm_version_x86_32.cpp
Wed, 27 Aug 2008 00:21:55 -0700
- author
- never
- date
- Wed, 27 Aug 2008 00:21:55 -0700
- changeset 739
- dc7f315e41f7
- parent 670
- 9c2ecc2ffb12
- child 840
- 2649e5276dd7
- permissions
- -rw-r--r--
5108146: Merge i486 and amd64 cpu directories
6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up
Reviewed-by: kvn
1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 # include "incls/_precompiled.incl"
26 # include "incls/_vm_version_x86_32.cpp.incl"
29 int VM_Version::_cpu;
30 int VM_Version::_model;
31 int VM_Version::_stepping;
32 int VM_Version::_cpuFeatures;
33 const char* VM_Version::_features_str = "";
34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
36 static BufferBlob* stub_blob;
37 static const int stub_size = 300;
39 extern "C" {
40 typedef void (*getPsrInfo_stub_t)(void*);
41 }
42 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
45 class VM_Version_StubGenerator: public StubCodeGenerator {
46 public:
48 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
50 address generate_getPsrInfo() {
51 // Flags to test CPU type.
52 const uint32_t EFL_AC = 0x40000;
53 const uint32_t EFL_ID = 0x200000;
54 // Values for when we don't have a CPUID instruction.
55 const int CPU_FAMILY_SHIFT = 8;
56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
59 Label detect_486, cpu486, detect_586, std_cpuid1;
60 Label ext_cpuid1, ext_cpuid5, done;
62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
63 # define __ _masm->
65 address start = __ pc();
67 //
68 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
69 //
70 __ push(rbp);
71 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
72 __ push(rbx);
73 __ push(rsi);
74 __ pushf(); // preserve rbx, and flags
75 __ pop(rax);
76 __ push(rax);
77 __ mov(rcx, rax);
78 //
79 // if we are unable to change the AC flag, we have a 386
80 //
81 __ xorl(rax, EFL_AC);
82 __ push(rax);
83 __ popf();
84 __ pushf();
85 __ pop(rax);
86 __ cmpptr(rax, rcx);
87 __ jccb(Assembler::notEqual, detect_486);
89 __ movl(rax, CPU_FAMILY_386);
90 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
91 __ jmp(done);
93 //
94 // If we are unable to change the ID flag, we have a 486 which does
95 // not support the "cpuid" instruction.
96 //
97 __ bind(detect_486);
98 __ mov(rax, rcx);
99 __ xorl(rax, EFL_ID);
100 __ push(rax);
101 __ popf();
102 __ pushf();
103 __ pop(rax);
104 __ cmpptr(rcx, rax);
105 __ jccb(Assembler::notEqual, detect_586);
107 __ bind(cpu486);
108 __ movl(rax, CPU_FAMILY_486);
109 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
110 __ jmp(done);
112 //
113 // at this point, we have a chip which supports the "cpuid" instruction
114 //
115 __ bind(detect_586);
116 __ xorptr(rax, rax);
117 __ cpuid();
118 __ orptr(rax, rax);
119 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
120 // value of at least 1, we give up and
121 // assume a 486
122 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
123 __ movl(Address(rsi, 0), rax);
124 __ movl(Address(rsi, 4), rbx);
125 __ movl(Address(rsi, 8), rcx);
126 __ movl(Address(rsi,12), rdx);
128 __ cmpl(rax, 3); // Is cpuid(0x4) supported?
129 __ jccb(Assembler::belowEqual, std_cpuid1);
131 //
132 // cpuid(0x4) Deterministic cache params
133 //
134 __ movl(rax, 4); // and rcx already set to 0x0
135 __ xorl(rcx, rcx);
136 __ cpuid();
137 __ push(rax);
138 __ andl(rax, 0x1f); // Determine if valid cache parameters used
139 __ orl(rax, rax); // rax,[4:0] == 0 indicates invalid cache
140 __ pop(rax);
141 __ jccb(Assembler::equal, std_cpuid1);
143 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
144 __ movl(Address(rsi, 0), rax);
145 __ movl(Address(rsi, 4), rbx);
146 __ movl(Address(rsi, 8), rcx);
147 __ movl(Address(rsi,12), rdx);
149 //
150 // Standard cpuid(0x1)
151 //
152 __ bind(std_cpuid1);
153 __ movl(rax, 1);
154 __ cpuid();
155 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
156 __ movl(Address(rsi, 0), rax);
157 __ movl(Address(rsi, 4), rbx);
158 __ movl(Address(rsi, 8), rcx);
159 __ movl(Address(rsi,12), rdx);
161 __ movl(rax, 0x80000000);
162 __ cpuid();
163 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
164 __ jcc(Assembler::belowEqual, done);
165 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
166 __ jccb(Assembler::belowEqual, ext_cpuid1);
167 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
168 __ jccb(Assembler::belowEqual, ext_cpuid5);
169 //
170 // Extended cpuid(0x80000008)
171 //
172 __ movl(rax, 0x80000008);
173 __ cpuid();
174 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
175 __ movl(Address(rsi, 0), rax);
176 __ movl(Address(rsi, 4), rbx);
177 __ movl(Address(rsi, 8), rcx);
178 __ movl(Address(rsi,12), rdx);
180 //
181 // Extended cpuid(0x80000005)
182 //
183 __ bind(ext_cpuid5);
184 __ movl(rax, 0x80000005);
185 __ cpuid();
186 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
187 __ movl(Address(rsi, 0), rax);
188 __ movl(Address(rsi, 4), rbx);
189 __ movl(Address(rsi, 8), rcx);
190 __ movl(Address(rsi,12), rdx);
192 //
193 // Extended cpuid(0x80000001)
194 //
195 __ bind(ext_cpuid1);
196 __ movl(rax, 0x80000001);
197 __ cpuid();
198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
199 __ movl(Address(rsi, 0), rax);
200 __ movl(Address(rsi, 4), rbx);
201 __ movl(Address(rsi, 8), rcx);
202 __ movl(Address(rsi,12), rdx);
204 //
205 // return
206 //
207 __ bind(done);
208 __ popf();
209 __ pop(rsi);
210 __ pop(rbx);
211 __ pop(rbp);
212 __ ret(0);
214 # undef __
216 return start;
217 };
218 };
221 void VM_Version::get_processor_features() {
223 _cpu = 4; // 486 by default
224 _model = 0;
225 _stepping = 0;
226 _cpuFeatures = 0;
227 _logical_processors_per_package = 1;
228 if (!Use486InstrsOnly) {
229 // Get raw processor info
230 getPsrInfo_stub(&_cpuid_info);
231 assert_is_initialized();
232 _cpu = extended_cpu_family();
233 _model = extended_cpu_model();
234 _stepping = cpu_stepping();
235 if (cpu_family() > 4) { // it supports CPUID
236 _cpuFeatures = feature_flags();
237 // Logical processors are only available on P4s and above,
238 // and only if hyperthreading is available.
239 _logical_processors_per_package = logical_processor_count();
240 }
241 }
242 _supports_cx8 = supports_cmpxchg8();
243 // if the OS doesn't support SSE, we can't use this feature even if the HW does
244 if( !os::supports_sse())
245 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4|CPU_SSE4A);
246 if (UseSSE < 4)
247 _cpuFeatures &= ~CPU_SSE4;
248 if (UseSSE < 3) {
249 _cpuFeatures &= ~CPU_SSE3;
250 _cpuFeatures &= ~CPU_SSSE3;
251 _cpuFeatures &= ~CPU_SSE4A;
252 }
253 if (UseSSE < 2)
254 _cpuFeatures &= ~CPU_SSE2;
255 if (UseSSE < 1)
256 _cpuFeatures &= ~CPU_SSE;
258 if (logical_processors_per_package() == 1) {
259 // HT processor could be installed on a system which doesn't support HT.
260 _cpuFeatures &= ~CPU_HT;
261 }
263 char buf[256];
264 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
265 cores_per_cpu(), threads_per_core(),
266 cpu_family(), _model, _stepping,
267 (supports_cmov() ? ", cmov" : ""),
268 (supports_cmpxchg8() ? ", cx8" : ""),
269 (supports_fxsr() ? ", fxsr" : ""),
270 (supports_mmx() ? ", mmx" : ""),
271 (supports_sse() ? ", sse" : ""),
272 (supports_sse2() ? ", sse2" : ""),
273 (supports_sse3() ? ", sse3" : ""),
274 (supports_ssse3()? ", ssse3": ""),
275 (supports_sse4() ? ", sse4" : ""),
276 (supports_mmx_ext() ? ", mmxext" : ""),
277 (supports_3dnow() ? ", 3dnow" : ""),
278 (supports_3dnow2() ? ", 3dnowext" : ""),
279 (supports_sse4a() ? ", sse4a": ""),
280 (supports_ht() ? ", ht": ""));
281 _features_str = strdup(buf);
283 // UseSSE is set to the smaller of what hardware supports and what
284 // the command line requires. I.e., you cannot set UseSSE to 2 on
285 // older Pentiums which do not support it.
286 if( UseSSE > 4 ) UseSSE=4;
287 if( UseSSE < 0 ) UseSSE=0;
288 if( !supports_sse4() ) // Drop to 3 if no SSE4 support
289 UseSSE = MIN2((intx)3,UseSSE);
290 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
291 UseSSE = MIN2((intx)2,UseSSE);
292 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
293 UseSSE = MIN2((intx)1,UseSSE);
294 if( !supports_sse () ) // Drop to 0 if no SSE support
295 UseSSE = 0;
297 // On new cpus instructions which update whole XMM register should be used
298 // to prevent partial register stall due to dependencies on high half.
299 //
300 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
301 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
302 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
303 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
305 if( is_amd() ) { // AMD cpus specific settings
306 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
307 // Use it on new AMD cpus starting from Opteron.
308 UseAddressNop = true;
309 }
310 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
311 // Use it on new AMD cpus starting from Opteron.
312 UseNewLongLShift = true;
313 }
314 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
315 if( supports_sse4a() ) {
316 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
317 } else {
318 UseXmmLoadAndClearUpper = false;
319 }
320 }
321 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
322 if( supports_sse4a() ) {
323 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
324 } else {
325 UseXmmRegToRegMoveAll = false;
326 }
327 }
328 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
329 if( supports_sse4a() ) {
330 UseXmmI2F = true;
331 } else {
332 UseXmmI2F = false;
333 }
334 }
335 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
336 if( supports_sse4a() ) {
337 UseXmmI2D = true;
338 } else {
339 UseXmmI2D = false;
340 }
341 }
342 }
344 if( is_intel() ) { // Intel cpus specific settings
345 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
346 UseStoreImmI16 = false; // don't use it on Intel cpus
347 }
348 if( cpu_family() == 6 || cpu_family() == 15 ) {
349 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
350 // Use it on all Intel cpus starting from PentiumPro
351 UseAddressNop = true;
352 }
353 }
354 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
355 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
356 }
357 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
358 if( supports_sse3() ) {
359 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
360 } else {
361 UseXmmRegToRegMoveAll = false;
362 }
363 }
364 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
365 #ifdef COMPILER2
366 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
367 // For new Intel cpus do the next optimization:
368 // don't align the beginning of a loop if there are enough instructions
369 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
370 // in current fetch line (OptoLoopAlignment) or the padding
371 // is big (> MaxLoopPad).
372 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
373 // generated NOP instructions. 11 is the largest size of one
374 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
375 MaxLoopPad = 11;
376 }
377 #endif // COMPILER2
378 }
379 }
381 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
382 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
384 // set valid Prefetch instruction
385 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
386 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
387 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
388 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
390 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
391 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
392 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
393 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
395 // Allocation prefetch settings
396 intx cache_line_size = L1_data_cache_line_size();
397 if( cache_line_size > AllocatePrefetchStepSize )
398 AllocatePrefetchStepSize = cache_line_size;
399 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
400 AllocatePrefetchLines = 3; // Optimistic value
401 assert(AllocatePrefetchLines > 0, "invalid value");
402 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
403 AllocatePrefetchLines = 1; // Conservative value
405 AllocatePrefetchDistance = allocate_prefetch_distance();
406 AllocatePrefetchStyle = allocate_prefetch_style();
408 if( AllocatePrefetchStyle == 2 && is_intel() &&
409 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
410 AllocatePrefetchDistance = 320;
411 }
412 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
414 #ifndef PRODUCT
415 if (PrintMiscellaneous && Verbose) {
416 tty->print_cr("Logical CPUs per package: %u",
417 logical_processors_per_package());
418 tty->print_cr("UseSSE=%d",UseSSE);
419 tty->print("Allocation: ");
420 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
421 tty->print_cr("no prefetching");
422 } else {
423 if (UseSSE == 0 && supports_3dnow()) {
424 tty->print("PREFETCHW");
425 } else if (UseSSE >= 1) {
426 if (AllocatePrefetchInstr == 0) {
427 tty->print("PREFETCHNTA");
428 } else if (AllocatePrefetchInstr == 1) {
429 tty->print("PREFETCHT0");
430 } else if (AllocatePrefetchInstr == 2) {
431 tty->print("PREFETCHT2");
432 } else if (AllocatePrefetchInstr == 3) {
433 tty->print("PREFETCHW");
434 }
435 }
436 if (AllocatePrefetchLines > 1) {
437 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
438 } else {
439 tty->print_cr(" %d, one line", AllocatePrefetchDistance);
440 }
441 }
442 }
443 #endif // !PRODUCT
444 }
446 void VM_Version::initialize() {
447 ResourceMark rm;
448 // Making this stub must be FIRST use of assembler
450 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
451 if (stub_blob == NULL) {
452 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
453 }
454 CodeBuffer c(stub_blob->instructions_begin(),
455 stub_blob->instructions_size());
456 VM_Version_StubGenerator g(&c);
457 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
458 g.generate_getPsrInfo());
460 get_processor_features();
461 }
