Sat, 29 Sep 2012 06:40:00 -0400
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
Summary: Capitalize these metadata types (and objArrayKlass)
Reviewed-by: stefank, twisti, kvn
1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
186 %}
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
201 #define __ _masm.
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
230 // Offset hacking within calls.
231 static int pre_call_FPU_size() {
232 if (Compile::current()->in_24_bit_fp_mode())
233 return 6; // fldcw
234 return 0;
235 }
237 static int preserve_SP_size() {
238 return 2; // op, rm(reg/reg)
239 }
241 // !!!!! Special hack to get all type of calls to specify the byte offset
242 // from the start of the call to the point where the return address
243 // will point.
244 int MachCallStaticJavaNode::ret_addr_offset() {
245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
246 if (_method_handle_invoke)
247 offset += preserve_SP_size();
248 return offset;
249 }
251 int MachCallDynamicJavaNode::ret_addr_offset() {
252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
253 }
255 static int sizeof_FFree_Float_Stack_All = -1;
257 int MachCallRuntimeNode::ret_addr_offset() {
258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
260 }
262 // Indicate if the safepoint node needs the polling page as an input.
263 // Since x86 does have absolute addressing, it doesn't.
264 bool SafePointNode::needs_polling_address_input() {
265 return false;
266 }
268 //
269 // Compute padding required for nodes which need alignment
270 //
272 // The address of the call instruction needs to be 4-byte aligned to
273 // ensure that it does not span a cache line so that it can be patched.
274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
275 current_offset += pre_call_FPU_size(); // skip fldcw, if any
276 current_offset += 1; // skip call opcode byte
277 return round_to(current_offset, alignment_required()) - current_offset;
278 }
280 // The address of the call instruction needs to be 4-byte aligned to
281 // ensure that it does not span a cache line so that it can be patched.
282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
283 current_offset += pre_call_FPU_size(); // skip fldcw, if any
284 current_offset += preserve_SP_size(); // skip mov rbp, rsp
285 current_offset += 1; // skip call opcode byte
286 return round_to(current_offset, alignment_required()) - current_offset;
287 }
289 // The address of the call instruction needs to be 4-byte aligned to
290 // ensure that it does not span a cache line so that it can be patched.
291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
292 current_offset += pre_call_FPU_size(); // skip fldcw, if any
293 current_offset += 5; // skip MOV instruction
294 current_offset += 1; // skip call opcode byte
295 return round_to(current_offset, alignment_required()) - current_offset;
296 }
298 // EMIT_RM()
299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
301 cbuf.insts()->emit_int8(c);
302 }
304 // EMIT_CC()
305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
306 unsigned char c = (unsigned char)( f1 | f2 );
307 cbuf.insts()->emit_int8(c);
308 }
310 // EMIT_OPCODE()
311 void emit_opcode(CodeBuffer &cbuf, int code) {
312 cbuf.insts()->emit_int8((unsigned char) code);
313 }
315 // EMIT_OPCODE() w/ relocation information
316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
317 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
318 emit_opcode(cbuf, code);
319 }
321 // EMIT_D8()
322 void emit_d8(CodeBuffer &cbuf, int d8) {
323 cbuf.insts()->emit_int8((unsigned char) d8);
324 }
326 // EMIT_D16()
327 void emit_d16(CodeBuffer &cbuf, int d16) {
328 cbuf.insts()->emit_int16(d16);
329 }
331 // EMIT_D32()
332 void emit_d32(CodeBuffer &cbuf, int d32) {
333 cbuf.insts()->emit_int32(d32);
334 }
336 // emit 32 bit value and construct relocation entry from relocInfo::relocType
337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
338 int format) {
339 cbuf.relocate(cbuf.insts_mark(), reloc, format);
340 cbuf.insts()->emit_int32(d32);
341 }
343 // emit 32 bit value and construct relocation entry from RelocationHolder
344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
345 int format) {
346 #ifdef ASSERT
347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
349 }
350 #endif
351 cbuf.relocate(cbuf.insts_mark(), rspec, format);
352 cbuf.insts()->emit_int32(d32);
353 }
355 // Access stack slot for load or store
356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
358 if( -128 <= disp && disp <= 127 ) {
359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
361 emit_d8 (cbuf, disp); // Displacement // R/M byte
362 } else {
363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 }
367 }
369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 }
378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127)
380 && (disp_reloc == relocInfo::none) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace);
383 }
384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here)
388 if ( disp_reloc != relocInfo::none ) {
389 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
390 } else {
391 emit_d32 (cbuf, displace);
392 }
393 }
394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( disp_reloc != relocInfo::none ) {
397 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
398 } else {
399 emit_d32 (cbuf, displace);
400 }
401 }
402 }
403 }
404 }
405 else { // Else, encode with the SIB byte
406 // If no displacement, mode is 0x0; unless base is [EBP]
407 if (displace == 0 && (base != EBP_enc)) { // If no displacement
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base);
410 }
411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127)
413 && (disp_reloc == relocInfo::none) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == 0x04 ) {
420 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, 0x04);
422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base);
425 }
426 if ( disp_reloc != relocInfo::none ) {
427 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
428 } else {
429 emit_d32 (cbuf, displace);
430 }
431 }
432 }
433 }
434 }
437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
438 if( dst_encoding == src_encoding ) {
439 // reg-reg copy, use an empty encoding
440 } else {
441 emit_opcode( cbuf, 0x8B );
442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
443 }
444 }
446 void emit_cmpfp_fixup(MacroAssembler& _masm) {
447 Label exit;
448 __ jccb(Assembler::noParity, exit);
449 __ pushf();
450 //
451 // comiss/ucomiss instructions set ZF,PF,CF flags and
452 // zero OF,AF,SF for NaN values.
453 // Fixup flags by zeroing ZF,PF so that compare of NaN
454 // values returns 'less than' result (CF is set).
455 // Leave the rest of flags unchanged.
456 //
457 // 7 6 5 4 3 2 1 0
458 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
459 // 0 0 1 0 1 0 1 1 (0x2B)
460 //
461 __ andl(Address(rsp, 0), 0xffffff2b);
462 __ popf();
463 __ bind(exit);
464 }
466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
467 Label done;
468 __ movl(dst, -1);
469 __ jcc(Assembler::parity, done);
470 __ jcc(Assembler::below, done);
471 __ setb(Assembler::notEqual, dst);
472 __ movzbl(dst, dst);
473 __ bind(done);
474 }
477 //=============================================================================
478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
480 int Compile::ConstantTable::calculate_table_base_offset() const {
481 return 0; // absolute addressing, no offset
482 }
484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
485 // Empty encoding
486 }
488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
489 return 0;
490 }
492 #ifndef PRODUCT
493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
494 st->print("# MachConstantBaseNode (empty encoding)");
495 }
496 #endif
499 //=============================================================================
500 #ifndef PRODUCT
501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
502 Compile* C = ra_->C;
504 int framesize = C->frame_slots() << LogBytesPerInt;
505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
506 // Remove wordSize for return addr which is already pushed.
507 framesize -= wordSize;
509 if (C->need_stack_bang(framesize)) {
510 framesize -= wordSize;
511 st->print("# stack bang");
512 st->print("\n\t");
513 st->print("PUSH EBP\t# Save EBP");
514 if (framesize) {
515 st->print("\n\t");
516 st->print("SUB ESP, #%d\t# Create frame",framesize);
517 }
518 } else {
519 st->print("SUB ESP, #%d\t# Create frame",framesize);
520 st->print("\n\t");
521 framesize -= wordSize;
522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
523 }
525 if (VerifyStackAtCalls) {
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
529 }
531 if( C->in_24_bit_fp_mode() ) {
532 st->print("\n\t");
533 st->print("FLDCW \t# load 24 bit fpu control word");
534 }
535 if (UseSSE >= 2 && VerifyFPU) {
536 st->print("\n\t");
537 st->print("# verify FPU stack (must be clean on entry)");
538 }
540 #ifdef ASSERT
541 if (VerifyStackAtCalls) {
542 st->print("\n\t");
543 st->print("# stack alignment check");
544 }
545 #endif
546 st->cr();
547 }
548 #endif
551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
552 Compile* C = ra_->C;
553 MacroAssembler _masm(&cbuf);
555 int framesize = C->frame_slots() << LogBytesPerInt;
557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
559 C->set_frame_complete(cbuf.insts_size());
561 if (C->has_mach_constant_base_node()) {
562 // NOTE: We set the table base offset here because users might be
563 // emitted before MachConstantBaseNode.
564 Compile::ConstantTable& constant_table = C->constant_table();
565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
566 }
567 }
569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
570 return MachNode::size(ra_); // too many variables; just compute it the hard way
571 }
573 int MachPrologNode::reloc() const {
574 return 0; // a large enough number
575 }
577 //=============================================================================
578 #ifndef PRODUCT
579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
580 Compile *C = ra_->C;
581 int framesize = C->frame_slots() << LogBytesPerInt;
582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
583 // Remove two words for return addr and rbp,
584 framesize -= 2*wordSize;
586 if( C->in_24_bit_fp_mode() ) {
587 st->print("FLDCW standard control word");
588 st->cr(); st->print("\t");
589 }
590 if( framesize ) {
591 st->print("ADD ESP,%d\t# Destroy frame",framesize);
592 st->cr(); st->print("\t");
593 }
594 st->print_cr("POPL EBP"); st->print("\t");
595 if( do_polling() && C->is_method_compilation() ) {
596 st->print("TEST PollPage,EAX\t! Poll Safepoint");
597 st->cr(); st->print("\t");
598 }
599 }
600 #endif
602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 Compile *C = ra_->C;
605 // If method set FPU control word, restore to standard control word
606 if( C->in_24_bit_fp_mode() ) {
607 MacroAssembler masm(&cbuf);
608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
609 }
611 int framesize = C->frame_slots() << LogBytesPerInt;
612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
613 // Remove two words for return addr and rbp,
614 framesize -= 2*wordSize;
616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
618 if( framesize >= 128 ) {
619 emit_opcode(cbuf, 0x81); // add SP, #framesize
620 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
621 emit_d32(cbuf, framesize);
622 }
623 else if( framesize ) {
624 emit_opcode(cbuf, 0x83); // add SP, #framesize
625 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
626 emit_d8(cbuf, framesize);
627 }
629 emit_opcode(cbuf, 0x58 | EBP_enc);
631 if( do_polling() && C->is_method_compilation() ) {
632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
633 emit_opcode(cbuf,0x85);
634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
635 emit_d32(cbuf, (intptr_t)os::get_polling_page());
636 }
637 }
639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
640 Compile *C = ra_->C;
641 // If method set FPU control word, restore to standard control word
642 int size = C->in_24_bit_fp_mode() ? 6 : 0;
643 if( do_polling() && C->is_method_compilation() ) size += 6;
645 int framesize = C->frame_slots() << LogBytesPerInt;
646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
647 // Remove two words for return addr and rbp,
648 framesize -= 2*wordSize;
650 size++; // popl rbp,
652 if( framesize >= 128 ) {
653 size += 6;
654 } else {
655 size += framesize ? 3 : 0;
656 }
657 return size;
658 }
660 int MachEpilogNode::reloc() const {
661 return 0; // a large enough number
662 }
664 const Pipeline * MachEpilogNode::pipeline() const {
665 return MachNode::pipeline_class();
666 }
668 int MachEpilogNode::safepoint_offset() const { return 0; }
670 //=============================================================================
672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
673 static enum RC rc_class( OptoReg::Name reg ) {
675 if( !OptoReg::is_valid(reg) ) return rc_bad;
676 if (OptoReg::is_stack(reg)) return rc_stack;
678 VMReg r = OptoReg::as_VMReg(reg);
679 if (r->is_Register()) return rc_int;
680 if (r->is_FloatRegister()) {
681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
682 return rc_float;
683 }
684 assert(r->is_XMMRegister(), "must be");
685 return rc_xmm;
686 }
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
693 #ifndef PRODUCT
694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
699 } else { // FLD, FST, PUSH, POP
700 st->print("%s [ESP + #%d]",op_str,offset);
701 }
702 #endif
703 }
704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
705 return size+3+offset_size;
706 }
708 // Helper for XMM registers. Extra opcode bits, limited syntax.
709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
711 if (cbuf) {
712 MacroAssembler _masm(cbuf);
713 if (reg_lo+1 == reg_hi) { // double move?
714 if (is_load) {
715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
716 } else {
717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
718 }
719 } else {
720 if (is_load) {
721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
722 } else {
723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
724 }
725 }
726 #ifndef PRODUCT
727 } else if (!do_size) {
728 if (size != 0) st->print("\n\t");
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) st->print("%s %s,[ESP + #%d]",
731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
732 Matcher::regName[reg_lo], offset);
733 else st->print("MOVSD [ESP + #%d],%s",
734 offset, Matcher::regName[reg_lo]);
735 } else {
736 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
737 Matcher::regName[reg_lo], offset);
738 else st->print("MOVSS [ESP + #%d],%s",
739 offset, Matcher::regName[reg_lo]);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
745 return size+5+offset_size;
746 }
749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
750 int src_hi, int dst_hi, int size, outputStream* st ) {
751 if (cbuf) {
752 MacroAssembler _masm(cbuf);
753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
755 as_XMMRegister(Matcher::_regEncode[src_lo]));
756 } else {
757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
758 as_XMMRegister(Matcher::_regEncode[src_lo]));
759 }
760 #ifndef PRODUCT
761 } else if (!do_size) {
762 if (size != 0) st->print("\n\t");
763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
766 } else {
767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
768 }
769 } else {
770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
772 } else {
773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
774 }
775 }
776 #endif
777 }
778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
779 // Only MOVAPS SSE prefix uses 1 byte.
780 int sz = 4;
781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
783 return size + sz;
784 }
786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
787 int src_hi, int dst_hi, int size, outputStream* st ) {
788 // 32-bit
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
792 as_Register(Matcher::_regEncode[src_lo]));
793 #ifndef PRODUCT
794 } else if (!do_size) {
795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
796 #endif
797 }
798 return 4;
799 }
802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
808 as_XMMRegister(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
818 if( cbuf ) {
819 emit_opcode(*cbuf, 0x8B );
820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
821 #ifndef PRODUCT
822 } else if( !do_size ) {
823 if( size != 0 ) st->print("\n\t");
824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
825 #endif
826 }
827 return size+2;
828 }
830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
831 int offset, int size, outputStream* st ) {
832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
833 if( cbuf ) {
834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 st->print("FLD %s",Matcher::regName[src_lo]);
840 #endif
841 }
842 size += 2;
843 }
845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
846 const char *op_str;
847 int op;
848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
850 op = 0xDD;
851 } else { // 32-bit store
852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
853 op = 0xD9;
854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
855 }
857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
858 }
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
963 // Get registers to move
964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
966 OptoReg::Name dst_second = ra_->get_reg_second(this );
967 OptoReg::Name dst_first = ra_->get_reg_first(this );
969 enum RC src_second_rc = rc_class(src_second);
970 enum RC src_first_rc = rc_class(src_first);
971 enum RC dst_second_rc = rc_class(dst_second);
972 enum RC dst_first_rc = rc_class(dst_first);
974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
976 // Generate spill code!
977 int size = 0;
979 if( src_first == dst_first && src_second == dst_second )
980 return size; // Self copy, no move
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1005 // --------------------------------------
1006 // Check for mem-mem move. push/pop to move.
1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1013 }
1014 // move low bits
1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1020 }
1021 return size;
1022 }
1024 // --------------------------------------
1025 // Check for integer reg-reg copy
1026 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1029 // Check for integer store
1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1033 // Check for integer load
1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1037 // Check for integer reg-xmm reg copy
1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1040 "no 64 bit integer-float reg moves" );
1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1042 }
1043 // --------------------------------------
1044 // Check for float reg-reg copy
1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1048 if( cbuf ) {
1050 // Note the mucking with the register encode to compensate for the 0/1
1051 // indexing issue mentioned in a comment in the reg_def sections
1052 // for FPR registers many lines above here.
1054 if( src_first != FPR1L_num ) {
1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1059 } else {
1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1062 }
1063 #ifndef PRODUCT
1064 } else if( !do_size ) {
1065 if( size != 0 ) st->print("\n\t");
1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1067 else st->print( "FST %s", Matcher::regName[dst_first]);
1068 #endif
1069 }
1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1071 }
1073 // Check for float store
1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1076 }
1078 // Check for float load
1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1080 int offset = ra_->reg2offset(src_first);
1081 const char *op_str;
1082 int op;
1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1084 op_str = "FLD_D";
1085 op = 0xDD;
1086 } else { // 32-bit load
1087 op_str = "FLD_S";
1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 }
1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT
1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t");
1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1100 #endif
1101 }
1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1103 return size + 3+offset_size+2;
1104 }
1106 // Check for xmm reg-reg copy
1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1109 (src_first+1 == src_second && dst_first+1 == dst_second),
1110 "no non-adjacent float-moves" );
1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1112 }
1114 // Check for xmm reg-integer reg copy
1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1117 "no 64 bit float-integer reg moves" );
1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1119 }
1121 // Check for xmm store
1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1124 }
1126 // Check for float xmm load
1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1129 }
1131 // Copy from float reg to xmm reg
1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1133 // copy to the top of stack from floating point reg
1134 // and use LEA to preserve flags
1135 if( cbuf ) {
1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d8(*cbuf,0xF8);
1140 #ifndef PRODUCT
1141 } else if( !do_size ) {
1142 if( size != 0 ) st->print("\n\t");
1143 st->print("LEA ESP,[ESP-8]");
1144 #endif
1145 }
1146 size += 4;
1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1150 // Copy from the temp memory to the xmm reg.
1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1153 if( cbuf ) {
1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1157 emit_d8(*cbuf,0x08);
1158 #ifndef PRODUCT
1159 } else if( !do_size ) {
1160 if( size != 0 ) st->print("\n\t");
1161 st->print("LEA ESP,[ESP+8]");
1162 #endif
1163 }
1164 size += 4;
1165 return size;
1166 }
1168 assert( size > 0, "missed a case" );
1170 // --------------------------------------------------------------------
1171 // Check for second bits still needing moving.
1172 if( src_second == dst_second )
1173 return size; // Self copy; no move
1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1176 // Check for second word int-int move
1177 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1180 // Check for second word integer store
1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1184 // Check for second word integer load
1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1189 Unimplemented();
1190 }
1192 #ifndef PRODUCT
1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1194 implementation( NULL, ra_, false, st );
1195 }
1196 #endif
1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1199 implementation( &cbuf, ra_, false, NULL );
1200 }
1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1203 return implementation( NULL, ra_, true, NULL );
1204 }
1207 //=============================================================================
1208 #ifndef PRODUCT
1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1211 int reg = ra_->get_reg_first(this);
1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1213 }
1214 #endif
1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1218 int reg = ra_->get_encode(this);
1219 if( offset >= 128 ) {
1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1221 emit_rm(cbuf, 0x2, reg, 0x04);
1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1223 emit_d32(cbuf, offset);
1224 }
1225 else {
1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1227 emit_rm(cbuf, 0x1, reg, 0x04);
1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1229 emit_d8(cbuf, offset);
1230 }
1231 }
1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 if( offset >= 128 ) {
1236 return 7;
1237 }
1238 else {
1239 return 4;
1240 }
1241 }
1243 //=============================================================================
1245 // emit call stub, compiled java to interpreter
1246 void emit_java_to_interp(CodeBuffer &cbuf ) {
1247 // Stub is fixed up when the corresponding call is converted from calling
1248 // compiled code to calling interpreted code.
1249 // mov rbx,0
1250 // jmp -1
1252 address mark = cbuf.insts_mark(); // get mark within main instrs section
1254 // Note that the code buffer's insts_mark is always relative to insts.
1255 // That's why we must use the macroassembler to generate a stub.
1256 MacroAssembler _masm(&cbuf);
1258 address base =
1259 __ start_a_stub(Compile::MAX_stubs_size);
1260 if (base == NULL) return; // CodeBuffer::expand failed
1261 // static stub relocation stores the instruction address of the call
1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1263 // static stub relocation also tags the Method* in the code-stream.
1264 __ mov_metadata(rbx, (Metadata*)NULL); // method is zapped till fixup time
1265 // This is recognized as unresolved by relocs/nativeInst/ic code
1266 __ jump(RuntimeAddress(__ pc()));
1268 __ end_a_stub();
1269 // Update current stubs pointer and restore insts_end.
1270 }
1271 // size of call stub, compiled java to interpretor
1272 uint size_java_to_interp() {
1273 return 10; // movl; jmp
1274 }
1275 // relocation entries for call stub, compiled java to interpretor
1276 uint reloc_java_to_interp() {
1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1278 }
1280 //=============================================================================
1281 #ifndef PRODUCT
1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1285 st->print_cr("\tNOP");
1286 st->print_cr("\tNOP");
1287 if( !OptoBreakpoint )
1288 st->print_cr("\tNOP");
1289 }
1290 #endif
1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1293 MacroAssembler masm(&cbuf);
1294 #ifdef ASSERT
1295 uint insts_size = cbuf.insts_size();
1296 #endif
1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1298 masm.jump_cc(Assembler::notEqual,
1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1300 /* WARNING these NOPs are critical so that verified entry point is properly
1301 aligned for patching by NativeJump::patch_verified_entry() */
1302 int nops_cnt = 2;
1303 if( !OptoBreakpoint ) // Leave space for int3
1304 nops_cnt += 1;
1305 masm.nop(nops_cnt);
1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1308 }
1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1311 return OptoBreakpoint ? 11 : 12;
1312 }
1315 //=============================================================================
1316 uint size_exception_handler() {
1317 // NativeCall instruction size is the same as NativeJump.
1318 // exception handler starts out as jump and can be patched to
1319 // a call be deoptimization. (4932387)
1320 // Note that this value is also credited (in output.cpp) to
1321 // the size of the code section.
1322 return NativeJump::instruction_size;
1323 }
1325 // Emit exception handler code. Stuff framesize into a register
1326 // and call a VM stub routine.
1327 int emit_exception_handler(CodeBuffer& cbuf) {
1329 // Note that the code buffer's insts_mark is always relative to insts.
1330 // That's why we must use the macroassembler to generate a handler.
1331 MacroAssembler _masm(&cbuf);
1332 address base =
1333 __ start_a_stub(size_exception_handler());
1334 if (base == NULL) return 0; // CodeBuffer::expand failed
1335 int offset = __ offset();
1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1338 __ end_a_stub();
1339 return offset;
1340 }
1342 uint size_deopt_handler() {
1343 // NativeCall instruction size is the same as NativeJump.
1344 // exception handler starts out as jump and can be patched to
1345 // a call be deoptimization. (4932387)
1346 // Note that this value is also credited (in output.cpp) to
1347 // the size of the code section.
1348 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1349 }
1351 // Emit deopt handler code.
1352 int emit_deopt_handler(CodeBuffer& cbuf) {
1354 // Note that the code buffer's insts_mark is always relative to insts.
1355 // That's why we must use the macroassembler to generate a handler.
1356 MacroAssembler _masm(&cbuf);
1357 address base =
1358 __ start_a_stub(size_exception_handler());
1359 if (base == NULL) return 0; // CodeBuffer::expand failed
1360 int offset = __ offset();
1361 InternalAddress here(__ pc());
1362 __ pushptr(here.addr());
1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1366 __ end_a_stub();
1367 return offset;
1368 }
1370 int Matcher::regnum_to_fpu_offset(int regnum) {
1371 return regnum - 32; // The FP registers are in the second chunk
1372 }
1374 // This is UltraSparc specific, true just means we have fast l2f conversion
1375 const bool Matcher::convL2FSupported(void) {
1376 return true;
1377 }
1379 // Is this branch offset short enough that a short branch can be used?
1380 //
1381 // NOTE: If the platform does not provide any short branch variants, then
1382 // this method should return false for offset 0.
1383 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1384 // The passed offset is relative to address of the branch.
1385 // On 86 a branch displacement is calculated relative to address
1386 // of a next instruction.
1387 offset -= br_size;
1389 // the short version of jmpConUCF2 contains multiple branches,
1390 // making the reach slightly less
1391 if (rule == jmpConUCF2_rule)
1392 return (-126 <= offset && offset <= 125);
1393 return (-128 <= offset && offset <= 127);
1394 }
1396 const bool Matcher::isSimpleConstant64(jlong value) {
1397 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1398 return false;
1399 }
1401 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1402 const bool Matcher::init_array_count_is_in_bytes = false;
1404 // Threshold size for cleararray.
1405 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1407 // Needs 2 CMOV's for longs.
1408 const int Matcher::long_cmove_cost() { return 1; }
1410 // No CMOVF/CMOVD with SSE/SSE2
1411 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1413 // Should the Matcher clone shifts on addressing modes, expecting them to
1414 // be subsumed into complex addressing expressions or compute them into
1415 // registers? True for Intel but false for most RISCs
1416 const bool Matcher::clone_shift_expressions = true;
1418 // Do we need to mask the count passed to shift instructions or does
1419 // the cpu only look at the lower 5/6 bits anyway?
1420 const bool Matcher::need_masked_shift_count = false;
1422 bool Matcher::narrow_oop_use_complex_address() {
1423 ShouldNotCallThis();
1424 return true;
1425 }
1428 // Is it better to copy float constants, or load them directly from memory?
1429 // Intel can load a float constant from a direct address, requiring no
1430 // extra registers. Most RISCs will have to materialize an address into a
1431 // register first, so they would do better to copy the constant from stack.
1432 const bool Matcher::rematerialize_float_constants = true;
1434 // If CPU can load and store mis-aligned doubles directly then no fixup is
1435 // needed. Else we split the double into 2 integer pieces and move it
1436 // piece-by-piece. Only happens when passing doubles into C code as the
1437 // Java calling convention forces doubles to be aligned.
1438 const bool Matcher::misaligned_doubles_ok = true;
1441 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1442 // Get the memory operand from the node
1443 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1444 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1445 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1446 uint opcnt = 1; // First operand
1447 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1448 while( idx >= skipped+num_edges ) {
1449 skipped += num_edges;
1450 opcnt++; // Bump operand count
1451 assert( opcnt < numopnds, "Accessing non-existent operand" );
1452 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1453 }
1455 MachOper *memory = node->_opnds[opcnt];
1456 MachOper *new_memory = NULL;
1457 switch (memory->opcode()) {
1458 case DIRECT:
1459 case INDOFFSET32X:
1460 // No transformation necessary.
1461 return;
1462 case INDIRECT:
1463 new_memory = new (C) indirect_win95_safeOper( );
1464 break;
1465 case INDOFFSET8:
1466 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1467 break;
1468 case INDOFFSET32:
1469 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1470 break;
1471 case INDINDEXOFFSET:
1472 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1473 break;
1474 case INDINDEXSCALE:
1475 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1476 break;
1477 case INDINDEXSCALEOFFSET:
1478 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1479 break;
1480 case LOAD_LONG_INDIRECT:
1481 case LOAD_LONG_INDOFFSET32:
1482 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1483 return;
1484 default:
1485 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1486 return;
1487 }
1488 node->_opnds[opcnt] = new_memory;
1489 }
1491 // Advertise here if the CPU requires explicit rounding operations
1492 // to implement the UseStrictFP mode.
1493 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1495 // Are floats conerted to double when stored to stack during deoptimization?
1496 // On x32 it is stored with convertion only when FPU is used for floats.
1497 bool Matcher::float_in_double() { return (UseSSE == 0); }
1499 // Do ints take an entire long register or just half?
1500 const bool Matcher::int_in_long = false;
1502 // Return whether or not this register is ever used as an argument. This
1503 // function is used on startup to build the trampoline stubs in generateOptoStub.
1504 // Registers not mentioned will be killed by the VM call in the trampoline, and
1505 // arguments in those registers not be available to the callee.
1506 bool Matcher::can_be_java_arg( int reg ) {
1507 if( reg == ECX_num || reg == EDX_num ) return true;
1508 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1509 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1510 return false;
1511 }
1513 bool Matcher::is_spillable_arg( int reg ) {
1514 return can_be_java_arg(reg);
1515 }
1517 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1518 // Use hardware integer DIV instruction when
1519 // it is faster than a code which use multiply.
1520 // Only when constant divisor fits into 32 bit
1521 // (min_jint is excluded to get only correct
1522 // positive 32 bit values from negative).
1523 return VM_Version::has_fast_idiv() &&
1524 (divisor == (int)divisor && divisor != min_jint);
1525 }
1527 // Register for DIVI projection of divmodI
1528 RegMask Matcher::divI_proj_mask() {
1529 return EAX_REG_mask();
1530 }
1532 // Register for MODI projection of divmodI
1533 RegMask Matcher::modI_proj_mask() {
1534 return EDX_REG_mask();
1535 }
1537 // Register for DIVL projection of divmodL
1538 RegMask Matcher::divL_proj_mask() {
1539 ShouldNotReachHere();
1540 return RegMask();
1541 }
1543 // Register for MODL projection of divmodL
1544 RegMask Matcher::modL_proj_mask() {
1545 ShouldNotReachHere();
1546 return RegMask();
1547 }
1549 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1550 return EBP_REG_mask();
1551 }
1553 // Returns true if the high 32 bits of the value is known to be zero.
1554 bool is_operand_hi32_zero(Node* n) {
1555 int opc = n->Opcode();
1556 if (opc == Op_LoadUI2L) {
1557 return true;
1558 }
1559 if (opc == Op_AndL) {
1560 Node* o2 = n->in(2);
1561 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1562 return true;
1563 }
1564 }
1565 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1566 return true;
1567 }
1568 return false;
1569 }
1571 %}
1573 //----------ENCODING BLOCK-----------------------------------------------------
1574 // This block specifies the encoding classes used by the compiler to output
1575 // byte streams. Encoding classes generate functions which are called by
1576 // Machine Instruction Nodes in order to generate the bit encoding of the
1577 // instruction. Operands specify their base encoding interface with the
1578 // interface keyword. There are currently supported four interfaces,
1579 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1580 // operand to generate a function which returns its register number when
1581 // queried. CONST_INTER causes an operand to generate a function which
1582 // returns the value of the constant when queried. MEMORY_INTER causes an
1583 // operand to generate four functions which return the Base Register, the
1584 // Index Register, the Scale Value, and the Offset Value of the operand when
1585 // queried. COND_INTER causes an operand to generate six functions which
1586 // return the encoding code (ie - encoding bits for the instruction)
1587 // associated with each basic boolean condition for a conditional instruction.
1588 // Instructions specify two basic values for encoding. They use the
1589 // ins_encode keyword to specify their encoding class (which must be one of
1590 // the class names specified in the encoding block), and they use the
1591 // opcode keyword to specify, in order, their primary, secondary, and
1592 // tertiary opcode. Only the opcode sections which a particular instruction
1593 // needs for encoding need to be specified.
1594 encode %{
1595 // Build emit functions for each basic byte or larger field in the intel
1596 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1597 // code in the enc_class source block. Emit functions will live in the
1598 // main source block for now. In future, we can generalize this by
1599 // adding a syntax that specifies the sizes of fields in an order,
1600 // so that the adlc can build the emit functions automagically
1602 // Emit primary opcode
1603 enc_class OpcP %{
1604 emit_opcode(cbuf, $primary);
1605 %}
1607 // Emit secondary opcode
1608 enc_class OpcS %{
1609 emit_opcode(cbuf, $secondary);
1610 %}
1612 // Emit opcode directly
1613 enc_class Opcode(immI d8) %{
1614 emit_opcode(cbuf, $d8$$constant);
1615 %}
1617 enc_class SizePrefix %{
1618 emit_opcode(cbuf,0x66);
1619 %}
1621 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1622 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1623 %}
1625 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1626 emit_opcode(cbuf,$opcode$$constant);
1627 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1628 %}
1630 enc_class mov_r32_imm0( rRegI dst ) %{
1631 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1632 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1633 %}
1635 enc_class cdq_enc %{
1636 // Full implementation of Java idiv and irem; checks for
1637 // special case as described in JVM spec., p.243 & p.271.
1638 //
1639 // normal case special case
1640 //
1641 // input : rax,: dividend min_int
1642 // reg: divisor -1
1643 //
1644 // output: rax,: quotient (= rax, idiv reg) min_int
1645 // rdx: remainder (= rax, irem reg) 0
1646 //
1647 // Code sequnce:
1648 //
1649 // 81 F8 00 00 00 80 cmp rax,80000000h
1650 // 0F 85 0B 00 00 00 jne normal_case
1651 // 33 D2 xor rdx,edx
1652 // 83 F9 FF cmp rcx,0FFh
1653 // 0F 84 03 00 00 00 je done
1654 // normal_case:
1655 // 99 cdq
1656 // F7 F9 idiv rax,ecx
1657 // done:
1658 //
1659 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1660 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1661 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1662 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1663 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1664 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1665 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1666 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1667 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1668 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1669 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1670 // normal_case:
1671 emit_opcode(cbuf,0x99); // cdq
1672 // idiv (note: must be emitted by the user of this rule)
1673 // normal:
1674 %}
1676 // Dense encoding for older common ops
1677 enc_class Opc_plus(immI opcode, rRegI reg) %{
1678 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1679 %}
1682 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1683 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1684 // Check for 8-bit immediate, and set sign extend bit in opcode
1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1686 emit_opcode(cbuf, $primary | 0x02);
1687 }
1688 else { // If 32-bit immediate
1689 emit_opcode(cbuf, $primary);
1690 }
1691 %}
1693 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1694 // Emit primary opcode and set sign-extend bit
1695 // Check for 8-bit immediate, and set sign extend bit in opcode
1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1697 emit_opcode(cbuf, $primary | 0x02); }
1698 else { // If 32-bit immediate
1699 emit_opcode(cbuf, $primary);
1700 }
1701 // Emit r/m byte with secondary opcode, after primary opcode.
1702 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1703 %}
1705 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1706 // Check for 8-bit immediate, and set sign extend bit in opcode
1707 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1708 $$$emit8$imm$$constant;
1709 }
1710 else { // If 32-bit immediate
1711 // Output immediate
1712 $$$emit32$imm$$constant;
1713 }
1714 %}
1716 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1717 // Emit primary opcode and set sign-extend bit
1718 // Check for 8-bit immediate, and set sign extend bit in opcode
1719 int con = (int)$imm$$constant; // Throw away top bits
1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1721 // Emit r/m byte with secondary opcode, after primary opcode.
1722 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1724 else emit_d32(cbuf,con);
1725 %}
1727 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1728 // Emit primary opcode and set sign-extend bit
1729 // Check for 8-bit immediate, and set sign extend bit in opcode
1730 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1731 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1732 // Emit r/m byte with tertiary opcode, after primary opcode.
1733 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1734 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1735 else emit_d32(cbuf,con);
1736 %}
1738 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1739 emit_cc(cbuf, $secondary, $dst$$reg );
1740 %}
1742 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1743 int destlo = $dst$$reg;
1744 int desthi = HIGH_FROM_LOW(destlo);
1745 // bswap lo
1746 emit_opcode(cbuf, 0x0F);
1747 emit_cc(cbuf, 0xC8, destlo);
1748 // bswap hi
1749 emit_opcode(cbuf, 0x0F);
1750 emit_cc(cbuf, 0xC8, desthi);
1751 // xchg lo and hi
1752 emit_opcode(cbuf, 0x87);
1753 emit_rm(cbuf, 0x3, destlo, desthi);
1754 %}
1756 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1757 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1758 %}
1760 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1761 $$$emit8$primary;
1762 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1763 %}
1765 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1766 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1767 emit_d8(cbuf, op >> 8 );
1768 emit_d8(cbuf, op & 255);
1769 %}
1771 // emulate a CMOV with a conditional branch around a MOV
1772 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1773 // Invert sense of branch from sense of CMOV
1774 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1775 emit_d8( cbuf, $brOffs$$constant );
1776 %}
1778 enc_class enc_PartialSubtypeCheck( ) %{
1779 Register Redi = as_Register(EDI_enc); // result register
1780 Register Reax = as_Register(EAX_enc); // super class
1781 Register Recx = as_Register(ECX_enc); // killed
1782 Register Resi = as_Register(ESI_enc); // sub class
1783 Label miss;
1785 MacroAssembler _masm(&cbuf);
1786 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1787 NULL, &miss,
1788 /*set_cond_codes:*/ true);
1789 if ($primary) {
1790 __ xorptr(Redi, Redi);
1791 }
1792 __ bind(miss);
1793 %}
1795 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1796 MacroAssembler masm(&cbuf);
1797 int start = masm.offset();
1798 if (UseSSE >= 2) {
1799 if (VerifyFPU) {
1800 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1801 }
1802 } else {
1803 // External c_calling_convention expects the FPU stack to be 'clean'.
1804 // Compiled code leaves it dirty. Do cleanup now.
1805 masm.empty_FPU_stack();
1806 }
1807 if (sizeof_FFree_Float_Stack_All == -1) {
1808 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1809 } else {
1810 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1811 }
1812 %}
1814 enc_class Verify_FPU_For_Leaf %{
1815 if( VerifyFPU ) {
1816 MacroAssembler masm(&cbuf);
1817 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1818 }
1819 %}
1821 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1822 // This is the instruction starting address for relocation info.
1823 cbuf.set_insts_mark();
1824 $$$emit8$primary;
1825 // CALL directly to the runtime
1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1827 runtime_call_Relocation::spec(), RELOC_IMM32 );
1829 if (UseSSE >= 2) {
1830 MacroAssembler _masm(&cbuf);
1831 BasicType rt = tf()->return_type();
1833 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1834 // A C runtime call where the return value is unused. In SSE2+
1835 // mode the result needs to be removed from the FPU stack. It's
1836 // likely that this function call could be removed by the
1837 // optimizer if the C function is a pure function.
1838 __ ffree(0);
1839 } else if (rt == T_FLOAT) {
1840 __ lea(rsp, Address(rsp, -4));
1841 __ fstp_s(Address(rsp, 0));
1842 __ movflt(xmm0, Address(rsp, 0));
1843 __ lea(rsp, Address(rsp, 4));
1844 } else if (rt == T_DOUBLE) {
1845 __ lea(rsp, Address(rsp, -8));
1846 __ fstp_d(Address(rsp, 0));
1847 __ movdbl(xmm0, Address(rsp, 0));
1848 __ lea(rsp, Address(rsp, 8));
1849 }
1850 }
1851 %}
1854 enc_class pre_call_FPU %{
1855 // If method sets FPU control word restore it here
1856 debug_only(int off0 = cbuf.insts_size());
1857 if( Compile::current()->in_24_bit_fp_mode() ) {
1858 MacroAssembler masm(&cbuf);
1859 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1860 }
1861 debug_only(int off1 = cbuf.insts_size());
1862 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1863 %}
1865 enc_class post_call_FPU %{
1866 // If method sets FPU control word do it here also
1867 if( Compile::current()->in_24_bit_fp_mode() ) {
1868 MacroAssembler masm(&cbuf);
1869 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1870 }
1871 %}
1873 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1874 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1875 // who we intended to call.
1876 cbuf.set_insts_mark();
1877 $$$emit8$primary;
1878 if ( !_method ) {
1879 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1880 runtime_call_Relocation::spec(), RELOC_IMM32 );
1881 } else if(_optimized_virtual) {
1882 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1883 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1884 } else {
1885 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1886 static_call_Relocation::spec(), RELOC_IMM32 );
1887 }
1888 if( _method ) { // Emit stub for static call
1889 emit_java_to_interp(cbuf);
1890 }
1891 %}
1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1894 MacroAssembler _masm(&cbuf);
1895 __ ic_call((address)$meth$$method);
1896 %}
1898 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1899 int disp = in_bytes(Method::from_compiled_offset());
1900 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1902 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1903 cbuf.set_insts_mark();
1904 $$$emit8$primary;
1905 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1906 emit_d8(cbuf, disp); // Displacement
1908 %}
1910 // Following encoding is no longer used, but may be restored if calling
1911 // convention changes significantly.
1912 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1913 //
1914 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1915 // // int ic_reg = Matcher::inline_cache_reg();
1916 // // int ic_encode = Matcher::_regEncode[ic_reg];
1917 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1918 // // int imo_encode = Matcher::_regEncode[imo_reg];
1919 //
1920 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1921 // // // so we load it immediately before the call
1922 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1923 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1924 //
1925 // // xor rbp,ebp
1926 // emit_opcode(cbuf, 0x33);
1927 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1928 //
1929 // // CALL to interpreter.
1930 // cbuf.set_insts_mark();
1931 // $$$emit8$primary;
1932 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1933 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1934 // %}
1936 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1937 $$$emit8$primary;
1938 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1939 $$$emit8$shift$$constant;
1940 %}
1942 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1943 // Load immediate does not have a zero or sign extended version
1944 // for 8-bit immediates
1945 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1946 $$$emit32$src$$constant;
1947 %}
1949 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1950 // Load immediate does not have a zero or sign extended version
1951 // for 8-bit immediates
1952 emit_opcode(cbuf, $primary + $dst$$reg);
1953 $$$emit32$src$$constant;
1954 %}
1956 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1957 // Load immediate does not have a zero or sign extended version
1958 // for 8-bit immediates
1959 int dst_enc = $dst$$reg;
1960 int src_con = $src$$constant & 0x0FFFFFFFFL;
1961 if (src_con == 0) {
1962 // xor dst, dst
1963 emit_opcode(cbuf, 0x33);
1964 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1965 } else {
1966 emit_opcode(cbuf, $primary + dst_enc);
1967 emit_d32(cbuf, src_con);
1968 }
1969 %}
1971 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1972 // Load immediate does not have a zero or sign extended version
1973 // for 8-bit immediates
1974 int dst_enc = $dst$$reg + 2;
1975 int src_con = ((julong)($src$$constant)) >> 32;
1976 if (src_con == 0) {
1977 // xor dst, dst
1978 emit_opcode(cbuf, 0x33);
1979 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1980 } else {
1981 emit_opcode(cbuf, $primary + dst_enc);
1982 emit_d32(cbuf, src_con);
1983 }
1984 %}
1987 // Encode a reg-reg copy. If it is useless, then empty encoding.
1988 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1989 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1990 %}
1992 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1993 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1994 %}
1996 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1998 %}
2000 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2001 $$$emit8$primary;
2002 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2003 %}
2005 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2006 $$$emit8$secondary;
2007 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2008 %}
2010 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2011 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2012 %}
2014 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2016 %}
2018 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2019 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2020 %}
2022 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2023 // Output immediate
2024 $$$emit32$src$$constant;
2025 %}
2027 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2028 // Output Float immediate bits
2029 jfloat jf = $src$$constant;
2030 int jf_as_bits = jint_cast( jf );
2031 emit_d32(cbuf, jf_as_bits);
2032 %}
2034 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2035 // Output Float immediate bits
2036 jfloat jf = $src$$constant;
2037 int jf_as_bits = jint_cast( jf );
2038 emit_d32(cbuf, jf_as_bits);
2039 %}
2041 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2042 // Output immediate
2043 $$$emit16$src$$constant;
2044 %}
2046 enc_class Con_d32(immI src) %{
2047 emit_d32(cbuf,$src$$constant);
2048 %}
2050 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2051 // Output immediate memory reference
2052 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2053 emit_d32(cbuf, 0x00);
2054 %}
2056 enc_class lock_prefix( ) %{
2057 if( os::is_MP() )
2058 emit_opcode(cbuf,0xF0); // [Lock]
2059 %}
2061 // Cmp-xchg long value.
2062 // Note: we need to swap rbx, and rcx before and after the
2063 // cmpxchg8 instruction because the instruction uses
2064 // rcx as the high order word of the new value to store but
2065 // our register encoding uses rbx,.
2066 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2068 // XCHG rbx,ecx
2069 emit_opcode(cbuf,0x87);
2070 emit_opcode(cbuf,0xD9);
2071 // [Lock]
2072 if( os::is_MP() )
2073 emit_opcode(cbuf,0xF0);
2074 // CMPXCHG8 [Eptr]
2075 emit_opcode(cbuf,0x0F);
2076 emit_opcode(cbuf,0xC7);
2077 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2078 // XCHG rbx,ecx
2079 emit_opcode(cbuf,0x87);
2080 emit_opcode(cbuf,0xD9);
2081 %}
2083 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2084 // [Lock]
2085 if( os::is_MP() )
2086 emit_opcode(cbuf,0xF0);
2088 // CMPXCHG [Eptr]
2089 emit_opcode(cbuf,0x0F);
2090 emit_opcode(cbuf,0xB1);
2091 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2092 %}
2094 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2095 int res_encoding = $res$$reg;
2097 // MOV res,0
2098 emit_opcode( cbuf, 0xB8 + res_encoding);
2099 emit_d32( cbuf, 0 );
2100 // JNE,s fail
2101 emit_opcode(cbuf,0x75);
2102 emit_d8(cbuf, 5 );
2103 // MOV res,1
2104 emit_opcode( cbuf, 0xB8 + res_encoding);
2105 emit_d32( cbuf, 1 );
2106 // fail:
2107 %}
2109 enc_class set_instruction_start( ) %{
2110 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2111 %}
2113 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2114 int reg_encoding = $ereg$$reg;
2115 int base = $mem$$base;
2116 int index = $mem$$index;
2117 int scale = $mem$$scale;
2118 int displace = $mem$$disp;
2119 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2120 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2121 %}
2123 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2124 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2125 int base = $mem$$base;
2126 int index = $mem$$index;
2127 int scale = $mem$$scale;
2128 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2129 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2130 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2131 %}
2133 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2134 int r1, r2;
2135 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2136 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2137 emit_opcode(cbuf,0x0F);
2138 emit_opcode(cbuf,$tertiary);
2139 emit_rm(cbuf, 0x3, r1, r2);
2140 emit_d8(cbuf,$cnt$$constant);
2141 emit_d8(cbuf,$primary);
2142 emit_rm(cbuf, 0x3, $secondary, r1);
2143 emit_d8(cbuf,$cnt$$constant);
2144 %}
2146 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2147 emit_opcode( cbuf, 0x8B ); // Move
2148 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2149 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2150 emit_d8(cbuf,$primary);
2151 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2152 emit_d8(cbuf,$cnt$$constant-32);
2153 }
2154 emit_d8(cbuf,$primary);
2155 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2156 emit_d8(cbuf,31);
2157 %}
2159 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2160 int r1, r2;
2161 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2162 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2164 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2165 emit_rm(cbuf, 0x3, r1, r2);
2166 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2167 emit_opcode(cbuf,$primary);
2168 emit_rm(cbuf, 0x3, $secondary, r1);
2169 emit_d8(cbuf,$cnt$$constant-32);
2170 }
2171 emit_opcode(cbuf,0x33); // XOR r2,r2
2172 emit_rm(cbuf, 0x3, r2, r2);
2173 %}
2175 // Clone of RegMem but accepts an extra parameter to access each
2176 // half of a double in memory; it never needs relocation info.
2177 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2178 emit_opcode(cbuf,$opcode$$constant);
2179 int reg_encoding = $rm_reg$$reg;
2180 int base = $mem$$base;
2181 int index = $mem$$index;
2182 int scale = $mem$$scale;
2183 int displace = $mem$$disp + $disp_for_half$$constant;
2184 relocInfo::relocType disp_reloc = relocInfo::none;
2185 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2186 %}
2188 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2189 //
2190 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2191 // and it never needs relocation information.
2192 // Frequently used to move data between FPU's Stack Top and memory.
2193 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2194 int rm_byte_opcode = $rm_opcode$$constant;
2195 int base = $mem$$base;
2196 int index = $mem$$index;
2197 int scale = $mem$$scale;
2198 int displace = $mem$$disp;
2199 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2200 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2201 %}
2203 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2204 int rm_byte_opcode = $rm_opcode$$constant;
2205 int base = $mem$$base;
2206 int index = $mem$$index;
2207 int scale = $mem$$scale;
2208 int displace = $mem$$disp;
2209 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2210 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2211 %}
2213 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2214 int reg_encoding = $dst$$reg;
2215 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2216 int index = 0x04; // 0x04 indicates no index
2217 int scale = 0x00; // 0x00 indicates no scale
2218 int displace = $src1$$constant; // 0x00 indicates no displacement
2219 relocInfo::relocType disp_reloc = relocInfo::none;
2220 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2221 %}
2223 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2224 // Compare dst,src
2225 emit_opcode(cbuf,0x3B);
2226 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2227 // jmp dst < src around move
2228 emit_opcode(cbuf,0x7C);
2229 emit_d8(cbuf,2);
2230 // move dst,src
2231 emit_opcode(cbuf,0x8B);
2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2233 %}
2235 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2236 // Compare dst,src
2237 emit_opcode(cbuf,0x3B);
2238 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2239 // jmp dst > src around move
2240 emit_opcode(cbuf,0x7F);
2241 emit_d8(cbuf,2);
2242 // move dst,src
2243 emit_opcode(cbuf,0x8B);
2244 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2245 %}
2247 enc_class enc_FPR_store(memory mem, regDPR src) %{
2248 // If src is FPR1, we can just FST to store it.
2249 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2250 int reg_encoding = 0x2; // Just store
2251 int base = $mem$$base;
2252 int index = $mem$$index;
2253 int scale = $mem$$scale;
2254 int displace = $mem$$disp;
2255 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2256 if( $src$$reg != FPR1L_enc ) {
2257 reg_encoding = 0x3; // Store & pop
2258 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2259 emit_d8( cbuf, 0xC0-1+$src$$reg );
2260 }
2261 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2262 emit_opcode(cbuf,$primary);
2263 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2264 %}
2266 enc_class neg_reg(rRegI dst) %{
2267 // NEG $dst
2268 emit_opcode(cbuf,0xF7);
2269 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2270 %}
2272 enc_class setLT_reg(eCXRegI dst) %{
2273 // SETLT $dst
2274 emit_opcode(cbuf,0x0F);
2275 emit_opcode(cbuf,0x9C);
2276 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2277 %}
2279 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2280 int tmpReg = $tmp$$reg;
2282 // SUB $p,$q
2283 emit_opcode(cbuf,0x2B);
2284 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2285 // SBB $tmp,$tmp
2286 emit_opcode(cbuf,0x1B);
2287 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2288 // AND $tmp,$y
2289 emit_opcode(cbuf,0x23);
2290 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2291 // ADD $p,$tmp
2292 emit_opcode(cbuf,0x03);
2293 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2294 %}
2296 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2297 int tmpReg = $tmp$$reg;
2299 // SUB $p,$q
2300 emit_opcode(cbuf,0x2B);
2301 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2302 // SBB $tmp,$tmp
2303 emit_opcode(cbuf,0x1B);
2304 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2305 // AND $tmp,$y
2306 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2307 emit_opcode(cbuf,0x23);
2308 int reg_encoding = tmpReg;
2309 int base = $mem$$base;
2310 int index = $mem$$index;
2311 int scale = $mem$$scale;
2312 int displace = $mem$$disp;
2313 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2314 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2315 // ADD $p,$tmp
2316 emit_opcode(cbuf,0x03);
2317 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2318 %}
2320 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2321 // TEST shift,32
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0, ECX_enc);
2324 emit_d32(cbuf,0x20);
2325 // JEQ,s small
2326 emit_opcode(cbuf, 0x74);
2327 emit_d8(cbuf, 0x04);
2328 // MOV $dst.hi,$dst.lo
2329 emit_opcode( cbuf, 0x8B );
2330 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2331 // CLR $dst.lo
2332 emit_opcode(cbuf, 0x33);
2333 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2334 // small:
2335 // SHLD $dst.hi,$dst.lo,$shift
2336 emit_opcode(cbuf,0x0F);
2337 emit_opcode(cbuf,0xA5);
2338 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2339 // SHL $dst.lo,$shift"
2340 emit_opcode(cbuf,0xD3);
2341 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2342 %}
2344 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2345 // TEST shift,32
2346 emit_opcode(cbuf,0xF7);
2347 emit_rm(cbuf, 0x3, 0, ECX_enc);
2348 emit_d32(cbuf,0x20);
2349 // JEQ,s small
2350 emit_opcode(cbuf, 0x74);
2351 emit_d8(cbuf, 0x04);
2352 // MOV $dst.lo,$dst.hi
2353 emit_opcode( cbuf, 0x8B );
2354 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2355 // CLR $dst.hi
2356 emit_opcode(cbuf, 0x33);
2357 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2358 // small:
2359 // SHRD $dst.lo,$dst.hi,$shift
2360 emit_opcode(cbuf,0x0F);
2361 emit_opcode(cbuf,0xAD);
2362 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2363 // SHR $dst.hi,$shift"
2364 emit_opcode(cbuf,0xD3);
2365 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2366 %}
2368 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2369 // TEST shift,32
2370 emit_opcode(cbuf,0xF7);
2371 emit_rm(cbuf, 0x3, 0, ECX_enc);
2372 emit_d32(cbuf,0x20);
2373 // JEQ,s small
2374 emit_opcode(cbuf, 0x74);
2375 emit_d8(cbuf, 0x05);
2376 // MOV $dst.lo,$dst.hi
2377 emit_opcode( cbuf, 0x8B );
2378 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2379 // SAR $dst.hi,31
2380 emit_opcode(cbuf, 0xC1);
2381 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2382 emit_d8(cbuf, 0x1F );
2383 // small:
2384 // SHRD $dst.lo,$dst.hi,$shift
2385 emit_opcode(cbuf,0x0F);
2386 emit_opcode(cbuf,0xAD);
2387 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2388 // SAR $dst.hi,$shift"
2389 emit_opcode(cbuf,0xD3);
2390 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2391 %}
2394 // ----------------- Encodings for floating point unit -----------------
2395 // May leave result in FPU-TOS or FPU reg depending on opcodes
2396 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2397 $$$emit8$primary;
2398 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2399 %}
2401 // Pop argument in FPR0 with FSTP ST(0)
2402 enc_class PopFPU() %{
2403 emit_opcode( cbuf, 0xDD );
2404 emit_d8( cbuf, 0xD8 );
2405 %}
2407 // !!!!! equivalent to Pop_Reg_F
2408 enc_class Pop_Reg_DPR( regDPR dst ) %{
2409 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2410 emit_d8( cbuf, 0xD8+$dst$$reg );
2411 %}
2413 enc_class Push_Reg_DPR( regDPR dst ) %{
2414 emit_opcode( cbuf, 0xD9 );
2415 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2416 %}
2418 enc_class strictfp_bias1( regDPR dst ) %{
2419 emit_opcode( cbuf, 0xDB ); // FLD m80real
2420 emit_opcode( cbuf, 0x2D );
2421 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2422 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2423 emit_opcode( cbuf, 0xC8+$dst$$reg );
2424 %}
2426 enc_class strictfp_bias2( regDPR dst ) %{
2427 emit_opcode( cbuf, 0xDB ); // FLD m80real
2428 emit_opcode( cbuf, 0x2D );
2429 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2430 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2431 emit_opcode( cbuf, 0xC8+$dst$$reg );
2432 %}
2434 // Special case for moving an integer register to a stack slot.
2435 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2436 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2437 %}
2439 // Special case for moving a register to a stack slot.
2440 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2441 // Opcode already emitted
2442 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2443 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2444 emit_d32(cbuf, $dst$$disp); // Displacement
2445 %}
2447 // Push the integer in stackSlot 'src' onto FP-stack
2448 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2449 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2450 %}
2452 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2453 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2454 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2455 %}
2457 // Same as Pop_Mem_F except for opcode
2458 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2459 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2460 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2461 %}
2463 enc_class Pop_Reg_FPR( regFPR dst ) %{
2464 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2465 emit_d8( cbuf, 0xD8+$dst$$reg );
2466 %}
2468 enc_class Push_Reg_FPR( regFPR dst ) %{
2469 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2470 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2471 %}
2473 // Push FPU's float to a stack-slot, and pop FPU-stack
2474 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2475 int pop = 0x02;
2476 if ($src$$reg != FPR1L_enc) {
2477 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2478 emit_d8( cbuf, 0xC0-1+$src$$reg );
2479 pop = 0x03;
2480 }
2481 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2482 %}
2484 // Push FPU's double to a stack-slot, and pop FPU-stack
2485 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2486 int pop = 0x02;
2487 if ($src$$reg != FPR1L_enc) {
2488 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2489 emit_d8( cbuf, 0xC0-1+$src$$reg );
2490 pop = 0x03;
2491 }
2492 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2493 %}
2495 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2496 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2497 int pop = 0xD0 - 1; // -1 since we skip FLD
2498 if ($src$$reg != FPR1L_enc) {
2499 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2500 emit_d8( cbuf, 0xC0-1+$src$$reg );
2501 pop = 0xD8;
2502 }
2503 emit_opcode( cbuf, 0xDD );
2504 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2505 %}
2508 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2509 // load dst in FPR0
2510 emit_opcode( cbuf, 0xD9 );
2511 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2512 if ($src$$reg != FPR1L_enc) {
2513 // fincstp
2514 emit_opcode (cbuf, 0xD9);
2515 emit_opcode (cbuf, 0xF7);
2516 // swap src with FPR1:
2517 // FXCH FPR1 with src
2518 emit_opcode(cbuf, 0xD9);
2519 emit_d8(cbuf, 0xC8-1+$src$$reg );
2520 // fdecstp
2521 emit_opcode (cbuf, 0xD9);
2522 emit_opcode (cbuf, 0xF6);
2523 }
2524 %}
2526 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2527 MacroAssembler _masm(&cbuf);
2528 __ subptr(rsp, 8);
2529 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2530 __ fld_d(Address(rsp, 0));
2531 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2532 __ fld_d(Address(rsp, 0));
2533 %}
2535 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2536 MacroAssembler _masm(&cbuf);
2537 __ subptr(rsp, 4);
2538 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2539 __ fld_s(Address(rsp, 0));
2540 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2541 __ fld_s(Address(rsp, 0));
2542 %}
2544 enc_class Push_ResultD(regD dst) %{
2545 MacroAssembler _masm(&cbuf);
2546 __ fstp_d(Address(rsp, 0));
2547 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2548 __ addptr(rsp, 8);
2549 %}
2551 enc_class Push_ResultF(regF dst, immI d8) %{
2552 MacroAssembler _masm(&cbuf);
2553 __ fstp_s(Address(rsp, 0));
2554 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2555 __ addptr(rsp, $d8$$constant);
2556 %}
2558 enc_class Push_SrcD(regD src) %{
2559 MacroAssembler _masm(&cbuf);
2560 __ subptr(rsp, 8);
2561 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2562 __ fld_d(Address(rsp, 0));
2563 %}
2565 enc_class push_stack_temp_qword() %{
2566 MacroAssembler _masm(&cbuf);
2567 __ subptr(rsp, 8);
2568 %}
2570 enc_class pop_stack_temp_qword() %{
2571 MacroAssembler _masm(&cbuf);
2572 __ addptr(rsp, 8);
2573 %}
2575 enc_class push_xmm_to_fpr1(regD src) %{
2576 MacroAssembler _masm(&cbuf);
2577 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2578 __ fld_d(Address(rsp, 0));
2579 %}
2581 enc_class Push_Result_Mod_DPR( regDPR src) %{
2582 if ($src$$reg != FPR1L_enc) {
2583 // fincstp
2584 emit_opcode (cbuf, 0xD9);
2585 emit_opcode (cbuf, 0xF7);
2586 // FXCH FPR1 with src
2587 emit_opcode(cbuf, 0xD9);
2588 emit_d8(cbuf, 0xC8-1+$src$$reg );
2589 // fdecstp
2590 emit_opcode (cbuf, 0xD9);
2591 emit_opcode (cbuf, 0xF6);
2592 }
2593 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2594 // // FSTP FPR$dst$$reg
2595 // emit_opcode( cbuf, 0xDD );
2596 // emit_d8( cbuf, 0xD8+$dst$$reg );
2597 %}
2599 enc_class fnstsw_sahf_skip_parity() %{
2600 // fnstsw ax
2601 emit_opcode( cbuf, 0xDF );
2602 emit_opcode( cbuf, 0xE0 );
2603 // sahf
2604 emit_opcode( cbuf, 0x9E );
2605 // jnp ::skip
2606 emit_opcode( cbuf, 0x7B );
2607 emit_opcode( cbuf, 0x05 );
2608 %}
2610 enc_class emitModDPR() %{
2611 // fprem must be iterative
2612 // :: loop
2613 // fprem
2614 emit_opcode( cbuf, 0xD9 );
2615 emit_opcode( cbuf, 0xF8 );
2616 // wait
2617 emit_opcode( cbuf, 0x9b );
2618 // fnstsw ax
2619 emit_opcode( cbuf, 0xDF );
2620 emit_opcode( cbuf, 0xE0 );
2621 // sahf
2622 emit_opcode( cbuf, 0x9E );
2623 // jp ::loop
2624 emit_opcode( cbuf, 0x0F );
2625 emit_opcode( cbuf, 0x8A );
2626 emit_opcode( cbuf, 0xF4 );
2627 emit_opcode( cbuf, 0xFF );
2628 emit_opcode( cbuf, 0xFF );
2629 emit_opcode( cbuf, 0xFF );
2630 %}
2632 enc_class fpu_flags() %{
2633 // fnstsw_ax
2634 emit_opcode( cbuf, 0xDF);
2635 emit_opcode( cbuf, 0xE0);
2636 // test ax,0x0400
2637 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2638 emit_opcode( cbuf, 0xA9 );
2639 emit_d16 ( cbuf, 0x0400 );
2640 // // // This sequence works, but stalls for 12-16 cycles on PPro
2641 // // test rax,0x0400
2642 // emit_opcode( cbuf, 0xA9 );
2643 // emit_d32 ( cbuf, 0x00000400 );
2644 //
2645 // jz exit (no unordered comparison)
2646 emit_opcode( cbuf, 0x74 );
2647 emit_d8 ( cbuf, 0x02 );
2648 // mov ah,1 - treat as LT case (set carry flag)
2649 emit_opcode( cbuf, 0xB4 );
2650 emit_d8 ( cbuf, 0x01 );
2651 // sahf
2652 emit_opcode( cbuf, 0x9E);
2653 %}
2655 enc_class cmpF_P6_fixup() %{
2656 // Fixup the integer flags in case comparison involved a NaN
2657 //
2658 // JNP exit (no unordered comparison, P-flag is set by NaN)
2659 emit_opcode( cbuf, 0x7B );
2660 emit_d8 ( cbuf, 0x03 );
2661 // MOV AH,1 - treat as LT case (set carry flag)
2662 emit_opcode( cbuf, 0xB4 );
2663 emit_d8 ( cbuf, 0x01 );
2664 // SAHF
2665 emit_opcode( cbuf, 0x9E);
2666 // NOP // target for branch to avoid branch to branch
2667 emit_opcode( cbuf, 0x90);
2668 %}
2670 // fnstsw_ax();
2671 // sahf();
2672 // movl(dst, nan_result);
2673 // jcc(Assembler::parity, exit);
2674 // movl(dst, less_result);
2675 // jcc(Assembler::below, exit);
2676 // movl(dst, equal_result);
2677 // jcc(Assembler::equal, exit);
2678 // movl(dst, greater_result);
2680 // less_result = 1;
2681 // greater_result = -1;
2682 // equal_result = 0;
2683 // nan_result = -1;
2685 enc_class CmpF_Result(rRegI dst) %{
2686 // fnstsw_ax();
2687 emit_opcode( cbuf, 0xDF);
2688 emit_opcode( cbuf, 0xE0);
2689 // sahf
2690 emit_opcode( cbuf, 0x9E);
2691 // movl(dst, nan_result);
2692 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2693 emit_d32( cbuf, -1 );
2694 // jcc(Assembler::parity, exit);
2695 emit_opcode( cbuf, 0x7A );
2696 emit_d8 ( cbuf, 0x13 );
2697 // movl(dst, less_result);
2698 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2699 emit_d32( cbuf, -1 );
2700 // jcc(Assembler::below, exit);
2701 emit_opcode( cbuf, 0x72 );
2702 emit_d8 ( cbuf, 0x0C );
2703 // movl(dst, equal_result);
2704 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2705 emit_d32( cbuf, 0 );
2706 // jcc(Assembler::equal, exit);
2707 emit_opcode( cbuf, 0x74 );
2708 emit_d8 ( cbuf, 0x05 );
2709 // movl(dst, greater_result);
2710 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2711 emit_d32( cbuf, 1 );
2712 %}
2715 // Compare the longs and set flags
2716 // BROKEN! Do Not use as-is
2717 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2718 // CMP $src1.hi,$src2.hi
2719 emit_opcode( cbuf, 0x3B );
2720 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2721 // JNE,s done
2722 emit_opcode(cbuf,0x75);
2723 emit_d8(cbuf, 2 );
2724 // CMP $src1.lo,$src2.lo
2725 emit_opcode( cbuf, 0x3B );
2726 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2727 // done:
2728 %}
2730 enc_class convert_int_long( regL dst, rRegI src ) %{
2731 // mov $dst.lo,$src
2732 int dst_encoding = $dst$$reg;
2733 int src_encoding = $src$$reg;
2734 encode_Copy( cbuf, dst_encoding , src_encoding );
2735 // mov $dst.hi,$src
2736 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2737 // sar $dst.hi,31
2738 emit_opcode( cbuf, 0xC1 );
2739 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2740 emit_d8(cbuf, 0x1F );
2741 %}
2743 enc_class convert_long_double( eRegL src ) %{
2744 // push $src.hi
2745 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2746 // push $src.lo
2747 emit_opcode(cbuf, 0x50+$src$$reg );
2748 // fild 64-bits at [SP]
2749 emit_opcode(cbuf,0xdf);
2750 emit_d8(cbuf, 0x6C);
2751 emit_d8(cbuf, 0x24);
2752 emit_d8(cbuf, 0x00);
2753 // pop stack
2754 emit_opcode(cbuf, 0x83); // add SP, #8
2755 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2756 emit_d8(cbuf, 0x8);
2757 %}
2759 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2760 // IMUL EDX:EAX,$src1
2761 emit_opcode( cbuf, 0xF7 );
2762 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2763 // SAR EDX,$cnt-32
2764 int shift_count = ((int)$cnt$$constant) - 32;
2765 if (shift_count > 0) {
2766 emit_opcode(cbuf, 0xC1);
2767 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2768 emit_d8(cbuf, shift_count);
2769 }
2770 %}
2772 // this version doesn't have add sp, 8
2773 enc_class convert_long_double2( eRegL src ) %{
2774 // push $src.hi
2775 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2776 // push $src.lo
2777 emit_opcode(cbuf, 0x50+$src$$reg );
2778 // fild 64-bits at [SP]
2779 emit_opcode(cbuf,0xdf);
2780 emit_d8(cbuf, 0x6C);
2781 emit_d8(cbuf, 0x24);
2782 emit_d8(cbuf, 0x00);
2783 %}
2785 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2786 // Basic idea: long = (long)int * (long)int
2787 // IMUL EDX:EAX, src
2788 emit_opcode( cbuf, 0xF7 );
2789 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2790 %}
2792 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2793 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2794 // MUL EDX:EAX, src
2795 emit_opcode( cbuf, 0xF7 );
2796 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2797 %}
2799 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2800 // Basic idea: lo(result) = lo(x_lo * y_lo)
2801 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2802 // MOV $tmp,$src.lo
2803 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2804 // IMUL $tmp,EDX
2805 emit_opcode( cbuf, 0x0F );
2806 emit_opcode( cbuf, 0xAF );
2807 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2808 // MOV EDX,$src.hi
2809 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2810 // IMUL EDX,EAX
2811 emit_opcode( cbuf, 0x0F );
2812 emit_opcode( cbuf, 0xAF );
2813 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2814 // ADD $tmp,EDX
2815 emit_opcode( cbuf, 0x03 );
2816 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2817 // MUL EDX:EAX,$src.lo
2818 emit_opcode( cbuf, 0xF7 );
2819 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2820 // ADD EDX,ESI
2821 emit_opcode( cbuf, 0x03 );
2822 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2823 %}
2825 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2826 // Basic idea: lo(result) = lo(src * y_lo)
2827 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2828 // IMUL $tmp,EDX,$src
2829 emit_opcode( cbuf, 0x6B );
2830 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2831 emit_d8( cbuf, (int)$src$$constant );
2832 // MOV EDX,$src
2833 emit_opcode(cbuf, 0xB8 + EDX_enc);
2834 emit_d32( cbuf, (int)$src$$constant );
2835 // MUL EDX:EAX,EDX
2836 emit_opcode( cbuf, 0xF7 );
2837 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2838 // ADD EDX,ESI
2839 emit_opcode( cbuf, 0x03 );
2840 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2841 %}
2843 enc_class long_div( eRegL src1, eRegL src2 ) %{
2844 // PUSH src1.hi
2845 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2846 // PUSH src1.lo
2847 emit_opcode(cbuf, 0x50+$src1$$reg );
2848 // PUSH src2.hi
2849 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2850 // PUSH src2.lo
2851 emit_opcode(cbuf, 0x50+$src2$$reg );
2852 // CALL directly to the runtime
2853 cbuf.set_insts_mark();
2854 emit_opcode(cbuf,0xE8); // Call into runtime
2855 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2856 // Restore stack
2857 emit_opcode(cbuf, 0x83); // add SP, #framesize
2858 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2859 emit_d8(cbuf, 4*4);
2860 %}
2862 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2863 // PUSH src1.hi
2864 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2865 // PUSH src1.lo
2866 emit_opcode(cbuf, 0x50+$src1$$reg );
2867 // PUSH src2.hi
2868 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2869 // PUSH src2.lo
2870 emit_opcode(cbuf, 0x50+$src2$$reg );
2871 // CALL directly to the runtime
2872 cbuf.set_insts_mark();
2873 emit_opcode(cbuf,0xE8); // Call into runtime
2874 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2875 // Restore stack
2876 emit_opcode(cbuf, 0x83); // add SP, #framesize
2877 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2878 emit_d8(cbuf, 4*4);
2879 %}
2881 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2882 // MOV $tmp,$src.lo
2883 emit_opcode(cbuf, 0x8B);
2884 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2885 // OR $tmp,$src.hi
2886 emit_opcode(cbuf, 0x0B);
2887 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2888 %}
2890 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2891 // CMP $src1.lo,$src2.lo
2892 emit_opcode( cbuf, 0x3B );
2893 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2894 // JNE,s skip
2895 emit_cc(cbuf, 0x70, 0x5);
2896 emit_d8(cbuf,2);
2897 // CMP $src1.hi,$src2.hi
2898 emit_opcode( cbuf, 0x3B );
2899 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2900 %}
2902 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2903 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2904 emit_opcode( cbuf, 0x3B );
2905 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2906 // MOV $tmp,$src1.hi
2907 emit_opcode( cbuf, 0x8B );
2908 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2909 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2910 emit_opcode( cbuf, 0x1B );
2911 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2912 %}
2914 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2915 // XOR $tmp,$tmp
2916 emit_opcode(cbuf,0x33); // XOR
2917 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2918 // CMP $tmp,$src.lo
2919 emit_opcode( cbuf, 0x3B );
2920 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2921 // SBB $tmp,$src.hi
2922 emit_opcode( cbuf, 0x1B );
2923 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2924 %}
2926 // Sniff, sniff... smells like Gnu Superoptimizer
2927 enc_class neg_long( eRegL dst ) %{
2928 emit_opcode(cbuf,0xF7); // NEG hi
2929 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2930 emit_opcode(cbuf,0xF7); // NEG lo
2931 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2932 emit_opcode(cbuf,0x83); // SBB hi,0
2933 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2934 emit_d8 (cbuf,0 );
2935 %}
2938 // Because the transitions from emitted code to the runtime
2939 // monitorenter/exit helper stubs are so slow it's critical that
2940 // we inline both the stack-locking fast-path and the inflated fast path.
2941 //
2942 // See also: cmpFastLock and cmpFastUnlock.
2943 //
2944 // What follows is a specialized inline transliteration of the code
2945 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2946 // another option would be to emit TrySlowEnter and TrySlowExit methods
2947 // at startup-time. These methods would accept arguments as
2948 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2949 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2950 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2951 // In practice, however, the # of lock sites is bounded and is usually small.
2952 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2953 // if the processor uses simple bimodal branch predictors keyed by EIP
2954 // Since the helper routines would be called from multiple synchronization
2955 // sites.
2956 //
2957 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2958 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2959 // to those specialized methods. That'd give us a mostly platform-independent
2960 // implementation that the JITs could optimize and inline at their pleasure.
2961 // Done correctly, the only time we'd need to cross to native could would be
2962 // to park() or unpark() threads. We'd also need a few more unsafe operators
2963 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2964 // (b) explicit barriers or fence operations.
2965 //
2966 // TODO:
2967 //
2968 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2969 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2970 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2971 // the lock operators would typically be faster than reifying Self.
2972 //
2973 // * Ideally I'd define the primitives as:
2974 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2975 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2976 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2977 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2978 // Furthermore the register assignments are overconstrained, possibly resulting in
2979 // sub-optimal code near the synchronization site.
2980 //
2981 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2982 // Alternately, use a better sp-proximity test.
2983 //
2984 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2985 // Either one is sufficient to uniquely identify a thread.
2986 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2987 //
2988 // * Intrinsify notify() and notifyAll() for the common cases where the
2989 // object is locked by the calling thread but the waitlist is empty.
2990 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2991 //
2992 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2993 // But beware of excessive branch density on AMD Opterons.
2994 //
2995 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2996 // or failure of the fast-path. If the fast-path fails then we pass
2997 // control to the slow-path, typically in C. In Fast_Lock and
2998 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2999 // will emit a conditional branch immediately after the node.
3000 // So we have branches to branches and lots of ICC.ZF games.
3001 // Instead, it might be better to have C2 pass a "FailureLabel"
3002 // into Fast_Lock and Fast_Unlock. In the case of success, control
3003 // will drop through the node. ICC.ZF is undefined at exit.
3004 // In the case of failure, the node will branch directly to the
3005 // FailureLabel
3008 // obj: object to lock
3009 // box: on-stack box address (displaced header location) - KILLED
3010 // rax,: tmp -- KILLED
3011 // scr: tmp -- KILLED
3012 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3014 Register objReg = as_Register($obj$$reg);
3015 Register boxReg = as_Register($box$$reg);
3016 Register tmpReg = as_Register($tmp$$reg);
3017 Register scrReg = as_Register($scr$$reg);
3019 // Ensure the register assignents are disjoint
3020 guarantee (objReg != boxReg, "") ;
3021 guarantee (objReg != tmpReg, "") ;
3022 guarantee (objReg != scrReg, "") ;
3023 guarantee (boxReg != tmpReg, "") ;
3024 guarantee (boxReg != scrReg, "") ;
3025 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3027 MacroAssembler masm(&cbuf);
3029 if (_counters != NULL) {
3030 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3031 }
3032 if (EmitSync & 1) {
3033 // set box->dhw = unused_mark (3)
3034 // Force all sync thru slow-path: slow_enter() and slow_exit()
3035 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3036 masm.cmpptr (rsp, (int32_t)0) ;
3037 } else
3038 if (EmitSync & 2) {
3039 Label DONE_LABEL ;
3040 if (UseBiasedLocking) {
3041 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3042 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3043 }
3045 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3046 masm.orptr (tmpReg, 0x1);
3047 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3048 if (os::is_MP()) { masm.lock(); }
3049 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3050 masm.jcc(Assembler::equal, DONE_LABEL);
3051 // Recursive locking
3052 masm.subptr(tmpReg, rsp);
3053 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3054 masm.movptr(Address(boxReg, 0), tmpReg);
3055 masm.bind(DONE_LABEL) ;
3056 } else {
3057 // Possible cases that we'll encounter in fast_lock
3058 // ------------------------------------------------
3059 // * Inflated
3060 // -- unlocked
3061 // -- Locked
3062 // = by self
3063 // = by other
3064 // * biased
3065 // -- by Self
3066 // -- by other
3067 // * neutral
3068 // * stack-locked
3069 // -- by self
3070 // = sp-proximity test hits
3071 // = sp-proximity test generates false-negative
3072 // -- by other
3073 //
3075 Label IsInflated, DONE_LABEL, PopDone ;
3077 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3078 // order to reduce the number of conditional branches in the most common cases.
3079 // Beware -- there's a subtle invariant that fetch of the markword
3080 // at [FETCH], below, will never observe a biased encoding (*101b).
3081 // If this invariant is not held we risk exclusion (safety) failure.
3082 if (UseBiasedLocking && !UseOptoBiasInlining) {
3083 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3084 }
3086 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3087 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3088 masm.jccb (Assembler::notZero, IsInflated) ;
3090 // Attempt stack-locking ...
3091 masm.orptr (tmpReg, 0x1);
3092 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3093 if (os::is_MP()) { masm.lock(); }
3094 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3095 if (_counters != NULL) {
3096 masm.cond_inc32(Assembler::equal,
3097 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3098 }
3099 masm.jccb (Assembler::equal, DONE_LABEL);
3101 // Recursive locking
3102 masm.subptr(tmpReg, rsp);
3103 masm.andptr(tmpReg, 0xFFFFF003 );
3104 masm.movptr(Address(boxReg, 0), tmpReg);
3105 if (_counters != NULL) {
3106 masm.cond_inc32(Assembler::equal,
3107 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3108 }
3109 masm.jmp (DONE_LABEL) ;
3111 masm.bind (IsInflated) ;
3113 // The object is inflated.
3114 //
3115 // TODO-FIXME: eliminate the ugly use of manifest constants:
3116 // Use markOopDesc::monitor_value instead of "2".
3117 // use markOop::unused_mark() instead of "3".
3118 // The tmpReg value is an objectMonitor reference ORed with
3119 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3120 // objectmonitor pointer by masking off the "2" bit or we can just
3121 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3122 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3123 //
3124 // I use the latter as it avoids AGI stalls.
3125 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3126 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3127 //
3128 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3130 // boxReg refers to the on-stack BasicLock in the current frame.
3131 // We'd like to write:
3132 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3133 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3134 // additional latency as we have another ST in the store buffer that must drain.
3136 if (EmitSync & 8192) {
3137 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3138 masm.get_thread (scrReg) ;
3139 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3140 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3141 if (os::is_MP()) { masm.lock(); }
3142 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3143 } else
3144 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3145 masm.movptr(scrReg, boxReg) ;
3146 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3148 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3149 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3150 // prefetchw [eax + Offset(_owner)-2]
3151 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3152 }
3154 if ((EmitSync & 64) == 0) {
3155 // Optimistic form: consider XORL tmpReg,tmpReg
3156 masm.movptr(tmpReg, NULL_WORD) ;
3157 } else {
3158 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3159 // Test-And-CAS instead of CAS
3160 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3161 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3162 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3163 }
3165 // Appears unlocked - try to swing _owner from null to non-null.
3166 // Ideally, I'd manifest "Self" with get_thread and then attempt
3167 // to CAS the register containing Self into m->Owner.
3168 // But we don't have enough registers, so instead we can either try to CAS
3169 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3170 // we later store "Self" into m->Owner. Transiently storing a stack address
3171 // (rsp or the address of the box) into m->owner is harmless.
3172 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3173 if (os::is_MP()) { masm.lock(); }
3174 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3175 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3176 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3177 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3178 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3179 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3181 // If the CAS fails we can either retry or pass control to the slow-path.
3182 // We use the latter tactic.
3183 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3184 // If the CAS was successful ...
3185 // Self has acquired the lock
3186 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3187 // Intentional fall-through into DONE_LABEL ...
3188 } else {
3189 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3190 masm.movptr(boxReg, tmpReg) ;
3192 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3193 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3194 // prefetchw [eax + Offset(_owner)-2]
3195 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3196 }
3198 if ((EmitSync & 64) == 0) {
3199 // Optimistic form
3200 masm.xorptr (tmpReg, tmpReg) ;
3201 } else {
3202 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3203 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3204 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3205 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3206 }
3208 // Appears unlocked - try to swing _owner from null to non-null.
3209 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3210 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3211 masm.get_thread (scrReg) ;
3212 if (os::is_MP()) { masm.lock(); }
3213 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3215 // If the CAS fails we can either retry or pass control to the slow-path.
3216 // We use the latter tactic.
3217 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3218 // If the CAS was successful ...
3219 // Self has acquired the lock
3220 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3221 // Intentional fall-through into DONE_LABEL ...
3222 }
3224 // DONE_LABEL is a hot target - we'd really like to place it at the
3225 // start of cache line by padding with NOPs.
3226 // See the AMD and Intel software optimization manuals for the
3227 // most efficient "long" NOP encodings.
3228 // Unfortunately none of our alignment mechanisms suffice.
3229 masm.bind(DONE_LABEL);
3231 // Avoid branch-to-branch on AMD processors
3232 // This appears to be superstition.
3233 if (EmitSync & 32) masm.nop() ;
3236 // At DONE_LABEL the icc ZFlag is set as follows ...
3237 // Fast_Unlock uses the same protocol.
3238 // ZFlag == 1 -> Success
3239 // ZFlag == 0 -> Failure - force control through the slow-path
3240 }
3241 %}
3243 // obj: object to unlock
3244 // box: box address (displaced header location), killed. Must be EAX.
3245 // rbx,: killed tmp; cannot be obj nor box.
3246 //
3247 // Some commentary on balanced locking:
3248 //
3249 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3250 // Methods that don't have provably balanced locking are forced to run in the
3251 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3252 // The interpreter provides two properties:
3253 // I1: At return-time the interpreter automatically and quietly unlocks any
3254 // objects acquired the current activation (frame). Recall that the
3255 // interpreter maintains an on-stack list of locks currently held by
3256 // a frame.
3257 // I2: If a method attempts to unlock an object that is not held by the
3258 // the frame the interpreter throws IMSX.
3259 //
3260 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3261 // B() doesn't have provably balanced locking so it runs in the interpreter.
3262 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3263 // is still locked by A().
3264 //
3265 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3266 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3267 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3268 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3270 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3272 Register objReg = as_Register($obj$$reg);
3273 Register boxReg = as_Register($box$$reg);
3274 Register tmpReg = as_Register($tmp$$reg);
3276 guarantee (objReg != boxReg, "") ;
3277 guarantee (objReg != tmpReg, "") ;
3278 guarantee (boxReg != tmpReg, "") ;
3279 guarantee (boxReg == as_Register(EAX_enc), "") ;
3280 MacroAssembler masm(&cbuf);
3282 if (EmitSync & 4) {
3283 // Disable - inhibit all inlining. Force control through the slow-path
3284 masm.cmpptr (rsp, 0) ;
3285 } else
3286 if (EmitSync & 8) {
3287 Label DONE_LABEL ;
3288 if (UseBiasedLocking) {
3289 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3290 }
3291 // classic stack-locking code ...
3292 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3293 masm.testptr(tmpReg, tmpReg) ;
3294 masm.jcc (Assembler::zero, DONE_LABEL) ;
3295 if (os::is_MP()) { masm.lock(); }
3296 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3297 masm.bind(DONE_LABEL);
3298 } else {
3299 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3301 // Critically, the biased locking test must have precedence over
3302 // and appear before the (box->dhw == 0) recursive stack-lock test.
3303 if (UseBiasedLocking && !UseOptoBiasInlining) {
3304 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3305 }
3307 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3308 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3309 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3311 masm.testptr(tmpReg, 0x02) ; // Inflated?
3312 masm.jccb (Assembler::zero, Stacked) ;
3314 masm.bind (Inflated) ;
3315 // It's inflated.
3316 // Despite our balanced locking property we still check that m->_owner == Self
3317 // as java routines or native JNI code called by this thread might
3318 // have released the lock.
3319 // Refer to the comments in synchronizer.cpp for how we might encode extra
3320 // state in _succ so we can avoid fetching EntryList|cxq.
3321 //
3322 // I'd like to add more cases in fast_lock() and fast_unlock() --
3323 // such as recursive enter and exit -- but we have to be wary of
3324 // I$ bloat, T$ effects and BP$ effects.
3325 //
3326 // If there's no contention try a 1-0 exit. That is, exit without
3327 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3328 // we detect and recover from the race that the 1-0 exit admits.
3329 //
3330 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3331 // before it STs null into _owner, releasing the lock. Updates
3332 // to data protected by the critical section must be visible before
3333 // we drop the lock (and thus before any other thread could acquire
3334 // the lock and observe the fields protected by the lock).
3335 // IA32's memory-model is SPO, so STs are ordered with respect to
3336 // each other and there's no need for an explicit barrier (fence).
3337 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3339 masm.get_thread (boxReg) ;
3340 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3341 // prefetchw [ebx + Offset(_owner)-2]
3342 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3343 }
3345 // Note that we could employ various encoding schemes to reduce
3346 // the number of loads below (currently 4) to just 2 or 3.
3347 // Refer to the comments in synchronizer.cpp.
3348 // In practice the chain of fetches doesn't seem to impact performance, however.
3349 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3350 // Attempt to reduce branch density - AMD's branch predictor.
3351 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3352 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3353 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3354 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3355 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3356 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3357 masm.jmpb (DONE_LABEL) ;
3358 } else {
3359 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3360 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3361 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3362 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3363 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3364 masm.jccb (Assembler::notZero, CheckSucc) ;
3365 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3366 masm.jmpb (DONE_LABEL) ;
3367 }
3369 // The Following code fragment (EmitSync & 65536) improves the performance of
3370 // contended applications and contended synchronization microbenchmarks.
3371 // Unfortunately the emission of the code - even though not executed - causes regressions
3372 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3373 // with an equal number of never-executed NOPs results in the same regression.
3374 // We leave it off by default.
3376 if ((EmitSync & 65536) != 0) {
3377 Label LSuccess, LGoSlowPath ;
3379 masm.bind (CheckSucc) ;
3381 // Optional pre-test ... it's safe to elide this
3382 if ((EmitSync & 16) == 0) {
3383 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3384 masm.jccb (Assembler::zero, LGoSlowPath) ;
3385 }
3387 // We have a classic Dekker-style idiom:
3388 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3389 // There are a number of ways to implement the barrier:
3390 // (1) lock:andl &m->_owner, 0
3391 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3392 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3393 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3394 // (2) If supported, an explicit MFENCE is appealing.
3395 // In older IA32 processors MFENCE is slower than lock:add or xchg
3396 // particularly if the write-buffer is full as might be the case if
3397 // if stores closely precede the fence or fence-equivalent instruction.
3398 // In more modern implementations MFENCE appears faster, however.
3399 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3400 // The $lines underlying the top-of-stack should be in M-state.
3401 // The locked add instruction is serializing, of course.
3402 // (4) Use xchg, which is serializing
3403 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3404 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3405 // The integer condition codes will tell us if succ was 0.
3406 // Since _succ and _owner should reside in the same $line and
3407 // we just stored into _owner, it's likely that the $line
3408 // remains in M-state for the lock:orl.
3409 //
3410 // We currently use (3), although it's likely that switching to (2)
3411 // is correct for the future.
3413 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3414 if (os::is_MP()) {
3415 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3416 masm.mfence();
3417 } else {
3418 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3419 }
3420 }
3421 // Ratify _succ remains non-null
3422 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3423 masm.jccb (Assembler::notZero, LSuccess) ;
3425 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3426 if (os::is_MP()) { masm.lock(); }
3427 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3428 masm.jccb (Assembler::notEqual, LSuccess) ;
3429 // Since we're low on registers we installed rsp as a placeholding in _owner.
3430 // Now install Self over rsp. This is safe as we're transitioning from
3431 // non-null to non=null
3432 masm.get_thread (boxReg) ;
3433 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3434 // Intentional fall-through into LGoSlowPath ...
3436 masm.bind (LGoSlowPath) ;
3437 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3438 masm.jmpb (DONE_LABEL) ;
3440 masm.bind (LSuccess) ;
3441 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3442 masm.jmpb (DONE_LABEL) ;
3443 }
3445 masm.bind (Stacked) ;
3446 // It's not inflated and it's not recursively stack-locked and it's not biased.
3447 // It must be stack-locked.
3448 // Try to reset the header to displaced header.
3449 // The "box" value on the stack is stable, so we can reload
3450 // and be assured we observe the same value as above.
3451 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3452 if (os::is_MP()) { masm.lock(); }
3453 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3454 // Intention fall-thru into DONE_LABEL
3457 // DONE_LABEL is a hot target - we'd really like to place it at the
3458 // start of cache line by padding with NOPs.
3459 // See the AMD and Intel software optimization manuals for the
3460 // most efficient "long" NOP encodings.
3461 // Unfortunately none of our alignment mechanisms suffice.
3462 if ((EmitSync & 65536) == 0) {
3463 masm.bind (CheckSucc) ;
3464 }
3465 masm.bind(DONE_LABEL);
3467 // Avoid branch to branch on AMD processors
3468 if (EmitSync & 32768) { masm.nop() ; }
3469 }
3470 %}
3473 enc_class enc_pop_rdx() %{
3474 emit_opcode(cbuf,0x5A);
3475 %}
3477 enc_class enc_rethrow() %{
3478 cbuf.set_insts_mark();
3479 emit_opcode(cbuf, 0xE9); // jmp entry
3480 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3481 runtime_call_Relocation::spec(), RELOC_IMM32 );
3482 %}
3485 // Convert a double to an int. Java semantics require we do complex
3486 // manglelations in the corner cases. So we set the rounding mode to
3487 // 'zero', store the darned double down as an int, and reset the
3488 // rounding mode to 'nearest'. The hardware throws an exception which
3489 // patches up the correct value directly to the stack.
3490 enc_class DPR2I_encoding( regDPR src ) %{
3491 // Flip to round-to-zero mode. We attempted to allow invalid-op
3492 // exceptions here, so that a NAN or other corner-case value will
3493 // thrown an exception (but normal values get converted at full speed).
3494 // However, I2C adapters and other float-stack manglers leave pending
3495 // invalid-op exceptions hanging. We would have to clear them before
3496 // enabling them and that is more expensive than just testing for the
3497 // invalid value Intel stores down in the corner cases.
3498 emit_opcode(cbuf,0xD9); // FLDCW trunc
3499 emit_opcode(cbuf,0x2D);
3500 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3501 // Allocate a word
3502 emit_opcode(cbuf,0x83); // SUB ESP,4
3503 emit_opcode(cbuf,0xEC);
3504 emit_d8(cbuf,0x04);
3505 // Encoding assumes a double has been pushed into FPR0.
3506 // Store down the double as an int, popping the FPU stack
3507 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3508 emit_opcode(cbuf,0x1C);
3509 emit_d8(cbuf,0x24);
3510 // Restore the rounding mode; mask the exception
3511 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3512 emit_opcode(cbuf,0x2D);
3513 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3514 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3515 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3517 // Load the converted int; adjust CPU stack
3518 emit_opcode(cbuf,0x58); // POP EAX
3519 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3520 emit_d32 (cbuf,0x80000000); // 0x80000000
3521 emit_opcode(cbuf,0x75); // JNE around_slow_call
3522 emit_d8 (cbuf,0x07); // Size of slow_call
3523 // Push src onto stack slow-path
3524 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3525 emit_d8 (cbuf,0xC0-1+$src$$reg );
3526 // CALL directly to the runtime
3527 cbuf.set_insts_mark();
3528 emit_opcode(cbuf,0xE8); // Call into runtime
3529 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3530 // Carry on here...
3531 %}
3533 enc_class DPR2L_encoding( regDPR src ) %{
3534 emit_opcode(cbuf,0xD9); // FLDCW trunc
3535 emit_opcode(cbuf,0x2D);
3536 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3537 // Allocate a word
3538 emit_opcode(cbuf,0x83); // SUB ESP,8
3539 emit_opcode(cbuf,0xEC);
3540 emit_d8(cbuf,0x08);
3541 // Encoding assumes a double has been pushed into FPR0.
3542 // Store down the double as a long, popping the FPU stack
3543 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3544 emit_opcode(cbuf,0x3C);
3545 emit_d8(cbuf,0x24);
3546 // Restore the rounding mode; mask the exception
3547 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3548 emit_opcode(cbuf,0x2D);
3549 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3550 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3551 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3553 // Load the converted int; adjust CPU stack
3554 emit_opcode(cbuf,0x58); // POP EAX
3555 emit_opcode(cbuf,0x5A); // POP EDX
3556 emit_opcode(cbuf,0x81); // CMP EDX,imm
3557 emit_d8 (cbuf,0xFA); // rdx
3558 emit_d32 (cbuf,0x80000000); // 0x80000000
3559 emit_opcode(cbuf,0x75); // JNE around_slow_call
3560 emit_d8 (cbuf,0x07+4); // Size of slow_call
3561 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3562 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3563 emit_opcode(cbuf,0x75); // JNE around_slow_call
3564 emit_d8 (cbuf,0x07); // Size of slow_call
3565 // Push src onto stack slow-path
3566 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3567 emit_d8 (cbuf,0xC0-1+$src$$reg );
3568 // CALL directly to the runtime
3569 cbuf.set_insts_mark();
3570 emit_opcode(cbuf,0xE8); // Call into runtime
3571 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3572 // Carry on here...
3573 %}
3575 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3576 // Operand was loaded from memory into fp ST (stack top)
3577 // FMUL ST,$src /* D8 C8+i */
3578 emit_opcode(cbuf, 0xD8);
3579 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3580 %}
3582 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3583 // FADDP ST,src2 /* D8 C0+i */
3584 emit_opcode(cbuf, 0xD8);
3585 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3586 //could use FADDP src2,fpST /* DE C0+i */
3587 %}
3589 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3590 // FADDP src2,ST /* DE C0+i */
3591 emit_opcode(cbuf, 0xDE);
3592 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3593 %}
3595 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3596 // Operand has been loaded into fp ST (stack top)
3597 // FSUB ST,$src1
3598 emit_opcode(cbuf, 0xD8);
3599 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3601 // FDIV
3602 emit_opcode(cbuf, 0xD8);
3603 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3604 %}
3606 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3607 // Operand was loaded from memory into fp ST (stack top)
3608 // FADD ST,$src /* D8 C0+i */
3609 emit_opcode(cbuf, 0xD8);
3610 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3612 // FMUL ST,src2 /* D8 C*+i */
3613 emit_opcode(cbuf, 0xD8);
3614 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3615 %}
3618 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3619 // Operand was loaded from memory into fp ST (stack top)
3620 // FADD ST,$src /* D8 C0+i */
3621 emit_opcode(cbuf, 0xD8);
3622 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3624 // FMULP src2,ST /* DE C8+i */
3625 emit_opcode(cbuf, 0xDE);
3626 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3627 %}
3629 // Atomically load the volatile long
3630 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3631 emit_opcode(cbuf,0xDF);
3632 int rm_byte_opcode = 0x05;
3633 int base = $mem$$base;
3634 int index = $mem$$index;
3635 int scale = $mem$$scale;
3636 int displace = $mem$$disp;
3637 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3638 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3639 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3640 %}
3642 // Volatile Store Long. Must be atomic, so move it into
3643 // the FP TOS and then do a 64-bit FIST. Has to probe the
3644 // target address before the store (for null-ptr checks)
3645 // so the memory operand is used twice in the encoding.
3646 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3647 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3648 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3649 emit_opcode(cbuf,0xDF);
3650 int rm_byte_opcode = 0x07;
3651 int base = $mem$$base;
3652 int index = $mem$$index;
3653 int scale = $mem$$scale;
3654 int displace = $mem$$disp;
3655 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3656 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3657 %}
3659 // Safepoint Poll. This polls the safepoint page, and causes an
3660 // exception if it is not readable. Unfortunately, it kills the condition code
3661 // in the process
3662 // We current use TESTL [spp],EDI
3663 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3665 enc_class Safepoint_Poll() %{
3666 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3667 emit_opcode(cbuf,0x85);
3668 emit_rm (cbuf, 0x0, 0x7, 0x5);
3669 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3670 %}
3671 %}
3674 //----------FRAME--------------------------------------------------------------
3675 // Definition of frame structure and management information.
3676 //
3677 // S T A C K L A Y O U T Allocators stack-slot number
3678 // | (to get allocators register number
3679 // G Owned by | | v add OptoReg::stack0())
3680 // r CALLER | |
3681 // o | +--------+ pad to even-align allocators stack-slot
3682 // w V | pad0 | numbers; owned by CALLER
3683 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3684 // h ^ | in | 5
3685 // | | args | 4 Holes in incoming args owned by SELF
3686 // | | | | 3
3687 // | | +--------+
3688 // V | | old out| Empty on Intel, window on Sparc
3689 // | old |preserve| Must be even aligned.
3690 // | SP-+--------+----> Matcher::_old_SP, even aligned
3691 // | | in | 3 area for Intel ret address
3692 // Owned by |preserve| Empty on Sparc.
3693 // SELF +--------+
3694 // | | pad2 | 2 pad to align old SP
3695 // | +--------+ 1
3696 // | | locks | 0
3697 // | +--------+----> OptoReg::stack0(), even aligned
3698 // | | pad1 | 11 pad to align new SP
3699 // | +--------+
3700 // | | | 10
3701 // | | spills | 9 spills
3702 // V | | 8 (pad0 slot for callee)
3703 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3704 // ^ | out | 7
3705 // | | args | 6 Holes in outgoing args owned by CALLEE
3706 // Owned by +--------+
3707 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3708 // | new |preserve| Must be even-aligned.
3709 // | SP-+--------+----> Matcher::_new_SP, even aligned
3710 // | | |
3711 //
3712 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3713 // known from SELF's arguments and the Java calling convention.
3714 // Region 6-7 is determined per call site.
3715 // Note 2: If the calling convention leaves holes in the incoming argument
3716 // area, those holes are owned by SELF. Holes in the outgoing area
3717 // are owned by the CALLEE. Holes should not be nessecary in the
3718 // incoming area, as the Java calling convention is completely under
3719 // the control of the AD file. Doubles can be sorted and packed to
3720 // avoid holes. Holes in the outgoing arguments may be nessecary for
3721 // varargs C calling conventions.
3722 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3723 // even aligned with pad0 as needed.
3724 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3725 // region 6-11 is even aligned; it may be padded out more so that
3726 // the region from SP to FP meets the minimum stack alignment.
3728 frame %{
3729 // What direction does stack grow in (assumed to be same for C & Java)
3730 stack_direction(TOWARDS_LOW);
3732 // These three registers define part of the calling convention
3733 // between compiled code and the interpreter.
3734 inline_cache_reg(EAX); // Inline Cache Register
3735 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3737 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3738 cisc_spilling_operand_name(indOffset32);
3740 // Number of stack slots consumed by locking an object
3741 sync_stack_slots(1);
3743 // Compiled code's Frame Pointer
3744 frame_pointer(ESP);
3745 // Interpreter stores its frame pointer in a register which is
3746 // stored to the stack by I2CAdaptors.
3747 // I2CAdaptors convert from interpreted java to compiled java.
3748 interpreter_frame_pointer(EBP);
3750 // Stack alignment requirement
3751 // Alignment size in bytes (128-bit -> 16 bytes)
3752 stack_alignment(StackAlignmentInBytes);
3754 // Number of stack slots between incoming argument block and the start of
3755 // a new frame. The PROLOG must add this many slots to the stack. The
3756 // EPILOG must remove this many slots. Intel needs one slot for
3757 // return address and one for rbp, (must save rbp)
3758 in_preserve_stack_slots(2+VerifyStackAtCalls);
3760 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3761 // for calls to C. Supports the var-args backing area for register parms.
3762 varargs_C_out_slots_killed(0);
3764 // The after-PROLOG location of the return address. Location of
3765 // return address specifies a type (REG or STACK) and a number
3766 // representing the register number (i.e. - use a register name) or
3767 // stack slot.
3768 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3769 // Otherwise, it is above the locks and verification slot and alignment word
3770 return_addr(STACK - 1 +
3771 round_to((Compile::current()->in_preserve_stack_slots() +
3772 Compile::current()->fixed_slots()),
3773 stack_alignment_in_slots()));
3775 // Body of function which returns an integer array locating
3776 // arguments either in registers or in stack slots. Passed an array
3777 // of ideal registers called "sig" and a "length" count. Stack-slot
3778 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3779 // arguments for a CALLEE. Incoming stack arguments are
3780 // automatically biased by the preserve_stack_slots field above.
3781 calling_convention %{
3782 // No difference between ingoing/outgoing just pass false
3783 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3784 %}
3787 // Body of function which returns an integer array locating
3788 // arguments either in registers or in stack slots. Passed an array
3789 // of ideal registers called "sig" and a "length" count. Stack-slot
3790 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3791 // arguments for a CALLEE. Incoming stack arguments are
3792 // automatically biased by the preserve_stack_slots field above.
3793 c_calling_convention %{
3794 // This is obviously always outgoing
3795 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3796 %}
3798 // Location of C & interpreter return values
3799 c_return_value %{
3800 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3801 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3802 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3804 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3805 // that C functions return float and double results in XMM0.
3806 if( ideal_reg == Op_RegD && UseSSE>=2 )
3807 return OptoRegPair(XMM0b_num,XMM0_num);
3808 if( ideal_reg == Op_RegF && UseSSE>=2 )
3809 return OptoRegPair(OptoReg::Bad,XMM0_num);
3811 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3812 %}
3814 // Location of return values
3815 return_value %{
3816 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3817 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3818 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3819 if( ideal_reg == Op_RegD && UseSSE>=2 )
3820 return OptoRegPair(XMM0b_num,XMM0_num);
3821 if( ideal_reg == Op_RegF && UseSSE>=1 )
3822 return OptoRegPair(OptoReg::Bad,XMM0_num);
3823 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3824 %}
3826 %}
3828 //----------ATTRIBUTES---------------------------------------------------------
3829 //----------Operand Attributes-------------------------------------------------
3830 op_attrib op_cost(0); // Required cost attribute
3832 //----------Instruction Attributes---------------------------------------------
3833 ins_attrib ins_cost(100); // Required cost attribute
3834 ins_attrib ins_size(8); // Required size attribute (in bits)
3835 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3836 // non-matching short branch variant of some
3837 // long branch?
3838 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3839 // specifies the alignment that some part of the instruction (not
3840 // necessarily the start) requires. If > 1, a compute_padding()
3841 // function must be provided for the instruction
3843 //----------OPERANDS-----------------------------------------------------------
3844 // Operand definitions must precede instruction definitions for correct parsing
3845 // in the ADLC because operands constitute user defined types which are used in
3846 // instruction definitions.
3848 //----------Simple Operands----------------------------------------------------
3849 // Immediate Operands
3850 // Integer Immediate
3851 operand immI() %{
3852 match(ConI);
3854 op_cost(10);
3855 format %{ %}
3856 interface(CONST_INTER);
3857 %}
3859 // Constant for test vs zero
3860 operand immI0() %{
3861 predicate(n->get_int() == 0);
3862 match(ConI);
3864 op_cost(0);
3865 format %{ %}
3866 interface(CONST_INTER);
3867 %}
3869 // Constant for increment
3870 operand immI1() %{
3871 predicate(n->get_int() == 1);
3872 match(ConI);
3874 op_cost(0);
3875 format %{ %}
3876 interface(CONST_INTER);
3877 %}
3879 // Constant for decrement
3880 operand immI_M1() %{
3881 predicate(n->get_int() == -1);
3882 match(ConI);
3884 op_cost(0);
3885 format %{ %}
3886 interface(CONST_INTER);
3887 %}
3889 // Valid scale values for addressing modes
3890 operand immI2() %{
3891 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3892 match(ConI);
3894 format %{ %}
3895 interface(CONST_INTER);
3896 %}
3898 operand immI8() %{
3899 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3900 match(ConI);
3902 op_cost(5);
3903 format %{ %}
3904 interface(CONST_INTER);
3905 %}
3907 operand immI16() %{
3908 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3909 match(ConI);
3911 op_cost(10);
3912 format %{ %}
3913 interface(CONST_INTER);
3914 %}
3916 // Constant for long shifts
3917 operand immI_32() %{
3918 predicate( n->get_int() == 32 );
3919 match(ConI);
3921 op_cost(0);
3922 format %{ %}
3923 interface(CONST_INTER);
3924 %}
3926 operand immI_1_31() %{
3927 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3928 match(ConI);
3930 op_cost(0);
3931 format %{ %}
3932 interface(CONST_INTER);
3933 %}
3935 operand immI_32_63() %{
3936 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3937 match(ConI);
3938 op_cost(0);
3940 format %{ %}
3941 interface(CONST_INTER);
3942 %}
3944 operand immI_1() %{
3945 predicate( n->get_int() == 1 );
3946 match(ConI);
3948 op_cost(0);
3949 format %{ %}
3950 interface(CONST_INTER);
3951 %}
3953 operand immI_2() %{
3954 predicate( n->get_int() == 2 );
3955 match(ConI);
3957 op_cost(0);
3958 format %{ %}
3959 interface(CONST_INTER);
3960 %}
3962 operand immI_3() %{
3963 predicate( n->get_int() == 3 );
3964 match(ConI);
3966 op_cost(0);
3967 format %{ %}
3968 interface(CONST_INTER);
3969 %}
3971 // Pointer Immediate
3972 operand immP() %{
3973 match(ConP);
3975 op_cost(10);
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3980 // NULL Pointer Immediate
3981 operand immP0() %{
3982 predicate( n->get_ptr() == 0 );
3983 match(ConP);
3984 op_cost(0);
3986 format %{ %}
3987 interface(CONST_INTER);
3988 %}
3990 // Long Immediate
3991 operand immL() %{
3992 match(ConL);
3994 op_cost(20);
3995 format %{ %}
3996 interface(CONST_INTER);
3997 %}
3999 // Long Immediate zero
4000 operand immL0() %{
4001 predicate( n->get_long() == 0L );
4002 match(ConL);
4003 op_cost(0);
4005 format %{ %}
4006 interface(CONST_INTER);
4007 %}
4009 // Long Immediate zero
4010 operand immL_M1() %{
4011 predicate( n->get_long() == -1L );
4012 match(ConL);
4013 op_cost(0);
4015 format %{ %}
4016 interface(CONST_INTER);
4017 %}
4019 // Long immediate from 0 to 127.
4020 // Used for a shorter form of long mul by 10.
4021 operand immL_127() %{
4022 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4023 match(ConL);
4024 op_cost(0);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4030 // Long Immediate: low 32-bit mask
4031 operand immL_32bits() %{
4032 predicate(n->get_long() == 0xFFFFFFFFL);
4033 match(ConL);
4034 op_cost(0);
4036 format %{ %}
4037 interface(CONST_INTER);
4038 %}
4040 // Long Immediate: low 32-bit mask
4041 operand immL32() %{
4042 predicate(n->get_long() == (int)(n->get_long()));
4043 match(ConL);
4044 op_cost(20);
4046 format %{ %}
4047 interface(CONST_INTER);
4048 %}
4050 //Double Immediate zero
4051 operand immDPR0() %{
4052 // Do additional (and counter-intuitive) test against NaN to work around VC++
4053 // bug that generates code such that NaNs compare equal to 0.0
4054 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4055 match(ConD);
4057 op_cost(5);
4058 format %{ %}
4059 interface(CONST_INTER);
4060 %}
4062 // Double Immediate one
4063 operand immDPR1() %{
4064 predicate( UseSSE<=1 && n->getd() == 1.0 );
4065 match(ConD);
4067 op_cost(5);
4068 format %{ %}
4069 interface(CONST_INTER);
4070 %}
4072 // Double Immediate
4073 operand immDPR() %{
4074 predicate(UseSSE<=1);
4075 match(ConD);
4077 op_cost(5);
4078 format %{ %}
4079 interface(CONST_INTER);
4080 %}
4082 operand immD() %{
4083 predicate(UseSSE>=2);
4084 match(ConD);
4086 op_cost(5);
4087 format %{ %}
4088 interface(CONST_INTER);
4089 %}
4091 // Double Immediate zero
4092 operand immD0() %{
4093 // Do additional (and counter-intuitive) test against NaN to work around VC++
4094 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4095 // compare equal to -0.0.
4096 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4097 match(ConD);
4099 format %{ %}
4100 interface(CONST_INTER);
4101 %}
4103 // Float Immediate zero
4104 operand immFPR0() %{
4105 predicate(UseSSE == 0 && n->getf() == 0.0F);
4106 match(ConF);
4108 op_cost(5);
4109 format %{ %}
4110 interface(CONST_INTER);
4111 %}
4113 // Float Immediate one
4114 operand immFPR1() %{
4115 predicate(UseSSE == 0 && n->getf() == 1.0F);
4116 match(ConF);
4118 op_cost(5);
4119 format %{ %}
4120 interface(CONST_INTER);
4121 %}
4123 // Float Immediate
4124 operand immFPR() %{
4125 predicate( UseSSE == 0 );
4126 match(ConF);
4128 op_cost(5);
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4133 // Float Immediate
4134 operand immF() %{
4135 predicate(UseSSE >= 1);
4136 match(ConF);
4138 op_cost(5);
4139 format %{ %}
4140 interface(CONST_INTER);
4141 %}
4143 // Float Immediate zero. Zero and not -0.0
4144 operand immF0() %{
4145 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4146 match(ConF);
4148 op_cost(5);
4149 format %{ %}
4150 interface(CONST_INTER);
4151 %}
4153 // Immediates for special shifts (sign extend)
4155 // Constants for increment
4156 operand immI_16() %{
4157 predicate( n->get_int() == 16 );
4158 match(ConI);
4160 format %{ %}
4161 interface(CONST_INTER);
4162 %}
4164 operand immI_24() %{
4165 predicate( n->get_int() == 24 );
4166 match(ConI);
4168 format %{ %}
4169 interface(CONST_INTER);
4170 %}
4172 // Constant for byte-wide masking
4173 operand immI_255() %{
4174 predicate( n->get_int() == 255 );
4175 match(ConI);
4177 format %{ %}
4178 interface(CONST_INTER);
4179 %}
4181 // Constant for short-wide masking
4182 operand immI_65535() %{
4183 predicate(n->get_int() == 65535);
4184 match(ConI);
4186 format %{ %}
4187 interface(CONST_INTER);
4188 %}
4190 // Register Operands
4191 // Integer Register
4192 operand rRegI() %{
4193 constraint(ALLOC_IN_RC(int_reg));
4194 match(RegI);
4195 match(xRegI);
4196 match(eAXRegI);
4197 match(eBXRegI);
4198 match(eCXRegI);
4199 match(eDXRegI);
4200 match(eDIRegI);
4201 match(eSIRegI);
4203 format %{ %}
4204 interface(REG_INTER);
4205 %}
4207 // Subset of Integer Register
4208 operand xRegI(rRegI reg) %{
4209 constraint(ALLOC_IN_RC(int_x_reg));
4210 match(reg);
4211 match(eAXRegI);
4212 match(eBXRegI);
4213 match(eCXRegI);
4214 match(eDXRegI);
4216 format %{ %}
4217 interface(REG_INTER);
4218 %}
4220 // Special Registers
4221 operand eAXRegI(xRegI reg) %{
4222 constraint(ALLOC_IN_RC(eax_reg));
4223 match(reg);
4224 match(rRegI);
4226 format %{ "EAX" %}
4227 interface(REG_INTER);
4228 %}
4230 // Special Registers
4231 operand eBXRegI(xRegI reg) %{
4232 constraint(ALLOC_IN_RC(ebx_reg));
4233 match(reg);
4234 match(rRegI);
4236 format %{ "EBX" %}
4237 interface(REG_INTER);
4238 %}
4240 operand eCXRegI(xRegI reg) %{
4241 constraint(ALLOC_IN_RC(ecx_reg));
4242 match(reg);
4243 match(rRegI);
4245 format %{ "ECX" %}
4246 interface(REG_INTER);
4247 %}
4249 operand eDXRegI(xRegI reg) %{
4250 constraint(ALLOC_IN_RC(edx_reg));
4251 match(reg);
4252 match(rRegI);
4254 format %{ "EDX" %}
4255 interface(REG_INTER);
4256 %}
4258 operand eDIRegI(xRegI reg) %{
4259 constraint(ALLOC_IN_RC(edi_reg));
4260 match(reg);
4261 match(rRegI);
4263 format %{ "EDI" %}
4264 interface(REG_INTER);
4265 %}
4267 operand naxRegI() %{
4268 constraint(ALLOC_IN_RC(nax_reg));
4269 match(RegI);
4270 match(eCXRegI);
4271 match(eDXRegI);
4272 match(eSIRegI);
4273 match(eDIRegI);
4275 format %{ %}
4276 interface(REG_INTER);
4277 %}
4279 operand nadxRegI() %{
4280 constraint(ALLOC_IN_RC(nadx_reg));
4281 match(RegI);
4282 match(eBXRegI);
4283 match(eCXRegI);
4284 match(eSIRegI);
4285 match(eDIRegI);
4287 format %{ %}
4288 interface(REG_INTER);
4289 %}
4291 operand ncxRegI() %{
4292 constraint(ALLOC_IN_RC(ncx_reg));
4293 match(RegI);
4294 match(eAXRegI);
4295 match(eDXRegI);
4296 match(eSIRegI);
4297 match(eDIRegI);
4299 format %{ %}
4300 interface(REG_INTER);
4301 %}
4303 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4304 // //
4305 operand eSIRegI(xRegI reg) %{
4306 constraint(ALLOC_IN_RC(esi_reg));
4307 match(reg);
4308 match(rRegI);
4310 format %{ "ESI" %}
4311 interface(REG_INTER);
4312 %}
4314 // Pointer Register
4315 operand anyRegP() %{
4316 constraint(ALLOC_IN_RC(any_reg));
4317 match(RegP);
4318 match(eAXRegP);
4319 match(eBXRegP);
4320 match(eCXRegP);
4321 match(eDIRegP);
4322 match(eRegP);
4324 format %{ %}
4325 interface(REG_INTER);
4326 %}
4328 operand eRegP() %{
4329 constraint(ALLOC_IN_RC(int_reg));
4330 match(RegP);
4331 match(eAXRegP);
4332 match(eBXRegP);
4333 match(eCXRegP);
4334 match(eDIRegP);
4336 format %{ %}
4337 interface(REG_INTER);
4338 %}
4340 // On windows95, EBP is not safe to use for implicit null tests.
4341 operand eRegP_no_EBP() %{
4342 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4343 match(RegP);
4344 match(eAXRegP);
4345 match(eBXRegP);
4346 match(eCXRegP);
4347 match(eDIRegP);
4349 op_cost(100);
4350 format %{ %}
4351 interface(REG_INTER);
4352 %}
4354 operand naxRegP() %{
4355 constraint(ALLOC_IN_RC(nax_reg));
4356 match(RegP);
4357 match(eBXRegP);
4358 match(eDXRegP);
4359 match(eCXRegP);
4360 match(eSIRegP);
4361 match(eDIRegP);
4363 format %{ %}
4364 interface(REG_INTER);
4365 %}
4367 operand nabxRegP() %{
4368 constraint(ALLOC_IN_RC(nabx_reg));
4369 match(RegP);
4370 match(eCXRegP);
4371 match(eDXRegP);
4372 match(eSIRegP);
4373 match(eDIRegP);
4375 format %{ %}
4376 interface(REG_INTER);
4377 %}
4379 operand pRegP() %{
4380 constraint(ALLOC_IN_RC(p_reg));
4381 match(RegP);
4382 match(eBXRegP);
4383 match(eDXRegP);
4384 match(eSIRegP);
4385 match(eDIRegP);
4387 format %{ %}
4388 interface(REG_INTER);
4389 %}
4391 // Special Registers
4392 // Return a pointer value
4393 operand eAXRegP(eRegP reg) %{
4394 constraint(ALLOC_IN_RC(eax_reg));
4395 match(reg);
4396 format %{ "EAX" %}
4397 interface(REG_INTER);
4398 %}
4400 // Used in AtomicAdd
4401 operand eBXRegP(eRegP reg) %{
4402 constraint(ALLOC_IN_RC(ebx_reg));
4403 match(reg);
4404 format %{ "EBX" %}
4405 interface(REG_INTER);
4406 %}
4408 // Tail-call (interprocedural jump) to interpreter
4409 operand eCXRegP(eRegP reg) %{
4410 constraint(ALLOC_IN_RC(ecx_reg));
4411 match(reg);
4412 format %{ "ECX" %}
4413 interface(REG_INTER);
4414 %}
4416 operand eSIRegP(eRegP reg) %{
4417 constraint(ALLOC_IN_RC(esi_reg));
4418 match(reg);
4419 format %{ "ESI" %}
4420 interface(REG_INTER);
4421 %}
4423 // Used in rep stosw
4424 operand eDIRegP(eRegP reg) %{
4425 constraint(ALLOC_IN_RC(edi_reg));
4426 match(reg);
4427 format %{ "EDI" %}
4428 interface(REG_INTER);
4429 %}
4431 operand eBPRegP() %{
4432 constraint(ALLOC_IN_RC(ebp_reg));
4433 match(RegP);
4434 format %{ "EBP" %}
4435 interface(REG_INTER);
4436 %}
4438 operand eRegL() %{
4439 constraint(ALLOC_IN_RC(long_reg));
4440 match(RegL);
4441 match(eADXRegL);
4443 format %{ %}
4444 interface(REG_INTER);
4445 %}
4447 operand eADXRegL( eRegL reg ) %{
4448 constraint(ALLOC_IN_RC(eadx_reg));
4449 match(reg);
4451 format %{ "EDX:EAX" %}
4452 interface(REG_INTER);
4453 %}
4455 operand eBCXRegL( eRegL reg ) %{
4456 constraint(ALLOC_IN_RC(ebcx_reg));
4457 match(reg);
4459 format %{ "EBX:ECX" %}
4460 interface(REG_INTER);
4461 %}
4463 // Special case for integer high multiply
4464 operand eADXRegL_low_only() %{
4465 constraint(ALLOC_IN_RC(eadx_reg));
4466 match(RegL);
4468 format %{ "EAX" %}
4469 interface(REG_INTER);
4470 %}
4472 // Flags register, used as output of compare instructions
4473 operand eFlagsReg() %{
4474 constraint(ALLOC_IN_RC(int_flags));
4475 match(RegFlags);
4477 format %{ "EFLAGS" %}
4478 interface(REG_INTER);
4479 %}
4481 // Flags register, used as output of FLOATING POINT compare instructions
4482 operand eFlagsRegU() %{
4483 constraint(ALLOC_IN_RC(int_flags));
4484 match(RegFlags);
4486 format %{ "EFLAGS_U" %}
4487 interface(REG_INTER);
4488 %}
4490 operand eFlagsRegUCF() %{
4491 constraint(ALLOC_IN_RC(int_flags));
4492 match(RegFlags);
4493 predicate(false);
4495 format %{ "EFLAGS_U_CF" %}
4496 interface(REG_INTER);
4497 %}
4499 // Condition Code Register used by long compare
4500 operand flagsReg_long_LTGE() %{
4501 constraint(ALLOC_IN_RC(int_flags));
4502 match(RegFlags);
4503 format %{ "FLAGS_LTGE" %}
4504 interface(REG_INTER);
4505 %}
4506 operand flagsReg_long_EQNE() %{
4507 constraint(ALLOC_IN_RC(int_flags));
4508 match(RegFlags);
4509 format %{ "FLAGS_EQNE" %}
4510 interface(REG_INTER);
4511 %}
4512 operand flagsReg_long_LEGT() %{
4513 constraint(ALLOC_IN_RC(int_flags));
4514 match(RegFlags);
4515 format %{ "FLAGS_LEGT" %}
4516 interface(REG_INTER);
4517 %}
4519 // Float register operands
4520 operand regDPR() %{
4521 predicate( UseSSE < 2 );
4522 constraint(ALLOC_IN_RC(fp_dbl_reg));
4523 match(RegD);
4524 match(regDPR1);
4525 match(regDPR2);
4526 format %{ %}
4527 interface(REG_INTER);
4528 %}
4530 operand regDPR1(regDPR reg) %{
4531 predicate( UseSSE < 2 );
4532 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4533 match(reg);
4534 format %{ "FPR1" %}
4535 interface(REG_INTER);
4536 %}
4538 operand regDPR2(regDPR reg) %{
4539 predicate( UseSSE < 2 );
4540 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4541 match(reg);
4542 format %{ "FPR2" %}
4543 interface(REG_INTER);
4544 %}
4546 operand regnotDPR1(regDPR reg) %{
4547 predicate( UseSSE < 2 );
4548 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4549 match(reg);
4550 format %{ %}
4551 interface(REG_INTER);
4552 %}
4554 // Float register operands
4555 operand regFPR() %{
4556 predicate( UseSSE < 2 );
4557 constraint(ALLOC_IN_RC(fp_flt_reg));
4558 match(RegF);
4559 match(regFPR1);
4560 format %{ %}
4561 interface(REG_INTER);
4562 %}
4564 // Float register operands
4565 operand regFPR1(regFPR reg) %{
4566 predicate( UseSSE < 2 );
4567 constraint(ALLOC_IN_RC(fp_flt_reg0));
4568 match(reg);
4569 format %{ "FPR1" %}
4570 interface(REG_INTER);
4571 %}
4573 // XMM Float register operands
4574 operand regF() %{
4575 predicate( UseSSE>=1 );
4576 constraint(ALLOC_IN_RC(float_reg));
4577 match(RegF);
4578 format %{ %}
4579 interface(REG_INTER);
4580 %}
4582 // XMM Double register operands
4583 operand regD() %{
4584 predicate( UseSSE>=2 );
4585 constraint(ALLOC_IN_RC(double_reg));
4586 match(RegD);
4587 format %{ %}
4588 interface(REG_INTER);
4589 %}
4592 //----------Memory Operands----------------------------------------------------
4593 // Direct Memory Operand
4594 operand direct(immP addr) %{
4595 match(addr);
4597 format %{ "[$addr]" %}
4598 interface(MEMORY_INTER) %{
4599 base(0xFFFFFFFF);
4600 index(0x4);
4601 scale(0x0);
4602 disp($addr);
4603 %}
4604 %}
4606 // Indirect Memory Operand
4607 operand indirect(eRegP reg) %{
4608 constraint(ALLOC_IN_RC(int_reg));
4609 match(reg);
4611 format %{ "[$reg]" %}
4612 interface(MEMORY_INTER) %{
4613 base($reg);
4614 index(0x4);
4615 scale(0x0);
4616 disp(0x0);
4617 %}
4618 %}
4620 // Indirect Memory Plus Short Offset Operand
4621 operand indOffset8(eRegP reg, immI8 off) %{
4622 match(AddP reg off);
4624 format %{ "[$reg + $off]" %}
4625 interface(MEMORY_INTER) %{
4626 base($reg);
4627 index(0x4);
4628 scale(0x0);
4629 disp($off);
4630 %}
4631 %}
4633 // Indirect Memory Plus Long Offset Operand
4634 operand indOffset32(eRegP reg, immI off) %{
4635 match(AddP reg off);
4637 format %{ "[$reg + $off]" %}
4638 interface(MEMORY_INTER) %{
4639 base($reg);
4640 index(0x4);
4641 scale(0x0);
4642 disp($off);
4643 %}
4644 %}
4646 // Indirect Memory Plus Long Offset Operand
4647 operand indOffset32X(rRegI reg, immP off) %{
4648 match(AddP off reg);
4650 format %{ "[$reg + $off]" %}
4651 interface(MEMORY_INTER) %{
4652 base($reg);
4653 index(0x4);
4654 scale(0x0);
4655 disp($off);
4656 %}
4657 %}
4659 // Indirect Memory Plus Index Register Plus Offset Operand
4660 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4661 match(AddP (AddP reg ireg) off);
4663 op_cost(10);
4664 format %{"[$reg + $off + $ireg]" %}
4665 interface(MEMORY_INTER) %{
4666 base($reg);
4667 index($ireg);
4668 scale(0x0);
4669 disp($off);
4670 %}
4671 %}
4673 // Indirect Memory Plus Index Register Plus Offset Operand
4674 operand indIndex(eRegP reg, rRegI ireg) %{
4675 match(AddP reg ireg);
4677 op_cost(10);
4678 format %{"[$reg + $ireg]" %}
4679 interface(MEMORY_INTER) %{
4680 base($reg);
4681 index($ireg);
4682 scale(0x0);
4683 disp(0x0);
4684 %}
4685 %}
4687 // // -------------------------------------------------------------------------
4688 // // 486 architecture doesn't support "scale * index + offset" with out a base
4689 // // -------------------------------------------------------------------------
4690 // // Scaled Memory Operands
4691 // // Indirect Memory Times Scale Plus Offset Operand
4692 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4693 // match(AddP off (LShiftI ireg scale));
4694 //
4695 // op_cost(10);
4696 // format %{"[$off + $ireg << $scale]" %}
4697 // interface(MEMORY_INTER) %{
4698 // base(0x4);
4699 // index($ireg);
4700 // scale($scale);
4701 // disp($off);
4702 // %}
4703 // %}
4705 // Indirect Memory Times Scale Plus Index Register
4706 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4707 match(AddP reg (LShiftI ireg scale));
4709 op_cost(10);
4710 format %{"[$reg + $ireg << $scale]" %}
4711 interface(MEMORY_INTER) %{
4712 base($reg);
4713 index($ireg);
4714 scale($scale);
4715 disp(0x0);
4716 %}
4717 %}
4719 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4720 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4721 match(AddP (AddP reg (LShiftI ireg scale)) off);
4723 op_cost(10);
4724 format %{"[$reg + $off + $ireg << $scale]" %}
4725 interface(MEMORY_INTER) %{
4726 base($reg);
4727 index($ireg);
4728 scale($scale);
4729 disp($off);
4730 %}
4731 %}
4733 //----------Load Long Memory Operands------------------------------------------
4734 // The load-long idiom will use it's address expression again after loading
4735 // the first word of the long. If the load-long destination overlaps with
4736 // registers used in the addressing expression, the 2nd half will be loaded
4737 // from a clobbered address. Fix this by requiring that load-long use
4738 // address registers that do not overlap with the load-long target.
4740 // load-long support
4741 operand load_long_RegP() %{
4742 constraint(ALLOC_IN_RC(esi_reg));
4743 match(RegP);
4744 match(eSIRegP);
4745 op_cost(100);
4746 format %{ %}
4747 interface(REG_INTER);
4748 %}
4750 // Indirect Memory Operand Long
4751 operand load_long_indirect(load_long_RegP reg) %{
4752 constraint(ALLOC_IN_RC(esi_reg));
4753 match(reg);
4755 format %{ "[$reg]" %}
4756 interface(MEMORY_INTER) %{
4757 base($reg);
4758 index(0x4);
4759 scale(0x0);
4760 disp(0x0);
4761 %}
4762 %}
4764 // Indirect Memory Plus Long Offset Operand
4765 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4766 match(AddP reg off);
4768 format %{ "[$reg + $off]" %}
4769 interface(MEMORY_INTER) %{
4770 base($reg);
4771 index(0x4);
4772 scale(0x0);
4773 disp($off);
4774 %}
4775 %}
4777 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4780 //----------Special Memory Operands--------------------------------------------
4781 // Stack Slot Operand - This operand is used for loading and storing temporary
4782 // values on the stack where a match requires a value to
4783 // flow through memory.
4784 operand stackSlotP(sRegP reg) %{
4785 constraint(ALLOC_IN_RC(stack_slots));
4786 // No match rule because this operand is only generated in matching
4787 format %{ "[$reg]" %}
4788 interface(MEMORY_INTER) %{
4789 base(0x4); // ESP
4790 index(0x4); // No Index
4791 scale(0x0); // No Scale
4792 disp($reg); // Stack Offset
4793 %}
4794 %}
4796 operand stackSlotI(sRegI reg) %{
4797 constraint(ALLOC_IN_RC(stack_slots));
4798 // No match rule because this operand is only generated in matching
4799 format %{ "[$reg]" %}
4800 interface(MEMORY_INTER) %{
4801 base(0x4); // ESP
4802 index(0x4); // No Index
4803 scale(0x0); // No Scale
4804 disp($reg); // Stack Offset
4805 %}
4806 %}
4808 operand stackSlotF(sRegF reg) %{
4809 constraint(ALLOC_IN_RC(stack_slots));
4810 // No match rule because this operand is only generated in matching
4811 format %{ "[$reg]" %}
4812 interface(MEMORY_INTER) %{
4813 base(0x4); // ESP
4814 index(0x4); // No Index
4815 scale(0x0); // No Scale
4816 disp($reg); // Stack Offset
4817 %}
4818 %}
4820 operand stackSlotD(sRegD reg) %{
4821 constraint(ALLOC_IN_RC(stack_slots));
4822 // No match rule because this operand is only generated in matching
4823 format %{ "[$reg]" %}
4824 interface(MEMORY_INTER) %{
4825 base(0x4); // ESP
4826 index(0x4); // No Index
4827 scale(0x0); // No Scale
4828 disp($reg); // Stack Offset
4829 %}
4830 %}
4832 operand stackSlotL(sRegL reg) %{
4833 constraint(ALLOC_IN_RC(stack_slots));
4834 // No match rule because this operand is only generated in matching
4835 format %{ "[$reg]" %}
4836 interface(MEMORY_INTER) %{
4837 base(0x4); // ESP
4838 index(0x4); // No Index
4839 scale(0x0); // No Scale
4840 disp($reg); // Stack Offset
4841 %}
4842 %}
4844 //----------Memory Operands - Win95 Implicit Null Variants----------------
4845 // Indirect Memory Operand
4846 operand indirect_win95_safe(eRegP_no_EBP reg)
4847 %{
4848 constraint(ALLOC_IN_RC(int_reg));
4849 match(reg);
4851 op_cost(100);
4852 format %{ "[$reg]" %}
4853 interface(MEMORY_INTER) %{
4854 base($reg);
4855 index(0x4);
4856 scale(0x0);
4857 disp(0x0);
4858 %}
4859 %}
4861 // Indirect Memory Plus Short Offset Operand
4862 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4863 %{
4864 match(AddP reg off);
4866 op_cost(100);
4867 format %{ "[$reg + $off]" %}
4868 interface(MEMORY_INTER) %{
4869 base($reg);
4870 index(0x4);
4871 scale(0x0);
4872 disp($off);
4873 %}
4874 %}
4876 // Indirect Memory Plus Long Offset Operand
4877 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4878 %{
4879 match(AddP reg off);
4881 op_cost(100);
4882 format %{ "[$reg + $off]" %}
4883 interface(MEMORY_INTER) %{
4884 base($reg);
4885 index(0x4);
4886 scale(0x0);
4887 disp($off);
4888 %}
4889 %}
4891 // Indirect Memory Plus Index Register Plus Offset Operand
4892 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4893 %{
4894 match(AddP (AddP reg ireg) off);
4896 op_cost(100);
4897 format %{"[$reg + $off + $ireg]" %}
4898 interface(MEMORY_INTER) %{
4899 base($reg);
4900 index($ireg);
4901 scale(0x0);
4902 disp($off);
4903 %}
4904 %}
4906 // Indirect Memory Times Scale Plus Index Register
4907 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4908 %{
4909 match(AddP reg (LShiftI ireg scale));
4911 op_cost(100);
4912 format %{"[$reg + $ireg << $scale]" %}
4913 interface(MEMORY_INTER) %{
4914 base($reg);
4915 index($ireg);
4916 scale($scale);
4917 disp(0x0);
4918 %}
4919 %}
4921 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4922 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4923 %{
4924 match(AddP (AddP reg (LShiftI ireg scale)) off);
4926 op_cost(100);
4927 format %{"[$reg + $off + $ireg << $scale]" %}
4928 interface(MEMORY_INTER) %{
4929 base($reg);
4930 index($ireg);
4931 scale($scale);
4932 disp($off);
4933 %}
4934 %}
4936 //----------Conditional Branch Operands----------------------------------------
4937 // Comparison Op - This is the operation of the comparison, and is limited to
4938 // the following set of codes:
4939 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4940 //
4941 // Other attributes of the comparison, such as unsignedness, are specified
4942 // by the comparison instruction that sets a condition code flags register.
4943 // That result is represented by a flags operand whose subtype is appropriate
4944 // to the unsignedness (etc.) of the comparison.
4945 //
4946 // Later, the instruction which matches both the Comparison Op (a Bool) and
4947 // the flags (produced by the Cmp) specifies the coding of the comparison op
4948 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4950 // Comparision Code
4951 operand cmpOp() %{
4952 match(Bool);
4954 format %{ "" %}
4955 interface(COND_INTER) %{
4956 equal(0x4, "e");
4957 not_equal(0x5, "ne");
4958 less(0xC, "l");
4959 greater_equal(0xD, "ge");
4960 less_equal(0xE, "le");
4961 greater(0xF, "g");
4962 %}
4963 %}
4965 // Comparison Code, unsigned compare. Used by FP also, with
4966 // C2 (unordered) turned into GT or LT already. The other bits
4967 // C0 and C3 are turned into Carry & Zero flags.
4968 operand cmpOpU() %{
4969 match(Bool);
4971 format %{ "" %}
4972 interface(COND_INTER) %{
4973 equal(0x4, "e");
4974 not_equal(0x5, "ne");
4975 less(0x2, "b");
4976 greater_equal(0x3, "nb");
4977 less_equal(0x6, "be");
4978 greater(0x7, "nbe");
4979 %}
4980 %}
4982 // Floating comparisons that don't require any fixup for the unordered case
4983 operand cmpOpUCF() %{
4984 match(Bool);
4985 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4986 n->as_Bool()->_test._test == BoolTest::ge ||
4987 n->as_Bool()->_test._test == BoolTest::le ||
4988 n->as_Bool()->_test._test == BoolTest::gt);
4989 format %{ "" %}
4990 interface(COND_INTER) %{
4991 equal(0x4, "e");
4992 not_equal(0x5, "ne");
4993 less(0x2, "b");
4994 greater_equal(0x3, "nb");
4995 less_equal(0x6, "be");
4996 greater(0x7, "nbe");
4997 %}
4998 %}
5001 // Floating comparisons that can be fixed up with extra conditional jumps
5002 operand cmpOpUCF2() %{
5003 match(Bool);
5004 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5005 n->as_Bool()->_test._test == BoolTest::eq);
5006 format %{ "" %}
5007 interface(COND_INTER) %{
5008 equal(0x4, "e");
5009 not_equal(0x5, "ne");
5010 less(0x2, "b");
5011 greater_equal(0x3, "nb");
5012 less_equal(0x6, "be");
5013 greater(0x7, "nbe");
5014 %}
5015 %}
5017 // Comparison Code for FP conditional move
5018 operand cmpOp_fcmov() %{
5019 match(Bool);
5021 format %{ "" %}
5022 interface(COND_INTER) %{
5023 equal (0x0C8);
5024 not_equal (0x1C8);
5025 less (0x0C0);
5026 greater_equal(0x1C0);
5027 less_equal (0x0D0);
5028 greater (0x1D0);
5029 %}
5030 %}
5032 // Comparision Code used in long compares
5033 operand cmpOp_commute() %{
5034 match(Bool);
5036 format %{ "" %}
5037 interface(COND_INTER) %{
5038 equal(0x4, "e");
5039 not_equal(0x5, "ne");
5040 less(0xF, "g");
5041 greater_equal(0xE, "le");
5042 less_equal(0xD, "ge");
5043 greater(0xC, "l");
5044 %}
5045 %}
5047 //----------OPERAND CLASSES----------------------------------------------------
5048 // Operand Classes are groups of operands that are used as to simplify
5049 // instruction definitions by not requiring the AD writer to specify separate
5050 // instructions for every form of operand when the instruction accepts
5051 // multiple operand types with the same basic encoding and format. The classic
5052 // case of this is memory operands.
5054 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5055 indIndex, indIndexScale, indIndexScaleOffset);
5057 // Long memory operations are encoded in 2 instructions and a +4 offset.
5058 // This means some kind of offset is always required and you cannot use
5059 // an oop as the offset (done when working on static globals).
5060 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5061 indIndex, indIndexScale, indIndexScaleOffset);
5064 //----------PIPELINE-----------------------------------------------------------
5065 // Rules which define the behavior of the target architectures pipeline.
5066 pipeline %{
5068 //----------ATTRIBUTES---------------------------------------------------------
5069 attributes %{
5070 variable_size_instructions; // Fixed size instructions
5071 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5072 instruction_unit_size = 1; // An instruction is 1 bytes long
5073 instruction_fetch_unit_size = 16; // The processor fetches one line
5074 instruction_fetch_units = 1; // of 16 bytes
5076 // List of nop instructions
5077 nops( MachNop );
5078 %}
5080 //----------RESOURCES----------------------------------------------------------
5081 // Resources are the functional units available to the machine
5083 // Generic P2/P3 pipeline
5084 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5085 // 3 instructions decoded per cycle.
5086 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5087 // 2 ALU op, only ALU0 handles mul/div instructions.
5088 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5089 MS0, MS1, MEM = MS0 | MS1,
5090 BR, FPU,
5091 ALU0, ALU1, ALU = ALU0 | ALU1 );
5093 //----------PIPELINE DESCRIPTION-----------------------------------------------
5094 // Pipeline Description specifies the stages in the machine's pipeline
5096 // Generic P2/P3 pipeline
5097 pipe_desc(S0, S1, S2, S3, S4, S5);
5099 //----------PIPELINE CLASSES---------------------------------------------------
5100 // Pipeline Classes describe the stages in which input and output are
5101 // referenced by the hardware pipeline.
5103 // Naming convention: ialu or fpu
5104 // Then: _reg
5105 // Then: _reg if there is a 2nd register
5106 // Then: _long if it's a pair of instructions implementing a long
5107 // Then: _fat if it requires the big decoder
5108 // Or: _mem if it requires the big decoder and a memory unit.
5110 // Integer ALU reg operation
5111 pipe_class ialu_reg(rRegI dst) %{
5112 single_instruction;
5113 dst : S4(write);
5114 dst : S3(read);
5115 DECODE : S0; // any decoder
5116 ALU : S3; // any alu
5117 %}
5119 // Long ALU reg operation
5120 pipe_class ialu_reg_long(eRegL dst) %{
5121 instruction_count(2);
5122 dst : S4(write);
5123 dst : S3(read);
5124 DECODE : S0(2); // any 2 decoders
5125 ALU : S3(2); // both alus
5126 %}
5128 // Integer ALU reg operation using big decoder
5129 pipe_class ialu_reg_fat(rRegI dst) %{
5130 single_instruction;
5131 dst : S4(write);
5132 dst : S3(read);
5133 D0 : S0; // big decoder only
5134 ALU : S3; // any alu
5135 %}
5137 // Long ALU reg operation using big decoder
5138 pipe_class ialu_reg_long_fat(eRegL dst) %{
5139 instruction_count(2);
5140 dst : S4(write);
5141 dst : S3(read);
5142 D0 : S0(2); // big decoder only; twice
5143 ALU : S3(2); // any 2 alus
5144 %}
5146 // Integer ALU reg-reg operation
5147 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5148 single_instruction;
5149 dst : S4(write);
5150 src : S3(read);
5151 DECODE : S0; // any decoder
5152 ALU : S3; // any alu
5153 %}
5155 // Long ALU reg-reg operation
5156 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5157 instruction_count(2);
5158 dst : S4(write);
5159 src : S3(read);
5160 DECODE : S0(2); // any 2 decoders
5161 ALU : S3(2); // both alus
5162 %}
5164 // Integer ALU reg-reg operation
5165 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5166 single_instruction;
5167 dst : S4(write);
5168 src : S3(read);
5169 D0 : S0; // big decoder only
5170 ALU : S3; // any alu
5171 %}
5173 // Long ALU reg-reg operation
5174 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5175 instruction_count(2);
5176 dst : S4(write);
5177 src : S3(read);
5178 D0 : S0(2); // big decoder only; twice
5179 ALU : S3(2); // both alus
5180 %}
5182 // Integer ALU reg-mem operation
5183 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5184 single_instruction;
5185 dst : S5(write);
5186 mem : S3(read);
5187 D0 : S0; // big decoder only
5188 ALU : S4; // any alu
5189 MEM : S3; // any mem
5190 %}
5192 // Long ALU reg-mem operation
5193 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5194 instruction_count(2);
5195 dst : S5(write);
5196 mem : S3(read);
5197 D0 : S0(2); // big decoder only; twice
5198 ALU : S4(2); // any 2 alus
5199 MEM : S3(2); // both mems
5200 %}
5202 // Integer mem operation (prefetch)
5203 pipe_class ialu_mem(memory mem)
5204 %{
5205 single_instruction;
5206 mem : S3(read);
5207 D0 : S0; // big decoder only
5208 MEM : S3; // any mem
5209 %}
5211 // Integer Store to Memory
5212 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5213 single_instruction;
5214 mem : S3(read);
5215 src : S5(read);
5216 D0 : S0; // big decoder only
5217 ALU : S4; // any alu
5218 MEM : S3;
5219 %}
5221 // Long Store to Memory
5222 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5223 instruction_count(2);
5224 mem : S3(read);
5225 src : S5(read);
5226 D0 : S0(2); // big decoder only; twice
5227 ALU : S4(2); // any 2 alus
5228 MEM : S3(2); // Both mems
5229 %}
5231 // Integer Store to Memory
5232 pipe_class ialu_mem_imm(memory mem) %{
5233 single_instruction;
5234 mem : S3(read);
5235 D0 : S0; // big decoder only
5236 ALU : S4; // any alu
5237 MEM : S3;
5238 %}
5240 // Integer ALU0 reg-reg operation
5241 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5242 single_instruction;
5243 dst : S4(write);
5244 src : S3(read);
5245 D0 : S0; // Big decoder only
5246 ALU0 : S3; // only alu0
5247 %}
5249 // Integer ALU0 reg-mem operation
5250 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5251 single_instruction;
5252 dst : S5(write);
5253 mem : S3(read);
5254 D0 : S0; // big decoder only
5255 ALU0 : S4; // ALU0 only
5256 MEM : S3; // any mem
5257 %}
5259 // Integer ALU reg-reg operation
5260 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5261 single_instruction;
5262 cr : S4(write);
5263 src1 : S3(read);
5264 src2 : S3(read);
5265 DECODE : S0; // any decoder
5266 ALU : S3; // any alu
5267 %}
5269 // Integer ALU reg-imm operation
5270 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5271 single_instruction;
5272 cr : S4(write);
5273 src1 : S3(read);
5274 DECODE : S0; // any decoder
5275 ALU : S3; // any alu
5276 %}
5278 // Integer ALU reg-mem operation
5279 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5280 single_instruction;
5281 cr : S4(write);
5282 src1 : S3(read);
5283 src2 : S3(read);
5284 D0 : S0; // big decoder only
5285 ALU : S4; // any alu
5286 MEM : S3;
5287 %}
5289 // Conditional move reg-reg
5290 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5291 instruction_count(4);
5292 y : S4(read);
5293 q : S3(read);
5294 p : S3(read);
5295 DECODE : S0(4); // any decoder
5296 %}
5298 // Conditional move reg-reg
5299 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5300 single_instruction;
5301 dst : S4(write);
5302 src : S3(read);
5303 cr : S3(read);
5304 DECODE : S0; // any decoder
5305 %}
5307 // Conditional move reg-mem
5308 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5309 single_instruction;
5310 dst : S4(write);
5311 src : S3(read);
5312 cr : S3(read);
5313 DECODE : S0; // any decoder
5314 MEM : S3;
5315 %}
5317 // Conditional move reg-reg long
5318 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5319 single_instruction;
5320 dst : S4(write);
5321 src : S3(read);
5322 cr : S3(read);
5323 DECODE : S0(2); // any 2 decoders
5324 %}
5326 // Conditional move double reg-reg
5327 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5328 single_instruction;
5329 dst : S4(write);
5330 src : S3(read);
5331 cr : S3(read);
5332 DECODE : S0; // any decoder
5333 %}
5335 // Float reg-reg operation
5336 pipe_class fpu_reg(regDPR dst) %{
5337 instruction_count(2);
5338 dst : S3(read);
5339 DECODE : S0(2); // any 2 decoders
5340 FPU : S3;
5341 %}
5343 // Float reg-reg operation
5344 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5345 instruction_count(2);
5346 dst : S4(write);
5347 src : S3(read);
5348 DECODE : S0(2); // any 2 decoders
5349 FPU : S3;
5350 %}
5352 // Float reg-reg operation
5353 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5354 instruction_count(3);
5355 dst : S4(write);
5356 src1 : S3(read);
5357 src2 : S3(read);
5358 DECODE : S0(3); // any 3 decoders
5359 FPU : S3(2);
5360 %}
5362 // Float reg-reg operation
5363 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5364 instruction_count(4);
5365 dst : S4(write);
5366 src1 : S3(read);
5367 src2 : S3(read);
5368 src3 : S3(read);
5369 DECODE : S0(4); // any 3 decoders
5370 FPU : S3(2);
5371 %}
5373 // Float reg-reg operation
5374 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5375 instruction_count(4);
5376 dst : S4(write);
5377 src1 : S3(read);
5378 src2 : S3(read);
5379 src3 : S3(read);
5380 DECODE : S1(3); // any 3 decoders
5381 D0 : S0; // Big decoder only
5382 FPU : S3(2);
5383 MEM : S3;
5384 %}
5386 // Float reg-mem operation
5387 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5388 instruction_count(2);
5389 dst : S5(write);
5390 mem : S3(read);
5391 D0 : S0; // big decoder only
5392 DECODE : S1; // any decoder for FPU POP
5393 FPU : S4;
5394 MEM : S3; // any mem
5395 %}
5397 // Float reg-mem operation
5398 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5399 instruction_count(3);
5400 dst : S5(write);
5401 src1 : S3(read);
5402 mem : S3(read);
5403 D0 : S0; // big decoder only
5404 DECODE : S1(2); // any decoder for FPU POP
5405 FPU : S4;
5406 MEM : S3; // any mem
5407 %}
5409 // Float mem-reg operation
5410 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5411 instruction_count(2);
5412 src : S5(read);
5413 mem : S3(read);
5414 DECODE : S0; // any decoder for FPU PUSH
5415 D0 : S1; // big decoder only
5416 FPU : S4;
5417 MEM : S3; // any mem
5418 %}
5420 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5421 instruction_count(3);
5422 src1 : S3(read);
5423 src2 : S3(read);
5424 mem : S3(read);
5425 DECODE : S0(2); // any decoder for FPU PUSH
5426 D0 : S1; // big decoder only
5427 FPU : S4;
5428 MEM : S3; // any mem
5429 %}
5431 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5432 instruction_count(3);
5433 src1 : S3(read);
5434 src2 : S3(read);
5435 mem : S4(read);
5436 DECODE : S0; // any decoder for FPU PUSH
5437 D0 : S0(2); // big decoder only
5438 FPU : S4;
5439 MEM : S3(2); // any mem
5440 %}
5442 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5443 instruction_count(2);
5444 src1 : S3(read);
5445 dst : S4(read);
5446 D0 : S0(2); // big decoder only
5447 MEM : S3(2); // any mem
5448 %}
5450 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5451 instruction_count(3);
5452 src1 : S3(read);
5453 src2 : S3(read);
5454 dst : S4(read);
5455 D0 : S0(3); // big decoder only
5456 FPU : S4;
5457 MEM : S3(3); // any mem
5458 %}
5460 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5461 instruction_count(3);
5462 src1 : S4(read);
5463 mem : S4(read);
5464 DECODE : S0; // any decoder for FPU PUSH
5465 D0 : S0(2); // big decoder only
5466 FPU : S4;
5467 MEM : S3(2); // any mem
5468 %}
5470 // Float load constant
5471 pipe_class fpu_reg_con(regDPR dst) %{
5472 instruction_count(2);
5473 dst : S5(write);
5474 D0 : S0; // big decoder only for the load
5475 DECODE : S1; // any decoder for FPU POP
5476 FPU : S4;
5477 MEM : S3; // any mem
5478 %}
5480 // Float load constant
5481 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5482 instruction_count(3);
5483 dst : S5(write);
5484 src : S3(read);
5485 D0 : S0; // big decoder only for the load
5486 DECODE : S1(2); // any decoder for FPU POP
5487 FPU : S4;
5488 MEM : S3; // any mem
5489 %}
5491 // UnConditional branch
5492 pipe_class pipe_jmp( label labl ) %{
5493 single_instruction;
5494 BR : S3;
5495 %}
5497 // Conditional branch
5498 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5499 single_instruction;
5500 cr : S1(read);
5501 BR : S3;
5502 %}
5504 // Allocation idiom
5505 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5506 instruction_count(1); force_serialization;
5507 fixed_latency(6);
5508 heap_ptr : S3(read);
5509 DECODE : S0(3);
5510 D0 : S2;
5511 MEM : S3;
5512 ALU : S3(2);
5513 dst : S5(write);
5514 BR : S5;
5515 %}
5517 // Generic big/slow expanded idiom
5518 pipe_class pipe_slow( ) %{
5519 instruction_count(10); multiple_bundles; force_serialization;
5520 fixed_latency(100);
5521 D0 : S0(2);
5522 MEM : S3(2);
5523 %}
5525 // The real do-nothing guy
5526 pipe_class empty( ) %{
5527 instruction_count(0);
5528 %}
5530 // Define the class for the Nop node
5531 define %{
5532 MachNop = empty;
5533 %}
5535 %}
5537 //----------INSTRUCTIONS-------------------------------------------------------
5538 //
5539 // match -- States which machine-independent subtree may be replaced
5540 // by this instruction.
5541 // ins_cost -- The estimated cost of this instruction is used by instruction
5542 // selection to identify a minimum cost tree of machine
5543 // instructions that matches a tree of machine-independent
5544 // instructions.
5545 // format -- A string providing the disassembly for this instruction.
5546 // The value of an instruction's operand may be inserted
5547 // by referring to it with a '$' prefix.
5548 // opcode -- Three instruction opcodes may be provided. These are referred
5549 // to within an encode class as $primary, $secondary, and $tertiary
5550 // respectively. The primary opcode is commonly used to
5551 // indicate the type of machine instruction, while secondary
5552 // and tertiary are often used for prefix options or addressing
5553 // modes.
5554 // ins_encode -- A list of encode classes with parameters. The encode class
5555 // name must have been defined in an 'enc_class' specification
5556 // in the encode section of the architecture description.
5558 //----------BSWAP-Instruction--------------------------------------------------
5559 instruct bytes_reverse_int(rRegI dst) %{
5560 match(Set dst (ReverseBytesI dst));
5562 format %{ "BSWAP $dst" %}
5563 opcode(0x0F, 0xC8);
5564 ins_encode( OpcP, OpcSReg(dst) );
5565 ins_pipe( ialu_reg );
5566 %}
5568 instruct bytes_reverse_long(eRegL dst) %{
5569 match(Set dst (ReverseBytesL dst));
5571 format %{ "BSWAP $dst.lo\n\t"
5572 "BSWAP $dst.hi\n\t"
5573 "XCHG $dst.lo $dst.hi" %}
5575 ins_cost(125);
5576 ins_encode( bswap_long_bytes(dst) );
5577 ins_pipe( ialu_reg_reg);
5578 %}
5580 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5581 match(Set dst (ReverseBytesUS dst));
5582 effect(KILL cr);
5584 format %{ "BSWAP $dst\n\t"
5585 "SHR $dst,16\n\t" %}
5586 ins_encode %{
5587 __ bswapl($dst$$Register);
5588 __ shrl($dst$$Register, 16);
5589 %}
5590 ins_pipe( ialu_reg );
5591 %}
5593 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5594 match(Set dst (ReverseBytesS dst));
5595 effect(KILL cr);
5597 format %{ "BSWAP $dst\n\t"
5598 "SAR $dst,16\n\t" %}
5599 ins_encode %{
5600 __ bswapl($dst$$Register);
5601 __ sarl($dst$$Register, 16);
5602 %}
5603 ins_pipe( ialu_reg );
5604 %}
5607 //---------- Zeros Count Instructions ------------------------------------------
5609 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5610 predicate(UseCountLeadingZerosInstruction);
5611 match(Set dst (CountLeadingZerosI src));
5612 effect(KILL cr);
5614 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5615 ins_encode %{
5616 __ lzcntl($dst$$Register, $src$$Register);
5617 %}
5618 ins_pipe(ialu_reg);
5619 %}
5621 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5622 predicate(!UseCountLeadingZerosInstruction);
5623 match(Set dst (CountLeadingZerosI src));
5624 effect(KILL cr);
5626 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5627 "JNZ skip\n\t"
5628 "MOV $dst, -1\n"
5629 "skip:\n\t"
5630 "NEG $dst\n\t"
5631 "ADD $dst, 31" %}
5632 ins_encode %{
5633 Register Rdst = $dst$$Register;
5634 Register Rsrc = $src$$Register;
5635 Label skip;
5636 __ bsrl(Rdst, Rsrc);
5637 __ jccb(Assembler::notZero, skip);
5638 __ movl(Rdst, -1);
5639 __ bind(skip);
5640 __ negl(Rdst);
5641 __ addl(Rdst, BitsPerInt - 1);
5642 %}
5643 ins_pipe(ialu_reg);
5644 %}
5646 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5647 predicate(UseCountLeadingZerosInstruction);
5648 match(Set dst (CountLeadingZerosL src));
5649 effect(TEMP dst, KILL cr);
5651 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5652 "JNC done\n\t"
5653 "LZCNT $dst, $src.lo\n\t"
5654 "ADD $dst, 32\n"
5655 "done:" %}
5656 ins_encode %{
5657 Register Rdst = $dst$$Register;
5658 Register Rsrc = $src$$Register;
5659 Label done;
5660 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5661 __ jccb(Assembler::carryClear, done);
5662 __ lzcntl(Rdst, Rsrc);
5663 __ addl(Rdst, BitsPerInt);
5664 __ bind(done);
5665 %}
5666 ins_pipe(ialu_reg);
5667 %}
5669 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5670 predicate(!UseCountLeadingZerosInstruction);
5671 match(Set dst (CountLeadingZerosL src));
5672 effect(TEMP dst, KILL cr);
5674 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5675 "JZ msw_is_zero\n\t"
5676 "ADD $dst, 32\n\t"
5677 "JMP not_zero\n"
5678 "msw_is_zero:\n\t"
5679 "BSR $dst, $src.lo\n\t"
5680 "JNZ not_zero\n\t"
5681 "MOV $dst, -1\n"
5682 "not_zero:\n\t"
5683 "NEG $dst\n\t"
5684 "ADD $dst, 63\n" %}
5685 ins_encode %{
5686 Register Rdst = $dst$$Register;
5687 Register Rsrc = $src$$Register;
5688 Label msw_is_zero;
5689 Label not_zero;
5690 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5691 __ jccb(Assembler::zero, msw_is_zero);
5692 __ addl(Rdst, BitsPerInt);
5693 __ jmpb(not_zero);
5694 __ bind(msw_is_zero);
5695 __ bsrl(Rdst, Rsrc);
5696 __ jccb(Assembler::notZero, not_zero);
5697 __ movl(Rdst, -1);
5698 __ bind(not_zero);
5699 __ negl(Rdst);
5700 __ addl(Rdst, BitsPerLong - 1);
5701 %}
5702 ins_pipe(ialu_reg);
5703 %}
5705 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5706 match(Set dst (CountTrailingZerosI src));
5707 effect(KILL cr);
5709 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5710 "JNZ done\n\t"
5711 "MOV $dst, 32\n"
5712 "done:" %}
5713 ins_encode %{
5714 Register Rdst = $dst$$Register;
5715 Label done;
5716 __ bsfl(Rdst, $src$$Register);
5717 __ jccb(Assembler::notZero, done);
5718 __ movl(Rdst, BitsPerInt);
5719 __ bind(done);
5720 %}
5721 ins_pipe(ialu_reg);
5722 %}
5724 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5725 match(Set dst (CountTrailingZerosL src));
5726 effect(TEMP dst, KILL cr);
5728 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5729 "JNZ done\n\t"
5730 "BSF $dst, $src.hi\n\t"
5731 "JNZ msw_not_zero\n\t"
5732 "MOV $dst, 32\n"
5733 "msw_not_zero:\n\t"
5734 "ADD $dst, 32\n"
5735 "done:" %}
5736 ins_encode %{
5737 Register Rdst = $dst$$Register;
5738 Register Rsrc = $src$$Register;
5739 Label msw_not_zero;
5740 Label done;
5741 __ bsfl(Rdst, Rsrc);
5742 __ jccb(Assembler::notZero, done);
5743 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5744 __ jccb(Assembler::notZero, msw_not_zero);
5745 __ movl(Rdst, BitsPerInt);
5746 __ bind(msw_not_zero);
5747 __ addl(Rdst, BitsPerInt);
5748 __ bind(done);
5749 %}
5750 ins_pipe(ialu_reg);
5751 %}
5754 //---------- Population Count Instructions -------------------------------------
5756 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5757 predicate(UsePopCountInstruction);
5758 match(Set dst (PopCountI src));
5759 effect(KILL cr);
5761 format %{ "POPCNT $dst, $src" %}
5762 ins_encode %{
5763 __ popcntl($dst$$Register, $src$$Register);
5764 %}
5765 ins_pipe(ialu_reg);
5766 %}
5768 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5769 predicate(UsePopCountInstruction);
5770 match(Set dst (PopCountI (LoadI mem)));
5771 effect(KILL cr);
5773 format %{ "POPCNT $dst, $mem" %}
5774 ins_encode %{
5775 __ popcntl($dst$$Register, $mem$$Address);
5776 %}
5777 ins_pipe(ialu_reg);
5778 %}
5780 // Note: Long.bitCount(long) returns an int.
5781 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5782 predicate(UsePopCountInstruction);
5783 match(Set dst (PopCountL src));
5784 effect(KILL cr, TEMP tmp, TEMP dst);
5786 format %{ "POPCNT $dst, $src.lo\n\t"
5787 "POPCNT $tmp, $src.hi\n\t"
5788 "ADD $dst, $tmp" %}
5789 ins_encode %{
5790 __ popcntl($dst$$Register, $src$$Register);
5791 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5792 __ addl($dst$$Register, $tmp$$Register);
5793 %}
5794 ins_pipe(ialu_reg);
5795 %}
5797 // Note: Long.bitCount(long) returns an int.
5798 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5799 predicate(UsePopCountInstruction);
5800 match(Set dst (PopCountL (LoadL mem)));
5801 effect(KILL cr, TEMP tmp, TEMP dst);
5803 format %{ "POPCNT $dst, $mem\n\t"
5804 "POPCNT $tmp, $mem+4\n\t"
5805 "ADD $dst, $tmp" %}
5806 ins_encode %{
5807 //__ popcntl($dst$$Register, $mem$$Address$$first);
5808 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5809 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5810 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5811 __ addl($dst$$Register, $tmp$$Register);
5812 %}
5813 ins_pipe(ialu_reg);
5814 %}
5817 //----------Load/Store/Move Instructions---------------------------------------
5818 //----------Load Instructions--------------------------------------------------
5819 // Load Byte (8bit signed)
5820 instruct loadB(xRegI dst, memory mem) %{
5821 match(Set dst (LoadB mem));
5823 ins_cost(125);
5824 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5826 ins_encode %{
5827 __ movsbl($dst$$Register, $mem$$Address);
5828 %}
5830 ins_pipe(ialu_reg_mem);
5831 %}
5833 // Load Byte (8bit signed) into Long Register
5834 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5835 match(Set dst (ConvI2L (LoadB mem)));
5836 effect(KILL cr);
5838 ins_cost(375);
5839 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5840 "MOV $dst.hi,$dst.lo\n\t"
5841 "SAR $dst.hi,7" %}
5843 ins_encode %{
5844 __ movsbl($dst$$Register, $mem$$Address);
5845 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5846 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5847 %}
5849 ins_pipe(ialu_reg_mem);
5850 %}
5852 // Load Unsigned Byte (8bit UNsigned)
5853 instruct loadUB(xRegI dst, memory mem) %{
5854 match(Set dst (LoadUB mem));
5856 ins_cost(125);
5857 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5859 ins_encode %{
5860 __ movzbl($dst$$Register, $mem$$Address);
5861 %}
5863 ins_pipe(ialu_reg_mem);
5864 %}
5866 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5867 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5868 match(Set dst (ConvI2L (LoadUB mem)));
5869 effect(KILL cr);
5871 ins_cost(250);
5872 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5873 "XOR $dst.hi,$dst.hi" %}
5875 ins_encode %{
5876 Register Rdst = $dst$$Register;
5877 __ movzbl(Rdst, $mem$$Address);
5878 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5879 %}
5881 ins_pipe(ialu_reg_mem);
5882 %}
5884 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5885 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5886 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5887 effect(KILL cr);
5889 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5890 "XOR $dst.hi,$dst.hi\n\t"
5891 "AND $dst.lo,$mask" %}
5892 ins_encode %{
5893 Register Rdst = $dst$$Register;
5894 __ movzbl(Rdst, $mem$$Address);
5895 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5896 __ andl(Rdst, $mask$$constant);
5897 %}
5898 ins_pipe(ialu_reg_mem);
5899 %}
5901 // Load Short (16bit signed)
5902 instruct loadS(rRegI dst, memory mem) %{
5903 match(Set dst (LoadS mem));
5905 ins_cost(125);
5906 format %{ "MOVSX $dst,$mem\t# short" %}
5908 ins_encode %{
5909 __ movswl($dst$$Register, $mem$$Address);
5910 %}
5912 ins_pipe(ialu_reg_mem);
5913 %}
5915 // Load Short (16 bit signed) to Byte (8 bit signed)
5916 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5917 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5919 ins_cost(125);
5920 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5921 ins_encode %{
5922 __ movsbl($dst$$Register, $mem$$Address);
5923 %}
5924 ins_pipe(ialu_reg_mem);
5925 %}
5927 // Load Short (16bit signed) into Long Register
5928 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5929 match(Set dst (ConvI2L (LoadS mem)));
5930 effect(KILL cr);
5932 ins_cost(375);
5933 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5934 "MOV $dst.hi,$dst.lo\n\t"
5935 "SAR $dst.hi,15" %}
5937 ins_encode %{
5938 __ movswl($dst$$Register, $mem$$Address);
5939 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5940 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5941 %}
5943 ins_pipe(ialu_reg_mem);
5944 %}
5946 // Load Unsigned Short/Char (16bit unsigned)
5947 instruct loadUS(rRegI dst, memory mem) %{
5948 match(Set dst (LoadUS mem));
5950 ins_cost(125);
5951 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5953 ins_encode %{
5954 __ movzwl($dst$$Register, $mem$$Address);
5955 %}
5957 ins_pipe(ialu_reg_mem);
5958 %}
5960 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5961 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5962 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5964 ins_cost(125);
5965 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5966 ins_encode %{
5967 __ movsbl($dst$$Register, $mem$$Address);
5968 %}
5969 ins_pipe(ialu_reg_mem);
5970 %}
5972 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5973 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5974 match(Set dst (ConvI2L (LoadUS mem)));
5975 effect(KILL cr);
5977 ins_cost(250);
5978 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5979 "XOR $dst.hi,$dst.hi" %}
5981 ins_encode %{
5982 __ movzwl($dst$$Register, $mem$$Address);
5983 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5984 %}
5986 ins_pipe(ialu_reg_mem);
5987 %}
5989 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5990 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5991 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5992 effect(KILL cr);
5994 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5995 "XOR $dst.hi,$dst.hi" %}
5996 ins_encode %{
5997 Register Rdst = $dst$$Register;
5998 __ movzbl(Rdst, $mem$$Address);
5999 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6000 %}
6001 ins_pipe(ialu_reg_mem);
6002 %}
6004 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6005 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6006 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6007 effect(KILL cr);
6009 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6010 "XOR $dst.hi,$dst.hi\n\t"
6011 "AND $dst.lo,$mask" %}
6012 ins_encode %{
6013 Register Rdst = $dst$$Register;
6014 __ movzwl(Rdst, $mem$$Address);
6015 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6016 __ andl(Rdst, $mask$$constant);
6017 %}
6018 ins_pipe(ialu_reg_mem);
6019 %}
6021 // Load Integer
6022 instruct loadI(rRegI dst, memory mem) %{
6023 match(Set dst (LoadI mem));
6025 ins_cost(125);
6026 format %{ "MOV $dst,$mem\t# int" %}
6028 ins_encode %{
6029 __ movl($dst$$Register, $mem$$Address);
6030 %}
6032 ins_pipe(ialu_reg_mem);
6033 %}
6035 // Load Integer (32 bit signed) to Byte (8 bit signed)
6036 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6037 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6039 ins_cost(125);
6040 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6041 ins_encode %{
6042 __ movsbl($dst$$Register, $mem$$Address);
6043 %}
6044 ins_pipe(ialu_reg_mem);
6045 %}
6047 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6048 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6049 match(Set dst (AndI (LoadI mem) mask));
6051 ins_cost(125);
6052 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6053 ins_encode %{
6054 __ movzbl($dst$$Register, $mem$$Address);
6055 %}
6056 ins_pipe(ialu_reg_mem);
6057 %}
6059 // Load Integer (32 bit signed) to Short (16 bit signed)
6060 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6061 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6063 ins_cost(125);
6064 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6065 ins_encode %{
6066 __ movswl($dst$$Register, $mem$$Address);
6067 %}
6068 ins_pipe(ialu_reg_mem);
6069 %}
6071 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6072 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6073 match(Set dst (AndI (LoadI mem) mask));
6075 ins_cost(125);
6076 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6077 ins_encode %{
6078 __ movzwl($dst$$Register, $mem$$Address);
6079 %}
6080 ins_pipe(ialu_reg_mem);
6081 %}
6083 // Load Integer into Long Register
6084 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6085 match(Set dst (ConvI2L (LoadI mem)));
6086 effect(KILL cr);
6088 ins_cost(375);
6089 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6090 "MOV $dst.hi,$dst.lo\n\t"
6091 "SAR $dst.hi,31" %}
6093 ins_encode %{
6094 __ movl($dst$$Register, $mem$$Address);
6095 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6096 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6097 %}
6099 ins_pipe(ialu_reg_mem);
6100 %}
6102 // Load Integer with mask 0xFF into Long Register
6103 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6104 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6105 effect(KILL cr);
6107 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6108 "XOR $dst.hi,$dst.hi" %}
6109 ins_encode %{
6110 Register Rdst = $dst$$Register;
6111 __ movzbl(Rdst, $mem$$Address);
6112 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6113 %}
6114 ins_pipe(ialu_reg_mem);
6115 %}
6117 // Load Integer with mask 0xFFFF into Long Register
6118 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6119 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6120 effect(KILL cr);
6122 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6123 "XOR $dst.hi,$dst.hi" %}
6124 ins_encode %{
6125 Register Rdst = $dst$$Register;
6126 __ movzwl(Rdst, $mem$$Address);
6127 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6128 %}
6129 ins_pipe(ialu_reg_mem);
6130 %}
6132 // Load Integer with 32-bit mask into Long Register
6133 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6134 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6135 effect(KILL cr);
6137 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6138 "XOR $dst.hi,$dst.hi\n\t"
6139 "AND $dst.lo,$mask" %}
6140 ins_encode %{
6141 Register Rdst = $dst$$Register;
6142 __ movl(Rdst, $mem$$Address);
6143 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6144 __ andl(Rdst, $mask$$constant);
6145 %}
6146 ins_pipe(ialu_reg_mem);
6147 %}
6149 // Load Unsigned Integer into Long Register
6150 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6151 match(Set dst (LoadUI2L mem));
6152 effect(KILL cr);
6154 ins_cost(250);
6155 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6156 "XOR $dst.hi,$dst.hi" %}
6158 ins_encode %{
6159 __ movl($dst$$Register, $mem$$Address);
6160 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6161 %}
6163 ins_pipe(ialu_reg_mem);
6164 %}
6166 // Load Long. Cannot clobber address while loading, so restrict address
6167 // register to ESI
6168 instruct loadL(eRegL dst, load_long_memory mem) %{
6169 predicate(!((LoadLNode*)n)->require_atomic_access());
6170 match(Set dst (LoadL mem));
6172 ins_cost(250);
6173 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6174 "MOV $dst.hi,$mem+4" %}
6176 ins_encode %{
6177 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6178 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6179 __ movl($dst$$Register, Amemlo);
6180 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6181 %}
6183 ins_pipe(ialu_reg_long_mem);
6184 %}
6186 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6187 // then store it down to the stack and reload on the int
6188 // side.
6189 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6190 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6191 match(Set dst (LoadL mem));
6193 ins_cost(200);
6194 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6195 "FISTp $dst" %}
6196 ins_encode(enc_loadL_volatile(mem,dst));
6197 ins_pipe( fpu_reg_mem );
6198 %}
6200 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6201 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6202 match(Set dst (LoadL mem));
6203 effect(TEMP tmp);
6204 ins_cost(180);
6205 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6206 "MOVSD $dst,$tmp" %}
6207 ins_encode %{
6208 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6209 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6210 %}
6211 ins_pipe( pipe_slow );
6212 %}
6214 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6215 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6216 match(Set dst (LoadL mem));
6217 effect(TEMP tmp);
6218 ins_cost(160);
6219 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6220 "MOVD $dst.lo,$tmp\n\t"
6221 "PSRLQ $tmp,32\n\t"
6222 "MOVD $dst.hi,$tmp" %}
6223 ins_encode %{
6224 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6225 __ movdl($dst$$Register, $tmp$$XMMRegister);
6226 __ psrlq($tmp$$XMMRegister, 32);
6227 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6228 %}
6229 ins_pipe( pipe_slow );
6230 %}
6232 // Load Range
6233 instruct loadRange(rRegI dst, memory mem) %{
6234 match(Set dst (LoadRange mem));
6236 ins_cost(125);
6237 format %{ "MOV $dst,$mem" %}
6238 opcode(0x8B);
6239 ins_encode( OpcP, RegMem(dst,mem));
6240 ins_pipe( ialu_reg_mem );
6241 %}
6244 // Load Pointer
6245 instruct loadP(eRegP dst, memory mem) %{
6246 match(Set dst (LoadP mem));
6248 ins_cost(125);
6249 format %{ "MOV $dst,$mem" %}
6250 opcode(0x8B);
6251 ins_encode( OpcP, RegMem(dst,mem));
6252 ins_pipe( ialu_reg_mem );
6253 %}
6255 // Load Klass Pointer
6256 instruct loadKlass(eRegP dst, memory mem) %{
6257 match(Set dst (LoadKlass mem));
6259 ins_cost(125);
6260 format %{ "MOV $dst,$mem" %}
6261 opcode(0x8B);
6262 ins_encode( OpcP, RegMem(dst,mem));
6263 ins_pipe( ialu_reg_mem );
6264 %}
6266 // Load Double
6267 instruct loadDPR(regDPR dst, memory mem) %{
6268 predicate(UseSSE<=1);
6269 match(Set dst (LoadD mem));
6271 ins_cost(150);
6272 format %{ "FLD_D ST,$mem\n\t"
6273 "FSTP $dst" %}
6274 opcode(0xDD); /* DD /0 */
6275 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6276 Pop_Reg_DPR(dst) );
6277 ins_pipe( fpu_reg_mem );
6278 %}
6280 // Load Double to XMM
6281 instruct loadD(regD dst, memory mem) %{
6282 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6283 match(Set dst (LoadD mem));
6284 ins_cost(145);
6285 format %{ "MOVSD $dst,$mem" %}
6286 ins_encode %{
6287 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6288 %}
6289 ins_pipe( pipe_slow );
6290 %}
6292 instruct loadD_partial(regD dst, memory mem) %{
6293 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6294 match(Set dst (LoadD mem));
6295 ins_cost(145);
6296 format %{ "MOVLPD $dst,$mem" %}
6297 ins_encode %{
6298 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6299 %}
6300 ins_pipe( pipe_slow );
6301 %}
6303 // Load to XMM register (single-precision floating point)
6304 // MOVSS instruction
6305 instruct loadF(regF dst, memory mem) %{
6306 predicate(UseSSE>=1);
6307 match(Set dst (LoadF mem));
6308 ins_cost(145);
6309 format %{ "MOVSS $dst,$mem" %}
6310 ins_encode %{
6311 __ movflt ($dst$$XMMRegister, $mem$$Address);
6312 %}
6313 ins_pipe( pipe_slow );
6314 %}
6316 // Load Float
6317 instruct loadFPR(regFPR dst, memory mem) %{
6318 predicate(UseSSE==0);
6319 match(Set dst (LoadF mem));
6321 ins_cost(150);
6322 format %{ "FLD_S ST,$mem\n\t"
6323 "FSTP $dst" %}
6324 opcode(0xD9); /* D9 /0 */
6325 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6326 Pop_Reg_FPR(dst) );
6327 ins_pipe( fpu_reg_mem );
6328 %}
6330 // Load Effective Address
6331 instruct leaP8(eRegP dst, indOffset8 mem) %{
6332 match(Set dst mem);
6334 ins_cost(110);
6335 format %{ "LEA $dst,$mem" %}
6336 opcode(0x8D);
6337 ins_encode( OpcP, RegMem(dst,mem));
6338 ins_pipe( ialu_reg_reg_fat );
6339 %}
6341 instruct leaP32(eRegP dst, indOffset32 mem) %{
6342 match(Set dst mem);
6344 ins_cost(110);
6345 format %{ "LEA $dst,$mem" %}
6346 opcode(0x8D);
6347 ins_encode( OpcP, RegMem(dst,mem));
6348 ins_pipe( ialu_reg_reg_fat );
6349 %}
6351 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6352 match(Set dst mem);
6354 ins_cost(110);
6355 format %{ "LEA $dst,$mem" %}
6356 opcode(0x8D);
6357 ins_encode( OpcP, RegMem(dst,mem));
6358 ins_pipe( ialu_reg_reg_fat );
6359 %}
6361 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6362 match(Set dst mem);
6364 ins_cost(110);
6365 format %{ "LEA $dst,$mem" %}
6366 opcode(0x8D);
6367 ins_encode( OpcP, RegMem(dst,mem));
6368 ins_pipe( ialu_reg_reg_fat );
6369 %}
6371 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6372 match(Set dst mem);
6374 ins_cost(110);
6375 format %{ "LEA $dst,$mem" %}
6376 opcode(0x8D);
6377 ins_encode( OpcP, RegMem(dst,mem));
6378 ins_pipe( ialu_reg_reg_fat );
6379 %}
6381 // Load Constant
6382 instruct loadConI(rRegI dst, immI src) %{
6383 match(Set dst src);
6385 format %{ "MOV $dst,$src" %}
6386 ins_encode( LdImmI(dst, src) );
6387 ins_pipe( ialu_reg_fat );
6388 %}
6390 // Load Constant zero
6391 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6392 match(Set dst src);
6393 effect(KILL cr);
6395 ins_cost(50);
6396 format %{ "XOR $dst,$dst" %}
6397 opcode(0x33); /* + rd */
6398 ins_encode( OpcP, RegReg( dst, dst ) );
6399 ins_pipe( ialu_reg );
6400 %}
6402 instruct loadConP(eRegP dst, immP src) %{
6403 match(Set dst src);
6405 format %{ "MOV $dst,$src" %}
6406 opcode(0xB8); /* + rd */
6407 ins_encode( LdImmP(dst, src) );
6408 ins_pipe( ialu_reg_fat );
6409 %}
6411 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6412 match(Set dst src);
6413 effect(KILL cr);
6414 ins_cost(200);
6415 format %{ "MOV $dst.lo,$src.lo\n\t"
6416 "MOV $dst.hi,$src.hi" %}
6417 opcode(0xB8);
6418 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6419 ins_pipe( ialu_reg_long_fat );
6420 %}
6422 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6423 match(Set dst src);
6424 effect(KILL cr);
6425 ins_cost(150);
6426 format %{ "XOR $dst.lo,$dst.lo\n\t"
6427 "XOR $dst.hi,$dst.hi" %}
6428 opcode(0x33,0x33);
6429 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6430 ins_pipe( ialu_reg_long );
6431 %}
6433 // The instruction usage is guarded by predicate in operand immFPR().
6434 instruct loadConFPR(regFPR dst, immFPR con) %{
6435 match(Set dst con);
6436 ins_cost(125);
6437 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6438 "FSTP $dst" %}
6439 ins_encode %{
6440 __ fld_s($constantaddress($con));
6441 __ fstp_d($dst$$reg);
6442 %}
6443 ins_pipe(fpu_reg_con);
6444 %}
6446 // The instruction usage is guarded by predicate in operand immFPR0().
6447 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6448 match(Set dst con);
6449 ins_cost(125);
6450 format %{ "FLDZ ST\n\t"
6451 "FSTP $dst" %}
6452 ins_encode %{
6453 __ fldz();
6454 __ fstp_d($dst$$reg);
6455 %}
6456 ins_pipe(fpu_reg_con);
6457 %}
6459 // The instruction usage is guarded by predicate in operand immFPR1().
6460 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6461 match(Set dst con);
6462 ins_cost(125);
6463 format %{ "FLD1 ST\n\t"
6464 "FSTP $dst" %}
6465 ins_encode %{
6466 __ fld1();
6467 __ fstp_d($dst$$reg);
6468 %}
6469 ins_pipe(fpu_reg_con);
6470 %}
6472 // The instruction usage is guarded by predicate in operand immF().
6473 instruct loadConF(regF dst, immF con) %{
6474 match(Set dst con);
6475 ins_cost(125);
6476 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6477 ins_encode %{
6478 __ movflt($dst$$XMMRegister, $constantaddress($con));
6479 %}
6480 ins_pipe(pipe_slow);
6481 %}
6483 // The instruction usage is guarded by predicate in operand immF0().
6484 instruct loadConF0(regF dst, immF0 src) %{
6485 match(Set dst src);
6486 ins_cost(100);
6487 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6488 ins_encode %{
6489 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6490 %}
6491 ins_pipe(pipe_slow);
6492 %}
6494 // The instruction usage is guarded by predicate in operand immDPR().
6495 instruct loadConDPR(regDPR dst, immDPR con) %{
6496 match(Set dst con);
6497 ins_cost(125);
6499 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6500 "FSTP $dst" %}
6501 ins_encode %{
6502 __ fld_d($constantaddress($con));
6503 __ fstp_d($dst$$reg);
6504 %}
6505 ins_pipe(fpu_reg_con);
6506 %}
6508 // The instruction usage is guarded by predicate in operand immDPR0().
6509 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6510 match(Set dst con);
6511 ins_cost(125);
6513 format %{ "FLDZ ST\n\t"
6514 "FSTP $dst" %}
6515 ins_encode %{
6516 __ fldz();
6517 __ fstp_d($dst$$reg);
6518 %}
6519 ins_pipe(fpu_reg_con);
6520 %}
6522 // The instruction usage is guarded by predicate in operand immDPR1().
6523 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6524 match(Set dst con);
6525 ins_cost(125);
6527 format %{ "FLD1 ST\n\t"
6528 "FSTP $dst" %}
6529 ins_encode %{
6530 __ fld1();
6531 __ fstp_d($dst$$reg);
6532 %}
6533 ins_pipe(fpu_reg_con);
6534 %}
6536 // The instruction usage is guarded by predicate in operand immD().
6537 instruct loadConD(regD dst, immD con) %{
6538 match(Set dst con);
6539 ins_cost(125);
6540 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6541 ins_encode %{
6542 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6543 %}
6544 ins_pipe(pipe_slow);
6545 %}
6547 // The instruction usage is guarded by predicate in operand immD0().
6548 instruct loadConD0(regD dst, immD0 src) %{
6549 match(Set dst src);
6550 ins_cost(100);
6551 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6552 ins_encode %{
6553 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6554 %}
6555 ins_pipe( pipe_slow );
6556 %}
6558 // Load Stack Slot
6559 instruct loadSSI(rRegI dst, stackSlotI src) %{
6560 match(Set dst src);
6561 ins_cost(125);
6563 format %{ "MOV $dst,$src" %}
6564 opcode(0x8B);
6565 ins_encode( OpcP, RegMem(dst,src));
6566 ins_pipe( ialu_reg_mem );
6567 %}
6569 instruct loadSSL(eRegL dst, stackSlotL src) %{
6570 match(Set dst src);
6572 ins_cost(200);
6573 format %{ "MOV $dst,$src.lo\n\t"
6574 "MOV $dst+4,$src.hi" %}
6575 opcode(0x8B, 0x8B);
6576 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6577 ins_pipe( ialu_mem_long_reg );
6578 %}
6580 // Load Stack Slot
6581 instruct loadSSP(eRegP dst, stackSlotP src) %{
6582 match(Set dst src);
6583 ins_cost(125);
6585 format %{ "MOV $dst,$src" %}
6586 opcode(0x8B);
6587 ins_encode( OpcP, RegMem(dst,src));
6588 ins_pipe( ialu_reg_mem );
6589 %}
6591 // Load Stack Slot
6592 instruct loadSSF(regFPR dst, stackSlotF src) %{
6593 match(Set dst src);
6594 ins_cost(125);
6596 format %{ "FLD_S $src\n\t"
6597 "FSTP $dst" %}
6598 opcode(0xD9); /* D9 /0, FLD m32real */
6599 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6600 Pop_Reg_FPR(dst) );
6601 ins_pipe( fpu_reg_mem );
6602 %}
6604 // Load Stack Slot
6605 instruct loadSSD(regDPR dst, stackSlotD src) %{
6606 match(Set dst src);
6607 ins_cost(125);
6609 format %{ "FLD_D $src\n\t"
6610 "FSTP $dst" %}
6611 opcode(0xDD); /* DD /0, FLD m64real */
6612 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6613 Pop_Reg_DPR(dst) );
6614 ins_pipe( fpu_reg_mem );
6615 %}
6617 // Prefetch instructions.
6618 // Must be safe to execute with invalid address (cannot fault).
6620 instruct prefetchr0( memory mem ) %{
6621 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6622 match(PrefetchRead mem);
6623 ins_cost(0);
6624 size(0);
6625 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6626 ins_encode();
6627 ins_pipe(empty);
6628 %}
6630 instruct prefetchr( memory mem ) %{
6631 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6632 match(PrefetchRead mem);
6633 ins_cost(100);
6635 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6636 ins_encode %{
6637 __ prefetchr($mem$$Address);
6638 %}
6639 ins_pipe(ialu_mem);
6640 %}
6642 instruct prefetchrNTA( memory mem ) %{
6643 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6644 match(PrefetchRead mem);
6645 ins_cost(100);
6647 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6648 ins_encode %{
6649 __ prefetchnta($mem$$Address);
6650 %}
6651 ins_pipe(ialu_mem);
6652 %}
6654 instruct prefetchrT0( memory mem ) %{
6655 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6656 match(PrefetchRead mem);
6657 ins_cost(100);
6659 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6660 ins_encode %{
6661 __ prefetcht0($mem$$Address);
6662 %}
6663 ins_pipe(ialu_mem);
6664 %}
6666 instruct prefetchrT2( memory mem ) %{
6667 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6668 match(PrefetchRead mem);
6669 ins_cost(100);
6671 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6672 ins_encode %{
6673 __ prefetcht2($mem$$Address);
6674 %}
6675 ins_pipe(ialu_mem);
6676 %}
6678 instruct prefetchw0( memory mem ) %{
6679 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6680 match(PrefetchWrite mem);
6681 ins_cost(0);
6682 size(0);
6683 format %{ "Prefetch (non-SSE is empty encoding)" %}
6684 ins_encode();
6685 ins_pipe(empty);
6686 %}
6688 instruct prefetchw( memory mem ) %{
6689 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6690 match( PrefetchWrite mem );
6691 ins_cost(100);
6693 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6694 ins_encode %{
6695 __ prefetchw($mem$$Address);
6696 %}
6697 ins_pipe(ialu_mem);
6698 %}
6700 instruct prefetchwNTA( memory mem ) %{
6701 predicate(UseSSE>=1);
6702 match(PrefetchWrite mem);
6703 ins_cost(100);
6705 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6706 ins_encode %{
6707 __ prefetchnta($mem$$Address);
6708 %}
6709 ins_pipe(ialu_mem);
6710 %}
6712 // Prefetch instructions for allocation.
6714 instruct prefetchAlloc0( memory mem ) %{
6715 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6716 match(PrefetchAllocation mem);
6717 ins_cost(0);
6718 size(0);
6719 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6720 ins_encode();
6721 ins_pipe(empty);
6722 %}
6724 instruct prefetchAlloc( memory mem ) %{
6725 predicate(AllocatePrefetchInstr==3);
6726 match( PrefetchAllocation mem );
6727 ins_cost(100);
6729 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6730 ins_encode %{
6731 __ prefetchw($mem$$Address);
6732 %}
6733 ins_pipe(ialu_mem);
6734 %}
6736 instruct prefetchAllocNTA( memory mem ) %{
6737 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6738 match(PrefetchAllocation mem);
6739 ins_cost(100);
6741 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6742 ins_encode %{
6743 __ prefetchnta($mem$$Address);
6744 %}
6745 ins_pipe(ialu_mem);
6746 %}
6748 instruct prefetchAllocT0( memory mem ) %{
6749 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6750 match(PrefetchAllocation mem);
6751 ins_cost(100);
6753 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6754 ins_encode %{
6755 __ prefetcht0($mem$$Address);
6756 %}
6757 ins_pipe(ialu_mem);
6758 %}
6760 instruct prefetchAllocT2( memory mem ) %{
6761 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6762 match(PrefetchAllocation mem);
6763 ins_cost(100);
6765 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6766 ins_encode %{
6767 __ prefetcht2($mem$$Address);
6768 %}
6769 ins_pipe(ialu_mem);
6770 %}
6772 //----------Store Instructions-------------------------------------------------
6774 // Store Byte
6775 instruct storeB(memory mem, xRegI src) %{
6776 match(Set mem (StoreB mem src));
6778 ins_cost(125);
6779 format %{ "MOV8 $mem,$src" %}
6780 opcode(0x88);
6781 ins_encode( OpcP, RegMem( src, mem ) );
6782 ins_pipe( ialu_mem_reg );
6783 %}
6785 // Store Char/Short
6786 instruct storeC(memory mem, rRegI src) %{
6787 match(Set mem (StoreC mem src));
6789 ins_cost(125);
6790 format %{ "MOV16 $mem,$src" %}
6791 opcode(0x89, 0x66);
6792 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6793 ins_pipe( ialu_mem_reg );
6794 %}
6796 // Store Integer
6797 instruct storeI(memory mem, rRegI src) %{
6798 match(Set mem (StoreI mem src));
6800 ins_cost(125);
6801 format %{ "MOV $mem,$src" %}
6802 opcode(0x89);
6803 ins_encode( OpcP, RegMem( src, mem ) );
6804 ins_pipe( ialu_mem_reg );
6805 %}
6807 // Store Long
6808 instruct storeL(long_memory mem, eRegL src) %{
6809 predicate(!((StoreLNode*)n)->require_atomic_access());
6810 match(Set mem (StoreL mem src));
6812 ins_cost(200);
6813 format %{ "MOV $mem,$src.lo\n\t"
6814 "MOV $mem+4,$src.hi" %}
6815 opcode(0x89, 0x89);
6816 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6817 ins_pipe( ialu_mem_long_reg );
6818 %}
6820 // Store Long to Integer
6821 instruct storeL2I(memory mem, eRegL src) %{
6822 match(Set mem (StoreI mem (ConvL2I src)));
6824 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6825 ins_encode %{
6826 __ movl($mem$$Address, $src$$Register);
6827 %}
6828 ins_pipe(ialu_mem_reg);
6829 %}
6831 // Volatile Store Long. Must be atomic, so move it into
6832 // the FP TOS and then do a 64-bit FIST. Has to probe the
6833 // target address before the store (for null-ptr checks)
6834 // so the memory operand is used twice in the encoding.
6835 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6836 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6837 match(Set mem (StoreL mem src));
6838 effect( KILL cr );
6839 ins_cost(400);
6840 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6841 "FILD $src\n\t"
6842 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6843 opcode(0x3B);
6844 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6845 ins_pipe( fpu_reg_mem );
6846 %}
6848 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6849 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6850 match(Set mem (StoreL mem src));
6851 effect( TEMP tmp, KILL cr );
6852 ins_cost(380);
6853 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6854 "MOVSD $tmp,$src\n\t"
6855 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6856 ins_encode %{
6857 __ cmpl(rax, $mem$$Address);
6858 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6859 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6860 %}
6861 ins_pipe( pipe_slow );
6862 %}
6864 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6865 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6866 match(Set mem (StoreL mem src));
6867 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6868 ins_cost(360);
6869 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6870 "MOVD $tmp,$src.lo\n\t"
6871 "MOVD $tmp2,$src.hi\n\t"
6872 "PUNPCKLDQ $tmp,$tmp2\n\t"
6873 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6874 ins_encode %{
6875 __ cmpl(rax, $mem$$Address);
6876 __ movdl($tmp$$XMMRegister, $src$$Register);
6877 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6878 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6879 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6880 %}
6881 ins_pipe( pipe_slow );
6882 %}
6884 // Store Pointer; for storing unknown oops and raw pointers
6885 instruct storeP(memory mem, anyRegP src) %{
6886 match(Set mem (StoreP mem src));
6888 ins_cost(125);
6889 format %{ "MOV $mem,$src" %}
6890 opcode(0x89);
6891 ins_encode( OpcP, RegMem( src, mem ) );
6892 ins_pipe( ialu_mem_reg );
6893 %}
6895 // Store Integer Immediate
6896 instruct storeImmI(memory mem, immI src) %{
6897 match(Set mem (StoreI mem src));
6899 ins_cost(150);
6900 format %{ "MOV $mem,$src" %}
6901 opcode(0xC7); /* C7 /0 */
6902 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6903 ins_pipe( ialu_mem_imm );
6904 %}
6906 // Store Short/Char Immediate
6907 instruct storeImmI16(memory mem, immI16 src) %{
6908 predicate(UseStoreImmI16);
6909 match(Set mem (StoreC mem src));
6911 ins_cost(150);
6912 format %{ "MOV16 $mem,$src" %}
6913 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6914 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6915 ins_pipe( ialu_mem_imm );
6916 %}
6918 // Store Pointer Immediate; null pointers or constant oops that do not
6919 // need card-mark barriers.
6920 instruct storeImmP(memory mem, immP src) %{
6921 match(Set mem (StoreP mem src));
6923 ins_cost(150);
6924 format %{ "MOV $mem,$src" %}
6925 opcode(0xC7); /* C7 /0 */
6926 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6927 ins_pipe( ialu_mem_imm );
6928 %}
6930 // Store Byte Immediate
6931 instruct storeImmB(memory mem, immI8 src) %{
6932 match(Set mem (StoreB mem src));
6934 ins_cost(150);
6935 format %{ "MOV8 $mem,$src" %}
6936 opcode(0xC6); /* C6 /0 */
6937 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6938 ins_pipe( ialu_mem_imm );
6939 %}
6941 // Store CMS card-mark Immediate
6942 instruct storeImmCM(memory mem, immI8 src) %{
6943 match(Set mem (StoreCM mem src));
6945 ins_cost(150);
6946 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6947 opcode(0xC6); /* C6 /0 */
6948 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6949 ins_pipe( ialu_mem_imm );
6950 %}
6952 // Store Double
6953 instruct storeDPR( memory mem, regDPR1 src) %{
6954 predicate(UseSSE<=1);
6955 match(Set mem (StoreD mem src));
6957 ins_cost(100);
6958 format %{ "FST_D $mem,$src" %}
6959 opcode(0xDD); /* DD /2 */
6960 ins_encode( enc_FPR_store(mem,src) );
6961 ins_pipe( fpu_mem_reg );
6962 %}
6964 // Store double does rounding on x86
6965 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6966 predicate(UseSSE<=1);
6967 match(Set mem (StoreD mem (RoundDouble src)));
6969 ins_cost(100);
6970 format %{ "FST_D $mem,$src\t# round" %}
6971 opcode(0xDD); /* DD /2 */
6972 ins_encode( enc_FPR_store(mem,src) );
6973 ins_pipe( fpu_mem_reg );
6974 %}
6976 // Store XMM register to memory (double-precision floating points)
6977 // MOVSD instruction
6978 instruct storeD(memory mem, regD src) %{
6979 predicate(UseSSE>=2);
6980 match(Set mem (StoreD mem src));
6981 ins_cost(95);
6982 format %{ "MOVSD $mem,$src" %}
6983 ins_encode %{
6984 __ movdbl($mem$$Address, $src$$XMMRegister);
6985 %}
6986 ins_pipe( pipe_slow );
6987 %}
6989 // Store XMM register to memory (single-precision floating point)
6990 // MOVSS instruction
6991 instruct storeF(memory mem, regF src) %{
6992 predicate(UseSSE>=1);
6993 match(Set mem (StoreF mem src));
6994 ins_cost(95);
6995 format %{ "MOVSS $mem,$src" %}
6996 ins_encode %{
6997 __ movflt($mem$$Address, $src$$XMMRegister);
6998 %}
6999 ins_pipe( pipe_slow );
7000 %}
7002 // Store Float
7003 instruct storeFPR( memory mem, regFPR1 src) %{
7004 predicate(UseSSE==0);
7005 match(Set mem (StoreF mem src));
7007 ins_cost(100);
7008 format %{ "FST_S $mem,$src" %}
7009 opcode(0xD9); /* D9 /2 */
7010 ins_encode( enc_FPR_store(mem,src) );
7011 ins_pipe( fpu_mem_reg );
7012 %}
7014 // Store Float does rounding on x86
7015 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7016 predicate(UseSSE==0);
7017 match(Set mem (StoreF mem (RoundFloat src)));
7019 ins_cost(100);
7020 format %{ "FST_S $mem,$src\t# round" %}
7021 opcode(0xD9); /* D9 /2 */
7022 ins_encode( enc_FPR_store(mem,src) );
7023 ins_pipe( fpu_mem_reg );
7024 %}
7026 // Store Float does rounding on x86
7027 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7028 predicate(UseSSE<=1);
7029 match(Set mem (StoreF mem (ConvD2F src)));
7031 ins_cost(100);
7032 format %{ "FST_S $mem,$src\t# D-round" %}
7033 opcode(0xD9); /* D9 /2 */
7034 ins_encode( enc_FPR_store(mem,src) );
7035 ins_pipe( fpu_mem_reg );
7036 %}
7038 // Store immediate Float value (it is faster than store from FPU register)
7039 // The instruction usage is guarded by predicate in operand immFPR().
7040 instruct storeFPR_imm( memory mem, immFPR src) %{
7041 match(Set mem (StoreF mem src));
7043 ins_cost(50);
7044 format %{ "MOV $mem,$src\t# store float" %}
7045 opcode(0xC7); /* C7 /0 */
7046 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7047 ins_pipe( ialu_mem_imm );
7048 %}
7050 // Store immediate Float value (it is faster than store from XMM register)
7051 // The instruction usage is guarded by predicate in operand immF().
7052 instruct storeF_imm( memory mem, immF src) %{
7053 match(Set mem (StoreF mem src));
7055 ins_cost(50);
7056 format %{ "MOV $mem,$src\t# store float" %}
7057 opcode(0xC7); /* C7 /0 */
7058 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7059 ins_pipe( ialu_mem_imm );
7060 %}
7062 // Store Integer to stack slot
7063 instruct storeSSI(stackSlotI dst, rRegI src) %{
7064 match(Set dst src);
7066 ins_cost(100);
7067 format %{ "MOV $dst,$src" %}
7068 opcode(0x89);
7069 ins_encode( OpcPRegSS( dst, src ) );
7070 ins_pipe( ialu_mem_reg );
7071 %}
7073 // Store Integer to stack slot
7074 instruct storeSSP(stackSlotP dst, eRegP src) %{
7075 match(Set dst src);
7077 ins_cost(100);
7078 format %{ "MOV $dst,$src" %}
7079 opcode(0x89);
7080 ins_encode( OpcPRegSS( dst, src ) );
7081 ins_pipe( ialu_mem_reg );
7082 %}
7084 // Store Long to stack slot
7085 instruct storeSSL(stackSlotL dst, eRegL src) %{
7086 match(Set dst src);
7088 ins_cost(200);
7089 format %{ "MOV $dst,$src.lo\n\t"
7090 "MOV $dst+4,$src.hi" %}
7091 opcode(0x89, 0x89);
7092 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7093 ins_pipe( ialu_mem_long_reg );
7094 %}
7096 //----------MemBar Instructions-----------------------------------------------
7097 // Memory barrier flavors
7099 instruct membar_acquire() %{
7100 match(MemBarAcquire);
7101 ins_cost(400);
7103 size(0);
7104 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7105 ins_encode();
7106 ins_pipe(empty);
7107 %}
7109 instruct membar_acquire_lock() %{
7110 match(MemBarAcquireLock);
7111 ins_cost(0);
7113 size(0);
7114 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7115 ins_encode( );
7116 ins_pipe(empty);
7117 %}
7119 instruct membar_release() %{
7120 match(MemBarRelease);
7121 ins_cost(400);
7123 size(0);
7124 format %{ "MEMBAR-release ! (empty encoding)" %}
7125 ins_encode( );
7126 ins_pipe(empty);
7127 %}
7129 instruct membar_release_lock() %{
7130 match(MemBarReleaseLock);
7131 ins_cost(0);
7133 size(0);
7134 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7135 ins_encode( );
7136 ins_pipe(empty);
7137 %}
7139 instruct membar_volatile(eFlagsReg cr) %{
7140 match(MemBarVolatile);
7141 effect(KILL cr);
7142 ins_cost(400);
7144 format %{
7145 $$template
7146 if (os::is_MP()) {
7147 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7148 } else {
7149 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7150 }
7151 %}
7152 ins_encode %{
7153 __ membar(Assembler::StoreLoad);
7154 %}
7155 ins_pipe(pipe_slow);
7156 %}
7158 instruct unnecessary_membar_volatile() %{
7159 match(MemBarVolatile);
7160 predicate(Matcher::post_store_load_barrier(n));
7161 ins_cost(0);
7163 size(0);
7164 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7165 ins_encode( );
7166 ins_pipe(empty);
7167 %}
7169 instruct membar_storestore() %{
7170 match(MemBarStoreStore);
7171 ins_cost(0);
7173 size(0);
7174 format %{ "MEMBAR-storestore (empty encoding)" %}
7175 ins_encode( );
7176 ins_pipe(empty);
7177 %}
7179 //----------Move Instructions--------------------------------------------------
7180 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7181 match(Set dst (CastX2P src));
7182 format %{ "# X2P $dst, $src" %}
7183 ins_encode( /*empty encoding*/ );
7184 ins_cost(0);
7185 ins_pipe(empty);
7186 %}
7188 instruct castP2X(rRegI dst, eRegP src ) %{
7189 match(Set dst (CastP2X src));
7190 ins_cost(50);
7191 format %{ "MOV $dst, $src\t# CastP2X" %}
7192 ins_encode( enc_Copy( dst, src) );
7193 ins_pipe( ialu_reg_reg );
7194 %}
7196 //----------Conditional Move---------------------------------------------------
7197 // Conditional move
7198 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7199 predicate(!VM_Version::supports_cmov() );
7200 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7201 ins_cost(200);
7202 format %{ "J$cop,us skip\t# signed cmove\n\t"
7203 "MOV $dst,$src\n"
7204 "skip:" %}
7205 ins_encode %{
7206 Label Lskip;
7207 // Invert sense of branch from sense of CMOV
7208 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7209 __ movl($dst$$Register, $src$$Register);
7210 __ bind(Lskip);
7211 %}
7212 ins_pipe( pipe_cmov_reg );
7213 %}
7215 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7216 predicate(!VM_Version::supports_cmov() );
7217 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7218 ins_cost(200);
7219 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7220 "MOV $dst,$src\n"
7221 "skip:" %}
7222 ins_encode %{
7223 Label Lskip;
7224 // Invert sense of branch from sense of CMOV
7225 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7226 __ movl($dst$$Register, $src$$Register);
7227 __ bind(Lskip);
7228 %}
7229 ins_pipe( pipe_cmov_reg );
7230 %}
7232 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7233 predicate(VM_Version::supports_cmov() );
7234 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7235 ins_cost(200);
7236 format %{ "CMOV$cop $dst,$src" %}
7237 opcode(0x0F,0x40);
7238 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7239 ins_pipe( pipe_cmov_reg );
7240 %}
7242 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7243 predicate(VM_Version::supports_cmov() );
7244 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7245 ins_cost(200);
7246 format %{ "CMOV$cop $dst,$src" %}
7247 opcode(0x0F,0x40);
7248 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7249 ins_pipe( pipe_cmov_reg );
7250 %}
7252 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7253 predicate(VM_Version::supports_cmov() );
7254 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7255 ins_cost(200);
7256 expand %{
7257 cmovI_regU(cop, cr, dst, src);
7258 %}
7259 %}
7261 // Conditional move
7262 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7263 predicate(VM_Version::supports_cmov() );
7264 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7265 ins_cost(250);
7266 format %{ "CMOV$cop $dst,$src" %}
7267 opcode(0x0F,0x40);
7268 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7269 ins_pipe( pipe_cmov_mem );
7270 %}
7272 // Conditional move
7273 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7274 predicate(VM_Version::supports_cmov() );
7275 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7276 ins_cost(250);
7277 format %{ "CMOV$cop $dst,$src" %}
7278 opcode(0x0F,0x40);
7279 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7280 ins_pipe( pipe_cmov_mem );
7281 %}
7283 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7284 predicate(VM_Version::supports_cmov() );
7285 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7286 ins_cost(250);
7287 expand %{
7288 cmovI_memU(cop, cr, dst, src);
7289 %}
7290 %}
7292 // Conditional move
7293 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7294 predicate(VM_Version::supports_cmov() );
7295 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7296 ins_cost(200);
7297 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7298 opcode(0x0F,0x40);
7299 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7300 ins_pipe( pipe_cmov_reg );
7301 %}
7303 // Conditional move (non-P6 version)
7304 // Note: a CMoveP is generated for stubs and native wrappers
7305 // regardless of whether we are on a P6, so we
7306 // emulate a cmov here
7307 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7308 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7309 ins_cost(300);
7310 format %{ "Jn$cop skip\n\t"
7311 "MOV $dst,$src\t# pointer\n"
7312 "skip:" %}
7313 opcode(0x8b);
7314 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7315 ins_pipe( pipe_cmov_reg );
7316 %}
7318 // Conditional move
7319 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7320 predicate(VM_Version::supports_cmov() );
7321 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7322 ins_cost(200);
7323 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7324 opcode(0x0F,0x40);
7325 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7326 ins_pipe( pipe_cmov_reg );
7327 %}
7329 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7330 predicate(VM_Version::supports_cmov() );
7331 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7332 ins_cost(200);
7333 expand %{
7334 cmovP_regU(cop, cr, dst, src);
7335 %}
7336 %}
7338 // DISABLED: Requires the ADLC to emit a bottom_type call that
7339 // correctly meets the two pointer arguments; one is an incoming
7340 // register but the other is a memory operand. ALSO appears to
7341 // be buggy with implicit null checks.
7342 //
7343 //// Conditional move
7344 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7345 // predicate(VM_Version::supports_cmov() );
7346 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7347 // ins_cost(250);
7348 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7349 // opcode(0x0F,0x40);
7350 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7351 // ins_pipe( pipe_cmov_mem );
7352 //%}
7353 //
7354 //// Conditional move
7355 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7356 // predicate(VM_Version::supports_cmov() );
7357 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7358 // ins_cost(250);
7359 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7360 // opcode(0x0F,0x40);
7361 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7362 // ins_pipe( pipe_cmov_mem );
7363 //%}
7365 // Conditional move
7366 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7367 predicate(UseSSE<=1);
7368 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7369 ins_cost(200);
7370 format %{ "FCMOV$cop $dst,$src\t# double" %}
7371 opcode(0xDA);
7372 ins_encode( enc_cmov_dpr(cop,src) );
7373 ins_pipe( pipe_cmovDPR_reg );
7374 %}
7376 // Conditional move
7377 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7378 predicate(UseSSE==0);
7379 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7380 ins_cost(200);
7381 format %{ "FCMOV$cop $dst,$src\t# float" %}
7382 opcode(0xDA);
7383 ins_encode( enc_cmov_dpr(cop,src) );
7384 ins_pipe( pipe_cmovDPR_reg );
7385 %}
7387 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7388 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7389 predicate(UseSSE<=1);
7390 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7391 ins_cost(200);
7392 format %{ "Jn$cop skip\n\t"
7393 "MOV $dst,$src\t# double\n"
7394 "skip:" %}
7395 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7396 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7397 ins_pipe( pipe_cmovDPR_reg );
7398 %}
7400 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7401 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7402 predicate(UseSSE==0);
7403 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7404 ins_cost(200);
7405 format %{ "Jn$cop skip\n\t"
7406 "MOV $dst,$src\t# float\n"
7407 "skip:" %}
7408 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7409 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7410 ins_pipe( pipe_cmovDPR_reg );
7411 %}
7413 // No CMOVE with SSE/SSE2
7414 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7415 predicate (UseSSE>=1);
7416 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7417 ins_cost(200);
7418 format %{ "Jn$cop skip\n\t"
7419 "MOVSS $dst,$src\t# float\n"
7420 "skip:" %}
7421 ins_encode %{
7422 Label skip;
7423 // Invert sense of branch from sense of CMOV
7424 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7425 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7426 __ bind(skip);
7427 %}
7428 ins_pipe( pipe_slow );
7429 %}
7431 // No CMOVE with SSE/SSE2
7432 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7433 predicate (UseSSE>=2);
7434 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7435 ins_cost(200);
7436 format %{ "Jn$cop skip\n\t"
7437 "MOVSD $dst,$src\t# float\n"
7438 "skip:" %}
7439 ins_encode %{
7440 Label skip;
7441 // Invert sense of branch from sense of CMOV
7442 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7443 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7444 __ bind(skip);
7445 %}
7446 ins_pipe( pipe_slow );
7447 %}
7449 // unsigned version
7450 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7451 predicate (UseSSE>=1);
7452 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7453 ins_cost(200);
7454 format %{ "Jn$cop skip\n\t"
7455 "MOVSS $dst,$src\t# float\n"
7456 "skip:" %}
7457 ins_encode %{
7458 Label skip;
7459 // Invert sense of branch from sense of CMOV
7460 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7461 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7462 __ bind(skip);
7463 %}
7464 ins_pipe( pipe_slow );
7465 %}
7467 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7468 predicate (UseSSE>=1);
7469 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7470 ins_cost(200);
7471 expand %{
7472 fcmovF_regU(cop, cr, dst, src);
7473 %}
7474 %}
7476 // unsigned version
7477 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7478 predicate (UseSSE>=2);
7479 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7480 ins_cost(200);
7481 format %{ "Jn$cop skip\n\t"
7482 "MOVSD $dst,$src\t# float\n"
7483 "skip:" %}
7484 ins_encode %{
7485 Label skip;
7486 // Invert sense of branch from sense of CMOV
7487 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7488 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7489 __ bind(skip);
7490 %}
7491 ins_pipe( pipe_slow );
7492 %}
7494 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7495 predicate (UseSSE>=2);
7496 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7497 ins_cost(200);
7498 expand %{
7499 fcmovD_regU(cop, cr, dst, src);
7500 %}
7501 %}
7503 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7504 predicate(VM_Version::supports_cmov() );
7505 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7506 ins_cost(200);
7507 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7508 "CMOV$cop $dst.hi,$src.hi" %}
7509 opcode(0x0F,0x40);
7510 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7511 ins_pipe( pipe_cmov_reg_long );
7512 %}
7514 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7515 predicate(VM_Version::supports_cmov() );
7516 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7517 ins_cost(200);
7518 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7519 "CMOV$cop $dst.hi,$src.hi" %}
7520 opcode(0x0F,0x40);
7521 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7522 ins_pipe( pipe_cmov_reg_long );
7523 %}
7525 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7526 predicate(VM_Version::supports_cmov() );
7527 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7528 ins_cost(200);
7529 expand %{
7530 cmovL_regU(cop, cr, dst, src);
7531 %}
7532 %}
7534 //----------Arithmetic Instructions--------------------------------------------
7535 //----------Addition Instructions----------------------------------------------
7536 // Integer Addition Instructions
7537 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7538 match(Set dst (AddI dst src));
7539 effect(KILL cr);
7541 size(2);
7542 format %{ "ADD $dst,$src" %}
7543 opcode(0x03);
7544 ins_encode( OpcP, RegReg( dst, src) );
7545 ins_pipe( ialu_reg_reg );
7546 %}
7548 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7549 match(Set dst (AddI dst src));
7550 effect(KILL cr);
7552 format %{ "ADD $dst,$src" %}
7553 opcode(0x81, 0x00); /* /0 id */
7554 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7555 ins_pipe( ialu_reg );
7556 %}
7558 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7559 predicate(UseIncDec);
7560 match(Set dst (AddI dst src));
7561 effect(KILL cr);
7563 size(1);
7564 format %{ "INC $dst" %}
7565 opcode(0x40); /* */
7566 ins_encode( Opc_plus( primary, dst ) );
7567 ins_pipe( ialu_reg );
7568 %}
7570 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7571 match(Set dst (AddI src0 src1));
7572 ins_cost(110);
7574 format %{ "LEA $dst,[$src0 + $src1]" %}
7575 opcode(0x8D); /* 0x8D /r */
7576 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7577 ins_pipe( ialu_reg_reg );
7578 %}
7580 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7581 match(Set dst (AddP src0 src1));
7582 ins_cost(110);
7584 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7585 opcode(0x8D); /* 0x8D /r */
7586 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7587 ins_pipe( ialu_reg_reg );
7588 %}
7590 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7591 predicate(UseIncDec);
7592 match(Set dst (AddI dst src));
7593 effect(KILL cr);
7595 size(1);
7596 format %{ "DEC $dst" %}
7597 opcode(0x48); /* */
7598 ins_encode( Opc_plus( primary, dst ) );
7599 ins_pipe( ialu_reg );
7600 %}
7602 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7603 match(Set dst (AddP dst src));
7604 effect(KILL cr);
7606 size(2);
7607 format %{ "ADD $dst,$src" %}
7608 opcode(0x03);
7609 ins_encode( OpcP, RegReg( dst, src) );
7610 ins_pipe( ialu_reg_reg );
7611 %}
7613 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7614 match(Set dst (AddP dst src));
7615 effect(KILL cr);
7617 format %{ "ADD $dst,$src" %}
7618 opcode(0x81,0x00); /* Opcode 81 /0 id */
7619 // ins_encode( RegImm( dst, src) );
7620 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7621 ins_pipe( ialu_reg );
7622 %}
7624 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7625 match(Set dst (AddI dst (LoadI src)));
7626 effect(KILL cr);
7628 ins_cost(125);
7629 format %{ "ADD $dst,$src" %}
7630 opcode(0x03);
7631 ins_encode( OpcP, RegMem( dst, src) );
7632 ins_pipe( ialu_reg_mem );
7633 %}
7635 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7636 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7637 effect(KILL cr);
7639 ins_cost(150);
7640 format %{ "ADD $dst,$src" %}
7641 opcode(0x01); /* Opcode 01 /r */
7642 ins_encode( OpcP, RegMem( src, dst ) );
7643 ins_pipe( ialu_mem_reg );
7644 %}
7646 // Add Memory with Immediate
7647 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7648 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7649 effect(KILL cr);
7651 ins_cost(125);
7652 format %{ "ADD $dst,$src" %}
7653 opcode(0x81); /* Opcode 81 /0 id */
7654 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7655 ins_pipe( ialu_mem_imm );
7656 %}
7658 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7659 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7660 effect(KILL cr);
7662 ins_cost(125);
7663 format %{ "INC $dst" %}
7664 opcode(0xFF); /* Opcode FF /0 */
7665 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7666 ins_pipe( ialu_mem_imm );
7667 %}
7669 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7670 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7671 effect(KILL cr);
7673 ins_cost(125);
7674 format %{ "DEC $dst" %}
7675 opcode(0xFF); /* Opcode FF /1 */
7676 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7677 ins_pipe( ialu_mem_imm );
7678 %}
7681 instruct checkCastPP( eRegP dst ) %{
7682 match(Set dst (CheckCastPP dst));
7684 size(0);
7685 format %{ "#checkcastPP of $dst" %}
7686 ins_encode( /*empty encoding*/ );
7687 ins_pipe( empty );
7688 %}
7690 instruct castPP( eRegP dst ) %{
7691 match(Set dst (CastPP dst));
7692 format %{ "#castPP of $dst" %}
7693 ins_encode( /*empty encoding*/ );
7694 ins_pipe( empty );
7695 %}
7697 instruct castII( rRegI dst ) %{
7698 match(Set dst (CastII dst));
7699 format %{ "#castII of $dst" %}
7700 ins_encode( /*empty encoding*/ );
7701 ins_cost(0);
7702 ins_pipe( empty );
7703 %}
7706 // Load-locked - same as a regular pointer load when used with compare-swap
7707 instruct loadPLocked(eRegP dst, memory mem) %{
7708 match(Set dst (LoadPLocked mem));
7710 ins_cost(125);
7711 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7712 opcode(0x8B);
7713 ins_encode( OpcP, RegMem(dst,mem));
7714 ins_pipe( ialu_reg_mem );
7715 %}
7717 // Conditional-store of the updated heap-top.
7718 // Used during allocation of the shared heap.
7719 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7720 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7721 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7722 // EAX is killed if there is contention, but then it's also unused.
7723 // In the common case of no contention, EAX holds the new oop address.
7724 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7725 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7726 ins_pipe( pipe_cmpxchg );
7727 %}
7729 // Conditional-store of an int value.
7730 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7731 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7732 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7733 effect(KILL oldval);
7734 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7735 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7736 ins_pipe( pipe_cmpxchg );
7737 %}
7739 // Conditional-store of a long value.
7740 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7741 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7742 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7743 effect(KILL oldval);
7744 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7745 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7746 "XCHG EBX,ECX"
7747 %}
7748 ins_encode %{
7749 // Note: we need to swap rbx, and rcx before and after the
7750 // cmpxchg8 instruction because the instruction uses
7751 // rcx as the high order word of the new value to store but
7752 // our register encoding uses rbx.
7753 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7754 if( os::is_MP() )
7755 __ lock();
7756 __ cmpxchg8($mem$$Address);
7757 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7758 %}
7759 ins_pipe( pipe_cmpxchg );
7760 %}
7762 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7764 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7765 predicate(VM_Version::supports_cx8());
7766 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7767 effect(KILL cr, KILL oldval);
7768 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7769 "MOV $res,0\n\t"
7770 "JNE,s fail\n\t"
7771 "MOV $res,1\n"
7772 "fail:" %}
7773 ins_encode( enc_cmpxchg8(mem_ptr),
7774 enc_flags_ne_to_boolean(res) );
7775 ins_pipe( pipe_cmpxchg );
7776 %}
7778 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7779 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7780 effect(KILL cr, KILL oldval);
7781 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7782 "MOV $res,0\n\t"
7783 "JNE,s fail\n\t"
7784 "MOV $res,1\n"
7785 "fail:" %}
7786 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7787 ins_pipe( pipe_cmpxchg );
7788 %}
7790 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7791 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7792 effect(KILL cr, KILL oldval);
7793 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7794 "MOV $res,0\n\t"
7795 "JNE,s fail\n\t"
7796 "MOV $res,1\n"
7797 "fail:" %}
7798 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7799 ins_pipe( pipe_cmpxchg );
7800 %}
7802 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7803 predicate(n->as_LoadStore()->result_not_used());
7804 match(Set dummy (GetAndAddI mem add));
7805 effect(KILL cr);
7806 format %{ "ADDL [$mem],$add" %}
7807 ins_encode %{
7808 if (os::is_MP()) { __ lock(); }
7809 __ addl($mem$$Address, $add$$constant);
7810 %}
7811 ins_pipe( pipe_cmpxchg );
7812 %}
7814 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7815 match(Set newval (GetAndAddI mem newval));
7816 effect(KILL cr);
7817 format %{ "XADDL [$mem],$newval" %}
7818 ins_encode %{
7819 if (os::is_MP()) { __ lock(); }
7820 __ xaddl($mem$$Address, $newval$$Register);
7821 %}
7822 ins_pipe( pipe_cmpxchg );
7823 %}
7825 instruct xchgI( memory mem, rRegI newval) %{
7826 match(Set newval (GetAndSetI mem newval));
7827 format %{ "XCHGL $newval,[$mem]" %}
7828 ins_encode %{
7829 __ xchgl($newval$$Register, $mem$$Address);
7830 %}
7831 ins_pipe( pipe_cmpxchg );
7832 %}
7834 instruct xchgP( memory mem, pRegP newval) %{
7835 match(Set newval (GetAndSetP mem newval));
7836 format %{ "XCHGL $newval,[$mem]" %}
7837 ins_encode %{
7838 __ xchgl($newval$$Register, $mem$$Address);
7839 %}
7840 ins_pipe( pipe_cmpxchg );
7841 %}
7843 //----------Subtraction Instructions-------------------------------------------
7844 // Integer Subtraction Instructions
7845 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7846 match(Set dst (SubI dst src));
7847 effect(KILL cr);
7849 size(2);
7850 format %{ "SUB $dst,$src" %}
7851 opcode(0x2B);
7852 ins_encode( OpcP, RegReg( dst, src) );
7853 ins_pipe( ialu_reg_reg );
7854 %}
7856 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7857 match(Set dst (SubI dst src));
7858 effect(KILL cr);
7860 format %{ "SUB $dst,$src" %}
7861 opcode(0x81,0x05); /* Opcode 81 /5 */
7862 // ins_encode( RegImm( dst, src) );
7863 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7864 ins_pipe( ialu_reg );
7865 %}
7867 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7868 match(Set dst (SubI dst (LoadI src)));
7869 effect(KILL cr);
7871 ins_cost(125);
7872 format %{ "SUB $dst,$src" %}
7873 opcode(0x2B);
7874 ins_encode( OpcP, RegMem( dst, src) );
7875 ins_pipe( ialu_reg_mem );
7876 %}
7878 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7879 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7880 effect(KILL cr);
7882 ins_cost(150);
7883 format %{ "SUB $dst,$src" %}
7884 opcode(0x29); /* Opcode 29 /r */
7885 ins_encode( OpcP, RegMem( src, dst ) );
7886 ins_pipe( ialu_mem_reg );
7887 %}
7889 // Subtract from a pointer
7890 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7891 match(Set dst (AddP dst (SubI zero src)));
7892 effect(KILL cr);
7894 size(2);
7895 format %{ "SUB $dst,$src" %}
7896 opcode(0x2B);
7897 ins_encode( OpcP, RegReg( dst, src) );
7898 ins_pipe( ialu_reg_reg );
7899 %}
7901 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7902 match(Set dst (SubI zero dst));
7903 effect(KILL cr);
7905 size(2);
7906 format %{ "NEG $dst" %}
7907 opcode(0xF7,0x03); // Opcode F7 /3
7908 ins_encode( OpcP, RegOpc( dst ) );
7909 ins_pipe( ialu_reg );
7910 %}
7913 //----------Multiplication/Division Instructions-------------------------------
7914 // Integer Multiplication Instructions
7915 // Multiply Register
7916 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7917 match(Set dst (MulI dst src));
7918 effect(KILL cr);
7920 size(3);
7921 ins_cost(300);
7922 format %{ "IMUL $dst,$src" %}
7923 opcode(0xAF, 0x0F);
7924 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7925 ins_pipe( ialu_reg_reg_alu0 );
7926 %}
7928 // Multiply 32-bit Immediate
7929 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7930 match(Set dst (MulI src imm));
7931 effect(KILL cr);
7933 ins_cost(300);
7934 format %{ "IMUL $dst,$src,$imm" %}
7935 opcode(0x69); /* 69 /r id */
7936 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7937 ins_pipe( ialu_reg_reg_alu0 );
7938 %}
7940 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7941 match(Set dst src);
7942 effect(KILL cr);
7944 // Note that this is artificially increased to make it more expensive than loadConL
7945 ins_cost(250);
7946 format %{ "MOV EAX,$src\t// low word only" %}
7947 opcode(0xB8);
7948 ins_encode( LdImmL_Lo(dst, src) );
7949 ins_pipe( ialu_reg_fat );
7950 %}
7952 // Multiply by 32-bit Immediate, taking the shifted high order results
7953 // (special case for shift by 32)
7954 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7955 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7956 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7957 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7958 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7959 effect(USE src1, KILL cr);
7961 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7962 ins_cost(0*100 + 1*400 - 150);
7963 format %{ "IMUL EDX:EAX,$src1" %}
7964 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7965 ins_pipe( pipe_slow );
7966 %}
7968 // Multiply by 32-bit Immediate, taking the shifted high order results
7969 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7970 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7971 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7972 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7973 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7974 effect(USE src1, KILL cr);
7976 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7977 ins_cost(1*100 + 1*400 - 150);
7978 format %{ "IMUL EDX:EAX,$src1\n\t"
7979 "SAR EDX,$cnt-32" %}
7980 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7981 ins_pipe( pipe_slow );
7982 %}
7984 // Multiply Memory 32-bit Immediate
7985 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7986 match(Set dst (MulI (LoadI src) imm));
7987 effect(KILL cr);
7989 ins_cost(300);
7990 format %{ "IMUL $dst,$src,$imm" %}
7991 opcode(0x69); /* 69 /r id */
7992 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7993 ins_pipe( ialu_reg_mem_alu0 );
7994 %}
7996 // Multiply Memory
7997 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7998 match(Set dst (MulI dst (LoadI src)));
7999 effect(KILL cr);
8001 ins_cost(350);
8002 format %{ "IMUL $dst,$src" %}
8003 opcode(0xAF, 0x0F);
8004 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8005 ins_pipe( ialu_reg_mem_alu0 );
8006 %}
8008 // Multiply Register Int to Long
8009 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8010 // Basic Idea: long = (long)int * (long)int
8011 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8012 effect(DEF dst, USE src, USE src1, KILL flags);
8014 ins_cost(300);
8015 format %{ "IMUL $dst,$src1" %}
8017 ins_encode( long_int_multiply( dst, src1 ) );
8018 ins_pipe( ialu_reg_reg_alu0 );
8019 %}
8021 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8022 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8023 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8024 effect(KILL flags);
8026 ins_cost(300);
8027 format %{ "MUL $dst,$src1" %}
8029 ins_encode( long_uint_multiply(dst, src1) );
8030 ins_pipe( ialu_reg_reg_alu0 );
8031 %}
8033 // Multiply Register Long
8034 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8035 match(Set dst (MulL dst src));
8036 effect(KILL cr, TEMP tmp);
8037 ins_cost(4*100+3*400);
8038 // Basic idea: lo(result) = lo(x_lo * y_lo)
8039 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8040 format %{ "MOV $tmp,$src.lo\n\t"
8041 "IMUL $tmp,EDX\n\t"
8042 "MOV EDX,$src.hi\n\t"
8043 "IMUL EDX,EAX\n\t"
8044 "ADD $tmp,EDX\n\t"
8045 "MUL EDX:EAX,$src.lo\n\t"
8046 "ADD EDX,$tmp" %}
8047 ins_encode( long_multiply( dst, src, tmp ) );
8048 ins_pipe( pipe_slow );
8049 %}
8051 // Multiply Register Long where the left operand's high 32 bits are zero
8052 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8053 predicate(is_operand_hi32_zero(n->in(1)));
8054 match(Set dst (MulL dst src));
8055 effect(KILL cr, TEMP tmp);
8056 ins_cost(2*100+2*400);
8057 // Basic idea: lo(result) = lo(x_lo * y_lo)
8058 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8059 format %{ "MOV $tmp,$src.hi\n\t"
8060 "IMUL $tmp,EAX\n\t"
8061 "MUL EDX:EAX,$src.lo\n\t"
8062 "ADD EDX,$tmp" %}
8063 ins_encode %{
8064 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8065 __ imull($tmp$$Register, rax);
8066 __ mull($src$$Register);
8067 __ addl(rdx, $tmp$$Register);
8068 %}
8069 ins_pipe( pipe_slow );
8070 %}
8072 // Multiply Register Long where the right operand's high 32 bits are zero
8073 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8074 predicate(is_operand_hi32_zero(n->in(2)));
8075 match(Set dst (MulL dst src));
8076 effect(KILL cr, TEMP tmp);
8077 ins_cost(2*100+2*400);
8078 // Basic idea: lo(result) = lo(x_lo * y_lo)
8079 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8080 format %{ "MOV $tmp,$src.lo\n\t"
8081 "IMUL $tmp,EDX\n\t"
8082 "MUL EDX:EAX,$src.lo\n\t"
8083 "ADD EDX,$tmp" %}
8084 ins_encode %{
8085 __ movl($tmp$$Register, $src$$Register);
8086 __ imull($tmp$$Register, rdx);
8087 __ mull($src$$Register);
8088 __ addl(rdx, $tmp$$Register);
8089 %}
8090 ins_pipe( pipe_slow );
8091 %}
8093 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8094 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8095 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8096 match(Set dst (MulL dst src));
8097 effect(KILL cr);
8098 ins_cost(1*400);
8099 // Basic idea: lo(result) = lo(x_lo * y_lo)
8100 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8101 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8102 ins_encode %{
8103 __ mull($src$$Register);
8104 %}
8105 ins_pipe( pipe_slow );
8106 %}
8108 // Multiply Register Long by small constant
8109 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8110 match(Set dst (MulL dst src));
8111 effect(KILL cr, TEMP tmp);
8112 ins_cost(2*100+2*400);
8113 size(12);
8114 // Basic idea: lo(result) = lo(src * EAX)
8115 // hi(result) = hi(src * EAX) + lo(src * EDX)
8116 format %{ "IMUL $tmp,EDX,$src\n\t"
8117 "MOV EDX,$src\n\t"
8118 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8119 "ADD EDX,$tmp" %}
8120 ins_encode( long_multiply_con( dst, src, tmp ) );
8121 ins_pipe( pipe_slow );
8122 %}
8124 // Integer DIV with Register
8125 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8126 match(Set rax (DivI rax div));
8127 effect(KILL rdx, KILL cr);
8128 size(26);
8129 ins_cost(30*100+10*100);
8130 format %{ "CMP EAX,0x80000000\n\t"
8131 "JNE,s normal\n\t"
8132 "XOR EDX,EDX\n\t"
8133 "CMP ECX,-1\n\t"
8134 "JE,s done\n"
8135 "normal: CDQ\n\t"
8136 "IDIV $div\n\t"
8137 "done:" %}
8138 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8139 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8140 ins_pipe( ialu_reg_reg_alu0 );
8141 %}
8143 // Divide Register Long
8144 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8145 match(Set dst (DivL src1 src2));
8146 effect( KILL cr, KILL cx, KILL bx );
8147 ins_cost(10000);
8148 format %{ "PUSH $src1.hi\n\t"
8149 "PUSH $src1.lo\n\t"
8150 "PUSH $src2.hi\n\t"
8151 "PUSH $src2.lo\n\t"
8152 "CALL SharedRuntime::ldiv\n\t"
8153 "ADD ESP,16" %}
8154 ins_encode( long_div(src1,src2) );
8155 ins_pipe( pipe_slow );
8156 %}
8158 // Integer DIVMOD with Register, both quotient and mod results
8159 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8160 match(DivModI rax div);
8161 effect(KILL cr);
8162 size(26);
8163 ins_cost(30*100+10*100);
8164 format %{ "CMP EAX,0x80000000\n\t"
8165 "JNE,s normal\n\t"
8166 "XOR EDX,EDX\n\t"
8167 "CMP ECX,-1\n\t"
8168 "JE,s done\n"
8169 "normal: CDQ\n\t"
8170 "IDIV $div\n\t"
8171 "done:" %}
8172 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8173 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8174 ins_pipe( pipe_slow );
8175 %}
8177 // Integer MOD with Register
8178 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8179 match(Set rdx (ModI rax div));
8180 effect(KILL rax, KILL cr);
8182 size(26);
8183 ins_cost(300);
8184 format %{ "CDQ\n\t"
8185 "IDIV $div" %}
8186 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8187 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8188 ins_pipe( ialu_reg_reg_alu0 );
8189 %}
8191 // Remainder Register Long
8192 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8193 match(Set dst (ModL src1 src2));
8194 effect( KILL cr, KILL cx, KILL bx );
8195 ins_cost(10000);
8196 format %{ "PUSH $src1.hi\n\t"
8197 "PUSH $src1.lo\n\t"
8198 "PUSH $src2.hi\n\t"
8199 "PUSH $src2.lo\n\t"
8200 "CALL SharedRuntime::lrem\n\t"
8201 "ADD ESP,16" %}
8202 ins_encode( long_mod(src1,src2) );
8203 ins_pipe( pipe_slow );
8204 %}
8206 // Divide Register Long (no special case since divisor != -1)
8207 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8208 match(Set dst (DivL dst imm));
8209 effect( TEMP tmp, TEMP tmp2, KILL cr );
8210 ins_cost(1000);
8211 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8212 "XOR $tmp2,$tmp2\n\t"
8213 "CMP $tmp,EDX\n\t"
8214 "JA,s fast\n\t"
8215 "MOV $tmp2,EAX\n\t"
8216 "MOV EAX,EDX\n\t"
8217 "MOV EDX,0\n\t"
8218 "JLE,s pos\n\t"
8219 "LNEG EAX : $tmp2\n\t"
8220 "DIV $tmp # unsigned division\n\t"
8221 "XCHG EAX,$tmp2\n\t"
8222 "DIV $tmp\n\t"
8223 "LNEG $tmp2 : EAX\n\t"
8224 "JMP,s done\n"
8225 "pos:\n\t"
8226 "DIV $tmp\n\t"
8227 "XCHG EAX,$tmp2\n"
8228 "fast:\n\t"
8229 "DIV $tmp\n"
8230 "done:\n\t"
8231 "MOV EDX,$tmp2\n\t"
8232 "NEG EDX:EAX # if $imm < 0" %}
8233 ins_encode %{
8234 int con = (int)$imm$$constant;
8235 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8236 int pcon = (con > 0) ? con : -con;
8237 Label Lfast, Lpos, Ldone;
8239 __ movl($tmp$$Register, pcon);
8240 __ xorl($tmp2$$Register,$tmp2$$Register);
8241 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8242 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8244 __ movl($tmp2$$Register, $dst$$Register); // save
8245 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8246 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8247 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8249 // Negative dividend.
8250 // convert value to positive to use unsigned division
8251 __ lneg($dst$$Register, $tmp2$$Register);
8252 __ divl($tmp$$Register);
8253 __ xchgl($dst$$Register, $tmp2$$Register);
8254 __ divl($tmp$$Register);
8255 // revert result back to negative
8256 __ lneg($tmp2$$Register, $dst$$Register);
8257 __ jmpb(Ldone);
8259 __ bind(Lpos);
8260 __ divl($tmp$$Register); // Use unsigned division
8261 __ xchgl($dst$$Register, $tmp2$$Register);
8262 // Fallthrow for final divide, tmp2 has 32 bit hi result
8264 __ bind(Lfast);
8265 // fast path: src is positive
8266 __ divl($tmp$$Register); // Use unsigned division
8268 __ bind(Ldone);
8269 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8270 if (con < 0) {
8271 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8272 }
8273 %}
8274 ins_pipe( pipe_slow );
8275 %}
8277 // Remainder Register Long (remainder fit into 32 bits)
8278 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8279 match(Set dst (ModL dst imm));
8280 effect( TEMP tmp, TEMP tmp2, KILL cr );
8281 ins_cost(1000);
8282 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8283 "CMP $tmp,EDX\n\t"
8284 "JA,s fast\n\t"
8285 "MOV $tmp2,EAX\n\t"
8286 "MOV EAX,EDX\n\t"
8287 "MOV EDX,0\n\t"
8288 "JLE,s pos\n\t"
8289 "LNEG EAX : $tmp2\n\t"
8290 "DIV $tmp # unsigned division\n\t"
8291 "MOV EAX,$tmp2\n\t"
8292 "DIV $tmp\n\t"
8293 "NEG EDX\n\t"
8294 "JMP,s done\n"
8295 "pos:\n\t"
8296 "DIV $tmp\n\t"
8297 "MOV EAX,$tmp2\n"
8298 "fast:\n\t"
8299 "DIV $tmp\n"
8300 "done:\n\t"
8301 "MOV EAX,EDX\n\t"
8302 "SAR EDX,31\n\t" %}
8303 ins_encode %{
8304 int con = (int)$imm$$constant;
8305 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8306 int pcon = (con > 0) ? con : -con;
8307 Label Lfast, Lpos, Ldone;
8309 __ movl($tmp$$Register, pcon);
8310 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8311 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8313 __ movl($tmp2$$Register, $dst$$Register); // save
8314 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8315 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8316 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8318 // Negative dividend.
8319 // convert value to positive to use unsigned division
8320 __ lneg($dst$$Register, $tmp2$$Register);
8321 __ divl($tmp$$Register);
8322 __ movl($dst$$Register, $tmp2$$Register);
8323 __ divl($tmp$$Register);
8324 // revert remainder back to negative
8325 __ negl(HIGH_FROM_LOW($dst$$Register));
8326 __ jmpb(Ldone);
8328 __ bind(Lpos);
8329 __ divl($tmp$$Register);
8330 __ movl($dst$$Register, $tmp2$$Register);
8332 __ bind(Lfast);
8333 // fast path: src is positive
8334 __ divl($tmp$$Register);
8336 __ bind(Ldone);
8337 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8338 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8340 %}
8341 ins_pipe( pipe_slow );
8342 %}
8344 // Integer Shift Instructions
8345 // Shift Left by one
8346 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8347 match(Set dst (LShiftI dst shift));
8348 effect(KILL cr);
8350 size(2);
8351 format %{ "SHL $dst,$shift" %}
8352 opcode(0xD1, 0x4); /* D1 /4 */
8353 ins_encode( OpcP, RegOpc( dst ) );
8354 ins_pipe( ialu_reg );
8355 %}
8357 // Shift Left by 8-bit immediate
8358 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8359 match(Set dst (LShiftI dst shift));
8360 effect(KILL cr);
8362 size(3);
8363 format %{ "SHL $dst,$shift" %}
8364 opcode(0xC1, 0x4); /* C1 /4 ib */
8365 ins_encode( RegOpcImm( dst, shift) );
8366 ins_pipe( ialu_reg );
8367 %}
8369 // Shift Left by variable
8370 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8371 match(Set dst (LShiftI dst shift));
8372 effect(KILL cr);
8374 size(2);
8375 format %{ "SHL $dst,$shift" %}
8376 opcode(0xD3, 0x4); /* D3 /4 */
8377 ins_encode( OpcP, RegOpc( dst ) );
8378 ins_pipe( ialu_reg_reg );
8379 %}
8381 // Arithmetic shift right by one
8382 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8383 match(Set dst (RShiftI dst shift));
8384 effect(KILL cr);
8386 size(2);
8387 format %{ "SAR $dst,$shift" %}
8388 opcode(0xD1, 0x7); /* D1 /7 */
8389 ins_encode( OpcP, RegOpc( dst ) );
8390 ins_pipe( ialu_reg );
8391 %}
8393 // Arithmetic shift right by one
8394 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8395 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8396 effect(KILL cr);
8397 format %{ "SAR $dst,$shift" %}
8398 opcode(0xD1, 0x7); /* D1 /7 */
8399 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8400 ins_pipe( ialu_mem_imm );
8401 %}
8403 // Arithmetic Shift Right by 8-bit immediate
8404 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8405 match(Set dst (RShiftI dst shift));
8406 effect(KILL cr);
8408 size(3);
8409 format %{ "SAR $dst,$shift" %}
8410 opcode(0xC1, 0x7); /* C1 /7 ib */
8411 ins_encode( RegOpcImm( dst, shift ) );
8412 ins_pipe( ialu_mem_imm );
8413 %}
8415 // Arithmetic Shift Right by 8-bit immediate
8416 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8417 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8418 effect(KILL cr);
8420 format %{ "SAR $dst,$shift" %}
8421 opcode(0xC1, 0x7); /* C1 /7 ib */
8422 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8423 ins_pipe( ialu_mem_imm );
8424 %}
8426 // Arithmetic Shift Right by variable
8427 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8428 match(Set dst (RShiftI dst shift));
8429 effect(KILL cr);
8431 size(2);
8432 format %{ "SAR $dst,$shift" %}
8433 opcode(0xD3, 0x7); /* D3 /7 */
8434 ins_encode( OpcP, RegOpc( dst ) );
8435 ins_pipe( ialu_reg_reg );
8436 %}
8438 // Logical shift right by one
8439 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8440 match(Set dst (URShiftI dst shift));
8441 effect(KILL cr);
8443 size(2);
8444 format %{ "SHR $dst,$shift" %}
8445 opcode(0xD1, 0x5); /* D1 /5 */
8446 ins_encode( OpcP, RegOpc( dst ) );
8447 ins_pipe( ialu_reg );
8448 %}
8450 // Logical Shift Right by 8-bit immediate
8451 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8452 match(Set dst (URShiftI dst shift));
8453 effect(KILL cr);
8455 size(3);
8456 format %{ "SHR $dst,$shift" %}
8457 opcode(0xC1, 0x5); /* C1 /5 ib */
8458 ins_encode( RegOpcImm( dst, shift) );
8459 ins_pipe( ialu_reg );
8460 %}
8463 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8464 // This idiom is used by the compiler for the i2b bytecode.
8465 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8466 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8468 size(3);
8469 format %{ "MOVSX $dst,$src :8" %}
8470 ins_encode %{
8471 __ movsbl($dst$$Register, $src$$Register);
8472 %}
8473 ins_pipe(ialu_reg_reg);
8474 %}
8476 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8477 // This idiom is used by the compiler the i2s bytecode.
8478 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8479 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8481 size(3);
8482 format %{ "MOVSX $dst,$src :16" %}
8483 ins_encode %{
8484 __ movswl($dst$$Register, $src$$Register);
8485 %}
8486 ins_pipe(ialu_reg_reg);
8487 %}
8490 // Logical Shift Right by variable
8491 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8492 match(Set dst (URShiftI dst shift));
8493 effect(KILL cr);
8495 size(2);
8496 format %{ "SHR $dst,$shift" %}
8497 opcode(0xD3, 0x5); /* D3 /5 */
8498 ins_encode( OpcP, RegOpc( dst ) );
8499 ins_pipe( ialu_reg_reg );
8500 %}
8503 //----------Logical Instructions-----------------------------------------------
8504 //----------Integer Logical Instructions---------------------------------------
8505 // And Instructions
8506 // And Register with Register
8507 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8508 match(Set dst (AndI dst src));
8509 effect(KILL cr);
8511 size(2);
8512 format %{ "AND $dst,$src" %}
8513 opcode(0x23);
8514 ins_encode( OpcP, RegReg( dst, src) );
8515 ins_pipe( ialu_reg_reg );
8516 %}
8518 // And Register with Immediate
8519 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8520 match(Set dst (AndI dst src));
8521 effect(KILL cr);
8523 format %{ "AND $dst,$src" %}
8524 opcode(0x81,0x04); /* Opcode 81 /4 */
8525 // ins_encode( RegImm( dst, src) );
8526 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8527 ins_pipe( ialu_reg );
8528 %}
8530 // And Register with Memory
8531 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8532 match(Set dst (AndI dst (LoadI src)));
8533 effect(KILL cr);
8535 ins_cost(125);
8536 format %{ "AND $dst,$src" %}
8537 opcode(0x23);
8538 ins_encode( OpcP, RegMem( dst, src) );
8539 ins_pipe( ialu_reg_mem );
8540 %}
8542 // And Memory with Register
8543 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8544 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8545 effect(KILL cr);
8547 ins_cost(150);
8548 format %{ "AND $dst,$src" %}
8549 opcode(0x21); /* Opcode 21 /r */
8550 ins_encode( OpcP, RegMem( src, dst ) );
8551 ins_pipe( ialu_mem_reg );
8552 %}
8554 // And Memory with Immediate
8555 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8556 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8557 effect(KILL cr);
8559 ins_cost(125);
8560 format %{ "AND $dst,$src" %}
8561 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8562 // ins_encode( MemImm( dst, src) );
8563 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8564 ins_pipe( ialu_mem_imm );
8565 %}
8567 // Or Instructions
8568 // Or Register with Register
8569 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8570 match(Set dst (OrI dst src));
8571 effect(KILL cr);
8573 size(2);
8574 format %{ "OR $dst,$src" %}
8575 opcode(0x0B);
8576 ins_encode( OpcP, RegReg( dst, src) );
8577 ins_pipe( ialu_reg_reg );
8578 %}
8580 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8581 match(Set dst (OrI dst (CastP2X src)));
8582 effect(KILL cr);
8584 size(2);
8585 format %{ "OR $dst,$src" %}
8586 opcode(0x0B);
8587 ins_encode( OpcP, RegReg( dst, src) );
8588 ins_pipe( ialu_reg_reg );
8589 %}
8592 // Or Register with Immediate
8593 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8594 match(Set dst (OrI dst src));
8595 effect(KILL cr);
8597 format %{ "OR $dst,$src" %}
8598 opcode(0x81,0x01); /* Opcode 81 /1 id */
8599 // ins_encode( RegImm( dst, src) );
8600 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8601 ins_pipe( ialu_reg );
8602 %}
8604 // Or Register with Memory
8605 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8606 match(Set dst (OrI dst (LoadI src)));
8607 effect(KILL cr);
8609 ins_cost(125);
8610 format %{ "OR $dst,$src" %}
8611 opcode(0x0B);
8612 ins_encode( OpcP, RegMem( dst, src) );
8613 ins_pipe( ialu_reg_mem );
8614 %}
8616 // Or Memory with Register
8617 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8618 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8619 effect(KILL cr);
8621 ins_cost(150);
8622 format %{ "OR $dst,$src" %}
8623 opcode(0x09); /* Opcode 09 /r */
8624 ins_encode( OpcP, RegMem( src, dst ) );
8625 ins_pipe( ialu_mem_reg );
8626 %}
8628 // Or Memory with Immediate
8629 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8630 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8631 effect(KILL cr);
8633 ins_cost(125);
8634 format %{ "OR $dst,$src" %}
8635 opcode(0x81,0x1); /* Opcode 81 /1 id */
8636 // ins_encode( MemImm( dst, src) );
8637 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8638 ins_pipe( ialu_mem_imm );
8639 %}
8641 // ROL/ROR
8642 // ROL expand
8643 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8644 effect(USE_DEF dst, USE shift, KILL cr);
8646 format %{ "ROL $dst, $shift" %}
8647 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8648 ins_encode( OpcP, RegOpc( dst ));
8649 ins_pipe( ialu_reg );
8650 %}
8652 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8653 effect(USE_DEF dst, USE shift, KILL cr);
8655 format %{ "ROL $dst, $shift" %}
8656 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8657 ins_encode( RegOpcImm(dst, shift) );
8658 ins_pipe(ialu_reg);
8659 %}
8661 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8662 effect(USE_DEF dst, USE shift, KILL cr);
8664 format %{ "ROL $dst, $shift" %}
8665 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8666 ins_encode(OpcP, RegOpc(dst));
8667 ins_pipe( ialu_reg_reg );
8668 %}
8669 // end of ROL expand
8671 // ROL 32bit by one once
8672 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8673 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8675 expand %{
8676 rolI_eReg_imm1(dst, lshift, cr);
8677 %}
8678 %}
8680 // ROL 32bit var by imm8 once
8681 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8682 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8683 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8685 expand %{
8686 rolI_eReg_imm8(dst, lshift, cr);
8687 %}
8688 %}
8690 // ROL 32bit var by var once
8691 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8692 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8694 expand %{
8695 rolI_eReg_CL(dst, shift, cr);
8696 %}
8697 %}
8699 // ROL 32bit var by var once
8700 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8701 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8703 expand %{
8704 rolI_eReg_CL(dst, shift, cr);
8705 %}
8706 %}
8708 // ROR expand
8709 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8710 effect(USE_DEF dst, USE shift, KILL cr);
8712 format %{ "ROR $dst, $shift" %}
8713 opcode(0xD1,0x1); /* Opcode D1 /1 */
8714 ins_encode( OpcP, RegOpc( dst ) );
8715 ins_pipe( ialu_reg );
8716 %}
8718 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8719 effect (USE_DEF dst, USE shift, KILL cr);
8721 format %{ "ROR $dst, $shift" %}
8722 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8723 ins_encode( RegOpcImm(dst, shift) );
8724 ins_pipe( ialu_reg );
8725 %}
8727 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8728 effect(USE_DEF dst, USE shift, KILL cr);
8730 format %{ "ROR $dst, $shift" %}
8731 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8732 ins_encode(OpcP, RegOpc(dst));
8733 ins_pipe( ialu_reg_reg );
8734 %}
8735 // end of ROR expand
8737 // ROR right once
8738 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8739 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8741 expand %{
8742 rorI_eReg_imm1(dst, rshift, cr);
8743 %}
8744 %}
8746 // ROR 32bit by immI8 once
8747 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8748 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8749 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8751 expand %{
8752 rorI_eReg_imm8(dst, rshift, cr);
8753 %}
8754 %}
8756 // ROR 32bit var by var once
8757 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8758 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8760 expand %{
8761 rorI_eReg_CL(dst, shift, cr);
8762 %}
8763 %}
8765 // ROR 32bit var by var once
8766 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8767 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8769 expand %{
8770 rorI_eReg_CL(dst, shift, cr);
8771 %}
8772 %}
8774 // Xor Instructions
8775 // Xor Register with Register
8776 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8777 match(Set dst (XorI dst src));
8778 effect(KILL cr);
8780 size(2);
8781 format %{ "XOR $dst,$src" %}
8782 opcode(0x33);
8783 ins_encode( OpcP, RegReg( dst, src) );
8784 ins_pipe( ialu_reg_reg );
8785 %}
8787 // Xor Register with Immediate -1
8788 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8789 match(Set dst (XorI dst imm));
8791 size(2);
8792 format %{ "NOT $dst" %}
8793 ins_encode %{
8794 __ notl($dst$$Register);
8795 %}
8796 ins_pipe( ialu_reg );
8797 %}
8799 // Xor Register with Immediate
8800 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8801 match(Set dst (XorI dst src));
8802 effect(KILL cr);
8804 format %{ "XOR $dst,$src" %}
8805 opcode(0x81,0x06); /* Opcode 81 /6 id */
8806 // ins_encode( RegImm( dst, src) );
8807 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8808 ins_pipe( ialu_reg );
8809 %}
8811 // Xor Register with Memory
8812 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8813 match(Set dst (XorI dst (LoadI src)));
8814 effect(KILL cr);
8816 ins_cost(125);
8817 format %{ "XOR $dst,$src" %}
8818 opcode(0x33);
8819 ins_encode( OpcP, RegMem(dst, src) );
8820 ins_pipe( ialu_reg_mem );
8821 %}
8823 // Xor Memory with Register
8824 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8825 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8826 effect(KILL cr);
8828 ins_cost(150);
8829 format %{ "XOR $dst,$src" %}
8830 opcode(0x31); /* Opcode 31 /r */
8831 ins_encode( OpcP, RegMem( src, dst ) );
8832 ins_pipe( ialu_mem_reg );
8833 %}
8835 // Xor Memory with Immediate
8836 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8837 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8838 effect(KILL cr);
8840 ins_cost(125);
8841 format %{ "XOR $dst,$src" %}
8842 opcode(0x81,0x6); /* Opcode 81 /6 id */
8843 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8844 ins_pipe( ialu_mem_imm );
8845 %}
8847 //----------Convert Int to Boolean---------------------------------------------
8849 instruct movI_nocopy(rRegI dst, rRegI src) %{
8850 effect( DEF dst, USE src );
8851 format %{ "MOV $dst,$src" %}
8852 ins_encode( enc_Copy( dst, src) );
8853 ins_pipe( ialu_reg_reg );
8854 %}
8856 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8857 effect( USE_DEF dst, USE src, KILL cr );
8859 size(4);
8860 format %{ "NEG $dst\n\t"
8861 "ADC $dst,$src" %}
8862 ins_encode( neg_reg(dst),
8863 OpcRegReg(0x13,dst,src) );
8864 ins_pipe( ialu_reg_reg_long );
8865 %}
8867 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8868 match(Set dst (Conv2B src));
8870 expand %{
8871 movI_nocopy(dst,src);
8872 ci2b(dst,src,cr);
8873 %}
8874 %}
8876 instruct movP_nocopy(rRegI dst, eRegP src) %{
8877 effect( DEF dst, USE src );
8878 format %{ "MOV $dst,$src" %}
8879 ins_encode( enc_Copy( dst, src) );
8880 ins_pipe( ialu_reg_reg );
8881 %}
8883 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8884 effect( USE_DEF dst, USE src, KILL cr );
8885 format %{ "NEG $dst\n\t"
8886 "ADC $dst,$src" %}
8887 ins_encode( neg_reg(dst),
8888 OpcRegReg(0x13,dst,src) );
8889 ins_pipe( ialu_reg_reg_long );
8890 %}
8892 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8893 match(Set dst (Conv2B src));
8895 expand %{
8896 movP_nocopy(dst,src);
8897 cp2b(dst,src,cr);
8898 %}
8899 %}
8901 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8902 match(Set dst (CmpLTMask p q));
8903 effect( KILL cr );
8904 ins_cost(400);
8906 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8907 format %{ "XOR $dst,$dst\n\t"
8908 "CMP $p,$q\n\t"
8909 "SETlt $dst\n\t"
8910 "NEG $dst" %}
8911 ins_encode( OpcRegReg(0x33,dst,dst),
8912 OpcRegReg(0x3B,p,q),
8913 setLT_reg(dst), neg_reg(dst) );
8914 ins_pipe( pipe_slow );
8915 %}
8917 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8918 match(Set dst (CmpLTMask dst zero));
8919 effect( DEF dst, KILL cr );
8920 ins_cost(100);
8922 format %{ "SAR $dst,31" %}
8923 opcode(0xC1, 0x7); /* C1 /7 ib */
8924 ins_encode( RegOpcImm( dst, 0x1F ) );
8925 ins_pipe( ialu_reg );
8926 %}
8929 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8930 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8931 effect( KILL tmp, KILL cr );
8932 ins_cost(400);
8933 // annoyingly, $tmp has no edges so you cant ask for it in
8934 // any format or encoding
8935 format %{ "SUB $p,$q\n\t"
8936 "SBB ECX,ECX\n\t"
8937 "AND ECX,$y\n\t"
8938 "ADD $p,ECX" %}
8939 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8940 ins_pipe( pipe_cmplt );
8941 %}
8943 /* If I enable this, I encourage spilling in the inner loop of compress.
8944 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8945 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8946 effect( USE_KILL tmp, KILL cr );
8947 ins_cost(400);
8949 format %{ "SUB $p,$q\n\t"
8950 "SBB ECX,ECX\n\t"
8951 "AND ECX,$y\n\t"
8952 "ADD $p,ECX" %}
8953 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8954 %}
8955 */
8957 //----------Long Instructions------------------------------------------------
8958 // Add Long Register with Register
8959 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8960 match(Set dst (AddL dst src));
8961 effect(KILL cr);
8962 ins_cost(200);
8963 format %{ "ADD $dst.lo,$src.lo\n\t"
8964 "ADC $dst.hi,$src.hi" %}
8965 opcode(0x03, 0x13);
8966 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8967 ins_pipe( ialu_reg_reg_long );
8968 %}
8970 // Add Long Register with Immediate
8971 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8972 match(Set dst (AddL dst src));
8973 effect(KILL cr);
8974 format %{ "ADD $dst.lo,$src.lo\n\t"
8975 "ADC $dst.hi,$src.hi" %}
8976 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8977 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8978 ins_pipe( ialu_reg_long );
8979 %}
8981 // Add Long Register with Memory
8982 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8983 match(Set dst (AddL dst (LoadL mem)));
8984 effect(KILL cr);
8985 ins_cost(125);
8986 format %{ "ADD $dst.lo,$mem\n\t"
8987 "ADC $dst.hi,$mem+4" %}
8988 opcode(0x03, 0x13);
8989 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8990 ins_pipe( ialu_reg_long_mem );
8991 %}
8993 // Subtract Long Register with Register.
8994 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8995 match(Set dst (SubL dst src));
8996 effect(KILL cr);
8997 ins_cost(200);
8998 format %{ "SUB $dst.lo,$src.lo\n\t"
8999 "SBB $dst.hi,$src.hi" %}
9000 opcode(0x2B, 0x1B);
9001 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9002 ins_pipe( ialu_reg_reg_long );
9003 %}
9005 // Subtract Long Register with Immediate
9006 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9007 match(Set dst (SubL dst src));
9008 effect(KILL cr);
9009 format %{ "SUB $dst.lo,$src.lo\n\t"
9010 "SBB $dst.hi,$src.hi" %}
9011 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9012 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9013 ins_pipe( ialu_reg_long );
9014 %}
9016 // Subtract Long Register with Memory
9017 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9018 match(Set dst (SubL dst (LoadL mem)));
9019 effect(KILL cr);
9020 ins_cost(125);
9021 format %{ "SUB $dst.lo,$mem\n\t"
9022 "SBB $dst.hi,$mem+4" %}
9023 opcode(0x2B, 0x1B);
9024 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9025 ins_pipe( ialu_reg_long_mem );
9026 %}
9028 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9029 match(Set dst (SubL zero dst));
9030 effect(KILL cr);
9031 ins_cost(300);
9032 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9033 ins_encode( neg_long(dst) );
9034 ins_pipe( ialu_reg_reg_long );
9035 %}
9037 // And Long Register with Register
9038 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9039 match(Set dst (AndL dst src));
9040 effect(KILL cr);
9041 format %{ "AND $dst.lo,$src.lo\n\t"
9042 "AND $dst.hi,$src.hi" %}
9043 opcode(0x23,0x23);
9044 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9045 ins_pipe( ialu_reg_reg_long );
9046 %}
9048 // And Long Register with Immediate
9049 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9050 match(Set dst (AndL dst src));
9051 effect(KILL cr);
9052 format %{ "AND $dst.lo,$src.lo\n\t"
9053 "AND $dst.hi,$src.hi" %}
9054 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9055 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9056 ins_pipe( ialu_reg_long );
9057 %}
9059 // And Long Register with Memory
9060 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9061 match(Set dst (AndL dst (LoadL mem)));
9062 effect(KILL cr);
9063 ins_cost(125);
9064 format %{ "AND $dst.lo,$mem\n\t"
9065 "AND $dst.hi,$mem+4" %}
9066 opcode(0x23, 0x23);
9067 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9068 ins_pipe( ialu_reg_long_mem );
9069 %}
9071 // Or Long Register with Register
9072 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9073 match(Set dst (OrL dst src));
9074 effect(KILL cr);
9075 format %{ "OR $dst.lo,$src.lo\n\t"
9076 "OR $dst.hi,$src.hi" %}
9077 opcode(0x0B,0x0B);
9078 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9079 ins_pipe( ialu_reg_reg_long );
9080 %}
9082 // Or Long Register with Immediate
9083 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9084 match(Set dst (OrL dst src));
9085 effect(KILL cr);
9086 format %{ "OR $dst.lo,$src.lo\n\t"
9087 "OR $dst.hi,$src.hi" %}
9088 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9089 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9090 ins_pipe( ialu_reg_long );
9091 %}
9093 // Or Long Register with Memory
9094 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9095 match(Set dst (OrL dst (LoadL mem)));
9096 effect(KILL cr);
9097 ins_cost(125);
9098 format %{ "OR $dst.lo,$mem\n\t"
9099 "OR $dst.hi,$mem+4" %}
9100 opcode(0x0B,0x0B);
9101 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9102 ins_pipe( ialu_reg_long_mem );
9103 %}
9105 // Xor Long Register with Register
9106 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9107 match(Set dst (XorL dst src));
9108 effect(KILL cr);
9109 format %{ "XOR $dst.lo,$src.lo\n\t"
9110 "XOR $dst.hi,$src.hi" %}
9111 opcode(0x33,0x33);
9112 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9113 ins_pipe( ialu_reg_reg_long );
9114 %}
9116 // Xor Long Register with Immediate -1
9117 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9118 match(Set dst (XorL dst imm));
9119 format %{ "NOT $dst.lo\n\t"
9120 "NOT $dst.hi" %}
9121 ins_encode %{
9122 __ notl($dst$$Register);
9123 __ notl(HIGH_FROM_LOW($dst$$Register));
9124 %}
9125 ins_pipe( ialu_reg_long );
9126 %}
9128 // Xor Long Register with Immediate
9129 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9130 match(Set dst (XorL dst src));
9131 effect(KILL cr);
9132 format %{ "XOR $dst.lo,$src.lo\n\t"
9133 "XOR $dst.hi,$src.hi" %}
9134 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9135 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9136 ins_pipe( ialu_reg_long );
9137 %}
9139 // Xor Long Register with Memory
9140 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9141 match(Set dst (XorL dst (LoadL mem)));
9142 effect(KILL cr);
9143 ins_cost(125);
9144 format %{ "XOR $dst.lo,$mem\n\t"
9145 "XOR $dst.hi,$mem+4" %}
9146 opcode(0x33,0x33);
9147 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9148 ins_pipe( ialu_reg_long_mem );
9149 %}
9151 // Shift Left Long by 1
9152 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9153 predicate(UseNewLongLShift);
9154 match(Set dst (LShiftL dst cnt));
9155 effect(KILL cr);
9156 ins_cost(100);
9157 format %{ "ADD $dst.lo,$dst.lo\n\t"
9158 "ADC $dst.hi,$dst.hi" %}
9159 ins_encode %{
9160 __ addl($dst$$Register,$dst$$Register);
9161 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9162 %}
9163 ins_pipe( ialu_reg_long );
9164 %}
9166 // Shift Left Long by 2
9167 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9168 predicate(UseNewLongLShift);
9169 match(Set dst (LShiftL dst cnt));
9170 effect(KILL cr);
9171 ins_cost(100);
9172 format %{ "ADD $dst.lo,$dst.lo\n\t"
9173 "ADC $dst.hi,$dst.hi\n\t"
9174 "ADD $dst.lo,$dst.lo\n\t"
9175 "ADC $dst.hi,$dst.hi" %}
9176 ins_encode %{
9177 __ addl($dst$$Register,$dst$$Register);
9178 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9179 __ addl($dst$$Register,$dst$$Register);
9180 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9181 %}
9182 ins_pipe( ialu_reg_long );
9183 %}
9185 // Shift Left Long by 3
9186 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9187 predicate(UseNewLongLShift);
9188 match(Set dst (LShiftL dst cnt));
9189 effect(KILL cr);
9190 ins_cost(100);
9191 format %{ "ADD $dst.lo,$dst.lo\n\t"
9192 "ADC $dst.hi,$dst.hi\n\t"
9193 "ADD $dst.lo,$dst.lo\n\t"
9194 "ADC $dst.hi,$dst.hi\n\t"
9195 "ADD $dst.lo,$dst.lo\n\t"
9196 "ADC $dst.hi,$dst.hi" %}
9197 ins_encode %{
9198 __ addl($dst$$Register,$dst$$Register);
9199 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9200 __ addl($dst$$Register,$dst$$Register);
9201 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9202 __ addl($dst$$Register,$dst$$Register);
9203 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9204 %}
9205 ins_pipe( ialu_reg_long );
9206 %}
9208 // Shift Left Long by 1-31
9209 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9210 match(Set dst (LShiftL dst cnt));
9211 effect(KILL cr);
9212 ins_cost(200);
9213 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9214 "SHL $dst.lo,$cnt" %}
9215 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9216 ins_encode( move_long_small_shift(dst,cnt) );
9217 ins_pipe( ialu_reg_long );
9218 %}
9220 // Shift Left Long by 32-63
9221 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9222 match(Set dst (LShiftL dst cnt));
9223 effect(KILL cr);
9224 ins_cost(300);
9225 format %{ "MOV $dst.hi,$dst.lo\n"
9226 "\tSHL $dst.hi,$cnt-32\n"
9227 "\tXOR $dst.lo,$dst.lo" %}
9228 opcode(0xC1, 0x4); /* C1 /4 ib */
9229 ins_encode( move_long_big_shift_clr(dst,cnt) );
9230 ins_pipe( ialu_reg_long );
9231 %}
9233 // Shift Left Long by variable
9234 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9235 match(Set dst (LShiftL dst shift));
9236 effect(KILL cr);
9237 ins_cost(500+200);
9238 size(17);
9239 format %{ "TEST $shift,32\n\t"
9240 "JEQ,s small\n\t"
9241 "MOV $dst.hi,$dst.lo\n\t"
9242 "XOR $dst.lo,$dst.lo\n"
9243 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9244 "SHL $dst.lo,$shift" %}
9245 ins_encode( shift_left_long( dst, shift ) );
9246 ins_pipe( pipe_slow );
9247 %}
9249 // Shift Right Long by 1-31
9250 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9251 match(Set dst (URShiftL dst cnt));
9252 effect(KILL cr);
9253 ins_cost(200);
9254 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9255 "SHR $dst.hi,$cnt" %}
9256 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9257 ins_encode( move_long_small_shift(dst,cnt) );
9258 ins_pipe( ialu_reg_long );
9259 %}
9261 // Shift Right Long by 32-63
9262 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9263 match(Set dst (URShiftL dst cnt));
9264 effect(KILL cr);
9265 ins_cost(300);
9266 format %{ "MOV $dst.lo,$dst.hi\n"
9267 "\tSHR $dst.lo,$cnt-32\n"
9268 "\tXOR $dst.hi,$dst.hi" %}
9269 opcode(0xC1, 0x5); /* C1 /5 ib */
9270 ins_encode( move_long_big_shift_clr(dst,cnt) );
9271 ins_pipe( ialu_reg_long );
9272 %}
9274 // Shift Right Long by variable
9275 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9276 match(Set dst (URShiftL dst shift));
9277 effect(KILL cr);
9278 ins_cost(600);
9279 size(17);
9280 format %{ "TEST $shift,32\n\t"
9281 "JEQ,s small\n\t"
9282 "MOV $dst.lo,$dst.hi\n\t"
9283 "XOR $dst.hi,$dst.hi\n"
9284 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9285 "SHR $dst.hi,$shift" %}
9286 ins_encode( shift_right_long( dst, shift ) );
9287 ins_pipe( pipe_slow );
9288 %}
9290 // Shift Right Long by 1-31
9291 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9292 match(Set dst (RShiftL dst cnt));
9293 effect(KILL cr);
9294 ins_cost(200);
9295 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9296 "SAR $dst.hi,$cnt" %}
9297 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9298 ins_encode( move_long_small_shift(dst,cnt) );
9299 ins_pipe( ialu_reg_long );
9300 %}
9302 // Shift Right Long by 32-63
9303 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9304 match(Set dst (RShiftL dst cnt));
9305 effect(KILL cr);
9306 ins_cost(300);
9307 format %{ "MOV $dst.lo,$dst.hi\n"
9308 "\tSAR $dst.lo,$cnt-32\n"
9309 "\tSAR $dst.hi,31" %}
9310 opcode(0xC1, 0x7); /* C1 /7 ib */
9311 ins_encode( move_long_big_shift_sign(dst,cnt) );
9312 ins_pipe( ialu_reg_long );
9313 %}
9315 // Shift Right arithmetic Long by variable
9316 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9317 match(Set dst (RShiftL dst shift));
9318 effect(KILL cr);
9319 ins_cost(600);
9320 size(18);
9321 format %{ "TEST $shift,32\n\t"
9322 "JEQ,s small\n\t"
9323 "MOV $dst.lo,$dst.hi\n\t"
9324 "SAR $dst.hi,31\n"
9325 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9326 "SAR $dst.hi,$shift" %}
9327 ins_encode( shift_right_arith_long( dst, shift ) );
9328 ins_pipe( pipe_slow );
9329 %}
9332 //----------Double Instructions------------------------------------------------
9333 // Double Math
9335 // Compare & branch
9337 // P6 version of float compare, sets condition codes in EFLAGS
9338 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9339 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9340 match(Set cr (CmpD src1 src2));
9341 effect(KILL rax);
9342 ins_cost(150);
9343 format %{ "FLD $src1\n\t"
9344 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9345 "JNP exit\n\t"
9346 "MOV ah,1 // saw a NaN, set CF\n\t"
9347 "SAHF\n"
9348 "exit:\tNOP // avoid branch to branch" %}
9349 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9350 ins_encode( Push_Reg_DPR(src1),
9351 OpcP, RegOpc(src2),
9352 cmpF_P6_fixup );
9353 ins_pipe( pipe_slow );
9354 %}
9356 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9357 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9358 match(Set cr (CmpD src1 src2));
9359 ins_cost(150);
9360 format %{ "FLD $src1\n\t"
9361 "FUCOMIP ST,$src2 // P6 instruction" %}
9362 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9363 ins_encode( Push_Reg_DPR(src1),
9364 OpcP, RegOpc(src2));
9365 ins_pipe( pipe_slow );
9366 %}
9368 // Compare & branch
9369 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9370 predicate(UseSSE<=1);
9371 match(Set cr (CmpD src1 src2));
9372 effect(KILL rax);
9373 ins_cost(200);
9374 format %{ "FLD $src1\n\t"
9375 "FCOMp $src2\n\t"
9376 "FNSTSW AX\n\t"
9377 "TEST AX,0x400\n\t"
9378 "JZ,s flags\n\t"
9379 "MOV AH,1\t# unordered treat as LT\n"
9380 "flags:\tSAHF" %}
9381 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9382 ins_encode( Push_Reg_DPR(src1),
9383 OpcP, RegOpc(src2),
9384 fpu_flags);
9385 ins_pipe( pipe_slow );
9386 %}
9388 // Compare vs zero into -1,0,1
9389 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9390 predicate(UseSSE<=1);
9391 match(Set dst (CmpD3 src1 zero));
9392 effect(KILL cr, KILL rax);
9393 ins_cost(280);
9394 format %{ "FTSTD $dst,$src1" %}
9395 opcode(0xE4, 0xD9);
9396 ins_encode( Push_Reg_DPR(src1),
9397 OpcS, OpcP, PopFPU,
9398 CmpF_Result(dst));
9399 ins_pipe( pipe_slow );
9400 %}
9402 // Compare into -1,0,1
9403 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9404 predicate(UseSSE<=1);
9405 match(Set dst (CmpD3 src1 src2));
9406 effect(KILL cr, KILL rax);
9407 ins_cost(300);
9408 format %{ "FCMPD $dst,$src1,$src2" %}
9409 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9410 ins_encode( Push_Reg_DPR(src1),
9411 OpcP, RegOpc(src2),
9412 CmpF_Result(dst));
9413 ins_pipe( pipe_slow );
9414 %}
9416 // float compare and set condition codes in EFLAGS by XMM regs
9417 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9418 predicate(UseSSE>=2);
9419 match(Set cr (CmpD src1 src2));
9420 ins_cost(145);
9421 format %{ "UCOMISD $src1,$src2\n\t"
9422 "JNP,s exit\n\t"
9423 "PUSHF\t# saw NaN, set CF\n\t"
9424 "AND [rsp], #0xffffff2b\n\t"
9425 "POPF\n"
9426 "exit:" %}
9427 ins_encode %{
9428 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9429 emit_cmpfp_fixup(_masm);
9430 %}
9431 ins_pipe( pipe_slow );
9432 %}
9434 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9435 predicate(UseSSE>=2);
9436 match(Set cr (CmpD src1 src2));
9437 ins_cost(100);
9438 format %{ "UCOMISD $src1,$src2" %}
9439 ins_encode %{
9440 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9441 %}
9442 ins_pipe( pipe_slow );
9443 %}
9445 // float compare and set condition codes in EFLAGS by XMM regs
9446 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9447 predicate(UseSSE>=2);
9448 match(Set cr (CmpD src1 (LoadD src2)));
9449 ins_cost(145);
9450 format %{ "UCOMISD $src1,$src2\n\t"
9451 "JNP,s exit\n\t"
9452 "PUSHF\t# saw NaN, set CF\n\t"
9453 "AND [rsp], #0xffffff2b\n\t"
9454 "POPF\n"
9455 "exit:" %}
9456 ins_encode %{
9457 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9458 emit_cmpfp_fixup(_masm);
9459 %}
9460 ins_pipe( pipe_slow );
9461 %}
9463 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9464 predicate(UseSSE>=2);
9465 match(Set cr (CmpD src1 (LoadD src2)));
9466 ins_cost(100);
9467 format %{ "UCOMISD $src1,$src2" %}
9468 ins_encode %{
9469 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9470 %}
9471 ins_pipe( pipe_slow );
9472 %}
9474 // Compare into -1,0,1 in XMM
9475 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9476 predicate(UseSSE>=2);
9477 match(Set dst (CmpD3 src1 src2));
9478 effect(KILL cr);
9479 ins_cost(255);
9480 format %{ "UCOMISD $src1, $src2\n\t"
9481 "MOV $dst, #-1\n\t"
9482 "JP,s done\n\t"
9483 "JB,s done\n\t"
9484 "SETNE $dst\n\t"
9485 "MOVZB $dst, $dst\n"
9486 "done:" %}
9487 ins_encode %{
9488 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9489 emit_cmpfp3(_masm, $dst$$Register);
9490 %}
9491 ins_pipe( pipe_slow );
9492 %}
9494 // Compare into -1,0,1 in XMM and memory
9495 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9496 predicate(UseSSE>=2);
9497 match(Set dst (CmpD3 src1 (LoadD src2)));
9498 effect(KILL cr);
9499 ins_cost(275);
9500 format %{ "UCOMISD $src1, $src2\n\t"
9501 "MOV $dst, #-1\n\t"
9502 "JP,s done\n\t"
9503 "JB,s done\n\t"
9504 "SETNE $dst\n\t"
9505 "MOVZB $dst, $dst\n"
9506 "done:" %}
9507 ins_encode %{
9508 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9509 emit_cmpfp3(_masm, $dst$$Register);
9510 %}
9511 ins_pipe( pipe_slow );
9512 %}
9515 instruct subDPR_reg(regDPR dst, regDPR src) %{
9516 predicate (UseSSE <=1);
9517 match(Set dst (SubD dst src));
9519 format %{ "FLD $src\n\t"
9520 "DSUBp $dst,ST" %}
9521 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9522 ins_cost(150);
9523 ins_encode( Push_Reg_DPR(src),
9524 OpcP, RegOpc(dst) );
9525 ins_pipe( fpu_reg_reg );
9526 %}
9528 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9529 predicate (UseSSE <=1);
9530 match(Set dst (RoundDouble (SubD src1 src2)));
9531 ins_cost(250);
9533 format %{ "FLD $src2\n\t"
9534 "DSUB ST,$src1\n\t"
9535 "FSTP_D $dst\t# D-round" %}
9536 opcode(0xD8, 0x5);
9537 ins_encode( Push_Reg_DPR(src2),
9538 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9539 ins_pipe( fpu_mem_reg_reg );
9540 %}
9543 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9544 predicate (UseSSE <=1);
9545 match(Set dst (SubD dst (LoadD src)));
9546 ins_cost(150);
9548 format %{ "FLD $src\n\t"
9549 "DSUBp $dst,ST" %}
9550 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9551 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9552 OpcP, RegOpc(dst) );
9553 ins_pipe( fpu_reg_mem );
9554 %}
9556 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9557 predicate (UseSSE<=1);
9558 match(Set dst (AbsD src));
9559 ins_cost(100);
9560 format %{ "FABS" %}
9561 opcode(0xE1, 0xD9);
9562 ins_encode( OpcS, OpcP );
9563 ins_pipe( fpu_reg_reg );
9564 %}
9566 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9567 predicate(UseSSE<=1);
9568 match(Set dst (NegD src));
9569 ins_cost(100);
9570 format %{ "FCHS" %}
9571 opcode(0xE0, 0xD9);
9572 ins_encode( OpcS, OpcP );
9573 ins_pipe( fpu_reg_reg );
9574 %}
9576 instruct addDPR_reg(regDPR dst, regDPR src) %{
9577 predicate(UseSSE<=1);
9578 match(Set dst (AddD dst src));
9579 format %{ "FLD $src\n\t"
9580 "DADD $dst,ST" %}
9581 size(4);
9582 ins_cost(150);
9583 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9584 ins_encode( Push_Reg_DPR(src),
9585 OpcP, RegOpc(dst) );
9586 ins_pipe( fpu_reg_reg );
9587 %}
9590 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9591 predicate(UseSSE<=1);
9592 match(Set dst (RoundDouble (AddD src1 src2)));
9593 ins_cost(250);
9595 format %{ "FLD $src2\n\t"
9596 "DADD ST,$src1\n\t"
9597 "FSTP_D $dst\t# D-round" %}
9598 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9599 ins_encode( Push_Reg_DPR(src2),
9600 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9601 ins_pipe( fpu_mem_reg_reg );
9602 %}
9605 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9606 predicate(UseSSE<=1);
9607 match(Set dst (AddD dst (LoadD src)));
9608 ins_cost(150);
9610 format %{ "FLD $src\n\t"
9611 "DADDp $dst,ST" %}
9612 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9613 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9614 OpcP, RegOpc(dst) );
9615 ins_pipe( fpu_reg_mem );
9616 %}
9618 // add-to-memory
9619 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9620 predicate(UseSSE<=1);
9621 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9622 ins_cost(150);
9624 format %{ "FLD_D $dst\n\t"
9625 "DADD ST,$src\n\t"
9626 "FST_D $dst" %}
9627 opcode(0xDD, 0x0);
9628 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9629 Opcode(0xD8), RegOpc(src),
9630 set_instruction_start,
9631 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9632 ins_pipe( fpu_reg_mem );
9633 %}
9635 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9636 predicate(UseSSE<=1);
9637 match(Set dst (AddD dst con));
9638 ins_cost(125);
9639 format %{ "FLD1\n\t"
9640 "DADDp $dst,ST" %}
9641 ins_encode %{
9642 __ fld1();
9643 __ faddp($dst$$reg);
9644 %}
9645 ins_pipe(fpu_reg);
9646 %}
9648 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9649 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9650 match(Set dst (AddD dst con));
9651 ins_cost(200);
9652 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9653 "DADDp $dst,ST" %}
9654 ins_encode %{
9655 __ fld_d($constantaddress($con));
9656 __ faddp($dst$$reg);
9657 %}
9658 ins_pipe(fpu_reg_mem);
9659 %}
9661 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9662 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9663 match(Set dst (RoundDouble (AddD src con)));
9664 ins_cost(200);
9665 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9666 "DADD ST,$src\n\t"
9667 "FSTP_D $dst\t# D-round" %}
9668 ins_encode %{
9669 __ fld_d($constantaddress($con));
9670 __ fadd($src$$reg);
9671 __ fstp_d(Address(rsp, $dst$$disp));
9672 %}
9673 ins_pipe(fpu_mem_reg_con);
9674 %}
9676 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9677 predicate(UseSSE<=1);
9678 match(Set dst (MulD dst src));
9679 format %{ "FLD $src\n\t"
9680 "DMULp $dst,ST" %}
9681 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9682 ins_cost(150);
9683 ins_encode( Push_Reg_DPR(src),
9684 OpcP, RegOpc(dst) );
9685 ins_pipe( fpu_reg_reg );
9686 %}
9688 // Strict FP instruction biases argument before multiply then
9689 // biases result to avoid double rounding of subnormals.
9690 //
9691 // scale arg1 by multiplying arg1 by 2^(-15360)
9692 // load arg2
9693 // multiply scaled arg1 by arg2
9694 // rescale product by 2^(15360)
9695 //
9696 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9697 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9698 match(Set dst (MulD dst src));
9699 ins_cost(1); // Select this instruction for all strict FP double multiplies
9701 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9702 "DMULp $dst,ST\n\t"
9703 "FLD $src\n\t"
9704 "DMULp $dst,ST\n\t"
9705 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9706 "DMULp $dst,ST\n\t" %}
9707 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9708 ins_encode( strictfp_bias1(dst),
9709 Push_Reg_DPR(src),
9710 OpcP, RegOpc(dst),
9711 strictfp_bias2(dst) );
9712 ins_pipe( fpu_reg_reg );
9713 %}
9715 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9716 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9717 match(Set dst (MulD dst con));
9718 ins_cost(200);
9719 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9720 "DMULp $dst,ST" %}
9721 ins_encode %{
9722 __ fld_d($constantaddress($con));
9723 __ fmulp($dst$$reg);
9724 %}
9725 ins_pipe(fpu_reg_mem);
9726 %}
9729 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9730 predicate( UseSSE<=1 );
9731 match(Set dst (MulD dst (LoadD src)));
9732 ins_cost(200);
9733 format %{ "FLD_D $src\n\t"
9734 "DMULp $dst,ST" %}
9735 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9736 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9737 OpcP, RegOpc(dst) );
9738 ins_pipe( fpu_reg_mem );
9739 %}
9741 //
9742 // Cisc-alternate to reg-reg multiply
9743 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9744 predicate( UseSSE<=1 );
9745 match(Set dst (MulD src (LoadD mem)));
9746 ins_cost(250);
9747 format %{ "FLD_D $mem\n\t"
9748 "DMUL ST,$src\n\t"
9749 "FSTP_D $dst" %}
9750 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9751 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9752 OpcReg_FPR(src),
9753 Pop_Reg_DPR(dst) );
9754 ins_pipe( fpu_reg_reg_mem );
9755 %}
9758 // MACRO3 -- addDPR a mulDPR
9759 // This instruction is a '2-address' instruction in that the result goes
9760 // back to src2. This eliminates a move from the macro; possibly the
9761 // register allocator will have to add it back (and maybe not).
9762 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9763 predicate( UseSSE<=1 );
9764 match(Set src2 (AddD (MulD src0 src1) src2));
9765 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9766 "DMUL ST,$src1\n\t"
9767 "DADDp $src2,ST" %}
9768 ins_cost(250);
9769 opcode(0xDD); /* LoadD DD /0 */
9770 ins_encode( Push_Reg_FPR(src0),
9771 FMul_ST_reg(src1),
9772 FAddP_reg_ST(src2) );
9773 ins_pipe( fpu_reg_reg_reg );
9774 %}
9777 // MACRO3 -- subDPR a mulDPR
9778 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9779 predicate( UseSSE<=1 );
9780 match(Set src2 (SubD (MulD src0 src1) src2));
9781 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9782 "DMUL ST,$src1\n\t"
9783 "DSUBRp $src2,ST" %}
9784 ins_cost(250);
9785 ins_encode( Push_Reg_FPR(src0),
9786 FMul_ST_reg(src1),
9787 Opcode(0xDE), Opc_plus(0xE0,src2));
9788 ins_pipe( fpu_reg_reg_reg );
9789 %}
9792 instruct divDPR_reg(regDPR dst, regDPR src) %{
9793 predicate( UseSSE<=1 );
9794 match(Set dst (DivD dst src));
9796 format %{ "FLD $src\n\t"
9797 "FDIVp $dst,ST" %}
9798 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9799 ins_cost(150);
9800 ins_encode( Push_Reg_DPR(src),
9801 OpcP, RegOpc(dst) );
9802 ins_pipe( fpu_reg_reg );
9803 %}
9805 // Strict FP instruction biases argument before division then
9806 // biases result, to avoid double rounding of subnormals.
9807 //
9808 // scale dividend by multiplying dividend by 2^(-15360)
9809 // load divisor
9810 // divide scaled dividend by divisor
9811 // rescale quotient by 2^(15360)
9812 //
9813 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9814 predicate (UseSSE<=1);
9815 match(Set dst (DivD dst src));
9816 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9817 ins_cost(01);
9819 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9820 "DMULp $dst,ST\n\t"
9821 "FLD $src\n\t"
9822 "FDIVp $dst,ST\n\t"
9823 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9824 "DMULp $dst,ST\n\t" %}
9825 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9826 ins_encode( strictfp_bias1(dst),
9827 Push_Reg_DPR(src),
9828 OpcP, RegOpc(dst),
9829 strictfp_bias2(dst) );
9830 ins_pipe( fpu_reg_reg );
9831 %}
9833 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9834 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9835 match(Set dst (RoundDouble (DivD src1 src2)));
9837 format %{ "FLD $src1\n\t"
9838 "FDIV ST,$src2\n\t"
9839 "FSTP_D $dst\t# D-round" %}
9840 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9841 ins_encode( Push_Reg_DPR(src1),
9842 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9843 ins_pipe( fpu_mem_reg_reg );
9844 %}
9847 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9848 predicate(UseSSE<=1);
9849 match(Set dst (ModD dst src));
9850 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9852 format %{ "DMOD $dst,$src" %}
9853 ins_cost(250);
9854 ins_encode(Push_Reg_Mod_DPR(dst, src),
9855 emitModDPR(),
9856 Push_Result_Mod_DPR(src),
9857 Pop_Reg_DPR(dst));
9858 ins_pipe( pipe_slow );
9859 %}
9861 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9862 predicate(UseSSE>=2);
9863 match(Set dst (ModD src0 src1));
9864 effect(KILL rax, KILL cr);
9866 format %{ "SUB ESP,8\t # DMOD\n"
9867 "\tMOVSD [ESP+0],$src1\n"
9868 "\tFLD_D [ESP+0]\n"
9869 "\tMOVSD [ESP+0],$src0\n"
9870 "\tFLD_D [ESP+0]\n"
9871 "loop:\tFPREM\n"
9872 "\tFWAIT\n"
9873 "\tFNSTSW AX\n"
9874 "\tSAHF\n"
9875 "\tJP loop\n"
9876 "\tFSTP_D [ESP+0]\n"
9877 "\tMOVSD $dst,[ESP+0]\n"
9878 "\tADD ESP,8\n"
9879 "\tFSTP ST0\t # Restore FPU Stack"
9880 %}
9881 ins_cost(250);
9882 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9883 ins_pipe( pipe_slow );
9884 %}
9886 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9887 predicate (UseSSE<=1);
9888 match(Set dst (SinD src));
9889 ins_cost(1800);
9890 format %{ "DSIN $dst" %}
9891 opcode(0xD9, 0xFE);
9892 ins_encode( OpcP, OpcS );
9893 ins_pipe( pipe_slow );
9894 %}
9896 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9897 predicate (UseSSE>=2);
9898 match(Set dst (SinD dst));
9899 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9900 ins_cost(1800);
9901 format %{ "DSIN $dst" %}
9902 opcode(0xD9, 0xFE);
9903 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9904 ins_pipe( pipe_slow );
9905 %}
9907 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9908 predicate (UseSSE<=1);
9909 match(Set dst (CosD src));
9910 ins_cost(1800);
9911 format %{ "DCOS $dst" %}
9912 opcode(0xD9, 0xFF);
9913 ins_encode( OpcP, OpcS );
9914 ins_pipe( pipe_slow );
9915 %}
9917 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9918 predicate (UseSSE>=2);
9919 match(Set dst (CosD dst));
9920 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9921 ins_cost(1800);
9922 format %{ "DCOS $dst" %}
9923 opcode(0xD9, 0xFF);
9924 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9925 ins_pipe( pipe_slow );
9926 %}
9928 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9929 predicate (UseSSE<=1);
9930 match(Set dst(TanD src));
9931 format %{ "DTAN $dst" %}
9932 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9933 Opcode(0xDD), Opcode(0xD8)); // fstp st
9934 ins_pipe( pipe_slow );
9935 %}
9937 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9938 predicate (UseSSE>=2);
9939 match(Set dst(TanD dst));
9940 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9941 format %{ "DTAN $dst" %}
9942 ins_encode( Push_SrcD(dst),
9943 Opcode(0xD9), Opcode(0xF2), // fptan
9944 Opcode(0xDD), Opcode(0xD8), // fstp st
9945 Push_ResultD(dst) );
9946 ins_pipe( pipe_slow );
9947 %}
9949 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9950 predicate (UseSSE<=1);
9951 match(Set dst(AtanD dst src));
9952 format %{ "DATA $dst,$src" %}
9953 opcode(0xD9, 0xF3);
9954 ins_encode( Push_Reg_DPR(src),
9955 OpcP, OpcS, RegOpc(dst) );
9956 ins_pipe( pipe_slow );
9957 %}
9959 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9960 predicate (UseSSE>=2);
9961 match(Set dst(AtanD dst src));
9962 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9963 format %{ "DATA $dst,$src" %}
9964 opcode(0xD9, 0xF3);
9965 ins_encode( Push_SrcD(src),
9966 OpcP, OpcS, Push_ResultD(dst) );
9967 ins_pipe( pipe_slow );
9968 %}
9970 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9971 predicate (UseSSE<=1);
9972 match(Set dst (SqrtD src));
9973 format %{ "DSQRT $dst,$src" %}
9974 opcode(0xFA, 0xD9);
9975 ins_encode( Push_Reg_DPR(src),
9976 OpcS, OpcP, Pop_Reg_DPR(dst) );
9977 ins_pipe( pipe_slow );
9978 %}
9980 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9981 predicate (UseSSE<=1);
9982 match(Set Y (PowD X Y)); // Raise X to the Yth power
9983 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9984 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9985 ins_encode %{
9986 __ subptr(rsp, 8);
9987 __ fld_s($X$$reg - 1);
9988 __ fast_pow();
9989 __ addptr(rsp, 8);
9990 %}
9991 ins_pipe( pipe_slow );
9992 %}
9994 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9995 predicate (UseSSE>=2);
9996 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9997 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9998 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9999 ins_encode %{
10000 __ subptr(rsp, 8);
10001 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10002 __ fld_d(Address(rsp, 0));
10003 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10004 __ fld_d(Address(rsp, 0));
10005 __ fast_pow();
10006 __ fstp_d(Address(rsp, 0));
10007 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10008 __ addptr(rsp, 8);
10009 %}
10010 ins_pipe( pipe_slow );
10011 %}
10014 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10015 predicate (UseSSE<=1);
10016 match(Set dpr1 (ExpD dpr1));
10017 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10018 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10019 ins_encode %{
10020 __ fast_exp();
10021 %}
10022 ins_pipe( pipe_slow );
10023 %}
10025 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10026 predicate (UseSSE>=2);
10027 match(Set dst (ExpD src));
10028 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10029 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10030 ins_encode %{
10031 __ subptr(rsp, 8);
10032 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10033 __ fld_d(Address(rsp, 0));
10034 __ fast_exp();
10035 __ fstp_d(Address(rsp, 0));
10036 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10037 __ addptr(rsp, 8);
10038 %}
10039 ins_pipe( pipe_slow );
10040 %}
10042 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10043 predicate (UseSSE<=1);
10044 // The source Double operand on FPU stack
10045 match(Set dst (Log10D src));
10046 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10047 // fxch ; swap ST(0) with ST(1)
10048 // fyl2x ; compute log_10(2) * log_2(x)
10049 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10050 "FXCH \n\t"
10051 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10052 %}
10053 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10054 Opcode(0xD9), Opcode(0xC9), // fxch
10055 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10057 ins_pipe( pipe_slow );
10058 %}
10060 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10061 predicate (UseSSE>=2);
10062 effect(KILL cr);
10063 match(Set dst (Log10D src));
10064 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10065 // fyl2x ; compute log_10(2) * log_2(x)
10066 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10067 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10068 %}
10069 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10070 Push_SrcD(src),
10071 Opcode(0xD9), Opcode(0xF1), // fyl2x
10072 Push_ResultD(dst));
10074 ins_pipe( pipe_slow );
10075 %}
10077 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10078 predicate (UseSSE<=1);
10079 // The source Double operand on FPU stack
10080 match(Set dst (LogD src));
10081 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10082 // fxch ; swap ST(0) with ST(1)
10083 // fyl2x ; compute log_e(2) * log_2(x)
10084 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10085 "FXCH \n\t"
10086 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10087 %}
10088 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10089 Opcode(0xD9), Opcode(0xC9), // fxch
10090 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10092 ins_pipe( pipe_slow );
10093 %}
10095 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10096 predicate (UseSSE>=2);
10097 effect(KILL cr);
10098 // The source and result Double operands in XMM registers
10099 match(Set dst (LogD src));
10100 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10101 // fyl2x ; compute log_e(2) * log_2(x)
10102 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10103 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10104 %}
10105 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10106 Push_SrcD(src),
10107 Opcode(0xD9), Opcode(0xF1), // fyl2x
10108 Push_ResultD(dst));
10109 ins_pipe( pipe_slow );
10110 %}
10112 //-------------Float Instructions-------------------------------
10113 // Float Math
10115 // Code for float compare:
10116 // fcompp();
10117 // fwait(); fnstsw_ax();
10118 // sahf();
10119 // movl(dst, unordered_result);
10120 // jcc(Assembler::parity, exit);
10121 // movl(dst, less_result);
10122 // jcc(Assembler::below, exit);
10123 // movl(dst, equal_result);
10124 // jcc(Assembler::equal, exit);
10125 // movl(dst, greater_result);
10126 // exit:
10128 // P6 version of float compare, sets condition codes in EFLAGS
10129 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10130 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10131 match(Set cr (CmpF src1 src2));
10132 effect(KILL rax);
10133 ins_cost(150);
10134 format %{ "FLD $src1\n\t"
10135 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10136 "JNP exit\n\t"
10137 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10138 "SAHF\n"
10139 "exit:\tNOP // avoid branch to branch" %}
10140 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10141 ins_encode( Push_Reg_DPR(src1),
10142 OpcP, RegOpc(src2),
10143 cmpF_P6_fixup );
10144 ins_pipe( pipe_slow );
10145 %}
10147 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10148 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10149 match(Set cr (CmpF src1 src2));
10150 ins_cost(100);
10151 format %{ "FLD $src1\n\t"
10152 "FUCOMIP ST,$src2 // P6 instruction" %}
10153 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10154 ins_encode( Push_Reg_DPR(src1),
10155 OpcP, RegOpc(src2));
10156 ins_pipe( pipe_slow );
10157 %}
10160 // Compare & branch
10161 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10162 predicate(UseSSE == 0);
10163 match(Set cr (CmpF src1 src2));
10164 effect(KILL rax);
10165 ins_cost(200);
10166 format %{ "FLD $src1\n\t"
10167 "FCOMp $src2\n\t"
10168 "FNSTSW AX\n\t"
10169 "TEST AX,0x400\n\t"
10170 "JZ,s flags\n\t"
10171 "MOV AH,1\t# unordered treat as LT\n"
10172 "flags:\tSAHF" %}
10173 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10174 ins_encode( Push_Reg_DPR(src1),
10175 OpcP, RegOpc(src2),
10176 fpu_flags);
10177 ins_pipe( pipe_slow );
10178 %}
10180 // Compare vs zero into -1,0,1
10181 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10182 predicate(UseSSE == 0);
10183 match(Set dst (CmpF3 src1 zero));
10184 effect(KILL cr, KILL rax);
10185 ins_cost(280);
10186 format %{ "FTSTF $dst,$src1" %}
10187 opcode(0xE4, 0xD9);
10188 ins_encode( Push_Reg_DPR(src1),
10189 OpcS, OpcP, PopFPU,
10190 CmpF_Result(dst));
10191 ins_pipe( pipe_slow );
10192 %}
10194 // Compare into -1,0,1
10195 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10196 predicate(UseSSE == 0);
10197 match(Set dst (CmpF3 src1 src2));
10198 effect(KILL cr, KILL rax);
10199 ins_cost(300);
10200 format %{ "FCMPF $dst,$src1,$src2" %}
10201 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10202 ins_encode( Push_Reg_DPR(src1),
10203 OpcP, RegOpc(src2),
10204 CmpF_Result(dst));
10205 ins_pipe( pipe_slow );
10206 %}
10208 // float compare and set condition codes in EFLAGS by XMM regs
10209 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10210 predicate(UseSSE>=1);
10211 match(Set cr (CmpF src1 src2));
10212 ins_cost(145);
10213 format %{ "UCOMISS $src1,$src2\n\t"
10214 "JNP,s exit\n\t"
10215 "PUSHF\t# saw NaN, set CF\n\t"
10216 "AND [rsp], #0xffffff2b\n\t"
10217 "POPF\n"
10218 "exit:" %}
10219 ins_encode %{
10220 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10221 emit_cmpfp_fixup(_masm);
10222 %}
10223 ins_pipe( pipe_slow );
10224 %}
10226 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10227 predicate(UseSSE>=1);
10228 match(Set cr (CmpF src1 src2));
10229 ins_cost(100);
10230 format %{ "UCOMISS $src1,$src2" %}
10231 ins_encode %{
10232 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10233 %}
10234 ins_pipe( pipe_slow );
10235 %}
10237 // float compare and set condition codes in EFLAGS by XMM regs
10238 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10239 predicate(UseSSE>=1);
10240 match(Set cr (CmpF src1 (LoadF src2)));
10241 ins_cost(165);
10242 format %{ "UCOMISS $src1,$src2\n\t"
10243 "JNP,s exit\n\t"
10244 "PUSHF\t# saw NaN, set CF\n\t"
10245 "AND [rsp], #0xffffff2b\n\t"
10246 "POPF\n"
10247 "exit:" %}
10248 ins_encode %{
10249 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10250 emit_cmpfp_fixup(_masm);
10251 %}
10252 ins_pipe( pipe_slow );
10253 %}
10255 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10256 predicate(UseSSE>=1);
10257 match(Set cr (CmpF src1 (LoadF src2)));
10258 ins_cost(100);
10259 format %{ "UCOMISS $src1,$src2" %}
10260 ins_encode %{
10261 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10262 %}
10263 ins_pipe( pipe_slow );
10264 %}
10266 // Compare into -1,0,1 in XMM
10267 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10268 predicate(UseSSE>=1);
10269 match(Set dst (CmpF3 src1 src2));
10270 effect(KILL cr);
10271 ins_cost(255);
10272 format %{ "UCOMISS $src1, $src2\n\t"
10273 "MOV $dst, #-1\n\t"
10274 "JP,s done\n\t"
10275 "JB,s done\n\t"
10276 "SETNE $dst\n\t"
10277 "MOVZB $dst, $dst\n"
10278 "done:" %}
10279 ins_encode %{
10280 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10281 emit_cmpfp3(_masm, $dst$$Register);
10282 %}
10283 ins_pipe( pipe_slow );
10284 %}
10286 // Compare into -1,0,1 in XMM and memory
10287 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10288 predicate(UseSSE>=1);
10289 match(Set dst (CmpF3 src1 (LoadF src2)));
10290 effect(KILL cr);
10291 ins_cost(275);
10292 format %{ "UCOMISS $src1, $src2\n\t"
10293 "MOV $dst, #-1\n\t"
10294 "JP,s done\n\t"
10295 "JB,s done\n\t"
10296 "SETNE $dst\n\t"
10297 "MOVZB $dst, $dst\n"
10298 "done:" %}
10299 ins_encode %{
10300 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10301 emit_cmpfp3(_masm, $dst$$Register);
10302 %}
10303 ins_pipe( pipe_slow );
10304 %}
10306 // Spill to obtain 24-bit precision
10307 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10308 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10309 match(Set dst (SubF src1 src2));
10311 format %{ "FSUB $dst,$src1 - $src2" %}
10312 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10313 ins_encode( Push_Reg_FPR(src1),
10314 OpcReg_FPR(src2),
10315 Pop_Mem_FPR(dst) );
10316 ins_pipe( fpu_mem_reg_reg );
10317 %}
10318 //
10319 // This instruction does not round to 24-bits
10320 instruct subFPR_reg(regFPR dst, regFPR src) %{
10321 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10322 match(Set dst (SubF dst src));
10324 format %{ "FSUB $dst,$src" %}
10325 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10326 ins_encode( Push_Reg_FPR(src),
10327 OpcP, RegOpc(dst) );
10328 ins_pipe( fpu_reg_reg );
10329 %}
10331 // Spill to obtain 24-bit precision
10332 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10333 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10334 match(Set dst (AddF src1 src2));
10336 format %{ "FADD $dst,$src1,$src2" %}
10337 opcode(0xD8, 0x0); /* D8 C0+i */
10338 ins_encode( Push_Reg_FPR(src2),
10339 OpcReg_FPR(src1),
10340 Pop_Mem_FPR(dst) );
10341 ins_pipe( fpu_mem_reg_reg );
10342 %}
10343 //
10344 // This instruction does not round to 24-bits
10345 instruct addFPR_reg(regFPR dst, regFPR src) %{
10346 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10347 match(Set dst (AddF dst src));
10349 format %{ "FLD $src\n\t"
10350 "FADDp $dst,ST" %}
10351 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10352 ins_encode( Push_Reg_FPR(src),
10353 OpcP, RegOpc(dst) );
10354 ins_pipe( fpu_reg_reg );
10355 %}
10357 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10358 predicate(UseSSE==0);
10359 match(Set dst (AbsF src));
10360 ins_cost(100);
10361 format %{ "FABS" %}
10362 opcode(0xE1, 0xD9);
10363 ins_encode( OpcS, OpcP );
10364 ins_pipe( fpu_reg_reg );
10365 %}
10367 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10368 predicate(UseSSE==0);
10369 match(Set dst (NegF src));
10370 ins_cost(100);
10371 format %{ "FCHS" %}
10372 opcode(0xE0, 0xD9);
10373 ins_encode( OpcS, OpcP );
10374 ins_pipe( fpu_reg_reg );
10375 %}
10377 // Cisc-alternate to addFPR_reg
10378 // Spill to obtain 24-bit precision
10379 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10380 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10381 match(Set dst (AddF src1 (LoadF src2)));
10383 format %{ "FLD $src2\n\t"
10384 "FADD ST,$src1\n\t"
10385 "FSTP_S $dst" %}
10386 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10387 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10388 OpcReg_FPR(src1),
10389 Pop_Mem_FPR(dst) );
10390 ins_pipe( fpu_mem_reg_mem );
10391 %}
10392 //
10393 // Cisc-alternate to addFPR_reg
10394 // This instruction does not round to 24-bits
10395 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10396 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10397 match(Set dst (AddF dst (LoadF src)));
10399 format %{ "FADD $dst,$src" %}
10400 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10401 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10402 OpcP, RegOpc(dst) );
10403 ins_pipe( fpu_reg_mem );
10404 %}
10406 // // Following two instructions for _222_mpegaudio
10407 // Spill to obtain 24-bit precision
10408 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10409 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10410 match(Set dst (AddF src1 src2));
10412 format %{ "FADD $dst,$src1,$src2" %}
10413 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10414 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10415 OpcReg_FPR(src2),
10416 Pop_Mem_FPR(dst) );
10417 ins_pipe( fpu_mem_reg_mem );
10418 %}
10420 // Cisc-spill variant
10421 // Spill to obtain 24-bit precision
10422 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10423 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10424 match(Set dst (AddF src1 (LoadF src2)));
10426 format %{ "FADD $dst,$src1,$src2 cisc" %}
10427 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10428 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10429 set_instruction_start,
10430 OpcP, RMopc_Mem(secondary,src1),
10431 Pop_Mem_FPR(dst) );
10432 ins_pipe( fpu_mem_mem_mem );
10433 %}
10435 // Spill to obtain 24-bit precision
10436 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10437 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10438 match(Set dst (AddF src1 src2));
10440 format %{ "FADD $dst,$src1,$src2" %}
10441 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10442 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10443 set_instruction_start,
10444 OpcP, RMopc_Mem(secondary,src1),
10445 Pop_Mem_FPR(dst) );
10446 ins_pipe( fpu_mem_mem_mem );
10447 %}
10450 // Spill to obtain 24-bit precision
10451 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10452 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10453 match(Set dst (AddF src con));
10454 format %{ "FLD $src\n\t"
10455 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10456 "FSTP_S $dst" %}
10457 ins_encode %{
10458 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10459 __ fadd_s($constantaddress($con));
10460 __ fstp_s(Address(rsp, $dst$$disp));
10461 %}
10462 ins_pipe(fpu_mem_reg_con);
10463 %}
10464 //
10465 // This instruction does not round to 24-bits
10466 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10467 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10468 match(Set dst (AddF src con));
10469 format %{ "FLD $src\n\t"
10470 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10471 "FSTP $dst" %}
10472 ins_encode %{
10473 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10474 __ fadd_s($constantaddress($con));
10475 __ fstp_d($dst$$reg);
10476 %}
10477 ins_pipe(fpu_reg_reg_con);
10478 %}
10480 // Spill to obtain 24-bit precision
10481 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10482 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10483 match(Set dst (MulF src1 src2));
10485 format %{ "FLD $src1\n\t"
10486 "FMUL $src2\n\t"
10487 "FSTP_S $dst" %}
10488 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10489 ins_encode( Push_Reg_FPR(src1),
10490 OpcReg_FPR(src2),
10491 Pop_Mem_FPR(dst) );
10492 ins_pipe( fpu_mem_reg_reg );
10493 %}
10494 //
10495 // This instruction does not round to 24-bits
10496 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10497 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10498 match(Set dst (MulF src1 src2));
10500 format %{ "FLD $src1\n\t"
10501 "FMUL $src2\n\t"
10502 "FSTP_S $dst" %}
10503 opcode(0xD8, 0x1); /* D8 C8+i */
10504 ins_encode( Push_Reg_FPR(src2),
10505 OpcReg_FPR(src1),
10506 Pop_Reg_FPR(dst) );
10507 ins_pipe( fpu_reg_reg_reg );
10508 %}
10511 // Spill to obtain 24-bit precision
10512 // Cisc-alternate to reg-reg multiply
10513 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10514 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10515 match(Set dst (MulF src1 (LoadF src2)));
10517 format %{ "FLD_S $src2\n\t"
10518 "FMUL $src1\n\t"
10519 "FSTP_S $dst" %}
10520 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10521 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10522 OpcReg_FPR(src1),
10523 Pop_Mem_FPR(dst) );
10524 ins_pipe( fpu_mem_reg_mem );
10525 %}
10526 //
10527 // This instruction does not round to 24-bits
10528 // Cisc-alternate to reg-reg multiply
10529 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10530 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10531 match(Set dst (MulF src1 (LoadF src2)));
10533 format %{ "FMUL $dst,$src1,$src2" %}
10534 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10535 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10536 OpcReg_FPR(src1),
10537 Pop_Reg_FPR(dst) );
10538 ins_pipe( fpu_reg_reg_mem );
10539 %}
10541 // Spill to obtain 24-bit precision
10542 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10543 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10544 match(Set dst (MulF src1 src2));
10546 format %{ "FMUL $dst,$src1,$src2" %}
10547 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10548 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10549 set_instruction_start,
10550 OpcP, RMopc_Mem(secondary,src1),
10551 Pop_Mem_FPR(dst) );
10552 ins_pipe( fpu_mem_mem_mem );
10553 %}
10555 // Spill to obtain 24-bit precision
10556 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10557 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10558 match(Set dst (MulF src con));
10560 format %{ "FLD $src\n\t"
10561 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10562 "FSTP_S $dst" %}
10563 ins_encode %{
10564 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10565 __ fmul_s($constantaddress($con));
10566 __ fstp_s(Address(rsp, $dst$$disp));
10567 %}
10568 ins_pipe(fpu_mem_reg_con);
10569 %}
10570 //
10571 // This instruction does not round to 24-bits
10572 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10573 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10574 match(Set dst (MulF src con));
10576 format %{ "FLD $src\n\t"
10577 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10578 "FSTP $dst" %}
10579 ins_encode %{
10580 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10581 __ fmul_s($constantaddress($con));
10582 __ fstp_d($dst$$reg);
10583 %}
10584 ins_pipe(fpu_reg_reg_con);
10585 %}
10588 //
10589 // MACRO1 -- subsume unshared load into mulFPR
10590 // This instruction does not round to 24-bits
10591 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10592 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10593 match(Set dst (MulF (LoadF mem1) src));
10595 format %{ "FLD $mem1 ===MACRO1===\n\t"
10596 "FMUL ST,$src\n\t"
10597 "FSTP $dst" %}
10598 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10599 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10600 OpcReg_FPR(src),
10601 Pop_Reg_FPR(dst) );
10602 ins_pipe( fpu_reg_reg_mem );
10603 %}
10604 //
10605 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10606 // This instruction does not round to 24-bits
10607 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10608 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10609 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10610 ins_cost(95);
10612 format %{ "FLD $mem1 ===MACRO2===\n\t"
10613 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10614 "FADD ST,$src2\n\t"
10615 "FSTP $dst" %}
10616 opcode(0xD9); /* LoadF D9 /0 */
10617 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10618 FMul_ST_reg(src1),
10619 FAdd_ST_reg(src2),
10620 Pop_Reg_FPR(dst) );
10621 ins_pipe( fpu_reg_mem_reg_reg );
10622 %}
10624 // MACRO3 -- addFPR a mulFPR
10625 // This instruction does not round to 24-bits. It is a '2-address'
10626 // instruction in that the result goes back to src2. This eliminates
10627 // a move from the macro; possibly the register allocator will have
10628 // to add it back (and maybe not).
10629 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10630 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10631 match(Set src2 (AddF (MulF src0 src1) src2));
10633 format %{ "FLD $src0 ===MACRO3===\n\t"
10634 "FMUL ST,$src1\n\t"
10635 "FADDP $src2,ST" %}
10636 opcode(0xD9); /* LoadF D9 /0 */
10637 ins_encode( Push_Reg_FPR(src0),
10638 FMul_ST_reg(src1),
10639 FAddP_reg_ST(src2) );
10640 ins_pipe( fpu_reg_reg_reg );
10641 %}
10643 // MACRO4 -- divFPR subFPR
10644 // This instruction does not round to 24-bits
10645 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10646 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10647 match(Set dst (DivF (SubF src2 src1) src3));
10649 format %{ "FLD $src2 ===MACRO4===\n\t"
10650 "FSUB ST,$src1\n\t"
10651 "FDIV ST,$src3\n\t"
10652 "FSTP $dst" %}
10653 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10654 ins_encode( Push_Reg_FPR(src2),
10655 subFPR_divFPR_encode(src1,src3),
10656 Pop_Reg_FPR(dst) );
10657 ins_pipe( fpu_reg_reg_reg_reg );
10658 %}
10660 // Spill to obtain 24-bit precision
10661 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10662 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10663 match(Set dst (DivF src1 src2));
10665 format %{ "FDIV $dst,$src1,$src2" %}
10666 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10667 ins_encode( Push_Reg_FPR(src1),
10668 OpcReg_FPR(src2),
10669 Pop_Mem_FPR(dst) );
10670 ins_pipe( fpu_mem_reg_reg );
10671 %}
10672 //
10673 // This instruction does not round to 24-bits
10674 instruct divFPR_reg(regFPR dst, regFPR src) %{
10675 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10676 match(Set dst (DivF dst src));
10678 format %{ "FDIV $dst,$src" %}
10679 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10680 ins_encode( Push_Reg_FPR(src),
10681 OpcP, RegOpc(dst) );
10682 ins_pipe( fpu_reg_reg );
10683 %}
10686 // Spill to obtain 24-bit precision
10687 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10688 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10689 match(Set dst (ModF src1 src2));
10690 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10692 format %{ "FMOD $dst,$src1,$src2" %}
10693 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10694 emitModDPR(),
10695 Push_Result_Mod_DPR(src2),
10696 Pop_Mem_FPR(dst));
10697 ins_pipe( pipe_slow );
10698 %}
10699 //
10700 // This instruction does not round to 24-bits
10701 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10702 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10703 match(Set dst (ModF dst src));
10704 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10706 format %{ "FMOD $dst,$src" %}
10707 ins_encode(Push_Reg_Mod_DPR(dst, src),
10708 emitModDPR(),
10709 Push_Result_Mod_DPR(src),
10710 Pop_Reg_FPR(dst));
10711 ins_pipe( pipe_slow );
10712 %}
10714 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10715 predicate(UseSSE>=1);
10716 match(Set dst (ModF src0 src1));
10717 effect(KILL rax, KILL cr);
10718 format %{ "SUB ESP,4\t # FMOD\n"
10719 "\tMOVSS [ESP+0],$src1\n"
10720 "\tFLD_S [ESP+0]\n"
10721 "\tMOVSS [ESP+0],$src0\n"
10722 "\tFLD_S [ESP+0]\n"
10723 "loop:\tFPREM\n"
10724 "\tFWAIT\n"
10725 "\tFNSTSW AX\n"
10726 "\tSAHF\n"
10727 "\tJP loop\n"
10728 "\tFSTP_S [ESP+0]\n"
10729 "\tMOVSS $dst,[ESP+0]\n"
10730 "\tADD ESP,4\n"
10731 "\tFSTP ST0\t # Restore FPU Stack"
10732 %}
10733 ins_cost(250);
10734 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10735 ins_pipe( pipe_slow );
10736 %}
10739 //----------Arithmetic Conversion Instructions---------------------------------
10740 // The conversions operations are all Alpha sorted. Please keep it that way!
10742 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10743 predicate(UseSSE==0);
10744 match(Set dst (RoundFloat src));
10745 ins_cost(125);
10746 format %{ "FST_S $dst,$src\t# F-round" %}
10747 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10748 ins_pipe( fpu_mem_reg );
10749 %}
10751 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10752 predicate(UseSSE<=1);
10753 match(Set dst (RoundDouble src));
10754 ins_cost(125);
10755 format %{ "FST_D $dst,$src\t# D-round" %}
10756 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10757 ins_pipe( fpu_mem_reg );
10758 %}
10760 // Force rounding to 24-bit precision and 6-bit exponent
10761 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10762 predicate(UseSSE==0);
10763 match(Set dst (ConvD2F src));
10764 format %{ "FST_S $dst,$src\t# F-round" %}
10765 expand %{
10766 roundFloat_mem_reg(dst,src);
10767 %}
10768 %}
10770 // Force rounding to 24-bit precision and 6-bit exponent
10771 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10772 predicate(UseSSE==1);
10773 match(Set dst (ConvD2F src));
10774 effect( KILL cr );
10775 format %{ "SUB ESP,4\n\t"
10776 "FST_S [ESP],$src\t# F-round\n\t"
10777 "MOVSS $dst,[ESP]\n\t"
10778 "ADD ESP,4" %}
10779 ins_encode %{
10780 __ subptr(rsp, 4);
10781 if ($src$$reg != FPR1L_enc) {
10782 __ fld_s($src$$reg-1);
10783 __ fstp_s(Address(rsp, 0));
10784 } else {
10785 __ fst_s(Address(rsp, 0));
10786 }
10787 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10788 __ addptr(rsp, 4);
10789 %}
10790 ins_pipe( pipe_slow );
10791 %}
10793 // Force rounding double precision to single precision
10794 instruct convD2F_reg(regF dst, regD src) %{
10795 predicate(UseSSE>=2);
10796 match(Set dst (ConvD2F src));
10797 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10798 ins_encode %{
10799 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10800 %}
10801 ins_pipe( pipe_slow );
10802 %}
10804 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10805 predicate(UseSSE==0);
10806 match(Set dst (ConvF2D src));
10807 format %{ "FST_S $dst,$src\t# D-round" %}
10808 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10809 ins_pipe( fpu_reg_reg );
10810 %}
10812 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10813 predicate(UseSSE==1);
10814 match(Set dst (ConvF2D src));
10815 format %{ "FST_D $dst,$src\t# D-round" %}
10816 expand %{
10817 roundDouble_mem_reg(dst,src);
10818 %}
10819 %}
10821 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10822 predicate(UseSSE==1);
10823 match(Set dst (ConvF2D src));
10824 effect( KILL cr );
10825 format %{ "SUB ESP,4\n\t"
10826 "MOVSS [ESP] $src\n\t"
10827 "FLD_S [ESP]\n\t"
10828 "ADD ESP,4\n\t"
10829 "FSTP $dst\t# D-round" %}
10830 ins_encode %{
10831 __ subptr(rsp, 4);
10832 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10833 __ fld_s(Address(rsp, 0));
10834 __ addptr(rsp, 4);
10835 __ fstp_d($dst$$reg);
10836 %}
10837 ins_pipe( pipe_slow );
10838 %}
10840 instruct convF2D_reg(regD dst, regF src) %{
10841 predicate(UseSSE>=2);
10842 match(Set dst (ConvF2D src));
10843 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10844 ins_encode %{
10845 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10846 %}
10847 ins_pipe( pipe_slow );
10848 %}
10850 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10851 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10852 predicate(UseSSE<=1);
10853 match(Set dst (ConvD2I src));
10854 effect( KILL tmp, KILL cr );
10855 format %{ "FLD $src\t# Convert double to int \n\t"
10856 "FLDCW trunc mode\n\t"
10857 "SUB ESP,4\n\t"
10858 "FISTp [ESP + #0]\n\t"
10859 "FLDCW std/24-bit mode\n\t"
10860 "POP EAX\n\t"
10861 "CMP EAX,0x80000000\n\t"
10862 "JNE,s fast\n\t"
10863 "FLD_D $src\n\t"
10864 "CALL d2i_wrapper\n"
10865 "fast:" %}
10866 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10867 ins_pipe( pipe_slow );
10868 %}
10870 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10871 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10872 predicate(UseSSE>=2);
10873 match(Set dst (ConvD2I src));
10874 effect( KILL tmp, KILL cr );
10875 format %{ "CVTTSD2SI $dst, $src\n\t"
10876 "CMP $dst,0x80000000\n\t"
10877 "JNE,s fast\n\t"
10878 "SUB ESP, 8\n\t"
10879 "MOVSD [ESP], $src\n\t"
10880 "FLD_D [ESP]\n\t"
10881 "ADD ESP, 8\n\t"
10882 "CALL d2i_wrapper\n"
10883 "fast:" %}
10884 ins_encode %{
10885 Label fast;
10886 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10887 __ cmpl($dst$$Register, 0x80000000);
10888 __ jccb(Assembler::notEqual, fast);
10889 __ subptr(rsp, 8);
10890 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10891 __ fld_d(Address(rsp, 0));
10892 __ addptr(rsp, 8);
10893 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10894 __ bind(fast);
10895 %}
10896 ins_pipe( pipe_slow );
10897 %}
10899 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10900 predicate(UseSSE<=1);
10901 match(Set dst (ConvD2L src));
10902 effect( KILL cr );
10903 format %{ "FLD $src\t# Convert double to long\n\t"
10904 "FLDCW trunc mode\n\t"
10905 "SUB ESP,8\n\t"
10906 "FISTp [ESP + #0]\n\t"
10907 "FLDCW std/24-bit mode\n\t"
10908 "POP EAX\n\t"
10909 "POP EDX\n\t"
10910 "CMP EDX,0x80000000\n\t"
10911 "JNE,s fast\n\t"
10912 "TEST EAX,EAX\n\t"
10913 "JNE,s fast\n\t"
10914 "FLD $src\n\t"
10915 "CALL d2l_wrapper\n"
10916 "fast:" %}
10917 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10918 ins_pipe( pipe_slow );
10919 %}
10921 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10922 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10923 predicate (UseSSE>=2);
10924 match(Set dst (ConvD2L src));
10925 effect( KILL cr );
10926 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10927 "MOVSD [ESP],$src\n\t"
10928 "FLD_D [ESP]\n\t"
10929 "FLDCW trunc mode\n\t"
10930 "FISTp [ESP + #0]\n\t"
10931 "FLDCW std/24-bit mode\n\t"
10932 "POP EAX\n\t"
10933 "POP EDX\n\t"
10934 "CMP EDX,0x80000000\n\t"
10935 "JNE,s fast\n\t"
10936 "TEST EAX,EAX\n\t"
10937 "JNE,s fast\n\t"
10938 "SUB ESP,8\n\t"
10939 "MOVSD [ESP],$src\n\t"
10940 "FLD_D [ESP]\n\t"
10941 "ADD ESP,8\n\t"
10942 "CALL d2l_wrapper\n"
10943 "fast:" %}
10944 ins_encode %{
10945 Label fast;
10946 __ subptr(rsp, 8);
10947 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10948 __ fld_d(Address(rsp, 0));
10949 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10950 __ fistp_d(Address(rsp, 0));
10951 // Restore the rounding mode, mask the exception
10952 if (Compile::current()->in_24_bit_fp_mode()) {
10953 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10954 } else {
10955 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10956 }
10957 // Load the converted long, adjust CPU stack
10958 __ pop(rax);
10959 __ pop(rdx);
10960 __ cmpl(rdx, 0x80000000);
10961 __ jccb(Assembler::notEqual, fast);
10962 __ testl(rax, rax);
10963 __ jccb(Assembler::notEqual, fast);
10964 __ subptr(rsp, 8);
10965 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10966 __ fld_d(Address(rsp, 0));
10967 __ addptr(rsp, 8);
10968 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10969 __ bind(fast);
10970 %}
10971 ins_pipe( pipe_slow );
10972 %}
10974 // Convert a double to an int. Java semantics require we do complex
10975 // manglations in the corner cases. So we set the rounding mode to
10976 // 'zero', store the darned double down as an int, and reset the
10977 // rounding mode to 'nearest'. The hardware stores a flag value down
10978 // if we would overflow or converted a NAN; we check for this and
10979 // and go the slow path if needed.
10980 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10981 predicate(UseSSE==0);
10982 match(Set dst (ConvF2I src));
10983 effect( KILL tmp, KILL cr );
10984 format %{ "FLD $src\t# Convert float to int \n\t"
10985 "FLDCW trunc mode\n\t"
10986 "SUB ESP,4\n\t"
10987 "FISTp [ESP + #0]\n\t"
10988 "FLDCW std/24-bit mode\n\t"
10989 "POP EAX\n\t"
10990 "CMP EAX,0x80000000\n\t"
10991 "JNE,s fast\n\t"
10992 "FLD $src\n\t"
10993 "CALL d2i_wrapper\n"
10994 "fast:" %}
10995 // DPR2I_encoding works for FPR2I
10996 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10997 ins_pipe( pipe_slow );
10998 %}
11000 // Convert a float in xmm to an int reg.
11001 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11002 predicate(UseSSE>=1);
11003 match(Set dst (ConvF2I src));
11004 effect( KILL tmp, KILL cr );
11005 format %{ "CVTTSS2SI $dst, $src\n\t"
11006 "CMP $dst,0x80000000\n\t"
11007 "JNE,s fast\n\t"
11008 "SUB ESP, 4\n\t"
11009 "MOVSS [ESP], $src\n\t"
11010 "FLD [ESP]\n\t"
11011 "ADD ESP, 4\n\t"
11012 "CALL d2i_wrapper\n"
11013 "fast:" %}
11014 ins_encode %{
11015 Label fast;
11016 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11017 __ cmpl($dst$$Register, 0x80000000);
11018 __ jccb(Assembler::notEqual, fast);
11019 __ subptr(rsp, 4);
11020 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11021 __ fld_s(Address(rsp, 0));
11022 __ addptr(rsp, 4);
11023 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11024 __ bind(fast);
11025 %}
11026 ins_pipe( pipe_slow );
11027 %}
11029 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11030 predicate(UseSSE==0);
11031 match(Set dst (ConvF2L src));
11032 effect( KILL cr );
11033 format %{ "FLD $src\t# Convert float to long\n\t"
11034 "FLDCW trunc mode\n\t"
11035 "SUB ESP,8\n\t"
11036 "FISTp [ESP + #0]\n\t"
11037 "FLDCW std/24-bit mode\n\t"
11038 "POP EAX\n\t"
11039 "POP EDX\n\t"
11040 "CMP EDX,0x80000000\n\t"
11041 "JNE,s fast\n\t"
11042 "TEST EAX,EAX\n\t"
11043 "JNE,s fast\n\t"
11044 "FLD $src\n\t"
11045 "CALL d2l_wrapper\n"
11046 "fast:" %}
11047 // DPR2L_encoding works for FPR2L
11048 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11049 ins_pipe( pipe_slow );
11050 %}
11052 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11053 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11054 predicate (UseSSE>=1);
11055 match(Set dst (ConvF2L src));
11056 effect( KILL cr );
11057 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11058 "MOVSS [ESP],$src\n\t"
11059 "FLD_S [ESP]\n\t"
11060 "FLDCW trunc mode\n\t"
11061 "FISTp [ESP + #0]\n\t"
11062 "FLDCW std/24-bit mode\n\t"
11063 "POP EAX\n\t"
11064 "POP EDX\n\t"
11065 "CMP EDX,0x80000000\n\t"
11066 "JNE,s fast\n\t"
11067 "TEST EAX,EAX\n\t"
11068 "JNE,s fast\n\t"
11069 "SUB ESP,4\t# Convert float to long\n\t"
11070 "MOVSS [ESP],$src\n\t"
11071 "FLD_S [ESP]\n\t"
11072 "ADD ESP,4\n\t"
11073 "CALL d2l_wrapper\n"
11074 "fast:" %}
11075 ins_encode %{
11076 Label fast;
11077 __ subptr(rsp, 8);
11078 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11079 __ fld_s(Address(rsp, 0));
11080 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11081 __ fistp_d(Address(rsp, 0));
11082 // Restore the rounding mode, mask the exception
11083 if (Compile::current()->in_24_bit_fp_mode()) {
11084 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11085 } else {
11086 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11087 }
11088 // Load the converted long, adjust CPU stack
11089 __ pop(rax);
11090 __ pop(rdx);
11091 __ cmpl(rdx, 0x80000000);
11092 __ jccb(Assembler::notEqual, fast);
11093 __ testl(rax, rax);
11094 __ jccb(Assembler::notEqual, fast);
11095 __ subptr(rsp, 4);
11096 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11097 __ fld_s(Address(rsp, 0));
11098 __ addptr(rsp, 4);
11099 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11100 __ bind(fast);
11101 %}
11102 ins_pipe( pipe_slow );
11103 %}
11105 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11106 predicate( UseSSE<=1 );
11107 match(Set dst (ConvI2D src));
11108 format %{ "FILD $src\n\t"
11109 "FSTP $dst" %}
11110 opcode(0xDB, 0x0); /* DB /0 */
11111 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11112 ins_pipe( fpu_reg_mem );
11113 %}
11115 instruct convI2D_reg(regD dst, rRegI src) %{
11116 predicate( UseSSE>=2 && !UseXmmI2D );
11117 match(Set dst (ConvI2D src));
11118 format %{ "CVTSI2SD $dst,$src" %}
11119 ins_encode %{
11120 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11121 %}
11122 ins_pipe( pipe_slow );
11123 %}
11125 instruct convI2D_mem(regD dst, memory mem) %{
11126 predicate( UseSSE>=2 );
11127 match(Set dst (ConvI2D (LoadI mem)));
11128 format %{ "CVTSI2SD $dst,$mem" %}
11129 ins_encode %{
11130 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11131 %}
11132 ins_pipe( pipe_slow );
11133 %}
11135 instruct convXI2D_reg(regD dst, rRegI src)
11136 %{
11137 predicate( UseSSE>=2 && UseXmmI2D );
11138 match(Set dst (ConvI2D src));
11140 format %{ "MOVD $dst,$src\n\t"
11141 "CVTDQ2PD $dst,$dst\t# i2d" %}
11142 ins_encode %{
11143 __ movdl($dst$$XMMRegister, $src$$Register);
11144 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11145 %}
11146 ins_pipe(pipe_slow); // XXX
11147 %}
11149 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11150 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11151 match(Set dst (ConvI2D (LoadI mem)));
11152 format %{ "FILD $mem\n\t"
11153 "FSTP $dst" %}
11154 opcode(0xDB); /* DB /0 */
11155 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11156 Pop_Reg_DPR(dst));
11157 ins_pipe( fpu_reg_mem );
11158 %}
11160 // Convert a byte to a float; no rounding step needed.
11161 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11162 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11163 match(Set dst (ConvI2F src));
11164 format %{ "FILD $src\n\t"
11165 "FSTP $dst" %}
11167 opcode(0xDB, 0x0); /* DB /0 */
11168 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11169 ins_pipe( fpu_reg_mem );
11170 %}
11172 // In 24-bit mode, force exponent rounding by storing back out
11173 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11174 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11175 match(Set dst (ConvI2F src));
11176 ins_cost(200);
11177 format %{ "FILD $src\n\t"
11178 "FSTP_S $dst" %}
11179 opcode(0xDB, 0x0); /* DB /0 */
11180 ins_encode( Push_Mem_I(src),
11181 Pop_Mem_FPR(dst));
11182 ins_pipe( fpu_mem_mem );
11183 %}
11185 // In 24-bit mode, force exponent rounding by storing back out
11186 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11187 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11188 match(Set dst (ConvI2F (LoadI mem)));
11189 ins_cost(200);
11190 format %{ "FILD $mem\n\t"
11191 "FSTP_S $dst" %}
11192 opcode(0xDB); /* DB /0 */
11193 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11194 Pop_Mem_FPR(dst));
11195 ins_pipe( fpu_mem_mem );
11196 %}
11198 // This instruction does not round to 24-bits
11199 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11200 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11201 match(Set dst (ConvI2F src));
11202 format %{ "FILD $src\n\t"
11203 "FSTP $dst" %}
11204 opcode(0xDB, 0x0); /* DB /0 */
11205 ins_encode( Push_Mem_I(src),
11206 Pop_Reg_FPR(dst));
11207 ins_pipe( fpu_reg_mem );
11208 %}
11210 // This instruction does not round to 24-bits
11211 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11212 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11213 match(Set dst (ConvI2F (LoadI mem)));
11214 format %{ "FILD $mem\n\t"
11215 "FSTP $dst" %}
11216 opcode(0xDB); /* DB /0 */
11217 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11218 Pop_Reg_FPR(dst));
11219 ins_pipe( fpu_reg_mem );
11220 %}
11222 // Convert an int to a float in xmm; no rounding step needed.
11223 instruct convI2F_reg(regF dst, rRegI src) %{
11224 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11225 match(Set dst (ConvI2F src));
11226 format %{ "CVTSI2SS $dst, $src" %}
11227 ins_encode %{
11228 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11229 %}
11230 ins_pipe( pipe_slow );
11231 %}
11233 instruct convXI2F_reg(regF dst, rRegI src)
11234 %{
11235 predicate( UseSSE>=2 && UseXmmI2F );
11236 match(Set dst (ConvI2F src));
11238 format %{ "MOVD $dst,$src\n\t"
11239 "CVTDQ2PS $dst,$dst\t# i2f" %}
11240 ins_encode %{
11241 __ movdl($dst$$XMMRegister, $src$$Register);
11242 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11243 %}
11244 ins_pipe(pipe_slow); // XXX
11245 %}
11247 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11248 match(Set dst (ConvI2L src));
11249 effect(KILL cr);
11250 ins_cost(375);
11251 format %{ "MOV $dst.lo,$src\n\t"
11252 "MOV $dst.hi,$src\n\t"
11253 "SAR $dst.hi,31" %}
11254 ins_encode(convert_int_long(dst,src));
11255 ins_pipe( ialu_reg_reg_long );
11256 %}
11258 // Zero-extend convert int to long
11259 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11260 match(Set dst (AndL (ConvI2L src) mask) );
11261 effect( KILL flags );
11262 ins_cost(250);
11263 format %{ "MOV $dst.lo,$src\n\t"
11264 "XOR $dst.hi,$dst.hi" %}
11265 opcode(0x33); // XOR
11266 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11267 ins_pipe( ialu_reg_reg_long );
11268 %}
11270 // Zero-extend long
11271 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11272 match(Set dst (AndL src mask) );
11273 effect( KILL flags );
11274 ins_cost(250);
11275 format %{ "MOV $dst.lo,$src.lo\n\t"
11276 "XOR $dst.hi,$dst.hi\n\t" %}
11277 opcode(0x33); // XOR
11278 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11279 ins_pipe( ialu_reg_reg_long );
11280 %}
11282 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11283 predicate (UseSSE<=1);
11284 match(Set dst (ConvL2D src));
11285 effect( KILL cr );
11286 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11287 "PUSH $src.lo\n\t"
11288 "FILD ST,[ESP + #0]\n\t"
11289 "ADD ESP,8\n\t"
11290 "FSTP_D $dst\t# D-round" %}
11291 opcode(0xDF, 0x5); /* DF /5 */
11292 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11293 ins_pipe( pipe_slow );
11294 %}
11296 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11297 predicate (UseSSE>=2);
11298 match(Set dst (ConvL2D src));
11299 effect( KILL cr );
11300 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11301 "PUSH $src.lo\n\t"
11302 "FILD_D [ESP]\n\t"
11303 "FSTP_D [ESP]\n\t"
11304 "MOVSD $dst,[ESP]\n\t"
11305 "ADD ESP,8" %}
11306 opcode(0xDF, 0x5); /* DF /5 */
11307 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11308 ins_pipe( pipe_slow );
11309 %}
11311 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11312 predicate (UseSSE>=1);
11313 match(Set dst (ConvL2F src));
11314 effect( KILL cr );
11315 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11316 "PUSH $src.lo\n\t"
11317 "FILD_D [ESP]\n\t"
11318 "FSTP_S [ESP]\n\t"
11319 "MOVSS $dst,[ESP]\n\t"
11320 "ADD ESP,8" %}
11321 opcode(0xDF, 0x5); /* DF /5 */
11322 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11323 ins_pipe( pipe_slow );
11324 %}
11326 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11327 match(Set dst (ConvL2F src));
11328 effect( KILL cr );
11329 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11330 "PUSH $src.lo\n\t"
11331 "FILD ST,[ESP + #0]\n\t"
11332 "ADD ESP,8\n\t"
11333 "FSTP_S $dst\t# F-round" %}
11334 opcode(0xDF, 0x5); /* DF /5 */
11335 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11336 ins_pipe( pipe_slow );
11337 %}
11339 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11340 match(Set dst (ConvL2I src));
11341 effect( DEF dst, USE src );
11342 format %{ "MOV $dst,$src.lo" %}
11343 ins_encode(enc_CopyL_Lo(dst,src));
11344 ins_pipe( ialu_reg_reg );
11345 %}
11348 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11349 match(Set dst (MoveF2I src));
11350 effect( DEF dst, USE src );
11351 ins_cost(100);
11352 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11353 ins_encode %{
11354 __ movl($dst$$Register, Address(rsp, $src$$disp));
11355 %}
11356 ins_pipe( ialu_reg_mem );
11357 %}
11359 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11360 predicate(UseSSE==0);
11361 match(Set dst (MoveF2I src));
11362 effect( DEF dst, USE src );
11364 ins_cost(125);
11365 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11366 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11367 ins_pipe( fpu_mem_reg );
11368 %}
11370 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11371 predicate(UseSSE>=1);
11372 match(Set dst (MoveF2I src));
11373 effect( DEF dst, USE src );
11375 ins_cost(95);
11376 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11377 ins_encode %{
11378 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11379 %}
11380 ins_pipe( pipe_slow );
11381 %}
11383 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11384 predicate(UseSSE>=2);
11385 match(Set dst (MoveF2I src));
11386 effect( DEF dst, USE src );
11387 ins_cost(85);
11388 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11389 ins_encode %{
11390 __ movdl($dst$$Register, $src$$XMMRegister);
11391 %}
11392 ins_pipe( pipe_slow );
11393 %}
11395 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11396 match(Set dst (MoveI2F src));
11397 effect( DEF dst, USE src );
11399 ins_cost(100);
11400 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11401 ins_encode %{
11402 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11403 %}
11404 ins_pipe( ialu_mem_reg );
11405 %}
11408 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11409 predicate(UseSSE==0);
11410 match(Set dst (MoveI2F src));
11411 effect(DEF dst, USE src);
11413 ins_cost(125);
11414 format %{ "FLD_S $src\n\t"
11415 "FSTP $dst\t# MoveI2F_stack_reg" %}
11416 opcode(0xD9); /* D9 /0, FLD m32real */
11417 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11418 Pop_Reg_FPR(dst) );
11419 ins_pipe( fpu_reg_mem );
11420 %}
11422 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11423 predicate(UseSSE>=1);
11424 match(Set dst (MoveI2F src));
11425 effect( DEF dst, USE src );
11427 ins_cost(95);
11428 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11429 ins_encode %{
11430 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11431 %}
11432 ins_pipe( pipe_slow );
11433 %}
11435 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11436 predicate(UseSSE>=2);
11437 match(Set dst (MoveI2F src));
11438 effect( DEF dst, USE src );
11440 ins_cost(85);
11441 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11442 ins_encode %{
11443 __ movdl($dst$$XMMRegister, $src$$Register);
11444 %}
11445 ins_pipe( pipe_slow );
11446 %}
11448 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11449 match(Set dst (MoveD2L src));
11450 effect(DEF dst, USE src);
11452 ins_cost(250);
11453 format %{ "MOV $dst.lo,$src\n\t"
11454 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11455 opcode(0x8B, 0x8B);
11456 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11457 ins_pipe( ialu_mem_long_reg );
11458 %}
11460 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11461 predicate(UseSSE<=1);
11462 match(Set dst (MoveD2L src));
11463 effect(DEF dst, USE src);
11465 ins_cost(125);
11466 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11467 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11468 ins_pipe( fpu_mem_reg );
11469 %}
11471 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11472 predicate(UseSSE>=2);
11473 match(Set dst (MoveD2L src));
11474 effect(DEF dst, USE src);
11475 ins_cost(95);
11476 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11477 ins_encode %{
11478 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11479 %}
11480 ins_pipe( pipe_slow );
11481 %}
11483 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11484 predicate(UseSSE>=2);
11485 match(Set dst (MoveD2L src));
11486 effect(DEF dst, USE src, TEMP tmp);
11487 ins_cost(85);
11488 format %{ "MOVD $dst.lo,$src\n\t"
11489 "PSHUFLW $tmp,$src,0x4E\n\t"
11490 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11491 ins_encode %{
11492 __ movdl($dst$$Register, $src$$XMMRegister);
11493 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11494 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11495 %}
11496 ins_pipe( pipe_slow );
11497 %}
11499 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11500 match(Set dst (MoveL2D src));
11501 effect(DEF dst, USE src);
11503 ins_cost(200);
11504 format %{ "MOV $dst,$src.lo\n\t"
11505 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11506 opcode(0x89, 0x89);
11507 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11508 ins_pipe( ialu_mem_long_reg );
11509 %}
11512 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11513 predicate(UseSSE<=1);
11514 match(Set dst (MoveL2D src));
11515 effect(DEF dst, USE src);
11516 ins_cost(125);
11518 format %{ "FLD_D $src\n\t"
11519 "FSTP $dst\t# MoveL2D_stack_reg" %}
11520 opcode(0xDD); /* DD /0, FLD m64real */
11521 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11522 Pop_Reg_DPR(dst) );
11523 ins_pipe( fpu_reg_mem );
11524 %}
11527 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11528 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11529 match(Set dst (MoveL2D src));
11530 effect(DEF dst, USE src);
11532 ins_cost(95);
11533 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11534 ins_encode %{
11535 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11536 %}
11537 ins_pipe( pipe_slow );
11538 %}
11540 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11541 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11542 match(Set dst (MoveL2D src));
11543 effect(DEF dst, USE src);
11545 ins_cost(95);
11546 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11547 ins_encode %{
11548 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11549 %}
11550 ins_pipe( pipe_slow );
11551 %}
11553 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11554 predicate(UseSSE>=2);
11555 match(Set dst (MoveL2D src));
11556 effect(TEMP dst, USE src, TEMP tmp);
11557 ins_cost(85);
11558 format %{ "MOVD $dst,$src.lo\n\t"
11559 "MOVD $tmp,$src.hi\n\t"
11560 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11561 ins_encode %{
11562 __ movdl($dst$$XMMRegister, $src$$Register);
11563 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11564 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11565 %}
11566 ins_pipe( pipe_slow );
11567 %}
11570 // =======================================================================
11571 // fast clearing of an array
11572 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11573 match(Set dummy (ClearArray cnt base));
11574 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11575 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11576 "XOR EAX,EAX\n\t"
11577 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11578 opcode(0,0x4);
11579 ins_encode( Opcode(0xD1), RegOpc(ECX),
11580 OpcRegReg(0x33,EAX,EAX),
11581 Opcode(0xF3), Opcode(0xAB) );
11582 ins_pipe( pipe_slow );
11583 %}
11585 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11586 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11587 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11588 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11590 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11591 ins_encode %{
11592 __ string_compare($str1$$Register, $str2$$Register,
11593 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11594 $tmp1$$XMMRegister);
11595 %}
11596 ins_pipe( pipe_slow );
11597 %}
11599 // fast string equals
11600 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11601 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11602 match(Set result (StrEquals (Binary str1 str2) cnt));
11603 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11605 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11606 ins_encode %{
11607 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11608 $cnt$$Register, $result$$Register, $tmp3$$Register,
11609 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11610 %}
11611 ins_pipe( pipe_slow );
11612 %}
11614 // fast search of substring with known size.
11615 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11616 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11617 predicate(UseSSE42Intrinsics);
11618 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11619 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11621 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11622 ins_encode %{
11623 int icnt2 = (int)$int_cnt2$$constant;
11624 if (icnt2 >= 8) {
11625 // IndexOf for constant substrings with size >= 8 elements
11626 // which don't need to be loaded through stack.
11627 __ string_indexofC8($str1$$Register, $str2$$Register,
11628 $cnt1$$Register, $cnt2$$Register,
11629 icnt2, $result$$Register,
11630 $vec$$XMMRegister, $tmp$$Register);
11631 } else {
11632 // Small strings are loaded through stack if they cross page boundary.
11633 __ string_indexof($str1$$Register, $str2$$Register,
11634 $cnt1$$Register, $cnt2$$Register,
11635 icnt2, $result$$Register,
11636 $vec$$XMMRegister, $tmp$$Register);
11637 }
11638 %}
11639 ins_pipe( pipe_slow );
11640 %}
11642 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11643 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11644 predicate(UseSSE42Intrinsics);
11645 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11646 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11648 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11649 ins_encode %{
11650 __ string_indexof($str1$$Register, $str2$$Register,
11651 $cnt1$$Register, $cnt2$$Register,
11652 (-1), $result$$Register,
11653 $vec$$XMMRegister, $tmp$$Register);
11654 %}
11655 ins_pipe( pipe_slow );
11656 %}
11658 // fast array equals
11659 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11660 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11661 %{
11662 match(Set result (AryEq ary1 ary2));
11663 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11664 //ins_cost(300);
11666 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11667 ins_encode %{
11668 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11669 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11670 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11671 %}
11672 ins_pipe( pipe_slow );
11673 %}
11675 //----------Control Flow Instructions------------------------------------------
11676 // Signed compare Instructions
11677 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11678 match(Set cr (CmpI op1 op2));
11679 effect( DEF cr, USE op1, USE op2 );
11680 format %{ "CMP $op1,$op2" %}
11681 opcode(0x3B); /* Opcode 3B /r */
11682 ins_encode( OpcP, RegReg( op1, op2) );
11683 ins_pipe( ialu_cr_reg_reg );
11684 %}
11686 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11687 match(Set cr (CmpI op1 op2));
11688 effect( DEF cr, USE op1 );
11689 format %{ "CMP $op1,$op2" %}
11690 opcode(0x81,0x07); /* Opcode 81 /7 */
11691 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11692 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11693 ins_pipe( ialu_cr_reg_imm );
11694 %}
11696 // Cisc-spilled version of cmpI_eReg
11697 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11698 match(Set cr (CmpI op1 (LoadI op2)));
11700 format %{ "CMP $op1,$op2" %}
11701 ins_cost(500);
11702 opcode(0x3B); /* Opcode 3B /r */
11703 ins_encode( OpcP, RegMem( op1, op2) );
11704 ins_pipe( ialu_cr_reg_mem );
11705 %}
11707 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11708 match(Set cr (CmpI src zero));
11709 effect( DEF cr, USE src );
11711 format %{ "TEST $src,$src" %}
11712 opcode(0x85);
11713 ins_encode( OpcP, RegReg( src, src ) );
11714 ins_pipe( ialu_cr_reg_imm );
11715 %}
11717 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11718 match(Set cr (CmpI (AndI src con) zero));
11720 format %{ "TEST $src,$con" %}
11721 opcode(0xF7,0x00);
11722 ins_encode( OpcP, RegOpc(src), Con32(con) );
11723 ins_pipe( ialu_cr_reg_imm );
11724 %}
11726 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11727 match(Set cr (CmpI (AndI src mem) zero));
11729 format %{ "TEST $src,$mem" %}
11730 opcode(0x85);
11731 ins_encode( OpcP, RegMem( src, mem ) );
11732 ins_pipe( ialu_cr_reg_mem );
11733 %}
11735 // Unsigned compare Instructions; really, same as signed except they
11736 // produce an eFlagsRegU instead of eFlagsReg.
11737 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11738 match(Set cr (CmpU op1 op2));
11740 format %{ "CMPu $op1,$op2" %}
11741 opcode(0x3B); /* Opcode 3B /r */
11742 ins_encode( OpcP, RegReg( op1, op2) );
11743 ins_pipe( ialu_cr_reg_reg );
11744 %}
11746 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11747 match(Set cr (CmpU op1 op2));
11749 format %{ "CMPu $op1,$op2" %}
11750 opcode(0x81,0x07); /* Opcode 81 /7 */
11751 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11752 ins_pipe( ialu_cr_reg_imm );
11753 %}
11755 // // Cisc-spilled version of cmpU_eReg
11756 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11757 match(Set cr (CmpU op1 (LoadI op2)));
11759 format %{ "CMPu $op1,$op2" %}
11760 ins_cost(500);
11761 opcode(0x3B); /* Opcode 3B /r */
11762 ins_encode( OpcP, RegMem( op1, op2) );
11763 ins_pipe( ialu_cr_reg_mem );
11764 %}
11766 // // Cisc-spilled version of cmpU_eReg
11767 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11768 // match(Set cr (CmpU (LoadI op1) op2));
11769 //
11770 // format %{ "CMPu $op1,$op2" %}
11771 // ins_cost(500);
11772 // opcode(0x39); /* Opcode 39 /r */
11773 // ins_encode( OpcP, RegMem( op1, op2) );
11774 //%}
11776 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11777 match(Set cr (CmpU src zero));
11779 format %{ "TESTu $src,$src" %}
11780 opcode(0x85);
11781 ins_encode( OpcP, RegReg( src, src ) );
11782 ins_pipe( ialu_cr_reg_imm );
11783 %}
11785 // Unsigned pointer compare Instructions
11786 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11787 match(Set cr (CmpP op1 op2));
11789 format %{ "CMPu $op1,$op2" %}
11790 opcode(0x3B); /* Opcode 3B /r */
11791 ins_encode( OpcP, RegReg( op1, op2) );
11792 ins_pipe( ialu_cr_reg_reg );
11793 %}
11795 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11796 match(Set cr (CmpP op1 op2));
11798 format %{ "CMPu $op1,$op2" %}
11799 opcode(0x81,0x07); /* Opcode 81 /7 */
11800 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11801 ins_pipe( ialu_cr_reg_imm );
11802 %}
11804 // // Cisc-spilled version of cmpP_eReg
11805 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11806 match(Set cr (CmpP op1 (LoadP op2)));
11808 format %{ "CMPu $op1,$op2" %}
11809 ins_cost(500);
11810 opcode(0x3B); /* Opcode 3B /r */
11811 ins_encode( OpcP, RegMem( op1, op2) );
11812 ins_pipe( ialu_cr_reg_mem );
11813 %}
11815 // // Cisc-spilled version of cmpP_eReg
11816 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11817 // match(Set cr (CmpP (LoadP op1) op2));
11818 //
11819 // format %{ "CMPu $op1,$op2" %}
11820 // ins_cost(500);
11821 // opcode(0x39); /* Opcode 39 /r */
11822 // ins_encode( OpcP, RegMem( op1, op2) );
11823 //%}
11825 // Compare raw pointer (used in out-of-heap check).
11826 // Only works because non-oop pointers must be raw pointers
11827 // and raw pointers have no anti-dependencies.
11828 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11829 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11830 match(Set cr (CmpP op1 (LoadP op2)));
11832 format %{ "CMPu $op1,$op2" %}
11833 opcode(0x3B); /* Opcode 3B /r */
11834 ins_encode( OpcP, RegMem( op1, op2) );
11835 ins_pipe( ialu_cr_reg_mem );
11836 %}
11838 //
11839 // This will generate a signed flags result. This should be ok
11840 // since any compare to a zero should be eq/neq.
11841 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11842 match(Set cr (CmpP src zero));
11844 format %{ "TEST $src,$src" %}
11845 opcode(0x85);
11846 ins_encode( OpcP, RegReg( src, src ) );
11847 ins_pipe( ialu_cr_reg_imm );
11848 %}
11850 // Cisc-spilled version of testP_reg
11851 // This will generate a signed flags result. This should be ok
11852 // since any compare to a zero should be eq/neq.
11853 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11854 match(Set cr (CmpP (LoadP op) zero));
11856 format %{ "TEST $op,0xFFFFFFFF" %}
11857 ins_cost(500);
11858 opcode(0xF7); /* Opcode F7 /0 */
11859 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11860 ins_pipe( ialu_cr_reg_imm );
11861 %}
11863 // Yanked all unsigned pointer compare operations.
11864 // Pointer compares are done with CmpP which is already unsigned.
11866 //----------Max and Min--------------------------------------------------------
11867 // Min Instructions
11868 ////
11869 // *** Min and Max using the conditional move are slower than the
11870 // *** branch version on a Pentium III.
11871 // // Conditional move for min
11872 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11873 // effect( USE_DEF op2, USE op1, USE cr );
11874 // format %{ "CMOVlt $op2,$op1\t! min" %}
11875 // opcode(0x4C,0x0F);
11876 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11877 // ins_pipe( pipe_cmov_reg );
11878 //%}
11879 //
11880 //// Min Register with Register (P6 version)
11881 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11882 // predicate(VM_Version::supports_cmov() );
11883 // match(Set op2 (MinI op1 op2));
11884 // ins_cost(200);
11885 // expand %{
11886 // eFlagsReg cr;
11887 // compI_eReg(cr,op1,op2);
11888 // cmovI_reg_lt(op2,op1,cr);
11889 // %}
11890 //%}
11892 // Min Register with Register (generic version)
11893 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11894 match(Set dst (MinI dst src));
11895 effect(KILL flags);
11896 ins_cost(300);
11898 format %{ "MIN $dst,$src" %}
11899 opcode(0xCC);
11900 ins_encode( min_enc(dst,src) );
11901 ins_pipe( pipe_slow );
11902 %}
11904 // Max Register with Register
11905 // *** Min and Max using the conditional move are slower than the
11906 // *** branch version on a Pentium III.
11907 // // Conditional move for max
11908 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11909 // effect( USE_DEF op2, USE op1, USE cr );
11910 // format %{ "CMOVgt $op2,$op1\t! max" %}
11911 // opcode(0x4F,0x0F);
11912 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11913 // ins_pipe( pipe_cmov_reg );
11914 //%}
11915 //
11916 // // Max Register with Register (P6 version)
11917 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11918 // predicate(VM_Version::supports_cmov() );
11919 // match(Set op2 (MaxI op1 op2));
11920 // ins_cost(200);
11921 // expand %{
11922 // eFlagsReg cr;
11923 // compI_eReg(cr,op1,op2);
11924 // cmovI_reg_gt(op2,op1,cr);
11925 // %}
11926 //%}
11928 // Max Register with Register (generic version)
11929 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11930 match(Set dst (MaxI dst src));
11931 effect(KILL flags);
11932 ins_cost(300);
11934 format %{ "MAX $dst,$src" %}
11935 opcode(0xCC);
11936 ins_encode( max_enc(dst,src) );
11937 ins_pipe( pipe_slow );
11938 %}
11940 // ============================================================================
11941 // Counted Loop limit node which represents exact final iterator value.
11942 // Note: the resulting value should fit into integer range since
11943 // counted loops have limit check on overflow.
11944 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11945 match(Set limit (LoopLimit (Binary init limit) stride));
11946 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11947 ins_cost(300);
11949 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11950 ins_encode %{
11951 int strd = (int)$stride$$constant;
11952 assert(strd != 1 && strd != -1, "sanity");
11953 int m1 = (strd > 0) ? 1 : -1;
11954 // Convert limit to long (EAX:EDX)
11955 __ cdql();
11956 // Convert init to long (init:tmp)
11957 __ movl($tmp$$Register, $init$$Register);
11958 __ sarl($tmp$$Register, 31);
11959 // $limit - $init
11960 __ subl($limit$$Register, $init$$Register);
11961 __ sbbl($limit_hi$$Register, $tmp$$Register);
11962 // + ($stride - 1)
11963 if (strd > 0) {
11964 __ addl($limit$$Register, (strd - 1));
11965 __ adcl($limit_hi$$Register, 0);
11966 __ movl($tmp$$Register, strd);
11967 } else {
11968 __ addl($limit$$Register, (strd + 1));
11969 __ adcl($limit_hi$$Register, -1);
11970 __ lneg($limit_hi$$Register, $limit$$Register);
11971 __ movl($tmp$$Register, -strd);
11972 }
11973 // signed devision: (EAX:EDX) / pos_stride
11974 __ idivl($tmp$$Register);
11975 if (strd < 0) {
11976 // restore sign
11977 __ negl($tmp$$Register);
11978 }
11979 // (EAX) * stride
11980 __ mull($tmp$$Register);
11981 // + init (ignore upper bits)
11982 __ addl($limit$$Register, $init$$Register);
11983 %}
11984 ins_pipe( pipe_slow );
11985 %}
11987 // ============================================================================
11988 // Branch Instructions
11989 // Jump Table
11990 instruct jumpXtnd(rRegI switch_val) %{
11991 match(Jump switch_val);
11992 ins_cost(350);
11993 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11994 ins_encode %{
11995 // Jump to Address(table_base + switch_reg)
11996 Address index(noreg, $switch_val$$Register, Address::times_1);
11997 __ jump(ArrayAddress($constantaddress, index));
11998 %}
11999 ins_pipe(pipe_jmp);
12000 %}
12002 // Jump Direct - Label defines a relative address from JMP+1
12003 instruct jmpDir(label labl) %{
12004 match(Goto);
12005 effect(USE labl);
12007 ins_cost(300);
12008 format %{ "JMP $labl" %}
12009 size(5);
12010 ins_encode %{
12011 Label* L = $labl$$label;
12012 __ jmp(*L, false); // Always long jump
12013 %}
12014 ins_pipe( pipe_jmp );
12015 %}
12017 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12018 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12019 match(If cop cr);
12020 effect(USE labl);
12022 ins_cost(300);
12023 format %{ "J$cop $labl" %}
12024 size(6);
12025 ins_encode %{
12026 Label* L = $labl$$label;
12027 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12028 %}
12029 ins_pipe( pipe_jcc );
12030 %}
12032 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12033 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12034 match(CountedLoopEnd cop cr);
12035 effect(USE labl);
12037 ins_cost(300);
12038 format %{ "J$cop $labl\t# Loop end" %}
12039 size(6);
12040 ins_encode %{
12041 Label* L = $labl$$label;
12042 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12043 %}
12044 ins_pipe( pipe_jcc );
12045 %}
12047 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12048 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12049 match(CountedLoopEnd cop cmp);
12050 effect(USE labl);
12052 ins_cost(300);
12053 format %{ "J$cop,u $labl\t# Loop end" %}
12054 size(6);
12055 ins_encode %{
12056 Label* L = $labl$$label;
12057 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12058 %}
12059 ins_pipe( pipe_jcc );
12060 %}
12062 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12063 match(CountedLoopEnd cop cmp);
12064 effect(USE labl);
12066 ins_cost(200);
12067 format %{ "J$cop,u $labl\t# Loop end" %}
12068 size(6);
12069 ins_encode %{
12070 Label* L = $labl$$label;
12071 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12072 %}
12073 ins_pipe( pipe_jcc );
12074 %}
12076 // Jump Direct Conditional - using unsigned comparison
12077 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12078 match(If cop cmp);
12079 effect(USE labl);
12081 ins_cost(300);
12082 format %{ "J$cop,u $labl" %}
12083 size(6);
12084 ins_encode %{
12085 Label* L = $labl$$label;
12086 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12087 %}
12088 ins_pipe(pipe_jcc);
12089 %}
12091 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12092 match(If cop cmp);
12093 effect(USE labl);
12095 ins_cost(200);
12096 format %{ "J$cop,u $labl" %}
12097 size(6);
12098 ins_encode %{
12099 Label* L = $labl$$label;
12100 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12101 %}
12102 ins_pipe(pipe_jcc);
12103 %}
12105 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12106 match(If cop cmp);
12107 effect(USE labl);
12109 ins_cost(200);
12110 format %{ $$template
12111 if ($cop$$cmpcode == Assembler::notEqual) {
12112 $$emit$$"JP,u $labl\n\t"
12113 $$emit$$"J$cop,u $labl"
12114 } else {
12115 $$emit$$"JP,u done\n\t"
12116 $$emit$$"J$cop,u $labl\n\t"
12117 $$emit$$"done:"
12118 }
12119 %}
12120 ins_encode %{
12121 Label* l = $labl$$label;
12122 if ($cop$$cmpcode == Assembler::notEqual) {
12123 __ jcc(Assembler::parity, *l, false);
12124 __ jcc(Assembler::notEqual, *l, false);
12125 } else if ($cop$$cmpcode == Assembler::equal) {
12126 Label done;
12127 __ jccb(Assembler::parity, done);
12128 __ jcc(Assembler::equal, *l, false);
12129 __ bind(done);
12130 } else {
12131 ShouldNotReachHere();
12132 }
12133 %}
12134 ins_pipe(pipe_jcc);
12135 %}
12137 // ============================================================================
12138 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12139 // array for an instance of the superklass. Set a hidden internal cache on a
12140 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12141 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12142 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12143 match(Set result (PartialSubtypeCheck sub super));
12144 effect( KILL rcx, KILL cr );
12146 ins_cost(1100); // slightly larger than the next version
12147 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12148 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12149 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12150 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12151 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12152 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12153 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12154 "miss:\t" %}
12156 opcode(0x1); // Force a XOR of EDI
12157 ins_encode( enc_PartialSubtypeCheck() );
12158 ins_pipe( pipe_slow );
12159 %}
12161 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12162 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12163 effect( KILL rcx, KILL result );
12165 ins_cost(1000);
12166 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12167 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12168 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12169 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12170 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12171 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12172 "miss:\t" %}
12174 opcode(0x0); // No need to XOR EDI
12175 ins_encode( enc_PartialSubtypeCheck() );
12176 ins_pipe( pipe_slow );
12177 %}
12179 // ============================================================================
12180 // Branch Instructions -- short offset versions
12181 //
12182 // These instructions are used to replace jumps of a long offset (the default
12183 // match) with jumps of a shorter offset. These instructions are all tagged
12184 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12185 // match rules in general matching. Instead, the ADLC generates a conversion
12186 // method in the MachNode which can be used to do in-place replacement of the
12187 // long variant with the shorter variant. The compiler will determine if a
12188 // branch can be taken by the is_short_branch_offset() predicate in the machine
12189 // specific code section of the file.
12191 // Jump Direct - Label defines a relative address from JMP+1
12192 instruct jmpDir_short(label labl) %{
12193 match(Goto);
12194 effect(USE labl);
12196 ins_cost(300);
12197 format %{ "JMP,s $labl" %}
12198 size(2);
12199 ins_encode %{
12200 Label* L = $labl$$label;
12201 __ jmpb(*L);
12202 %}
12203 ins_pipe( pipe_jmp );
12204 ins_short_branch(1);
12205 %}
12207 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12208 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12209 match(If cop cr);
12210 effect(USE labl);
12212 ins_cost(300);
12213 format %{ "J$cop,s $labl" %}
12214 size(2);
12215 ins_encode %{
12216 Label* L = $labl$$label;
12217 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12218 %}
12219 ins_pipe( pipe_jcc );
12220 ins_short_branch(1);
12221 %}
12223 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12224 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12225 match(CountedLoopEnd cop cr);
12226 effect(USE labl);
12228 ins_cost(300);
12229 format %{ "J$cop,s $labl\t# Loop end" %}
12230 size(2);
12231 ins_encode %{
12232 Label* L = $labl$$label;
12233 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12234 %}
12235 ins_pipe( pipe_jcc );
12236 ins_short_branch(1);
12237 %}
12239 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12240 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12241 match(CountedLoopEnd cop cmp);
12242 effect(USE labl);
12244 ins_cost(300);
12245 format %{ "J$cop,us $labl\t# Loop end" %}
12246 size(2);
12247 ins_encode %{
12248 Label* L = $labl$$label;
12249 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12250 %}
12251 ins_pipe( pipe_jcc );
12252 ins_short_branch(1);
12253 %}
12255 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12256 match(CountedLoopEnd cop cmp);
12257 effect(USE labl);
12259 ins_cost(300);
12260 format %{ "J$cop,us $labl\t# Loop end" %}
12261 size(2);
12262 ins_encode %{
12263 Label* L = $labl$$label;
12264 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12265 %}
12266 ins_pipe( pipe_jcc );
12267 ins_short_branch(1);
12268 %}
12270 // Jump Direct Conditional - using unsigned comparison
12271 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12272 match(If cop cmp);
12273 effect(USE labl);
12275 ins_cost(300);
12276 format %{ "J$cop,us $labl" %}
12277 size(2);
12278 ins_encode %{
12279 Label* L = $labl$$label;
12280 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12281 %}
12282 ins_pipe( pipe_jcc );
12283 ins_short_branch(1);
12284 %}
12286 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12287 match(If cop cmp);
12288 effect(USE labl);
12290 ins_cost(300);
12291 format %{ "J$cop,us $labl" %}
12292 size(2);
12293 ins_encode %{
12294 Label* L = $labl$$label;
12295 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12296 %}
12297 ins_pipe( pipe_jcc );
12298 ins_short_branch(1);
12299 %}
12301 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12302 match(If cop cmp);
12303 effect(USE labl);
12305 ins_cost(300);
12306 format %{ $$template
12307 if ($cop$$cmpcode == Assembler::notEqual) {
12308 $$emit$$"JP,u,s $labl\n\t"
12309 $$emit$$"J$cop,u,s $labl"
12310 } else {
12311 $$emit$$"JP,u,s done\n\t"
12312 $$emit$$"J$cop,u,s $labl\n\t"
12313 $$emit$$"done:"
12314 }
12315 %}
12316 size(4);
12317 ins_encode %{
12318 Label* l = $labl$$label;
12319 if ($cop$$cmpcode == Assembler::notEqual) {
12320 __ jccb(Assembler::parity, *l);
12321 __ jccb(Assembler::notEqual, *l);
12322 } else if ($cop$$cmpcode == Assembler::equal) {
12323 Label done;
12324 __ jccb(Assembler::parity, done);
12325 __ jccb(Assembler::equal, *l);
12326 __ bind(done);
12327 } else {
12328 ShouldNotReachHere();
12329 }
12330 %}
12331 ins_pipe(pipe_jcc);
12332 ins_short_branch(1);
12333 %}
12335 // ============================================================================
12336 // Long Compare
12337 //
12338 // Currently we hold longs in 2 registers. Comparing such values efficiently
12339 // is tricky. The flavor of compare used depends on whether we are testing
12340 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12341 // The GE test is the negated LT test. The LE test can be had by commuting
12342 // the operands (yielding a GE test) and then negating; negate again for the
12343 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12344 // NE test is negated from that.
12346 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12347 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12348 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12349 // are collapsed internally in the ADLC's dfa-gen code. The match for
12350 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12351 // foo match ends up with the wrong leaf. One fix is to not match both
12352 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12353 // both forms beat the trinary form of long-compare and both are very useful
12354 // on Intel which has so few registers.
12356 // Manifest a CmpL result in an integer register. Very painful.
12357 // This is the test to avoid.
12358 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12359 match(Set dst (CmpL3 src1 src2));
12360 effect( KILL flags );
12361 ins_cost(1000);
12362 format %{ "XOR $dst,$dst\n\t"
12363 "CMP $src1.hi,$src2.hi\n\t"
12364 "JLT,s m_one\n\t"
12365 "JGT,s p_one\n\t"
12366 "CMP $src1.lo,$src2.lo\n\t"
12367 "JB,s m_one\n\t"
12368 "JEQ,s done\n"
12369 "p_one:\tINC $dst\n\t"
12370 "JMP,s done\n"
12371 "m_one:\tDEC $dst\n"
12372 "done:" %}
12373 ins_encode %{
12374 Label p_one, m_one, done;
12375 __ xorptr($dst$$Register, $dst$$Register);
12376 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12377 __ jccb(Assembler::less, m_one);
12378 __ jccb(Assembler::greater, p_one);
12379 __ cmpl($src1$$Register, $src2$$Register);
12380 __ jccb(Assembler::below, m_one);
12381 __ jccb(Assembler::equal, done);
12382 __ bind(p_one);
12383 __ incrementl($dst$$Register);
12384 __ jmpb(done);
12385 __ bind(m_one);
12386 __ decrementl($dst$$Register);
12387 __ bind(done);
12388 %}
12389 ins_pipe( pipe_slow );
12390 %}
12392 //======
12393 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12394 // compares. Can be used for LE or GT compares by reversing arguments.
12395 // NOT GOOD FOR EQ/NE tests.
12396 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12397 match( Set flags (CmpL src zero ));
12398 ins_cost(100);
12399 format %{ "TEST $src.hi,$src.hi" %}
12400 opcode(0x85);
12401 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12402 ins_pipe( ialu_cr_reg_reg );
12403 %}
12405 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12406 // compares. Can be used for LE or GT compares by reversing arguments.
12407 // NOT GOOD FOR EQ/NE tests.
12408 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12409 match( Set flags (CmpL src1 src2 ));
12410 effect( TEMP tmp );
12411 ins_cost(300);
12412 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12413 "MOV $tmp,$src1.hi\n\t"
12414 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12415 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12416 ins_pipe( ialu_cr_reg_reg );
12417 %}
12419 // Long compares reg < zero/req OR reg >= zero/req.
12420 // Just a wrapper for a normal branch, plus the predicate test.
12421 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12422 match(If cmp flags);
12423 effect(USE labl);
12424 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12425 expand %{
12426 jmpCon(cmp,flags,labl); // JLT or JGE...
12427 %}
12428 %}
12430 // Compare 2 longs and CMOVE longs.
12431 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12432 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12433 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12434 ins_cost(400);
12435 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12436 "CMOV$cmp $dst.hi,$src.hi" %}
12437 opcode(0x0F,0x40);
12438 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12439 ins_pipe( pipe_cmov_reg_long );
12440 %}
12442 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12443 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12444 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12445 ins_cost(500);
12446 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12447 "CMOV$cmp $dst.hi,$src.hi" %}
12448 opcode(0x0F,0x40);
12449 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12450 ins_pipe( pipe_cmov_reg_long );
12451 %}
12453 // Compare 2 longs and CMOVE ints.
12454 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12455 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12456 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12457 ins_cost(200);
12458 format %{ "CMOV$cmp $dst,$src" %}
12459 opcode(0x0F,0x40);
12460 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12461 ins_pipe( pipe_cmov_reg );
12462 %}
12464 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12465 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12466 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12467 ins_cost(250);
12468 format %{ "CMOV$cmp $dst,$src" %}
12469 opcode(0x0F,0x40);
12470 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12471 ins_pipe( pipe_cmov_mem );
12472 %}
12474 // Compare 2 longs and CMOVE ints.
12475 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12476 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12477 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12478 ins_cost(200);
12479 format %{ "CMOV$cmp $dst,$src" %}
12480 opcode(0x0F,0x40);
12481 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12482 ins_pipe( pipe_cmov_reg );
12483 %}
12485 // Compare 2 longs and CMOVE doubles
12486 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12487 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12488 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12489 ins_cost(200);
12490 expand %{
12491 fcmovDPR_regS(cmp,flags,dst,src);
12492 %}
12493 %}
12495 // Compare 2 longs and CMOVE doubles
12496 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12497 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12498 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12499 ins_cost(200);
12500 expand %{
12501 fcmovD_regS(cmp,flags,dst,src);
12502 %}
12503 %}
12505 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12506 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12507 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12508 ins_cost(200);
12509 expand %{
12510 fcmovFPR_regS(cmp,flags,dst,src);
12511 %}
12512 %}
12514 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12515 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12516 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12517 ins_cost(200);
12518 expand %{
12519 fcmovF_regS(cmp,flags,dst,src);
12520 %}
12521 %}
12523 //======
12524 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12525 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12526 match( Set flags (CmpL src zero ));
12527 effect(TEMP tmp);
12528 ins_cost(200);
12529 format %{ "MOV $tmp,$src.lo\n\t"
12530 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12531 ins_encode( long_cmp_flags0( src, tmp ) );
12532 ins_pipe( ialu_reg_reg_long );
12533 %}
12535 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12536 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12537 match( Set flags (CmpL src1 src2 ));
12538 ins_cost(200+300);
12539 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12540 "JNE,s skip\n\t"
12541 "CMP $src1.hi,$src2.hi\n\t"
12542 "skip:\t" %}
12543 ins_encode( long_cmp_flags1( src1, src2 ) );
12544 ins_pipe( ialu_cr_reg_reg );
12545 %}
12547 // Long compare reg == zero/reg OR reg != zero/reg
12548 // Just a wrapper for a normal branch, plus the predicate test.
12549 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12550 match(If cmp flags);
12551 effect(USE labl);
12552 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12553 expand %{
12554 jmpCon(cmp,flags,labl); // JEQ or JNE...
12555 %}
12556 %}
12558 // Compare 2 longs and CMOVE longs.
12559 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12560 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12561 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12562 ins_cost(400);
12563 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12564 "CMOV$cmp $dst.hi,$src.hi" %}
12565 opcode(0x0F,0x40);
12566 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12567 ins_pipe( pipe_cmov_reg_long );
12568 %}
12570 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12571 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12572 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12573 ins_cost(500);
12574 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12575 "CMOV$cmp $dst.hi,$src.hi" %}
12576 opcode(0x0F,0x40);
12577 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12578 ins_pipe( pipe_cmov_reg_long );
12579 %}
12581 // Compare 2 longs and CMOVE ints.
12582 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12583 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12584 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12585 ins_cost(200);
12586 format %{ "CMOV$cmp $dst,$src" %}
12587 opcode(0x0F,0x40);
12588 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12589 ins_pipe( pipe_cmov_reg );
12590 %}
12592 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12593 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12594 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12595 ins_cost(250);
12596 format %{ "CMOV$cmp $dst,$src" %}
12597 opcode(0x0F,0x40);
12598 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12599 ins_pipe( pipe_cmov_mem );
12600 %}
12602 // Compare 2 longs and CMOVE ints.
12603 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12604 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12605 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12606 ins_cost(200);
12607 format %{ "CMOV$cmp $dst,$src" %}
12608 opcode(0x0F,0x40);
12609 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12610 ins_pipe( pipe_cmov_reg );
12611 %}
12613 // Compare 2 longs and CMOVE doubles
12614 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12615 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12616 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12617 ins_cost(200);
12618 expand %{
12619 fcmovDPR_regS(cmp,flags,dst,src);
12620 %}
12621 %}
12623 // Compare 2 longs and CMOVE doubles
12624 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12625 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12626 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12627 ins_cost(200);
12628 expand %{
12629 fcmovD_regS(cmp,flags,dst,src);
12630 %}
12631 %}
12633 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12634 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12635 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12636 ins_cost(200);
12637 expand %{
12638 fcmovFPR_regS(cmp,flags,dst,src);
12639 %}
12640 %}
12642 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12643 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12644 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12645 ins_cost(200);
12646 expand %{
12647 fcmovF_regS(cmp,flags,dst,src);
12648 %}
12649 %}
12651 //======
12652 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12653 // Same as cmpL_reg_flags_LEGT except must negate src
12654 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12655 match( Set flags (CmpL src zero ));
12656 effect( TEMP tmp );
12657 ins_cost(300);
12658 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12659 "CMP $tmp,$src.lo\n\t"
12660 "SBB $tmp,$src.hi\n\t" %}
12661 ins_encode( long_cmp_flags3(src, tmp) );
12662 ins_pipe( ialu_reg_reg_long );
12663 %}
12665 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12666 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12667 // requires a commuted test to get the same result.
12668 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12669 match( Set flags (CmpL src1 src2 ));
12670 effect( TEMP tmp );
12671 ins_cost(300);
12672 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12673 "MOV $tmp,$src2.hi\n\t"
12674 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12675 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12676 ins_pipe( ialu_cr_reg_reg );
12677 %}
12679 // Long compares reg < zero/req OR reg >= zero/req.
12680 // Just a wrapper for a normal branch, plus the predicate test
12681 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12682 match(If cmp flags);
12683 effect(USE labl);
12684 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12685 ins_cost(300);
12686 expand %{
12687 jmpCon(cmp,flags,labl); // JGT or JLE...
12688 %}
12689 %}
12691 // Compare 2 longs and CMOVE longs.
12692 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12693 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12694 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12695 ins_cost(400);
12696 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12697 "CMOV$cmp $dst.hi,$src.hi" %}
12698 opcode(0x0F,0x40);
12699 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12700 ins_pipe( pipe_cmov_reg_long );
12701 %}
12703 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12704 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12705 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12706 ins_cost(500);
12707 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12708 "CMOV$cmp $dst.hi,$src.hi+4" %}
12709 opcode(0x0F,0x40);
12710 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12711 ins_pipe( pipe_cmov_reg_long );
12712 %}
12714 // Compare 2 longs and CMOVE ints.
12715 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12716 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12717 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12718 ins_cost(200);
12719 format %{ "CMOV$cmp $dst,$src" %}
12720 opcode(0x0F,0x40);
12721 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12722 ins_pipe( pipe_cmov_reg );
12723 %}
12725 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12726 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12727 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12728 ins_cost(250);
12729 format %{ "CMOV$cmp $dst,$src" %}
12730 opcode(0x0F,0x40);
12731 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12732 ins_pipe( pipe_cmov_mem );
12733 %}
12735 // Compare 2 longs and CMOVE ptrs.
12736 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12737 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12738 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12739 ins_cost(200);
12740 format %{ "CMOV$cmp $dst,$src" %}
12741 opcode(0x0F,0x40);
12742 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12743 ins_pipe( pipe_cmov_reg );
12744 %}
12746 // Compare 2 longs and CMOVE doubles
12747 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12748 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12749 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12750 ins_cost(200);
12751 expand %{
12752 fcmovDPR_regS(cmp,flags,dst,src);
12753 %}
12754 %}
12756 // Compare 2 longs and CMOVE doubles
12757 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12758 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12759 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12760 ins_cost(200);
12761 expand %{
12762 fcmovD_regS(cmp,flags,dst,src);
12763 %}
12764 %}
12766 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12767 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12768 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12769 ins_cost(200);
12770 expand %{
12771 fcmovFPR_regS(cmp,flags,dst,src);
12772 %}
12773 %}
12776 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12777 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12778 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12779 ins_cost(200);
12780 expand %{
12781 fcmovF_regS(cmp,flags,dst,src);
12782 %}
12783 %}
12786 // ============================================================================
12787 // Procedure Call/Return Instructions
12788 // Call Java Static Instruction
12789 // Note: If this code changes, the corresponding ret_addr_offset() and
12790 // compute_padding() functions will have to be adjusted.
12791 instruct CallStaticJavaDirect(method meth) %{
12792 match(CallStaticJava);
12793 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12794 effect(USE meth);
12796 ins_cost(300);
12797 format %{ "CALL,static " %}
12798 opcode(0xE8); /* E8 cd */
12799 ins_encode( pre_call_FPU,
12800 Java_Static_Call( meth ),
12801 call_epilog,
12802 post_call_FPU );
12803 ins_pipe( pipe_slow );
12804 ins_alignment(4);
12805 %}
12807 // Call Java Static Instruction (method handle version)
12808 // Note: If this code changes, the corresponding ret_addr_offset() and
12809 // compute_padding() functions will have to be adjusted.
12810 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12811 match(CallStaticJava);
12812 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12813 effect(USE meth);
12814 // EBP is saved by all callees (for interpreter stack correction).
12815 // We use it here for a similar purpose, in {preserve,restore}_SP.
12817 ins_cost(300);
12818 format %{ "CALL,static/MethodHandle " %}
12819 opcode(0xE8); /* E8 cd */
12820 ins_encode( pre_call_FPU,
12821 preserve_SP,
12822 Java_Static_Call( meth ),
12823 restore_SP,
12824 call_epilog,
12825 post_call_FPU );
12826 ins_pipe( pipe_slow );
12827 ins_alignment(4);
12828 %}
12830 // Call Java Dynamic Instruction
12831 // Note: If this code changes, the corresponding ret_addr_offset() and
12832 // compute_padding() functions will have to be adjusted.
12833 instruct CallDynamicJavaDirect(method meth) %{
12834 match(CallDynamicJava);
12835 effect(USE meth);
12837 ins_cost(300);
12838 format %{ "MOV EAX,(oop)-1\n\t"
12839 "CALL,dynamic" %}
12840 opcode(0xE8); /* E8 cd */
12841 ins_encode( pre_call_FPU,
12842 Java_Dynamic_Call( meth ),
12843 call_epilog,
12844 post_call_FPU );
12845 ins_pipe( pipe_slow );
12846 ins_alignment(4);
12847 %}
12849 // Call Runtime Instruction
12850 instruct CallRuntimeDirect(method meth) %{
12851 match(CallRuntime );
12852 effect(USE meth);
12854 ins_cost(300);
12855 format %{ "CALL,runtime " %}
12856 opcode(0xE8); /* E8 cd */
12857 // Use FFREEs to clear entries in float stack
12858 ins_encode( pre_call_FPU,
12859 FFree_Float_Stack_All,
12860 Java_To_Runtime( meth ),
12861 post_call_FPU );
12862 ins_pipe( pipe_slow );
12863 %}
12865 // Call runtime without safepoint
12866 instruct CallLeafDirect(method meth) %{
12867 match(CallLeaf);
12868 effect(USE meth);
12870 ins_cost(300);
12871 format %{ "CALL_LEAF,runtime " %}
12872 opcode(0xE8); /* E8 cd */
12873 ins_encode( pre_call_FPU,
12874 FFree_Float_Stack_All,
12875 Java_To_Runtime( meth ),
12876 Verify_FPU_For_Leaf, post_call_FPU );
12877 ins_pipe( pipe_slow );
12878 %}
12880 instruct CallLeafNoFPDirect(method meth) %{
12881 match(CallLeafNoFP);
12882 effect(USE meth);
12884 ins_cost(300);
12885 format %{ "CALL_LEAF_NOFP,runtime " %}
12886 opcode(0xE8); /* E8 cd */
12887 ins_encode(Java_To_Runtime(meth));
12888 ins_pipe( pipe_slow );
12889 %}
12892 // Return Instruction
12893 // Remove the return address & jump to it.
12894 instruct Ret() %{
12895 match(Return);
12896 format %{ "RET" %}
12897 opcode(0xC3);
12898 ins_encode(OpcP);
12899 ins_pipe( pipe_jmp );
12900 %}
12902 // Tail Call; Jump from runtime stub to Java code.
12903 // Also known as an 'interprocedural jump'.
12904 // Target of jump will eventually return to caller.
12905 // TailJump below removes the return address.
12906 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12907 match(TailCall jump_target method_oop );
12908 ins_cost(300);
12909 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12910 opcode(0xFF, 0x4); /* Opcode FF /4 */
12911 ins_encode( OpcP, RegOpc(jump_target) );
12912 ins_pipe( pipe_jmp );
12913 %}
12916 // Tail Jump; remove the return address; jump to target.
12917 // TailCall above leaves the return address around.
12918 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12919 match( TailJump jump_target ex_oop );
12920 ins_cost(300);
12921 format %{ "POP EDX\t# pop return address into dummy\n\t"
12922 "JMP $jump_target " %}
12923 opcode(0xFF, 0x4); /* Opcode FF /4 */
12924 ins_encode( enc_pop_rdx,
12925 OpcP, RegOpc(jump_target) );
12926 ins_pipe( pipe_jmp );
12927 %}
12929 // Create exception oop: created by stack-crawling runtime code.
12930 // Created exception is now available to this handler, and is setup
12931 // just prior to jumping to this handler. No code emitted.
12932 instruct CreateException( eAXRegP ex_oop )
12933 %{
12934 match(Set ex_oop (CreateEx));
12936 size(0);
12937 // use the following format syntax
12938 format %{ "# exception oop is in EAX; no code emitted" %}
12939 ins_encode();
12940 ins_pipe( empty );
12941 %}
12944 // Rethrow exception:
12945 // The exception oop will come in the first argument position.
12946 // Then JUMP (not call) to the rethrow stub code.
12947 instruct RethrowException()
12948 %{
12949 match(Rethrow);
12951 // use the following format syntax
12952 format %{ "JMP rethrow_stub" %}
12953 ins_encode(enc_rethrow);
12954 ins_pipe( pipe_jmp );
12955 %}
12957 // inlined locking and unlocking
12960 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12961 match( Set cr (FastLock object box) );
12962 effect( TEMP tmp, TEMP scr, USE_KILL box );
12963 ins_cost(300);
12964 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12965 ins_encode( Fast_Lock(object,box,tmp,scr) );
12966 ins_pipe( pipe_slow );
12967 %}
12969 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12970 match( Set cr (FastUnlock object box) );
12971 effect( TEMP tmp, USE_KILL box );
12972 ins_cost(300);
12973 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12974 ins_encode( Fast_Unlock(object,box,tmp) );
12975 ins_pipe( pipe_slow );
12976 %}
12980 // ============================================================================
12981 // Safepoint Instruction
12982 instruct safePoint_poll(eFlagsReg cr) %{
12983 match(SafePoint);
12984 effect(KILL cr);
12986 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12987 // On SPARC that might be acceptable as we can generate the address with
12988 // just a sethi, saving an or. By polling at offset 0 we can end up
12989 // putting additional pressure on the index-0 in the D$. Because of
12990 // alignment (just like the situation at hand) the lower indices tend
12991 // to see more traffic. It'd be better to change the polling address
12992 // to offset 0 of the last $line in the polling page.
12994 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12995 ins_cost(125);
12996 size(6) ;
12997 ins_encode( Safepoint_Poll() );
12998 ins_pipe( ialu_reg_mem );
12999 %}
13002 // ============================================================================
13003 // This name is KNOWN by the ADLC and cannot be changed.
13004 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13005 // for this guy.
13006 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13007 match(Set dst (ThreadLocal));
13008 effect(DEF dst, KILL cr);
13010 format %{ "MOV $dst, Thread::current()" %}
13011 ins_encode %{
13012 Register dstReg = as_Register($dst$$reg);
13013 __ get_thread(dstReg);
13014 %}
13015 ins_pipe( ialu_reg_fat );
13016 %}
13020 //----------PEEPHOLE RULES-----------------------------------------------------
13021 // These must follow all instruction definitions as they use the names
13022 // defined in the instructions definitions.
13023 //
13024 // peepmatch ( root_instr_name [preceding_instruction]* );
13025 //
13026 // peepconstraint %{
13027 // (instruction_number.operand_name relational_op instruction_number.operand_name
13028 // [, ...] );
13029 // // instruction numbers are zero-based using left to right order in peepmatch
13030 //
13031 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13032 // // provide an instruction_number.operand_name for each operand that appears
13033 // // in the replacement instruction's match rule
13034 //
13035 // ---------VM FLAGS---------------------------------------------------------
13036 //
13037 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13038 //
13039 // Each peephole rule is given an identifying number starting with zero and
13040 // increasing by one in the order seen by the parser. An individual peephole
13041 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13042 // on the command-line.
13043 //
13044 // ---------CURRENT LIMITATIONS----------------------------------------------
13045 //
13046 // Only match adjacent instructions in same basic block
13047 // Only equality constraints
13048 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13049 // Only one replacement instruction
13050 //
13051 // ---------EXAMPLE----------------------------------------------------------
13052 //
13053 // // pertinent parts of existing instructions in architecture description
13054 // instruct movI(rRegI dst, rRegI src) %{
13055 // match(Set dst (CopyI src));
13056 // %}
13057 //
13058 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13059 // match(Set dst (AddI dst src));
13060 // effect(KILL cr);
13061 // %}
13062 //
13063 // // Change (inc mov) to lea
13064 // peephole %{
13065 // // increment preceeded by register-register move
13066 // peepmatch ( incI_eReg movI );
13067 // // require that the destination register of the increment
13068 // // match the destination register of the move
13069 // peepconstraint ( 0.dst == 1.dst );
13070 // // construct a replacement instruction that sets
13071 // // the destination to ( move's source register + one )
13072 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13073 // %}
13074 //
13075 // Implementation no longer uses movX instructions since
13076 // machine-independent system no longer uses CopyX nodes.
13077 //
13078 // peephole %{
13079 // peepmatch ( incI_eReg movI );
13080 // peepconstraint ( 0.dst == 1.dst );
13081 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13082 // %}
13083 //
13084 // peephole %{
13085 // peepmatch ( decI_eReg movI );
13086 // peepconstraint ( 0.dst == 1.dst );
13087 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13088 // %}
13089 //
13090 // peephole %{
13091 // peepmatch ( addI_eReg_imm movI );
13092 // peepconstraint ( 0.dst == 1.dst );
13093 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13094 // %}
13095 //
13096 // peephole %{
13097 // peepmatch ( addP_eReg_imm movP );
13098 // peepconstraint ( 0.dst == 1.dst );
13099 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13100 // %}
13102 // // Change load of spilled value to only a spill
13103 // instruct storeI(memory mem, rRegI src) %{
13104 // match(Set mem (StoreI mem src));
13105 // %}
13106 //
13107 // instruct loadI(rRegI dst, memory mem) %{
13108 // match(Set dst (LoadI mem));
13109 // %}
13110 //
13111 peephole %{
13112 peepmatch ( loadI storeI );
13113 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13114 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13115 %}
13117 //----------SMARTSPILL RULES---------------------------------------------------
13118 // These must follow all instruction definitions as they use the names
13119 // defined in the instructions definitions.