Wed, 26 Oct 2011 06:08:56 -0700
7097546: Optimize use of CMOVE instructions
Summary: Avoid CMove in a loop if possible. May generate CMove if it could be moved outside a loop.
Reviewed-by: never
1 //
2 // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
247 #define __ _masm.
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
283 static int preserve_SP_size() {
284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
285 }
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
301 static int sizeof_FFree_Float_Stack_All = -1;
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
314 //
315 // Compute padding required for nodes which need alignment
316 //
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
350 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 cbuf.insts()->emit_int8(c);
354 }
356 // EMIT_CC()
357 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
358 unsigned char c = (unsigned char)( f1 | f2 );
359 cbuf.insts()->emit_int8(c);
360 }
362 // EMIT_OPCODE()
363 void emit_opcode(CodeBuffer &cbuf, int code) {
364 cbuf.insts()->emit_int8((unsigned char) code);
365 }
367 // EMIT_OPCODE() w/ relocation information
368 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
369 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
370 emit_opcode(cbuf, code);
371 }
373 // EMIT_D8()
374 void emit_d8(CodeBuffer &cbuf, int d8) {
375 cbuf.insts()->emit_int8((unsigned char) d8);
376 }
378 // EMIT_D16()
379 void emit_d16(CodeBuffer &cbuf, int d16) {
380 cbuf.insts()->emit_int16(d16);
381 }
383 // EMIT_D32()
384 void emit_d32(CodeBuffer &cbuf, int d32) {
385 cbuf.insts()->emit_int32(d32);
386 }
388 // emit 32 bit value and construct relocation entry from relocInfo::relocType
389 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
390 int format) {
391 cbuf.relocate(cbuf.insts_mark(), reloc, format);
392 cbuf.insts()->emit_int32(d32);
393 }
395 // emit 32 bit value and construct relocation entry from RelocationHolder
396 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
397 int format) {
398 #ifdef ASSERT
399 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
400 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
401 }
402 #endif
403 cbuf.relocate(cbuf.insts_mark(), rspec, format);
404 cbuf.insts()->emit_int32(d32);
405 }
407 // Access stack slot for load or store
408 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
409 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
410 if( -128 <= disp && disp <= 127 ) {
411 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
412 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
413 emit_d8 (cbuf, disp); // Displacement // R/M byte
414 } else {
415 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
416 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
417 emit_d32(cbuf, disp); // Displacement // R/M byte
418 }
419 }
421 // eRegI ereg, memory mem) %{ // emit_reg_mem
422 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
423 // There is no index & no scale, use form without SIB byte
424 if ((index == 0x4) &&
425 (scale == 0) && (base != ESP_enc)) {
426 // If no displacement, mode is 0x0; unless base is [EBP]
427 if ( (displace == 0) && (base != EBP_enc) ) {
428 emit_rm(cbuf, 0x0, reg_encoding, base);
429 }
430 else { // If 8-bit displacement, mode 0x1
431 if ((displace >= -128) && (displace <= 127)
432 && !(displace_is_oop) ) {
433 emit_rm(cbuf, 0x1, reg_encoding, base);
434 emit_d8(cbuf, displace);
435 }
436 else { // If 32-bit displacement
437 if (base == -1) { // Special flag for absolute address
438 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
439 // (manual lies; no SIB needed here)
440 if ( displace_is_oop ) {
441 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
442 } else {
443 emit_d32 (cbuf, displace);
444 }
445 }
446 else { // Normal base + offset
447 emit_rm(cbuf, 0x2, reg_encoding, base);
448 if ( displace_is_oop ) {
449 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
450 } else {
451 emit_d32 (cbuf, displace);
452 }
453 }
454 }
455 }
456 }
457 else { // Else, encode with the SIB byte
458 // If no displacement, mode is 0x0; unless base is [EBP]
459 if (displace == 0 && (base != EBP_enc)) { // If no displacement
460 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
461 emit_rm(cbuf, scale, index, base);
462 }
463 else { // If 8-bit displacement, mode 0x1
464 if ((displace >= -128) && (displace <= 127)
465 && !(displace_is_oop) ) {
466 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
467 emit_rm(cbuf, scale, index, base);
468 emit_d8(cbuf, displace);
469 }
470 else { // If 32-bit displacement
471 if (base == 0x04 ) {
472 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
473 emit_rm(cbuf, scale, index, 0x04);
474 } else {
475 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
476 emit_rm(cbuf, scale, index, base);
477 }
478 if ( displace_is_oop ) {
479 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
480 } else {
481 emit_d32 (cbuf, displace);
482 }
483 }
484 }
485 }
486 }
489 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
490 if( dst_encoding == src_encoding ) {
491 // reg-reg copy, use an empty encoding
492 } else {
493 emit_opcode( cbuf, 0x8B );
494 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
495 }
496 }
498 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
499 if( dst_encoding == src_encoding ) {
500 // reg-reg copy, use an empty encoding
501 } else {
502 MacroAssembler _masm(&cbuf);
504 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
505 }
506 }
509 //=============================================================================
510 const bool Matcher::constant_table_absolute_addressing = true;
511 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
513 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
514 // Empty encoding
515 }
517 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
518 return 0;
519 }
521 #ifndef PRODUCT
522 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
523 st->print("# MachConstantBaseNode (empty encoding)");
524 }
525 #endif
528 //=============================================================================
529 #ifndef PRODUCT
530 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
531 Compile* C = ra_->C;
532 if( C->in_24_bit_fp_mode() ) {
533 st->print("FLDCW 24 bit fpu control word");
534 st->print_cr(""); st->print("\t");
535 }
537 int framesize = C->frame_slots() << LogBytesPerInt;
538 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
539 // Remove two words for return addr and rbp,
540 framesize -= 2*wordSize;
542 // Calls to C2R adapters often do not accept exceptional returns.
543 // We require that their callers must bang for them. But be careful, because
544 // some VM calls (such as call site linkage) can use several kilobytes of
545 // stack. But the stack safety zone should account for that.
546 // See bugs 4446381, 4468289, 4497237.
547 if (C->need_stack_bang(framesize)) {
548 st->print_cr("# stack bang"); st->print("\t");
549 }
550 st->print_cr("PUSHL EBP"); st->print("\t");
552 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
553 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
554 st->print_cr(""); st->print("\t");
555 framesize -= wordSize;
556 }
558 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
559 if (framesize) {
560 st->print("SUB ESP,%d\t# Create frame",framesize);
561 }
562 } else {
563 st->print("SUB ESP,%d\t# Create frame",framesize);
564 }
565 }
566 #endif
569 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
570 Compile* C = ra_->C;
572 if (UseSSE >= 2 && VerifyFPU) {
573 MacroAssembler masm(&cbuf);
574 masm.verify_FPU(0, "FPU stack must be clean on entry");
575 }
577 // WARNING: Initial instruction MUST be 5 bytes or longer so that
578 // NativeJump::patch_verified_entry will be able to patch out the entry
579 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
580 // depth is ok at 5 bytes, the frame allocation can be either 3 or
581 // 6 bytes. So if we don't do the fldcw or the push then we must
582 // use the 6 byte frame allocation even if we have no frame. :-(
583 // If method sets FPU control word do it now
584 if( C->in_24_bit_fp_mode() ) {
585 MacroAssembler masm(&cbuf);
586 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
587 }
589 int framesize = C->frame_slots() << LogBytesPerInt;
590 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
591 // Remove two words for return addr and rbp,
592 framesize -= 2*wordSize;
594 // Calls to C2R adapters often do not accept exceptional returns.
595 // We require that their callers must bang for them. But be careful, because
596 // some VM calls (such as call site linkage) can use several kilobytes of
597 // stack. But the stack safety zone should account for that.
598 // See bugs 4446381, 4468289, 4497237.
599 if (C->need_stack_bang(framesize)) {
600 MacroAssembler masm(&cbuf);
601 masm.generate_stack_overflow_check(framesize);
602 }
604 // We always push rbp, so that on return to interpreter rbp, will be
605 // restored correctly and we can correct the stack.
606 emit_opcode(cbuf, 0x50 | EBP_enc);
608 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
609 emit_opcode(cbuf, 0x68); // push 0xbadb100d
610 emit_d32(cbuf, 0xbadb100d);
611 framesize -= wordSize;
612 }
614 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
615 if (framesize) {
616 emit_opcode(cbuf, 0x83); // sub SP,#framesize
617 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
618 emit_d8(cbuf, framesize);
619 }
620 } else {
621 emit_opcode(cbuf, 0x81); // sub SP,#framesize
622 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
623 emit_d32(cbuf, framesize);
624 }
625 C->set_frame_complete(cbuf.insts_size());
627 #ifdef ASSERT
628 if (VerifyStackAtCalls) {
629 Label L;
630 MacroAssembler masm(&cbuf);
631 masm.push(rax);
632 masm.mov(rax, rsp);
633 masm.andptr(rax, StackAlignmentInBytes-1);
634 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
635 masm.pop(rax);
636 masm.jcc(Assembler::equal, L);
637 masm.stop("Stack is not properly aligned!");
638 masm.bind(L);
639 }
640 #endif
642 }
644 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
645 return MachNode::size(ra_); // too many variables; just compute it the hard way
646 }
648 int MachPrologNode::reloc() const {
649 return 0; // a large enough number
650 }
652 //=============================================================================
653 #ifndef PRODUCT
654 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
655 Compile *C = ra_->C;
656 int framesize = C->frame_slots() << LogBytesPerInt;
657 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
658 // Remove two words for return addr and rbp,
659 framesize -= 2*wordSize;
661 if( C->in_24_bit_fp_mode() ) {
662 st->print("FLDCW standard control word");
663 st->cr(); st->print("\t");
664 }
665 if( framesize ) {
666 st->print("ADD ESP,%d\t# Destroy frame",framesize);
667 st->cr(); st->print("\t");
668 }
669 st->print_cr("POPL EBP"); st->print("\t");
670 if( do_polling() && C->is_method_compilation() ) {
671 st->print("TEST PollPage,EAX\t! Poll Safepoint");
672 st->cr(); st->print("\t");
673 }
674 }
675 #endif
677 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
678 Compile *C = ra_->C;
680 // If method set FPU control word, restore to standard control word
681 if( C->in_24_bit_fp_mode() ) {
682 MacroAssembler masm(&cbuf);
683 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
684 }
686 int framesize = C->frame_slots() << LogBytesPerInt;
687 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
688 // Remove two words for return addr and rbp,
689 framesize -= 2*wordSize;
691 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
693 if( framesize >= 128 ) {
694 emit_opcode(cbuf, 0x81); // add SP, #framesize
695 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
696 emit_d32(cbuf, framesize);
697 }
698 else if( framesize ) {
699 emit_opcode(cbuf, 0x83); // add SP, #framesize
700 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
701 emit_d8(cbuf, framesize);
702 }
704 emit_opcode(cbuf, 0x58 | EBP_enc);
706 if( do_polling() && C->is_method_compilation() ) {
707 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
708 emit_opcode(cbuf,0x85);
709 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
710 emit_d32(cbuf, (intptr_t)os::get_polling_page());
711 }
712 }
714 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
715 Compile *C = ra_->C;
716 // If method set FPU control word, restore to standard control word
717 int size = C->in_24_bit_fp_mode() ? 6 : 0;
718 if( do_polling() && C->is_method_compilation() ) size += 6;
720 int framesize = C->frame_slots() << LogBytesPerInt;
721 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
722 // Remove two words for return addr and rbp,
723 framesize -= 2*wordSize;
725 size++; // popl rbp,
727 if( framesize >= 128 ) {
728 size += 6;
729 } else {
730 size += framesize ? 3 : 0;
731 }
732 return size;
733 }
735 int MachEpilogNode::reloc() const {
736 return 0; // a large enough number
737 }
739 const Pipeline * MachEpilogNode::pipeline() const {
740 return MachNode::pipeline_class();
741 }
743 int MachEpilogNode::safepoint_offset() const { return 0; }
745 //=============================================================================
747 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
748 static enum RC rc_class( OptoReg::Name reg ) {
750 if( !OptoReg::is_valid(reg) ) return rc_bad;
751 if (OptoReg::is_stack(reg)) return rc_stack;
753 VMReg r = OptoReg::as_VMReg(reg);
754 if (r->is_Register()) return rc_int;
755 if (r->is_FloatRegister()) {
756 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
757 return rc_float;
758 }
759 assert(r->is_XMMRegister(), "must be");
760 return rc_xmm;
761 }
763 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
764 int opcode, const char *op_str, int size, outputStream* st ) {
765 if( cbuf ) {
766 emit_opcode (*cbuf, opcode );
767 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
768 #ifndef PRODUCT
769 } else if( !do_size ) {
770 if( size != 0 ) st->print("\n\t");
771 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
772 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
773 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
774 } else { // FLD, FST, PUSH, POP
775 st->print("%s [ESP + #%d]",op_str,offset);
776 }
777 #endif
778 }
779 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
780 return size+3+offset_size;
781 }
783 // Helper for XMM registers. Extra opcode bits, limited syntax.
784 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
785 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
786 if( cbuf ) {
787 if( reg_lo+1 == reg_hi ) { // double move?
788 if( is_load && !UseXmmLoadAndClearUpper )
789 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
790 else
791 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
792 } else {
793 emit_opcode(*cbuf, 0xF3 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
797 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
798 else
799 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
800 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
801 #ifndef PRODUCT
802 } else if( !do_size ) {
803 if( size != 0 ) st->print("\n\t");
804 if( reg_lo+1 == reg_hi ) { // double move?
805 if( is_load ) st->print("%s %s,[ESP + #%d]",
806 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
807 Matcher::regName[reg_lo], offset);
808 else st->print("MOVSD [ESP + #%d],%s",
809 offset, Matcher::regName[reg_lo]);
810 } else {
811 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
812 Matcher::regName[reg_lo], offset);
813 else st->print("MOVSS [ESP + #%d],%s",
814 offset, Matcher::regName[reg_lo]);
815 }
816 #endif
817 }
818 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
819 return size+5+offset_size;
820 }
823 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
826 if( cbuf ) {
827 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
828 emit_opcode(*cbuf, 0x66 );
829 }
830 emit_opcode(*cbuf, 0x0F );
831 emit_opcode(*cbuf, 0x28 );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
837 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
838 } else {
839 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
840 }
841 #endif
842 }
843 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
844 } else {
845 if( cbuf ) {
846 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
847 emit_opcode(*cbuf, 0x0F );
848 emit_opcode(*cbuf, 0x10 );
849 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
850 #ifndef PRODUCT
851 } else if( !do_size ) {
852 if( size != 0 ) st->print("\n\t");
853 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
854 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
855 } else {
856 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
857 }
858 #endif
859 }
860 return size+4;
861 }
862 }
864 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
865 int src_hi, int dst_hi, int size, outputStream* st ) {
866 // 32-bit
867 if (cbuf) {
868 emit_opcode(*cbuf, 0x66);
869 emit_opcode(*cbuf, 0x0F);
870 emit_opcode(*cbuf, 0x6E);
871 emit_rm(*cbuf, 0x3, Matcher::_regEncode[dst_lo] & 7, Matcher::_regEncode[src_lo] & 7);
872 #ifndef PRODUCT
873 } else if (!do_size) {
874 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
875 #endif
876 }
877 return 4;
878 }
881 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
882 int src_hi, int dst_hi, int size, outputStream* st ) {
883 // 32-bit
884 if (cbuf) {
885 emit_opcode(*cbuf, 0x66);
886 emit_opcode(*cbuf, 0x0F);
887 emit_opcode(*cbuf, 0x7E);
888 emit_rm(*cbuf, 0x3, Matcher::_regEncode[src_lo] & 7, Matcher::_regEncode[dst_lo] & 7);
889 #ifndef PRODUCT
890 } else if (!do_size) {
891 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
892 #endif
893 }
894 return 4;
895 }
897 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
898 if( cbuf ) {
899 emit_opcode(*cbuf, 0x8B );
900 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
901 #ifndef PRODUCT
902 } else if( !do_size ) {
903 if( size != 0 ) st->print("\n\t");
904 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
905 #endif
906 }
907 return size+2;
908 }
910 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
911 int offset, int size, outputStream* st ) {
912 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
913 if( cbuf ) {
914 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
915 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
916 #ifndef PRODUCT
917 } else if( !do_size ) {
918 if( size != 0 ) st->print("\n\t");
919 st->print("FLD %s",Matcher::regName[src_lo]);
920 #endif
921 }
922 size += 2;
923 }
925 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
926 const char *op_str;
927 int op;
928 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
929 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
930 op = 0xDD;
931 } else { // 32-bit store
932 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
933 op = 0xD9;
934 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
935 }
937 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
938 }
940 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
941 // Get registers to move
942 OptoReg::Name src_second = ra_->get_reg_second(in(1));
943 OptoReg::Name src_first = ra_->get_reg_first(in(1));
944 OptoReg::Name dst_second = ra_->get_reg_second(this );
945 OptoReg::Name dst_first = ra_->get_reg_first(this );
947 enum RC src_second_rc = rc_class(src_second);
948 enum RC src_first_rc = rc_class(src_first);
949 enum RC dst_second_rc = rc_class(dst_second);
950 enum RC dst_first_rc = rc_class(dst_first);
952 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
954 // Generate spill code!
955 int size = 0;
957 if( src_first == dst_first && src_second == dst_second )
958 return size; // Self copy, no move
960 // --------------------------------------
961 // Check for mem-mem move. push/pop to move.
962 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
963 if( src_second == dst_first ) { // overlapping stack copy ranges
964 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
965 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
966 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
967 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
968 }
969 // move low bits
970 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
971 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
972 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
973 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
974 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
975 }
976 return size;
977 }
979 // --------------------------------------
980 // Check for integer reg-reg copy
981 if( src_first_rc == rc_int && dst_first_rc == rc_int )
982 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
984 // Check for integer store
985 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
986 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
988 // Check for integer load
989 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
990 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
992 // Check for integer reg-xmm reg copy
993 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
994 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
995 "no 64 bit integer-float reg moves" );
996 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
997 }
998 // --------------------------------------
999 // Check for float reg-reg copy
1000 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1001 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1002 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1003 if( cbuf ) {
1005 // Note the mucking with the register encode to compensate for the 0/1
1006 // indexing issue mentioned in a comment in the reg_def sections
1007 // for FPR registers many lines above here.
1009 if( src_first != FPR1L_num ) {
1010 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1011 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1012 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1013 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1014 } else {
1015 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1016 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1017 }
1018 #ifndef PRODUCT
1019 } else if( !do_size ) {
1020 if( size != 0 ) st->print("\n\t");
1021 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1022 else st->print( "FST %s", Matcher::regName[dst_first]);
1023 #endif
1024 }
1025 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1026 }
1028 // Check for float store
1029 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1030 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1031 }
1033 // Check for float load
1034 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1035 int offset = ra_->reg2offset(src_first);
1036 const char *op_str;
1037 int op;
1038 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1039 op_str = "FLD_D";
1040 op = 0xDD;
1041 } else { // 32-bit load
1042 op_str = "FLD_S";
1043 op = 0xD9;
1044 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1045 }
1046 if( cbuf ) {
1047 emit_opcode (*cbuf, op );
1048 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1049 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1050 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1051 #ifndef PRODUCT
1052 } else if( !do_size ) {
1053 if( size != 0 ) st->print("\n\t");
1054 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1055 #endif
1056 }
1057 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1058 return size + 3+offset_size+2;
1059 }
1061 // Check for xmm reg-reg copy
1062 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1063 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1064 (src_first+1 == src_second && dst_first+1 == dst_second),
1065 "no non-adjacent float-moves" );
1066 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1067 }
1069 // Check for xmm reg-integer reg copy
1070 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1071 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1072 "no 64 bit float-integer reg moves" );
1073 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1074 }
1076 // Check for xmm store
1077 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1078 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1079 }
1081 // Check for float xmm load
1082 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1083 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1084 }
1086 // Copy from float reg to xmm reg
1087 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1088 // copy to the top of stack from floating point reg
1089 // and use LEA to preserve flags
1090 if( cbuf ) {
1091 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1092 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1093 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1094 emit_d8(*cbuf,0xF8);
1095 #ifndef PRODUCT
1096 } else if( !do_size ) {
1097 if( size != 0 ) st->print("\n\t");
1098 st->print("LEA ESP,[ESP-8]");
1099 #endif
1100 }
1101 size += 4;
1103 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1105 // Copy from the temp memory to the xmm reg.
1106 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1108 if( cbuf ) {
1109 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1110 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1111 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1112 emit_d8(*cbuf,0x08);
1113 #ifndef PRODUCT
1114 } else if( !do_size ) {
1115 if( size != 0 ) st->print("\n\t");
1116 st->print("LEA ESP,[ESP+8]");
1117 #endif
1118 }
1119 size += 4;
1120 return size;
1121 }
1123 assert( size > 0, "missed a case" );
1125 // --------------------------------------------------------------------
1126 // Check for second bits still needing moving.
1127 if( src_second == dst_second )
1128 return size; // Self copy; no move
1129 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1131 // Check for second word int-int move
1132 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1133 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1135 // Check for second word integer store
1136 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1137 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1139 // Check for second word integer load
1140 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1141 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1144 Unimplemented();
1145 }
1147 #ifndef PRODUCT
1148 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1149 implementation( NULL, ra_, false, st );
1150 }
1151 #endif
1153 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1154 implementation( &cbuf, ra_, false, NULL );
1155 }
1157 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1158 return implementation( NULL, ra_, true, NULL );
1159 }
1161 //=============================================================================
1162 #ifndef PRODUCT
1163 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1164 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1165 }
1166 #endif
1168 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1169 MacroAssembler _masm(&cbuf);
1170 __ nop(_count);
1171 }
1173 uint MachNopNode::size(PhaseRegAlloc *) const {
1174 return _count;
1175 }
1178 //=============================================================================
1179 #ifndef PRODUCT
1180 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1181 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1182 int reg = ra_->get_reg_first(this);
1183 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1184 }
1185 #endif
1187 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1188 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1189 int reg = ra_->get_encode(this);
1190 if( offset >= 128 ) {
1191 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1192 emit_rm(cbuf, 0x2, reg, 0x04);
1193 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1194 emit_d32(cbuf, offset);
1195 }
1196 else {
1197 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1198 emit_rm(cbuf, 0x1, reg, 0x04);
1199 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1200 emit_d8(cbuf, offset);
1201 }
1202 }
1204 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1205 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1206 if( offset >= 128 ) {
1207 return 7;
1208 }
1209 else {
1210 return 4;
1211 }
1212 }
1214 //=============================================================================
1216 // emit call stub, compiled java to interpreter
1217 void emit_java_to_interp(CodeBuffer &cbuf ) {
1218 // Stub is fixed up when the corresponding call is converted from calling
1219 // compiled code to calling interpreted code.
1220 // mov rbx,0
1221 // jmp -1
1223 address mark = cbuf.insts_mark(); // get mark within main instrs section
1225 // Note that the code buffer's insts_mark is always relative to insts.
1226 // That's why we must use the macroassembler to generate a stub.
1227 MacroAssembler _masm(&cbuf);
1229 address base =
1230 __ start_a_stub(Compile::MAX_stubs_size);
1231 if (base == NULL) return; // CodeBuffer::expand failed
1232 // static stub relocation stores the instruction address of the call
1233 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1234 // static stub relocation also tags the methodOop in the code-stream.
1235 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1236 // This is recognized as unresolved by relocs/nativeInst/ic code
1237 __ jump(RuntimeAddress(__ pc()));
1239 __ end_a_stub();
1240 // Update current stubs pointer and restore insts_end.
1241 }
1242 // size of call stub, compiled java to interpretor
1243 uint size_java_to_interp() {
1244 return 10; // movl; jmp
1245 }
1246 // relocation entries for call stub, compiled java to interpretor
1247 uint reloc_java_to_interp() {
1248 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1249 }
1251 //=============================================================================
1252 #ifndef PRODUCT
1253 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1254 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1255 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1256 st->print_cr("\tNOP");
1257 st->print_cr("\tNOP");
1258 if( !OptoBreakpoint )
1259 st->print_cr("\tNOP");
1260 }
1261 #endif
1263 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1264 MacroAssembler masm(&cbuf);
1265 #ifdef ASSERT
1266 uint insts_size = cbuf.insts_size();
1267 #endif
1268 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1269 masm.jump_cc(Assembler::notEqual,
1270 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1271 /* WARNING these NOPs are critical so that verified entry point is properly
1272 aligned for patching by NativeJump::patch_verified_entry() */
1273 int nops_cnt = 2;
1274 if( !OptoBreakpoint ) // Leave space for int3
1275 nops_cnt += 1;
1276 masm.nop(nops_cnt);
1278 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1279 }
1281 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1282 return OptoBreakpoint ? 11 : 12;
1283 }
1286 //=============================================================================
1287 uint size_exception_handler() {
1288 // NativeCall instruction size is the same as NativeJump.
1289 // exception handler starts out as jump and can be patched to
1290 // a call be deoptimization. (4932387)
1291 // Note that this value is also credited (in output.cpp) to
1292 // the size of the code section.
1293 return NativeJump::instruction_size;
1294 }
1296 // Emit exception handler code. Stuff framesize into a register
1297 // and call a VM stub routine.
1298 int emit_exception_handler(CodeBuffer& cbuf) {
1300 // Note that the code buffer's insts_mark is always relative to insts.
1301 // That's why we must use the macroassembler to generate a handler.
1302 MacroAssembler _masm(&cbuf);
1303 address base =
1304 __ start_a_stub(size_exception_handler());
1305 if (base == NULL) return 0; // CodeBuffer::expand failed
1306 int offset = __ offset();
1307 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1308 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1309 __ end_a_stub();
1310 return offset;
1311 }
1313 uint size_deopt_handler() {
1314 // NativeCall instruction size is the same as NativeJump.
1315 // exception handler starts out as jump and can be patched to
1316 // a call be deoptimization. (4932387)
1317 // Note that this value is also credited (in output.cpp) to
1318 // the size of the code section.
1319 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1320 }
1322 // Emit deopt handler code.
1323 int emit_deopt_handler(CodeBuffer& cbuf) {
1325 // Note that the code buffer's insts_mark is always relative to insts.
1326 // That's why we must use the macroassembler to generate a handler.
1327 MacroAssembler _masm(&cbuf);
1328 address base =
1329 __ start_a_stub(size_exception_handler());
1330 if (base == NULL) return 0; // CodeBuffer::expand failed
1331 int offset = __ offset();
1332 InternalAddress here(__ pc());
1333 __ pushptr(here.addr());
1335 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1336 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1337 __ end_a_stub();
1338 return offset;
1339 }
1342 const bool Matcher::match_rule_supported(int opcode) {
1343 if (!has_match_rule(opcode))
1344 return false;
1346 return true; // Per default match rules are supported.
1347 }
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350 return regnum - 32; // The FP registers are in the second chunk
1351 }
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355 return true;
1356 }
1358 // Vector width in bytes
1359 const uint Matcher::vector_width_in_bytes(void) {
1360 return UseSSE >= 2 ? 8 : 0;
1361 }
1363 // Vector ideal reg
1364 const uint Matcher::vector_ideal_reg(void) {
1365 return Op_RegD;
1366 }
1368 // Is this branch offset short enough that a short branch can be used?
1369 //
1370 // NOTE: If the platform does not provide any short branch variants, then
1371 // this method should return false for offset 0.
1372 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1373 // The passed offset is relative to address of the branch.
1374 // On 86 a branch displacement is calculated relative to address
1375 // of a next instruction.
1376 offset -= br_size;
1378 // the short version of jmpConUCF2 contains multiple branches,
1379 // making the reach slightly less
1380 if (rule == jmpConUCF2_rule)
1381 return (-126 <= offset && offset <= 125);
1382 return (-128 <= offset && offset <= 127);
1383 }
1385 const bool Matcher::isSimpleConstant64(jlong value) {
1386 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1387 return false;
1388 }
1390 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1391 const bool Matcher::init_array_count_is_in_bytes = false;
1393 // Threshold size for cleararray.
1394 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1396 // Needs 2 CMOV's for longs.
1397 const int Matcher::long_cmove_cost() { return 1; }
1399 // No CMOVF/CMOVD with SSE/SSE2
1400 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1402 // Should the Matcher clone shifts on addressing modes, expecting them to
1403 // be subsumed into complex addressing expressions or compute them into
1404 // registers? True for Intel but false for most RISCs
1405 const bool Matcher::clone_shift_expressions = true;
1407 // Do we need to mask the count passed to shift instructions or does
1408 // the cpu only look at the lower 5/6 bits anyway?
1409 const bool Matcher::need_masked_shift_count = false;
1411 bool Matcher::narrow_oop_use_complex_address() {
1412 ShouldNotCallThis();
1413 return true;
1414 }
1417 // Is it better to copy float constants, or load them directly from memory?
1418 // Intel can load a float constant from a direct address, requiring no
1419 // extra registers. Most RISCs will have to materialize an address into a
1420 // register first, so they would do better to copy the constant from stack.
1421 const bool Matcher::rematerialize_float_constants = true;
1423 // If CPU can load and store mis-aligned doubles directly then no fixup is
1424 // needed. Else we split the double into 2 integer pieces and move it
1425 // piece-by-piece. Only happens when passing doubles into C code as the
1426 // Java calling convention forces doubles to be aligned.
1427 const bool Matcher::misaligned_doubles_ok = true;
1430 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1431 // Get the memory operand from the node
1432 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1433 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1434 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1435 uint opcnt = 1; // First operand
1436 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1437 while( idx >= skipped+num_edges ) {
1438 skipped += num_edges;
1439 opcnt++; // Bump operand count
1440 assert( opcnt < numopnds, "Accessing non-existent operand" );
1441 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1442 }
1444 MachOper *memory = node->_opnds[opcnt];
1445 MachOper *new_memory = NULL;
1446 switch (memory->opcode()) {
1447 case DIRECT:
1448 case INDOFFSET32X:
1449 // No transformation necessary.
1450 return;
1451 case INDIRECT:
1452 new_memory = new (C) indirect_win95_safeOper( );
1453 break;
1454 case INDOFFSET8:
1455 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1456 break;
1457 case INDOFFSET32:
1458 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1459 break;
1460 case INDINDEXOFFSET:
1461 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1462 break;
1463 case INDINDEXSCALE:
1464 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1465 break;
1466 case INDINDEXSCALEOFFSET:
1467 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1468 break;
1469 case LOAD_LONG_INDIRECT:
1470 case LOAD_LONG_INDOFFSET32:
1471 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1472 return;
1473 default:
1474 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1475 return;
1476 }
1477 node->_opnds[opcnt] = new_memory;
1478 }
1480 // Advertise here if the CPU requires explicit rounding operations
1481 // to implement the UseStrictFP mode.
1482 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1484 // Are floats conerted to double when stored to stack during deoptimization?
1485 // On x32 it is stored with convertion only when FPU is used for floats.
1486 bool Matcher::float_in_double() { return (UseSSE == 0); }
1488 // Do ints take an entire long register or just half?
1489 const bool Matcher::int_in_long = false;
1491 // Return whether or not this register is ever used as an argument. This
1492 // function is used on startup to build the trampoline stubs in generateOptoStub.
1493 // Registers not mentioned will be killed by the VM call in the trampoline, and
1494 // arguments in those registers not be available to the callee.
1495 bool Matcher::can_be_java_arg( int reg ) {
1496 if( reg == ECX_num || reg == EDX_num ) return true;
1497 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1498 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1499 return false;
1500 }
1502 bool Matcher::is_spillable_arg( int reg ) {
1503 return can_be_java_arg(reg);
1504 }
1506 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1507 // Use hardware integer DIV instruction when
1508 // it is faster than a code which use multiply.
1509 // Only when constant divisor fits into 32 bit
1510 // (min_jint is excluded to get only correct
1511 // positive 32 bit values from negative).
1512 return VM_Version::has_fast_idiv() &&
1513 (divisor == (int)divisor && divisor != min_jint);
1514 }
1516 // Register for DIVI projection of divmodI
1517 RegMask Matcher::divI_proj_mask() {
1518 return EAX_REG_mask;
1519 }
1521 // Register for MODI projection of divmodI
1522 RegMask Matcher::modI_proj_mask() {
1523 return EDX_REG_mask;
1524 }
1526 // Register for DIVL projection of divmodL
1527 RegMask Matcher::divL_proj_mask() {
1528 ShouldNotReachHere();
1529 return RegMask();
1530 }
1532 // Register for MODL projection of divmodL
1533 RegMask Matcher::modL_proj_mask() {
1534 ShouldNotReachHere();
1535 return RegMask();
1536 }
1538 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1539 return EBP_REG_mask;
1540 }
1542 // Returns true if the high 32 bits of the value is known to be zero.
1543 bool is_operand_hi32_zero(Node* n) {
1544 int opc = n->Opcode();
1545 if (opc == Op_LoadUI2L) {
1546 return true;
1547 }
1548 if (opc == Op_AndL) {
1549 Node* o2 = n->in(2);
1550 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1551 return true;
1552 }
1553 }
1554 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1555 return true;
1556 }
1557 return false;
1558 }
1560 %}
1562 //----------ENCODING BLOCK-----------------------------------------------------
1563 // This block specifies the encoding classes used by the compiler to output
1564 // byte streams. Encoding classes generate functions which are called by
1565 // Machine Instruction Nodes in order to generate the bit encoding of the
1566 // instruction. Operands specify their base encoding interface with the
1567 // interface keyword. There are currently supported four interfaces,
1568 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1569 // operand to generate a function which returns its register number when
1570 // queried. CONST_INTER causes an operand to generate a function which
1571 // returns the value of the constant when queried. MEMORY_INTER causes an
1572 // operand to generate four functions which return the Base Register, the
1573 // Index Register, the Scale Value, and the Offset Value of the operand when
1574 // queried. COND_INTER causes an operand to generate six functions which
1575 // return the encoding code (ie - encoding bits for the instruction)
1576 // associated with each basic boolean condition for a conditional instruction.
1577 // Instructions specify two basic values for encoding. They use the
1578 // ins_encode keyword to specify their encoding class (which must be one of
1579 // the class names specified in the encoding block), and they use the
1580 // opcode keyword to specify, in order, their primary, secondary, and
1581 // tertiary opcode. Only the opcode sections which a particular instruction
1582 // needs for encoding need to be specified.
1583 encode %{
1584 // Build emit functions for each basic byte or larger field in the intel
1585 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1586 // code in the enc_class source block. Emit functions will live in the
1587 // main source block for now. In future, we can generalize this by
1588 // adding a syntax that specifies the sizes of fields in an order,
1589 // so that the adlc can build the emit functions automagically
1591 // Emit primary opcode
1592 enc_class OpcP %{
1593 emit_opcode(cbuf, $primary);
1594 %}
1596 // Emit secondary opcode
1597 enc_class OpcS %{
1598 emit_opcode(cbuf, $secondary);
1599 %}
1601 // Emit opcode directly
1602 enc_class Opcode(immI d8) %{
1603 emit_opcode(cbuf, $d8$$constant);
1604 %}
1606 enc_class SizePrefix %{
1607 emit_opcode(cbuf,0x66);
1608 %}
1610 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1611 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1612 %}
1614 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1615 emit_opcode(cbuf,$opcode$$constant);
1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1617 %}
1619 enc_class mov_r32_imm0( eRegI dst ) %{
1620 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1621 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1622 %}
1624 enc_class cdq_enc %{
1625 // Full implementation of Java idiv and irem; checks for
1626 // special case as described in JVM spec., p.243 & p.271.
1627 //
1628 // normal case special case
1629 //
1630 // input : rax,: dividend min_int
1631 // reg: divisor -1
1632 //
1633 // output: rax,: quotient (= rax, idiv reg) min_int
1634 // rdx: remainder (= rax, irem reg) 0
1635 //
1636 // Code sequnce:
1637 //
1638 // 81 F8 00 00 00 80 cmp rax,80000000h
1639 // 0F 85 0B 00 00 00 jne normal_case
1640 // 33 D2 xor rdx,edx
1641 // 83 F9 FF cmp rcx,0FFh
1642 // 0F 84 03 00 00 00 je done
1643 // normal_case:
1644 // 99 cdq
1645 // F7 F9 idiv rax,ecx
1646 // done:
1647 //
1648 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1649 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1650 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1651 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1652 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1653 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1654 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1655 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1657 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1659 // normal_case:
1660 emit_opcode(cbuf,0x99); // cdq
1661 // idiv (note: must be emitted by the user of this rule)
1662 // normal:
1663 %}
1665 // Dense encoding for older common ops
1666 enc_class Opc_plus(immI opcode, eRegI reg) %{
1667 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1668 %}
1671 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1672 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1673 // Check for 8-bit immediate, and set sign extend bit in opcode
1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1675 emit_opcode(cbuf, $primary | 0x02);
1676 }
1677 else { // If 32-bit immediate
1678 emit_opcode(cbuf, $primary);
1679 }
1680 %}
1682 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1683 // Emit primary opcode and set sign-extend bit
1684 // Check for 8-bit immediate, and set sign extend bit in opcode
1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1686 emit_opcode(cbuf, $primary | 0x02); }
1687 else { // If 32-bit immediate
1688 emit_opcode(cbuf, $primary);
1689 }
1690 // Emit r/m byte with secondary opcode, after primary opcode.
1691 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1692 %}
1694 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1695 // Check for 8-bit immediate, and set sign extend bit in opcode
1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1697 $$$emit8$imm$$constant;
1698 }
1699 else { // If 32-bit immediate
1700 // Output immediate
1701 $$$emit32$imm$$constant;
1702 }
1703 %}
1705 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1706 // Emit primary opcode and set sign-extend bit
1707 // Check for 8-bit immediate, and set sign extend bit in opcode
1708 int con = (int)$imm$$constant; // Throw away top bits
1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1710 // Emit r/m byte with secondary opcode, after primary opcode.
1711 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1713 else emit_d32(cbuf,con);
1714 %}
1716 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1717 // Emit primary opcode and set sign-extend bit
1718 // Check for 8-bit immediate, and set sign extend bit in opcode
1719 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1721 // Emit r/m byte with tertiary opcode, after primary opcode.
1722 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1724 else emit_d32(cbuf,con);
1725 %}
1727 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1728 emit_cc(cbuf, $secondary, $dst$$reg );
1729 %}
1731 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1732 int destlo = $dst$$reg;
1733 int desthi = HIGH_FROM_LOW(destlo);
1734 // bswap lo
1735 emit_opcode(cbuf, 0x0F);
1736 emit_cc(cbuf, 0xC8, destlo);
1737 // bswap hi
1738 emit_opcode(cbuf, 0x0F);
1739 emit_cc(cbuf, 0xC8, desthi);
1740 // xchg lo and hi
1741 emit_opcode(cbuf, 0x87);
1742 emit_rm(cbuf, 0x3, destlo, desthi);
1743 %}
1745 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1746 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1747 %}
1749 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1750 $$$emit8$primary;
1751 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1752 %}
1754 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1755 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1756 emit_d8(cbuf, op >> 8 );
1757 emit_d8(cbuf, op & 255);
1758 %}
1760 // emulate a CMOV with a conditional branch around a MOV
1761 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1762 // Invert sense of branch from sense of CMOV
1763 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1764 emit_d8( cbuf, $brOffs$$constant );
1765 %}
1767 enc_class enc_PartialSubtypeCheck( ) %{
1768 Register Redi = as_Register(EDI_enc); // result register
1769 Register Reax = as_Register(EAX_enc); // super class
1770 Register Recx = as_Register(ECX_enc); // killed
1771 Register Resi = as_Register(ESI_enc); // sub class
1772 Label miss;
1774 MacroAssembler _masm(&cbuf);
1775 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1776 NULL, &miss,
1777 /*set_cond_codes:*/ true);
1778 if ($primary) {
1779 __ xorptr(Redi, Redi);
1780 }
1781 __ bind(miss);
1782 %}
1784 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1785 MacroAssembler masm(&cbuf);
1786 int start = masm.offset();
1787 if (UseSSE >= 2) {
1788 if (VerifyFPU) {
1789 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1790 }
1791 } else {
1792 // External c_calling_convention expects the FPU stack to be 'clean'.
1793 // Compiled code leaves it dirty. Do cleanup now.
1794 masm.empty_FPU_stack();
1795 }
1796 if (sizeof_FFree_Float_Stack_All == -1) {
1797 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1798 } else {
1799 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1800 }
1801 %}
1803 enc_class Verify_FPU_For_Leaf %{
1804 if( VerifyFPU ) {
1805 MacroAssembler masm(&cbuf);
1806 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1807 }
1808 %}
1810 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1811 // This is the instruction starting address for relocation info.
1812 cbuf.set_insts_mark();
1813 $$$emit8$primary;
1814 // CALL directly to the runtime
1815 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1816 runtime_call_Relocation::spec(), RELOC_IMM32 );
1818 if (UseSSE >= 2) {
1819 MacroAssembler _masm(&cbuf);
1820 BasicType rt = tf()->return_type();
1822 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1823 // A C runtime call where the return value is unused. In SSE2+
1824 // mode the result needs to be removed from the FPU stack. It's
1825 // likely that this function call could be removed by the
1826 // optimizer if the C function is a pure function.
1827 __ ffree(0);
1828 } else if (rt == T_FLOAT) {
1829 __ lea(rsp, Address(rsp, -4));
1830 __ fstp_s(Address(rsp, 0));
1831 __ movflt(xmm0, Address(rsp, 0));
1832 __ lea(rsp, Address(rsp, 4));
1833 } else if (rt == T_DOUBLE) {
1834 __ lea(rsp, Address(rsp, -8));
1835 __ fstp_d(Address(rsp, 0));
1836 __ movdbl(xmm0, Address(rsp, 0));
1837 __ lea(rsp, Address(rsp, 8));
1838 }
1839 }
1840 %}
1843 enc_class pre_call_FPU %{
1844 // If method sets FPU control word restore it here
1845 debug_only(int off0 = cbuf.insts_size());
1846 if( Compile::current()->in_24_bit_fp_mode() ) {
1847 MacroAssembler masm(&cbuf);
1848 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1849 }
1850 debug_only(int off1 = cbuf.insts_size());
1851 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1852 %}
1854 enc_class post_call_FPU %{
1855 // If method sets FPU control word do it here also
1856 if( Compile::current()->in_24_bit_fp_mode() ) {
1857 MacroAssembler masm(&cbuf);
1858 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1859 }
1860 %}
1862 enc_class preserve_SP %{
1863 debug_only(int off0 = cbuf.insts_size());
1864 MacroAssembler _masm(&cbuf);
1865 // RBP is preserved across all calls, even compiled calls.
1866 // Use it to preserve RSP in places where the callee might change the SP.
1867 __ movptr(rbp_mh_SP_save, rsp);
1868 debug_only(int off1 = cbuf.insts_size());
1869 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1870 %}
1872 enc_class restore_SP %{
1873 MacroAssembler _masm(&cbuf);
1874 __ movptr(rsp, rbp_mh_SP_save);
1875 %}
1877 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1878 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1879 // who we intended to call.
1880 cbuf.set_insts_mark();
1881 $$$emit8$primary;
1882 if ( !_method ) {
1883 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1884 runtime_call_Relocation::spec(), RELOC_IMM32 );
1885 } else if(_optimized_virtual) {
1886 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1887 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1888 } else {
1889 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1890 static_call_Relocation::spec(), RELOC_IMM32 );
1891 }
1892 if( _method ) { // Emit stub for static call
1893 emit_java_to_interp(cbuf);
1894 }
1895 %}
1897 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1898 // !!!!!
1899 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1900 // emit_call_dynamic_prologue( cbuf );
1901 cbuf.set_insts_mark();
1902 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1903 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1904 address virtual_call_oop_addr = cbuf.insts_mark();
1905 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1906 // who we intended to call.
1907 cbuf.set_insts_mark();
1908 $$$emit8$primary;
1909 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1910 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1911 %}
1913 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1914 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1915 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1917 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1918 cbuf.set_insts_mark();
1919 $$$emit8$primary;
1920 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1921 emit_d8(cbuf, disp); // Displacement
1923 %}
1925 enc_class Xor_Reg (eRegI dst) %{
1926 emit_opcode(cbuf, 0x33);
1927 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1928 %}
1930 // Following encoding is no longer used, but may be restored if calling
1931 // convention changes significantly.
1932 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1933 //
1934 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1935 // // int ic_reg = Matcher::inline_cache_reg();
1936 // // int ic_encode = Matcher::_regEncode[ic_reg];
1937 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1938 // // int imo_encode = Matcher::_regEncode[imo_reg];
1939 //
1940 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1941 // // // so we load it immediately before the call
1942 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1943 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1944 //
1945 // // xor rbp,ebp
1946 // emit_opcode(cbuf, 0x33);
1947 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1948 //
1949 // // CALL to interpreter.
1950 // cbuf.set_insts_mark();
1951 // $$$emit8$primary;
1952 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1953 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1954 // %}
1956 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1957 $$$emit8$primary;
1958 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1959 $$$emit8$shift$$constant;
1960 %}
1962 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1963 // Load immediate does not have a zero or sign extended version
1964 // for 8-bit immediates
1965 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1966 $$$emit32$src$$constant;
1967 %}
1969 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1970 // Load immediate does not have a zero or sign extended version
1971 // for 8-bit immediates
1972 emit_opcode(cbuf, $primary + $dst$$reg);
1973 $$$emit32$src$$constant;
1974 %}
1976 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1977 // Load immediate does not have a zero or sign extended version
1978 // for 8-bit immediates
1979 int dst_enc = $dst$$reg;
1980 int src_con = $src$$constant & 0x0FFFFFFFFL;
1981 if (src_con == 0) {
1982 // xor dst, dst
1983 emit_opcode(cbuf, 0x33);
1984 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1985 } else {
1986 emit_opcode(cbuf, $primary + dst_enc);
1987 emit_d32(cbuf, src_con);
1988 }
1989 %}
1991 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1992 // Load immediate does not have a zero or sign extended version
1993 // for 8-bit immediates
1994 int dst_enc = $dst$$reg + 2;
1995 int src_con = ((julong)($src$$constant)) >> 32;
1996 if (src_con == 0) {
1997 // xor dst, dst
1998 emit_opcode(cbuf, 0x33);
1999 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2000 } else {
2001 emit_opcode(cbuf, $primary + dst_enc);
2002 emit_d32(cbuf, src_con);
2003 }
2004 %}
2007 enc_class MovI2X_reg(regX dst, eRegI src) %{
2008 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2009 emit_opcode(cbuf, 0x0F );
2010 emit_opcode(cbuf, 0x6E );
2011 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2012 %}
2014 enc_class MovX2I_reg(eRegI dst, regX src) %{
2015 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2016 emit_opcode(cbuf, 0x0F );
2017 emit_opcode(cbuf, 0x7E );
2018 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2019 %}
2021 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
2022 { // MOVD $dst,$src.lo
2023 emit_opcode(cbuf,0x66);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x6E);
2026 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2027 }
2028 { // MOVD $tmp,$src.hi
2029 emit_opcode(cbuf,0x66);
2030 emit_opcode(cbuf,0x0F);
2031 emit_opcode(cbuf,0x6E);
2032 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2033 }
2034 { // PUNPCKLDQ $dst,$tmp
2035 emit_opcode(cbuf,0x66);
2036 emit_opcode(cbuf,0x0F);
2037 emit_opcode(cbuf,0x62);
2038 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2039 }
2040 %}
2042 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2043 { // MOVD $dst.lo,$src
2044 emit_opcode(cbuf,0x66);
2045 emit_opcode(cbuf,0x0F);
2046 emit_opcode(cbuf,0x7E);
2047 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2048 }
2049 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2050 emit_opcode(cbuf,0xF2);
2051 emit_opcode(cbuf,0x0F);
2052 emit_opcode(cbuf,0x70);
2053 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2054 emit_d8(cbuf, 0x4E);
2055 }
2056 { // MOVD $dst.hi,$tmp
2057 emit_opcode(cbuf,0x66);
2058 emit_opcode(cbuf,0x0F);
2059 emit_opcode(cbuf,0x7E);
2060 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2061 }
2062 %}
2065 // Encode a reg-reg copy. If it is useless, then empty encoding.
2066 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2067 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2068 %}
2070 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2071 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2072 %}
2074 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2075 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2076 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2077 %}
2079 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2080 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2081 %}
2083 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2084 $$$emit8$primary;
2085 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2086 %}
2088 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2089 $$$emit8$secondary;
2090 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2091 %}
2093 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2094 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2095 %}
2097 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2098 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2099 %}
2101 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2102 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2103 %}
2105 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2106 // Output immediate
2107 $$$emit32$src$$constant;
2108 %}
2110 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2111 // Output Float immediate bits
2112 jfloat jf = $src$$constant;
2113 int jf_as_bits = jint_cast( jf );
2114 emit_d32(cbuf, jf_as_bits);
2115 %}
2117 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2118 // Output Float immediate bits
2119 jfloat jf = $src$$constant;
2120 int jf_as_bits = jint_cast( jf );
2121 emit_d32(cbuf, jf_as_bits);
2122 %}
2124 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2125 // Output immediate
2126 $$$emit16$src$$constant;
2127 %}
2129 enc_class Con_d32(immI src) %{
2130 emit_d32(cbuf,$src$$constant);
2131 %}
2133 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2134 // Output immediate memory reference
2135 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2136 emit_d32(cbuf, 0x00);
2137 %}
2139 enc_class lock_prefix( ) %{
2140 if( os::is_MP() )
2141 emit_opcode(cbuf,0xF0); // [Lock]
2142 %}
2144 // Cmp-xchg long value.
2145 // Note: we need to swap rbx, and rcx before and after the
2146 // cmpxchg8 instruction because the instruction uses
2147 // rcx as the high order word of the new value to store but
2148 // our register encoding uses rbx,.
2149 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2151 // XCHG rbx,ecx
2152 emit_opcode(cbuf,0x87);
2153 emit_opcode(cbuf,0xD9);
2154 // [Lock]
2155 if( os::is_MP() )
2156 emit_opcode(cbuf,0xF0);
2157 // CMPXCHG8 [Eptr]
2158 emit_opcode(cbuf,0x0F);
2159 emit_opcode(cbuf,0xC7);
2160 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2161 // XCHG rbx,ecx
2162 emit_opcode(cbuf,0x87);
2163 emit_opcode(cbuf,0xD9);
2164 %}
2166 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2167 // [Lock]
2168 if( os::is_MP() )
2169 emit_opcode(cbuf,0xF0);
2171 // CMPXCHG [Eptr]
2172 emit_opcode(cbuf,0x0F);
2173 emit_opcode(cbuf,0xB1);
2174 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2175 %}
2177 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2178 int res_encoding = $res$$reg;
2180 // MOV res,0
2181 emit_opcode( cbuf, 0xB8 + res_encoding);
2182 emit_d32( cbuf, 0 );
2183 // JNE,s fail
2184 emit_opcode(cbuf,0x75);
2185 emit_d8(cbuf, 5 );
2186 // MOV res,1
2187 emit_opcode( cbuf, 0xB8 + res_encoding);
2188 emit_d32( cbuf, 1 );
2189 // fail:
2190 %}
2192 enc_class set_instruction_start( ) %{
2193 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2194 %}
2196 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2197 int reg_encoding = $ereg$$reg;
2198 int base = $mem$$base;
2199 int index = $mem$$index;
2200 int scale = $mem$$scale;
2201 int displace = $mem$$disp;
2202 bool disp_is_oop = $mem->disp_is_oop();
2203 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2204 %}
2206 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2207 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2208 int base = $mem$$base;
2209 int index = $mem$$index;
2210 int scale = $mem$$scale;
2211 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2212 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2213 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2214 %}
2216 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2217 int r1, r2;
2218 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2219 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2220 emit_opcode(cbuf,0x0F);
2221 emit_opcode(cbuf,$tertiary);
2222 emit_rm(cbuf, 0x3, r1, r2);
2223 emit_d8(cbuf,$cnt$$constant);
2224 emit_d8(cbuf,$primary);
2225 emit_rm(cbuf, 0x3, $secondary, r1);
2226 emit_d8(cbuf,$cnt$$constant);
2227 %}
2229 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2230 emit_opcode( cbuf, 0x8B ); // Move
2231 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2232 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2233 emit_d8(cbuf,$primary);
2234 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2235 emit_d8(cbuf,$cnt$$constant-32);
2236 }
2237 emit_d8(cbuf,$primary);
2238 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2239 emit_d8(cbuf,31);
2240 %}
2242 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2243 int r1, r2;
2244 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2245 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2247 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2248 emit_rm(cbuf, 0x3, r1, r2);
2249 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2250 emit_opcode(cbuf,$primary);
2251 emit_rm(cbuf, 0x3, $secondary, r1);
2252 emit_d8(cbuf,$cnt$$constant-32);
2253 }
2254 emit_opcode(cbuf,0x33); // XOR r2,r2
2255 emit_rm(cbuf, 0x3, r2, r2);
2256 %}
2258 // Clone of RegMem but accepts an extra parameter to access each
2259 // half of a double in memory; it never needs relocation info.
2260 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2261 emit_opcode(cbuf,$opcode$$constant);
2262 int reg_encoding = $rm_reg$$reg;
2263 int base = $mem$$base;
2264 int index = $mem$$index;
2265 int scale = $mem$$scale;
2266 int displace = $mem$$disp + $disp_for_half$$constant;
2267 bool disp_is_oop = false;
2268 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2269 %}
2271 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2272 //
2273 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2274 // and it never needs relocation information.
2275 // Frequently used to move data between FPU's Stack Top and memory.
2276 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2277 int rm_byte_opcode = $rm_opcode$$constant;
2278 int base = $mem$$base;
2279 int index = $mem$$index;
2280 int scale = $mem$$scale;
2281 int displace = $mem$$disp;
2282 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2283 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2284 %}
2286 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2287 int rm_byte_opcode = $rm_opcode$$constant;
2288 int base = $mem$$base;
2289 int index = $mem$$index;
2290 int scale = $mem$$scale;
2291 int displace = $mem$$disp;
2292 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2293 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2294 %}
2296 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2297 int reg_encoding = $dst$$reg;
2298 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2299 int index = 0x04; // 0x04 indicates no index
2300 int scale = 0x00; // 0x00 indicates no scale
2301 int displace = $src1$$constant; // 0x00 indicates no displacement
2302 bool disp_is_oop = false;
2303 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2304 %}
2306 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2307 // Compare dst,src
2308 emit_opcode(cbuf,0x3B);
2309 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2310 // jmp dst < src around move
2311 emit_opcode(cbuf,0x7C);
2312 emit_d8(cbuf,2);
2313 // move dst,src
2314 emit_opcode(cbuf,0x8B);
2315 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2316 %}
2318 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2319 // Compare dst,src
2320 emit_opcode(cbuf,0x3B);
2321 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2322 // jmp dst > src around move
2323 emit_opcode(cbuf,0x7F);
2324 emit_d8(cbuf,2);
2325 // move dst,src
2326 emit_opcode(cbuf,0x8B);
2327 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2328 %}
2330 enc_class enc_FP_store(memory mem, regD src) %{
2331 // If src is FPR1, we can just FST to store it.
2332 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2333 int reg_encoding = 0x2; // Just store
2334 int base = $mem$$base;
2335 int index = $mem$$index;
2336 int scale = $mem$$scale;
2337 int displace = $mem$$disp;
2338 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2339 if( $src$$reg != FPR1L_enc ) {
2340 reg_encoding = 0x3; // Store & pop
2341 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2342 emit_d8( cbuf, 0xC0-1+$src$$reg );
2343 }
2344 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2345 emit_opcode(cbuf,$primary);
2346 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2347 %}
2349 enc_class neg_reg(eRegI dst) %{
2350 // NEG $dst
2351 emit_opcode(cbuf,0xF7);
2352 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2353 %}
2355 enc_class setLT_reg(eCXRegI dst) %{
2356 // SETLT $dst
2357 emit_opcode(cbuf,0x0F);
2358 emit_opcode(cbuf,0x9C);
2359 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2360 %}
2362 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2363 int tmpReg = $tmp$$reg;
2365 // SUB $p,$q
2366 emit_opcode(cbuf,0x2B);
2367 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2368 // SBB $tmp,$tmp
2369 emit_opcode(cbuf,0x1B);
2370 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2371 // AND $tmp,$y
2372 emit_opcode(cbuf,0x23);
2373 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2374 // ADD $p,$tmp
2375 emit_opcode(cbuf,0x03);
2376 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2377 %}
2379 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2380 int tmpReg = $tmp$$reg;
2382 // SUB $p,$q
2383 emit_opcode(cbuf,0x2B);
2384 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2385 // SBB $tmp,$tmp
2386 emit_opcode(cbuf,0x1B);
2387 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2388 // AND $tmp,$y
2389 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2390 emit_opcode(cbuf,0x23);
2391 int reg_encoding = tmpReg;
2392 int base = $mem$$base;
2393 int index = $mem$$index;
2394 int scale = $mem$$scale;
2395 int displace = $mem$$disp;
2396 bool disp_is_oop = $mem->disp_is_oop();
2397 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2398 // ADD $p,$tmp
2399 emit_opcode(cbuf,0x03);
2400 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2401 %}
2403 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2404 // TEST shift,32
2405 emit_opcode(cbuf,0xF7);
2406 emit_rm(cbuf, 0x3, 0, ECX_enc);
2407 emit_d32(cbuf,0x20);
2408 // JEQ,s small
2409 emit_opcode(cbuf, 0x74);
2410 emit_d8(cbuf, 0x04);
2411 // MOV $dst.hi,$dst.lo
2412 emit_opcode( cbuf, 0x8B );
2413 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2414 // CLR $dst.lo
2415 emit_opcode(cbuf, 0x33);
2416 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2417 // small:
2418 // SHLD $dst.hi,$dst.lo,$shift
2419 emit_opcode(cbuf,0x0F);
2420 emit_opcode(cbuf,0xA5);
2421 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2422 // SHL $dst.lo,$shift"
2423 emit_opcode(cbuf,0xD3);
2424 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2425 %}
2427 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2428 // TEST shift,32
2429 emit_opcode(cbuf,0xF7);
2430 emit_rm(cbuf, 0x3, 0, ECX_enc);
2431 emit_d32(cbuf,0x20);
2432 // JEQ,s small
2433 emit_opcode(cbuf, 0x74);
2434 emit_d8(cbuf, 0x04);
2435 // MOV $dst.lo,$dst.hi
2436 emit_opcode( cbuf, 0x8B );
2437 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2438 // CLR $dst.hi
2439 emit_opcode(cbuf, 0x33);
2440 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2441 // small:
2442 // SHRD $dst.lo,$dst.hi,$shift
2443 emit_opcode(cbuf,0x0F);
2444 emit_opcode(cbuf,0xAD);
2445 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2446 // SHR $dst.hi,$shift"
2447 emit_opcode(cbuf,0xD3);
2448 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2449 %}
2451 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2452 // TEST shift,32
2453 emit_opcode(cbuf,0xF7);
2454 emit_rm(cbuf, 0x3, 0, ECX_enc);
2455 emit_d32(cbuf,0x20);
2456 // JEQ,s small
2457 emit_opcode(cbuf, 0x74);
2458 emit_d8(cbuf, 0x05);
2459 // MOV $dst.lo,$dst.hi
2460 emit_opcode( cbuf, 0x8B );
2461 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2462 // SAR $dst.hi,31
2463 emit_opcode(cbuf, 0xC1);
2464 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2465 emit_d8(cbuf, 0x1F );
2466 // small:
2467 // SHRD $dst.lo,$dst.hi,$shift
2468 emit_opcode(cbuf,0x0F);
2469 emit_opcode(cbuf,0xAD);
2470 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2471 // SAR $dst.hi,$shift"
2472 emit_opcode(cbuf,0xD3);
2473 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2474 %}
2477 // ----------------- Encodings for floating point unit -----------------
2478 // May leave result in FPU-TOS or FPU reg depending on opcodes
2479 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2480 $$$emit8$primary;
2481 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2482 %}
2484 // Pop argument in FPR0 with FSTP ST(0)
2485 enc_class PopFPU() %{
2486 emit_opcode( cbuf, 0xDD );
2487 emit_d8( cbuf, 0xD8 );
2488 %}
2490 // !!!!! equivalent to Pop_Reg_F
2491 enc_class Pop_Reg_D( regD dst ) %{
2492 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2493 emit_d8( cbuf, 0xD8+$dst$$reg );
2494 %}
2496 enc_class Push_Reg_D( regD dst ) %{
2497 emit_opcode( cbuf, 0xD9 );
2498 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2499 %}
2501 enc_class strictfp_bias1( regD dst ) %{
2502 emit_opcode( cbuf, 0xDB ); // FLD m80real
2503 emit_opcode( cbuf, 0x2D );
2504 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2505 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2506 emit_opcode( cbuf, 0xC8+$dst$$reg );
2507 %}
2509 enc_class strictfp_bias2( regD dst ) %{
2510 emit_opcode( cbuf, 0xDB ); // FLD m80real
2511 emit_opcode( cbuf, 0x2D );
2512 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2513 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2514 emit_opcode( cbuf, 0xC8+$dst$$reg );
2515 %}
2517 // Special case for moving an integer register to a stack slot.
2518 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2519 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2520 %}
2522 // Special case for moving a register to a stack slot.
2523 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2524 // Opcode already emitted
2525 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2526 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2527 emit_d32(cbuf, $dst$$disp); // Displacement
2528 %}
2530 // Push the integer in stackSlot 'src' onto FP-stack
2531 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2532 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2533 %}
2535 // Push the float in stackSlot 'src' onto FP-stack
2536 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2537 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2538 %}
2540 // Push the double in stackSlot 'src' onto FP-stack
2541 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2542 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2543 %}
2545 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2546 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2547 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2548 %}
2550 // Same as Pop_Mem_F except for opcode
2551 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2552 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2553 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2554 %}
2556 enc_class Pop_Reg_F( regF dst ) %{
2557 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2558 emit_d8( cbuf, 0xD8+$dst$$reg );
2559 %}
2561 enc_class Push_Reg_F( regF dst ) %{
2562 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2563 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2564 %}
2566 // Push FPU's float to a stack-slot, and pop FPU-stack
2567 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2568 int pop = 0x02;
2569 if ($src$$reg != FPR1L_enc) {
2570 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2571 emit_d8( cbuf, 0xC0-1+$src$$reg );
2572 pop = 0x03;
2573 }
2574 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2575 %}
2577 // Push FPU's double to a stack-slot, and pop FPU-stack
2578 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2579 int pop = 0x02;
2580 if ($src$$reg != FPR1L_enc) {
2581 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2582 emit_d8( cbuf, 0xC0-1+$src$$reg );
2583 pop = 0x03;
2584 }
2585 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2586 %}
2588 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2589 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2590 int pop = 0xD0 - 1; // -1 since we skip FLD
2591 if ($src$$reg != FPR1L_enc) {
2592 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2593 emit_d8( cbuf, 0xC0-1+$src$$reg );
2594 pop = 0xD8;
2595 }
2596 emit_opcode( cbuf, 0xDD );
2597 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2598 %}
2601 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2602 MacroAssembler masm(&cbuf);
2603 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2604 masm.fmul( $src2$$reg+0); // value at TOS
2605 masm.fadd( $src$$reg+0); // value at TOS
2606 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2607 %}
2610 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2611 // load dst in FPR0
2612 emit_opcode( cbuf, 0xD9 );
2613 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2614 if ($src$$reg != FPR1L_enc) {
2615 // fincstp
2616 emit_opcode (cbuf, 0xD9);
2617 emit_opcode (cbuf, 0xF7);
2618 // swap src with FPR1:
2619 // FXCH FPR1 with src
2620 emit_opcode(cbuf, 0xD9);
2621 emit_d8(cbuf, 0xC8-1+$src$$reg );
2622 // fdecstp
2623 emit_opcode (cbuf, 0xD9);
2624 emit_opcode (cbuf, 0xF6);
2625 }
2626 %}
2628 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2629 // Allocate a word
2630 emit_opcode(cbuf,0x83); // SUB ESP,8
2631 emit_opcode(cbuf,0xEC);
2632 emit_d8(cbuf,0x08);
2634 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2635 emit_opcode (cbuf, 0x0F );
2636 emit_opcode (cbuf, 0x11 );
2637 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2639 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2640 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2642 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2643 emit_opcode (cbuf, 0x0F );
2644 emit_opcode (cbuf, 0x11 );
2645 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2647 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2648 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2650 %}
2652 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2653 // Allocate a word
2654 emit_opcode(cbuf,0x83); // SUB ESP,4
2655 emit_opcode(cbuf,0xEC);
2656 emit_d8(cbuf,0x04);
2658 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2659 emit_opcode (cbuf, 0x0F );
2660 emit_opcode (cbuf, 0x11 );
2661 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2663 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2664 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2666 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2667 emit_opcode (cbuf, 0x0F );
2668 emit_opcode (cbuf, 0x11 );
2669 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2671 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2672 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2674 %}
2676 enc_class Push_ResultXD(regXD dst) %{
2677 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2679 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2680 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2681 emit_opcode (cbuf, 0x0F );
2682 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2683 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2685 emit_opcode(cbuf,0x83); // ADD ESP,8
2686 emit_opcode(cbuf,0xC4);
2687 emit_d8(cbuf,0x08);
2688 %}
2690 enc_class Push_ResultX(regX dst, immI d8) %{
2691 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2693 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2694 emit_opcode (cbuf, 0x0F );
2695 emit_opcode (cbuf, 0x10 );
2696 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2698 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2699 emit_opcode(cbuf,0xC4);
2700 emit_d8(cbuf,$d8$$constant);
2701 %}
2703 enc_class Push_SrcXD(regXD src) %{
2704 // Allocate a word
2705 emit_opcode(cbuf,0x83); // SUB ESP,8
2706 emit_opcode(cbuf,0xEC);
2707 emit_d8(cbuf,0x08);
2709 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2710 emit_opcode (cbuf, 0x0F );
2711 emit_opcode (cbuf, 0x11 );
2712 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2714 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2715 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2716 %}
2718 enc_class push_stack_temp_qword() %{
2719 emit_opcode(cbuf,0x83); // SUB ESP,8
2720 emit_opcode(cbuf,0xEC);
2721 emit_d8 (cbuf,0x08);
2722 %}
2724 enc_class pop_stack_temp_qword() %{
2725 emit_opcode(cbuf,0x83); // ADD ESP,8
2726 emit_opcode(cbuf,0xC4);
2727 emit_d8 (cbuf,0x08);
2728 %}
2730 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2731 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2732 emit_opcode (cbuf, 0x0F );
2733 emit_opcode (cbuf, 0x11 );
2734 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2736 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2737 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2738 %}
2740 // Compute X^Y using Intel's fast hardware instructions, if possible.
2741 // Otherwise return a NaN.
2742 enc_class pow_exp_core_encoding %{
2743 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2744 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2745 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2746 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2747 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2748 emit_opcode(cbuf,0x1C);
2749 emit_d8(cbuf,0x24);
2750 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2751 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2752 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2753 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2754 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2755 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2756 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2757 emit_d32(cbuf,0xFFFFF800);
2758 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2759 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2760 emit_d32(cbuf,1023);
2761 emit_opcode(cbuf,0x8B); // mov rbx,eax
2762 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2763 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2764 emit_rm(cbuf,0x3,0x4,EAX_enc);
2765 emit_d8(cbuf,20);
2766 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2767 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2768 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2769 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2770 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2771 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2772 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2773 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2774 emit_d32(cbuf,0);
2775 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2776 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2777 %}
2779 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2780 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2782 enc_class Push_Result_Mod_D( regD src) %{
2783 if ($src$$reg != FPR1L_enc) {
2784 // fincstp
2785 emit_opcode (cbuf, 0xD9);
2786 emit_opcode (cbuf, 0xF7);
2787 // FXCH FPR1 with src
2788 emit_opcode(cbuf, 0xD9);
2789 emit_d8(cbuf, 0xC8-1+$src$$reg );
2790 // fdecstp
2791 emit_opcode (cbuf, 0xD9);
2792 emit_opcode (cbuf, 0xF6);
2793 }
2794 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2795 // // FSTP FPR$dst$$reg
2796 // emit_opcode( cbuf, 0xDD );
2797 // emit_d8( cbuf, 0xD8+$dst$$reg );
2798 %}
2800 enc_class fnstsw_sahf_skip_parity() %{
2801 // fnstsw ax
2802 emit_opcode( cbuf, 0xDF );
2803 emit_opcode( cbuf, 0xE0 );
2804 // sahf
2805 emit_opcode( cbuf, 0x9E );
2806 // jnp ::skip
2807 emit_opcode( cbuf, 0x7B );
2808 emit_opcode( cbuf, 0x05 );
2809 %}
2811 enc_class emitModD() %{
2812 // fprem must be iterative
2813 // :: loop
2814 // fprem
2815 emit_opcode( cbuf, 0xD9 );
2816 emit_opcode( cbuf, 0xF8 );
2817 // wait
2818 emit_opcode( cbuf, 0x9b );
2819 // fnstsw ax
2820 emit_opcode( cbuf, 0xDF );
2821 emit_opcode( cbuf, 0xE0 );
2822 // sahf
2823 emit_opcode( cbuf, 0x9E );
2824 // jp ::loop
2825 emit_opcode( cbuf, 0x0F );
2826 emit_opcode( cbuf, 0x8A );
2827 emit_opcode( cbuf, 0xF4 );
2828 emit_opcode( cbuf, 0xFF );
2829 emit_opcode( cbuf, 0xFF );
2830 emit_opcode( cbuf, 0xFF );
2831 %}
2833 enc_class fpu_flags() %{
2834 // fnstsw_ax
2835 emit_opcode( cbuf, 0xDF);
2836 emit_opcode( cbuf, 0xE0);
2837 // test ax,0x0400
2838 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2839 emit_opcode( cbuf, 0xA9 );
2840 emit_d16 ( cbuf, 0x0400 );
2841 // // // This sequence works, but stalls for 12-16 cycles on PPro
2842 // // test rax,0x0400
2843 // emit_opcode( cbuf, 0xA9 );
2844 // emit_d32 ( cbuf, 0x00000400 );
2845 //
2846 // jz exit (no unordered comparison)
2847 emit_opcode( cbuf, 0x74 );
2848 emit_d8 ( cbuf, 0x02 );
2849 // mov ah,1 - treat as LT case (set carry flag)
2850 emit_opcode( cbuf, 0xB4 );
2851 emit_d8 ( cbuf, 0x01 );
2852 // sahf
2853 emit_opcode( cbuf, 0x9E);
2854 %}
2856 enc_class cmpF_P6_fixup() %{
2857 // Fixup the integer flags in case comparison involved a NaN
2858 //
2859 // JNP exit (no unordered comparison, P-flag is set by NaN)
2860 emit_opcode( cbuf, 0x7B );
2861 emit_d8 ( cbuf, 0x03 );
2862 // MOV AH,1 - treat as LT case (set carry flag)
2863 emit_opcode( cbuf, 0xB4 );
2864 emit_d8 ( cbuf, 0x01 );
2865 // SAHF
2866 emit_opcode( cbuf, 0x9E);
2867 // NOP // target for branch to avoid branch to branch
2868 emit_opcode( cbuf, 0x90);
2869 %}
2871 // fnstsw_ax();
2872 // sahf();
2873 // movl(dst, nan_result);
2874 // jcc(Assembler::parity, exit);
2875 // movl(dst, less_result);
2876 // jcc(Assembler::below, exit);
2877 // movl(dst, equal_result);
2878 // jcc(Assembler::equal, exit);
2879 // movl(dst, greater_result);
2881 // less_result = 1;
2882 // greater_result = -1;
2883 // equal_result = 0;
2884 // nan_result = -1;
2886 enc_class CmpF_Result(eRegI dst) %{
2887 // fnstsw_ax();
2888 emit_opcode( cbuf, 0xDF);
2889 emit_opcode( cbuf, 0xE0);
2890 // sahf
2891 emit_opcode( cbuf, 0x9E);
2892 // movl(dst, nan_result);
2893 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2894 emit_d32( cbuf, -1 );
2895 // jcc(Assembler::parity, exit);
2896 emit_opcode( cbuf, 0x7A );
2897 emit_d8 ( cbuf, 0x13 );
2898 // movl(dst, less_result);
2899 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2900 emit_d32( cbuf, -1 );
2901 // jcc(Assembler::below, exit);
2902 emit_opcode( cbuf, 0x72 );
2903 emit_d8 ( cbuf, 0x0C );
2904 // movl(dst, equal_result);
2905 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2906 emit_d32( cbuf, 0 );
2907 // jcc(Assembler::equal, exit);
2908 emit_opcode( cbuf, 0x74 );
2909 emit_d8 ( cbuf, 0x05 );
2910 // movl(dst, greater_result);
2911 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2912 emit_d32( cbuf, 1 );
2913 %}
2916 // XMM version of CmpF_Result. Because the XMM compare
2917 // instructions set the EFLAGS directly. It becomes simpler than
2918 // the float version above.
2919 enc_class CmpX_Result(eRegI dst) %{
2920 MacroAssembler _masm(&cbuf);
2921 Label nan, inc, done;
2923 __ jccb(Assembler::parity, nan);
2924 __ jccb(Assembler::equal, done);
2925 __ jccb(Assembler::above, inc);
2926 __ bind(nan);
2927 __ decrement(as_Register($dst$$reg)); // NO L qqq
2928 __ jmpb(done);
2929 __ bind(inc);
2930 __ increment(as_Register($dst$$reg)); // NO L qqq
2931 __ bind(done);
2932 %}
2934 // Compare the longs and set flags
2935 // BROKEN! Do Not use as-is
2936 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2937 // CMP $src1.hi,$src2.hi
2938 emit_opcode( cbuf, 0x3B );
2939 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2940 // JNE,s done
2941 emit_opcode(cbuf,0x75);
2942 emit_d8(cbuf, 2 );
2943 // CMP $src1.lo,$src2.lo
2944 emit_opcode( cbuf, 0x3B );
2945 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2946 // done:
2947 %}
2949 enc_class convert_int_long( regL dst, eRegI src ) %{
2950 // mov $dst.lo,$src
2951 int dst_encoding = $dst$$reg;
2952 int src_encoding = $src$$reg;
2953 encode_Copy( cbuf, dst_encoding , src_encoding );
2954 // mov $dst.hi,$src
2955 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2956 // sar $dst.hi,31
2957 emit_opcode( cbuf, 0xC1 );
2958 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2959 emit_d8(cbuf, 0x1F );
2960 %}
2962 enc_class convert_long_double( eRegL src ) %{
2963 // push $src.hi
2964 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2965 // push $src.lo
2966 emit_opcode(cbuf, 0x50+$src$$reg );
2967 // fild 64-bits at [SP]
2968 emit_opcode(cbuf,0xdf);
2969 emit_d8(cbuf, 0x6C);
2970 emit_d8(cbuf, 0x24);
2971 emit_d8(cbuf, 0x00);
2972 // pop stack
2973 emit_opcode(cbuf, 0x83); // add SP, #8
2974 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2975 emit_d8(cbuf, 0x8);
2976 %}
2978 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2979 // IMUL EDX:EAX,$src1
2980 emit_opcode( cbuf, 0xF7 );
2981 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2982 // SAR EDX,$cnt-32
2983 int shift_count = ((int)$cnt$$constant) - 32;
2984 if (shift_count > 0) {
2985 emit_opcode(cbuf, 0xC1);
2986 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2987 emit_d8(cbuf, shift_count);
2988 }
2989 %}
2991 // this version doesn't have add sp, 8
2992 enc_class convert_long_double2( eRegL src ) %{
2993 // push $src.hi
2994 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2995 // push $src.lo
2996 emit_opcode(cbuf, 0x50+$src$$reg );
2997 // fild 64-bits at [SP]
2998 emit_opcode(cbuf,0xdf);
2999 emit_d8(cbuf, 0x6C);
3000 emit_d8(cbuf, 0x24);
3001 emit_d8(cbuf, 0x00);
3002 %}
3004 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
3005 // Basic idea: long = (long)int * (long)int
3006 // IMUL EDX:EAX, src
3007 emit_opcode( cbuf, 0xF7 );
3008 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
3009 %}
3011 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
3012 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
3013 // MUL EDX:EAX, src
3014 emit_opcode( cbuf, 0xF7 );
3015 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
3016 %}
3018 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
3019 // Basic idea: lo(result) = lo(x_lo * y_lo)
3020 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3021 // MOV $tmp,$src.lo
3022 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
3023 // IMUL $tmp,EDX
3024 emit_opcode( cbuf, 0x0F );
3025 emit_opcode( cbuf, 0xAF );
3026 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3027 // MOV EDX,$src.hi
3028 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3029 // IMUL EDX,EAX
3030 emit_opcode( cbuf, 0x0F );
3031 emit_opcode( cbuf, 0xAF );
3032 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3033 // ADD $tmp,EDX
3034 emit_opcode( cbuf, 0x03 );
3035 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3036 // MUL EDX:EAX,$src.lo
3037 emit_opcode( cbuf, 0xF7 );
3038 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3039 // ADD EDX,ESI
3040 emit_opcode( cbuf, 0x03 );
3041 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3042 %}
3044 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3045 // Basic idea: lo(result) = lo(src * y_lo)
3046 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3047 // IMUL $tmp,EDX,$src
3048 emit_opcode( cbuf, 0x6B );
3049 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3050 emit_d8( cbuf, (int)$src$$constant );
3051 // MOV EDX,$src
3052 emit_opcode(cbuf, 0xB8 + EDX_enc);
3053 emit_d32( cbuf, (int)$src$$constant );
3054 // MUL EDX:EAX,EDX
3055 emit_opcode( cbuf, 0xF7 );
3056 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3057 // ADD EDX,ESI
3058 emit_opcode( cbuf, 0x03 );
3059 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3060 %}
3062 enc_class long_div( eRegL src1, eRegL src2 ) %{
3063 // PUSH src1.hi
3064 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3065 // PUSH src1.lo
3066 emit_opcode(cbuf, 0x50+$src1$$reg );
3067 // PUSH src2.hi
3068 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3069 // PUSH src2.lo
3070 emit_opcode(cbuf, 0x50+$src2$$reg );
3071 // CALL directly to the runtime
3072 cbuf.set_insts_mark();
3073 emit_opcode(cbuf,0xE8); // Call into runtime
3074 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3075 // Restore stack
3076 emit_opcode(cbuf, 0x83); // add SP, #framesize
3077 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3078 emit_d8(cbuf, 4*4);
3079 %}
3081 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3082 // PUSH src1.hi
3083 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3084 // PUSH src1.lo
3085 emit_opcode(cbuf, 0x50+$src1$$reg );
3086 // PUSH src2.hi
3087 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3088 // PUSH src2.lo
3089 emit_opcode(cbuf, 0x50+$src2$$reg );
3090 // CALL directly to the runtime
3091 cbuf.set_insts_mark();
3092 emit_opcode(cbuf,0xE8); // Call into runtime
3093 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3094 // Restore stack
3095 emit_opcode(cbuf, 0x83); // add SP, #framesize
3096 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3097 emit_d8(cbuf, 4*4);
3098 %}
3100 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3101 // MOV $tmp,$src.lo
3102 emit_opcode(cbuf, 0x8B);
3103 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3104 // OR $tmp,$src.hi
3105 emit_opcode(cbuf, 0x0B);
3106 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3107 %}
3109 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3110 // CMP $src1.lo,$src2.lo
3111 emit_opcode( cbuf, 0x3B );
3112 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3113 // JNE,s skip
3114 emit_cc(cbuf, 0x70, 0x5);
3115 emit_d8(cbuf,2);
3116 // CMP $src1.hi,$src2.hi
3117 emit_opcode( cbuf, 0x3B );
3118 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3119 %}
3121 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3122 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3123 emit_opcode( cbuf, 0x3B );
3124 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3125 // MOV $tmp,$src1.hi
3126 emit_opcode( cbuf, 0x8B );
3127 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3128 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3129 emit_opcode( cbuf, 0x1B );
3130 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3131 %}
3133 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3134 // XOR $tmp,$tmp
3135 emit_opcode(cbuf,0x33); // XOR
3136 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3137 // CMP $tmp,$src.lo
3138 emit_opcode( cbuf, 0x3B );
3139 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3140 // SBB $tmp,$src.hi
3141 emit_opcode( cbuf, 0x1B );
3142 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3143 %}
3145 // Sniff, sniff... smells like Gnu Superoptimizer
3146 enc_class neg_long( eRegL dst ) %{
3147 emit_opcode(cbuf,0xF7); // NEG hi
3148 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3149 emit_opcode(cbuf,0xF7); // NEG lo
3150 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3151 emit_opcode(cbuf,0x83); // SBB hi,0
3152 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3153 emit_d8 (cbuf,0 );
3154 %}
3156 enc_class movq_ld(regXD dst, memory mem) %{
3157 MacroAssembler _masm(&cbuf);
3158 __ movq($dst$$XMMRegister, $mem$$Address);
3159 %}
3161 enc_class movq_st(memory mem, regXD src) %{
3162 MacroAssembler _masm(&cbuf);
3163 __ movq($mem$$Address, $src$$XMMRegister);
3164 %}
3166 enc_class pshufd_8x8(regX dst, regX src) %{
3167 MacroAssembler _masm(&cbuf);
3169 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3170 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3171 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3172 %}
3174 enc_class pshufd_4x16(regX dst, regX src) %{
3175 MacroAssembler _masm(&cbuf);
3177 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3178 %}
3180 enc_class pshufd(regXD dst, regXD src, int mode) %{
3181 MacroAssembler _masm(&cbuf);
3183 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3184 %}
3186 enc_class pxor(regXD dst, regXD src) %{
3187 MacroAssembler _masm(&cbuf);
3189 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3190 %}
3192 enc_class mov_i2x(regXD dst, eRegI src) %{
3193 MacroAssembler _masm(&cbuf);
3195 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3196 %}
3199 // Because the transitions from emitted code to the runtime
3200 // monitorenter/exit helper stubs are so slow it's critical that
3201 // we inline both the stack-locking fast-path and the inflated fast path.
3202 //
3203 // See also: cmpFastLock and cmpFastUnlock.
3204 //
3205 // What follows is a specialized inline transliteration of the code
3206 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3207 // another option would be to emit TrySlowEnter and TrySlowExit methods
3208 // at startup-time. These methods would accept arguments as
3209 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3210 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3211 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3212 // In practice, however, the # of lock sites is bounded and is usually small.
3213 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3214 // if the processor uses simple bimodal branch predictors keyed by EIP
3215 // Since the helper routines would be called from multiple synchronization
3216 // sites.
3217 //
3218 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3219 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3220 // to those specialized methods. That'd give us a mostly platform-independent
3221 // implementation that the JITs could optimize and inline at their pleasure.
3222 // Done correctly, the only time we'd need to cross to native could would be
3223 // to park() or unpark() threads. We'd also need a few more unsafe operators
3224 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3225 // (b) explicit barriers or fence operations.
3226 //
3227 // TODO:
3228 //
3229 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3230 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3231 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3232 // the lock operators would typically be faster than reifying Self.
3233 //
3234 // * Ideally I'd define the primitives as:
3235 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3236 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3237 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3238 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3239 // Furthermore the register assignments are overconstrained, possibly resulting in
3240 // sub-optimal code near the synchronization site.
3241 //
3242 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3243 // Alternately, use a better sp-proximity test.
3244 //
3245 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3246 // Either one is sufficient to uniquely identify a thread.
3247 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3248 //
3249 // * Intrinsify notify() and notifyAll() for the common cases where the
3250 // object is locked by the calling thread but the waitlist is empty.
3251 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3252 //
3253 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3254 // But beware of excessive branch density on AMD Opterons.
3255 //
3256 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3257 // or failure of the fast-path. If the fast-path fails then we pass
3258 // control to the slow-path, typically in C. In Fast_Lock and
3259 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3260 // will emit a conditional branch immediately after the node.
3261 // So we have branches to branches and lots of ICC.ZF games.
3262 // Instead, it might be better to have C2 pass a "FailureLabel"
3263 // into Fast_Lock and Fast_Unlock. In the case of success, control
3264 // will drop through the node. ICC.ZF is undefined at exit.
3265 // In the case of failure, the node will branch directly to the
3266 // FailureLabel
3269 // obj: object to lock
3270 // box: on-stack box address (displaced header location) - KILLED
3271 // rax,: tmp -- KILLED
3272 // scr: tmp -- KILLED
3273 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3275 Register objReg = as_Register($obj$$reg);
3276 Register boxReg = as_Register($box$$reg);
3277 Register tmpReg = as_Register($tmp$$reg);
3278 Register scrReg = as_Register($scr$$reg);
3280 // Ensure the register assignents are disjoint
3281 guarantee (objReg != boxReg, "") ;
3282 guarantee (objReg != tmpReg, "") ;
3283 guarantee (objReg != scrReg, "") ;
3284 guarantee (boxReg != tmpReg, "") ;
3285 guarantee (boxReg != scrReg, "") ;
3286 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3288 MacroAssembler masm(&cbuf);
3290 if (_counters != NULL) {
3291 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3292 }
3293 if (EmitSync & 1) {
3294 // set box->dhw = unused_mark (3)
3295 // Force all sync thru slow-path: slow_enter() and slow_exit()
3296 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3297 masm.cmpptr (rsp, (int32_t)0) ;
3298 } else
3299 if (EmitSync & 2) {
3300 Label DONE_LABEL ;
3301 if (UseBiasedLocking) {
3302 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3303 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3304 }
3306 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3307 masm.orptr (tmpReg, 0x1);
3308 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3309 if (os::is_MP()) { masm.lock(); }
3310 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3311 masm.jcc(Assembler::equal, DONE_LABEL);
3312 // Recursive locking
3313 masm.subptr(tmpReg, rsp);
3314 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3315 masm.movptr(Address(boxReg, 0), tmpReg);
3316 masm.bind(DONE_LABEL) ;
3317 } else {
3318 // Possible cases that we'll encounter in fast_lock
3319 // ------------------------------------------------
3320 // * Inflated
3321 // -- unlocked
3322 // -- Locked
3323 // = by self
3324 // = by other
3325 // * biased
3326 // -- by Self
3327 // -- by other
3328 // * neutral
3329 // * stack-locked
3330 // -- by self
3331 // = sp-proximity test hits
3332 // = sp-proximity test generates false-negative
3333 // -- by other
3334 //
3336 Label IsInflated, DONE_LABEL, PopDone ;
3338 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3339 // order to reduce the number of conditional branches in the most common cases.
3340 // Beware -- there's a subtle invariant that fetch of the markword
3341 // at [FETCH], below, will never observe a biased encoding (*101b).
3342 // If this invariant is not held we risk exclusion (safety) failure.
3343 if (UseBiasedLocking && !UseOptoBiasInlining) {
3344 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3345 }
3347 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3348 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3349 masm.jccb (Assembler::notZero, IsInflated) ;
3351 // Attempt stack-locking ...
3352 masm.orptr (tmpReg, 0x1);
3353 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3354 if (os::is_MP()) { masm.lock(); }
3355 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3356 if (_counters != NULL) {
3357 masm.cond_inc32(Assembler::equal,
3358 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3359 }
3360 masm.jccb (Assembler::equal, DONE_LABEL);
3362 // Recursive locking
3363 masm.subptr(tmpReg, rsp);
3364 masm.andptr(tmpReg, 0xFFFFF003 );
3365 masm.movptr(Address(boxReg, 0), tmpReg);
3366 if (_counters != NULL) {
3367 masm.cond_inc32(Assembler::equal,
3368 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3369 }
3370 masm.jmp (DONE_LABEL) ;
3372 masm.bind (IsInflated) ;
3374 // The object is inflated.
3375 //
3376 // TODO-FIXME: eliminate the ugly use of manifest constants:
3377 // Use markOopDesc::monitor_value instead of "2".
3378 // use markOop::unused_mark() instead of "3".
3379 // The tmpReg value is an objectMonitor reference ORed with
3380 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3381 // objectmonitor pointer by masking off the "2" bit or we can just
3382 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3383 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3384 //
3385 // I use the latter as it avoids AGI stalls.
3386 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3387 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3388 //
3389 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3391 // boxReg refers to the on-stack BasicLock in the current frame.
3392 // We'd like to write:
3393 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3394 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3395 // additional latency as we have another ST in the store buffer that must drain.
3397 if (EmitSync & 8192) {
3398 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3399 masm.get_thread (scrReg) ;
3400 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3401 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3402 if (os::is_MP()) { masm.lock(); }
3403 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3404 } else
3405 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3406 masm.movptr(scrReg, boxReg) ;
3407 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3409 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3410 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3411 // prefetchw [eax + Offset(_owner)-2]
3412 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3413 }
3415 if ((EmitSync & 64) == 0) {
3416 // Optimistic form: consider XORL tmpReg,tmpReg
3417 masm.movptr(tmpReg, NULL_WORD) ;
3418 } else {
3419 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3420 // Test-And-CAS instead of CAS
3421 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3422 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3423 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3424 }
3426 // Appears unlocked - try to swing _owner from null to non-null.
3427 // Ideally, I'd manifest "Self" with get_thread and then attempt
3428 // to CAS the register containing Self into m->Owner.
3429 // But we don't have enough registers, so instead we can either try to CAS
3430 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3431 // we later store "Self" into m->Owner. Transiently storing a stack address
3432 // (rsp or the address of the box) into m->owner is harmless.
3433 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3434 if (os::is_MP()) { masm.lock(); }
3435 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3436 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3437 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3438 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3439 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3440 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3442 // If the CAS fails we can either retry or pass control to the slow-path.
3443 // We use the latter tactic.
3444 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3445 // If the CAS was successful ...
3446 // Self has acquired the lock
3447 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3448 // Intentional fall-through into DONE_LABEL ...
3449 } else {
3450 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3451 masm.movptr(boxReg, tmpReg) ;
3453 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3454 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3455 // prefetchw [eax + Offset(_owner)-2]
3456 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3457 }
3459 if ((EmitSync & 64) == 0) {
3460 // Optimistic form
3461 masm.xorptr (tmpReg, tmpReg) ;
3462 } else {
3463 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3464 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3465 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3466 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3467 }
3469 // Appears unlocked - try to swing _owner from null to non-null.
3470 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3471 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3472 masm.get_thread (scrReg) ;
3473 if (os::is_MP()) { masm.lock(); }
3474 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3476 // If the CAS fails we can either retry or pass control to the slow-path.
3477 // We use the latter tactic.
3478 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3479 // If the CAS was successful ...
3480 // Self has acquired the lock
3481 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3482 // Intentional fall-through into DONE_LABEL ...
3483 }
3485 // DONE_LABEL is a hot target - we'd really like to place it at the
3486 // start of cache line by padding with NOPs.
3487 // See the AMD and Intel software optimization manuals for the
3488 // most efficient "long" NOP encodings.
3489 // Unfortunately none of our alignment mechanisms suffice.
3490 masm.bind(DONE_LABEL);
3492 // Avoid branch-to-branch on AMD processors
3493 // This appears to be superstition.
3494 if (EmitSync & 32) masm.nop() ;
3497 // At DONE_LABEL the icc ZFlag is set as follows ...
3498 // Fast_Unlock uses the same protocol.
3499 // ZFlag == 1 -> Success
3500 // ZFlag == 0 -> Failure - force control through the slow-path
3501 }
3502 %}
3504 // obj: object to unlock
3505 // box: box address (displaced header location), killed. Must be EAX.
3506 // rbx,: killed tmp; cannot be obj nor box.
3507 //
3508 // Some commentary on balanced locking:
3509 //
3510 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3511 // Methods that don't have provably balanced locking are forced to run in the
3512 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3513 // The interpreter provides two properties:
3514 // I1: At return-time the interpreter automatically and quietly unlocks any
3515 // objects acquired the current activation (frame). Recall that the
3516 // interpreter maintains an on-stack list of locks currently held by
3517 // a frame.
3518 // I2: If a method attempts to unlock an object that is not held by the
3519 // the frame the interpreter throws IMSX.
3520 //
3521 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3522 // B() doesn't have provably balanced locking so it runs in the interpreter.
3523 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3524 // is still locked by A().
3525 //
3526 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3527 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3528 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3529 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3531 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3533 Register objReg = as_Register($obj$$reg);
3534 Register boxReg = as_Register($box$$reg);
3535 Register tmpReg = as_Register($tmp$$reg);
3537 guarantee (objReg != boxReg, "") ;
3538 guarantee (objReg != tmpReg, "") ;
3539 guarantee (boxReg != tmpReg, "") ;
3540 guarantee (boxReg == as_Register(EAX_enc), "") ;
3541 MacroAssembler masm(&cbuf);
3543 if (EmitSync & 4) {
3544 // Disable - inhibit all inlining. Force control through the slow-path
3545 masm.cmpptr (rsp, 0) ;
3546 } else
3547 if (EmitSync & 8) {
3548 Label DONE_LABEL ;
3549 if (UseBiasedLocking) {
3550 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3551 }
3552 // classic stack-locking code ...
3553 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3554 masm.testptr(tmpReg, tmpReg) ;
3555 masm.jcc (Assembler::zero, DONE_LABEL) ;
3556 if (os::is_MP()) { masm.lock(); }
3557 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3558 masm.bind(DONE_LABEL);
3559 } else {
3560 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3562 // Critically, the biased locking test must have precedence over
3563 // and appear before the (box->dhw == 0) recursive stack-lock test.
3564 if (UseBiasedLocking && !UseOptoBiasInlining) {
3565 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3566 }
3568 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3569 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3570 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3572 masm.testptr(tmpReg, 0x02) ; // Inflated?
3573 masm.jccb (Assembler::zero, Stacked) ;
3575 masm.bind (Inflated) ;
3576 // It's inflated.
3577 // Despite our balanced locking property we still check that m->_owner == Self
3578 // as java routines or native JNI code called by this thread might
3579 // have released the lock.
3580 // Refer to the comments in synchronizer.cpp for how we might encode extra
3581 // state in _succ so we can avoid fetching EntryList|cxq.
3582 //
3583 // I'd like to add more cases in fast_lock() and fast_unlock() --
3584 // such as recursive enter and exit -- but we have to be wary of
3585 // I$ bloat, T$ effects and BP$ effects.
3586 //
3587 // If there's no contention try a 1-0 exit. That is, exit without
3588 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3589 // we detect and recover from the race that the 1-0 exit admits.
3590 //
3591 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3592 // before it STs null into _owner, releasing the lock. Updates
3593 // to data protected by the critical section must be visible before
3594 // we drop the lock (and thus before any other thread could acquire
3595 // the lock and observe the fields protected by the lock).
3596 // IA32's memory-model is SPO, so STs are ordered with respect to
3597 // each other and there's no need for an explicit barrier (fence).
3598 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3600 masm.get_thread (boxReg) ;
3601 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3602 // prefetchw [ebx + Offset(_owner)-2]
3603 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3604 }
3606 // Note that we could employ various encoding schemes to reduce
3607 // the number of loads below (currently 4) to just 2 or 3.
3608 // Refer to the comments in synchronizer.cpp.
3609 // In practice the chain of fetches doesn't seem to impact performance, however.
3610 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3611 // Attempt to reduce branch density - AMD's branch predictor.
3612 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3613 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3614 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3615 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3616 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3617 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3618 masm.jmpb (DONE_LABEL) ;
3619 } else {
3620 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3621 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3622 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3623 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3624 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3625 masm.jccb (Assembler::notZero, CheckSucc) ;
3626 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3627 masm.jmpb (DONE_LABEL) ;
3628 }
3630 // The Following code fragment (EmitSync & 65536) improves the performance of
3631 // contended applications and contended synchronization microbenchmarks.
3632 // Unfortunately the emission of the code - even though not executed - causes regressions
3633 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3634 // with an equal number of never-executed NOPs results in the same regression.
3635 // We leave it off by default.
3637 if ((EmitSync & 65536) != 0) {
3638 Label LSuccess, LGoSlowPath ;
3640 masm.bind (CheckSucc) ;
3642 // Optional pre-test ... it's safe to elide this
3643 if ((EmitSync & 16) == 0) {
3644 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3645 masm.jccb (Assembler::zero, LGoSlowPath) ;
3646 }
3648 // We have a classic Dekker-style idiom:
3649 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3650 // There are a number of ways to implement the barrier:
3651 // (1) lock:andl &m->_owner, 0
3652 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3653 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3654 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3655 // (2) If supported, an explicit MFENCE is appealing.
3656 // In older IA32 processors MFENCE is slower than lock:add or xchg
3657 // particularly if the write-buffer is full as might be the case if
3658 // if stores closely precede the fence or fence-equivalent instruction.
3659 // In more modern implementations MFENCE appears faster, however.
3660 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3661 // The $lines underlying the top-of-stack should be in M-state.
3662 // The locked add instruction is serializing, of course.
3663 // (4) Use xchg, which is serializing
3664 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3665 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3666 // The integer condition codes will tell us if succ was 0.
3667 // Since _succ and _owner should reside in the same $line and
3668 // we just stored into _owner, it's likely that the $line
3669 // remains in M-state for the lock:orl.
3670 //
3671 // We currently use (3), although it's likely that switching to (2)
3672 // is correct for the future.
3674 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3675 if (os::is_MP()) {
3676 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3677 masm.mfence();
3678 } else {
3679 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3680 }
3681 }
3682 // Ratify _succ remains non-null
3683 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3684 masm.jccb (Assembler::notZero, LSuccess) ;
3686 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3687 if (os::is_MP()) { masm.lock(); }
3688 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3689 masm.jccb (Assembler::notEqual, LSuccess) ;
3690 // Since we're low on registers we installed rsp as a placeholding in _owner.
3691 // Now install Self over rsp. This is safe as we're transitioning from
3692 // non-null to non=null
3693 masm.get_thread (boxReg) ;
3694 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3695 // Intentional fall-through into LGoSlowPath ...
3697 masm.bind (LGoSlowPath) ;
3698 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3699 masm.jmpb (DONE_LABEL) ;
3701 masm.bind (LSuccess) ;
3702 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3703 masm.jmpb (DONE_LABEL) ;
3704 }
3706 masm.bind (Stacked) ;
3707 // It's not inflated and it's not recursively stack-locked and it's not biased.
3708 // It must be stack-locked.
3709 // Try to reset the header to displaced header.
3710 // The "box" value on the stack is stable, so we can reload
3711 // and be assured we observe the same value as above.
3712 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3713 if (os::is_MP()) { masm.lock(); }
3714 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3715 // Intention fall-thru into DONE_LABEL
3718 // DONE_LABEL is a hot target - we'd really like to place it at the
3719 // start of cache line by padding with NOPs.
3720 // See the AMD and Intel software optimization manuals for the
3721 // most efficient "long" NOP encodings.
3722 // Unfortunately none of our alignment mechanisms suffice.
3723 if ((EmitSync & 65536) == 0) {
3724 masm.bind (CheckSucc) ;
3725 }
3726 masm.bind(DONE_LABEL);
3728 // Avoid branch to branch on AMD processors
3729 if (EmitSync & 32768) { masm.nop() ; }
3730 }
3731 %}
3734 enc_class enc_pop_rdx() %{
3735 emit_opcode(cbuf,0x5A);
3736 %}
3738 enc_class enc_rethrow() %{
3739 cbuf.set_insts_mark();
3740 emit_opcode(cbuf, 0xE9); // jmp entry
3741 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3742 runtime_call_Relocation::spec(), RELOC_IMM32 );
3743 %}
3746 // Convert a double to an int. Java semantics require we do complex
3747 // manglelations in the corner cases. So we set the rounding mode to
3748 // 'zero', store the darned double down as an int, and reset the
3749 // rounding mode to 'nearest'. The hardware throws an exception which
3750 // patches up the correct value directly to the stack.
3751 enc_class D2I_encoding( regD src ) %{
3752 // Flip to round-to-zero mode. We attempted to allow invalid-op
3753 // exceptions here, so that a NAN or other corner-case value will
3754 // thrown an exception (but normal values get converted at full speed).
3755 // However, I2C adapters and other float-stack manglers leave pending
3756 // invalid-op exceptions hanging. We would have to clear them before
3757 // enabling them and that is more expensive than just testing for the
3758 // invalid value Intel stores down in the corner cases.
3759 emit_opcode(cbuf,0xD9); // FLDCW trunc
3760 emit_opcode(cbuf,0x2D);
3761 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3762 // Allocate a word
3763 emit_opcode(cbuf,0x83); // SUB ESP,4
3764 emit_opcode(cbuf,0xEC);
3765 emit_d8(cbuf,0x04);
3766 // Encoding assumes a double has been pushed into FPR0.
3767 // Store down the double as an int, popping the FPU stack
3768 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3769 emit_opcode(cbuf,0x1C);
3770 emit_d8(cbuf,0x24);
3771 // Restore the rounding mode; mask the exception
3772 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3773 emit_opcode(cbuf,0x2D);
3774 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3775 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3776 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3778 // Load the converted int; adjust CPU stack
3779 emit_opcode(cbuf,0x58); // POP EAX
3780 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3781 emit_d32 (cbuf,0x80000000); // 0x80000000
3782 emit_opcode(cbuf,0x75); // JNE around_slow_call
3783 emit_d8 (cbuf,0x07); // Size of slow_call
3784 // Push src onto stack slow-path
3785 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3786 emit_d8 (cbuf,0xC0-1+$src$$reg );
3787 // CALL directly to the runtime
3788 cbuf.set_insts_mark();
3789 emit_opcode(cbuf,0xE8); // Call into runtime
3790 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3791 // Carry on here...
3792 %}
3794 enc_class D2L_encoding( regD src ) %{
3795 emit_opcode(cbuf,0xD9); // FLDCW trunc
3796 emit_opcode(cbuf,0x2D);
3797 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3798 // Allocate a word
3799 emit_opcode(cbuf,0x83); // SUB ESP,8
3800 emit_opcode(cbuf,0xEC);
3801 emit_d8(cbuf,0x08);
3802 // Encoding assumes a double has been pushed into FPR0.
3803 // Store down the double as a long, popping the FPU stack
3804 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3805 emit_opcode(cbuf,0x3C);
3806 emit_d8(cbuf,0x24);
3807 // Restore the rounding mode; mask the exception
3808 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3809 emit_opcode(cbuf,0x2D);
3810 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3811 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3812 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3814 // Load the converted int; adjust CPU stack
3815 emit_opcode(cbuf,0x58); // POP EAX
3816 emit_opcode(cbuf,0x5A); // POP EDX
3817 emit_opcode(cbuf,0x81); // CMP EDX,imm
3818 emit_d8 (cbuf,0xFA); // rdx
3819 emit_d32 (cbuf,0x80000000); // 0x80000000
3820 emit_opcode(cbuf,0x75); // JNE around_slow_call
3821 emit_d8 (cbuf,0x07+4); // Size of slow_call
3822 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3823 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3824 emit_opcode(cbuf,0x75); // JNE around_slow_call
3825 emit_d8 (cbuf,0x07); // Size of slow_call
3826 // Push src onto stack slow-path
3827 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3828 emit_d8 (cbuf,0xC0-1+$src$$reg );
3829 // CALL directly to the runtime
3830 cbuf.set_insts_mark();
3831 emit_opcode(cbuf,0xE8); // Call into runtime
3832 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3833 // Carry on here...
3834 %}
3836 enc_class X2L_encoding( regX src ) %{
3837 // Allocate a word
3838 emit_opcode(cbuf,0x83); // SUB ESP,8
3839 emit_opcode(cbuf,0xEC);
3840 emit_d8(cbuf,0x08);
3842 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3843 emit_opcode (cbuf, 0x0F );
3844 emit_opcode (cbuf, 0x11 );
3845 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3847 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3848 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3850 emit_opcode(cbuf,0xD9); // FLDCW trunc
3851 emit_opcode(cbuf,0x2D);
3852 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3854 // Encoding assumes a double has been pushed into FPR0.
3855 // Store down the double as a long, popping the FPU stack
3856 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3857 emit_opcode(cbuf,0x3C);
3858 emit_d8(cbuf,0x24);
3860 // Restore the rounding mode; mask the exception
3861 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3862 emit_opcode(cbuf,0x2D);
3863 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3864 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3865 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3867 // Load the converted int; adjust CPU stack
3868 emit_opcode(cbuf,0x58); // POP EAX
3870 emit_opcode(cbuf,0x5A); // POP EDX
3872 emit_opcode(cbuf,0x81); // CMP EDX,imm
3873 emit_d8 (cbuf,0xFA); // rdx
3874 emit_d32 (cbuf,0x80000000);// 0x80000000
3876 emit_opcode(cbuf,0x75); // JNE around_slow_call
3877 emit_d8 (cbuf,0x13+4); // Size of slow_call
3879 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3880 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3882 emit_opcode(cbuf,0x75); // JNE around_slow_call
3883 emit_d8 (cbuf,0x13); // Size of slow_call
3885 // Allocate a word
3886 emit_opcode(cbuf,0x83); // SUB ESP,4
3887 emit_opcode(cbuf,0xEC);
3888 emit_d8(cbuf,0x04);
3890 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3891 emit_opcode (cbuf, 0x0F );
3892 emit_opcode (cbuf, 0x11 );
3893 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3895 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3896 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3898 emit_opcode(cbuf,0x83); // ADD ESP,4
3899 emit_opcode(cbuf,0xC4);
3900 emit_d8(cbuf,0x04);
3902 // CALL directly to the runtime
3903 cbuf.set_insts_mark();
3904 emit_opcode(cbuf,0xE8); // Call into runtime
3905 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3906 // Carry on here...
3907 %}
3909 enc_class XD2L_encoding( regXD src ) %{
3910 // Allocate a word
3911 emit_opcode(cbuf,0x83); // SUB ESP,8
3912 emit_opcode(cbuf,0xEC);
3913 emit_d8(cbuf,0x08);
3915 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3916 emit_opcode (cbuf, 0x0F );
3917 emit_opcode (cbuf, 0x11 );
3918 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3920 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3921 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3923 emit_opcode(cbuf,0xD9); // FLDCW trunc
3924 emit_opcode(cbuf,0x2D);
3925 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3927 // Encoding assumes a double has been pushed into FPR0.
3928 // Store down the double as a long, popping the FPU stack
3929 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3930 emit_opcode(cbuf,0x3C);
3931 emit_d8(cbuf,0x24);
3933 // Restore the rounding mode; mask the exception
3934 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3935 emit_opcode(cbuf,0x2D);
3936 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3937 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3938 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3940 // Load the converted int; adjust CPU stack
3941 emit_opcode(cbuf,0x58); // POP EAX
3943 emit_opcode(cbuf,0x5A); // POP EDX
3945 emit_opcode(cbuf,0x81); // CMP EDX,imm
3946 emit_d8 (cbuf,0xFA); // rdx
3947 emit_d32 (cbuf,0x80000000); // 0x80000000
3949 emit_opcode(cbuf,0x75); // JNE around_slow_call
3950 emit_d8 (cbuf,0x13+4); // Size of slow_call
3952 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3953 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3955 emit_opcode(cbuf,0x75); // JNE around_slow_call
3956 emit_d8 (cbuf,0x13); // Size of slow_call
3958 // Push src onto stack slow-path
3959 // Allocate a word
3960 emit_opcode(cbuf,0x83); // SUB ESP,8
3961 emit_opcode(cbuf,0xEC);
3962 emit_d8(cbuf,0x08);
3964 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3965 emit_opcode (cbuf, 0x0F );
3966 emit_opcode (cbuf, 0x11 );
3967 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3969 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3970 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3972 emit_opcode(cbuf,0x83); // ADD ESP,8
3973 emit_opcode(cbuf,0xC4);
3974 emit_d8(cbuf,0x08);
3976 // CALL directly to the runtime
3977 cbuf.set_insts_mark();
3978 emit_opcode(cbuf,0xE8); // Call into runtime
3979 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3980 // Carry on here...
3981 %}
3983 enc_class D2X_encoding( regX dst, regD src ) %{
3984 // Allocate a word
3985 emit_opcode(cbuf,0x83); // SUB ESP,4
3986 emit_opcode(cbuf,0xEC);
3987 emit_d8(cbuf,0x04);
3988 int pop = 0x02;
3989 if ($src$$reg != FPR1L_enc) {
3990 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
3991 emit_d8( cbuf, 0xC0-1+$src$$reg );
3992 pop = 0x03;
3993 }
3994 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
3996 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
3997 emit_opcode (cbuf, 0x0F );
3998 emit_opcode (cbuf, 0x10 );
3999 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4001 emit_opcode(cbuf,0x83); // ADD ESP,4
4002 emit_opcode(cbuf,0xC4);
4003 emit_d8(cbuf,0x04);
4004 // Carry on here...
4005 %}
4007 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4008 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4010 // Compare the result to see if we need to go to the slow path
4011 emit_opcode(cbuf,0x81); // CMP dst,imm
4012 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4013 emit_d32 (cbuf,0x80000000); // 0x80000000
4015 emit_opcode(cbuf,0x75); // JNE around_slow_call
4016 emit_d8 (cbuf,0x13); // Size of slow_call
4017 // Store xmm to a temp memory
4018 // location and push it onto stack.
4020 emit_opcode(cbuf,0x83); // SUB ESP,4
4021 emit_opcode(cbuf,0xEC);
4022 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4024 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4025 emit_opcode (cbuf, 0x0F );
4026 emit_opcode (cbuf, 0x11 );
4027 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4029 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4030 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4032 emit_opcode(cbuf,0x83); // ADD ESP,4
4033 emit_opcode(cbuf,0xC4);
4034 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4036 // CALL directly to the runtime
4037 cbuf.set_insts_mark();
4038 emit_opcode(cbuf,0xE8); // Call into runtime
4039 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4041 // Carry on here...
4042 %}
4044 enc_class X2D_encoding( regD dst, regX src ) %{
4045 // Allocate a word
4046 emit_opcode(cbuf,0x83); // SUB ESP,4
4047 emit_opcode(cbuf,0xEC);
4048 emit_d8(cbuf,0x04);
4050 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4051 emit_opcode (cbuf, 0x0F );
4052 emit_opcode (cbuf, 0x11 );
4053 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4055 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4056 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4058 emit_opcode(cbuf,0x83); // ADD ESP,4
4059 emit_opcode(cbuf,0xC4);
4060 emit_d8(cbuf,0x04);
4062 // Carry on here...
4063 %}
4065 enc_class AbsXF_encoding(regX dst) %{
4066 address signmask_address=(address)float_signmask_pool;
4067 // andpd:\tANDPS $dst,[signconst]
4068 emit_opcode(cbuf, 0x0F);
4069 emit_opcode(cbuf, 0x54);
4070 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4071 emit_d32(cbuf, (int)signmask_address);
4072 %}
4074 enc_class AbsXD_encoding(regXD dst) %{
4075 address signmask_address=(address)double_signmask_pool;
4076 // andpd:\tANDPD $dst,[signconst]
4077 emit_opcode(cbuf, 0x66);
4078 emit_opcode(cbuf, 0x0F);
4079 emit_opcode(cbuf, 0x54);
4080 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4081 emit_d32(cbuf, (int)signmask_address);
4082 %}
4084 enc_class NegXF_encoding(regX dst) %{
4085 address signmask_address=(address)float_signflip_pool;
4086 // andpd:\tXORPS $dst,[signconst]
4087 emit_opcode(cbuf, 0x0F);
4088 emit_opcode(cbuf, 0x57);
4089 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4090 emit_d32(cbuf, (int)signmask_address);
4091 %}
4093 enc_class NegXD_encoding(regXD dst) %{
4094 address signmask_address=(address)double_signflip_pool;
4095 // andpd:\tXORPD $dst,[signconst]
4096 emit_opcode(cbuf, 0x66);
4097 emit_opcode(cbuf, 0x0F);
4098 emit_opcode(cbuf, 0x57);
4099 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4100 emit_d32(cbuf, (int)signmask_address);
4101 %}
4103 enc_class FMul_ST_reg( eRegF src1 ) %{
4104 // Operand was loaded from memory into fp ST (stack top)
4105 // FMUL ST,$src /* D8 C8+i */
4106 emit_opcode(cbuf, 0xD8);
4107 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4108 %}
4110 enc_class FAdd_ST_reg( eRegF src2 ) %{
4111 // FADDP ST,src2 /* D8 C0+i */
4112 emit_opcode(cbuf, 0xD8);
4113 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4114 //could use FADDP src2,fpST /* DE C0+i */
4115 %}
4117 enc_class FAddP_reg_ST( eRegF src2 ) %{
4118 // FADDP src2,ST /* DE C0+i */
4119 emit_opcode(cbuf, 0xDE);
4120 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4121 %}
4123 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4124 // Operand has been loaded into fp ST (stack top)
4125 // FSUB ST,$src1
4126 emit_opcode(cbuf, 0xD8);
4127 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4129 // FDIV
4130 emit_opcode(cbuf, 0xD8);
4131 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4132 %}
4134 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4135 // Operand was loaded from memory into fp ST (stack top)
4136 // FADD ST,$src /* D8 C0+i */
4137 emit_opcode(cbuf, 0xD8);
4138 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4140 // FMUL ST,src2 /* D8 C*+i */
4141 emit_opcode(cbuf, 0xD8);
4142 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4143 %}
4146 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4147 // Operand was loaded from memory into fp ST (stack top)
4148 // FADD ST,$src /* D8 C0+i */
4149 emit_opcode(cbuf, 0xD8);
4150 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4152 // FMULP src2,ST /* DE C8+i */
4153 emit_opcode(cbuf, 0xDE);
4154 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4155 %}
4157 // Atomically load the volatile long
4158 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4159 emit_opcode(cbuf,0xDF);
4160 int rm_byte_opcode = 0x05;
4161 int base = $mem$$base;
4162 int index = $mem$$index;
4163 int scale = $mem$$scale;
4164 int displace = $mem$$disp;
4165 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4166 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4167 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4168 %}
4170 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4171 { // Atomic long load
4172 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4173 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4174 emit_opcode(cbuf,0x0F);
4175 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4176 int base = $mem$$base;
4177 int index = $mem$$index;
4178 int scale = $mem$$scale;
4179 int displace = $mem$$disp;
4180 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4181 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4182 }
4183 { // MOVSD $dst,$tmp ! atomic long store
4184 emit_opcode(cbuf,0xF2);
4185 emit_opcode(cbuf,0x0F);
4186 emit_opcode(cbuf,0x11);
4187 int base = $dst$$base;
4188 int index = $dst$$index;
4189 int scale = $dst$$scale;
4190 int displace = $dst$$disp;
4191 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4192 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4193 }
4194 %}
4196 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4197 { // Atomic long load
4198 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4199 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4200 emit_opcode(cbuf,0x0F);
4201 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4202 int base = $mem$$base;
4203 int index = $mem$$index;
4204 int scale = $mem$$scale;
4205 int displace = $mem$$disp;
4206 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4207 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4208 }
4209 { // MOVD $dst.lo,$tmp
4210 emit_opcode(cbuf,0x66);
4211 emit_opcode(cbuf,0x0F);
4212 emit_opcode(cbuf,0x7E);
4213 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4214 }
4215 { // PSRLQ $tmp,32
4216 emit_opcode(cbuf,0x66);
4217 emit_opcode(cbuf,0x0F);
4218 emit_opcode(cbuf,0x73);
4219 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4220 emit_d8(cbuf, 0x20);
4221 }
4222 { // MOVD $dst.hi,$tmp
4223 emit_opcode(cbuf,0x66);
4224 emit_opcode(cbuf,0x0F);
4225 emit_opcode(cbuf,0x7E);
4226 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4227 }
4228 %}
4230 // Volatile Store Long. Must be atomic, so move it into
4231 // the FP TOS and then do a 64-bit FIST. Has to probe the
4232 // target address before the store (for null-ptr checks)
4233 // so the memory operand is used twice in the encoding.
4234 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4235 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4236 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
4237 emit_opcode(cbuf,0xDF);
4238 int rm_byte_opcode = 0x07;
4239 int base = $mem$$base;
4240 int index = $mem$$index;
4241 int scale = $mem$$scale;
4242 int displace = $mem$$disp;
4243 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4244 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4245 %}
4247 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4248 { // Atomic long load
4249 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4250 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4251 emit_opcode(cbuf,0x0F);
4252 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4253 int base = $src$$base;
4254 int index = $src$$index;
4255 int scale = $src$$scale;
4256 int displace = $src$$disp;
4257 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4258 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4259 }
4260 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop
4261 { // MOVSD $mem,$tmp ! atomic long store
4262 emit_opcode(cbuf,0xF2);
4263 emit_opcode(cbuf,0x0F);
4264 emit_opcode(cbuf,0x11);
4265 int base = $mem$$base;
4266 int index = $mem$$index;
4267 int scale = $mem$$scale;
4268 int displace = $mem$$disp;
4269 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4270 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4271 }
4272 %}
4274 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4275 { // MOVD $tmp,$src.lo
4276 emit_opcode(cbuf,0x66);
4277 emit_opcode(cbuf,0x0F);
4278 emit_opcode(cbuf,0x6E);
4279 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4280 }
4281 { // MOVD $tmp2,$src.hi
4282 emit_opcode(cbuf,0x66);
4283 emit_opcode(cbuf,0x0F);
4284 emit_opcode(cbuf,0x6E);
4285 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4286 }
4287 { // PUNPCKLDQ $tmp,$tmp2
4288 emit_opcode(cbuf,0x66);
4289 emit_opcode(cbuf,0x0F);
4290 emit_opcode(cbuf,0x62);
4291 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4292 }
4293 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop
4294 { // MOVSD $mem,$tmp ! atomic long store
4295 emit_opcode(cbuf,0xF2);
4296 emit_opcode(cbuf,0x0F);
4297 emit_opcode(cbuf,0x11);
4298 int base = $mem$$base;
4299 int index = $mem$$index;
4300 int scale = $mem$$scale;
4301 int displace = $mem$$disp;
4302 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4303 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4304 }
4305 %}
4307 // Safepoint Poll. This polls the safepoint page, and causes an
4308 // exception if it is not readable. Unfortunately, it kills the condition code
4309 // in the process
4310 // We current use TESTL [spp],EDI
4311 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4313 enc_class Safepoint_Poll() %{
4314 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
4315 emit_opcode(cbuf,0x85);
4316 emit_rm (cbuf, 0x0, 0x7, 0x5);
4317 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4318 %}
4319 %}
4322 //----------FRAME--------------------------------------------------------------
4323 // Definition of frame structure and management information.
4324 //
4325 // S T A C K L A Y O U T Allocators stack-slot number
4326 // | (to get allocators register number
4327 // G Owned by | | v add OptoReg::stack0())
4328 // r CALLER | |
4329 // o | +--------+ pad to even-align allocators stack-slot
4330 // w V | pad0 | numbers; owned by CALLER
4331 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4332 // h ^ | in | 5
4333 // | | args | 4 Holes in incoming args owned by SELF
4334 // | | | | 3
4335 // | | +--------+
4336 // V | | old out| Empty on Intel, window on Sparc
4337 // | old |preserve| Must be even aligned.
4338 // | SP-+--------+----> Matcher::_old_SP, even aligned
4339 // | | in | 3 area for Intel ret address
4340 // Owned by |preserve| Empty on Sparc.
4341 // SELF +--------+
4342 // | | pad2 | 2 pad to align old SP
4343 // | +--------+ 1
4344 // | | locks | 0
4345 // | +--------+----> OptoReg::stack0(), even aligned
4346 // | | pad1 | 11 pad to align new SP
4347 // | +--------+
4348 // | | | 10
4349 // | | spills | 9 spills
4350 // V | | 8 (pad0 slot for callee)
4351 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4352 // ^ | out | 7
4353 // | | args | 6 Holes in outgoing args owned by CALLEE
4354 // Owned by +--------+
4355 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4356 // | new |preserve| Must be even-aligned.
4357 // | SP-+--------+----> Matcher::_new_SP, even aligned
4358 // | | |
4359 //
4360 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4361 // known from SELF's arguments and the Java calling convention.
4362 // Region 6-7 is determined per call site.
4363 // Note 2: If the calling convention leaves holes in the incoming argument
4364 // area, those holes are owned by SELF. Holes in the outgoing area
4365 // are owned by the CALLEE. Holes should not be nessecary in the
4366 // incoming area, as the Java calling convention is completely under
4367 // the control of the AD file. Doubles can be sorted and packed to
4368 // avoid holes. Holes in the outgoing arguments may be nessecary for
4369 // varargs C calling conventions.
4370 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4371 // even aligned with pad0 as needed.
4372 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4373 // region 6-11 is even aligned; it may be padded out more so that
4374 // the region from SP to FP meets the minimum stack alignment.
4376 frame %{
4377 // What direction does stack grow in (assumed to be same for C & Java)
4378 stack_direction(TOWARDS_LOW);
4380 // These three registers define part of the calling convention
4381 // between compiled code and the interpreter.
4382 inline_cache_reg(EAX); // Inline Cache Register
4383 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4385 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4386 cisc_spilling_operand_name(indOffset32);
4388 // Number of stack slots consumed by locking an object
4389 sync_stack_slots(1);
4391 // Compiled code's Frame Pointer
4392 frame_pointer(ESP);
4393 // Interpreter stores its frame pointer in a register which is
4394 // stored to the stack by I2CAdaptors.
4395 // I2CAdaptors convert from interpreted java to compiled java.
4396 interpreter_frame_pointer(EBP);
4398 // Stack alignment requirement
4399 // Alignment size in bytes (128-bit -> 16 bytes)
4400 stack_alignment(StackAlignmentInBytes);
4402 // Number of stack slots between incoming argument block and the start of
4403 // a new frame. The PROLOG must add this many slots to the stack. The
4404 // EPILOG must remove this many slots. Intel needs one slot for
4405 // return address and one for rbp, (must save rbp)
4406 in_preserve_stack_slots(2+VerifyStackAtCalls);
4408 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4409 // for calls to C. Supports the var-args backing area for register parms.
4410 varargs_C_out_slots_killed(0);
4412 // The after-PROLOG location of the return address. Location of
4413 // return address specifies a type (REG or STACK) and a number
4414 // representing the register number (i.e. - use a register name) or
4415 // stack slot.
4416 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4417 // Otherwise, it is above the locks and verification slot and alignment word
4418 return_addr(STACK - 1 +
4419 round_to(1+VerifyStackAtCalls+
4420 Compile::current()->fixed_slots(),
4421 (StackAlignmentInBytes/wordSize)));
4423 // Body of function which returns an integer array locating
4424 // arguments either in registers or in stack slots. Passed an array
4425 // of ideal registers called "sig" and a "length" count. Stack-slot
4426 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4427 // arguments for a CALLEE. Incoming stack arguments are
4428 // automatically biased by the preserve_stack_slots field above.
4429 calling_convention %{
4430 // No difference between ingoing/outgoing just pass false
4431 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4432 %}
4435 // Body of function which returns an integer array locating
4436 // arguments either in registers or in stack slots. Passed an array
4437 // of ideal registers called "sig" and a "length" count. Stack-slot
4438 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4439 // arguments for a CALLEE. Incoming stack arguments are
4440 // automatically biased by the preserve_stack_slots field above.
4441 c_calling_convention %{
4442 // This is obviously always outgoing
4443 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4444 %}
4446 // Location of C & interpreter return values
4447 c_return_value %{
4448 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4449 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4450 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4452 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4453 // that C functions return float and double results in XMM0.
4454 if( ideal_reg == Op_RegD && UseSSE>=2 )
4455 return OptoRegPair(XMM0b_num,XMM0a_num);
4456 if( ideal_reg == Op_RegF && UseSSE>=2 )
4457 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4459 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4460 %}
4462 // Location of return values
4463 return_value %{
4464 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4465 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4466 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4467 if( ideal_reg == Op_RegD && UseSSE>=2 )
4468 return OptoRegPair(XMM0b_num,XMM0a_num);
4469 if( ideal_reg == Op_RegF && UseSSE>=1 )
4470 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4471 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4472 %}
4474 %}
4476 //----------ATTRIBUTES---------------------------------------------------------
4477 //----------Operand Attributes-------------------------------------------------
4478 op_attrib op_cost(0); // Required cost attribute
4480 //----------Instruction Attributes---------------------------------------------
4481 ins_attrib ins_cost(100); // Required cost attribute
4482 ins_attrib ins_size(8); // Required size attribute (in bits)
4483 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4484 // non-matching short branch variant of some
4485 // long branch?
4486 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4487 // specifies the alignment that some part of the instruction (not
4488 // necessarily the start) requires. If > 1, a compute_padding()
4489 // function must be provided for the instruction
4491 //----------OPERANDS-----------------------------------------------------------
4492 // Operand definitions must precede instruction definitions for correct parsing
4493 // in the ADLC because operands constitute user defined types which are used in
4494 // instruction definitions.
4496 //----------Simple Operands----------------------------------------------------
4497 // Immediate Operands
4498 // Integer Immediate
4499 operand immI() %{
4500 match(ConI);
4502 op_cost(10);
4503 format %{ %}
4504 interface(CONST_INTER);
4505 %}
4507 // Constant for test vs zero
4508 operand immI0() %{
4509 predicate(n->get_int() == 0);
4510 match(ConI);
4512 op_cost(0);
4513 format %{ %}
4514 interface(CONST_INTER);
4515 %}
4517 // Constant for increment
4518 operand immI1() %{
4519 predicate(n->get_int() == 1);
4520 match(ConI);
4522 op_cost(0);
4523 format %{ %}
4524 interface(CONST_INTER);
4525 %}
4527 // Constant for decrement
4528 operand immI_M1() %{
4529 predicate(n->get_int() == -1);
4530 match(ConI);
4532 op_cost(0);
4533 format %{ %}
4534 interface(CONST_INTER);
4535 %}
4537 // Valid scale values for addressing modes
4538 operand immI2() %{
4539 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4540 match(ConI);
4542 format %{ %}
4543 interface(CONST_INTER);
4544 %}
4546 operand immI8() %{
4547 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4548 match(ConI);
4550 op_cost(5);
4551 format %{ %}
4552 interface(CONST_INTER);
4553 %}
4555 operand immI16() %{
4556 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4557 match(ConI);
4559 op_cost(10);
4560 format %{ %}
4561 interface(CONST_INTER);
4562 %}
4564 // Constant for long shifts
4565 operand immI_32() %{
4566 predicate( n->get_int() == 32 );
4567 match(ConI);
4569 op_cost(0);
4570 format %{ %}
4571 interface(CONST_INTER);
4572 %}
4574 operand immI_1_31() %{
4575 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4576 match(ConI);
4578 op_cost(0);
4579 format %{ %}
4580 interface(CONST_INTER);
4581 %}
4583 operand immI_32_63() %{
4584 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4585 match(ConI);
4586 op_cost(0);
4588 format %{ %}
4589 interface(CONST_INTER);
4590 %}
4592 operand immI_1() %{
4593 predicate( n->get_int() == 1 );
4594 match(ConI);
4596 op_cost(0);
4597 format %{ %}
4598 interface(CONST_INTER);
4599 %}
4601 operand immI_2() %{
4602 predicate( n->get_int() == 2 );
4603 match(ConI);
4605 op_cost(0);
4606 format %{ %}
4607 interface(CONST_INTER);
4608 %}
4610 operand immI_3() %{
4611 predicate( n->get_int() == 3 );
4612 match(ConI);
4614 op_cost(0);
4615 format %{ %}
4616 interface(CONST_INTER);
4617 %}
4619 // Pointer Immediate
4620 operand immP() %{
4621 match(ConP);
4623 op_cost(10);
4624 format %{ %}
4625 interface(CONST_INTER);
4626 %}
4628 // NULL Pointer Immediate
4629 operand immP0() %{
4630 predicate( n->get_ptr() == 0 );
4631 match(ConP);
4632 op_cost(0);
4634 format %{ %}
4635 interface(CONST_INTER);
4636 %}
4638 // Long Immediate
4639 operand immL() %{
4640 match(ConL);
4642 op_cost(20);
4643 format %{ %}
4644 interface(CONST_INTER);
4645 %}
4647 // Long Immediate zero
4648 operand immL0() %{
4649 predicate( n->get_long() == 0L );
4650 match(ConL);
4651 op_cost(0);
4653 format %{ %}
4654 interface(CONST_INTER);
4655 %}
4657 // Long Immediate zero
4658 operand immL_M1() %{
4659 predicate( n->get_long() == -1L );
4660 match(ConL);
4661 op_cost(0);
4663 format %{ %}
4664 interface(CONST_INTER);
4665 %}
4667 // Long immediate from 0 to 127.
4668 // Used for a shorter form of long mul by 10.
4669 operand immL_127() %{
4670 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4671 match(ConL);
4672 op_cost(0);
4674 format %{ %}
4675 interface(CONST_INTER);
4676 %}
4678 // Long Immediate: low 32-bit mask
4679 operand immL_32bits() %{
4680 predicate(n->get_long() == 0xFFFFFFFFL);
4681 match(ConL);
4682 op_cost(0);
4684 format %{ %}
4685 interface(CONST_INTER);
4686 %}
4688 // Long Immediate: low 32-bit mask
4689 operand immL32() %{
4690 predicate(n->get_long() == (int)(n->get_long()));
4691 match(ConL);
4692 op_cost(20);
4694 format %{ %}
4695 interface(CONST_INTER);
4696 %}
4698 //Double Immediate zero
4699 operand immD0() %{
4700 // Do additional (and counter-intuitive) test against NaN to work around VC++
4701 // bug that generates code such that NaNs compare equal to 0.0
4702 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4703 match(ConD);
4705 op_cost(5);
4706 format %{ %}
4707 interface(CONST_INTER);
4708 %}
4710 // Double Immediate one
4711 operand immD1() %{
4712 predicate( UseSSE<=1 && n->getd() == 1.0 );
4713 match(ConD);
4715 op_cost(5);
4716 format %{ %}
4717 interface(CONST_INTER);
4718 %}
4720 // Double Immediate
4721 operand immD() %{
4722 predicate(UseSSE<=1);
4723 match(ConD);
4725 op_cost(5);
4726 format %{ %}
4727 interface(CONST_INTER);
4728 %}
4730 operand immXD() %{
4731 predicate(UseSSE>=2);
4732 match(ConD);
4734 op_cost(5);
4735 format %{ %}
4736 interface(CONST_INTER);
4737 %}
4739 // Double Immediate zero
4740 operand immXD0() %{
4741 // Do additional (and counter-intuitive) test against NaN to work around VC++
4742 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4743 // compare equal to -0.0.
4744 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4745 match(ConD);
4747 format %{ %}
4748 interface(CONST_INTER);
4749 %}
4751 // Float Immediate zero
4752 operand immF0() %{
4753 predicate(UseSSE == 0 && n->getf() == 0.0F);
4754 match(ConF);
4756 op_cost(5);
4757 format %{ %}
4758 interface(CONST_INTER);
4759 %}
4761 // Float Immediate one
4762 operand immF1() %{
4763 predicate(UseSSE == 0 && n->getf() == 1.0F);
4764 match(ConF);
4766 op_cost(5);
4767 format %{ %}
4768 interface(CONST_INTER);
4769 %}
4771 // Float Immediate
4772 operand immF() %{
4773 predicate( UseSSE == 0 );
4774 match(ConF);
4776 op_cost(5);
4777 format %{ %}
4778 interface(CONST_INTER);
4779 %}
4781 // Float Immediate
4782 operand immXF() %{
4783 predicate(UseSSE >= 1);
4784 match(ConF);
4786 op_cost(5);
4787 format %{ %}
4788 interface(CONST_INTER);
4789 %}
4791 // Float Immediate zero. Zero and not -0.0
4792 operand immXF0() %{
4793 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4794 match(ConF);
4796 op_cost(5);
4797 format %{ %}
4798 interface(CONST_INTER);
4799 %}
4801 // Immediates for special shifts (sign extend)
4803 // Constants for increment
4804 operand immI_16() %{
4805 predicate( n->get_int() == 16 );
4806 match(ConI);
4808 format %{ %}
4809 interface(CONST_INTER);
4810 %}
4812 operand immI_24() %{
4813 predicate( n->get_int() == 24 );
4814 match(ConI);
4816 format %{ %}
4817 interface(CONST_INTER);
4818 %}
4820 // Constant for byte-wide masking
4821 operand immI_255() %{
4822 predicate( n->get_int() == 255 );
4823 match(ConI);
4825 format %{ %}
4826 interface(CONST_INTER);
4827 %}
4829 // Constant for short-wide masking
4830 operand immI_65535() %{
4831 predicate(n->get_int() == 65535);
4832 match(ConI);
4834 format %{ %}
4835 interface(CONST_INTER);
4836 %}
4838 // Register Operands
4839 // Integer Register
4840 operand eRegI() %{
4841 constraint(ALLOC_IN_RC(e_reg));
4842 match(RegI);
4843 match(xRegI);
4844 match(eAXRegI);
4845 match(eBXRegI);
4846 match(eCXRegI);
4847 match(eDXRegI);
4848 match(eDIRegI);
4849 match(eSIRegI);
4851 format %{ %}
4852 interface(REG_INTER);
4853 %}
4855 // Subset of Integer Register
4856 operand xRegI(eRegI reg) %{
4857 constraint(ALLOC_IN_RC(x_reg));
4858 match(reg);
4859 match(eAXRegI);
4860 match(eBXRegI);
4861 match(eCXRegI);
4862 match(eDXRegI);
4864 format %{ %}
4865 interface(REG_INTER);
4866 %}
4868 // Special Registers
4869 operand eAXRegI(xRegI reg) %{
4870 constraint(ALLOC_IN_RC(eax_reg));
4871 match(reg);
4872 match(eRegI);
4874 format %{ "EAX" %}
4875 interface(REG_INTER);
4876 %}
4878 // Special Registers
4879 operand eBXRegI(xRegI reg) %{
4880 constraint(ALLOC_IN_RC(ebx_reg));
4881 match(reg);
4882 match(eRegI);
4884 format %{ "EBX" %}
4885 interface(REG_INTER);
4886 %}
4888 operand eCXRegI(xRegI reg) %{
4889 constraint(ALLOC_IN_RC(ecx_reg));
4890 match(reg);
4891 match(eRegI);
4893 format %{ "ECX" %}
4894 interface(REG_INTER);
4895 %}
4897 operand eDXRegI(xRegI reg) %{
4898 constraint(ALLOC_IN_RC(edx_reg));
4899 match(reg);
4900 match(eRegI);
4902 format %{ "EDX" %}
4903 interface(REG_INTER);
4904 %}
4906 operand eDIRegI(xRegI reg) %{
4907 constraint(ALLOC_IN_RC(edi_reg));
4908 match(reg);
4909 match(eRegI);
4911 format %{ "EDI" %}
4912 interface(REG_INTER);
4913 %}
4915 operand naxRegI() %{
4916 constraint(ALLOC_IN_RC(nax_reg));
4917 match(RegI);
4918 match(eCXRegI);
4919 match(eDXRegI);
4920 match(eSIRegI);
4921 match(eDIRegI);
4923 format %{ %}
4924 interface(REG_INTER);
4925 %}
4927 operand nadxRegI() %{
4928 constraint(ALLOC_IN_RC(nadx_reg));
4929 match(RegI);
4930 match(eBXRegI);
4931 match(eCXRegI);
4932 match(eSIRegI);
4933 match(eDIRegI);
4935 format %{ %}
4936 interface(REG_INTER);
4937 %}
4939 operand ncxRegI() %{
4940 constraint(ALLOC_IN_RC(ncx_reg));
4941 match(RegI);
4942 match(eAXRegI);
4943 match(eDXRegI);
4944 match(eSIRegI);
4945 match(eDIRegI);
4947 format %{ %}
4948 interface(REG_INTER);
4949 %}
4951 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4952 // //
4953 operand eSIRegI(xRegI reg) %{
4954 constraint(ALLOC_IN_RC(esi_reg));
4955 match(reg);
4956 match(eRegI);
4958 format %{ "ESI" %}
4959 interface(REG_INTER);
4960 %}
4962 // Pointer Register
4963 operand anyRegP() %{
4964 constraint(ALLOC_IN_RC(any_reg));
4965 match(RegP);
4966 match(eAXRegP);
4967 match(eBXRegP);
4968 match(eCXRegP);
4969 match(eDIRegP);
4970 match(eRegP);
4972 format %{ %}
4973 interface(REG_INTER);
4974 %}
4976 operand eRegP() %{
4977 constraint(ALLOC_IN_RC(e_reg));
4978 match(RegP);
4979 match(eAXRegP);
4980 match(eBXRegP);
4981 match(eCXRegP);
4982 match(eDIRegP);
4984 format %{ %}
4985 interface(REG_INTER);
4986 %}
4988 // On windows95, EBP is not safe to use for implicit null tests.
4989 operand eRegP_no_EBP() %{
4990 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4991 match(RegP);
4992 match(eAXRegP);
4993 match(eBXRegP);
4994 match(eCXRegP);
4995 match(eDIRegP);
4997 op_cost(100);
4998 format %{ %}
4999 interface(REG_INTER);
5000 %}
5002 operand naxRegP() %{
5003 constraint(ALLOC_IN_RC(nax_reg));
5004 match(RegP);
5005 match(eBXRegP);
5006 match(eDXRegP);
5007 match(eCXRegP);
5008 match(eSIRegP);
5009 match(eDIRegP);
5011 format %{ %}
5012 interface(REG_INTER);
5013 %}
5015 operand nabxRegP() %{
5016 constraint(ALLOC_IN_RC(nabx_reg));
5017 match(RegP);
5018 match(eCXRegP);
5019 match(eDXRegP);
5020 match(eSIRegP);
5021 match(eDIRegP);
5023 format %{ %}
5024 interface(REG_INTER);
5025 %}
5027 operand pRegP() %{
5028 constraint(ALLOC_IN_RC(p_reg));
5029 match(RegP);
5030 match(eBXRegP);
5031 match(eDXRegP);
5032 match(eSIRegP);
5033 match(eDIRegP);
5035 format %{ %}
5036 interface(REG_INTER);
5037 %}
5039 // Special Registers
5040 // Return a pointer value
5041 operand eAXRegP(eRegP reg) %{
5042 constraint(ALLOC_IN_RC(eax_reg));
5043 match(reg);
5044 format %{ "EAX" %}
5045 interface(REG_INTER);
5046 %}
5048 // Used in AtomicAdd
5049 operand eBXRegP(eRegP reg) %{
5050 constraint(ALLOC_IN_RC(ebx_reg));
5051 match(reg);
5052 format %{ "EBX" %}
5053 interface(REG_INTER);
5054 %}
5056 // Tail-call (interprocedural jump) to interpreter
5057 operand eCXRegP(eRegP reg) %{
5058 constraint(ALLOC_IN_RC(ecx_reg));
5059 match(reg);
5060 format %{ "ECX" %}
5061 interface(REG_INTER);
5062 %}
5064 operand eSIRegP(eRegP reg) %{
5065 constraint(ALLOC_IN_RC(esi_reg));
5066 match(reg);
5067 format %{ "ESI" %}
5068 interface(REG_INTER);
5069 %}
5071 // Used in rep stosw
5072 operand eDIRegP(eRegP reg) %{
5073 constraint(ALLOC_IN_RC(edi_reg));
5074 match(reg);
5075 format %{ "EDI" %}
5076 interface(REG_INTER);
5077 %}
5079 operand eBPRegP() %{
5080 constraint(ALLOC_IN_RC(ebp_reg));
5081 match(RegP);
5082 format %{ "EBP" %}
5083 interface(REG_INTER);
5084 %}
5086 operand eRegL() %{
5087 constraint(ALLOC_IN_RC(long_reg));
5088 match(RegL);
5089 match(eADXRegL);
5091 format %{ %}
5092 interface(REG_INTER);
5093 %}
5095 operand eADXRegL( eRegL reg ) %{
5096 constraint(ALLOC_IN_RC(eadx_reg));
5097 match(reg);
5099 format %{ "EDX:EAX" %}
5100 interface(REG_INTER);
5101 %}
5103 operand eBCXRegL( eRegL reg ) %{
5104 constraint(ALLOC_IN_RC(ebcx_reg));
5105 match(reg);
5107 format %{ "EBX:ECX" %}
5108 interface(REG_INTER);
5109 %}
5111 // Special case for integer high multiply
5112 operand eADXRegL_low_only() %{
5113 constraint(ALLOC_IN_RC(eadx_reg));
5114 match(RegL);
5116 format %{ "EAX" %}
5117 interface(REG_INTER);
5118 %}
5120 // Flags register, used as output of compare instructions
5121 operand eFlagsReg() %{
5122 constraint(ALLOC_IN_RC(int_flags));
5123 match(RegFlags);
5125 format %{ "EFLAGS" %}
5126 interface(REG_INTER);
5127 %}
5129 // Flags register, used as output of FLOATING POINT compare instructions
5130 operand eFlagsRegU() %{
5131 constraint(ALLOC_IN_RC(int_flags));
5132 match(RegFlags);
5134 format %{ "EFLAGS_U" %}
5135 interface(REG_INTER);
5136 %}
5138 operand eFlagsRegUCF() %{
5139 constraint(ALLOC_IN_RC(int_flags));
5140 match(RegFlags);
5141 predicate(false);
5143 format %{ "EFLAGS_U_CF" %}
5144 interface(REG_INTER);
5145 %}
5147 // Condition Code Register used by long compare
5148 operand flagsReg_long_LTGE() %{
5149 constraint(ALLOC_IN_RC(int_flags));
5150 match(RegFlags);
5151 format %{ "FLAGS_LTGE" %}
5152 interface(REG_INTER);
5153 %}
5154 operand flagsReg_long_EQNE() %{
5155 constraint(ALLOC_IN_RC(int_flags));
5156 match(RegFlags);
5157 format %{ "FLAGS_EQNE" %}
5158 interface(REG_INTER);
5159 %}
5160 operand flagsReg_long_LEGT() %{
5161 constraint(ALLOC_IN_RC(int_flags));
5162 match(RegFlags);
5163 format %{ "FLAGS_LEGT" %}
5164 interface(REG_INTER);
5165 %}
5167 // Float register operands
5168 operand regD() %{
5169 predicate( UseSSE < 2 );
5170 constraint(ALLOC_IN_RC(dbl_reg));
5171 match(RegD);
5172 match(regDPR1);
5173 match(regDPR2);
5174 format %{ %}
5175 interface(REG_INTER);
5176 %}
5178 operand regDPR1(regD reg) %{
5179 predicate( UseSSE < 2 );
5180 constraint(ALLOC_IN_RC(dbl_reg0));
5181 match(reg);
5182 format %{ "FPR1" %}
5183 interface(REG_INTER);
5184 %}
5186 operand regDPR2(regD reg) %{
5187 predicate( UseSSE < 2 );
5188 constraint(ALLOC_IN_RC(dbl_reg1));
5189 match(reg);
5190 format %{ "FPR2" %}
5191 interface(REG_INTER);
5192 %}
5194 operand regnotDPR1(regD reg) %{
5195 predicate( UseSSE < 2 );
5196 constraint(ALLOC_IN_RC(dbl_notreg0));
5197 match(reg);
5198 format %{ %}
5199 interface(REG_INTER);
5200 %}
5202 // XMM Double register operands
5203 operand regXD() %{
5204 predicate( UseSSE>=2 );
5205 constraint(ALLOC_IN_RC(xdb_reg));
5206 match(RegD);
5207 match(regXD6);
5208 match(regXD7);
5209 format %{ %}
5210 interface(REG_INTER);
5211 %}
5213 // XMM6 double register operands
5214 operand regXD6(regXD reg) %{
5215 predicate( UseSSE>=2 );
5216 constraint(ALLOC_IN_RC(xdb_reg6));
5217 match(reg);
5218 format %{ "XMM6" %}
5219 interface(REG_INTER);
5220 %}
5222 // XMM7 double register operands
5223 operand regXD7(regXD reg) %{
5224 predicate( UseSSE>=2 );
5225 constraint(ALLOC_IN_RC(xdb_reg7));
5226 match(reg);
5227 format %{ "XMM7" %}
5228 interface(REG_INTER);
5229 %}
5231 // Float register operands
5232 operand regF() %{
5233 predicate( UseSSE < 2 );
5234 constraint(ALLOC_IN_RC(flt_reg));
5235 match(RegF);
5236 match(regFPR1);
5237 format %{ %}
5238 interface(REG_INTER);
5239 %}
5241 // Float register operands
5242 operand regFPR1(regF reg) %{
5243 predicate( UseSSE < 2 );
5244 constraint(ALLOC_IN_RC(flt_reg0));
5245 match(reg);
5246 format %{ "FPR1" %}
5247 interface(REG_INTER);
5248 %}
5250 // XMM register operands
5251 operand regX() %{
5252 predicate( UseSSE>=1 );
5253 constraint(ALLOC_IN_RC(xmm_reg));
5254 match(RegF);
5255 format %{ %}
5256 interface(REG_INTER);
5257 %}
5260 //----------Memory Operands----------------------------------------------------
5261 // Direct Memory Operand
5262 operand direct(immP addr) %{
5263 match(addr);
5265 format %{ "[$addr]" %}
5266 interface(MEMORY_INTER) %{
5267 base(0xFFFFFFFF);
5268 index(0x4);
5269 scale(0x0);
5270 disp($addr);
5271 %}
5272 %}
5274 // Indirect Memory Operand
5275 operand indirect(eRegP reg) %{
5276 constraint(ALLOC_IN_RC(e_reg));
5277 match(reg);
5279 format %{ "[$reg]" %}
5280 interface(MEMORY_INTER) %{
5281 base($reg);
5282 index(0x4);
5283 scale(0x0);
5284 disp(0x0);
5285 %}
5286 %}
5288 // Indirect Memory Plus Short Offset Operand
5289 operand indOffset8(eRegP reg, immI8 off) %{
5290 match(AddP reg off);
5292 format %{ "[$reg + $off]" %}
5293 interface(MEMORY_INTER) %{
5294 base($reg);
5295 index(0x4);
5296 scale(0x0);
5297 disp($off);
5298 %}
5299 %}
5301 // Indirect Memory Plus Long Offset Operand
5302 operand indOffset32(eRegP reg, immI off) %{
5303 match(AddP reg off);
5305 format %{ "[$reg + $off]" %}
5306 interface(MEMORY_INTER) %{
5307 base($reg);
5308 index(0x4);
5309 scale(0x0);
5310 disp($off);
5311 %}
5312 %}
5314 // Indirect Memory Plus Long Offset Operand
5315 operand indOffset32X(eRegI reg, immP off) %{
5316 match(AddP off reg);
5318 format %{ "[$reg + $off]" %}
5319 interface(MEMORY_INTER) %{
5320 base($reg);
5321 index(0x4);
5322 scale(0x0);
5323 disp($off);
5324 %}
5325 %}
5327 // Indirect Memory Plus Index Register Plus Offset Operand
5328 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5329 match(AddP (AddP reg ireg) off);
5331 op_cost(10);
5332 format %{"[$reg + $off + $ireg]" %}
5333 interface(MEMORY_INTER) %{
5334 base($reg);
5335 index($ireg);
5336 scale(0x0);
5337 disp($off);
5338 %}
5339 %}
5341 // Indirect Memory Plus Index Register Plus Offset Operand
5342 operand indIndex(eRegP reg, eRegI ireg) %{
5343 match(AddP reg ireg);
5345 op_cost(10);
5346 format %{"[$reg + $ireg]" %}
5347 interface(MEMORY_INTER) %{
5348 base($reg);
5349 index($ireg);
5350 scale(0x0);
5351 disp(0x0);
5352 %}
5353 %}
5355 // // -------------------------------------------------------------------------
5356 // // 486 architecture doesn't support "scale * index + offset" with out a base
5357 // // -------------------------------------------------------------------------
5358 // // Scaled Memory Operands
5359 // // Indirect Memory Times Scale Plus Offset Operand
5360 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5361 // match(AddP off (LShiftI ireg scale));
5362 //
5363 // op_cost(10);
5364 // format %{"[$off + $ireg << $scale]" %}
5365 // interface(MEMORY_INTER) %{
5366 // base(0x4);
5367 // index($ireg);
5368 // scale($scale);
5369 // disp($off);
5370 // %}
5371 // %}
5373 // Indirect Memory Times Scale Plus Index Register
5374 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5375 match(AddP reg (LShiftI ireg scale));
5377 op_cost(10);
5378 format %{"[$reg + $ireg << $scale]" %}
5379 interface(MEMORY_INTER) %{
5380 base($reg);
5381 index($ireg);
5382 scale($scale);
5383 disp(0x0);
5384 %}
5385 %}
5387 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5388 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5389 match(AddP (AddP reg (LShiftI ireg scale)) off);
5391 op_cost(10);
5392 format %{"[$reg + $off + $ireg << $scale]" %}
5393 interface(MEMORY_INTER) %{
5394 base($reg);
5395 index($ireg);
5396 scale($scale);
5397 disp($off);
5398 %}
5399 %}
5401 //----------Load Long Memory Operands------------------------------------------
5402 // The load-long idiom will use it's address expression again after loading
5403 // the first word of the long. If the load-long destination overlaps with
5404 // registers used in the addressing expression, the 2nd half will be loaded
5405 // from a clobbered address. Fix this by requiring that load-long use
5406 // address registers that do not overlap with the load-long target.
5408 // load-long support
5409 operand load_long_RegP() %{
5410 constraint(ALLOC_IN_RC(esi_reg));
5411 match(RegP);
5412 match(eSIRegP);
5413 op_cost(100);
5414 format %{ %}
5415 interface(REG_INTER);
5416 %}
5418 // Indirect Memory Operand Long
5419 operand load_long_indirect(load_long_RegP reg) %{
5420 constraint(ALLOC_IN_RC(esi_reg));
5421 match(reg);
5423 format %{ "[$reg]" %}
5424 interface(MEMORY_INTER) %{
5425 base($reg);
5426 index(0x4);
5427 scale(0x0);
5428 disp(0x0);
5429 %}
5430 %}
5432 // Indirect Memory Plus Long Offset Operand
5433 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5434 match(AddP reg off);
5436 format %{ "[$reg + $off]" %}
5437 interface(MEMORY_INTER) %{
5438 base($reg);
5439 index(0x4);
5440 scale(0x0);
5441 disp($off);
5442 %}
5443 %}
5445 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5448 //----------Special Memory Operands--------------------------------------------
5449 // Stack Slot Operand - This operand is used for loading and storing temporary
5450 // values on the stack where a match requires a value to
5451 // flow through memory.
5452 operand stackSlotP(sRegP reg) %{
5453 constraint(ALLOC_IN_RC(stack_slots));
5454 // No match rule because this operand is only generated in matching
5455 format %{ "[$reg]" %}
5456 interface(MEMORY_INTER) %{
5457 base(0x4); // ESP
5458 index(0x4); // No Index
5459 scale(0x0); // No Scale
5460 disp($reg); // Stack Offset
5461 %}
5462 %}
5464 operand stackSlotI(sRegI reg) %{
5465 constraint(ALLOC_IN_RC(stack_slots));
5466 // No match rule because this operand is only generated in matching
5467 format %{ "[$reg]" %}
5468 interface(MEMORY_INTER) %{
5469 base(0x4); // ESP
5470 index(0x4); // No Index
5471 scale(0x0); // No Scale
5472 disp($reg); // Stack Offset
5473 %}
5474 %}
5476 operand stackSlotF(sRegF reg) %{
5477 constraint(ALLOC_IN_RC(stack_slots));
5478 // No match rule because this operand is only generated in matching
5479 format %{ "[$reg]" %}
5480 interface(MEMORY_INTER) %{
5481 base(0x4); // ESP
5482 index(0x4); // No Index
5483 scale(0x0); // No Scale
5484 disp($reg); // Stack Offset
5485 %}
5486 %}
5488 operand stackSlotD(sRegD reg) %{
5489 constraint(ALLOC_IN_RC(stack_slots));
5490 // No match rule because this operand is only generated in matching
5491 format %{ "[$reg]" %}
5492 interface(MEMORY_INTER) %{
5493 base(0x4); // ESP
5494 index(0x4); // No Index
5495 scale(0x0); // No Scale
5496 disp($reg); // Stack Offset
5497 %}
5498 %}
5500 operand stackSlotL(sRegL reg) %{
5501 constraint(ALLOC_IN_RC(stack_slots));
5502 // No match rule because this operand is only generated in matching
5503 format %{ "[$reg]" %}
5504 interface(MEMORY_INTER) %{
5505 base(0x4); // ESP
5506 index(0x4); // No Index
5507 scale(0x0); // No Scale
5508 disp($reg); // Stack Offset
5509 %}
5510 %}
5512 //----------Memory Operands - Win95 Implicit Null Variants----------------
5513 // Indirect Memory Operand
5514 operand indirect_win95_safe(eRegP_no_EBP reg)
5515 %{
5516 constraint(ALLOC_IN_RC(e_reg));
5517 match(reg);
5519 op_cost(100);
5520 format %{ "[$reg]" %}
5521 interface(MEMORY_INTER) %{
5522 base($reg);
5523 index(0x4);
5524 scale(0x0);
5525 disp(0x0);
5526 %}
5527 %}
5529 // Indirect Memory Plus Short Offset Operand
5530 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5531 %{
5532 match(AddP reg off);
5534 op_cost(100);
5535 format %{ "[$reg + $off]" %}
5536 interface(MEMORY_INTER) %{
5537 base($reg);
5538 index(0x4);
5539 scale(0x0);
5540 disp($off);
5541 %}
5542 %}
5544 // Indirect Memory Plus Long Offset Operand
5545 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5546 %{
5547 match(AddP reg off);
5549 op_cost(100);
5550 format %{ "[$reg + $off]" %}
5551 interface(MEMORY_INTER) %{
5552 base($reg);
5553 index(0x4);
5554 scale(0x0);
5555 disp($off);
5556 %}
5557 %}
5559 // Indirect Memory Plus Index Register Plus Offset Operand
5560 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5561 %{
5562 match(AddP (AddP reg ireg) off);
5564 op_cost(100);
5565 format %{"[$reg + $off + $ireg]" %}
5566 interface(MEMORY_INTER) %{
5567 base($reg);
5568 index($ireg);
5569 scale(0x0);
5570 disp($off);
5571 %}
5572 %}
5574 // Indirect Memory Times Scale Plus Index Register
5575 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5576 %{
5577 match(AddP reg (LShiftI ireg scale));
5579 op_cost(100);
5580 format %{"[$reg + $ireg << $scale]" %}
5581 interface(MEMORY_INTER) %{
5582 base($reg);
5583 index($ireg);
5584 scale($scale);
5585 disp(0x0);
5586 %}
5587 %}
5589 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5590 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5591 %{
5592 match(AddP (AddP reg (LShiftI ireg scale)) off);
5594 op_cost(100);
5595 format %{"[$reg + $off + $ireg << $scale]" %}
5596 interface(MEMORY_INTER) %{
5597 base($reg);
5598 index($ireg);
5599 scale($scale);
5600 disp($off);
5601 %}
5602 %}
5604 //----------Conditional Branch Operands----------------------------------------
5605 // Comparison Op - This is the operation of the comparison, and is limited to
5606 // the following set of codes:
5607 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5608 //
5609 // Other attributes of the comparison, such as unsignedness, are specified
5610 // by the comparison instruction that sets a condition code flags register.
5611 // That result is represented by a flags operand whose subtype is appropriate
5612 // to the unsignedness (etc.) of the comparison.
5613 //
5614 // Later, the instruction which matches both the Comparison Op (a Bool) and
5615 // the flags (produced by the Cmp) specifies the coding of the comparison op
5616 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5618 // Comparision Code
5619 operand cmpOp() %{
5620 match(Bool);
5622 format %{ "" %}
5623 interface(COND_INTER) %{
5624 equal(0x4, "e");
5625 not_equal(0x5, "ne");
5626 less(0xC, "l");
5627 greater_equal(0xD, "ge");
5628 less_equal(0xE, "le");
5629 greater(0xF, "g");
5630 %}
5631 %}
5633 // Comparison Code, unsigned compare. Used by FP also, with
5634 // C2 (unordered) turned into GT or LT already. The other bits
5635 // C0 and C3 are turned into Carry & Zero flags.
5636 operand cmpOpU() %{
5637 match(Bool);
5639 format %{ "" %}
5640 interface(COND_INTER) %{
5641 equal(0x4, "e");
5642 not_equal(0x5, "ne");
5643 less(0x2, "b");
5644 greater_equal(0x3, "nb");
5645 less_equal(0x6, "be");
5646 greater(0x7, "nbe");
5647 %}
5648 %}
5650 // Floating comparisons that don't require any fixup for the unordered case
5651 operand cmpOpUCF() %{
5652 match(Bool);
5653 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5654 n->as_Bool()->_test._test == BoolTest::ge ||
5655 n->as_Bool()->_test._test == BoolTest::le ||
5656 n->as_Bool()->_test._test == BoolTest::gt);
5657 format %{ "" %}
5658 interface(COND_INTER) %{
5659 equal(0x4, "e");
5660 not_equal(0x5, "ne");
5661 less(0x2, "b");
5662 greater_equal(0x3, "nb");
5663 less_equal(0x6, "be");
5664 greater(0x7, "nbe");
5665 %}
5666 %}
5669 // Floating comparisons that can be fixed up with extra conditional jumps
5670 operand cmpOpUCF2() %{
5671 match(Bool);
5672 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5673 n->as_Bool()->_test._test == BoolTest::eq);
5674 format %{ "" %}
5675 interface(COND_INTER) %{
5676 equal(0x4, "e");
5677 not_equal(0x5, "ne");
5678 less(0x2, "b");
5679 greater_equal(0x3, "nb");
5680 less_equal(0x6, "be");
5681 greater(0x7, "nbe");
5682 %}
5683 %}
5685 // Comparison Code for FP conditional move
5686 operand cmpOp_fcmov() %{
5687 match(Bool);
5689 format %{ "" %}
5690 interface(COND_INTER) %{
5691 equal (0x0C8);
5692 not_equal (0x1C8);
5693 less (0x0C0);
5694 greater_equal(0x1C0);
5695 less_equal (0x0D0);
5696 greater (0x1D0);
5697 %}
5698 %}
5700 // Comparision Code used in long compares
5701 operand cmpOp_commute() %{
5702 match(Bool);
5704 format %{ "" %}
5705 interface(COND_INTER) %{
5706 equal(0x4, "e");
5707 not_equal(0x5, "ne");
5708 less(0xF, "g");
5709 greater_equal(0xE, "le");
5710 less_equal(0xD, "ge");
5711 greater(0xC, "l");
5712 %}
5713 %}
5715 //----------OPERAND CLASSES----------------------------------------------------
5716 // Operand Classes are groups of operands that are used as to simplify
5717 // instruction definitions by not requiring the AD writer to specify separate
5718 // instructions for every form of operand when the instruction accepts
5719 // multiple operand types with the same basic encoding and format. The classic
5720 // case of this is memory operands.
5722 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5723 indIndex, indIndexScale, indIndexScaleOffset);
5725 // Long memory operations are encoded in 2 instructions and a +4 offset.
5726 // This means some kind of offset is always required and you cannot use
5727 // an oop as the offset (done when working on static globals).
5728 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5729 indIndex, indIndexScale, indIndexScaleOffset);
5732 //----------PIPELINE-----------------------------------------------------------
5733 // Rules which define the behavior of the target architectures pipeline.
5734 pipeline %{
5736 //----------ATTRIBUTES---------------------------------------------------------
5737 attributes %{
5738 variable_size_instructions; // Fixed size instructions
5739 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5740 instruction_unit_size = 1; // An instruction is 1 bytes long
5741 instruction_fetch_unit_size = 16; // The processor fetches one line
5742 instruction_fetch_units = 1; // of 16 bytes
5744 // List of nop instructions
5745 nops( MachNop );
5746 %}
5748 //----------RESOURCES----------------------------------------------------------
5749 // Resources are the functional units available to the machine
5751 // Generic P2/P3 pipeline
5752 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5753 // 3 instructions decoded per cycle.
5754 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5755 // 2 ALU op, only ALU0 handles mul/div instructions.
5756 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5757 MS0, MS1, MEM = MS0 | MS1,
5758 BR, FPU,
5759 ALU0, ALU1, ALU = ALU0 | ALU1 );
5761 //----------PIPELINE DESCRIPTION-----------------------------------------------
5762 // Pipeline Description specifies the stages in the machine's pipeline
5764 // Generic P2/P3 pipeline
5765 pipe_desc(S0, S1, S2, S3, S4, S5);
5767 //----------PIPELINE CLASSES---------------------------------------------------
5768 // Pipeline Classes describe the stages in which input and output are
5769 // referenced by the hardware pipeline.
5771 // Naming convention: ialu or fpu
5772 // Then: _reg
5773 // Then: _reg if there is a 2nd register
5774 // Then: _long if it's a pair of instructions implementing a long
5775 // Then: _fat if it requires the big decoder
5776 // Or: _mem if it requires the big decoder and a memory unit.
5778 // Integer ALU reg operation
5779 pipe_class ialu_reg(eRegI dst) %{
5780 single_instruction;
5781 dst : S4(write);
5782 dst : S3(read);
5783 DECODE : S0; // any decoder
5784 ALU : S3; // any alu
5785 %}
5787 // Long ALU reg operation
5788 pipe_class ialu_reg_long(eRegL dst) %{
5789 instruction_count(2);
5790 dst : S4(write);
5791 dst : S3(read);
5792 DECODE : S0(2); // any 2 decoders
5793 ALU : S3(2); // both alus
5794 %}
5796 // Integer ALU reg operation using big decoder
5797 pipe_class ialu_reg_fat(eRegI dst) %{
5798 single_instruction;
5799 dst : S4(write);
5800 dst : S3(read);
5801 D0 : S0; // big decoder only
5802 ALU : S3; // any alu
5803 %}
5805 // Long ALU reg operation using big decoder
5806 pipe_class ialu_reg_long_fat(eRegL dst) %{
5807 instruction_count(2);
5808 dst : S4(write);
5809 dst : S3(read);
5810 D0 : S0(2); // big decoder only; twice
5811 ALU : S3(2); // any 2 alus
5812 %}
5814 // Integer ALU reg-reg operation
5815 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5816 single_instruction;
5817 dst : S4(write);
5818 src : S3(read);
5819 DECODE : S0; // any decoder
5820 ALU : S3; // any alu
5821 %}
5823 // Long ALU reg-reg operation
5824 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5825 instruction_count(2);
5826 dst : S4(write);
5827 src : S3(read);
5828 DECODE : S0(2); // any 2 decoders
5829 ALU : S3(2); // both alus
5830 %}
5832 // Integer ALU reg-reg operation
5833 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5834 single_instruction;
5835 dst : S4(write);
5836 src : S3(read);
5837 D0 : S0; // big decoder only
5838 ALU : S3; // any alu
5839 %}
5841 // Long ALU reg-reg operation
5842 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5843 instruction_count(2);
5844 dst : S4(write);
5845 src : S3(read);
5846 D0 : S0(2); // big decoder only; twice
5847 ALU : S3(2); // both alus
5848 %}
5850 // Integer ALU reg-mem operation
5851 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5852 single_instruction;
5853 dst : S5(write);
5854 mem : S3(read);
5855 D0 : S0; // big decoder only
5856 ALU : S4; // any alu
5857 MEM : S3; // any mem
5858 %}
5860 // Long ALU reg-mem operation
5861 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5862 instruction_count(2);
5863 dst : S5(write);
5864 mem : S3(read);
5865 D0 : S0(2); // big decoder only; twice
5866 ALU : S4(2); // any 2 alus
5867 MEM : S3(2); // both mems
5868 %}
5870 // Integer mem operation (prefetch)
5871 pipe_class ialu_mem(memory mem)
5872 %{
5873 single_instruction;
5874 mem : S3(read);
5875 D0 : S0; // big decoder only
5876 MEM : S3; // any mem
5877 %}
5879 // Integer Store to Memory
5880 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5881 single_instruction;
5882 mem : S3(read);
5883 src : S5(read);
5884 D0 : S0; // big decoder only
5885 ALU : S4; // any alu
5886 MEM : S3;
5887 %}
5889 // Long Store to Memory
5890 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5891 instruction_count(2);
5892 mem : S3(read);
5893 src : S5(read);
5894 D0 : S0(2); // big decoder only; twice
5895 ALU : S4(2); // any 2 alus
5896 MEM : S3(2); // Both mems
5897 %}
5899 // Integer Store to Memory
5900 pipe_class ialu_mem_imm(memory mem) %{
5901 single_instruction;
5902 mem : S3(read);
5903 D0 : S0; // big decoder only
5904 ALU : S4; // any alu
5905 MEM : S3;
5906 %}
5908 // Integer ALU0 reg-reg operation
5909 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5910 single_instruction;
5911 dst : S4(write);
5912 src : S3(read);
5913 D0 : S0; // Big decoder only
5914 ALU0 : S3; // only alu0
5915 %}
5917 // Integer ALU0 reg-mem operation
5918 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5919 single_instruction;
5920 dst : S5(write);
5921 mem : S3(read);
5922 D0 : S0; // big decoder only
5923 ALU0 : S4; // ALU0 only
5924 MEM : S3; // any mem
5925 %}
5927 // Integer ALU reg-reg operation
5928 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5929 single_instruction;
5930 cr : S4(write);
5931 src1 : S3(read);
5932 src2 : S3(read);
5933 DECODE : S0; // any decoder
5934 ALU : S3; // any alu
5935 %}
5937 // Integer ALU reg-imm operation
5938 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5939 single_instruction;
5940 cr : S4(write);
5941 src1 : S3(read);
5942 DECODE : S0; // any decoder
5943 ALU : S3; // any alu
5944 %}
5946 // Integer ALU reg-mem operation
5947 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5948 single_instruction;
5949 cr : S4(write);
5950 src1 : S3(read);
5951 src2 : S3(read);
5952 D0 : S0; // big decoder only
5953 ALU : S4; // any alu
5954 MEM : S3;
5955 %}
5957 // Conditional move reg-reg
5958 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5959 instruction_count(4);
5960 y : S4(read);
5961 q : S3(read);
5962 p : S3(read);
5963 DECODE : S0(4); // any decoder
5964 %}
5966 // Conditional move reg-reg
5967 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5968 single_instruction;
5969 dst : S4(write);
5970 src : S3(read);
5971 cr : S3(read);
5972 DECODE : S0; // any decoder
5973 %}
5975 // Conditional move reg-mem
5976 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5977 single_instruction;
5978 dst : S4(write);
5979 src : S3(read);
5980 cr : S3(read);
5981 DECODE : S0; // any decoder
5982 MEM : S3;
5983 %}
5985 // Conditional move reg-reg long
5986 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5987 single_instruction;
5988 dst : S4(write);
5989 src : S3(read);
5990 cr : S3(read);
5991 DECODE : S0(2); // any 2 decoders
5992 %}
5994 // Conditional move double reg-reg
5995 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
5996 single_instruction;
5997 dst : S4(write);
5998 src : S3(read);
5999 cr : S3(read);
6000 DECODE : S0; // any decoder
6001 %}
6003 // Float reg-reg operation
6004 pipe_class fpu_reg(regD dst) %{
6005 instruction_count(2);
6006 dst : S3(read);
6007 DECODE : S0(2); // any 2 decoders
6008 FPU : S3;
6009 %}
6011 // Float reg-reg operation
6012 pipe_class fpu_reg_reg(regD dst, regD src) %{
6013 instruction_count(2);
6014 dst : S4(write);
6015 src : S3(read);
6016 DECODE : S0(2); // any 2 decoders
6017 FPU : S3;
6018 %}
6020 // Float reg-reg operation
6021 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6022 instruction_count(3);
6023 dst : S4(write);
6024 src1 : S3(read);
6025 src2 : S3(read);
6026 DECODE : S0(3); // any 3 decoders
6027 FPU : S3(2);
6028 %}
6030 // Float reg-reg operation
6031 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6032 instruction_count(4);
6033 dst : S4(write);
6034 src1 : S3(read);
6035 src2 : S3(read);
6036 src3 : S3(read);
6037 DECODE : S0(4); // any 3 decoders
6038 FPU : S3(2);
6039 %}
6041 // Float reg-reg operation
6042 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6043 instruction_count(4);
6044 dst : S4(write);
6045 src1 : S3(read);
6046 src2 : S3(read);
6047 src3 : S3(read);
6048 DECODE : S1(3); // any 3 decoders
6049 D0 : S0; // Big decoder only
6050 FPU : S3(2);
6051 MEM : S3;
6052 %}
6054 // Float reg-mem operation
6055 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6056 instruction_count(2);
6057 dst : S5(write);
6058 mem : S3(read);
6059 D0 : S0; // big decoder only
6060 DECODE : S1; // any decoder for FPU POP
6061 FPU : S4;
6062 MEM : S3; // any mem
6063 %}
6065 // Float reg-mem operation
6066 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6067 instruction_count(3);
6068 dst : S5(write);
6069 src1 : S3(read);
6070 mem : S3(read);
6071 D0 : S0; // big decoder only
6072 DECODE : S1(2); // any decoder for FPU POP
6073 FPU : S4;
6074 MEM : S3; // any mem
6075 %}
6077 // Float mem-reg operation
6078 pipe_class fpu_mem_reg(memory mem, regD src) %{
6079 instruction_count(2);
6080 src : S5(read);
6081 mem : S3(read);
6082 DECODE : S0; // any decoder for FPU PUSH
6083 D0 : S1; // big decoder only
6084 FPU : S4;
6085 MEM : S3; // any mem
6086 %}
6088 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6089 instruction_count(3);
6090 src1 : S3(read);
6091 src2 : S3(read);
6092 mem : S3(read);
6093 DECODE : S0(2); // any decoder for FPU PUSH
6094 D0 : S1; // big decoder only
6095 FPU : S4;
6096 MEM : S3; // any mem
6097 %}
6099 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6100 instruction_count(3);
6101 src1 : S3(read);
6102 src2 : S3(read);
6103 mem : S4(read);
6104 DECODE : S0; // any decoder for FPU PUSH
6105 D0 : S0(2); // big decoder only
6106 FPU : S4;
6107 MEM : S3(2); // any mem
6108 %}
6110 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6111 instruction_count(2);
6112 src1 : S3(read);
6113 dst : S4(read);
6114 D0 : S0(2); // big decoder only
6115 MEM : S3(2); // any mem
6116 %}
6118 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6119 instruction_count(3);
6120 src1 : S3(read);
6121 src2 : S3(read);
6122 dst : S4(read);
6123 D0 : S0(3); // big decoder only
6124 FPU : S4;
6125 MEM : S3(3); // any mem
6126 %}
6128 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6129 instruction_count(3);
6130 src1 : S4(read);
6131 mem : S4(read);
6132 DECODE : S0; // any decoder for FPU PUSH
6133 D0 : S0(2); // big decoder only
6134 FPU : S4;
6135 MEM : S3(2); // any mem
6136 %}
6138 // Float load constant
6139 pipe_class fpu_reg_con(regD dst) %{
6140 instruction_count(2);
6141 dst : S5(write);
6142 D0 : S0; // big decoder only for the load
6143 DECODE : S1; // any decoder for FPU POP
6144 FPU : S4;
6145 MEM : S3; // any mem
6146 %}
6148 // Float load constant
6149 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6150 instruction_count(3);
6151 dst : S5(write);
6152 src : S3(read);
6153 D0 : S0; // big decoder only for the load
6154 DECODE : S1(2); // any decoder for FPU POP
6155 FPU : S4;
6156 MEM : S3; // any mem
6157 %}
6159 // UnConditional branch
6160 pipe_class pipe_jmp( label labl ) %{
6161 single_instruction;
6162 BR : S3;
6163 %}
6165 // Conditional branch
6166 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6167 single_instruction;
6168 cr : S1(read);
6169 BR : S3;
6170 %}
6172 // Allocation idiom
6173 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6174 instruction_count(1); force_serialization;
6175 fixed_latency(6);
6176 heap_ptr : S3(read);
6177 DECODE : S0(3);
6178 D0 : S2;
6179 MEM : S3;
6180 ALU : S3(2);
6181 dst : S5(write);
6182 BR : S5;
6183 %}
6185 // Generic big/slow expanded idiom
6186 pipe_class pipe_slow( ) %{
6187 instruction_count(10); multiple_bundles; force_serialization;
6188 fixed_latency(100);
6189 D0 : S0(2);
6190 MEM : S3(2);
6191 %}
6193 // The real do-nothing guy
6194 pipe_class empty( ) %{
6195 instruction_count(0);
6196 %}
6198 // Define the class for the Nop node
6199 define %{
6200 MachNop = empty;
6201 %}
6203 %}
6205 //----------INSTRUCTIONS-------------------------------------------------------
6206 //
6207 // match -- States which machine-independent subtree may be replaced
6208 // by this instruction.
6209 // ins_cost -- The estimated cost of this instruction is used by instruction
6210 // selection to identify a minimum cost tree of machine
6211 // instructions that matches a tree of machine-independent
6212 // instructions.
6213 // format -- A string providing the disassembly for this instruction.
6214 // The value of an instruction's operand may be inserted
6215 // by referring to it with a '$' prefix.
6216 // opcode -- Three instruction opcodes may be provided. These are referred
6217 // to within an encode class as $primary, $secondary, and $tertiary
6218 // respectively. The primary opcode is commonly used to
6219 // indicate the type of machine instruction, while secondary
6220 // and tertiary are often used for prefix options or addressing
6221 // modes.
6222 // ins_encode -- A list of encode classes with parameters. The encode class
6223 // name must have been defined in an 'enc_class' specification
6224 // in the encode section of the architecture description.
6226 //----------BSWAP-Instruction--------------------------------------------------
6227 instruct bytes_reverse_int(eRegI dst) %{
6228 match(Set dst (ReverseBytesI dst));
6230 format %{ "BSWAP $dst" %}
6231 opcode(0x0F, 0xC8);
6232 ins_encode( OpcP, OpcSReg(dst) );
6233 ins_pipe( ialu_reg );
6234 %}
6236 instruct bytes_reverse_long(eRegL dst) %{
6237 match(Set dst (ReverseBytesL dst));
6239 format %{ "BSWAP $dst.lo\n\t"
6240 "BSWAP $dst.hi\n\t"
6241 "XCHG $dst.lo $dst.hi" %}
6243 ins_cost(125);
6244 ins_encode( bswap_long_bytes(dst) );
6245 ins_pipe( ialu_reg_reg);
6246 %}
6248 instruct bytes_reverse_unsigned_short(eRegI dst) %{
6249 match(Set dst (ReverseBytesUS dst));
6251 format %{ "BSWAP $dst\n\t"
6252 "SHR $dst,16\n\t" %}
6253 ins_encode %{
6254 __ bswapl($dst$$Register);
6255 __ shrl($dst$$Register, 16);
6256 %}
6257 ins_pipe( ialu_reg );
6258 %}
6260 instruct bytes_reverse_short(eRegI dst) %{
6261 match(Set dst (ReverseBytesS dst));
6263 format %{ "BSWAP $dst\n\t"
6264 "SAR $dst,16\n\t" %}
6265 ins_encode %{
6266 __ bswapl($dst$$Register);
6267 __ sarl($dst$$Register, 16);
6268 %}
6269 ins_pipe( ialu_reg );
6270 %}
6273 //---------- Zeros Count Instructions ------------------------------------------
6275 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6276 predicate(UseCountLeadingZerosInstruction);
6277 match(Set dst (CountLeadingZerosI src));
6278 effect(KILL cr);
6280 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6281 ins_encode %{
6282 __ lzcntl($dst$$Register, $src$$Register);
6283 %}
6284 ins_pipe(ialu_reg);
6285 %}
6287 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6288 predicate(!UseCountLeadingZerosInstruction);
6289 match(Set dst (CountLeadingZerosI src));
6290 effect(KILL cr);
6292 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6293 "JNZ skip\n\t"
6294 "MOV $dst, -1\n"
6295 "skip:\n\t"
6296 "NEG $dst\n\t"
6297 "ADD $dst, 31" %}
6298 ins_encode %{
6299 Register Rdst = $dst$$Register;
6300 Register Rsrc = $src$$Register;
6301 Label skip;
6302 __ bsrl(Rdst, Rsrc);
6303 __ jccb(Assembler::notZero, skip);
6304 __ movl(Rdst, -1);
6305 __ bind(skip);
6306 __ negl(Rdst);
6307 __ addl(Rdst, BitsPerInt - 1);
6308 %}
6309 ins_pipe(ialu_reg);
6310 %}
6312 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6313 predicate(UseCountLeadingZerosInstruction);
6314 match(Set dst (CountLeadingZerosL src));
6315 effect(TEMP dst, KILL cr);
6317 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6318 "JNC done\n\t"
6319 "LZCNT $dst, $src.lo\n\t"
6320 "ADD $dst, 32\n"
6321 "done:" %}
6322 ins_encode %{
6323 Register Rdst = $dst$$Register;
6324 Register Rsrc = $src$$Register;
6325 Label done;
6326 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6327 __ jccb(Assembler::carryClear, done);
6328 __ lzcntl(Rdst, Rsrc);
6329 __ addl(Rdst, BitsPerInt);
6330 __ bind(done);
6331 %}
6332 ins_pipe(ialu_reg);
6333 %}
6335 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6336 predicate(!UseCountLeadingZerosInstruction);
6337 match(Set dst (CountLeadingZerosL src));
6338 effect(TEMP dst, KILL cr);
6340 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6341 "JZ msw_is_zero\n\t"
6342 "ADD $dst, 32\n\t"
6343 "JMP not_zero\n"
6344 "msw_is_zero:\n\t"
6345 "BSR $dst, $src.lo\n\t"
6346 "JNZ not_zero\n\t"
6347 "MOV $dst, -1\n"
6348 "not_zero:\n\t"
6349 "NEG $dst\n\t"
6350 "ADD $dst, 63\n" %}
6351 ins_encode %{
6352 Register Rdst = $dst$$Register;
6353 Register Rsrc = $src$$Register;
6354 Label msw_is_zero;
6355 Label not_zero;
6356 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6357 __ jccb(Assembler::zero, msw_is_zero);
6358 __ addl(Rdst, BitsPerInt);
6359 __ jmpb(not_zero);
6360 __ bind(msw_is_zero);
6361 __ bsrl(Rdst, Rsrc);
6362 __ jccb(Assembler::notZero, not_zero);
6363 __ movl(Rdst, -1);
6364 __ bind(not_zero);
6365 __ negl(Rdst);
6366 __ addl(Rdst, BitsPerLong - 1);
6367 %}
6368 ins_pipe(ialu_reg);
6369 %}
6371 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6372 match(Set dst (CountTrailingZerosI src));
6373 effect(KILL cr);
6375 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6376 "JNZ done\n\t"
6377 "MOV $dst, 32\n"
6378 "done:" %}
6379 ins_encode %{
6380 Register Rdst = $dst$$Register;
6381 Label done;
6382 __ bsfl(Rdst, $src$$Register);
6383 __ jccb(Assembler::notZero, done);
6384 __ movl(Rdst, BitsPerInt);
6385 __ bind(done);
6386 %}
6387 ins_pipe(ialu_reg);
6388 %}
6390 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6391 match(Set dst (CountTrailingZerosL src));
6392 effect(TEMP dst, KILL cr);
6394 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6395 "JNZ done\n\t"
6396 "BSF $dst, $src.hi\n\t"
6397 "JNZ msw_not_zero\n\t"
6398 "MOV $dst, 32\n"
6399 "msw_not_zero:\n\t"
6400 "ADD $dst, 32\n"
6401 "done:" %}
6402 ins_encode %{
6403 Register Rdst = $dst$$Register;
6404 Register Rsrc = $src$$Register;
6405 Label msw_not_zero;
6406 Label done;
6407 __ bsfl(Rdst, Rsrc);
6408 __ jccb(Assembler::notZero, done);
6409 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6410 __ jccb(Assembler::notZero, msw_not_zero);
6411 __ movl(Rdst, BitsPerInt);
6412 __ bind(msw_not_zero);
6413 __ addl(Rdst, BitsPerInt);
6414 __ bind(done);
6415 %}
6416 ins_pipe(ialu_reg);
6417 %}
6420 //---------- Population Count Instructions -------------------------------------
6422 instruct popCountI(eRegI dst, eRegI src) %{
6423 predicate(UsePopCountInstruction);
6424 match(Set dst (PopCountI src));
6426 format %{ "POPCNT $dst, $src" %}
6427 ins_encode %{
6428 __ popcntl($dst$$Register, $src$$Register);
6429 %}
6430 ins_pipe(ialu_reg);
6431 %}
6433 instruct popCountI_mem(eRegI dst, memory mem) %{
6434 predicate(UsePopCountInstruction);
6435 match(Set dst (PopCountI (LoadI mem)));
6437 format %{ "POPCNT $dst, $mem" %}
6438 ins_encode %{
6439 __ popcntl($dst$$Register, $mem$$Address);
6440 %}
6441 ins_pipe(ialu_reg);
6442 %}
6444 // Note: Long.bitCount(long) returns an int.
6445 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6446 predicate(UsePopCountInstruction);
6447 match(Set dst (PopCountL src));
6448 effect(KILL cr, TEMP tmp, TEMP dst);
6450 format %{ "POPCNT $dst, $src.lo\n\t"
6451 "POPCNT $tmp, $src.hi\n\t"
6452 "ADD $dst, $tmp" %}
6453 ins_encode %{
6454 __ popcntl($dst$$Register, $src$$Register);
6455 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6456 __ addl($dst$$Register, $tmp$$Register);
6457 %}
6458 ins_pipe(ialu_reg);
6459 %}
6461 // Note: Long.bitCount(long) returns an int.
6462 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6463 predicate(UsePopCountInstruction);
6464 match(Set dst (PopCountL (LoadL mem)));
6465 effect(KILL cr, TEMP tmp, TEMP dst);
6467 format %{ "POPCNT $dst, $mem\n\t"
6468 "POPCNT $tmp, $mem+4\n\t"
6469 "ADD $dst, $tmp" %}
6470 ins_encode %{
6471 //__ popcntl($dst$$Register, $mem$$Address$$first);
6472 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6473 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6474 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6475 __ addl($dst$$Register, $tmp$$Register);
6476 %}
6477 ins_pipe(ialu_reg);
6478 %}
6481 //----------Load/Store/Move Instructions---------------------------------------
6482 //----------Load Instructions--------------------------------------------------
6483 // Load Byte (8bit signed)
6484 instruct loadB(xRegI dst, memory mem) %{
6485 match(Set dst (LoadB mem));
6487 ins_cost(125);
6488 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6490 ins_encode %{
6491 __ movsbl($dst$$Register, $mem$$Address);
6492 %}
6494 ins_pipe(ialu_reg_mem);
6495 %}
6497 // Load Byte (8bit signed) into Long Register
6498 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6499 match(Set dst (ConvI2L (LoadB mem)));
6500 effect(KILL cr);
6502 ins_cost(375);
6503 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6504 "MOV $dst.hi,$dst.lo\n\t"
6505 "SAR $dst.hi,7" %}
6507 ins_encode %{
6508 __ movsbl($dst$$Register, $mem$$Address);
6509 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6510 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6511 %}
6513 ins_pipe(ialu_reg_mem);
6514 %}
6516 // Load Unsigned Byte (8bit UNsigned)
6517 instruct loadUB(xRegI dst, memory mem) %{
6518 match(Set dst (LoadUB mem));
6520 ins_cost(125);
6521 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6523 ins_encode %{
6524 __ movzbl($dst$$Register, $mem$$Address);
6525 %}
6527 ins_pipe(ialu_reg_mem);
6528 %}
6530 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6531 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6532 match(Set dst (ConvI2L (LoadUB mem)));
6533 effect(KILL cr);
6535 ins_cost(250);
6536 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6537 "XOR $dst.hi,$dst.hi" %}
6539 ins_encode %{
6540 Register Rdst = $dst$$Register;
6541 __ movzbl(Rdst, $mem$$Address);
6542 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6543 %}
6545 ins_pipe(ialu_reg_mem);
6546 %}
6548 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6549 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6550 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6551 effect(KILL cr);
6553 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6554 "XOR $dst.hi,$dst.hi\n\t"
6555 "AND $dst.lo,$mask" %}
6556 ins_encode %{
6557 Register Rdst = $dst$$Register;
6558 __ movzbl(Rdst, $mem$$Address);
6559 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6560 __ andl(Rdst, $mask$$constant);
6561 %}
6562 ins_pipe(ialu_reg_mem);
6563 %}
6565 // Load Short (16bit signed)
6566 instruct loadS(eRegI dst, memory mem) %{
6567 match(Set dst (LoadS mem));
6569 ins_cost(125);
6570 format %{ "MOVSX $dst,$mem\t# short" %}
6572 ins_encode %{
6573 __ movswl($dst$$Register, $mem$$Address);
6574 %}
6576 ins_pipe(ialu_reg_mem);
6577 %}
6579 // Load Short (16 bit signed) to Byte (8 bit signed)
6580 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6581 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6583 ins_cost(125);
6584 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6585 ins_encode %{
6586 __ movsbl($dst$$Register, $mem$$Address);
6587 %}
6588 ins_pipe(ialu_reg_mem);
6589 %}
6591 // Load Short (16bit signed) into Long Register
6592 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6593 match(Set dst (ConvI2L (LoadS mem)));
6594 effect(KILL cr);
6596 ins_cost(375);
6597 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6598 "MOV $dst.hi,$dst.lo\n\t"
6599 "SAR $dst.hi,15" %}
6601 ins_encode %{
6602 __ movswl($dst$$Register, $mem$$Address);
6603 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6604 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6605 %}
6607 ins_pipe(ialu_reg_mem);
6608 %}
6610 // Load Unsigned Short/Char (16bit unsigned)
6611 instruct loadUS(eRegI dst, memory mem) %{
6612 match(Set dst (LoadUS mem));
6614 ins_cost(125);
6615 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6617 ins_encode %{
6618 __ movzwl($dst$$Register, $mem$$Address);
6619 %}
6621 ins_pipe(ialu_reg_mem);
6622 %}
6624 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6625 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6626 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6628 ins_cost(125);
6629 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6630 ins_encode %{
6631 __ movsbl($dst$$Register, $mem$$Address);
6632 %}
6633 ins_pipe(ialu_reg_mem);
6634 %}
6636 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6637 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6638 match(Set dst (ConvI2L (LoadUS mem)));
6639 effect(KILL cr);
6641 ins_cost(250);
6642 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6643 "XOR $dst.hi,$dst.hi" %}
6645 ins_encode %{
6646 __ movzwl($dst$$Register, $mem$$Address);
6647 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6648 %}
6650 ins_pipe(ialu_reg_mem);
6651 %}
6653 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6654 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6655 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6656 effect(KILL cr);
6658 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6659 "XOR $dst.hi,$dst.hi" %}
6660 ins_encode %{
6661 Register Rdst = $dst$$Register;
6662 __ movzbl(Rdst, $mem$$Address);
6663 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6664 %}
6665 ins_pipe(ialu_reg_mem);
6666 %}
6668 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6669 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6670 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6671 effect(KILL cr);
6673 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6674 "XOR $dst.hi,$dst.hi\n\t"
6675 "AND $dst.lo,$mask" %}
6676 ins_encode %{
6677 Register Rdst = $dst$$Register;
6678 __ movzwl(Rdst, $mem$$Address);
6679 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6680 __ andl(Rdst, $mask$$constant);
6681 %}
6682 ins_pipe(ialu_reg_mem);
6683 %}
6685 // Load Integer
6686 instruct loadI(eRegI dst, memory mem) %{
6687 match(Set dst (LoadI mem));
6689 ins_cost(125);
6690 format %{ "MOV $dst,$mem\t# int" %}
6692 ins_encode %{
6693 __ movl($dst$$Register, $mem$$Address);
6694 %}
6696 ins_pipe(ialu_reg_mem);
6697 %}
6699 // Load Integer (32 bit signed) to Byte (8 bit signed)
6700 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6701 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6703 ins_cost(125);
6704 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6705 ins_encode %{
6706 __ movsbl($dst$$Register, $mem$$Address);
6707 %}
6708 ins_pipe(ialu_reg_mem);
6709 %}
6711 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6712 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6713 match(Set dst (AndI (LoadI mem) mask));
6715 ins_cost(125);
6716 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6717 ins_encode %{
6718 __ movzbl($dst$$Register, $mem$$Address);
6719 %}
6720 ins_pipe(ialu_reg_mem);
6721 %}
6723 // Load Integer (32 bit signed) to Short (16 bit signed)
6724 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6725 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6727 ins_cost(125);
6728 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6729 ins_encode %{
6730 __ movswl($dst$$Register, $mem$$Address);
6731 %}
6732 ins_pipe(ialu_reg_mem);
6733 %}
6735 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6736 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6737 match(Set dst (AndI (LoadI mem) mask));
6739 ins_cost(125);
6740 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6741 ins_encode %{
6742 __ movzwl($dst$$Register, $mem$$Address);
6743 %}
6744 ins_pipe(ialu_reg_mem);
6745 %}
6747 // Load Integer into Long Register
6748 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6749 match(Set dst (ConvI2L (LoadI mem)));
6750 effect(KILL cr);
6752 ins_cost(375);
6753 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6754 "MOV $dst.hi,$dst.lo\n\t"
6755 "SAR $dst.hi,31" %}
6757 ins_encode %{
6758 __ movl($dst$$Register, $mem$$Address);
6759 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6760 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6761 %}
6763 ins_pipe(ialu_reg_mem);
6764 %}
6766 // Load Integer with mask 0xFF into Long Register
6767 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6768 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6769 effect(KILL cr);
6771 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6772 "XOR $dst.hi,$dst.hi" %}
6773 ins_encode %{
6774 Register Rdst = $dst$$Register;
6775 __ movzbl(Rdst, $mem$$Address);
6776 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6777 %}
6778 ins_pipe(ialu_reg_mem);
6779 %}
6781 // Load Integer with mask 0xFFFF into Long Register
6782 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6783 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6784 effect(KILL cr);
6786 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6787 "XOR $dst.hi,$dst.hi" %}
6788 ins_encode %{
6789 Register Rdst = $dst$$Register;
6790 __ movzwl(Rdst, $mem$$Address);
6791 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6792 %}
6793 ins_pipe(ialu_reg_mem);
6794 %}
6796 // Load Integer with 32-bit mask into Long Register
6797 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6798 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6799 effect(KILL cr);
6801 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6802 "XOR $dst.hi,$dst.hi\n\t"
6803 "AND $dst.lo,$mask" %}
6804 ins_encode %{
6805 Register Rdst = $dst$$Register;
6806 __ movl(Rdst, $mem$$Address);
6807 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6808 __ andl(Rdst, $mask$$constant);
6809 %}
6810 ins_pipe(ialu_reg_mem);
6811 %}
6813 // Load Unsigned Integer into Long Register
6814 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6815 match(Set dst (LoadUI2L mem));
6816 effect(KILL cr);
6818 ins_cost(250);
6819 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6820 "XOR $dst.hi,$dst.hi" %}
6822 ins_encode %{
6823 __ movl($dst$$Register, $mem$$Address);
6824 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6825 %}
6827 ins_pipe(ialu_reg_mem);
6828 %}
6830 // Load Long. Cannot clobber address while loading, so restrict address
6831 // register to ESI
6832 instruct loadL(eRegL dst, load_long_memory mem) %{
6833 predicate(!((LoadLNode*)n)->require_atomic_access());
6834 match(Set dst (LoadL mem));
6836 ins_cost(250);
6837 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6838 "MOV $dst.hi,$mem+4" %}
6840 ins_encode %{
6841 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6842 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6843 __ movl($dst$$Register, Amemlo);
6844 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6845 %}
6847 ins_pipe(ialu_reg_long_mem);
6848 %}
6850 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6851 // then store it down to the stack and reload on the int
6852 // side.
6853 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6854 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6855 match(Set dst (LoadL mem));
6857 ins_cost(200);
6858 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6859 "FISTp $dst" %}
6860 ins_encode(enc_loadL_volatile(mem,dst));
6861 ins_pipe( fpu_reg_mem );
6862 %}
6864 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6865 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6866 match(Set dst (LoadL mem));
6867 effect(TEMP tmp);
6868 ins_cost(180);
6869 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6870 "MOVSD $dst,$tmp" %}
6871 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6872 ins_pipe( pipe_slow );
6873 %}
6875 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6876 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6877 match(Set dst (LoadL mem));
6878 effect(TEMP tmp);
6879 ins_cost(160);
6880 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6881 "MOVD $dst.lo,$tmp\n\t"
6882 "PSRLQ $tmp,32\n\t"
6883 "MOVD $dst.hi,$tmp" %}
6884 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6885 ins_pipe( pipe_slow );
6886 %}
6888 // Load Range
6889 instruct loadRange(eRegI dst, memory mem) %{
6890 match(Set dst (LoadRange mem));
6892 ins_cost(125);
6893 format %{ "MOV $dst,$mem" %}
6894 opcode(0x8B);
6895 ins_encode( OpcP, RegMem(dst,mem));
6896 ins_pipe( ialu_reg_mem );
6897 %}
6900 // Load Pointer
6901 instruct loadP(eRegP dst, memory mem) %{
6902 match(Set dst (LoadP mem));
6904 ins_cost(125);
6905 format %{ "MOV $dst,$mem" %}
6906 opcode(0x8B);
6907 ins_encode( OpcP, RegMem(dst,mem));
6908 ins_pipe( ialu_reg_mem );
6909 %}
6911 // Load Klass Pointer
6912 instruct loadKlass(eRegP dst, memory mem) %{
6913 match(Set dst (LoadKlass mem));
6915 ins_cost(125);
6916 format %{ "MOV $dst,$mem" %}
6917 opcode(0x8B);
6918 ins_encode( OpcP, RegMem(dst,mem));
6919 ins_pipe( ialu_reg_mem );
6920 %}
6922 // Load Double
6923 instruct loadD(regD dst, memory mem) %{
6924 predicate(UseSSE<=1);
6925 match(Set dst (LoadD mem));
6927 ins_cost(150);
6928 format %{ "FLD_D ST,$mem\n\t"
6929 "FSTP $dst" %}
6930 opcode(0xDD); /* DD /0 */
6931 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6932 Pop_Reg_D(dst) );
6933 ins_pipe( fpu_reg_mem );
6934 %}
6936 // Load Double to XMM
6937 instruct loadXD(regXD dst, memory mem) %{
6938 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6939 match(Set dst (LoadD mem));
6940 ins_cost(145);
6941 format %{ "MOVSD $dst,$mem" %}
6942 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6943 ins_pipe( pipe_slow );
6944 %}
6946 instruct loadXD_partial(regXD dst, memory mem) %{
6947 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6948 match(Set dst (LoadD mem));
6949 ins_cost(145);
6950 format %{ "MOVLPD $dst,$mem" %}
6951 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6952 ins_pipe( pipe_slow );
6953 %}
6955 // Load to XMM register (single-precision floating point)
6956 // MOVSS instruction
6957 instruct loadX(regX dst, memory mem) %{
6958 predicate(UseSSE>=1);
6959 match(Set dst (LoadF mem));
6960 ins_cost(145);
6961 format %{ "MOVSS $dst,$mem" %}
6962 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6963 ins_pipe( pipe_slow );
6964 %}
6966 // Load Float
6967 instruct loadF(regF dst, memory mem) %{
6968 predicate(UseSSE==0);
6969 match(Set dst (LoadF mem));
6971 ins_cost(150);
6972 format %{ "FLD_S ST,$mem\n\t"
6973 "FSTP $dst" %}
6974 opcode(0xD9); /* D9 /0 */
6975 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6976 Pop_Reg_F(dst) );
6977 ins_pipe( fpu_reg_mem );
6978 %}
6980 // Load Aligned Packed Byte to XMM register
6981 instruct loadA8B(regXD dst, memory mem) %{
6982 predicate(UseSSE>=1);
6983 match(Set dst (Load8B mem));
6984 ins_cost(125);
6985 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6986 ins_encode( movq_ld(dst, mem));
6987 ins_pipe( pipe_slow );
6988 %}
6990 // Load Aligned Packed Short to XMM register
6991 instruct loadA4S(regXD dst, memory mem) %{
6992 predicate(UseSSE>=1);
6993 match(Set dst (Load4S mem));
6994 ins_cost(125);
6995 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6996 ins_encode( movq_ld(dst, mem));
6997 ins_pipe( pipe_slow );
6998 %}
7000 // Load Aligned Packed Char to XMM register
7001 instruct loadA4C(regXD dst, memory mem) %{
7002 predicate(UseSSE>=1);
7003 match(Set dst (Load4C mem));
7004 ins_cost(125);
7005 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7006 ins_encode( movq_ld(dst, mem));
7007 ins_pipe( pipe_slow );
7008 %}
7010 // Load Aligned Packed Integer to XMM register
7011 instruct load2IU(regXD dst, memory mem) %{
7012 predicate(UseSSE>=1);
7013 match(Set dst (Load2I mem));
7014 ins_cost(125);
7015 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7016 ins_encode( movq_ld(dst, mem));
7017 ins_pipe( pipe_slow );
7018 %}
7020 // Load Aligned Packed Single to XMM
7021 instruct loadA2F(regXD dst, memory mem) %{
7022 predicate(UseSSE>=1);
7023 match(Set dst (Load2F mem));
7024 ins_cost(145);
7025 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7026 ins_encode( movq_ld(dst, mem));
7027 ins_pipe( pipe_slow );
7028 %}
7030 // Load Effective Address
7031 instruct leaP8(eRegP dst, indOffset8 mem) %{
7032 match(Set dst mem);
7034 ins_cost(110);
7035 format %{ "LEA $dst,$mem" %}
7036 opcode(0x8D);
7037 ins_encode( OpcP, RegMem(dst,mem));
7038 ins_pipe( ialu_reg_reg_fat );
7039 %}
7041 instruct leaP32(eRegP dst, indOffset32 mem) %{
7042 match(Set dst mem);
7044 ins_cost(110);
7045 format %{ "LEA $dst,$mem" %}
7046 opcode(0x8D);
7047 ins_encode( OpcP, RegMem(dst,mem));
7048 ins_pipe( ialu_reg_reg_fat );
7049 %}
7051 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7052 match(Set dst mem);
7054 ins_cost(110);
7055 format %{ "LEA $dst,$mem" %}
7056 opcode(0x8D);
7057 ins_encode( OpcP, RegMem(dst,mem));
7058 ins_pipe( ialu_reg_reg_fat );
7059 %}
7061 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7062 match(Set dst mem);
7064 ins_cost(110);
7065 format %{ "LEA $dst,$mem" %}
7066 opcode(0x8D);
7067 ins_encode( OpcP, RegMem(dst,mem));
7068 ins_pipe( ialu_reg_reg_fat );
7069 %}
7071 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7072 match(Set dst mem);
7074 ins_cost(110);
7075 format %{ "LEA $dst,$mem" %}
7076 opcode(0x8D);
7077 ins_encode( OpcP, RegMem(dst,mem));
7078 ins_pipe( ialu_reg_reg_fat );
7079 %}
7081 // Load Constant
7082 instruct loadConI(eRegI dst, immI src) %{
7083 match(Set dst src);
7085 format %{ "MOV $dst,$src" %}
7086 ins_encode( LdImmI(dst, src) );
7087 ins_pipe( ialu_reg_fat );
7088 %}
7090 // Load Constant zero
7091 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7092 match(Set dst src);
7093 effect(KILL cr);
7095 ins_cost(50);
7096 format %{ "XOR $dst,$dst" %}
7097 opcode(0x33); /* + rd */
7098 ins_encode( OpcP, RegReg( dst, dst ) );
7099 ins_pipe( ialu_reg );
7100 %}
7102 instruct loadConP(eRegP dst, immP src) %{
7103 match(Set dst src);
7105 format %{ "MOV $dst,$src" %}
7106 opcode(0xB8); /* + rd */
7107 ins_encode( LdImmP(dst, src) );
7108 ins_pipe( ialu_reg_fat );
7109 %}
7111 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7112 match(Set dst src);
7113 effect(KILL cr);
7114 ins_cost(200);
7115 format %{ "MOV $dst.lo,$src.lo\n\t"
7116 "MOV $dst.hi,$src.hi" %}
7117 opcode(0xB8);
7118 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7119 ins_pipe( ialu_reg_long_fat );
7120 %}
7122 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7123 match(Set dst src);
7124 effect(KILL cr);
7125 ins_cost(150);
7126 format %{ "XOR $dst.lo,$dst.lo\n\t"
7127 "XOR $dst.hi,$dst.hi" %}
7128 opcode(0x33,0x33);
7129 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7130 ins_pipe( ialu_reg_long );
7131 %}
7133 // The instruction usage is guarded by predicate in operand immF().
7134 instruct loadConF(regF dst, immF con) %{
7135 match(Set dst con);
7136 ins_cost(125);
7137 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
7138 "FSTP $dst" %}
7139 ins_encode %{
7140 __ fld_s($constantaddress($con));
7141 __ fstp_d($dst$$reg);
7142 %}
7143 ins_pipe(fpu_reg_con);
7144 %}
7146 // The instruction usage is guarded by predicate in operand immF0().
7147 instruct loadConF0(regF dst, immF0 con) %{
7148 match(Set dst con);
7149 ins_cost(125);
7150 format %{ "FLDZ ST\n\t"
7151 "FSTP $dst" %}
7152 ins_encode %{
7153 __ fldz();
7154 __ fstp_d($dst$$reg);
7155 %}
7156 ins_pipe(fpu_reg_con);
7157 %}
7159 // The instruction usage is guarded by predicate in operand immF1().
7160 instruct loadConF1(regF dst, immF1 con) %{
7161 match(Set dst con);
7162 ins_cost(125);
7163 format %{ "FLD1 ST\n\t"
7164 "FSTP $dst" %}
7165 ins_encode %{
7166 __ fld1();
7167 __ fstp_d($dst$$reg);
7168 %}
7169 ins_pipe(fpu_reg_con);
7170 %}
7172 // The instruction usage is guarded by predicate in operand immXF().
7173 instruct loadConX(regX dst, immXF con) %{
7174 match(Set dst con);
7175 ins_cost(125);
7176 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
7177 ins_encode %{
7178 __ movflt($dst$$XMMRegister, $constantaddress($con));
7179 %}
7180 ins_pipe(pipe_slow);
7181 %}
7183 // The instruction usage is guarded by predicate in operand immXF0().
7184 instruct loadConX0(regX dst, immXF0 src) %{
7185 match(Set dst src);
7186 ins_cost(100);
7187 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7188 ins_encode %{
7189 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
7190 %}
7191 ins_pipe(pipe_slow);
7192 %}
7194 // The instruction usage is guarded by predicate in operand immD().
7195 instruct loadConD(regD dst, immD con) %{
7196 match(Set dst con);
7197 ins_cost(125);
7199 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
7200 "FSTP $dst" %}
7201 ins_encode %{
7202 __ fld_d($constantaddress($con));
7203 __ fstp_d($dst$$reg);
7204 %}
7205 ins_pipe(fpu_reg_con);
7206 %}
7208 // The instruction usage is guarded by predicate in operand immD0().
7209 instruct loadConD0(regD dst, immD0 con) %{
7210 match(Set dst con);
7211 ins_cost(125);
7213 format %{ "FLDZ ST\n\t"
7214 "FSTP $dst" %}
7215 ins_encode %{
7216 __ fldz();
7217 __ fstp_d($dst$$reg);
7218 %}
7219 ins_pipe(fpu_reg_con);
7220 %}
7222 // The instruction usage is guarded by predicate in operand immD1().
7223 instruct loadConD1(regD dst, immD1 con) %{
7224 match(Set dst con);
7225 ins_cost(125);
7227 format %{ "FLD1 ST\n\t"
7228 "FSTP $dst" %}
7229 ins_encode %{
7230 __ fld1();
7231 __ fstp_d($dst$$reg);
7232 %}
7233 ins_pipe(fpu_reg_con);
7234 %}
7236 // The instruction usage is guarded by predicate in operand immXD().
7237 instruct loadConXD(regXD dst, immXD con) %{
7238 match(Set dst con);
7239 ins_cost(125);
7240 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
7241 ins_encode %{
7242 __ movdbl($dst$$XMMRegister, $constantaddress($con));
7243 %}
7244 ins_pipe(pipe_slow);
7245 %}
7247 // The instruction usage is guarded by predicate in operand immXD0().
7248 instruct loadConXD0(regXD dst, immXD0 src) %{
7249 match(Set dst src);
7250 ins_cost(100);
7251 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7252 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7253 ins_pipe( pipe_slow );
7254 %}
7256 // Load Stack Slot
7257 instruct loadSSI(eRegI dst, stackSlotI src) %{
7258 match(Set dst src);
7259 ins_cost(125);
7261 format %{ "MOV $dst,$src" %}
7262 opcode(0x8B);
7263 ins_encode( OpcP, RegMem(dst,src));
7264 ins_pipe( ialu_reg_mem );
7265 %}
7267 instruct loadSSL(eRegL dst, stackSlotL src) %{
7268 match(Set dst src);
7270 ins_cost(200);
7271 format %{ "MOV $dst,$src.lo\n\t"
7272 "MOV $dst+4,$src.hi" %}
7273 opcode(0x8B, 0x8B);
7274 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7275 ins_pipe( ialu_mem_long_reg );
7276 %}
7278 // Load Stack Slot
7279 instruct loadSSP(eRegP dst, stackSlotP src) %{
7280 match(Set dst src);
7281 ins_cost(125);
7283 format %{ "MOV $dst,$src" %}
7284 opcode(0x8B);
7285 ins_encode( OpcP, RegMem(dst,src));
7286 ins_pipe( ialu_reg_mem );
7287 %}
7289 // Load Stack Slot
7290 instruct loadSSF(regF dst, stackSlotF src) %{
7291 match(Set dst src);
7292 ins_cost(125);
7294 format %{ "FLD_S $src\n\t"
7295 "FSTP $dst" %}
7296 opcode(0xD9); /* D9 /0, FLD m32real */
7297 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7298 Pop_Reg_F(dst) );
7299 ins_pipe( fpu_reg_mem );
7300 %}
7302 // Load Stack Slot
7303 instruct loadSSD(regD dst, stackSlotD src) %{
7304 match(Set dst src);
7305 ins_cost(125);
7307 format %{ "FLD_D $src\n\t"
7308 "FSTP $dst" %}
7309 opcode(0xDD); /* DD /0, FLD m64real */
7310 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7311 Pop_Reg_D(dst) );
7312 ins_pipe( fpu_reg_mem );
7313 %}
7315 // Prefetch instructions.
7316 // Must be safe to execute with invalid address (cannot fault).
7318 instruct prefetchr0( memory mem ) %{
7319 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7320 match(PrefetchRead mem);
7321 ins_cost(0);
7322 size(0);
7323 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7324 ins_encode();
7325 ins_pipe(empty);
7326 %}
7328 instruct prefetchr( memory mem ) %{
7329 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
7330 match(PrefetchRead mem);
7331 ins_cost(100);
7333 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7334 ins_encode %{
7335 __ prefetchr($mem$$Address);
7336 %}
7337 ins_pipe(ialu_mem);
7338 %}
7340 instruct prefetchrNTA( memory mem ) %{
7341 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7342 match(PrefetchRead mem);
7343 ins_cost(100);
7345 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7346 ins_encode %{
7347 __ prefetchnta($mem$$Address);
7348 %}
7349 ins_pipe(ialu_mem);
7350 %}
7352 instruct prefetchrT0( memory mem ) %{
7353 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7354 match(PrefetchRead mem);
7355 ins_cost(100);
7357 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7358 ins_encode %{
7359 __ prefetcht0($mem$$Address);
7360 %}
7361 ins_pipe(ialu_mem);
7362 %}
7364 instruct prefetchrT2( memory mem ) %{
7365 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7366 match(PrefetchRead mem);
7367 ins_cost(100);
7369 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7370 ins_encode %{
7371 __ prefetcht2($mem$$Address);
7372 %}
7373 ins_pipe(ialu_mem);
7374 %}
7376 instruct prefetchw0( memory mem ) %{
7377 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7378 match(PrefetchWrite mem);
7379 ins_cost(0);
7380 size(0);
7381 format %{ "Prefetch (non-SSE is empty encoding)" %}
7382 ins_encode();
7383 ins_pipe(empty);
7384 %}
7386 instruct prefetchw( memory mem ) %{
7387 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
7388 match( PrefetchWrite mem );
7389 ins_cost(100);
7391 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7392 ins_encode %{
7393 __ prefetchw($mem$$Address);
7394 %}
7395 ins_pipe(ialu_mem);
7396 %}
7398 instruct prefetchwNTA( memory mem ) %{
7399 predicate(UseSSE>=1);
7400 match(PrefetchWrite mem);
7401 ins_cost(100);
7403 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7404 ins_encode %{
7405 __ prefetchnta($mem$$Address);
7406 %}
7407 ins_pipe(ialu_mem);
7408 %}
7410 // Prefetch instructions for allocation.
7412 instruct prefetchAlloc0( memory mem ) %{
7413 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
7414 match(PrefetchAllocation mem);
7415 ins_cost(0);
7416 size(0);
7417 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
7418 ins_encode();
7419 ins_pipe(empty);
7420 %}
7422 instruct prefetchAlloc( memory mem ) %{
7423 predicate(AllocatePrefetchInstr==3);
7424 match( PrefetchAllocation mem );
7425 ins_cost(100);
7427 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
7428 ins_encode %{
7429 __ prefetchw($mem$$Address);
7430 %}
7431 ins_pipe(ialu_mem);
7432 %}
7434 instruct prefetchAllocNTA( memory mem ) %{
7435 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7436 match(PrefetchAllocation mem);
7437 ins_cost(100);
7439 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
7440 ins_encode %{
7441 __ prefetchnta($mem$$Address);
7442 %}
7443 ins_pipe(ialu_mem);
7444 %}
7446 instruct prefetchAllocT0( memory mem ) %{
7447 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7448 match(PrefetchAllocation mem);
7449 ins_cost(100);
7451 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
7452 ins_encode %{
7453 __ prefetcht0($mem$$Address);
7454 %}
7455 ins_pipe(ialu_mem);
7456 %}
7458 instruct prefetchAllocT2( memory mem ) %{
7459 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7460 match(PrefetchAllocation mem);
7461 ins_cost(100);
7463 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
7464 ins_encode %{
7465 __ prefetcht2($mem$$Address);
7466 %}
7467 ins_pipe(ialu_mem);
7468 %}
7470 //----------Store Instructions-------------------------------------------------
7472 // Store Byte
7473 instruct storeB(memory mem, xRegI src) %{
7474 match(Set mem (StoreB mem src));
7476 ins_cost(125);
7477 format %{ "MOV8 $mem,$src" %}
7478 opcode(0x88);
7479 ins_encode( OpcP, RegMem( src, mem ) );
7480 ins_pipe( ialu_mem_reg );
7481 %}
7483 // Store Char/Short
7484 instruct storeC(memory mem, eRegI src) %{
7485 match(Set mem (StoreC mem src));
7487 ins_cost(125);
7488 format %{ "MOV16 $mem,$src" %}
7489 opcode(0x89, 0x66);
7490 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7491 ins_pipe( ialu_mem_reg );
7492 %}
7494 // Store Integer
7495 instruct storeI(memory mem, eRegI src) %{
7496 match(Set mem (StoreI mem src));
7498 ins_cost(125);
7499 format %{ "MOV $mem,$src" %}
7500 opcode(0x89);
7501 ins_encode( OpcP, RegMem( src, mem ) );
7502 ins_pipe( ialu_mem_reg );
7503 %}
7505 // Store Long
7506 instruct storeL(long_memory mem, eRegL src) %{
7507 predicate(!((StoreLNode*)n)->require_atomic_access());
7508 match(Set mem (StoreL mem src));
7510 ins_cost(200);
7511 format %{ "MOV $mem,$src.lo\n\t"
7512 "MOV $mem+4,$src.hi" %}
7513 opcode(0x89, 0x89);
7514 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7515 ins_pipe( ialu_mem_long_reg );
7516 %}
7518 // Store Long to Integer
7519 instruct storeL2I(memory mem, eRegL src) %{
7520 match(Set mem (StoreI mem (ConvL2I src)));
7522 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7523 ins_encode %{
7524 __ movl($mem$$Address, $src$$Register);
7525 %}
7526 ins_pipe(ialu_mem_reg);
7527 %}
7529 // Volatile Store Long. Must be atomic, so move it into
7530 // the FP TOS and then do a 64-bit FIST. Has to probe the
7531 // target address before the store (for null-ptr checks)
7532 // so the memory operand is used twice in the encoding.
7533 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7534 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7535 match(Set mem (StoreL mem src));
7536 effect( KILL cr );
7537 ins_cost(400);
7538 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7539 "FILD $src\n\t"
7540 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7541 opcode(0x3B);
7542 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7543 ins_pipe( fpu_reg_mem );
7544 %}
7546 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7547 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7548 match(Set mem (StoreL mem src));
7549 effect( TEMP tmp, KILL cr );
7550 ins_cost(380);
7551 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7552 "MOVSD $tmp,$src\n\t"
7553 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7554 opcode(0x3B);
7555 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7556 ins_pipe( pipe_slow );
7557 %}
7559 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7560 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7561 match(Set mem (StoreL mem src));
7562 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7563 ins_cost(360);
7564 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7565 "MOVD $tmp,$src.lo\n\t"
7566 "MOVD $tmp2,$src.hi\n\t"
7567 "PUNPCKLDQ $tmp,$tmp2\n\t"
7568 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7569 opcode(0x3B);
7570 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7571 ins_pipe( pipe_slow );
7572 %}
7574 // Store Pointer; for storing unknown oops and raw pointers
7575 instruct storeP(memory mem, anyRegP src) %{
7576 match(Set mem (StoreP mem src));
7578 ins_cost(125);
7579 format %{ "MOV $mem,$src" %}
7580 opcode(0x89);
7581 ins_encode( OpcP, RegMem( src, mem ) );
7582 ins_pipe( ialu_mem_reg );
7583 %}
7585 // Store Integer Immediate
7586 instruct storeImmI(memory mem, immI src) %{
7587 match(Set mem (StoreI mem src));
7589 ins_cost(150);
7590 format %{ "MOV $mem,$src" %}
7591 opcode(0xC7); /* C7 /0 */
7592 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7593 ins_pipe( ialu_mem_imm );
7594 %}
7596 // Store Short/Char Immediate
7597 instruct storeImmI16(memory mem, immI16 src) %{
7598 predicate(UseStoreImmI16);
7599 match(Set mem (StoreC mem src));
7601 ins_cost(150);
7602 format %{ "MOV16 $mem,$src" %}
7603 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7604 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7605 ins_pipe( ialu_mem_imm );
7606 %}
7608 // Store Pointer Immediate; null pointers or constant oops that do not
7609 // need card-mark barriers.
7610 instruct storeImmP(memory mem, immP src) %{
7611 match(Set mem (StoreP mem src));
7613 ins_cost(150);
7614 format %{ "MOV $mem,$src" %}
7615 opcode(0xC7); /* C7 /0 */
7616 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7617 ins_pipe( ialu_mem_imm );
7618 %}
7620 // Store Byte Immediate
7621 instruct storeImmB(memory mem, immI8 src) %{
7622 match(Set mem (StoreB mem src));
7624 ins_cost(150);
7625 format %{ "MOV8 $mem,$src" %}
7626 opcode(0xC6); /* C6 /0 */
7627 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7628 ins_pipe( ialu_mem_imm );
7629 %}
7631 // Store Aligned Packed Byte XMM register to memory
7632 instruct storeA8B(memory mem, regXD src) %{
7633 predicate(UseSSE>=1);
7634 match(Set mem (Store8B mem src));
7635 ins_cost(145);
7636 format %{ "MOVQ $mem,$src\t! packed8B" %}
7637 ins_encode( movq_st(mem, src));
7638 ins_pipe( pipe_slow );
7639 %}
7641 // Store Aligned Packed Char/Short XMM register to memory
7642 instruct storeA4C(memory mem, regXD src) %{
7643 predicate(UseSSE>=1);
7644 match(Set mem (Store4C mem src));
7645 ins_cost(145);
7646 format %{ "MOVQ $mem,$src\t! packed4C" %}
7647 ins_encode( movq_st(mem, src));
7648 ins_pipe( pipe_slow );
7649 %}
7651 // Store Aligned Packed Integer XMM register to memory
7652 instruct storeA2I(memory mem, regXD src) %{
7653 predicate(UseSSE>=1);
7654 match(Set mem (Store2I mem src));
7655 ins_cost(145);
7656 format %{ "MOVQ $mem,$src\t! packed2I" %}
7657 ins_encode( movq_st(mem, src));
7658 ins_pipe( pipe_slow );
7659 %}
7661 // Store CMS card-mark Immediate
7662 instruct storeImmCM(memory mem, immI8 src) %{
7663 match(Set mem (StoreCM mem src));
7665 ins_cost(150);
7666 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7667 opcode(0xC6); /* C6 /0 */
7668 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7669 ins_pipe( ialu_mem_imm );
7670 %}
7672 // Store Double
7673 instruct storeD( memory mem, regDPR1 src) %{
7674 predicate(UseSSE<=1);
7675 match(Set mem (StoreD mem src));
7677 ins_cost(100);
7678 format %{ "FST_D $mem,$src" %}
7679 opcode(0xDD); /* DD /2 */
7680 ins_encode( enc_FP_store(mem,src) );
7681 ins_pipe( fpu_mem_reg );
7682 %}
7684 // Store double does rounding on x86
7685 instruct storeD_rounded( memory mem, regDPR1 src) %{
7686 predicate(UseSSE<=1);
7687 match(Set mem (StoreD mem (RoundDouble src)));
7689 ins_cost(100);
7690 format %{ "FST_D $mem,$src\t# round" %}
7691 opcode(0xDD); /* DD /2 */
7692 ins_encode( enc_FP_store(mem,src) );
7693 ins_pipe( fpu_mem_reg );
7694 %}
7696 // Store XMM register to memory (double-precision floating points)
7697 // MOVSD instruction
7698 instruct storeXD(memory mem, regXD src) %{
7699 predicate(UseSSE>=2);
7700 match(Set mem (StoreD mem src));
7701 ins_cost(95);
7702 format %{ "MOVSD $mem,$src" %}
7703 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7704 ins_pipe( pipe_slow );
7705 %}
7707 // Store XMM register to memory (single-precision floating point)
7708 // MOVSS instruction
7709 instruct storeX(memory mem, regX src) %{
7710 predicate(UseSSE>=1);
7711 match(Set mem (StoreF mem src));
7712 ins_cost(95);
7713 format %{ "MOVSS $mem,$src" %}
7714 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7715 ins_pipe( pipe_slow );
7716 %}
7718 // Store Aligned Packed Single Float XMM register to memory
7719 instruct storeA2F(memory mem, regXD src) %{
7720 predicate(UseSSE>=1);
7721 match(Set mem (Store2F mem src));
7722 ins_cost(145);
7723 format %{ "MOVQ $mem,$src\t! packed2F" %}
7724 ins_encode( movq_st(mem, src));
7725 ins_pipe( pipe_slow );
7726 %}
7728 // Store Float
7729 instruct storeF( memory mem, regFPR1 src) %{
7730 predicate(UseSSE==0);
7731 match(Set mem (StoreF mem src));
7733 ins_cost(100);
7734 format %{ "FST_S $mem,$src" %}
7735 opcode(0xD9); /* D9 /2 */
7736 ins_encode( enc_FP_store(mem,src) );
7737 ins_pipe( fpu_mem_reg );
7738 %}
7740 // Store Float does rounding on x86
7741 instruct storeF_rounded( memory mem, regFPR1 src) %{
7742 predicate(UseSSE==0);
7743 match(Set mem (StoreF mem (RoundFloat src)));
7745 ins_cost(100);
7746 format %{ "FST_S $mem,$src\t# round" %}
7747 opcode(0xD9); /* D9 /2 */
7748 ins_encode( enc_FP_store(mem,src) );
7749 ins_pipe( fpu_mem_reg );
7750 %}
7752 // Store Float does rounding on x86
7753 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7754 predicate(UseSSE<=1);
7755 match(Set mem (StoreF mem (ConvD2F src)));
7757 ins_cost(100);
7758 format %{ "FST_S $mem,$src\t# D-round" %}
7759 opcode(0xD9); /* D9 /2 */
7760 ins_encode( enc_FP_store(mem,src) );
7761 ins_pipe( fpu_mem_reg );
7762 %}
7764 // Store immediate Float value (it is faster than store from FPU register)
7765 // The instruction usage is guarded by predicate in operand immF().
7766 instruct storeF_imm( memory mem, immF src) %{
7767 match(Set mem (StoreF mem src));
7769 ins_cost(50);
7770 format %{ "MOV $mem,$src\t# store float" %}
7771 opcode(0xC7); /* C7 /0 */
7772 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7773 ins_pipe( ialu_mem_imm );
7774 %}
7776 // Store immediate Float value (it is faster than store from XMM register)
7777 // The instruction usage is guarded by predicate in operand immXF().
7778 instruct storeX_imm( memory mem, immXF src) %{
7779 match(Set mem (StoreF mem src));
7781 ins_cost(50);
7782 format %{ "MOV $mem,$src\t# store float" %}
7783 opcode(0xC7); /* C7 /0 */
7784 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7785 ins_pipe( ialu_mem_imm );
7786 %}
7788 // Store Integer to stack slot
7789 instruct storeSSI(stackSlotI dst, eRegI src) %{
7790 match(Set dst src);
7792 ins_cost(100);
7793 format %{ "MOV $dst,$src" %}
7794 opcode(0x89);
7795 ins_encode( OpcPRegSS( dst, src ) );
7796 ins_pipe( ialu_mem_reg );
7797 %}
7799 // Store Integer to stack slot
7800 instruct storeSSP(stackSlotP dst, eRegP src) %{
7801 match(Set dst src);
7803 ins_cost(100);
7804 format %{ "MOV $dst,$src" %}
7805 opcode(0x89);
7806 ins_encode( OpcPRegSS( dst, src ) );
7807 ins_pipe( ialu_mem_reg );
7808 %}
7810 // Store Long to stack slot
7811 instruct storeSSL(stackSlotL dst, eRegL src) %{
7812 match(Set dst src);
7814 ins_cost(200);
7815 format %{ "MOV $dst,$src.lo\n\t"
7816 "MOV $dst+4,$src.hi" %}
7817 opcode(0x89, 0x89);
7818 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7819 ins_pipe( ialu_mem_long_reg );
7820 %}
7822 //----------MemBar Instructions-----------------------------------------------
7823 // Memory barrier flavors
7825 instruct membar_acquire() %{
7826 match(MemBarAcquire);
7827 ins_cost(400);
7829 size(0);
7830 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7831 ins_encode();
7832 ins_pipe(empty);
7833 %}
7835 instruct membar_acquire_lock() %{
7836 match(MemBarAcquireLock);
7837 ins_cost(0);
7839 size(0);
7840 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7841 ins_encode( );
7842 ins_pipe(empty);
7843 %}
7845 instruct membar_release() %{
7846 match(MemBarRelease);
7847 ins_cost(400);
7849 size(0);
7850 format %{ "MEMBAR-release ! (empty encoding)" %}
7851 ins_encode( );
7852 ins_pipe(empty);
7853 %}
7855 instruct membar_release_lock() %{
7856 match(MemBarReleaseLock);
7857 ins_cost(0);
7859 size(0);
7860 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7861 ins_encode( );
7862 ins_pipe(empty);
7863 %}
7865 instruct membar_volatile(eFlagsReg cr) %{
7866 match(MemBarVolatile);
7867 effect(KILL cr);
7868 ins_cost(400);
7870 format %{
7871 $$template
7872 if (os::is_MP()) {
7873 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7874 } else {
7875 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7876 }
7877 %}
7878 ins_encode %{
7879 __ membar(Assembler::StoreLoad);
7880 %}
7881 ins_pipe(pipe_slow);
7882 %}
7884 instruct unnecessary_membar_volatile() %{
7885 match(MemBarVolatile);
7886 predicate(Matcher::post_store_load_barrier(n));
7887 ins_cost(0);
7889 size(0);
7890 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7891 ins_encode( );
7892 ins_pipe(empty);
7893 %}
7895 //----------Move Instructions--------------------------------------------------
7896 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7897 match(Set dst (CastX2P src));
7898 format %{ "# X2P $dst, $src" %}
7899 ins_encode( /*empty encoding*/ );
7900 ins_cost(0);
7901 ins_pipe(empty);
7902 %}
7904 instruct castP2X(eRegI dst, eRegP src ) %{
7905 match(Set dst (CastP2X src));
7906 ins_cost(50);
7907 format %{ "MOV $dst, $src\t# CastP2X" %}
7908 ins_encode( enc_Copy( dst, src) );
7909 ins_pipe( ialu_reg_reg );
7910 %}
7912 //----------Conditional Move---------------------------------------------------
7913 // Conditional move
7914 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
7915 predicate(!VM_Version::supports_cmov() );
7916 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7917 ins_cost(200);
7918 format %{ "J$cop,us skip\t# signed cmove\n\t"
7919 "MOV $dst,$src\n"
7920 "skip:" %}
7921 ins_encode %{
7922 Label Lskip;
7923 // Invert sense of branch from sense of CMOV
7924 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7925 __ movl($dst$$Register, $src$$Register);
7926 __ bind(Lskip);
7927 %}
7928 ins_pipe( pipe_cmov_reg );
7929 %}
7931 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
7932 predicate(!VM_Version::supports_cmov() );
7933 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7934 ins_cost(200);
7935 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7936 "MOV $dst,$src\n"
7937 "skip:" %}
7938 ins_encode %{
7939 Label Lskip;
7940 // Invert sense of branch from sense of CMOV
7941 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7942 __ movl($dst$$Register, $src$$Register);
7943 __ bind(Lskip);
7944 %}
7945 ins_pipe( pipe_cmov_reg );
7946 %}
7948 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7949 predicate(VM_Version::supports_cmov() );
7950 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7951 ins_cost(200);
7952 format %{ "CMOV$cop $dst,$src" %}
7953 opcode(0x0F,0x40);
7954 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7955 ins_pipe( pipe_cmov_reg );
7956 %}
7958 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7959 predicate(VM_Version::supports_cmov() );
7960 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7961 ins_cost(200);
7962 format %{ "CMOV$cop $dst,$src" %}
7963 opcode(0x0F,0x40);
7964 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7965 ins_pipe( pipe_cmov_reg );
7966 %}
7968 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7969 predicate(VM_Version::supports_cmov() );
7970 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7971 ins_cost(200);
7972 expand %{
7973 cmovI_regU(cop, cr, dst, src);
7974 %}
7975 %}
7977 // Conditional move
7978 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7979 predicate(VM_Version::supports_cmov() );
7980 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7981 ins_cost(250);
7982 format %{ "CMOV$cop $dst,$src" %}
7983 opcode(0x0F,0x40);
7984 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7985 ins_pipe( pipe_cmov_mem );
7986 %}
7988 // Conditional move
7989 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7990 predicate(VM_Version::supports_cmov() );
7991 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7992 ins_cost(250);
7993 format %{ "CMOV$cop $dst,$src" %}
7994 opcode(0x0F,0x40);
7995 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7996 ins_pipe( pipe_cmov_mem );
7997 %}
7999 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
8000 predicate(VM_Version::supports_cmov() );
8001 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
8002 ins_cost(250);
8003 expand %{
8004 cmovI_memU(cop, cr, dst, src);
8005 %}
8006 %}
8008 // Conditional move
8009 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8010 predicate(VM_Version::supports_cmov() );
8011 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8012 ins_cost(200);
8013 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8014 opcode(0x0F,0x40);
8015 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8016 ins_pipe( pipe_cmov_reg );
8017 %}
8019 // Conditional move (non-P6 version)
8020 // Note: a CMoveP is generated for stubs and native wrappers
8021 // regardless of whether we are on a P6, so we
8022 // emulate a cmov here
8023 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
8024 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8025 ins_cost(300);
8026 format %{ "Jn$cop skip\n\t"
8027 "MOV $dst,$src\t# pointer\n"
8028 "skip:" %}
8029 opcode(0x8b);
8030 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
8031 ins_pipe( pipe_cmov_reg );
8032 %}
8034 // Conditional move
8035 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
8036 predicate(VM_Version::supports_cmov() );
8037 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8038 ins_cost(200);
8039 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8040 opcode(0x0F,0x40);
8041 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8042 ins_pipe( pipe_cmov_reg );
8043 %}
8045 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
8046 predicate(VM_Version::supports_cmov() );
8047 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8048 ins_cost(200);
8049 expand %{
8050 cmovP_regU(cop, cr, dst, src);
8051 %}
8052 %}
8054 // DISABLED: Requires the ADLC to emit a bottom_type call that
8055 // correctly meets the two pointer arguments; one is an incoming
8056 // register but the other is a memory operand. ALSO appears to
8057 // be buggy with implicit null checks.
8058 //
8059 //// Conditional move
8060 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
8061 // predicate(VM_Version::supports_cmov() );
8062 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8063 // ins_cost(250);
8064 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8065 // opcode(0x0F,0x40);
8066 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8067 // ins_pipe( pipe_cmov_mem );
8068 //%}
8069 //
8070 //// Conditional move
8071 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
8072 // predicate(VM_Version::supports_cmov() );
8073 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8074 // ins_cost(250);
8075 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8076 // opcode(0x0F,0x40);
8077 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8078 // ins_pipe( pipe_cmov_mem );
8079 //%}
8081 // Conditional move
8082 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
8083 predicate(UseSSE<=1);
8084 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8085 ins_cost(200);
8086 format %{ "FCMOV$cop $dst,$src\t# double" %}
8087 opcode(0xDA);
8088 ins_encode( enc_cmov_d(cop,src) );
8089 ins_pipe( pipe_cmovD_reg );
8090 %}
8092 // Conditional move
8093 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
8094 predicate(UseSSE==0);
8095 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8096 ins_cost(200);
8097 format %{ "FCMOV$cop $dst,$src\t# float" %}
8098 opcode(0xDA);
8099 ins_encode( enc_cmov_d(cop,src) );
8100 ins_pipe( pipe_cmovD_reg );
8101 %}
8103 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8104 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
8105 predicate(UseSSE<=1);
8106 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8107 ins_cost(200);
8108 format %{ "Jn$cop skip\n\t"
8109 "MOV $dst,$src\t# double\n"
8110 "skip:" %}
8111 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8112 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
8113 ins_pipe( pipe_cmovD_reg );
8114 %}
8116 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8117 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
8118 predicate(UseSSE==0);
8119 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8120 ins_cost(200);
8121 format %{ "Jn$cop skip\n\t"
8122 "MOV $dst,$src\t# float\n"
8123 "skip:" %}
8124 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8125 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
8126 ins_pipe( pipe_cmovD_reg );
8127 %}
8129 // No CMOVE with SSE/SSE2
8130 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
8131 predicate (UseSSE>=1);
8132 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8133 ins_cost(200);
8134 format %{ "Jn$cop skip\n\t"
8135 "MOVSS $dst,$src\t# float\n"
8136 "skip:" %}
8137 ins_encode %{
8138 Label skip;
8139 // Invert sense of branch from sense of CMOV
8140 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8141 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8142 __ bind(skip);
8143 %}
8144 ins_pipe( pipe_slow );
8145 %}
8147 // No CMOVE with SSE/SSE2
8148 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8149 predicate (UseSSE>=2);
8150 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8151 ins_cost(200);
8152 format %{ "Jn$cop skip\n\t"
8153 "MOVSD $dst,$src\t# float\n"
8154 "skip:" %}
8155 ins_encode %{
8156 Label skip;
8157 // Invert sense of branch from sense of CMOV
8158 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8159 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8160 __ bind(skip);
8161 %}
8162 ins_pipe( pipe_slow );
8163 %}
8165 // unsigned version
8166 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8167 predicate (UseSSE>=1);
8168 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8169 ins_cost(200);
8170 format %{ "Jn$cop skip\n\t"
8171 "MOVSS $dst,$src\t# float\n"
8172 "skip:" %}
8173 ins_encode %{
8174 Label skip;
8175 // Invert sense of branch from sense of CMOV
8176 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8177 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8178 __ bind(skip);
8179 %}
8180 ins_pipe( pipe_slow );
8181 %}
8183 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8184 predicate (UseSSE>=1);
8185 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8186 ins_cost(200);
8187 expand %{
8188 fcmovX_regU(cop, cr, dst, src);
8189 %}
8190 %}
8192 // unsigned version
8193 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8194 predicate (UseSSE>=2);
8195 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8196 ins_cost(200);
8197 format %{ "Jn$cop skip\n\t"
8198 "MOVSD $dst,$src\t# float\n"
8199 "skip:" %}
8200 ins_encode %{
8201 Label skip;
8202 // Invert sense of branch from sense of CMOV
8203 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8204 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8205 __ bind(skip);
8206 %}
8207 ins_pipe( pipe_slow );
8208 %}
8210 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8211 predicate (UseSSE>=2);
8212 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8213 ins_cost(200);
8214 expand %{
8215 fcmovXD_regU(cop, cr, dst, src);
8216 %}
8217 %}
8219 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8220 predicate(VM_Version::supports_cmov() );
8221 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8222 ins_cost(200);
8223 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8224 "CMOV$cop $dst.hi,$src.hi" %}
8225 opcode(0x0F,0x40);
8226 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8227 ins_pipe( pipe_cmov_reg_long );
8228 %}
8230 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8231 predicate(VM_Version::supports_cmov() );
8232 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8233 ins_cost(200);
8234 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8235 "CMOV$cop $dst.hi,$src.hi" %}
8236 opcode(0x0F,0x40);
8237 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8238 ins_pipe( pipe_cmov_reg_long );
8239 %}
8241 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8242 predicate(VM_Version::supports_cmov() );
8243 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8244 ins_cost(200);
8245 expand %{
8246 cmovL_regU(cop, cr, dst, src);
8247 %}
8248 %}
8250 //----------Arithmetic Instructions--------------------------------------------
8251 //----------Addition Instructions----------------------------------------------
8252 // Integer Addition Instructions
8253 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8254 match(Set dst (AddI dst src));
8255 effect(KILL cr);
8257 size(2);
8258 format %{ "ADD $dst,$src" %}
8259 opcode(0x03);
8260 ins_encode( OpcP, RegReg( dst, src) );
8261 ins_pipe( ialu_reg_reg );
8262 %}
8264 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8265 match(Set dst (AddI dst src));
8266 effect(KILL cr);
8268 format %{ "ADD $dst,$src" %}
8269 opcode(0x81, 0x00); /* /0 id */
8270 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8271 ins_pipe( ialu_reg );
8272 %}
8274 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8275 predicate(UseIncDec);
8276 match(Set dst (AddI dst src));
8277 effect(KILL cr);
8279 size(1);
8280 format %{ "INC $dst" %}
8281 opcode(0x40); /* */
8282 ins_encode( Opc_plus( primary, dst ) );
8283 ins_pipe( ialu_reg );
8284 %}
8286 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8287 match(Set dst (AddI src0 src1));
8288 ins_cost(110);
8290 format %{ "LEA $dst,[$src0 + $src1]" %}
8291 opcode(0x8D); /* 0x8D /r */
8292 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8293 ins_pipe( ialu_reg_reg );
8294 %}
8296 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8297 match(Set dst (AddP src0 src1));
8298 ins_cost(110);
8300 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8301 opcode(0x8D); /* 0x8D /r */
8302 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8303 ins_pipe( ialu_reg_reg );
8304 %}
8306 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8307 predicate(UseIncDec);
8308 match(Set dst (AddI dst src));
8309 effect(KILL cr);
8311 size(1);
8312 format %{ "DEC $dst" %}
8313 opcode(0x48); /* */
8314 ins_encode( Opc_plus( primary, dst ) );
8315 ins_pipe( ialu_reg );
8316 %}
8318 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8319 match(Set dst (AddP dst src));
8320 effect(KILL cr);
8322 size(2);
8323 format %{ "ADD $dst,$src" %}
8324 opcode(0x03);
8325 ins_encode( OpcP, RegReg( dst, src) );
8326 ins_pipe( ialu_reg_reg );
8327 %}
8329 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8330 match(Set dst (AddP dst src));
8331 effect(KILL cr);
8333 format %{ "ADD $dst,$src" %}
8334 opcode(0x81,0x00); /* Opcode 81 /0 id */
8335 // ins_encode( RegImm( dst, src) );
8336 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8337 ins_pipe( ialu_reg );
8338 %}
8340 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8341 match(Set dst (AddI dst (LoadI src)));
8342 effect(KILL cr);
8344 ins_cost(125);
8345 format %{ "ADD $dst,$src" %}
8346 opcode(0x03);
8347 ins_encode( OpcP, RegMem( dst, src) );
8348 ins_pipe( ialu_reg_mem );
8349 %}
8351 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8352 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8353 effect(KILL cr);
8355 ins_cost(150);
8356 format %{ "ADD $dst,$src" %}
8357 opcode(0x01); /* Opcode 01 /r */
8358 ins_encode( OpcP, RegMem( src, dst ) );
8359 ins_pipe( ialu_mem_reg );
8360 %}
8362 // Add Memory with Immediate
8363 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8364 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8365 effect(KILL cr);
8367 ins_cost(125);
8368 format %{ "ADD $dst,$src" %}
8369 opcode(0x81); /* Opcode 81 /0 id */
8370 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8371 ins_pipe( ialu_mem_imm );
8372 %}
8374 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8375 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8376 effect(KILL cr);
8378 ins_cost(125);
8379 format %{ "INC $dst" %}
8380 opcode(0xFF); /* Opcode FF /0 */
8381 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8382 ins_pipe( ialu_mem_imm );
8383 %}
8385 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8386 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8387 effect(KILL cr);
8389 ins_cost(125);
8390 format %{ "DEC $dst" %}
8391 opcode(0xFF); /* Opcode FF /1 */
8392 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8393 ins_pipe( ialu_mem_imm );
8394 %}
8397 instruct checkCastPP( eRegP dst ) %{
8398 match(Set dst (CheckCastPP dst));
8400 size(0);
8401 format %{ "#checkcastPP of $dst" %}
8402 ins_encode( /*empty encoding*/ );
8403 ins_pipe( empty );
8404 %}
8406 instruct castPP( eRegP dst ) %{
8407 match(Set dst (CastPP dst));
8408 format %{ "#castPP of $dst" %}
8409 ins_encode( /*empty encoding*/ );
8410 ins_pipe( empty );
8411 %}
8413 instruct castII( eRegI dst ) %{
8414 match(Set dst (CastII dst));
8415 format %{ "#castII of $dst" %}
8416 ins_encode( /*empty encoding*/ );
8417 ins_cost(0);
8418 ins_pipe( empty );
8419 %}
8422 // Load-locked - same as a regular pointer load when used with compare-swap
8423 instruct loadPLocked(eRegP dst, memory mem) %{
8424 match(Set dst (LoadPLocked mem));
8426 ins_cost(125);
8427 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8428 opcode(0x8B);
8429 ins_encode( OpcP, RegMem(dst,mem));
8430 ins_pipe( ialu_reg_mem );
8431 %}
8433 // LoadLong-locked - same as a volatile long load when used with compare-swap
8434 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8435 predicate(UseSSE<=1);
8436 match(Set dst (LoadLLocked mem));
8438 ins_cost(200);
8439 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8440 "FISTp $dst" %}
8441 ins_encode(enc_loadL_volatile(mem,dst));
8442 ins_pipe( fpu_reg_mem );
8443 %}
8445 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8446 predicate(UseSSE>=2);
8447 match(Set dst (LoadLLocked mem));
8448 effect(TEMP tmp);
8449 ins_cost(180);
8450 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8451 "MOVSD $dst,$tmp" %}
8452 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8453 ins_pipe( pipe_slow );
8454 %}
8456 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8457 predicate(UseSSE>=2);
8458 match(Set dst (LoadLLocked mem));
8459 effect(TEMP tmp);
8460 ins_cost(160);
8461 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8462 "MOVD $dst.lo,$tmp\n\t"
8463 "PSRLQ $tmp,32\n\t"
8464 "MOVD $dst.hi,$tmp" %}
8465 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8466 ins_pipe( pipe_slow );
8467 %}
8469 // Conditional-store of the updated heap-top.
8470 // Used during allocation of the shared heap.
8471 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8472 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8473 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8474 // EAX is killed if there is contention, but then it's also unused.
8475 // In the common case of no contention, EAX holds the new oop address.
8476 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8477 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8478 ins_pipe( pipe_cmpxchg );
8479 %}
8481 // Conditional-store of an int value.
8482 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8483 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8484 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8485 effect(KILL oldval);
8486 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8487 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8488 ins_pipe( pipe_cmpxchg );
8489 %}
8491 // Conditional-store of a long value.
8492 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8493 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8494 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8495 effect(KILL oldval);
8496 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8497 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8498 "XCHG EBX,ECX"
8499 %}
8500 ins_encode %{
8501 // Note: we need to swap rbx, and rcx before and after the
8502 // cmpxchg8 instruction because the instruction uses
8503 // rcx as the high order word of the new value to store but
8504 // our register encoding uses rbx.
8505 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8506 if( os::is_MP() )
8507 __ lock();
8508 __ cmpxchg8($mem$$Address);
8509 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8510 %}
8511 ins_pipe( pipe_cmpxchg );
8512 %}
8514 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8516 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8517 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8518 effect(KILL cr, KILL oldval);
8519 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8520 "MOV $res,0\n\t"
8521 "JNE,s fail\n\t"
8522 "MOV $res,1\n"
8523 "fail:" %}
8524 ins_encode( enc_cmpxchg8(mem_ptr),
8525 enc_flags_ne_to_boolean(res) );
8526 ins_pipe( pipe_cmpxchg );
8527 %}
8529 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8530 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8531 effect(KILL cr, KILL oldval);
8532 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8533 "MOV $res,0\n\t"
8534 "JNE,s fail\n\t"
8535 "MOV $res,1\n"
8536 "fail:" %}
8537 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8538 ins_pipe( pipe_cmpxchg );
8539 %}
8541 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8542 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8543 effect(KILL cr, KILL oldval);
8544 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8545 "MOV $res,0\n\t"
8546 "JNE,s fail\n\t"
8547 "MOV $res,1\n"
8548 "fail:" %}
8549 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8550 ins_pipe( pipe_cmpxchg );
8551 %}
8553 //----------Subtraction Instructions-------------------------------------------
8554 // Integer Subtraction Instructions
8555 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8556 match(Set dst (SubI dst src));
8557 effect(KILL cr);
8559 size(2);
8560 format %{ "SUB $dst,$src" %}
8561 opcode(0x2B);
8562 ins_encode( OpcP, RegReg( dst, src) );
8563 ins_pipe( ialu_reg_reg );
8564 %}
8566 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8567 match(Set dst (SubI dst src));
8568 effect(KILL cr);
8570 format %{ "SUB $dst,$src" %}
8571 opcode(0x81,0x05); /* Opcode 81 /5 */
8572 // ins_encode( RegImm( dst, src) );
8573 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8574 ins_pipe( ialu_reg );
8575 %}
8577 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8578 match(Set dst (SubI dst (LoadI src)));
8579 effect(KILL cr);
8581 ins_cost(125);
8582 format %{ "SUB $dst,$src" %}
8583 opcode(0x2B);
8584 ins_encode( OpcP, RegMem( dst, src) );
8585 ins_pipe( ialu_reg_mem );
8586 %}
8588 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8589 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8590 effect(KILL cr);
8592 ins_cost(150);
8593 format %{ "SUB $dst,$src" %}
8594 opcode(0x29); /* Opcode 29 /r */
8595 ins_encode( OpcP, RegMem( src, dst ) );
8596 ins_pipe( ialu_mem_reg );
8597 %}
8599 // Subtract from a pointer
8600 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8601 match(Set dst (AddP dst (SubI zero src)));
8602 effect(KILL cr);
8604 size(2);
8605 format %{ "SUB $dst,$src" %}
8606 opcode(0x2B);
8607 ins_encode( OpcP, RegReg( dst, src) );
8608 ins_pipe( ialu_reg_reg );
8609 %}
8611 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8612 match(Set dst (SubI zero dst));
8613 effect(KILL cr);
8615 size(2);
8616 format %{ "NEG $dst" %}
8617 opcode(0xF7,0x03); // Opcode F7 /3
8618 ins_encode( OpcP, RegOpc( dst ) );
8619 ins_pipe( ialu_reg );
8620 %}
8623 //----------Multiplication/Division Instructions-------------------------------
8624 // Integer Multiplication Instructions
8625 // Multiply Register
8626 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8627 match(Set dst (MulI dst src));
8628 effect(KILL cr);
8630 size(3);
8631 ins_cost(300);
8632 format %{ "IMUL $dst,$src" %}
8633 opcode(0xAF, 0x0F);
8634 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8635 ins_pipe( ialu_reg_reg_alu0 );
8636 %}
8638 // Multiply 32-bit Immediate
8639 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8640 match(Set dst (MulI src imm));
8641 effect(KILL cr);
8643 ins_cost(300);
8644 format %{ "IMUL $dst,$src,$imm" %}
8645 opcode(0x69); /* 69 /r id */
8646 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8647 ins_pipe( ialu_reg_reg_alu0 );
8648 %}
8650 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8651 match(Set dst src);
8652 effect(KILL cr);
8654 // Note that this is artificially increased to make it more expensive than loadConL
8655 ins_cost(250);
8656 format %{ "MOV EAX,$src\t// low word only" %}
8657 opcode(0xB8);
8658 ins_encode( LdImmL_Lo(dst, src) );
8659 ins_pipe( ialu_reg_fat );
8660 %}
8662 // Multiply by 32-bit Immediate, taking the shifted high order results
8663 // (special case for shift by 32)
8664 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8665 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8666 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8667 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8668 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8669 effect(USE src1, KILL cr);
8671 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8672 ins_cost(0*100 + 1*400 - 150);
8673 format %{ "IMUL EDX:EAX,$src1" %}
8674 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8675 ins_pipe( pipe_slow );
8676 %}
8678 // Multiply by 32-bit Immediate, taking the shifted high order results
8679 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8680 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8681 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8682 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8683 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8684 effect(USE src1, KILL cr);
8686 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8687 ins_cost(1*100 + 1*400 - 150);
8688 format %{ "IMUL EDX:EAX,$src1\n\t"
8689 "SAR EDX,$cnt-32" %}
8690 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8691 ins_pipe( pipe_slow );
8692 %}
8694 // Multiply Memory 32-bit Immediate
8695 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8696 match(Set dst (MulI (LoadI src) imm));
8697 effect(KILL cr);
8699 ins_cost(300);
8700 format %{ "IMUL $dst,$src,$imm" %}
8701 opcode(0x69); /* 69 /r id */
8702 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8703 ins_pipe( ialu_reg_mem_alu0 );
8704 %}
8706 // Multiply Memory
8707 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8708 match(Set dst (MulI dst (LoadI src)));
8709 effect(KILL cr);
8711 ins_cost(350);
8712 format %{ "IMUL $dst,$src" %}
8713 opcode(0xAF, 0x0F);
8714 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8715 ins_pipe( ialu_reg_mem_alu0 );
8716 %}
8718 // Multiply Register Int to Long
8719 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8720 // Basic Idea: long = (long)int * (long)int
8721 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8722 effect(DEF dst, USE src, USE src1, KILL flags);
8724 ins_cost(300);
8725 format %{ "IMUL $dst,$src1" %}
8727 ins_encode( long_int_multiply( dst, src1 ) );
8728 ins_pipe( ialu_reg_reg_alu0 );
8729 %}
8731 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8732 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8733 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8734 effect(KILL flags);
8736 ins_cost(300);
8737 format %{ "MUL $dst,$src1" %}
8739 ins_encode( long_uint_multiply(dst, src1) );
8740 ins_pipe( ialu_reg_reg_alu0 );
8741 %}
8743 // Multiply Register Long
8744 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8745 match(Set dst (MulL dst src));
8746 effect(KILL cr, TEMP tmp);
8747 ins_cost(4*100+3*400);
8748 // Basic idea: lo(result) = lo(x_lo * y_lo)
8749 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8750 format %{ "MOV $tmp,$src.lo\n\t"
8751 "IMUL $tmp,EDX\n\t"
8752 "MOV EDX,$src.hi\n\t"
8753 "IMUL EDX,EAX\n\t"
8754 "ADD $tmp,EDX\n\t"
8755 "MUL EDX:EAX,$src.lo\n\t"
8756 "ADD EDX,$tmp" %}
8757 ins_encode( long_multiply( dst, src, tmp ) );
8758 ins_pipe( pipe_slow );
8759 %}
8761 // Multiply Register Long where the left operand's high 32 bits are zero
8762 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8763 predicate(is_operand_hi32_zero(n->in(1)));
8764 match(Set dst (MulL dst src));
8765 effect(KILL cr, TEMP tmp);
8766 ins_cost(2*100+2*400);
8767 // Basic idea: lo(result) = lo(x_lo * y_lo)
8768 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8769 format %{ "MOV $tmp,$src.hi\n\t"
8770 "IMUL $tmp,EAX\n\t"
8771 "MUL EDX:EAX,$src.lo\n\t"
8772 "ADD EDX,$tmp" %}
8773 ins_encode %{
8774 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8775 __ imull($tmp$$Register, rax);
8776 __ mull($src$$Register);
8777 __ addl(rdx, $tmp$$Register);
8778 %}
8779 ins_pipe( pipe_slow );
8780 %}
8782 // Multiply Register Long where the right operand's high 32 bits are zero
8783 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8784 predicate(is_operand_hi32_zero(n->in(2)));
8785 match(Set dst (MulL dst src));
8786 effect(KILL cr, TEMP tmp);
8787 ins_cost(2*100+2*400);
8788 // Basic idea: lo(result) = lo(x_lo * y_lo)
8789 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8790 format %{ "MOV $tmp,$src.lo\n\t"
8791 "IMUL $tmp,EDX\n\t"
8792 "MUL EDX:EAX,$src.lo\n\t"
8793 "ADD EDX,$tmp" %}
8794 ins_encode %{
8795 __ movl($tmp$$Register, $src$$Register);
8796 __ imull($tmp$$Register, rdx);
8797 __ mull($src$$Register);
8798 __ addl(rdx, $tmp$$Register);
8799 %}
8800 ins_pipe( pipe_slow );
8801 %}
8803 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8804 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8805 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8806 match(Set dst (MulL dst src));
8807 effect(KILL cr);
8808 ins_cost(1*400);
8809 // Basic idea: lo(result) = lo(x_lo * y_lo)
8810 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8811 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8812 ins_encode %{
8813 __ mull($src$$Register);
8814 %}
8815 ins_pipe( pipe_slow );
8816 %}
8818 // Multiply Register Long by small constant
8819 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8820 match(Set dst (MulL dst src));
8821 effect(KILL cr, TEMP tmp);
8822 ins_cost(2*100+2*400);
8823 size(12);
8824 // Basic idea: lo(result) = lo(src * EAX)
8825 // hi(result) = hi(src * EAX) + lo(src * EDX)
8826 format %{ "IMUL $tmp,EDX,$src\n\t"
8827 "MOV EDX,$src\n\t"
8828 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8829 "ADD EDX,$tmp" %}
8830 ins_encode( long_multiply_con( dst, src, tmp ) );
8831 ins_pipe( pipe_slow );
8832 %}
8834 // Integer DIV with Register
8835 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8836 match(Set rax (DivI rax div));
8837 effect(KILL rdx, KILL cr);
8838 size(26);
8839 ins_cost(30*100+10*100);
8840 format %{ "CMP EAX,0x80000000\n\t"
8841 "JNE,s normal\n\t"
8842 "XOR EDX,EDX\n\t"
8843 "CMP ECX,-1\n\t"
8844 "JE,s done\n"
8845 "normal: CDQ\n\t"
8846 "IDIV $div\n\t"
8847 "done:" %}
8848 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8849 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8850 ins_pipe( ialu_reg_reg_alu0 );
8851 %}
8853 // Divide Register Long
8854 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8855 match(Set dst (DivL src1 src2));
8856 effect( KILL cr, KILL cx, KILL bx );
8857 ins_cost(10000);
8858 format %{ "PUSH $src1.hi\n\t"
8859 "PUSH $src1.lo\n\t"
8860 "PUSH $src2.hi\n\t"
8861 "PUSH $src2.lo\n\t"
8862 "CALL SharedRuntime::ldiv\n\t"
8863 "ADD ESP,16" %}
8864 ins_encode( long_div(src1,src2) );
8865 ins_pipe( pipe_slow );
8866 %}
8868 // Integer DIVMOD with Register, both quotient and mod results
8869 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8870 match(DivModI rax div);
8871 effect(KILL cr);
8872 size(26);
8873 ins_cost(30*100+10*100);
8874 format %{ "CMP EAX,0x80000000\n\t"
8875 "JNE,s normal\n\t"
8876 "XOR EDX,EDX\n\t"
8877 "CMP ECX,-1\n\t"
8878 "JE,s done\n"
8879 "normal: CDQ\n\t"
8880 "IDIV $div\n\t"
8881 "done:" %}
8882 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8883 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8884 ins_pipe( pipe_slow );
8885 %}
8887 // Integer MOD with Register
8888 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8889 match(Set rdx (ModI rax div));
8890 effect(KILL rax, KILL cr);
8892 size(26);
8893 ins_cost(300);
8894 format %{ "CDQ\n\t"
8895 "IDIV $div" %}
8896 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8897 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8898 ins_pipe( ialu_reg_reg_alu0 );
8899 %}
8901 // Remainder Register Long
8902 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8903 match(Set dst (ModL src1 src2));
8904 effect( KILL cr, KILL cx, KILL bx );
8905 ins_cost(10000);
8906 format %{ "PUSH $src1.hi\n\t"
8907 "PUSH $src1.lo\n\t"
8908 "PUSH $src2.hi\n\t"
8909 "PUSH $src2.lo\n\t"
8910 "CALL SharedRuntime::lrem\n\t"
8911 "ADD ESP,16" %}
8912 ins_encode( long_mod(src1,src2) );
8913 ins_pipe( pipe_slow );
8914 %}
8916 // Divide Register Long (no special case since divisor != -1)
8917 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8918 match(Set dst (DivL dst imm));
8919 effect( TEMP tmp, TEMP tmp2, KILL cr );
8920 ins_cost(1000);
8921 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8922 "XOR $tmp2,$tmp2\n\t"
8923 "CMP $tmp,EDX\n\t"
8924 "JA,s fast\n\t"
8925 "MOV $tmp2,EAX\n\t"
8926 "MOV EAX,EDX\n\t"
8927 "MOV EDX,0\n\t"
8928 "JLE,s pos\n\t"
8929 "LNEG EAX : $tmp2\n\t"
8930 "DIV $tmp # unsigned division\n\t"
8931 "XCHG EAX,$tmp2\n\t"
8932 "DIV $tmp\n\t"
8933 "LNEG $tmp2 : EAX\n\t"
8934 "JMP,s done\n"
8935 "pos:\n\t"
8936 "DIV $tmp\n\t"
8937 "XCHG EAX,$tmp2\n"
8938 "fast:\n\t"
8939 "DIV $tmp\n"
8940 "done:\n\t"
8941 "MOV EDX,$tmp2\n\t"
8942 "NEG EDX:EAX # if $imm < 0" %}
8943 ins_encode %{
8944 int con = (int)$imm$$constant;
8945 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8946 int pcon = (con > 0) ? con : -con;
8947 Label Lfast, Lpos, Ldone;
8949 __ movl($tmp$$Register, pcon);
8950 __ xorl($tmp2$$Register,$tmp2$$Register);
8951 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8952 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8954 __ movl($tmp2$$Register, $dst$$Register); // save
8955 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8956 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8957 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8959 // Negative dividend.
8960 // convert value to positive to use unsigned division
8961 __ lneg($dst$$Register, $tmp2$$Register);
8962 __ divl($tmp$$Register);
8963 __ xchgl($dst$$Register, $tmp2$$Register);
8964 __ divl($tmp$$Register);
8965 // revert result back to negative
8966 __ lneg($tmp2$$Register, $dst$$Register);
8967 __ jmpb(Ldone);
8969 __ bind(Lpos);
8970 __ divl($tmp$$Register); // Use unsigned division
8971 __ xchgl($dst$$Register, $tmp2$$Register);
8972 // Fallthrow for final divide, tmp2 has 32 bit hi result
8974 __ bind(Lfast);
8975 // fast path: src is positive
8976 __ divl($tmp$$Register); // Use unsigned division
8978 __ bind(Ldone);
8979 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8980 if (con < 0) {
8981 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8982 }
8983 %}
8984 ins_pipe( pipe_slow );
8985 %}
8987 // Remainder Register Long (remainder fit into 32 bits)
8988 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8989 match(Set dst (ModL dst imm));
8990 effect( TEMP tmp, TEMP tmp2, KILL cr );
8991 ins_cost(1000);
8992 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8993 "CMP $tmp,EDX\n\t"
8994 "JA,s fast\n\t"
8995 "MOV $tmp2,EAX\n\t"
8996 "MOV EAX,EDX\n\t"
8997 "MOV EDX,0\n\t"
8998 "JLE,s pos\n\t"
8999 "LNEG EAX : $tmp2\n\t"
9000 "DIV $tmp # unsigned division\n\t"
9001 "MOV EAX,$tmp2\n\t"
9002 "DIV $tmp\n\t"
9003 "NEG EDX\n\t"
9004 "JMP,s done\n"
9005 "pos:\n\t"
9006 "DIV $tmp\n\t"
9007 "MOV EAX,$tmp2\n"
9008 "fast:\n\t"
9009 "DIV $tmp\n"
9010 "done:\n\t"
9011 "MOV EAX,EDX\n\t"
9012 "SAR EDX,31\n\t" %}
9013 ins_encode %{
9014 int con = (int)$imm$$constant;
9015 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
9016 int pcon = (con > 0) ? con : -con;
9017 Label Lfast, Lpos, Ldone;
9019 __ movl($tmp$$Register, pcon);
9020 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
9021 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
9023 __ movl($tmp2$$Register, $dst$$Register); // save
9024 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
9025 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
9026 __ jccb(Assembler::lessEqual, Lpos); // result is positive
9028 // Negative dividend.
9029 // convert value to positive to use unsigned division
9030 __ lneg($dst$$Register, $tmp2$$Register);
9031 __ divl($tmp$$Register);
9032 __ movl($dst$$Register, $tmp2$$Register);
9033 __ divl($tmp$$Register);
9034 // revert remainder back to negative
9035 __ negl(HIGH_FROM_LOW($dst$$Register));
9036 __ jmpb(Ldone);
9038 __ bind(Lpos);
9039 __ divl($tmp$$Register);
9040 __ movl($dst$$Register, $tmp2$$Register);
9042 __ bind(Lfast);
9043 // fast path: src is positive
9044 __ divl($tmp$$Register);
9046 __ bind(Ldone);
9047 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
9048 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
9050 %}
9051 ins_pipe( pipe_slow );
9052 %}
9054 // Integer Shift Instructions
9055 // Shift Left by one
9056 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9057 match(Set dst (LShiftI dst shift));
9058 effect(KILL cr);
9060 size(2);
9061 format %{ "SHL $dst,$shift" %}
9062 opcode(0xD1, 0x4); /* D1 /4 */
9063 ins_encode( OpcP, RegOpc( dst ) );
9064 ins_pipe( ialu_reg );
9065 %}
9067 // Shift Left by 8-bit immediate
9068 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9069 match(Set dst (LShiftI dst shift));
9070 effect(KILL cr);
9072 size(3);
9073 format %{ "SHL $dst,$shift" %}
9074 opcode(0xC1, 0x4); /* C1 /4 ib */
9075 ins_encode( RegOpcImm( dst, shift) );
9076 ins_pipe( ialu_reg );
9077 %}
9079 // Shift Left by variable
9080 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9081 match(Set dst (LShiftI dst shift));
9082 effect(KILL cr);
9084 size(2);
9085 format %{ "SHL $dst,$shift" %}
9086 opcode(0xD3, 0x4); /* D3 /4 */
9087 ins_encode( OpcP, RegOpc( dst ) );
9088 ins_pipe( ialu_reg_reg );
9089 %}
9091 // Arithmetic shift right by one
9092 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9093 match(Set dst (RShiftI dst shift));
9094 effect(KILL cr);
9096 size(2);
9097 format %{ "SAR $dst,$shift" %}
9098 opcode(0xD1, 0x7); /* D1 /7 */
9099 ins_encode( OpcP, RegOpc( dst ) );
9100 ins_pipe( ialu_reg );
9101 %}
9103 // Arithmetic shift right by one
9104 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
9105 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9106 effect(KILL cr);
9107 format %{ "SAR $dst,$shift" %}
9108 opcode(0xD1, 0x7); /* D1 /7 */
9109 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
9110 ins_pipe( ialu_mem_imm );
9111 %}
9113 // Arithmetic Shift Right by 8-bit immediate
9114 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9115 match(Set dst (RShiftI dst shift));
9116 effect(KILL cr);
9118 size(3);
9119 format %{ "SAR $dst,$shift" %}
9120 opcode(0xC1, 0x7); /* C1 /7 ib */
9121 ins_encode( RegOpcImm( dst, shift ) );
9122 ins_pipe( ialu_mem_imm );
9123 %}
9125 // Arithmetic Shift Right by 8-bit immediate
9126 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
9127 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9128 effect(KILL cr);
9130 format %{ "SAR $dst,$shift" %}
9131 opcode(0xC1, 0x7); /* C1 /7 ib */
9132 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
9133 ins_pipe( ialu_mem_imm );
9134 %}
9136 // Arithmetic Shift Right by variable
9137 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9138 match(Set dst (RShiftI dst shift));
9139 effect(KILL cr);
9141 size(2);
9142 format %{ "SAR $dst,$shift" %}
9143 opcode(0xD3, 0x7); /* D3 /7 */
9144 ins_encode( OpcP, RegOpc( dst ) );
9145 ins_pipe( ialu_reg_reg );
9146 %}
9148 // Logical shift right by one
9149 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9150 match(Set dst (URShiftI dst shift));
9151 effect(KILL cr);
9153 size(2);
9154 format %{ "SHR $dst,$shift" %}
9155 opcode(0xD1, 0x5); /* D1 /5 */
9156 ins_encode( OpcP, RegOpc( dst ) );
9157 ins_pipe( ialu_reg );
9158 %}
9160 // Logical Shift Right by 8-bit immediate
9161 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9162 match(Set dst (URShiftI dst shift));
9163 effect(KILL cr);
9165 size(3);
9166 format %{ "SHR $dst,$shift" %}
9167 opcode(0xC1, 0x5); /* C1 /5 ib */
9168 ins_encode( RegOpcImm( dst, shift) );
9169 ins_pipe( ialu_reg );
9170 %}
9173 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9174 // This idiom is used by the compiler for the i2b bytecode.
9175 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
9176 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9178 size(3);
9179 format %{ "MOVSX $dst,$src :8" %}
9180 ins_encode %{
9181 __ movsbl($dst$$Register, $src$$Register);
9182 %}
9183 ins_pipe(ialu_reg_reg);
9184 %}
9186 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9187 // This idiom is used by the compiler the i2s bytecode.
9188 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
9189 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9191 size(3);
9192 format %{ "MOVSX $dst,$src :16" %}
9193 ins_encode %{
9194 __ movswl($dst$$Register, $src$$Register);
9195 %}
9196 ins_pipe(ialu_reg_reg);
9197 %}
9200 // Logical Shift Right by variable
9201 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9202 match(Set dst (URShiftI dst shift));
9203 effect(KILL cr);
9205 size(2);
9206 format %{ "SHR $dst,$shift" %}
9207 opcode(0xD3, 0x5); /* D3 /5 */
9208 ins_encode( OpcP, RegOpc( dst ) );
9209 ins_pipe( ialu_reg_reg );
9210 %}
9213 //----------Logical Instructions-----------------------------------------------
9214 //----------Integer Logical Instructions---------------------------------------
9215 // And Instructions
9216 // And Register with Register
9217 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9218 match(Set dst (AndI dst src));
9219 effect(KILL cr);
9221 size(2);
9222 format %{ "AND $dst,$src" %}
9223 opcode(0x23);
9224 ins_encode( OpcP, RegReg( dst, src) );
9225 ins_pipe( ialu_reg_reg );
9226 %}
9228 // And Register with Immediate
9229 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9230 match(Set dst (AndI dst src));
9231 effect(KILL cr);
9233 format %{ "AND $dst,$src" %}
9234 opcode(0x81,0x04); /* Opcode 81 /4 */
9235 // ins_encode( RegImm( dst, src) );
9236 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9237 ins_pipe( ialu_reg );
9238 %}
9240 // And Register with Memory
9241 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9242 match(Set dst (AndI dst (LoadI src)));
9243 effect(KILL cr);
9245 ins_cost(125);
9246 format %{ "AND $dst,$src" %}
9247 opcode(0x23);
9248 ins_encode( OpcP, RegMem( dst, src) );
9249 ins_pipe( ialu_reg_mem );
9250 %}
9252 // And Memory with Register
9253 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9254 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9255 effect(KILL cr);
9257 ins_cost(150);
9258 format %{ "AND $dst,$src" %}
9259 opcode(0x21); /* Opcode 21 /r */
9260 ins_encode( OpcP, RegMem( src, dst ) );
9261 ins_pipe( ialu_mem_reg );
9262 %}
9264 // And Memory with Immediate
9265 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9266 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9267 effect(KILL cr);
9269 ins_cost(125);
9270 format %{ "AND $dst,$src" %}
9271 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9272 // ins_encode( MemImm( dst, src) );
9273 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9274 ins_pipe( ialu_mem_imm );
9275 %}
9277 // Or Instructions
9278 // Or Register with Register
9279 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9280 match(Set dst (OrI dst src));
9281 effect(KILL cr);
9283 size(2);
9284 format %{ "OR $dst,$src" %}
9285 opcode(0x0B);
9286 ins_encode( OpcP, RegReg( dst, src) );
9287 ins_pipe( ialu_reg_reg );
9288 %}
9290 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9291 match(Set dst (OrI dst (CastP2X src)));
9292 effect(KILL cr);
9294 size(2);
9295 format %{ "OR $dst,$src" %}
9296 opcode(0x0B);
9297 ins_encode( OpcP, RegReg( dst, src) );
9298 ins_pipe( ialu_reg_reg );
9299 %}
9302 // Or Register with Immediate
9303 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9304 match(Set dst (OrI dst src));
9305 effect(KILL cr);
9307 format %{ "OR $dst,$src" %}
9308 opcode(0x81,0x01); /* Opcode 81 /1 id */
9309 // ins_encode( RegImm( dst, src) );
9310 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9311 ins_pipe( ialu_reg );
9312 %}
9314 // Or Register with Memory
9315 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9316 match(Set dst (OrI dst (LoadI src)));
9317 effect(KILL cr);
9319 ins_cost(125);
9320 format %{ "OR $dst,$src" %}
9321 opcode(0x0B);
9322 ins_encode( OpcP, RegMem( dst, src) );
9323 ins_pipe( ialu_reg_mem );
9324 %}
9326 // Or Memory with Register
9327 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9328 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9329 effect(KILL cr);
9331 ins_cost(150);
9332 format %{ "OR $dst,$src" %}
9333 opcode(0x09); /* Opcode 09 /r */
9334 ins_encode( OpcP, RegMem( src, dst ) );
9335 ins_pipe( ialu_mem_reg );
9336 %}
9338 // Or Memory with Immediate
9339 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9340 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9341 effect(KILL cr);
9343 ins_cost(125);
9344 format %{ "OR $dst,$src" %}
9345 opcode(0x81,0x1); /* Opcode 81 /1 id */
9346 // ins_encode( MemImm( dst, src) );
9347 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9348 ins_pipe( ialu_mem_imm );
9349 %}
9351 // ROL/ROR
9352 // ROL expand
9353 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9354 effect(USE_DEF dst, USE shift, KILL cr);
9356 format %{ "ROL $dst, $shift" %}
9357 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9358 ins_encode( OpcP, RegOpc( dst ));
9359 ins_pipe( ialu_reg );
9360 %}
9362 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9363 effect(USE_DEF dst, USE shift, KILL cr);
9365 format %{ "ROL $dst, $shift" %}
9366 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9367 ins_encode( RegOpcImm(dst, shift) );
9368 ins_pipe(ialu_reg);
9369 %}
9371 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9372 effect(USE_DEF dst, USE shift, KILL cr);
9374 format %{ "ROL $dst, $shift" %}
9375 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9376 ins_encode(OpcP, RegOpc(dst));
9377 ins_pipe( ialu_reg_reg );
9378 %}
9379 // end of ROL expand
9381 // ROL 32bit by one once
9382 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9383 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9385 expand %{
9386 rolI_eReg_imm1(dst, lshift, cr);
9387 %}
9388 %}
9390 // ROL 32bit var by imm8 once
9391 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9392 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9393 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9395 expand %{
9396 rolI_eReg_imm8(dst, lshift, cr);
9397 %}
9398 %}
9400 // ROL 32bit var by var once
9401 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9402 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9404 expand %{
9405 rolI_eReg_CL(dst, shift, cr);
9406 %}
9407 %}
9409 // ROL 32bit var by var once
9410 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9411 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9413 expand %{
9414 rolI_eReg_CL(dst, shift, cr);
9415 %}
9416 %}
9418 // ROR expand
9419 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9420 effect(USE_DEF dst, USE shift, KILL cr);
9422 format %{ "ROR $dst, $shift" %}
9423 opcode(0xD1,0x1); /* Opcode D1 /1 */
9424 ins_encode( OpcP, RegOpc( dst ) );
9425 ins_pipe( ialu_reg );
9426 %}
9428 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9429 effect (USE_DEF dst, USE shift, KILL cr);
9431 format %{ "ROR $dst, $shift" %}
9432 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9433 ins_encode( RegOpcImm(dst, shift) );
9434 ins_pipe( ialu_reg );
9435 %}
9437 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9438 effect(USE_DEF dst, USE shift, KILL cr);
9440 format %{ "ROR $dst, $shift" %}
9441 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9442 ins_encode(OpcP, RegOpc(dst));
9443 ins_pipe( ialu_reg_reg );
9444 %}
9445 // end of ROR expand
9447 // ROR right once
9448 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9449 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9451 expand %{
9452 rorI_eReg_imm1(dst, rshift, cr);
9453 %}
9454 %}
9456 // ROR 32bit by immI8 once
9457 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9458 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9459 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9461 expand %{
9462 rorI_eReg_imm8(dst, rshift, cr);
9463 %}
9464 %}
9466 // ROR 32bit var by var once
9467 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9468 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9470 expand %{
9471 rorI_eReg_CL(dst, shift, cr);
9472 %}
9473 %}
9475 // ROR 32bit var by var once
9476 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9477 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9479 expand %{
9480 rorI_eReg_CL(dst, shift, cr);
9481 %}
9482 %}
9484 // Xor Instructions
9485 // Xor Register with Register
9486 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9487 match(Set dst (XorI dst src));
9488 effect(KILL cr);
9490 size(2);
9491 format %{ "XOR $dst,$src" %}
9492 opcode(0x33);
9493 ins_encode( OpcP, RegReg( dst, src) );
9494 ins_pipe( ialu_reg_reg );
9495 %}
9497 // Xor Register with Immediate -1
9498 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9499 match(Set dst (XorI dst imm));
9501 size(2);
9502 format %{ "NOT $dst" %}
9503 ins_encode %{
9504 __ notl($dst$$Register);
9505 %}
9506 ins_pipe( ialu_reg );
9507 %}
9509 // Xor Register with Immediate
9510 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9511 match(Set dst (XorI dst src));
9512 effect(KILL cr);
9514 format %{ "XOR $dst,$src" %}
9515 opcode(0x81,0x06); /* Opcode 81 /6 id */
9516 // ins_encode( RegImm( dst, src) );
9517 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9518 ins_pipe( ialu_reg );
9519 %}
9521 // Xor Register with Memory
9522 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9523 match(Set dst (XorI dst (LoadI src)));
9524 effect(KILL cr);
9526 ins_cost(125);
9527 format %{ "XOR $dst,$src" %}
9528 opcode(0x33);
9529 ins_encode( OpcP, RegMem(dst, src) );
9530 ins_pipe( ialu_reg_mem );
9531 %}
9533 // Xor Memory with Register
9534 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9535 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9536 effect(KILL cr);
9538 ins_cost(150);
9539 format %{ "XOR $dst,$src" %}
9540 opcode(0x31); /* Opcode 31 /r */
9541 ins_encode( OpcP, RegMem( src, dst ) );
9542 ins_pipe( ialu_mem_reg );
9543 %}
9545 // Xor Memory with Immediate
9546 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9547 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9548 effect(KILL cr);
9550 ins_cost(125);
9551 format %{ "XOR $dst,$src" %}
9552 opcode(0x81,0x6); /* Opcode 81 /6 id */
9553 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9554 ins_pipe( ialu_mem_imm );
9555 %}
9557 //----------Convert Int to Boolean---------------------------------------------
9559 instruct movI_nocopy(eRegI dst, eRegI src) %{
9560 effect( DEF dst, USE src );
9561 format %{ "MOV $dst,$src" %}
9562 ins_encode( enc_Copy( dst, src) );
9563 ins_pipe( ialu_reg_reg );
9564 %}
9566 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9567 effect( USE_DEF dst, USE src, KILL cr );
9569 size(4);
9570 format %{ "NEG $dst\n\t"
9571 "ADC $dst,$src" %}
9572 ins_encode( neg_reg(dst),
9573 OpcRegReg(0x13,dst,src) );
9574 ins_pipe( ialu_reg_reg_long );
9575 %}
9577 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9578 match(Set dst (Conv2B src));
9580 expand %{
9581 movI_nocopy(dst,src);
9582 ci2b(dst,src,cr);
9583 %}
9584 %}
9586 instruct movP_nocopy(eRegI dst, eRegP src) %{
9587 effect( DEF dst, USE src );
9588 format %{ "MOV $dst,$src" %}
9589 ins_encode( enc_Copy( dst, src) );
9590 ins_pipe( ialu_reg_reg );
9591 %}
9593 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9594 effect( USE_DEF dst, USE src, KILL cr );
9595 format %{ "NEG $dst\n\t"
9596 "ADC $dst,$src" %}
9597 ins_encode( neg_reg(dst),
9598 OpcRegReg(0x13,dst,src) );
9599 ins_pipe( ialu_reg_reg_long );
9600 %}
9602 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9603 match(Set dst (Conv2B src));
9605 expand %{
9606 movP_nocopy(dst,src);
9607 cp2b(dst,src,cr);
9608 %}
9609 %}
9611 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9612 match(Set dst (CmpLTMask p q));
9613 effect( KILL cr );
9614 ins_cost(400);
9616 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9617 format %{ "XOR $dst,$dst\n\t"
9618 "CMP $p,$q\n\t"
9619 "SETlt $dst\n\t"
9620 "NEG $dst" %}
9621 ins_encode( OpcRegReg(0x33,dst,dst),
9622 OpcRegReg(0x3B,p,q),
9623 setLT_reg(dst), neg_reg(dst) );
9624 ins_pipe( pipe_slow );
9625 %}
9627 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9628 match(Set dst (CmpLTMask dst zero));
9629 effect( DEF dst, KILL cr );
9630 ins_cost(100);
9632 format %{ "SAR $dst,31" %}
9633 opcode(0xC1, 0x7); /* C1 /7 ib */
9634 ins_encode( RegOpcImm( dst, 0x1F ) );
9635 ins_pipe( ialu_reg );
9636 %}
9639 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9640 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9641 effect( KILL tmp, KILL cr );
9642 ins_cost(400);
9643 // annoyingly, $tmp has no edges so you cant ask for it in
9644 // any format or encoding
9645 format %{ "SUB $p,$q\n\t"
9646 "SBB ECX,ECX\n\t"
9647 "AND ECX,$y\n\t"
9648 "ADD $p,ECX" %}
9649 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9650 ins_pipe( pipe_cmplt );
9651 %}
9653 /* If I enable this, I encourage spilling in the inner loop of compress.
9654 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9655 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9656 effect( USE_KILL tmp, KILL cr );
9657 ins_cost(400);
9659 format %{ "SUB $p,$q\n\t"
9660 "SBB ECX,ECX\n\t"
9661 "AND ECX,$y\n\t"
9662 "ADD $p,ECX" %}
9663 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9664 %}
9665 */
9667 //----------Long Instructions------------------------------------------------
9668 // Add Long Register with Register
9669 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9670 match(Set dst (AddL dst src));
9671 effect(KILL cr);
9672 ins_cost(200);
9673 format %{ "ADD $dst.lo,$src.lo\n\t"
9674 "ADC $dst.hi,$src.hi" %}
9675 opcode(0x03, 0x13);
9676 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9677 ins_pipe( ialu_reg_reg_long );
9678 %}
9680 // Add Long Register with Immediate
9681 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9682 match(Set dst (AddL dst src));
9683 effect(KILL cr);
9684 format %{ "ADD $dst.lo,$src.lo\n\t"
9685 "ADC $dst.hi,$src.hi" %}
9686 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9687 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9688 ins_pipe( ialu_reg_long );
9689 %}
9691 // Add Long Register with Memory
9692 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9693 match(Set dst (AddL dst (LoadL mem)));
9694 effect(KILL cr);
9695 ins_cost(125);
9696 format %{ "ADD $dst.lo,$mem\n\t"
9697 "ADC $dst.hi,$mem+4" %}
9698 opcode(0x03, 0x13);
9699 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9700 ins_pipe( ialu_reg_long_mem );
9701 %}
9703 // Subtract Long Register with Register.
9704 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9705 match(Set dst (SubL dst src));
9706 effect(KILL cr);
9707 ins_cost(200);
9708 format %{ "SUB $dst.lo,$src.lo\n\t"
9709 "SBB $dst.hi,$src.hi" %}
9710 opcode(0x2B, 0x1B);
9711 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9712 ins_pipe( ialu_reg_reg_long );
9713 %}
9715 // Subtract Long Register with Immediate
9716 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9717 match(Set dst (SubL dst src));
9718 effect(KILL cr);
9719 format %{ "SUB $dst.lo,$src.lo\n\t"
9720 "SBB $dst.hi,$src.hi" %}
9721 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9722 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9723 ins_pipe( ialu_reg_long );
9724 %}
9726 // Subtract Long Register with Memory
9727 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9728 match(Set dst (SubL dst (LoadL mem)));
9729 effect(KILL cr);
9730 ins_cost(125);
9731 format %{ "SUB $dst.lo,$mem\n\t"
9732 "SBB $dst.hi,$mem+4" %}
9733 opcode(0x2B, 0x1B);
9734 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9735 ins_pipe( ialu_reg_long_mem );
9736 %}
9738 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9739 match(Set dst (SubL zero dst));
9740 effect(KILL cr);
9741 ins_cost(300);
9742 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9743 ins_encode( neg_long(dst) );
9744 ins_pipe( ialu_reg_reg_long );
9745 %}
9747 // And Long Register with Register
9748 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9749 match(Set dst (AndL dst src));
9750 effect(KILL cr);
9751 format %{ "AND $dst.lo,$src.lo\n\t"
9752 "AND $dst.hi,$src.hi" %}
9753 opcode(0x23,0x23);
9754 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9755 ins_pipe( ialu_reg_reg_long );
9756 %}
9758 // And Long Register with Immediate
9759 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9760 match(Set dst (AndL dst src));
9761 effect(KILL cr);
9762 format %{ "AND $dst.lo,$src.lo\n\t"
9763 "AND $dst.hi,$src.hi" %}
9764 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9765 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9766 ins_pipe( ialu_reg_long );
9767 %}
9769 // And Long Register with Memory
9770 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9771 match(Set dst (AndL dst (LoadL mem)));
9772 effect(KILL cr);
9773 ins_cost(125);
9774 format %{ "AND $dst.lo,$mem\n\t"
9775 "AND $dst.hi,$mem+4" %}
9776 opcode(0x23, 0x23);
9777 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9778 ins_pipe( ialu_reg_long_mem );
9779 %}
9781 // Or Long Register with Register
9782 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9783 match(Set dst (OrL dst src));
9784 effect(KILL cr);
9785 format %{ "OR $dst.lo,$src.lo\n\t"
9786 "OR $dst.hi,$src.hi" %}
9787 opcode(0x0B,0x0B);
9788 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9789 ins_pipe( ialu_reg_reg_long );
9790 %}
9792 // Or Long Register with Immediate
9793 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9794 match(Set dst (OrL dst src));
9795 effect(KILL cr);
9796 format %{ "OR $dst.lo,$src.lo\n\t"
9797 "OR $dst.hi,$src.hi" %}
9798 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9799 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9800 ins_pipe( ialu_reg_long );
9801 %}
9803 // Or Long Register with Memory
9804 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9805 match(Set dst (OrL dst (LoadL mem)));
9806 effect(KILL cr);
9807 ins_cost(125);
9808 format %{ "OR $dst.lo,$mem\n\t"
9809 "OR $dst.hi,$mem+4" %}
9810 opcode(0x0B,0x0B);
9811 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9812 ins_pipe( ialu_reg_long_mem );
9813 %}
9815 // Xor Long Register with Register
9816 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9817 match(Set dst (XorL dst src));
9818 effect(KILL cr);
9819 format %{ "XOR $dst.lo,$src.lo\n\t"
9820 "XOR $dst.hi,$src.hi" %}
9821 opcode(0x33,0x33);
9822 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9823 ins_pipe( ialu_reg_reg_long );
9824 %}
9826 // Xor Long Register with Immediate -1
9827 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9828 match(Set dst (XorL dst imm));
9829 format %{ "NOT $dst.lo\n\t"
9830 "NOT $dst.hi" %}
9831 ins_encode %{
9832 __ notl($dst$$Register);
9833 __ notl(HIGH_FROM_LOW($dst$$Register));
9834 %}
9835 ins_pipe( ialu_reg_long );
9836 %}
9838 // Xor Long Register with Immediate
9839 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9840 match(Set dst (XorL dst src));
9841 effect(KILL cr);
9842 format %{ "XOR $dst.lo,$src.lo\n\t"
9843 "XOR $dst.hi,$src.hi" %}
9844 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9845 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9846 ins_pipe( ialu_reg_long );
9847 %}
9849 // Xor Long Register with Memory
9850 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9851 match(Set dst (XorL dst (LoadL mem)));
9852 effect(KILL cr);
9853 ins_cost(125);
9854 format %{ "XOR $dst.lo,$mem\n\t"
9855 "XOR $dst.hi,$mem+4" %}
9856 opcode(0x33,0x33);
9857 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9858 ins_pipe( ialu_reg_long_mem );
9859 %}
9861 // Shift Left Long by 1
9862 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9863 predicate(UseNewLongLShift);
9864 match(Set dst (LShiftL dst cnt));
9865 effect(KILL cr);
9866 ins_cost(100);
9867 format %{ "ADD $dst.lo,$dst.lo\n\t"
9868 "ADC $dst.hi,$dst.hi" %}
9869 ins_encode %{
9870 __ addl($dst$$Register,$dst$$Register);
9871 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9872 %}
9873 ins_pipe( ialu_reg_long );
9874 %}
9876 // Shift Left Long by 2
9877 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9878 predicate(UseNewLongLShift);
9879 match(Set dst (LShiftL dst cnt));
9880 effect(KILL cr);
9881 ins_cost(100);
9882 format %{ "ADD $dst.lo,$dst.lo\n\t"
9883 "ADC $dst.hi,$dst.hi\n\t"
9884 "ADD $dst.lo,$dst.lo\n\t"
9885 "ADC $dst.hi,$dst.hi" %}
9886 ins_encode %{
9887 __ addl($dst$$Register,$dst$$Register);
9888 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9889 __ addl($dst$$Register,$dst$$Register);
9890 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9891 %}
9892 ins_pipe( ialu_reg_long );
9893 %}
9895 // Shift Left Long by 3
9896 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9897 predicate(UseNewLongLShift);
9898 match(Set dst (LShiftL dst cnt));
9899 effect(KILL cr);
9900 ins_cost(100);
9901 format %{ "ADD $dst.lo,$dst.lo\n\t"
9902 "ADC $dst.hi,$dst.hi\n\t"
9903 "ADD $dst.lo,$dst.lo\n\t"
9904 "ADC $dst.hi,$dst.hi\n\t"
9905 "ADD $dst.lo,$dst.lo\n\t"
9906 "ADC $dst.hi,$dst.hi" %}
9907 ins_encode %{
9908 __ addl($dst$$Register,$dst$$Register);
9909 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9910 __ addl($dst$$Register,$dst$$Register);
9911 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9912 __ addl($dst$$Register,$dst$$Register);
9913 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9914 %}
9915 ins_pipe( ialu_reg_long );
9916 %}
9918 // Shift Left Long by 1-31
9919 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9920 match(Set dst (LShiftL dst cnt));
9921 effect(KILL cr);
9922 ins_cost(200);
9923 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9924 "SHL $dst.lo,$cnt" %}
9925 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9926 ins_encode( move_long_small_shift(dst,cnt) );
9927 ins_pipe( ialu_reg_long );
9928 %}
9930 // Shift Left Long by 32-63
9931 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9932 match(Set dst (LShiftL dst cnt));
9933 effect(KILL cr);
9934 ins_cost(300);
9935 format %{ "MOV $dst.hi,$dst.lo\n"
9936 "\tSHL $dst.hi,$cnt-32\n"
9937 "\tXOR $dst.lo,$dst.lo" %}
9938 opcode(0xC1, 0x4); /* C1 /4 ib */
9939 ins_encode( move_long_big_shift_clr(dst,cnt) );
9940 ins_pipe( ialu_reg_long );
9941 %}
9943 // Shift Left Long by variable
9944 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9945 match(Set dst (LShiftL dst shift));
9946 effect(KILL cr);
9947 ins_cost(500+200);
9948 size(17);
9949 format %{ "TEST $shift,32\n\t"
9950 "JEQ,s small\n\t"
9951 "MOV $dst.hi,$dst.lo\n\t"
9952 "XOR $dst.lo,$dst.lo\n"
9953 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9954 "SHL $dst.lo,$shift" %}
9955 ins_encode( shift_left_long( dst, shift ) );
9956 ins_pipe( pipe_slow );
9957 %}
9959 // Shift Right Long by 1-31
9960 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9961 match(Set dst (URShiftL dst cnt));
9962 effect(KILL cr);
9963 ins_cost(200);
9964 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9965 "SHR $dst.hi,$cnt" %}
9966 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9967 ins_encode( move_long_small_shift(dst,cnt) );
9968 ins_pipe( ialu_reg_long );
9969 %}
9971 // Shift Right Long by 32-63
9972 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9973 match(Set dst (URShiftL dst cnt));
9974 effect(KILL cr);
9975 ins_cost(300);
9976 format %{ "MOV $dst.lo,$dst.hi\n"
9977 "\tSHR $dst.lo,$cnt-32\n"
9978 "\tXOR $dst.hi,$dst.hi" %}
9979 opcode(0xC1, 0x5); /* C1 /5 ib */
9980 ins_encode( move_long_big_shift_clr(dst,cnt) );
9981 ins_pipe( ialu_reg_long );
9982 %}
9984 // Shift Right Long by variable
9985 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9986 match(Set dst (URShiftL dst shift));
9987 effect(KILL cr);
9988 ins_cost(600);
9989 size(17);
9990 format %{ "TEST $shift,32\n\t"
9991 "JEQ,s small\n\t"
9992 "MOV $dst.lo,$dst.hi\n\t"
9993 "XOR $dst.hi,$dst.hi\n"
9994 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9995 "SHR $dst.hi,$shift" %}
9996 ins_encode( shift_right_long( dst, shift ) );
9997 ins_pipe( pipe_slow );
9998 %}
10000 // Shift Right Long by 1-31
10001 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
10002 match(Set dst (RShiftL dst cnt));
10003 effect(KILL cr);
10004 ins_cost(200);
10005 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
10006 "SAR $dst.hi,$cnt" %}
10007 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
10008 ins_encode( move_long_small_shift(dst,cnt) );
10009 ins_pipe( ialu_reg_long );
10010 %}
10012 // Shift Right Long by 32-63
10013 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
10014 match(Set dst (RShiftL dst cnt));
10015 effect(KILL cr);
10016 ins_cost(300);
10017 format %{ "MOV $dst.lo,$dst.hi\n"
10018 "\tSAR $dst.lo,$cnt-32\n"
10019 "\tSAR $dst.hi,31" %}
10020 opcode(0xC1, 0x7); /* C1 /7 ib */
10021 ins_encode( move_long_big_shift_sign(dst,cnt) );
10022 ins_pipe( ialu_reg_long );
10023 %}
10025 // Shift Right arithmetic Long by variable
10026 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
10027 match(Set dst (RShiftL dst shift));
10028 effect(KILL cr);
10029 ins_cost(600);
10030 size(18);
10031 format %{ "TEST $shift,32\n\t"
10032 "JEQ,s small\n\t"
10033 "MOV $dst.lo,$dst.hi\n\t"
10034 "SAR $dst.hi,31\n"
10035 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
10036 "SAR $dst.hi,$shift" %}
10037 ins_encode( shift_right_arith_long( dst, shift ) );
10038 ins_pipe( pipe_slow );
10039 %}
10042 //----------Double Instructions------------------------------------------------
10043 // Double Math
10045 // Compare & branch
10047 // P6 version of float compare, sets condition codes in EFLAGS
10048 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
10049 predicate(VM_Version::supports_cmov() && UseSSE <=1);
10050 match(Set cr (CmpD src1 src2));
10051 effect(KILL rax);
10052 ins_cost(150);
10053 format %{ "FLD $src1\n\t"
10054 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10055 "JNP exit\n\t"
10056 "MOV ah,1 // saw a NaN, set CF\n\t"
10057 "SAHF\n"
10058 "exit:\tNOP // avoid branch to branch" %}
10059 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10060 ins_encode( Push_Reg_D(src1),
10061 OpcP, RegOpc(src2),
10062 cmpF_P6_fixup );
10063 ins_pipe( pipe_slow );
10064 %}
10066 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
10067 predicate(VM_Version::supports_cmov() && UseSSE <=1);
10068 match(Set cr (CmpD src1 src2));
10069 ins_cost(150);
10070 format %{ "FLD $src1\n\t"
10071 "FUCOMIP ST,$src2 // P6 instruction" %}
10072 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10073 ins_encode( Push_Reg_D(src1),
10074 OpcP, RegOpc(src2));
10075 ins_pipe( pipe_slow );
10076 %}
10078 // Compare & branch
10079 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
10080 predicate(UseSSE<=1);
10081 match(Set cr (CmpD src1 src2));
10082 effect(KILL rax);
10083 ins_cost(200);
10084 format %{ "FLD $src1\n\t"
10085 "FCOMp $src2\n\t"
10086 "FNSTSW AX\n\t"
10087 "TEST AX,0x400\n\t"
10088 "JZ,s flags\n\t"
10089 "MOV AH,1\t# unordered treat as LT\n"
10090 "flags:\tSAHF" %}
10091 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10092 ins_encode( Push_Reg_D(src1),
10093 OpcP, RegOpc(src2),
10094 fpu_flags);
10095 ins_pipe( pipe_slow );
10096 %}
10098 // Compare vs zero into -1,0,1
10099 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
10100 predicate(UseSSE<=1);
10101 match(Set dst (CmpD3 src1 zero));
10102 effect(KILL cr, KILL rax);
10103 ins_cost(280);
10104 format %{ "FTSTD $dst,$src1" %}
10105 opcode(0xE4, 0xD9);
10106 ins_encode( Push_Reg_D(src1),
10107 OpcS, OpcP, PopFPU,
10108 CmpF_Result(dst));
10109 ins_pipe( pipe_slow );
10110 %}
10112 // Compare into -1,0,1
10113 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
10114 predicate(UseSSE<=1);
10115 match(Set dst (CmpD3 src1 src2));
10116 effect(KILL cr, KILL rax);
10117 ins_cost(300);
10118 format %{ "FCMPD $dst,$src1,$src2" %}
10119 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10120 ins_encode( Push_Reg_D(src1),
10121 OpcP, RegOpc(src2),
10122 CmpF_Result(dst));
10123 ins_pipe( pipe_slow );
10124 %}
10126 // float compare and set condition codes in EFLAGS by XMM regs
10127 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
10128 predicate(UseSSE>=2);
10129 match(Set cr (CmpD dst src));
10130 effect(KILL rax);
10131 ins_cost(125);
10132 format %{ "COMISD $dst,$src\n"
10133 "\tJNP exit\n"
10134 "\tMOV ah,1 // saw a NaN, set CF\n"
10135 "\tSAHF\n"
10136 "exit:\tNOP // avoid branch to branch" %}
10137 opcode(0x66, 0x0F, 0x2F);
10138 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
10139 ins_pipe( pipe_slow );
10140 %}
10142 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
10143 predicate(UseSSE>=2);
10144 match(Set cr (CmpD dst src));
10145 ins_cost(100);
10146 format %{ "COMISD $dst,$src" %}
10147 opcode(0x66, 0x0F, 0x2F);
10148 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10149 ins_pipe( pipe_slow );
10150 %}
10152 // float compare and set condition codes in EFLAGS by XMM regs
10153 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
10154 predicate(UseSSE>=2);
10155 match(Set cr (CmpD dst (LoadD src)));
10156 effect(KILL rax);
10157 ins_cost(145);
10158 format %{ "COMISD $dst,$src\n"
10159 "\tJNP exit\n"
10160 "\tMOV ah,1 // saw a NaN, set CF\n"
10161 "\tSAHF\n"
10162 "exit:\tNOP // avoid branch to branch" %}
10163 opcode(0x66, 0x0F, 0x2F);
10164 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
10165 ins_pipe( pipe_slow );
10166 %}
10168 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
10169 predicate(UseSSE>=2);
10170 match(Set cr (CmpD dst (LoadD src)));
10171 ins_cost(100);
10172 format %{ "COMISD $dst,$src" %}
10173 opcode(0x66, 0x0F, 0x2F);
10174 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
10175 ins_pipe( pipe_slow );
10176 %}
10178 // Compare into -1,0,1 in XMM
10179 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
10180 predicate(UseSSE>=2);
10181 match(Set dst (CmpD3 src1 src2));
10182 effect(KILL cr);
10183 ins_cost(255);
10184 format %{ "XOR $dst,$dst\n"
10185 "\tCOMISD $src1,$src2\n"
10186 "\tJP,s nan\n"
10187 "\tJEQ,s exit\n"
10188 "\tJA,s inc\n"
10189 "nan:\tDEC $dst\n"
10190 "\tJMP,s exit\n"
10191 "inc:\tINC $dst\n"
10192 "exit:"
10193 %}
10194 opcode(0x66, 0x0F, 0x2F);
10195 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
10196 CmpX_Result(dst));
10197 ins_pipe( pipe_slow );
10198 %}
10200 // Compare into -1,0,1 in XMM and memory
10201 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
10202 predicate(UseSSE>=2);
10203 match(Set dst (CmpD3 src1 (LoadD mem)));
10204 effect(KILL cr);
10205 ins_cost(275);
10206 format %{ "COMISD $src1,$mem\n"
10207 "\tMOV $dst,0\t\t# do not blow flags\n"
10208 "\tJP,s nan\n"
10209 "\tJEQ,s exit\n"
10210 "\tJA,s inc\n"
10211 "nan:\tDEC $dst\n"
10212 "\tJMP,s exit\n"
10213 "inc:\tINC $dst\n"
10214 "exit:"
10215 %}
10216 opcode(0x66, 0x0F, 0x2F);
10217 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
10218 LdImmI(dst,0x0), CmpX_Result(dst));
10219 ins_pipe( pipe_slow );
10220 %}
10223 instruct subD_reg(regD dst, regD src) %{
10224 predicate (UseSSE <=1);
10225 match(Set dst (SubD dst src));
10227 format %{ "FLD $src\n\t"
10228 "DSUBp $dst,ST" %}
10229 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10230 ins_cost(150);
10231 ins_encode( Push_Reg_D(src),
10232 OpcP, RegOpc(dst) );
10233 ins_pipe( fpu_reg_reg );
10234 %}
10236 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10237 predicate (UseSSE <=1);
10238 match(Set dst (RoundDouble (SubD src1 src2)));
10239 ins_cost(250);
10241 format %{ "FLD $src2\n\t"
10242 "DSUB ST,$src1\n\t"
10243 "FSTP_D $dst\t# D-round" %}
10244 opcode(0xD8, 0x5);
10245 ins_encode( Push_Reg_D(src2),
10246 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10247 ins_pipe( fpu_mem_reg_reg );
10248 %}
10251 instruct subD_reg_mem(regD dst, memory src) %{
10252 predicate (UseSSE <=1);
10253 match(Set dst (SubD dst (LoadD src)));
10254 ins_cost(150);
10256 format %{ "FLD $src\n\t"
10257 "DSUBp $dst,ST" %}
10258 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10259 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10260 OpcP, RegOpc(dst) );
10261 ins_pipe( fpu_reg_mem );
10262 %}
10264 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
10265 predicate (UseSSE<=1);
10266 match(Set dst (AbsD src));
10267 ins_cost(100);
10268 format %{ "FABS" %}
10269 opcode(0xE1, 0xD9);
10270 ins_encode( OpcS, OpcP );
10271 ins_pipe( fpu_reg_reg );
10272 %}
10274 instruct absXD_reg( regXD dst ) %{
10275 predicate(UseSSE>=2);
10276 match(Set dst (AbsD dst));
10277 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10278 ins_encode( AbsXD_encoding(dst));
10279 ins_pipe( pipe_slow );
10280 %}
10282 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10283 predicate(UseSSE<=1);
10284 match(Set dst (NegD src));
10285 ins_cost(100);
10286 format %{ "FCHS" %}
10287 opcode(0xE0, 0xD9);
10288 ins_encode( OpcS, OpcP );
10289 ins_pipe( fpu_reg_reg );
10290 %}
10292 instruct negXD_reg( regXD dst ) %{
10293 predicate(UseSSE>=2);
10294 match(Set dst (NegD dst));
10295 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10296 ins_encode %{
10297 __ xorpd($dst$$XMMRegister,
10298 ExternalAddress((address)double_signflip_pool));
10299 %}
10300 ins_pipe( pipe_slow );
10301 %}
10303 instruct addD_reg(regD dst, regD src) %{
10304 predicate(UseSSE<=1);
10305 match(Set dst (AddD dst src));
10306 format %{ "FLD $src\n\t"
10307 "DADD $dst,ST" %}
10308 size(4);
10309 ins_cost(150);
10310 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10311 ins_encode( Push_Reg_D(src),
10312 OpcP, RegOpc(dst) );
10313 ins_pipe( fpu_reg_reg );
10314 %}
10317 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10318 predicate(UseSSE<=1);
10319 match(Set dst (RoundDouble (AddD src1 src2)));
10320 ins_cost(250);
10322 format %{ "FLD $src2\n\t"
10323 "DADD ST,$src1\n\t"
10324 "FSTP_D $dst\t# D-round" %}
10325 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10326 ins_encode( Push_Reg_D(src2),
10327 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10328 ins_pipe( fpu_mem_reg_reg );
10329 %}
10332 instruct addD_reg_mem(regD dst, memory src) %{
10333 predicate(UseSSE<=1);
10334 match(Set dst (AddD dst (LoadD src)));
10335 ins_cost(150);
10337 format %{ "FLD $src\n\t"
10338 "DADDp $dst,ST" %}
10339 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10340 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10341 OpcP, RegOpc(dst) );
10342 ins_pipe( fpu_reg_mem );
10343 %}
10345 // add-to-memory
10346 instruct addD_mem_reg(memory dst, regD src) %{
10347 predicate(UseSSE<=1);
10348 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10349 ins_cost(150);
10351 format %{ "FLD_D $dst\n\t"
10352 "DADD ST,$src\n\t"
10353 "FST_D $dst" %}
10354 opcode(0xDD, 0x0);
10355 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10356 Opcode(0xD8), RegOpc(src),
10357 set_instruction_start,
10358 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10359 ins_pipe( fpu_reg_mem );
10360 %}
10362 instruct addD_reg_imm1(regD dst, immD1 con) %{
10363 predicate(UseSSE<=1);
10364 match(Set dst (AddD dst con));
10365 ins_cost(125);
10366 format %{ "FLD1\n\t"
10367 "DADDp $dst,ST" %}
10368 ins_encode %{
10369 __ fld1();
10370 __ faddp($dst$$reg);
10371 %}
10372 ins_pipe(fpu_reg);
10373 %}
10375 instruct addD_reg_imm(regD dst, immD con) %{
10376 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10377 match(Set dst (AddD dst con));
10378 ins_cost(200);
10379 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10380 "DADDp $dst,ST" %}
10381 ins_encode %{
10382 __ fld_d($constantaddress($con));
10383 __ faddp($dst$$reg);
10384 %}
10385 ins_pipe(fpu_reg_mem);
10386 %}
10388 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10389 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10390 match(Set dst (RoundDouble (AddD src con)));
10391 ins_cost(200);
10392 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10393 "DADD ST,$src\n\t"
10394 "FSTP_D $dst\t# D-round" %}
10395 ins_encode %{
10396 __ fld_d($constantaddress($con));
10397 __ fadd($src$$reg);
10398 __ fstp_d(Address(rsp, $dst$$disp));
10399 %}
10400 ins_pipe(fpu_mem_reg_con);
10401 %}
10403 // Add two double precision floating point values in xmm
10404 instruct addXD_reg(regXD dst, regXD src) %{
10405 predicate(UseSSE>=2);
10406 match(Set dst (AddD dst src));
10407 format %{ "ADDSD $dst,$src" %}
10408 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10409 ins_pipe( pipe_slow );
10410 %}
10412 instruct addXD_imm(regXD dst, immXD con) %{
10413 predicate(UseSSE>=2);
10414 match(Set dst (AddD dst con));
10415 format %{ "ADDSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10416 ins_encode %{
10417 __ addsd($dst$$XMMRegister, $constantaddress($con));
10418 %}
10419 ins_pipe(pipe_slow);
10420 %}
10422 instruct addXD_mem(regXD dst, memory mem) %{
10423 predicate(UseSSE>=2);
10424 match(Set dst (AddD dst (LoadD mem)));
10425 format %{ "ADDSD $dst,$mem" %}
10426 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10427 ins_pipe( pipe_slow );
10428 %}
10430 // Sub two double precision floating point values in xmm
10431 instruct subXD_reg(regXD dst, regXD src) %{
10432 predicate(UseSSE>=2);
10433 match(Set dst (SubD dst src));
10434 format %{ "SUBSD $dst,$src" %}
10435 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10436 ins_pipe( pipe_slow );
10437 %}
10439 instruct subXD_imm(regXD dst, immXD con) %{
10440 predicate(UseSSE>=2);
10441 match(Set dst (SubD dst con));
10442 format %{ "SUBSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10443 ins_encode %{
10444 __ subsd($dst$$XMMRegister, $constantaddress($con));
10445 %}
10446 ins_pipe(pipe_slow);
10447 %}
10449 instruct subXD_mem(regXD dst, memory mem) %{
10450 predicate(UseSSE>=2);
10451 match(Set dst (SubD dst (LoadD mem)));
10452 format %{ "SUBSD $dst,$mem" %}
10453 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10454 ins_pipe( pipe_slow );
10455 %}
10457 // Mul two double precision floating point values in xmm
10458 instruct mulXD_reg(regXD dst, regXD src) %{
10459 predicate(UseSSE>=2);
10460 match(Set dst (MulD dst src));
10461 format %{ "MULSD $dst,$src" %}
10462 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10463 ins_pipe( pipe_slow );
10464 %}
10466 instruct mulXD_imm(regXD dst, immXD con) %{
10467 predicate(UseSSE>=2);
10468 match(Set dst (MulD dst con));
10469 format %{ "MULSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10470 ins_encode %{
10471 __ mulsd($dst$$XMMRegister, $constantaddress($con));
10472 %}
10473 ins_pipe(pipe_slow);
10474 %}
10476 instruct mulXD_mem(regXD dst, memory mem) %{
10477 predicate(UseSSE>=2);
10478 match(Set dst (MulD dst (LoadD mem)));
10479 format %{ "MULSD $dst,$mem" %}
10480 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10481 ins_pipe( pipe_slow );
10482 %}
10484 // Div two double precision floating point values in xmm
10485 instruct divXD_reg(regXD dst, regXD src) %{
10486 predicate(UseSSE>=2);
10487 match(Set dst (DivD dst src));
10488 format %{ "DIVSD $dst,$src" %}
10489 opcode(0xF2, 0x0F, 0x5E);
10490 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10491 ins_pipe( pipe_slow );
10492 %}
10494 instruct divXD_imm(regXD dst, immXD con) %{
10495 predicate(UseSSE>=2);
10496 match(Set dst (DivD dst con));
10497 format %{ "DIVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10498 ins_encode %{
10499 __ divsd($dst$$XMMRegister, $constantaddress($con));
10500 %}
10501 ins_pipe(pipe_slow);
10502 %}
10504 instruct divXD_mem(regXD dst, memory mem) %{
10505 predicate(UseSSE>=2);
10506 match(Set dst (DivD dst (LoadD mem)));
10507 format %{ "DIVSD $dst,$mem" %}
10508 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10509 ins_pipe( pipe_slow );
10510 %}
10513 instruct mulD_reg(regD dst, regD src) %{
10514 predicate(UseSSE<=1);
10515 match(Set dst (MulD dst src));
10516 format %{ "FLD $src\n\t"
10517 "DMULp $dst,ST" %}
10518 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10519 ins_cost(150);
10520 ins_encode( Push_Reg_D(src),
10521 OpcP, RegOpc(dst) );
10522 ins_pipe( fpu_reg_reg );
10523 %}
10525 // Strict FP instruction biases argument before multiply then
10526 // biases result to avoid double rounding of subnormals.
10527 //
10528 // scale arg1 by multiplying arg1 by 2^(-15360)
10529 // load arg2
10530 // multiply scaled arg1 by arg2
10531 // rescale product by 2^(15360)
10532 //
10533 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10534 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10535 match(Set dst (MulD dst src));
10536 ins_cost(1); // Select this instruction for all strict FP double multiplies
10538 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10539 "DMULp $dst,ST\n\t"
10540 "FLD $src\n\t"
10541 "DMULp $dst,ST\n\t"
10542 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10543 "DMULp $dst,ST\n\t" %}
10544 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10545 ins_encode( strictfp_bias1(dst),
10546 Push_Reg_D(src),
10547 OpcP, RegOpc(dst),
10548 strictfp_bias2(dst) );
10549 ins_pipe( fpu_reg_reg );
10550 %}
10552 instruct mulD_reg_imm(regD dst, immD con) %{
10553 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10554 match(Set dst (MulD dst con));
10555 ins_cost(200);
10556 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10557 "DMULp $dst,ST" %}
10558 ins_encode %{
10559 __ fld_d($constantaddress($con));
10560 __ fmulp($dst$$reg);
10561 %}
10562 ins_pipe(fpu_reg_mem);
10563 %}
10566 instruct mulD_reg_mem(regD dst, memory src) %{
10567 predicate( UseSSE<=1 );
10568 match(Set dst (MulD dst (LoadD src)));
10569 ins_cost(200);
10570 format %{ "FLD_D $src\n\t"
10571 "DMULp $dst,ST" %}
10572 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10573 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10574 OpcP, RegOpc(dst) );
10575 ins_pipe( fpu_reg_mem );
10576 %}
10578 //
10579 // Cisc-alternate to reg-reg multiply
10580 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10581 predicate( UseSSE<=1 );
10582 match(Set dst (MulD src (LoadD mem)));
10583 ins_cost(250);
10584 format %{ "FLD_D $mem\n\t"
10585 "DMUL ST,$src\n\t"
10586 "FSTP_D $dst" %}
10587 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10588 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10589 OpcReg_F(src),
10590 Pop_Reg_D(dst) );
10591 ins_pipe( fpu_reg_reg_mem );
10592 %}
10595 // MACRO3 -- addD a mulD
10596 // This instruction is a '2-address' instruction in that the result goes
10597 // back to src2. This eliminates a move from the macro; possibly the
10598 // register allocator will have to add it back (and maybe not).
10599 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10600 predicate( UseSSE<=1 );
10601 match(Set src2 (AddD (MulD src0 src1) src2));
10602 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10603 "DMUL ST,$src1\n\t"
10604 "DADDp $src2,ST" %}
10605 ins_cost(250);
10606 opcode(0xDD); /* LoadD DD /0 */
10607 ins_encode( Push_Reg_F(src0),
10608 FMul_ST_reg(src1),
10609 FAddP_reg_ST(src2) );
10610 ins_pipe( fpu_reg_reg_reg );
10611 %}
10614 // MACRO3 -- subD a mulD
10615 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10616 predicate( UseSSE<=1 );
10617 match(Set src2 (SubD (MulD src0 src1) src2));
10618 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10619 "DMUL ST,$src1\n\t"
10620 "DSUBRp $src2,ST" %}
10621 ins_cost(250);
10622 ins_encode( Push_Reg_F(src0),
10623 FMul_ST_reg(src1),
10624 Opcode(0xDE), Opc_plus(0xE0,src2));
10625 ins_pipe( fpu_reg_reg_reg );
10626 %}
10629 instruct divD_reg(regD dst, regD src) %{
10630 predicate( UseSSE<=1 );
10631 match(Set dst (DivD dst src));
10633 format %{ "FLD $src\n\t"
10634 "FDIVp $dst,ST" %}
10635 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10636 ins_cost(150);
10637 ins_encode( Push_Reg_D(src),
10638 OpcP, RegOpc(dst) );
10639 ins_pipe( fpu_reg_reg );
10640 %}
10642 // Strict FP instruction biases argument before division then
10643 // biases result, to avoid double rounding of subnormals.
10644 //
10645 // scale dividend by multiplying dividend by 2^(-15360)
10646 // load divisor
10647 // divide scaled dividend by divisor
10648 // rescale quotient by 2^(15360)
10649 //
10650 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10651 predicate (UseSSE<=1);
10652 match(Set dst (DivD dst src));
10653 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10654 ins_cost(01);
10656 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10657 "DMULp $dst,ST\n\t"
10658 "FLD $src\n\t"
10659 "FDIVp $dst,ST\n\t"
10660 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10661 "DMULp $dst,ST\n\t" %}
10662 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10663 ins_encode( strictfp_bias1(dst),
10664 Push_Reg_D(src),
10665 OpcP, RegOpc(dst),
10666 strictfp_bias2(dst) );
10667 ins_pipe( fpu_reg_reg );
10668 %}
10670 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10671 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10672 match(Set dst (RoundDouble (DivD src1 src2)));
10674 format %{ "FLD $src1\n\t"
10675 "FDIV ST,$src2\n\t"
10676 "FSTP_D $dst\t# D-round" %}
10677 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10678 ins_encode( Push_Reg_D(src1),
10679 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10680 ins_pipe( fpu_mem_reg_reg );
10681 %}
10684 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10685 predicate(UseSSE<=1);
10686 match(Set dst (ModD dst src));
10687 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10689 format %{ "DMOD $dst,$src" %}
10690 ins_cost(250);
10691 ins_encode(Push_Reg_Mod_D(dst, src),
10692 emitModD(),
10693 Push_Result_Mod_D(src),
10694 Pop_Reg_D(dst));
10695 ins_pipe( pipe_slow );
10696 %}
10698 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10699 predicate(UseSSE>=2);
10700 match(Set dst (ModD src0 src1));
10701 effect(KILL rax, KILL cr);
10703 format %{ "SUB ESP,8\t # DMOD\n"
10704 "\tMOVSD [ESP+0],$src1\n"
10705 "\tFLD_D [ESP+0]\n"
10706 "\tMOVSD [ESP+0],$src0\n"
10707 "\tFLD_D [ESP+0]\n"
10708 "loop:\tFPREM\n"
10709 "\tFWAIT\n"
10710 "\tFNSTSW AX\n"
10711 "\tSAHF\n"
10712 "\tJP loop\n"
10713 "\tFSTP_D [ESP+0]\n"
10714 "\tMOVSD $dst,[ESP+0]\n"
10715 "\tADD ESP,8\n"
10716 "\tFSTP ST0\t # Restore FPU Stack"
10717 %}
10718 ins_cost(250);
10719 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10720 ins_pipe( pipe_slow );
10721 %}
10723 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10724 predicate (UseSSE<=1);
10725 match(Set dst (SinD src));
10726 ins_cost(1800);
10727 format %{ "DSIN $dst" %}
10728 opcode(0xD9, 0xFE);
10729 ins_encode( OpcP, OpcS );
10730 ins_pipe( pipe_slow );
10731 %}
10733 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10734 predicate (UseSSE>=2);
10735 match(Set dst (SinD dst));
10736 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10737 ins_cost(1800);
10738 format %{ "DSIN $dst" %}
10739 opcode(0xD9, 0xFE);
10740 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10741 ins_pipe( pipe_slow );
10742 %}
10744 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10745 predicate (UseSSE<=1);
10746 match(Set dst (CosD src));
10747 ins_cost(1800);
10748 format %{ "DCOS $dst" %}
10749 opcode(0xD9, 0xFF);
10750 ins_encode( OpcP, OpcS );
10751 ins_pipe( pipe_slow );
10752 %}
10754 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10755 predicate (UseSSE>=2);
10756 match(Set dst (CosD dst));
10757 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10758 ins_cost(1800);
10759 format %{ "DCOS $dst" %}
10760 opcode(0xD9, 0xFF);
10761 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10762 ins_pipe( pipe_slow );
10763 %}
10765 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10766 predicate (UseSSE<=1);
10767 match(Set dst(TanD src));
10768 format %{ "DTAN $dst" %}
10769 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10770 Opcode(0xDD), Opcode(0xD8)); // fstp st
10771 ins_pipe( pipe_slow );
10772 %}
10774 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10775 predicate (UseSSE>=2);
10776 match(Set dst(TanD dst));
10777 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10778 format %{ "DTAN $dst" %}
10779 ins_encode( Push_SrcXD(dst),
10780 Opcode(0xD9), Opcode(0xF2), // fptan
10781 Opcode(0xDD), Opcode(0xD8), // fstp st
10782 Push_ResultXD(dst) );
10783 ins_pipe( pipe_slow );
10784 %}
10786 instruct atanD_reg(regD dst, regD src) %{
10787 predicate (UseSSE<=1);
10788 match(Set dst(AtanD dst src));
10789 format %{ "DATA $dst,$src" %}
10790 opcode(0xD9, 0xF3);
10791 ins_encode( Push_Reg_D(src),
10792 OpcP, OpcS, RegOpc(dst) );
10793 ins_pipe( pipe_slow );
10794 %}
10796 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10797 predicate (UseSSE>=2);
10798 match(Set dst(AtanD dst src));
10799 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10800 format %{ "DATA $dst,$src" %}
10801 opcode(0xD9, 0xF3);
10802 ins_encode( Push_SrcXD(src),
10803 OpcP, OpcS, Push_ResultXD(dst) );
10804 ins_pipe( pipe_slow );
10805 %}
10807 instruct sqrtD_reg(regD dst, regD src) %{
10808 predicate (UseSSE<=1);
10809 match(Set dst (SqrtD src));
10810 format %{ "DSQRT $dst,$src" %}
10811 opcode(0xFA, 0xD9);
10812 ins_encode( Push_Reg_D(src),
10813 OpcS, OpcP, Pop_Reg_D(dst) );
10814 ins_pipe( pipe_slow );
10815 %}
10817 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10818 predicate (UseSSE<=1);
10819 match(Set Y (PowD X Y)); // Raise X to the Yth power
10820 effect(KILL rax, KILL rbx, KILL rcx);
10821 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10822 "FLD_D $X\n\t"
10823 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10825 "FDUP \t\t\t# Q Q\n\t"
10826 "FRNDINT\t\t\t# int(Q) Q\n\t"
10827 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10828 "FISTP dword [ESP]\n\t"
10829 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10830 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10831 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10832 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10833 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10834 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10835 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10836 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10837 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10838 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10839 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10840 "MOV [ESP+0],0\n\t"
10841 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10843 "ADD ESP,8"
10844 %}
10845 ins_encode( push_stack_temp_qword,
10846 Push_Reg_D(X),
10847 Opcode(0xD9), Opcode(0xF1), // fyl2x
10848 pow_exp_core_encoding,
10849 pop_stack_temp_qword);
10850 ins_pipe( pipe_slow );
10851 %}
10853 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10854 predicate (UseSSE>=2);
10855 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10856 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10857 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10858 "MOVSD [ESP],$src1\n\t"
10859 "FLD FPR1,$src1\n\t"
10860 "MOVSD [ESP],$src0\n\t"
10861 "FLD FPR1,$src0\n\t"
10862 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10864 "FDUP \t\t\t# Q Q\n\t"
10865 "FRNDINT\t\t\t# int(Q) Q\n\t"
10866 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10867 "FISTP dword [ESP]\n\t"
10868 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10869 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10870 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10871 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10872 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10873 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10874 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10875 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10876 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10877 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10878 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10879 "MOV [ESP+0],0\n\t"
10880 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10882 "FST_D [ESP]\n\t"
10883 "MOVSD $dst,[ESP]\n\t"
10884 "ADD ESP,8"
10885 %}
10886 ins_encode( push_stack_temp_qword,
10887 push_xmm_to_fpr1(src1),
10888 push_xmm_to_fpr1(src0),
10889 Opcode(0xD9), Opcode(0xF1), // fyl2x
10890 pow_exp_core_encoding,
10891 Push_ResultXD(dst) );
10892 ins_pipe( pipe_slow );
10893 %}
10896 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10897 predicate (UseSSE<=1);
10898 match(Set dpr1 (ExpD dpr1));
10899 effect(KILL rax, KILL rbx, KILL rcx);
10900 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10901 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10902 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10904 "FDUP \t\t\t# Q Q\n\t"
10905 "FRNDINT\t\t\t# int(Q) Q\n\t"
10906 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10907 "FISTP dword [ESP]\n\t"
10908 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10909 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10910 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10911 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10912 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10913 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10914 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10915 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10916 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10917 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10918 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10919 "MOV [ESP+0],0\n\t"
10920 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10922 "ADD ESP,8"
10923 %}
10924 ins_encode( push_stack_temp_qword,
10925 Opcode(0xD9), Opcode(0xEA), // fldl2e
10926 Opcode(0xDE), Opcode(0xC9), // fmulp
10927 pow_exp_core_encoding,
10928 pop_stack_temp_qword);
10929 ins_pipe( pipe_slow );
10930 %}
10932 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10933 predicate (UseSSE>=2);
10934 match(Set dst (ExpD src));
10935 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10936 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10937 "MOVSD [ESP],$src\n\t"
10938 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10939 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10941 "FDUP \t\t\t# Q Q\n\t"
10942 "FRNDINT\t\t\t# int(Q) Q\n\t"
10943 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10944 "FISTP dword [ESP]\n\t"
10945 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10946 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10947 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10948 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10949 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10950 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10951 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10952 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10953 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10954 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10955 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10956 "MOV [ESP+0],0\n\t"
10957 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10959 "FST_D [ESP]\n\t"
10960 "MOVSD $dst,[ESP]\n\t"
10961 "ADD ESP,8"
10962 %}
10963 ins_encode( Push_SrcXD(src),
10964 Opcode(0xD9), Opcode(0xEA), // fldl2e
10965 Opcode(0xDE), Opcode(0xC9), // fmulp
10966 pow_exp_core_encoding,
10967 Push_ResultXD(dst) );
10968 ins_pipe( pipe_slow );
10969 %}
10973 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10974 predicate (UseSSE<=1);
10975 // The source Double operand on FPU stack
10976 match(Set dst (Log10D src));
10977 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10978 // fxch ; swap ST(0) with ST(1)
10979 // fyl2x ; compute log_10(2) * log_2(x)
10980 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10981 "FXCH \n\t"
10982 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10983 %}
10984 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10985 Opcode(0xD9), Opcode(0xC9), // fxch
10986 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10988 ins_pipe( pipe_slow );
10989 %}
10991 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10992 predicate (UseSSE>=2);
10993 effect(KILL cr);
10994 match(Set dst (Log10D src));
10995 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10996 // fyl2x ; compute log_10(2) * log_2(x)
10997 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10998 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10999 %}
11000 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
11001 Push_SrcXD(src),
11002 Opcode(0xD9), Opcode(0xF1), // fyl2x
11003 Push_ResultXD(dst));
11005 ins_pipe( pipe_slow );
11006 %}
11008 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
11009 predicate (UseSSE<=1);
11010 // The source Double operand on FPU stack
11011 match(Set dst (LogD src));
11012 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
11013 // fxch ; swap ST(0) with ST(1)
11014 // fyl2x ; compute log_e(2) * log_2(x)
11015 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
11016 "FXCH \n\t"
11017 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
11018 %}
11019 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
11020 Opcode(0xD9), Opcode(0xC9), // fxch
11021 Opcode(0xD9), Opcode(0xF1)); // fyl2x
11023 ins_pipe( pipe_slow );
11024 %}
11026 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
11027 predicate (UseSSE>=2);
11028 effect(KILL cr);
11029 // The source and result Double operands in XMM registers
11030 match(Set dst (LogD src));
11031 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
11032 // fyl2x ; compute log_e(2) * log_2(x)
11033 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
11034 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
11035 %}
11036 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
11037 Push_SrcXD(src),
11038 Opcode(0xD9), Opcode(0xF1), // fyl2x
11039 Push_ResultXD(dst));
11040 ins_pipe( pipe_slow );
11041 %}
11043 //-------------Float Instructions-------------------------------
11044 // Float Math
11046 // Code for float compare:
11047 // fcompp();
11048 // fwait(); fnstsw_ax();
11049 // sahf();
11050 // movl(dst, unordered_result);
11051 // jcc(Assembler::parity, exit);
11052 // movl(dst, less_result);
11053 // jcc(Assembler::below, exit);
11054 // movl(dst, equal_result);
11055 // jcc(Assembler::equal, exit);
11056 // movl(dst, greater_result);
11057 // exit:
11059 // P6 version of float compare, sets condition codes in EFLAGS
11060 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
11061 predicate(VM_Version::supports_cmov() && UseSSE == 0);
11062 match(Set cr (CmpF src1 src2));
11063 effect(KILL rax);
11064 ins_cost(150);
11065 format %{ "FLD $src1\n\t"
11066 "FUCOMIP ST,$src2 // P6 instruction\n\t"
11067 "JNP exit\n\t"
11068 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
11069 "SAHF\n"
11070 "exit:\tNOP // avoid branch to branch" %}
11071 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11072 ins_encode( Push_Reg_D(src1),
11073 OpcP, RegOpc(src2),
11074 cmpF_P6_fixup );
11075 ins_pipe( pipe_slow );
11076 %}
11078 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
11079 predicate(VM_Version::supports_cmov() && UseSSE == 0);
11080 match(Set cr (CmpF src1 src2));
11081 ins_cost(100);
11082 format %{ "FLD $src1\n\t"
11083 "FUCOMIP ST,$src2 // P6 instruction" %}
11084 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11085 ins_encode( Push_Reg_D(src1),
11086 OpcP, RegOpc(src2));
11087 ins_pipe( pipe_slow );
11088 %}
11091 // Compare & branch
11092 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
11093 predicate(UseSSE == 0);
11094 match(Set cr (CmpF src1 src2));
11095 effect(KILL rax);
11096 ins_cost(200);
11097 format %{ "FLD $src1\n\t"
11098 "FCOMp $src2\n\t"
11099 "FNSTSW AX\n\t"
11100 "TEST AX,0x400\n\t"
11101 "JZ,s flags\n\t"
11102 "MOV AH,1\t# unordered treat as LT\n"
11103 "flags:\tSAHF" %}
11104 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11105 ins_encode( Push_Reg_D(src1),
11106 OpcP, RegOpc(src2),
11107 fpu_flags);
11108 ins_pipe( pipe_slow );
11109 %}
11111 // Compare vs zero into -1,0,1
11112 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
11113 predicate(UseSSE == 0);
11114 match(Set dst (CmpF3 src1 zero));
11115 effect(KILL cr, KILL rax);
11116 ins_cost(280);
11117 format %{ "FTSTF $dst,$src1" %}
11118 opcode(0xE4, 0xD9);
11119 ins_encode( Push_Reg_D(src1),
11120 OpcS, OpcP, PopFPU,
11121 CmpF_Result(dst));
11122 ins_pipe( pipe_slow );
11123 %}
11125 // Compare into -1,0,1
11126 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11127 predicate(UseSSE == 0);
11128 match(Set dst (CmpF3 src1 src2));
11129 effect(KILL cr, KILL rax);
11130 ins_cost(300);
11131 format %{ "FCMPF $dst,$src1,$src2" %}
11132 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11133 ins_encode( Push_Reg_D(src1),
11134 OpcP, RegOpc(src2),
11135 CmpF_Result(dst));
11136 ins_pipe( pipe_slow );
11137 %}
11139 // float compare and set condition codes in EFLAGS by XMM regs
11140 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
11141 predicate(UseSSE>=1);
11142 match(Set cr (CmpF dst src));
11143 effect(KILL rax);
11144 ins_cost(145);
11145 format %{ "COMISS $dst,$src\n"
11146 "\tJNP exit\n"
11147 "\tMOV ah,1 // saw a NaN, set CF\n"
11148 "\tSAHF\n"
11149 "exit:\tNOP // avoid branch to branch" %}
11150 opcode(0x0F, 0x2F);
11151 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
11152 ins_pipe( pipe_slow );
11153 %}
11155 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
11156 predicate(UseSSE>=1);
11157 match(Set cr (CmpF dst src));
11158 ins_cost(100);
11159 format %{ "COMISS $dst,$src" %}
11160 opcode(0x0F, 0x2F);
11161 ins_encode(OpcP, OpcS, RegReg(dst, src));
11162 ins_pipe( pipe_slow );
11163 %}
11165 // float compare and set condition codes in EFLAGS by XMM regs
11166 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
11167 predicate(UseSSE>=1);
11168 match(Set cr (CmpF dst (LoadF src)));
11169 effect(KILL rax);
11170 ins_cost(165);
11171 format %{ "COMISS $dst,$src\n"
11172 "\tJNP exit\n"
11173 "\tMOV ah,1 // saw a NaN, set CF\n"
11174 "\tSAHF\n"
11175 "exit:\tNOP // avoid branch to branch" %}
11176 opcode(0x0F, 0x2F);
11177 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
11178 ins_pipe( pipe_slow );
11179 %}
11181 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
11182 predicate(UseSSE>=1);
11183 match(Set cr (CmpF dst (LoadF src)));
11184 ins_cost(100);
11185 format %{ "COMISS $dst,$src" %}
11186 opcode(0x0F, 0x2F);
11187 ins_encode(OpcP, OpcS, RegMem(dst, src));
11188 ins_pipe( pipe_slow );
11189 %}
11191 // Compare into -1,0,1 in XMM
11192 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
11193 predicate(UseSSE>=1);
11194 match(Set dst (CmpF3 src1 src2));
11195 effect(KILL cr);
11196 ins_cost(255);
11197 format %{ "XOR $dst,$dst\n"
11198 "\tCOMISS $src1,$src2\n"
11199 "\tJP,s nan\n"
11200 "\tJEQ,s exit\n"
11201 "\tJA,s inc\n"
11202 "nan:\tDEC $dst\n"
11203 "\tJMP,s exit\n"
11204 "inc:\tINC $dst\n"
11205 "exit:"
11206 %}
11207 opcode(0x0F, 0x2F);
11208 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
11209 ins_pipe( pipe_slow );
11210 %}
11212 // Compare into -1,0,1 in XMM and memory
11213 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
11214 predicate(UseSSE>=1);
11215 match(Set dst (CmpF3 src1 (LoadF mem)));
11216 effect(KILL cr);
11217 ins_cost(275);
11218 format %{ "COMISS $src1,$mem\n"
11219 "\tMOV $dst,0\t\t# do not blow flags\n"
11220 "\tJP,s nan\n"
11221 "\tJEQ,s exit\n"
11222 "\tJA,s inc\n"
11223 "nan:\tDEC $dst\n"
11224 "\tJMP,s exit\n"
11225 "inc:\tINC $dst\n"
11226 "exit:"
11227 %}
11228 opcode(0x0F, 0x2F);
11229 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
11230 ins_pipe( pipe_slow );
11231 %}
11233 // Spill to obtain 24-bit precision
11234 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
11235 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11236 match(Set dst (SubF src1 src2));
11238 format %{ "FSUB $dst,$src1 - $src2" %}
11239 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
11240 ins_encode( Push_Reg_F(src1),
11241 OpcReg_F(src2),
11242 Pop_Mem_F(dst) );
11243 ins_pipe( fpu_mem_reg_reg );
11244 %}
11245 //
11246 // This instruction does not round to 24-bits
11247 instruct subF_reg(regF dst, regF src) %{
11248 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11249 match(Set dst (SubF dst src));
11251 format %{ "FSUB $dst,$src" %}
11252 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
11253 ins_encode( Push_Reg_F(src),
11254 OpcP, RegOpc(dst) );
11255 ins_pipe( fpu_reg_reg );
11256 %}
11258 // Spill to obtain 24-bit precision
11259 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
11260 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11261 match(Set dst (AddF src1 src2));
11263 format %{ "FADD $dst,$src1,$src2" %}
11264 opcode(0xD8, 0x0); /* D8 C0+i */
11265 ins_encode( Push_Reg_F(src2),
11266 OpcReg_F(src1),
11267 Pop_Mem_F(dst) );
11268 ins_pipe( fpu_mem_reg_reg );
11269 %}
11270 //
11271 // This instruction does not round to 24-bits
11272 instruct addF_reg(regF dst, regF src) %{
11273 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11274 match(Set dst (AddF dst src));
11276 format %{ "FLD $src\n\t"
11277 "FADDp $dst,ST" %}
11278 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
11279 ins_encode( Push_Reg_F(src),
11280 OpcP, RegOpc(dst) );
11281 ins_pipe( fpu_reg_reg );
11282 %}
11284 // Add two single precision floating point values in xmm
11285 instruct addX_reg(regX dst, regX src) %{
11286 predicate(UseSSE>=1);
11287 match(Set dst (AddF dst src));
11288 format %{ "ADDSS $dst,$src" %}
11289 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11290 ins_pipe( pipe_slow );
11291 %}
11293 instruct addX_imm(regX dst, immXF con) %{
11294 predicate(UseSSE>=1);
11295 match(Set dst (AddF dst con));
11296 format %{ "ADDSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11297 ins_encode %{
11298 __ addss($dst$$XMMRegister, $constantaddress($con));
11299 %}
11300 ins_pipe(pipe_slow);
11301 %}
11303 instruct addX_mem(regX dst, memory mem) %{
11304 predicate(UseSSE>=1);
11305 match(Set dst (AddF dst (LoadF mem)));
11306 format %{ "ADDSS $dst,$mem" %}
11307 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11308 ins_pipe( pipe_slow );
11309 %}
11311 // Subtract two single precision floating point values in xmm
11312 instruct subX_reg(regX dst, regX src) %{
11313 predicate(UseSSE>=1);
11314 match(Set dst (SubF dst src));
11315 format %{ "SUBSS $dst,$src" %}
11316 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11317 ins_pipe( pipe_slow );
11318 %}
11320 instruct subX_imm(regX dst, immXF con) %{
11321 predicate(UseSSE>=1);
11322 match(Set dst (SubF dst con));
11323 format %{ "SUBSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11324 ins_encode %{
11325 __ subss($dst$$XMMRegister, $constantaddress($con));
11326 %}
11327 ins_pipe(pipe_slow);
11328 %}
11330 instruct subX_mem(regX dst, memory mem) %{
11331 predicate(UseSSE>=1);
11332 match(Set dst (SubF dst (LoadF mem)));
11333 format %{ "SUBSS $dst,$mem" %}
11334 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11335 ins_pipe( pipe_slow );
11336 %}
11338 // Multiply two single precision floating point values in xmm
11339 instruct mulX_reg(regX dst, regX src) %{
11340 predicate(UseSSE>=1);
11341 match(Set dst (MulF dst src));
11342 format %{ "MULSS $dst,$src" %}
11343 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11344 ins_pipe( pipe_slow );
11345 %}
11347 instruct mulX_imm(regX dst, immXF con) %{
11348 predicate(UseSSE>=1);
11349 match(Set dst (MulF dst con));
11350 format %{ "MULSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11351 ins_encode %{
11352 __ mulss($dst$$XMMRegister, $constantaddress($con));
11353 %}
11354 ins_pipe(pipe_slow);
11355 %}
11357 instruct mulX_mem(regX dst, memory mem) %{
11358 predicate(UseSSE>=1);
11359 match(Set dst (MulF dst (LoadF mem)));
11360 format %{ "MULSS $dst,$mem" %}
11361 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11362 ins_pipe( pipe_slow );
11363 %}
11365 // Divide two single precision floating point values in xmm
11366 instruct divX_reg(regX dst, regX src) %{
11367 predicate(UseSSE>=1);
11368 match(Set dst (DivF dst src));
11369 format %{ "DIVSS $dst,$src" %}
11370 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11371 ins_pipe( pipe_slow );
11372 %}
11374 instruct divX_imm(regX dst, immXF con) %{
11375 predicate(UseSSE>=1);
11376 match(Set dst (DivF dst con));
11377 format %{ "DIVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11378 ins_encode %{
11379 __ divss($dst$$XMMRegister, $constantaddress($con));
11380 %}
11381 ins_pipe(pipe_slow);
11382 %}
11384 instruct divX_mem(regX dst, memory mem) %{
11385 predicate(UseSSE>=1);
11386 match(Set dst (DivF dst (LoadF mem)));
11387 format %{ "DIVSS $dst,$mem" %}
11388 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11389 ins_pipe( pipe_slow );
11390 %}
11392 // Get the square root of a single precision floating point values in xmm
11393 instruct sqrtX_reg(regX dst, regX src) %{
11394 predicate(UseSSE>=1);
11395 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11396 format %{ "SQRTSS $dst,$src" %}
11397 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11398 ins_pipe( pipe_slow );
11399 %}
11401 instruct sqrtX_mem(regX dst, memory mem) %{
11402 predicate(UseSSE>=1);
11403 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11404 format %{ "SQRTSS $dst,$mem" %}
11405 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11406 ins_pipe( pipe_slow );
11407 %}
11409 // Get the square root of a double precision floating point values in xmm
11410 instruct sqrtXD_reg(regXD dst, regXD src) %{
11411 predicate(UseSSE>=2);
11412 match(Set dst (SqrtD src));
11413 format %{ "SQRTSD $dst,$src" %}
11414 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11415 ins_pipe( pipe_slow );
11416 %}
11418 instruct sqrtXD_mem(regXD dst, memory mem) %{
11419 predicate(UseSSE>=2);
11420 match(Set dst (SqrtD (LoadD mem)));
11421 format %{ "SQRTSD $dst,$mem" %}
11422 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11423 ins_pipe( pipe_slow );
11424 %}
11426 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11427 predicate(UseSSE==0);
11428 match(Set dst (AbsF src));
11429 ins_cost(100);
11430 format %{ "FABS" %}
11431 opcode(0xE1, 0xD9);
11432 ins_encode( OpcS, OpcP );
11433 ins_pipe( fpu_reg_reg );
11434 %}
11436 instruct absX_reg(regX dst ) %{
11437 predicate(UseSSE>=1);
11438 match(Set dst (AbsF dst));
11439 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11440 ins_encode( AbsXF_encoding(dst));
11441 ins_pipe( pipe_slow );
11442 %}
11444 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11445 predicate(UseSSE==0);
11446 match(Set dst (NegF src));
11447 ins_cost(100);
11448 format %{ "FCHS" %}
11449 opcode(0xE0, 0xD9);
11450 ins_encode( OpcS, OpcP );
11451 ins_pipe( fpu_reg_reg );
11452 %}
11454 instruct negX_reg( regX dst ) %{
11455 predicate(UseSSE>=1);
11456 match(Set dst (NegF dst));
11457 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11458 ins_encode( NegXF_encoding(dst));
11459 ins_pipe( pipe_slow );
11460 %}
11462 // Cisc-alternate to addF_reg
11463 // Spill to obtain 24-bit precision
11464 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11465 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11466 match(Set dst (AddF src1 (LoadF src2)));
11468 format %{ "FLD $src2\n\t"
11469 "FADD ST,$src1\n\t"
11470 "FSTP_S $dst" %}
11471 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11472 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11473 OpcReg_F(src1),
11474 Pop_Mem_F(dst) );
11475 ins_pipe( fpu_mem_reg_mem );
11476 %}
11477 //
11478 // Cisc-alternate to addF_reg
11479 // This instruction does not round to 24-bits
11480 instruct addF_reg_mem(regF dst, memory src) %{
11481 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11482 match(Set dst (AddF dst (LoadF src)));
11484 format %{ "FADD $dst,$src" %}
11485 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11486 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11487 OpcP, RegOpc(dst) );
11488 ins_pipe( fpu_reg_mem );
11489 %}
11491 // // Following two instructions for _222_mpegaudio
11492 // Spill to obtain 24-bit precision
11493 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11494 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11495 match(Set dst (AddF src1 src2));
11497 format %{ "FADD $dst,$src1,$src2" %}
11498 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11499 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11500 OpcReg_F(src2),
11501 Pop_Mem_F(dst) );
11502 ins_pipe( fpu_mem_reg_mem );
11503 %}
11505 // Cisc-spill variant
11506 // Spill to obtain 24-bit precision
11507 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11508 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11509 match(Set dst (AddF src1 (LoadF src2)));
11511 format %{ "FADD $dst,$src1,$src2 cisc" %}
11512 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11513 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11514 set_instruction_start,
11515 OpcP, RMopc_Mem(secondary,src1),
11516 Pop_Mem_F(dst) );
11517 ins_pipe( fpu_mem_mem_mem );
11518 %}
11520 // Spill to obtain 24-bit precision
11521 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11522 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11523 match(Set dst (AddF src1 src2));
11525 format %{ "FADD $dst,$src1,$src2" %}
11526 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11527 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11528 set_instruction_start,
11529 OpcP, RMopc_Mem(secondary,src1),
11530 Pop_Mem_F(dst) );
11531 ins_pipe( fpu_mem_mem_mem );
11532 %}
11535 // Spill to obtain 24-bit precision
11536 instruct addF24_reg_imm(stackSlotF dst, regF src, immF con) %{
11537 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11538 match(Set dst (AddF src con));
11539 format %{ "FLD $src\n\t"
11540 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11541 "FSTP_S $dst" %}
11542 ins_encode %{
11543 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11544 __ fadd_s($constantaddress($con));
11545 __ fstp_s(Address(rsp, $dst$$disp));
11546 %}
11547 ins_pipe(fpu_mem_reg_con);
11548 %}
11549 //
11550 // This instruction does not round to 24-bits
11551 instruct addF_reg_imm(regF dst, regF src, immF con) %{
11552 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11553 match(Set dst (AddF src con));
11554 format %{ "FLD $src\n\t"
11555 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11556 "FSTP $dst" %}
11557 ins_encode %{
11558 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11559 __ fadd_s($constantaddress($con));
11560 __ fstp_d($dst$$reg);
11561 %}
11562 ins_pipe(fpu_reg_reg_con);
11563 %}
11565 // Spill to obtain 24-bit precision
11566 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11567 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11568 match(Set dst (MulF src1 src2));
11570 format %{ "FLD $src1\n\t"
11571 "FMUL $src2\n\t"
11572 "FSTP_S $dst" %}
11573 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11574 ins_encode( Push_Reg_F(src1),
11575 OpcReg_F(src2),
11576 Pop_Mem_F(dst) );
11577 ins_pipe( fpu_mem_reg_reg );
11578 %}
11579 //
11580 // This instruction does not round to 24-bits
11581 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11582 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11583 match(Set dst (MulF src1 src2));
11585 format %{ "FLD $src1\n\t"
11586 "FMUL $src2\n\t"
11587 "FSTP_S $dst" %}
11588 opcode(0xD8, 0x1); /* D8 C8+i */
11589 ins_encode( Push_Reg_F(src2),
11590 OpcReg_F(src1),
11591 Pop_Reg_F(dst) );
11592 ins_pipe( fpu_reg_reg_reg );
11593 %}
11596 // Spill to obtain 24-bit precision
11597 // Cisc-alternate to reg-reg multiply
11598 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11599 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11600 match(Set dst (MulF src1 (LoadF src2)));
11602 format %{ "FLD_S $src2\n\t"
11603 "FMUL $src1\n\t"
11604 "FSTP_S $dst" %}
11605 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11606 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11607 OpcReg_F(src1),
11608 Pop_Mem_F(dst) );
11609 ins_pipe( fpu_mem_reg_mem );
11610 %}
11611 //
11612 // This instruction does not round to 24-bits
11613 // Cisc-alternate to reg-reg multiply
11614 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11615 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11616 match(Set dst (MulF src1 (LoadF src2)));
11618 format %{ "FMUL $dst,$src1,$src2" %}
11619 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11620 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11621 OpcReg_F(src1),
11622 Pop_Reg_F(dst) );
11623 ins_pipe( fpu_reg_reg_mem );
11624 %}
11626 // Spill to obtain 24-bit precision
11627 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11628 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11629 match(Set dst (MulF src1 src2));
11631 format %{ "FMUL $dst,$src1,$src2" %}
11632 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11633 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11634 set_instruction_start,
11635 OpcP, RMopc_Mem(secondary,src1),
11636 Pop_Mem_F(dst) );
11637 ins_pipe( fpu_mem_mem_mem );
11638 %}
11640 // Spill to obtain 24-bit precision
11641 instruct mulF24_reg_imm(stackSlotF dst, regF src, immF con) %{
11642 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11643 match(Set dst (MulF src con));
11645 format %{ "FLD $src\n\t"
11646 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11647 "FSTP_S $dst" %}
11648 ins_encode %{
11649 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11650 __ fmul_s($constantaddress($con));
11651 __ fstp_s(Address(rsp, $dst$$disp));
11652 %}
11653 ins_pipe(fpu_mem_reg_con);
11654 %}
11655 //
11656 // This instruction does not round to 24-bits
11657 instruct mulF_reg_imm(regF dst, regF src, immF con) %{
11658 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11659 match(Set dst (MulF src con));
11661 format %{ "FLD $src\n\t"
11662 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11663 "FSTP $dst" %}
11664 ins_encode %{
11665 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11666 __ fmul_s($constantaddress($con));
11667 __ fstp_d($dst$$reg);
11668 %}
11669 ins_pipe(fpu_reg_reg_con);
11670 %}
11673 //
11674 // MACRO1 -- subsume unshared load into mulF
11675 // This instruction does not round to 24-bits
11676 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11677 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11678 match(Set dst (MulF (LoadF mem1) src));
11680 format %{ "FLD $mem1 ===MACRO1===\n\t"
11681 "FMUL ST,$src\n\t"
11682 "FSTP $dst" %}
11683 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11684 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11685 OpcReg_F(src),
11686 Pop_Reg_F(dst) );
11687 ins_pipe( fpu_reg_reg_mem );
11688 %}
11689 //
11690 // MACRO2 -- addF a mulF which subsumed an unshared load
11691 // This instruction does not round to 24-bits
11692 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11693 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11694 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11695 ins_cost(95);
11697 format %{ "FLD $mem1 ===MACRO2===\n\t"
11698 "FMUL ST,$src1 subsume mulF left load\n\t"
11699 "FADD ST,$src2\n\t"
11700 "FSTP $dst" %}
11701 opcode(0xD9); /* LoadF D9 /0 */
11702 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11703 FMul_ST_reg(src1),
11704 FAdd_ST_reg(src2),
11705 Pop_Reg_F(dst) );
11706 ins_pipe( fpu_reg_mem_reg_reg );
11707 %}
11709 // MACRO3 -- addF a mulF
11710 // This instruction does not round to 24-bits. It is a '2-address'
11711 // instruction in that the result goes back to src2. This eliminates
11712 // a move from the macro; possibly the register allocator will have
11713 // to add it back (and maybe not).
11714 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11715 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11716 match(Set src2 (AddF (MulF src0 src1) src2));
11718 format %{ "FLD $src0 ===MACRO3===\n\t"
11719 "FMUL ST,$src1\n\t"
11720 "FADDP $src2,ST" %}
11721 opcode(0xD9); /* LoadF D9 /0 */
11722 ins_encode( Push_Reg_F(src0),
11723 FMul_ST_reg(src1),
11724 FAddP_reg_ST(src2) );
11725 ins_pipe( fpu_reg_reg_reg );
11726 %}
11728 // MACRO4 -- divF subF
11729 // This instruction does not round to 24-bits
11730 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11731 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11732 match(Set dst (DivF (SubF src2 src1) src3));
11734 format %{ "FLD $src2 ===MACRO4===\n\t"
11735 "FSUB ST,$src1\n\t"
11736 "FDIV ST,$src3\n\t"
11737 "FSTP $dst" %}
11738 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11739 ins_encode( Push_Reg_F(src2),
11740 subF_divF_encode(src1,src3),
11741 Pop_Reg_F(dst) );
11742 ins_pipe( fpu_reg_reg_reg_reg );
11743 %}
11745 // Spill to obtain 24-bit precision
11746 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11747 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11748 match(Set dst (DivF src1 src2));
11750 format %{ "FDIV $dst,$src1,$src2" %}
11751 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11752 ins_encode( Push_Reg_F(src1),
11753 OpcReg_F(src2),
11754 Pop_Mem_F(dst) );
11755 ins_pipe( fpu_mem_reg_reg );
11756 %}
11757 //
11758 // This instruction does not round to 24-bits
11759 instruct divF_reg(regF dst, regF src) %{
11760 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11761 match(Set dst (DivF dst src));
11763 format %{ "FDIV $dst,$src" %}
11764 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11765 ins_encode( Push_Reg_F(src),
11766 OpcP, RegOpc(dst) );
11767 ins_pipe( fpu_reg_reg );
11768 %}
11771 // Spill to obtain 24-bit precision
11772 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11773 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11774 match(Set dst (ModF src1 src2));
11775 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11777 format %{ "FMOD $dst,$src1,$src2" %}
11778 ins_encode( Push_Reg_Mod_D(src1, src2),
11779 emitModD(),
11780 Push_Result_Mod_D(src2),
11781 Pop_Mem_F(dst));
11782 ins_pipe( pipe_slow );
11783 %}
11784 //
11785 // This instruction does not round to 24-bits
11786 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11787 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11788 match(Set dst (ModF dst src));
11789 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11791 format %{ "FMOD $dst,$src" %}
11792 ins_encode(Push_Reg_Mod_D(dst, src),
11793 emitModD(),
11794 Push_Result_Mod_D(src),
11795 Pop_Reg_F(dst));
11796 ins_pipe( pipe_slow );
11797 %}
11799 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11800 predicate(UseSSE>=1);
11801 match(Set dst (ModF src0 src1));
11802 effect(KILL rax, KILL cr);
11803 format %{ "SUB ESP,4\t # FMOD\n"
11804 "\tMOVSS [ESP+0],$src1\n"
11805 "\tFLD_S [ESP+0]\n"
11806 "\tMOVSS [ESP+0],$src0\n"
11807 "\tFLD_S [ESP+0]\n"
11808 "loop:\tFPREM\n"
11809 "\tFWAIT\n"
11810 "\tFNSTSW AX\n"
11811 "\tSAHF\n"
11812 "\tJP loop\n"
11813 "\tFSTP_S [ESP+0]\n"
11814 "\tMOVSS $dst,[ESP+0]\n"
11815 "\tADD ESP,4\n"
11816 "\tFSTP ST0\t # Restore FPU Stack"
11817 %}
11818 ins_cost(250);
11819 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11820 ins_pipe( pipe_slow );
11821 %}
11824 //----------Arithmetic Conversion Instructions---------------------------------
11825 // The conversions operations are all Alpha sorted. Please keep it that way!
11827 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11828 predicate(UseSSE==0);
11829 match(Set dst (RoundFloat src));
11830 ins_cost(125);
11831 format %{ "FST_S $dst,$src\t# F-round" %}
11832 ins_encode( Pop_Mem_Reg_F(dst, src) );
11833 ins_pipe( fpu_mem_reg );
11834 %}
11836 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11837 predicate(UseSSE<=1);
11838 match(Set dst (RoundDouble src));
11839 ins_cost(125);
11840 format %{ "FST_D $dst,$src\t# D-round" %}
11841 ins_encode( Pop_Mem_Reg_D(dst, src) );
11842 ins_pipe( fpu_mem_reg );
11843 %}
11845 // Force rounding to 24-bit precision and 6-bit exponent
11846 instruct convD2F_reg(stackSlotF dst, regD src) %{
11847 predicate(UseSSE==0);
11848 match(Set dst (ConvD2F src));
11849 format %{ "FST_S $dst,$src\t# F-round" %}
11850 expand %{
11851 roundFloat_mem_reg(dst,src);
11852 %}
11853 %}
11855 // Force rounding to 24-bit precision and 6-bit exponent
11856 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11857 predicate(UseSSE==1);
11858 match(Set dst (ConvD2F src));
11859 effect( KILL cr );
11860 format %{ "SUB ESP,4\n\t"
11861 "FST_S [ESP],$src\t# F-round\n\t"
11862 "MOVSS $dst,[ESP]\n\t"
11863 "ADD ESP,4" %}
11864 ins_encode( D2X_encoding(dst, src) );
11865 ins_pipe( pipe_slow );
11866 %}
11868 // Force rounding double precision to single precision
11869 instruct convXD2X_reg(regX dst, regXD src) %{
11870 predicate(UseSSE>=2);
11871 match(Set dst (ConvD2F src));
11872 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11873 opcode(0xF2, 0x0F, 0x5A);
11874 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11875 ins_pipe( pipe_slow );
11876 %}
11878 instruct convF2D_reg_reg(regD dst, regF src) %{
11879 predicate(UseSSE==0);
11880 match(Set dst (ConvF2D src));
11881 format %{ "FST_S $dst,$src\t# D-round" %}
11882 ins_encode( Pop_Reg_Reg_D(dst, src));
11883 ins_pipe( fpu_reg_reg );
11884 %}
11886 instruct convF2D_reg(stackSlotD dst, regF src) %{
11887 predicate(UseSSE==1);
11888 match(Set dst (ConvF2D src));
11889 format %{ "FST_D $dst,$src\t# D-round" %}
11890 expand %{
11891 roundDouble_mem_reg(dst,src);
11892 %}
11893 %}
11895 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11896 predicate(UseSSE==1);
11897 match(Set dst (ConvF2D src));
11898 effect( KILL cr );
11899 format %{ "SUB ESP,4\n\t"
11900 "MOVSS [ESP] $src\n\t"
11901 "FLD_S [ESP]\n\t"
11902 "ADD ESP,4\n\t"
11903 "FSTP $dst\t# D-round" %}
11904 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11905 ins_pipe( pipe_slow );
11906 %}
11908 instruct convX2XD_reg(regXD dst, regX src) %{
11909 predicate(UseSSE>=2);
11910 match(Set dst (ConvF2D src));
11911 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11912 opcode(0xF3, 0x0F, 0x5A);
11913 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11914 ins_pipe( pipe_slow );
11915 %}
11917 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11918 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11919 predicate(UseSSE<=1);
11920 match(Set dst (ConvD2I src));
11921 effect( KILL tmp, KILL cr );
11922 format %{ "FLD $src\t# Convert double to int \n\t"
11923 "FLDCW trunc mode\n\t"
11924 "SUB ESP,4\n\t"
11925 "FISTp [ESP + #0]\n\t"
11926 "FLDCW std/24-bit mode\n\t"
11927 "POP EAX\n\t"
11928 "CMP EAX,0x80000000\n\t"
11929 "JNE,s fast\n\t"
11930 "FLD_D $src\n\t"
11931 "CALL d2i_wrapper\n"
11932 "fast:" %}
11933 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11934 ins_pipe( pipe_slow );
11935 %}
11937 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11938 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11939 predicate(UseSSE>=2);
11940 match(Set dst (ConvD2I src));
11941 effect( KILL tmp, KILL cr );
11942 format %{ "CVTTSD2SI $dst, $src\n\t"
11943 "CMP $dst,0x80000000\n\t"
11944 "JNE,s fast\n\t"
11945 "SUB ESP, 8\n\t"
11946 "MOVSD [ESP], $src\n\t"
11947 "FLD_D [ESP]\n\t"
11948 "ADD ESP, 8\n\t"
11949 "CALL d2i_wrapper\n"
11950 "fast:" %}
11951 opcode(0x1); // double-precision conversion
11952 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11953 ins_pipe( pipe_slow );
11954 %}
11956 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11957 predicate(UseSSE<=1);
11958 match(Set dst (ConvD2L src));
11959 effect( KILL cr );
11960 format %{ "FLD $src\t# Convert double to long\n\t"
11961 "FLDCW trunc mode\n\t"
11962 "SUB ESP,8\n\t"
11963 "FISTp [ESP + #0]\n\t"
11964 "FLDCW std/24-bit mode\n\t"
11965 "POP EAX\n\t"
11966 "POP EDX\n\t"
11967 "CMP EDX,0x80000000\n\t"
11968 "JNE,s fast\n\t"
11969 "TEST EAX,EAX\n\t"
11970 "JNE,s fast\n\t"
11971 "FLD $src\n\t"
11972 "CALL d2l_wrapper\n"
11973 "fast:" %}
11974 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11975 ins_pipe( pipe_slow );
11976 %}
11978 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11979 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11980 predicate (UseSSE>=2);
11981 match(Set dst (ConvD2L src));
11982 effect( KILL cr );
11983 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11984 "MOVSD [ESP],$src\n\t"
11985 "FLD_D [ESP]\n\t"
11986 "FLDCW trunc mode\n\t"
11987 "FISTp [ESP + #0]\n\t"
11988 "FLDCW std/24-bit mode\n\t"
11989 "POP EAX\n\t"
11990 "POP EDX\n\t"
11991 "CMP EDX,0x80000000\n\t"
11992 "JNE,s fast\n\t"
11993 "TEST EAX,EAX\n\t"
11994 "JNE,s fast\n\t"
11995 "SUB ESP,8\n\t"
11996 "MOVSD [ESP],$src\n\t"
11997 "FLD_D [ESP]\n\t"
11998 "CALL d2l_wrapper\n"
11999 "fast:" %}
12000 ins_encode( XD2L_encoding(src) );
12001 ins_pipe( pipe_slow );
12002 %}
12004 // Convert a double to an int. Java semantics require we do complex
12005 // manglations in the corner cases. So we set the rounding mode to
12006 // 'zero', store the darned double down as an int, and reset the
12007 // rounding mode to 'nearest'. The hardware stores a flag value down
12008 // if we would overflow or converted a NAN; we check for this and
12009 // and go the slow path if needed.
12010 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
12011 predicate(UseSSE==0);
12012 match(Set dst (ConvF2I src));
12013 effect( KILL tmp, KILL cr );
12014 format %{ "FLD $src\t# Convert float to int \n\t"
12015 "FLDCW trunc mode\n\t"
12016 "SUB ESP,4\n\t"
12017 "FISTp [ESP + #0]\n\t"
12018 "FLDCW std/24-bit mode\n\t"
12019 "POP EAX\n\t"
12020 "CMP EAX,0x80000000\n\t"
12021 "JNE,s fast\n\t"
12022 "FLD $src\n\t"
12023 "CALL d2i_wrapper\n"
12024 "fast:" %}
12025 // D2I_encoding works for F2I
12026 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
12027 ins_pipe( pipe_slow );
12028 %}
12030 // Convert a float in xmm to an int reg.
12031 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
12032 predicate(UseSSE>=1);
12033 match(Set dst (ConvF2I src));
12034 effect( KILL tmp, KILL cr );
12035 format %{ "CVTTSS2SI $dst, $src\n\t"
12036 "CMP $dst,0x80000000\n\t"
12037 "JNE,s fast\n\t"
12038 "SUB ESP, 4\n\t"
12039 "MOVSS [ESP], $src\n\t"
12040 "FLD [ESP]\n\t"
12041 "ADD ESP, 4\n\t"
12042 "CALL d2i_wrapper\n"
12043 "fast:" %}
12044 opcode(0x0); // single-precision conversion
12045 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
12046 ins_pipe( pipe_slow );
12047 %}
12049 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
12050 predicate(UseSSE==0);
12051 match(Set dst (ConvF2L src));
12052 effect( KILL cr );
12053 format %{ "FLD $src\t# Convert float to long\n\t"
12054 "FLDCW trunc mode\n\t"
12055 "SUB ESP,8\n\t"
12056 "FISTp [ESP + #0]\n\t"
12057 "FLDCW std/24-bit mode\n\t"
12058 "POP EAX\n\t"
12059 "POP EDX\n\t"
12060 "CMP EDX,0x80000000\n\t"
12061 "JNE,s fast\n\t"
12062 "TEST EAX,EAX\n\t"
12063 "JNE,s fast\n\t"
12064 "FLD $src\n\t"
12065 "CALL d2l_wrapper\n"
12066 "fast:" %}
12067 // D2L_encoding works for F2L
12068 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
12069 ins_pipe( pipe_slow );
12070 %}
12072 // XMM lacks a float/double->long conversion, so use the old FPU stack.
12073 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
12074 predicate (UseSSE>=1);
12075 match(Set dst (ConvF2L src));
12076 effect( KILL cr );
12077 format %{ "SUB ESP,8\t# Convert float to long\n\t"
12078 "MOVSS [ESP],$src\n\t"
12079 "FLD_S [ESP]\n\t"
12080 "FLDCW trunc mode\n\t"
12081 "FISTp [ESP + #0]\n\t"
12082 "FLDCW std/24-bit mode\n\t"
12083 "POP EAX\n\t"
12084 "POP EDX\n\t"
12085 "CMP EDX,0x80000000\n\t"
12086 "JNE,s fast\n\t"
12087 "TEST EAX,EAX\n\t"
12088 "JNE,s fast\n\t"
12089 "SUB ESP,4\t# Convert float to long\n\t"
12090 "MOVSS [ESP],$src\n\t"
12091 "FLD_S [ESP]\n\t"
12092 "ADD ESP,4\n\t"
12093 "CALL d2l_wrapper\n"
12094 "fast:" %}
12095 ins_encode( X2L_encoding(src) );
12096 ins_pipe( pipe_slow );
12097 %}
12099 instruct convI2D_reg(regD dst, stackSlotI src) %{
12100 predicate( UseSSE<=1 );
12101 match(Set dst (ConvI2D src));
12102 format %{ "FILD $src\n\t"
12103 "FSTP $dst" %}
12104 opcode(0xDB, 0x0); /* DB /0 */
12105 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
12106 ins_pipe( fpu_reg_mem );
12107 %}
12109 instruct convI2XD_reg(regXD dst, eRegI src) %{
12110 predicate( UseSSE>=2 && !UseXmmI2D );
12111 match(Set dst (ConvI2D src));
12112 format %{ "CVTSI2SD $dst,$src" %}
12113 opcode(0xF2, 0x0F, 0x2A);
12114 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12115 ins_pipe( pipe_slow );
12116 %}
12118 instruct convI2XD_mem(regXD dst, memory mem) %{
12119 predicate( UseSSE>=2 );
12120 match(Set dst (ConvI2D (LoadI mem)));
12121 format %{ "CVTSI2SD $dst,$mem" %}
12122 opcode(0xF2, 0x0F, 0x2A);
12123 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
12124 ins_pipe( pipe_slow );
12125 %}
12127 instruct convXI2XD_reg(regXD dst, eRegI src)
12128 %{
12129 predicate( UseSSE>=2 && UseXmmI2D );
12130 match(Set dst (ConvI2D src));
12132 format %{ "MOVD $dst,$src\n\t"
12133 "CVTDQ2PD $dst,$dst\t# i2d" %}
12134 ins_encode %{
12135 __ movdl($dst$$XMMRegister, $src$$Register);
12136 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
12137 %}
12138 ins_pipe(pipe_slow); // XXX
12139 %}
12141 instruct convI2D_mem(regD dst, memory mem) %{
12142 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
12143 match(Set dst (ConvI2D (LoadI mem)));
12144 format %{ "FILD $mem\n\t"
12145 "FSTP $dst" %}
12146 opcode(0xDB); /* DB /0 */
12147 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12148 Pop_Reg_D(dst));
12149 ins_pipe( fpu_reg_mem );
12150 %}
12152 // Convert a byte to a float; no rounding step needed.
12153 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
12154 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
12155 match(Set dst (ConvI2F src));
12156 format %{ "FILD $src\n\t"
12157 "FSTP $dst" %}
12159 opcode(0xDB, 0x0); /* DB /0 */
12160 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
12161 ins_pipe( fpu_reg_mem );
12162 %}
12164 // In 24-bit mode, force exponent rounding by storing back out
12165 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
12166 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12167 match(Set dst (ConvI2F src));
12168 ins_cost(200);
12169 format %{ "FILD $src\n\t"
12170 "FSTP_S $dst" %}
12171 opcode(0xDB, 0x0); /* DB /0 */
12172 ins_encode( Push_Mem_I(src),
12173 Pop_Mem_F(dst));
12174 ins_pipe( fpu_mem_mem );
12175 %}
12177 // In 24-bit mode, force exponent rounding by storing back out
12178 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
12179 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12180 match(Set dst (ConvI2F (LoadI mem)));
12181 ins_cost(200);
12182 format %{ "FILD $mem\n\t"
12183 "FSTP_S $dst" %}
12184 opcode(0xDB); /* DB /0 */
12185 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12186 Pop_Mem_F(dst));
12187 ins_pipe( fpu_mem_mem );
12188 %}
12190 // This instruction does not round to 24-bits
12191 instruct convI2F_reg(regF dst, stackSlotI src) %{
12192 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12193 match(Set dst (ConvI2F src));
12194 format %{ "FILD $src\n\t"
12195 "FSTP $dst" %}
12196 opcode(0xDB, 0x0); /* DB /0 */
12197 ins_encode( Push_Mem_I(src),
12198 Pop_Reg_F(dst));
12199 ins_pipe( fpu_reg_mem );
12200 %}
12202 // This instruction does not round to 24-bits
12203 instruct convI2F_mem(regF dst, memory mem) %{
12204 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12205 match(Set dst (ConvI2F (LoadI mem)));
12206 format %{ "FILD $mem\n\t"
12207 "FSTP $dst" %}
12208 opcode(0xDB); /* DB /0 */
12209 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12210 Pop_Reg_F(dst));
12211 ins_pipe( fpu_reg_mem );
12212 %}
12214 // Convert an int to a float in xmm; no rounding step needed.
12215 instruct convI2X_reg(regX dst, eRegI src) %{
12216 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
12217 match(Set dst (ConvI2F src));
12218 format %{ "CVTSI2SS $dst, $src" %}
12220 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
12221 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12222 ins_pipe( pipe_slow );
12223 %}
12225 instruct convXI2X_reg(regX dst, eRegI src)
12226 %{
12227 predicate( UseSSE>=2 && UseXmmI2F );
12228 match(Set dst (ConvI2F src));
12230 format %{ "MOVD $dst,$src\n\t"
12231 "CVTDQ2PS $dst,$dst\t# i2f" %}
12232 ins_encode %{
12233 __ movdl($dst$$XMMRegister, $src$$Register);
12234 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
12235 %}
12236 ins_pipe(pipe_slow); // XXX
12237 %}
12239 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
12240 match(Set dst (ConvI2L src));
12241 effect(KILL cr);
12242 ins_cost(375);
12243 format %{ "MOV $dst.lo,$src\n\t"
12244 "MOV $dst.hi,$src\n\t"
12245 "SAR $dst.hi,31" %}
12246 ins_encode(convert_int_long(dst,src));
12247 ins_pipe( ialu_reg_reg_long );
12248 %}
12250 // Zero-extend convert int to long
12251 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
12252 match(Set dst (AndL (ConvI2L src) mask) );
12253 effect( KILL flags );
12254 ins_cost(250);
12255 format %{ "MOV $dst.lo,$src\n\t"
12256 "XOR $dst.hi,$dst.hi" %}
12257 opcode(0x33); // XOR
12258 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12259 ins_pipe( ialu_reg_reg_long );
12260 %}
12262 // Zero-extend long
12263 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
12264 match(Set dst (AndL src mask) );
12265 effect( KILL flags );
12266 ins_cost(250);
12267 format %{ "MOV $dst.lo,$src.lo\n\t"
12268 "XOR $dst.hi,$dst.hi\n\t" %}
12269 opcode(0x33); // XOR
12270 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12271 ins_pipe( ialu_reg_reg_long );
12272 %}
12274 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
12275 predicate (UseSSE<=1);
12276 match(Set dst (ConvL2D src));
12277 effect( KILL cr );
12278 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12279 "PUSH $src.lo\n\t"
12280 "FILD ST,[ESP + #0]\n\t"
12281 "ADD ESP,8\n\t"
12282 "FSTP_D $dst\t# D-round" %}
12283 opcode(0xDF, 0x5); /* DF /5 */
12284 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
12285 ins_pipe( pipe_slow );
12286 %}
12288 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
12289 predicate (UseSSE>=2);
12290 match(Set dst (ConvL2D src));
12291 effect( KILL cr );
12292 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12293 "PUSH $src.lo\n\t"
12294 "FILD_D [ESP]\n\t"
12295 "FSTP_D [ESP]\n\t"
12296 "MOVSD $dst,[ESP]\n\t"
12297 "ADD ESP,8" %}
12298 opcode(0xDF, 0x5); /* DF /5 */
12299 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
12300 ins_pipe( pipe_slow );
12301 %}
12303 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
12304 predicate (UseSSE>=1);
12305 match(Set dst (ConvL2F src));
12306 effect( KILL cr );
12307 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12308 "PUSH $src.lo\n\t"
12309 "FILD_D [ESP]\n\t"
12310 "FSTP_S [ESP]\n\t"
12311 "MOVSS $dst,[ESP]\n\t"
12312 "ADD ESP,8" %}
12313 opcode(0xDF, 0x5); /* DF /5 */
12314 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12315 ins_pipe( pipe_slow );
12316 %}
12318 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12319 match(Set dst (ConvL2F src));
12320 effect( KILL cr );
12321 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12322 "PUSH $src.lo\n\t"
12323 "FILD ST,[ESP + #0]\n\t"
12324 "ADD ESP,8\n\t"
12325 "FSTP_S $dst\t# F-round" %}
12326 opcode(0xDF, 0x5); /* DF /5 */
12327 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12328 ins_pipe( pipe_slow );
12329 %}
12331 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12332 match(Set dst (ConvL2I src));
12333 effect( DEF dst, USE src );
12334 format %{ "MOV $dst,$src.lo" %}
12335 ins_encode(enc_CopyL_Lo(dst,src));
12336 ins_pipe( ialu_reg_reg );
12337 %}
12340 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12341 match(Set dst (MoveF2I src));
12342 effect( DEF dst, USE src );
12343 ins_cost(100);
12344 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12345 opcode(0x8B);
12346 ins_encode( OpcP, RegMem(dst,src));
12347 ins_pipe( ialu_reg_mem );
12348 %}
12350 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12351 predicate(UseSSE==0);
12352 match(Set dst (MoveF2I src));
12353 effect( DEF dst, USE src );
12355 ins_cost(125);
12356 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12357 ins_encode( Pop_Mem_Reg_F(dst, src) );
12358 ins_pipe( fpu_mem_reg );
12359 %}
12361 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12362 predicate(UseSSE>=1);
12363 match(Set dst (MoveF2I src));
12364 effect( DEF dst, USE src );
12366 ins_cost(95);
12367 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12368 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12369 ins_pipe( pipe_slow );
12370 %}
12372 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12373 predicate(UseSSE>=2);
12374 match(Set dst (MoveF2I src));
12375 effect( DEF dst, USE src );
12376 ins_cost(85);
12377 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12378 ins_encode( MovX2I_reg(dst, src));
12379 ins_pipe( pipe_slow );
12380 %}
12382 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12383 match(Set dst (MoveI2F src));
12384 effect( DEF dst, USE src );
12386 ins_cost(100);
12387 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12388 opcode(0x89);
12389 ins_encode( OpcPRegSS( dst, src ) );
12390 ins_pipe( ialu_mem_reg );
12391 %}
12394 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12395 predicate(UseSSE==0);
12396 match(Set dst (MoveI2F src));
12397 effect(DEF dst, USE src);
12399 ins_cost(125);
12400 format %{ "FLD_S $src\n\t"
12401 "FSTP $dst\t# MoveI2F_stack_reg" %}
12402 opcode(0xD9); /* D9 /0, FLD m32real */
12403 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12404 Pop_Reg_F(dst) );
12405 ins_pipe( fpu_reg_mem );
12406 %}
12408 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12409 predicate(UseSSE>=1);
12410 match(Set dst (MoveI2F src));
12411 effect( DEF dst, USE src );
12413 ins_cost(95);
12414 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12415 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12416 ins_pipe( pipe_slow );
12417 %}
12419 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12420 predicate(UseSSE>=2);
12421 match(Set dst (MoveI2F src));
12422 effect( DEF dst, USE src );
12424 ins_cost(85);
12425 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12426 ins_encode( MovI2X_reg(dst, src) );
12427 ins_pipe( pipe_slow );
12428 %}
12430 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12431 match(Set dst (MoveD2L src));
12432 effect(DEF dst, USE src);
12434 ins_cost(250);
12435 format %{ "MOV $dst.lo,$src\n\t"
12436 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12437 opcode(0x8B, 0x8B);
12438 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12439 ins_pipe( ialu_mem_long_reg );
12440 %}
12442 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12443 predicate(UseSSE<=1);
12444 match(Set dst (MoveD2L src));
12445 effect(DEF dst, USE src);
12447 ins_cost(125);
12448 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12449 ins_encode( Pop_Mem_Reg_D(dst, src) );
12450 ins_pipe( fpu_mem_reg );
12451 %}
12453 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12454 predicate(UseSSE>=2);
12455 match(Set dst (MoveD2L src));
12456 effect(DEF dst, USE src);
12457 ins_cost(95);
12459 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12460 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12461 ins_pipe( pipe_slow );
12462 %}
12464 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12465 predicate(UseSSE>=2);
12466 match(Set dst (MoveD2L src));
12467 effect(DEF dst, USE src, TEMP tmp);
12468 ins_cost(85);
12469 format %{ "MOVD $dst.lo,$src\n\t"
12470 "PSHUFLW $tmp,$src,0x4E\n\t"
12471 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12472 ins_encode( MovXD2L_reg(dst, src, tmp) );
12473 ins_pipe( pipe_slow );
12474 %}
12476 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12477 match(Set dst (MoveL2D src));
12478 effect(DEF dst, USE src);
12480 ins_cost(200);
12481 format %{ "MOV $dst,$src.lo\n\t"
12482 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12483 opcode(0x89, 0x89);
12484 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12485 ins_pipe( ialu_mem_long_reg );
12486 %}
12489 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12490 predicate(UseSSE<=1);
12491 match(Set dst (MoveL2D src));
12492 effect(DEF dst, USE src);
12493 ins_cost(125);
12495 format %{ "FLD_D $src\n\t"
12496 "FSTP $dst\t# MoveL2D_stack_reg" %}
12497 opcode(0xDD); /* DD /0, FLD m64real */
12498 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12499 Pop_Reg_D(dst) );
12500 ins_pipe( fpu_reg_mem );
12501 %}
12504 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12505 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12506 match(Set dst (MoveL2D src));
12507 effect(DEF dst, USE src);
12509 ins_cost(95);
12510 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12511 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12512 ins_pipe( pipe_slow );
12513 %}
12515 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12516 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12517 match(Set dst (MoveL2D src));
12518 effect(DEF dst, USE src);
12520 ins_cost(95);
12521 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12522 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12523 ins_pipe( pipe_slow );
12524 %}
12526 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12527 predicate(UseSSE>=2);
12528 match(Set dst (MoveL2D src));
12529 effect(TEMP dst, USE src, TEMP tmp);
12530 ins_cost(85);
12531 format %{ "MOVD $dst,$src.lo\n\t"
12532 "MOVD $tmp,$src.hi\n\t"
12533 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12534 ins_encode( MovL2XD_reg(dst, src, tmp) );
12535 ins_pipe( pipe_slow );
12536 %}
12538 // Replicate scalar to packed byte (1 byte) values in xmm
12539 instruct Repl8B_reg(regXD dst, regXD src) %{
12540 predicate(UseSSE>=2);
12541 match(Set dst (Replicate8B src));
12542 format %{ "MOVDQA $dst,$src\n\t"
12543 "PUNPCKLBW $dst,$dst\n\t"
12544 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12545 ins_encode( pshufd_8x8(dst, src));
12546 ins_pipe( pipe_slow );
12547 %}
12549 // Replicate scalar to packed byte (1 byte) values in xmm
12550 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12551 predicate(UseSSE>=2);
12552 match(Set dst (Replicate8B src));
12553 format %{ "MOVD $dst,$src\n\t"
12554 "PUNPCKLBW $dst,$dst\n\t"
12555 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12556 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12557 ins_pipe( pipe_slow );
12558 %}
12560 // Replicate scalar zero to packed byte (1 byte) values in xmm
12561 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12562 predicate(UseSSE>=2);
12563 match(Set dst (Replicate8B zero));
12564 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12565 ins_encode( pxor(dst, dst));
12566 ins_pipe( fpu_reg_reg );
12567 %}
12569 // Replicate scalar to packed shore (2 byte) values in xmm
12570 instruct Repl4S_reg(regXD dst, regXD src) %{
12571 predicate(UseSSE>=2);
12572 match(Set dst (Replicate4S src));
12573 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12574 ins_encode( pshufd_4x16(dst, src));
12575 ins_pipe( fpu_reg_reg );
12576 %}
12578 // Replicate scalar to packed shore (2 byte) values in xmm
12579 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12580 predicate(UseSSE>=2);
12581 match(Set dst (Replicate4S src));
12582 format %{ "MOVD $dst,$src\n\t"
12583 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12584 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12585 ins_pipe( fpu_reg_reg );
12586 %}
12588 // Replicate scalar zero to packed short (2 byte) values in xmm
12589 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12590 predicate(UseSSE>=2);
12591 match(Set dst (Replicate4S zero));
12592 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12593 ins_encode( pxor(dst, dst));
12594 ins_pipe( fpu_reg_reg );
12595 %}
12597 // Replicate scalar to packed char (2 byte) values in xmm
12598 instruct Repl4C_reg(regXD dst, regXD src) %{
12599 predicate(UseSSE>=2);
12600 match(Set dst (Replicate4C src));
12601 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12602 ins_encode( pshufd_4x16(dst, src));
12603 ins_pipe( fpu_reg_reg );
12604 %}
12606 // Replicate scalar to packed char (2 byte) values in xmm
12607 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12608 predicate(UseSSE>=2);
12609 match(Set dst (Replicate4C src));
12610 format %{ "MOVD $dst,$src\n\t"
12611 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12612 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12613 ins_pipe( fpu_reg_reg );
12614 %}
12616 // Replicate scalar zero to packed char (2 byte) values in xmm
12617 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12618 predicate(UseSSE>=2);
12619 match(Set dst (Replicate4C zero));
12620 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12621 ins_encode( pxor(dst, dst));
12622 ins_pipe( fpu_reg_reg );
12623 %}
12625 // Replicate scalar to packed integer (4 byte) values in xmm
12626 instruct Repl2I_reg(regXD dst, regXD src) %{
12627 predicate(UseSSE>=2);
12628 match(Set dst (Replicate2I src));
12629 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12630 ins_encode( pshufd(dst, src, 0x00));
12631 ins_pipe( fpu_reg_reg );
12632 %}
12634 // Replicate scalar to packed integer (4 byte) values in xmm
12635 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12636 predicate(UseSSE>=2);
12637 match(Set dst (Replicate2I src));
12638 format %{ "MOVD $dst,$src\n\t"
12639 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12640 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12641 ins_pipe( fpu_reg_reg );
12642 %}
12644 // Replicate scalar zero to packed integer (2 byte) values in xmm
12645 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12646 predicate(UseSSE>=2);
12647 match(Set dst (Replicate2I zero));
12648 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12649 ins_encode( pxor(dst, dst));
12650 ins_pipe( fpu_reg_reg );
12651 %}
12653 // Replicate scalar to packed single precision floating point values in xmm
12654 instruct Repl2F_reg(regXD dst, regXD src) %{
12655 predicate(UseSSE>=2);
12656 match(Set dst (Replicate2F src));
12657 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12658 ins_encode( pshufd(dst, src, 0xe0));
12659 ins_pipe( fpu_reg_reg );
12660 %}
12662 // Replicate scalar to packed single precision floating point values in xmm
12663 instruct Repl2F_regX(regXD dst, regX src) %{
12664 predicate(UseSSE>=2);
12665 match(Set dst (Replicate2F src));
12666 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12667 ins_encode( pshufd(dst, src, 0xe0));
12668 ins_pipe( fpu_reg_reg );
12669 %}
12671 // Replicate scalar to packed single precision floating point values in xmm
12672 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12673 predicate(UseSSE>=2);
12674 match(Set dst (Replicate2F zero));
12675 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12676 ins_encode( pxor(dst, dst));
12677 ins_pipe( fpu_reg_reg );
12678 %}
12680 // =======================================================================
12681 // fast clearing of an array
12682 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12683 match(Set dummy (ClearArray cnt base));
12684 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12685 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12686 "XOR EAX,EAX\n\t"
12687 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12688 opcode(0,0x4);
12689 ins_encode( Opcode(0xD1), RegOpc(ECX),
12690 OpcRegReg(0x33,EAX,EAX),
12691 Opcode(0xF3), Opcode(0xAB) );
12692 ins_pipe( pipe_slow );
12693 %}
12695 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
12696 eAXRegI result, regXD tmp1, eFlagsReg cr) %{
12697 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12698 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12700 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12701 ins_encode %{
12702 __ string_compare($str1$$Register, $str2$$Register,
12703 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12704 $tmp1$$XMMRegister);
12705 %}
12706 ins_pipe( pipe_slow );
12707 %}
12709 // fast string equals
12710 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12711 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12712 match(Set result (StrEquals (Binary str1 str2) cnt));
12713 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12715 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12716 ins_encode %{
12717 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12718 $cnt$$Register, $result$$Register, $tmp3$$Register,
12719 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12720 %}
12721 ins_pipe( pipe_slow );
12722 %}
12724 // fast search of substring with known size.
12725 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
12726 eBXRegI result, regXD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
12727 predicate(UseSSE42Intrinsics);
12728 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12729 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12731 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
12732 ins_encode %{
12733 int icnt2 = (int)$int_cnt2$$constant;
12734 if (icnt2 >= 8) {
12735 // IndexOf for constant substrings with size >= 8 elements
12736 // which don't need to be loaded through stack.
12737 __ string_indexofC8($str1$$Register, $str2$$Register,
12738 $cnt1$$Register, $cnt2$$Register,
12739 icnt2, $result$$Register,
12740 $vec$$XMMRegister, $tmp$$Register);
12741 } else {
12742 // Small strings are loaded through stack if they cross page boundary.
12743 __ string_indexof($str1$$Register, $str2$$Register,
12744 $cnt1$$Register, $cnt2$$Register,
12745 icnt2, $result$$Register,
12746 $vec$$XMMRegister, $tmp$$Register);
12747 }
12748 %}
12749 ins_pipe( pipe_slow );
12750 %}
12752 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12753 eBXRegI result, regXD vec, eCXRegI tmp, eFlagsReg cr) %{
12754 predicate(UseSSE42Intrinsics);
12755 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12756 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12758 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12759 ins_encode %{
12760 __ string_indexof($str1$$Register, $str2$$Register,
12761 $cnt1$$Register, $cnt2$$Register,
12762 (-1), $result$$Register,
12763 $vec$$XMMRegister, $tmp$$Register);
12764 %}
12765 ins_pipe( pipe_slow );
12766 %}
12768 // fast array equals
12769 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12770 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12771 %{
12772 match(Set result (AryEq ary1 ary2));
12773 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12774 //ins_cost(300);
12776 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12777 ins_encode %{
12778 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12779 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12780 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12781 %}
12782 ins_pipe( pipe_slow );
12783 %}
12785 //----------Control Flow Instructions------------------------------------------
12786 // Signed compare Instructions
12787 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12788 match(Set cr (CmpI op1 op2));
12789 effect( DEF cr, USE op1, USE op2 );
12790 format %{ "CMP $op1,$op2" %}
12791 opcode(0x3B); /* Opcode 3B /r */
12792 ins_encode( OpcP, RegReg( op1, op2) );
12793 ins_pipe( ialu_cr_reg_reg );
12794 %}
12796 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12797 match(Set cr (CmpI op1 op2));
12798 effect( DEF cr, USE op1 );
12799 format %{ "CMP $op1,$op2" %}
12800 opcode(0x81,0x07); /* Opcode 81 /7 */
12801 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12802 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12803 ins_pipe( ialu_cr_reg_imm );
12804 %}
12806 // Cisc-spilled version of cmpI_eReg
12807 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12808 match(Set cr (CmpI op1 (LoadI op2)));
12810 format %{ "CMP $op1,$op2" %}
12811 ins_cost(500);
12812 opcode(0x3B); /* Opcode 3B /r */
12813 ins_encode( OpcP, RegMem( op1, op2) );
12814 ins_pipe( ialu_cr_reg_mem );
12815 %}
12817 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12818 match(Set cr (CmpI src zero));
12819 effect( DEF cr, USE src );
12821 format %{ "TEST $src,$src" %}
12822 opcode(0x85);
12823 ins_encode( OpcP, RegReg( src, src ) );
12824 ins_pipe( ialu_cr_reg_imm );
12825 %}
12827 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12828 match(Set cr (CmpI (AndI src con) zero));
12830 format %{ "TEST $src,$con" %}
12831 opcode(0xF7,0x00);
12832 ins_encode( OpcP, RegOpc(src), Con32(con) );
12833 ins_pipe( ialu_cr_reg_imm );
12834 %}
12836 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12837 match(Set cr (CmpI (AndI src mem) zero));
12839 format %{ "TEST $src,$mem" %}
12840 opcode(0x85);
12841 ins_encode( OpcP, RegMem( src, mem ) );
12842 ins_pipe( ialu_cr_reg_mem );
12843 %}
12845 // Unsigned compare Instructions; really, same as signed except they
12846 // produce an eFlagsRegU instead of eFlagsReg.
12847 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12848 match(Set cr (CmpU op1 op2));
12850 format %{ "CMPu $op1,$op2" %}
12851 opcode(0x3B); /* Opcode 3B /r */
12852 ins_encode( OpcP, RegReg( op1, op2) );
12853 ins_pipe( ialu_cr_reg_reg );
12854 %}
12856 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12857 match(Set cr (CmpU op1 op2));
12859 format %{ "CMPu $op1,$op2" %}
12860 opcode(0x81,0x07); /* Opcode 81 /7 */
12861 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12862 ins_pipe( ialu_cr_reg_imm );
12863 %}
12865 // // Cisc-spilled version of cmpU_eReg
12866 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12867 match(Set cr (CmpU op1 (LoadI op2)));
12869 format %{ "CMPu $op1,$op2" %}
12870 ins_cost(500);
12871 opcode(0x3B); /* Opcode 3B /r */
12872 ins_encode( OpcP, RegMem( op1, op2) );
12873 ins_pipe( ialu_cr_reg_mem );
12874 %}
12876 // // Cisc-spilled version of cmpU_eReg
12877 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12878 // match(Set cr (CmpU (LoadI op1) op2));
12879 //
12880 // format %{ "CMPu $op1,$op2" %}
12881 // ins_cost(500);
12882 // opcode(0x39); /* Opcode 39 /r */
12883 // ins_encode( OpcP, RegMem( op1, op2) );
12884 //%}
12886 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12887 match(Set cr (CmpU src zero));
12889 format %{ "TESTu $src,$src" %}
12890 opcode(0x85);
12891 ins_encode( OpcP, RegReg( src, src ) );
12892 ins_pipe( ialu_cr_reg_imm );
12893 %}
12895 // Unsigned pointer compare Instructions
12896 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12897 match(Set cr (CmpP op1 op2));
12899 format %{ "CMPu $op1,$op2" %}
12900 opcode(0x3B); /* Opcode 3B /r */
12901 ins_encode( OpcP, RegReg( op1, op2) );
12902 ins_pipe( ialu_cr_reg_reg );
12903 %}
12905 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12906 match(Set cr (CmpP op1 op2));
12908 format %{ "CMPu $op1,$op2" %}
12909 opcode(0x81,0x07); /* Opcode 81 /7 */
12910 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12911 ins_pipe( ialu_cr_reg_imm );
12912 %}
12914 // // Cisc-spilled version of cmpP_eReg
12915 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12916 match(Set cr (CmpP op1 (LoadP op2)));
12918 format %{ "CMPu $op1,$op2" %}
12919 ins_cost(500);
12920 opcode(0x3B); /* Opcode 3B /r */
12921 ins_encode( OpcP, RegMem( op1, op2) );
12922 ins_pipe( ialu_cr_reg_mem );
12923 %}
12925 // // Cisc-spilled version of cmpP_eReg
12926 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12927 // match(Set cr (CmpP (LoadP op1) op2));
12928 //
12929 // format %{ "CMPu $op1,$op2" %}
12930 // ins_cost(500);
12931 // opcode(0x39); /* Opcode 39 /r */
12932 // ins_encode( OpcP, RegMem( op1, op2) );
12933 //%}
12935 // Compare raw pointer (used in out-of-heap check).
12936 // Only works because non-oop pointers must be raw pointers
12937 // and raw pointers have no anti-dependencies.
12938 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12939 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12940 match(Set cr (CmpP op1 (LoadP op2)));
12942 format %{ "CMPu $op1,$op2" %}
12943 opcode(0x3B); /* Opcode 3B /r */
12944 ins_encode( OpcP, RegMem( op1, op2) );
12945 ins_pipe( ialu_cr_reg_mem );
12946 %}
12948 //
12949 // This will generate a signed flags result. This should be ok
12950 // since any compare to a zero should be eq/neq.
12951 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12952 match(Set cr (CmpP src zero));
12954 format %{ "TEST $src,$src" %}
12955 opcode(0x85);
12956 ins_encode( OpcP, RegReg( src, src ) );
12957 ins_pipe( ialu_cr_reg_imm );
12958 %}
12960 // Cisc-spilled version of testP_reg
12961 // This will generate a signed flags result. This should be ok
12962 // since any compare to a zero should be eq/neq.
12963 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12964 match(Set cr (CmpP (LoadP op) zero));
12966 format %{ "TEST $op,0xFFFFFFFF" %}
12967 ins_cost(500);
12968 opcode(0xF7); /* Opcode F7 /0 */
12969 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12970 ins_pipe( ialu_cr_reg_imm );
12971 %}
12973 // Yanked all unsigned pointer compare operations.
12974 // Pointer compares are done with CmpP which is already unsigned.
12976 //----------Max and Min--------------------------------------------------------
12977 // Min Instructions
12978 ////
12979 // *** Min and Max using the conditional move are slower than the
12980 // *** branch version on a Pentium III.
12981 // // Conditional move for min
12982 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12983 // effect( USE_DEF op2, USE op1, USE cr );
12984 // format %{ "CMOVlt $op2,$op1\t! min" %}
12985 // opcode(0x4C,0x0F);
12986 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12987 // ins_pipe( pipe_cmov_reg );
12988 //%}
12989 //
12990 //// Min Register with Register (P6 version)
12991 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12992 // predicate(VM_Version::supports_cmov() );
12993 // match(Set op2 (MinI op1 op2));
12994 // ins_cost(200);
12995 // expand %{
12996 // eFlagsReg cr;
12997 // compI_eReg(cr,op1,op2);
12998 // cmovI_reg_lt(op2,op1,cr);
12999 // %}
13000 //%}
13002 // Min Register with Register (generic version)
13003 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
13004 match(Set dst (MinI dst src));
13005 effect(KILL flags);
13006 ins_cost(300);
13008 format %{ "MIN $dst,$src" %}
13009 opcode(0xCC);
13010 ins_encode( min_enc(dst,src) );
13011 ins_pipe( pipe_slow );
13012 %}
13014 // Max Register with Register
13015 // *** Min and Max using the conditional move are slower than the
13016 // *** branch version on a Pentium III.
13017 // // Conditional move for max
13018 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13019 // effect( USE_DEF op2, USE op1, USE cr );
13020 // format %{ "CMOVgt $op2,$op1\t! max" %}
13021 // opcode(0x4F,0x0F);
13022 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13023 // ins_pipe( pipe_cmov_reg );
13024 //%}
13025 //
13026 // // Max Register with Register (P6 version)
13027 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
13028 // predicate(VM_Version::supports_cmov() );
13029 // match(Set op2 (MaxI op1 op2));
13030 // ins_cost(200);
13031 // expand %{
13032 // eFlagsReg cr;
13033 // compI_eReg(cr,op1,op2);
13034 // cmovI_reg_gt(op2,op1,cr);
13035 // %}
13036 //%}
13038 // Max Register with Register (generic version)
13039 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
13040 match(Set dst (MaxI dst src));
13041 effect(KILL flags);
13042 ins_cost(300);
13044 format %{ "MAX $dst,$src" %}
13045 opcode(0xCC);
13046 ins_encode( max_enc(dst,src) );
13047 ins_pipe( pipe_slow );
13048 %}
13050 // ============================================================================
13051 // Counted Loop limit node which represents exact final iterator value.
13052 // Note: the resulting value should fit into integer range since
13053 // counted loops have limit check on overflow.
13054 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
13055 match(Set limit (LoopLimit (Binary init limit) stride));
13056 effect(TEMP limit_hi, TEMP tmp, KILL flags);
13057 ins_cost(300);
13059 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
13060 ins_encode %{
13061 int strd = (int)$stride$$constant;
13062 assert(strd != 1 && strd != -1, "sanity");
13063 int m1 = (strd > 0) ? 1 : -1;
13064 // Convert limit to long (EAX:EDX)
13065 __ cdql();
13066 // Convert init to long (init:tmp)
13067 __ movl($tmp$$Register, $init$$Register);
13068 __ sarl($tmp$$Register, 31);
13069 // $limit - $init
13070 __ subl($limit$$Register, $init$$Register);
13071 __ sbbl($limit_hi$$Register, $tmp$$Register);
13072 // + ($stride - 1)
13073 if (strd > 0) {
13074 __ addl($limit$$Register, (strd - 1));
13075 __ adcl($limit_hi$$Register, 0);
13076 __ movl($tmp$$Register, strd);
13077 } else {
13078 __ addl($limit$$Register, (strd + 1));
13079 __ adcl($limit_hi$$Register, -1);
13080 __ lneg($limit_hi$$Register, $limit$$Register);
13081 __ movl($tmp$$Register, -strd);
13082 }
13083 // signed devision: (EAX:EDX) / pos_stride
13084 __ idivl($tmp$$Register);
13085 if (strd < 0) {
13086 // restore sign
13087 __ negl($tmp$$Register);
13088 }
13089 // (EAX) * stride
13090 __ mull($tmp$$Register);
13091 // + init (ignore upper bits)
13092 __ addl($limit$$Register, $init$$Register);
13093 %}
13094 ins_pipe( pipe_slow );
13095 %}
13097 // ============================================================================
13098 // Branch Instructions
13099 // Jump Table
13100 instruct jumpXtnd(eRegI switch_val) %{
13101 match(Jump switch_val);
13102 ins_cost(350);
13103 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
13104 ins_encode %{
13105 // Jump to Address(table_base + switch_reg)
13106 Address index(noreg, $switch_val$$Register, Address::times_1);
13107 __ jump(ArrayAddress($constantaddress, index));
13108 %}
13109 ins_pipe(pipe_jmp);
13110 %}
13112 // Jump Direct - Label defines a relative address from JMP+1
13113 instruct jmpDir(label labl) %{
13114 match(Goto);
13115 effect(USE labl);
13117 ins_cost(300);
13118 format %{ "JMP $labl" %}
13119 size(5);
13120 ins_encode %{
13121 Label* L = $labl$$label;
13122 __ jmp(*L, false); // Always long jump
13123 %}
13124 ins_pipe( pipe_jmp );
13125 %}
13127 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13128 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
13129 match(If cop cr);
13130 effect(USE labl);
13132 ins_cost(300);
13133 format %{ "J$cop $labl" %}
13134 size(6);
13135 ins_encode %{
13136 Label* L = $labl$$label;
13137 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13138 %}
13139 ins_pipe( pipe_jcc );
13140 %}
13142 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13143 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
13144 match(CountedLoopEnd cop cr);
13145 effect(USE labl);
13147 ins_cost(300);
13148 format %{ "J$cop $labl\t# Loop end" %}
13149 size(6);
13150 ins_encode %{
13151 Label* L = $labl$$label;
13152 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13153 %}
13154 ins_pipe( pipe_jcc );
13155 %}
13157 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13158 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13159 match(CountedLoopEnd cop cmp);
13160 effect(USE labl);
13162 ins_cost(300);
13163 format %{ "J$cop,u $labl\t# Loop end" %}
13164 size(6);
13165 ins_encode %{
13166 Label* L = $labl$$label;
13167 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13168 %}
13169 ins_pipe( pipe_jcc );
13170 %}
13172 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13173 match(CountedLoopEnd cop cmp);
13174 effect(USE labl);
13176 ins_cost(200);
13177 format %{ "J$cop,u $labl\t# Loop end" %}
13178 size(6);
13179 ins_encode %{
13180 Label* L = $labl$$label;
13181 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13182 %}
13183 ins_pipe( pipe_jcc );
13184 %}
13186 // Jump Direct Conditional - using unsigned comparison
13187 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13188 match(If cop cmp);
13189 effect(USE labl);
13191 ins_cost(300);
13192 format %{ "J$cop,u $labl" %}
13193 size(6);
13194 ins_encode %{
13195 Label* L = $labl$$label;
13196 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13197 %}
13198 ins_pipe(pipe_jcc);
13199 %}
13201 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13202 match(If cop cmp);
13203 effect(USE labl);
13205 ins_cost(200);
13206 format %{ "J$cop,u $labl" %}
13207 size(6);
13208 ins_encode %{
13209 Label* L = $labl$$label;
13210 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13211 %}
13212 ins_pipe(pipe_jcc);
13213 %}
13215 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13216 match(If cop cmp);
13217 effect(USE labl);
13219 ins_cost(200);
13220 format %{ $$template
13221 if ($cop$$cmpcode == Assembler::notEqual) {
13222 $$emit$$"JP,u $labl\n\t"
13223 $$emit$$"J$cop,u $labl"
13224 } else {
13225 $$emit$$"JP,u done\n\t"
13226 $$emit$$"J$cop,u $labl\n\t"
13227 $$emit$$"done:"
13228 }
13229 %}
13230 ins_encode %{
13231 Label* l = $labl$$label;
13232 if ($cop$$cmpcode == Assembler::notEqual) {
13233 __ jcc(Assembler::parity, *l, false);
13234 __ jcc(Assembler::notEqual, *l, false);
13235 } else if ($cop$$cmpcode == Assembler::equal) {
13236 Label done;
13237 __ jccb(Assembler::parity, done);
13238 __ jcc(Assembler::equal, *l, false);
13239 __ bind(done);
13240 } else {
13241 ShouldNotReachHere();
13242 }
13243 %}
13244 ins_pipe(pipe_jcc);
13245 %}
13247 // ============================================================================
13248 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
13249 // array for an instance of the superklass. Set a hidden internal cache on a
13250 // hit (cache is checked with exposed code in gen_subtype_check()). Return
13251 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
13252 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
13253 match(Set result (PartialSubtypeCheck sub super));
13254 effect( KILL rcx, KILL cr );
13256 ins_cost(1100); // slightly larger than the next version
13257 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13258 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13259 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13260 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13261 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
13262 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
13263 "XOR $result,$result\t\t Hit: EDI zero\n\t"
13264 "miss:\t" %}
13266 opcode(0x1); // Force a XOR of EDI
13267 ins_encode( enc_PartialSubtypeCheck() );
13268 ins_pipe( pipe_slow );
13269 %}
13271 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
13272 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
13273 effect( KILL rcx, KILL result );
13275 ins_cost(1000);
13276 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13277 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13278 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13279 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13280 "JNE,s miss\t\t# Missed: flags NZ\n\t"
13281 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
13282 "miss:\t" %}
13284 opcode(0x0); // No need to XOR EDI
13285 ins_encode( enc_PartialSubtypeCheck() );
13286 ins_pipe( pipe_slow );
13287 %}
13289 // ============================================================================
13290 // Branch Instructions -- short offset versions
13291 //
13292 // These instructions are used to replace jumps of a long offset (the default
13293 // match) with jumps of a shorter offset. These instructions are all tagged
13294 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13295 // match rules in general matching. Instead, the ADLC generates a conversion
13296 // method in the MachNode which can be used to do in-place replacement of the
13297 // long variant with the shorter variant. The compiler will determine if a
13298 // branch can be taken by the is_short_branch_offset() predicate in the machine
13299 // specific code section of the file.
13301 // Jump Direct - Label defines a relative address from JMP+1
13302 instruct jmpDir_short(label labl) %{
13303 match(Goto);
13304 effect(USE labl);
13306 ins_cost(300);
13307 format %{ "JMP,s $labl" %}
13308 size(2);
13309 ins_encode %{
13310 Label* L = $labl$$label;
13311 __ jmpb(*L);
13312 %}
13313 ins_pipe( pipe_jmp );
13314 ins_short_branch(1);
13315 %}
13317 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13318 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
13319 match(If cop cr);
13320 effect(USE labl);
13322 ins_cost(300);
13323 format %{ "J$cop,s $labl" %}
13324 size(2);
13325 ins_encode %{
13326 Label* L = $labl$$label;
13327 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13328 %}
13329 ins_pipe( pipe_jcc );
13330 ins_short_branch(1);
13331 %}
13333 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13334 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
13335 match(CountedLoopEnd cop cr);
13336 effect(USE labl);
13338 ins_cost(300);
13339 format %{ "J$cop,s $labl\t# Loop end" %}
13340 size(2);
13341 ins_encode %{
13342 Label* L = $labl$$label;
13343 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13344 %}
13345 ins_pipe( pipe_jcc );
13346 ins_short_branch(1);
13347 %}
13349 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13350 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13351 match(CountedLoopEnd cop cmp);
13352 effect(USE labl);
13354 ins_cost(300);
13355 format %{ "J$cop,us $labl\t# Loop end" %}
13356 size(2);
13357 ins_encode %{
13358 Label* L = $labl$$label;
13359 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13360 %}
13361 ins_pipe( pipe_jcc );
13362 ins_short_branch(1);
13363 %}
13365 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13366 match(CountedLoopEnd cop cmp);
13367 effect(USE labl);
13369 ins_cost(300);
13370 format %{ "J$cop,us $labl\t# Loop end" %}
13371 size(2);
13372 ins_encode %{
13373 Label* L = $labl$$label;
13374 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13375 %}
13376 ins_pipe( pipe_jcc );
13377 ins_short_branch(1);
13378 %}
13380 // Jump Direct Conditional - using unsigned comparison
13381 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13382 match(If cop cmp);
13383 effect(USE labl);
13385 ins_cost(300);
13386 format %{ "J$cop,us $labl" %}
13387 size(2);
13388 ins_encode %{
13389 Label* L = $labl$$label;
13390 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13391 %}
13392 ins_pipe( pipe_jcc );
13393 ins_short_branch(1);
13394 %}
13396 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13397 match(If cop cmp);
13398 effect(USE labl);
13400 ins_cost(300);
13401 format %{ "J$cop,us $labl" %}
13402 size(2);
13403 ins_encode %{
13404 Label* L = $labl$$label;
13405 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13406 %}
13407 ins_pipe( pipe_jcc );
13408 ins_short_branch(1);
13409 %}
13411 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13412 match(If cop cmp);
13413 effect(USE labl);
13415 ins_cost(300);
13416 format %{ $$template
13417 if ($cop$$cmpcode == Assembler::notEqual) {
13418 $$emit$$"JP,u,s $labl\n\t"
13419 $$emit$$"J$cop,u,s $labl"
13420 } else {
13421 $$emit$$"JP,u,s done\n\t"
13422 $$emit$$"J$cop,u,s $labl\n\t"
13423 $$emit$$"done:"
13424 }
13425 %}
13426 size(4);
13427 ins_encode %{
13428 Label* l = $labl$$label;
13429 if ($cop$$cmpcode == Assembler::notEqual) {
13430 __ jccb(Assembler::parity, *l);
13431 __ jccb(Assembler::notEqual, *l);
13432 } else if ($cop$$cmpcode == Assembler::equal) {
13433 Label done;
13434 __ jccb(Assembler::parity, done);
13435 __ jccb(Assembler::equal, *l);
13436 __ bind(done);
13437 } else {
13438 ShouldNotReachHere();
13439 }
13440 %}
13441 ins_pipe(pipe_jcc);
13442 ins_short_branch(1);
13443 %}
13445 // ============================================================================
13446 // Long Compare
13447 //
13448 // Currently we hold longs in 2 registers. Comparing such values efficiently
13449 // is tricky. The flavor of compare used depends on whether we are testing
13450 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13451 // The GE test is the negated LT test. The LE test can be had by commuting
13452 // the operands (yielding a GE test) and then negating; negate again for the
13453 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13454 // NE test is negated from that.
13456 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13457 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13458 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13459 // are collapsed internally in the ADLC's dfa-gen code. The match for
13460 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13461 // foo match ends up with the wrong leaf. One fix is to not match both
13462 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13463 // both forms beat the trinary form of long-compare and both are very useful
13464 // on Intel which has so few registers.
13466 // Manifest a CmpL result in an integer register. Very painful.
13467 // This is the test to avoid.
13468 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13469 match(Set dst (CmpL3 src1 src2));
13470 effect( KILL flags );
13471 ins_cost(1000);
13472 format %{ "XOR $dst,$dst\n\t"
13473 "CMP $src1.hi,$src2.hi\n\t"
13474 "JLT,s m_one\n\t"
13475 "JGT,s p_one\n\t"
13476 "CMP $src1.lo,$src2.lo\n\t"
13477 "JB,s m_one\n\t"
13478 "JEQ,s done\n"
13479 "p_one:\tINC $dst\n\t"
13480 "JMP,s done\n"
13481 "m_one:\tDEC $dst\n"
13482 "done:" %}
13483 ins_encode %{
13484 Label p_one, m_one, done;
13485 __ xorptr($dst$$Register, $dst$$Register);
13486 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13487 __ jccb(Assembler::less, m_one);
13488 __ jccb(Assembler::greater, p_one);
13489 __ cmpl($src1$$Register, $src2$$Register);
13490 __ jccb(Assembler::below, m_one);
13491 __ jccb(Assembler::equal, done);
13492 __ bind(p_one);
13493 __ incrementl($dst$$Register);
13494 __ jmpb(done);
13495 __ bind(m_one);
13496 __ decrementl($dst$$Register);
13497 __ bind(done);
13498 %}
13499 ins_pipe( pipe_slow );
13500 %}
13502 //======
13503 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13504 // compares. Can be used for LE or GT compares by reversing arguments.
13505 // NOT GOOD FOR EQ/NE tests.
13506 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13507 match( Set flags (CmpL src zero ));
13508 ins_cost(100);
13509 format %{ "TEST $src.hi,$src.hi" %}
13510 opcode(0x85);
13511 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13512 ins_pipe( ialu_cr_reg_reg );
13513 %}
13515 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13516 // compares. Can be used for LE or GT compares by reversing arguments.
13517 // NOT GOOD FOR EQ/NE tests.
13518 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13519 match( Set flags (CmpL src1 src2 ));
13520 effect( TEMP tmp );
13521 ins_cost(300);
13522 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13523 "MOV $tmp,$src1.hi\n\t"
13524 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13525 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13526 ins_pipe( ialu_cr_reg_reg );
13527 %}
13529 // Long compares reg < zero/req OR reg >= zero/req.
13530 // Just a wrapper for a normal branch, plus the predicate test.
13531 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13532 match(If cmp flags);
13533 effect(USE labl);
13534 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13535 expand %{
13536 jmpCon(cmp,flags,labl); // JLT or JGE...
13537 %}
13538 %}
13540 // Compare 2 longs and CMOVE longs.
13541 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13542 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13543 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13544 ins_cost(400);
13545 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13546 "CMOV$cmp $dst.hi,$src.hi" %}
13547 opcode(0x0F,0x40);
13548 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13549 ins_pipe( pipe_cmov_reg_long );
13550 %}
13552 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13553 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13554 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13555 ins_cost(500);
13556 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13557 "CMOV$cmp $dst.hi,$src.hi" %}
13558 opcode(0x0F,0x40);
13559 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13560 ins_pipe( pipe_cmov_reg_long );
13561 %}
13563 // Compare 2 longs and CMOVE ints.
13564 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13565 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13566 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13567 ins_cost(200);
13568 format %{ "CMOV$cmp $dst,$src" %}
13569 opcode(0x0F,0x40);
13570 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13571 ins_pipe( pipe_cmov_reg );
13572 %}
13574 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13575 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13576 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13577 ins_cost(250);
13578 format %{ "CMOV$cmp $dst,$src" %}
13579 opcode(0x0F,0x40);
13580 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13581 ins_pipe( pipe_cmov_mem );
13582 %}
13584 // Compare 2 longs and CMOVE ints.
13585 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13586 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13587 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13588 ins_cost(200);
13589 format %{ "CMOV$cmp $dst,$src" %}
13590 opcode(0x0F,0x40);
13591 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13592 ins_pipe( pipe_cmov_reg );
13593 %}
13595 // Compare 2 longs and CMOVE doubles
13596 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13597 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13598 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13599 ins_cost(200);
13600 expand %{
13601 fcmovD_regS(cmp,flags,dst,src);
13602 %}
13603 %}
13605 // Compare 2 longs and CMOVE doubles
13606 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13607 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13608 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13609 ins_cost(200);
13610 expand %{
13611 fcmovXD_regS(cmp,flags,dst,src);
13612 %}
13613 %}
13615 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13616 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13617 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13618 ins_cost(200);
13619 expand %{
13620 fcmovF_regS(cmp,flags,dst,src);
13621 %}
13622 %}
13624 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13625 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13626 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13627 ins_cost(200);
13628 expand %{
13629 fcmovX_regS(cmp,flags,dst,src);
13630 %}
13631 %}
13633 //======
13634 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13635 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13636 match( Set flags (CmpL src zero ));
13637 effect(TEMP tmp);
13638 ins_cost(200);
13639 format %{ "MOV $tmp,$src.lo\n\t"
13640 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13641 ins_encode( long_cmp_flags0( src, tmp ) );
13642 ins_pipe( ialu_reg_reg_long );
13643 %}
13645 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13646 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13647 match( Set flags (CmpL src1 src2 ));
13648 ins_cost(200+300);
13649 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13650 "JNE,s skip\n\t"
13651 "CMP $src1.hi,$src2.hi\n\t"
13652 "skip:\t" %}
13653 ins_encode( long_cmp_flags1( src1, src2 ) );
13654 ins_pipe( ialu_cr_reg_reg );
13655 %}
13657 // Long compare reg == zero/reg OR reg != zero/reg
13658 // Just a wrapper for a normal branch, plus the predicate test.
13659 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13660 match(If cmp flags);
13661 effect(USE labl);
13662 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13663 expand %{
13664 jmpCon(cmp,flags,labl); // JEQ or JNE...
13665 %}
13666 %}
13668 // Compare 2 longs and CMOVE longs.
13669 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13670 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13671 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13672 ins_cost(400);
13673 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13674 "CMOV$cmp $dst.hi,$src.hi" %}
13675 opcode(0x0F,0x40);
13676 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13677 ins_pipe( pipe_cmov_reg_long );
13678 %}
13680 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13681 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13682 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13683 ins_cost(500);
13684 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13685 "CMOV$cmp $dst.hi,$src.hi" %}
13686 opcode(0x0F,0x40);
13687 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13688 ins_pipe( pipe_cmov_reg_long );
13689 %}
13691 // Compare 2 longs and CMOVE ints.
13692 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13693 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13694 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13695 ins_cost(200);
13696 format %{ "CMOV$cmp $dst,$src" %}
13697 opcode(0x0F,0x40);
13698 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13699 ins_pipe( pipe_cmov_reg );
13700 %}
13702 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13703 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13704 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13705 ins_cost(250);
13706 format %{ "CMOV$cmp $dst,$src" %}
13707 opcode(0x0F,0x40);
13708 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13709 ins_pipe( pipe_cmov_mem );
13710 %}
13712 // Compare 2 longs and CMOVE ints.
13713 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13714 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13715 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13716 ins_cost(200);
13717 format %{ "CMOV$cmp $dst,$src" %}
13718 opcode(0x0F,0x40);
13719 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13720 ins_pipe( pipe_cmov_reg );
13721 %}
13723 // Compare 2 longs and CMOVE doubles
13724 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13725 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13726 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13727 ins_cost(200);
13728 expand %{
13729 fcmovD_regS(cmp,flags,dst,src);
13730 %}
13731 %}
13733 // Compare 2 longs and CMOVE doubles
13734 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13735 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13736 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13737 ins_cost(200);
13738 expand %{
13739 fcmovXD_regS(cmp,flags,dst,src);
13740 %}
13741 %}
13743 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13744 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13745 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13746 ins_cost(200);
13747 expand %{
13748 fcmovF_regS(cmp,flags,dst,src);
13749 %}
13750 %}
13752 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13753 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13754 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13755 ins_cost(200);
13756 expand %{
13757 fcmovX_regS(cmp,flags,dst,src);
13758 %}
13759 %}
13761 //======
13762 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13763 // Same as cmpL_reg_flags_LEGT except must negate src
13764 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13765 match( Set flags (CmpL src zero ));
13766 effect( TEMP tmp );
13767 ins_cost(300);
13768 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13769 "CMP $tmp,$src.lo\n\t"
13770 "SBB $tmp,$src.hi\n\t" %}
13771 ins_encode( long_cmp_flags3(src, tmp) );
13772 ins_pipe( ialu_reg_reg_long );
13773 %}
13775 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13776 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13777 // requires a commuted test to get the same result.
13778 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13779 match( Set flags (CmpL src1 src2 ));
13780 effect( TEMP tmp );
13781 ins_cost(300);
13782 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13783 "MOV $tmp,$src2.hi\n\t"
13784 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13785 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13786 ins_pipe( ialu_cr_reg_reg );
13787 %}
13789 // Long compares reg < zero/req OR reg >= zero/req.
13790 // Just a wrapper for a normal branch, plus the predicate test
13791 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13792 match(If cmp flags);
13793 effect(USE labl);
13794 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13795 ins_cost(300);
13796 expand %{
13797 jmpCon(cmp,flags,labl); // JGT or JLE...
13798 %}
13799 %}
13801 // Compare 2 longs and CMOVE longs.
13802 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13803 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13804 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13805 ins_cost(400);
13806 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13807 "CMOV$cmp $dst.hi,$src.hi" %}
13808 opcode(0x0F,0x40);
13809 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13810 ins_pipe( pipe_cmov_reg_long );
13811 %}
13813 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13814 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13815 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13816 ins_cost(500);
13817 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13818 "CMOV$cmp $dst.hi,$src.hi+4" %}
13819 opcode(0x0F,0x40);
13820 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13821 ins_pipe( pipe_cmov_reg_long );
13822 %}
13824 // Compare 2 longs and CMOVE ints.
13825 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13826 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13827 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13828 ins_cost(200);
13829 format %{ "CMOV$cmp $dst,$src" %}
13830 opcode(0x0F,0x40);
13831 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13832 ins_pipe( pipe_cmov_reg );
13833 %}
13835 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13836 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13837 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13838 ins_cost(250);
13839 format %{ "CMOV$cmp $dst,$src" %}
13840 opcode(0x0F,0x40);
13841 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13842 ins_pipe( pipe_cmov_mem );
13843 %}
13845 // Compare 2 longs and CMOVE ptrs.
13846 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13847 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13848 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13849 ins_cost(200);
13850 format %{ "CMOV$cmp $dst,$src" %}
13851 opcode(0x0F,0x40);
13852 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13853 ins_pipe( pipe_cmov_reg );
13854 %}
13856 // Compare 2 longs and CMOVE doubles
13857 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13858 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13859 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13860 ins_cost(200);
13861 expand %{
13862 fcmovD_regS(cmp,flags,dst,src);
13863 %}
13864 %}
13866 // Compare 2 longs and CMOVE doubles
13867 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13868 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13869 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13870 ins_cost(200);
13871 expand %{
13872 fcmovXD_regS(cmp,flags,dst,src);
13873 %}
13874 %}
13876 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13877 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13878 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13879 ins_cost(200);
13880 expand %{
13881 fcmovF_regS(cmp,flags,dst,src);
13882 %}
13883 %}
13886 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13887 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13888 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13889 ins_cost(200);
13890 expand %{
13891 fcmovX_regS(cmp,flags,dst,src);
13892 %}
13893 %}
13896 // ============================================================================
13897 // Procedure Call/Return Instructions
13898 // Call Java Static Instruction
13899 // Note: If this code changes, the corresponding ret_addr_offset() and
13900 // compute_padding() functions will have to be adjusted.
13901 instruct CallStaticJavaDirect(method meth) %{
13902 match(CallStaticJava);
13903 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13904 effect(USE meth);
13906 ins_cost(300);
13907 format %{ "CALL,static " %}
13908 opcode(0xE8); /* E8 cd */
13909 ins_encode( pre_call_FPU,
13910 Java_Static_Call( meth ),
13911 call_epilog,
13912 post_call_FPU );
13913 ins_pipe( pipe_slow );
13914 ins_alignment(4);
13915 %}
13917 // Call Java Static Instruction (method handle version)
13918 // Note: If this code changes, the corresponding ret_addr_offset() and
13919 // compute_padding() functions will have to be adjusted.
13920 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13921 match(CallStaticJava);
13922 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13923 effect(USE meth);
13924 // EBP is saved by all callees (for interpreter stack correction).
13925 // We use it here for a similar purpose, in {preserve,restore}_SP.
13927 ins_cost(300);
13928 format %{ "CALL,static/MethodHandle " %}
13929 opcode(0xE8); /* E8 cd */
13930 ins_encode( pre_call_FPU,
13931 preserve_SP,
13932 Java_Static_Call( meth ),
13933 restore_SP,
13934 call_epilog,
13935 post_call_FPU );
13936 ins_pipe( pipe_slow );
13937 ins_alignment(4);
13938 %}
13940 // Call Java Dynamic Instruction
13941 // Note: If this code changes, the corresponding ret_addr_offset() and
13942 // compute_padding() functions will have to be adjusted.
13943 instruct CallDynamicJavaDirect(method meth) %{
13944 match(CallDynamicJava);
13945 effect(USE meth);
13947 ins_cost(300);
13948 format %{ "MOV EAX,(oop)-1\n\t"
13949 "CALL,dynamic" %}
13950 opcode(0xE8); /* E8 cd */
13951 ins_encode( pre_call_FPU,
13952 Java_Dynamic_Call( meth ),
13953 call_epilog,
13954 post_call_FPU );
13955 ins_pipe( pipe_slow );
13956 ins_alignment(4);
13957 %}
13959 // Call Runtime Instruction
13960 instruct CallRuntimeDirect(method meth) %{
13961 match(CallRuntime );
13962 effect(USE meth);
13964 ins_cost(300);
13965 format %{ "CALL,runtime " %}
13966 opcode(0xE8); /* E8 cd */
13967 // Use FFREEs to clear entries in float stack
13968 ins_encode( pre_call_FPU,
13969 FFree_Float_Stack_All,
13970 Java_To_Runtime( meth ),
13971 post_call_FPU );
13972 ins_pipe( pipe_slow );
13973 %}
13975 // Call runtime without safepoint
13976 instruct CallLeafDirect(method meth) %{
13977 match(CallLeaf);
13978 effect(USE meth);
13980 ins_cost(300);
13981 format %{ "CALL_LEAF,runtime " %}
13982 opcode(0xE8); /* E8 cd */
13983 ins_encode( pre_call_FPU,
13984 FFree_Float_Stack_All,
13985 Java_To_Runtime( meth ),
13986 Verify_FPU_For_Leaf, post_call_FPU );
13987 ins_pipe( pipe_slow );
13988 %}
13990 instruct CallLeafNoFPDirect(method meth) %{
13991 match(CallLeafNoFP);
13992 effect(USE meth);
13994 ins_cost(300);
13995 format %{ "CALL_LEAF_NOFP,runtime " %}
13996 opcode(0xE8); /* E8 cd */
13997 ins_encode(Java_To_Runtime(meth));
13998 ins_pipe( pipe_slow );
13999 %}
14002 // Return Instruction
14003 // Remove the return address & jump to it.
14004 instruct Ret() %{
14005 match(Return);
14006 format %{ "RET" %}
14007 opcode(0xC3);
14008 ins_encode(OpcP);
14009 ins_pipe( pipe_jmp );
14010 %}
14012 // Tail Call; Jump from runtime stub to Java code.
14013 // Also known as an 'interprocedural jump'.
14014 // Target of jump will eventually return to caller.
14015 // TailJump below removes the return address.
14016 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
14017 match(TailCall jump_target method_oop );
14018 ins_cost(300);
14019 format %{ "JMP $jump_target \t# EBX holds method oop" %}
14020 opcode(0xFF, 0x4); /* Opcode FF /4 */
14021 ins_encode( OpcP, RegOpc(jump_target) );
14022 ins_pipe( pipe_jmp );
14023 %}
14026 // Tail Jump; remove the return address; jump to target.
14027 // TailCall above leaves the return address around.
14028 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
14029 match( TailJump jump_target ex_oop );
14030 ins_cost(300);
14031 format %{ "POP EDX\t# pop return address into dummy\n\t"
14032 "JMP $jump_target " %}
14033 opcode(0xFF, 0x4); /* Opcode FF /4 */
14034 ins_encode( enc_pop_rdx,
14035 OpcP, RegOpc(jump_target) );
14036 ins_pipe( pipe_jmp );
14037 %}
14039 // Create exception oop: created by stack-crawling runtime code.
14040 // Created exception is now available to this handler, and is setup
14041 // just prior to jumping to this handler. No code emitted.
14042 instruct CreateException( eAXRegP ex_oop )
14043 %{
14044 match(Set ex_oop (CreateEx));
14046 size(0);
14047 // use the following format syntax
14048 format %{ "# exception oop is in EAX; no code emitted" %}
14049 ins_encode();
14050 ins_pipe( empty );
14051 %}
14054 // Rethrow exception:
14055 // The exception oop will come in the first argument position.
14056 // Then JUMP (not call) to the rethrow stub code.
14057 instruct RethrowException()
14058 %{
14059 match(Rethrow);
14061 // use the following format syntax
14062 format %{ "JMP rethrow_stub" %}
14063 ins_encode(enc_rethrow);
14064 ins_pipe( pipe_jmp );
14065 %}
14067 // inlined locking and unlocking
14070 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
14071 match( Set cr (FastLock object box) );
14072 effect( TEMP tmp, TEMP scr );
14073 ins_cost(300);
14074 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
14075 ins_encode( Fast_Lock(object,box,tmp,scr) );
14076 ins_pipe( pipe_slow );
14077 %}
14079 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
14080 match( Set cr (FastUnlock object box) );
14081 effect( TEMP tmp );
14082 ins_cost(300);
14083 format %{ "FASTUNLOCK $object, $box, $tmp" %}
14084 ins_encode( Fast_Unlock(object,box,tmp) );
14085 ins_pipe( pipe_slow );
14086 %}
14090 // ============================================================================
14091 // Safepoint Instruction
14092 instruct safePoint_poll(eFlagsReg cr) %{
14093 match(SafePoint);
14094 effect(KILL cr);
14096 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
14097 // On SPARC that might be acceptable as we can generate the address with
14098 // just a sethi, saving an or. By polling at offset 0 we can end up
14099 // putting additional pressure on the index-0 in the D$. Because of
14100 // alignment (just like the situation at hand) the lower indices tend
14101 // to see more traffic. It'd be better to change the polling address
14102 // to offset 0 of the last $line in the polling page.
14104 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
14105 ins_cost(125);
14106 size(6) ;
14107 ins_encode( Safepoint_Poll() );
14108 ins_pipe( ialu_reg_mem );
14109 %}
14111 //----------PEEPHOLE RULES-----------------------------------------------------
14112 // These must follow all instruction definitions as they use the names
14113 // defined in the instructions definitions.
14114 //
14115 // peepmatch ( root_instr_name [preceding_instruction]* );
14116 //
14117 // peepconstraint %{
14118 // (instruction_number.operand_name relational_op instruction_number.operand_name
14119 // [, ...] );
14120 // // instruction numbers are zero-based using left to right order in peepmatch
14121 //
14122 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14123 // // provide an instruction_number.operand_name for each operand that appears
14124 // // in the replacement instruction's match rule
14125 //
14126 // ---------VM FLAGS---------------------------------------------------------
14127 //
14128 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14129 //
14130 // Each peephole rule is given an identifying number starting with zero and
14131 // increasing by one in the order seen by the parser. An individual peephole
14132 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14133 // on the command-line.
14134 //
14135 // ---------CURRENT LIMITATIONS----------------------------------------------
14136 //
14137 // Only match adjacent instructions in same basic block
14138 // Only equality constraints
14139 // Only constraints between operands, not (0.dest_reg == EAX_enc)
14140 // Only one replacement instruction
14141 //
14142 // ---------EXAMPLE----------------------------------------------------------
14143 //
14144 // // pertinent parts of existing instructions in architecture description
14145 // instruct movI(eRegI dst, eRegI src) %{
14146 // match(Set dst (CopyI src));
14147 // %}
14148 //
14149 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
14150 // match(Set dst (AddI dst src));
14151 // effect(KILL cr);
14152 // %}
14153 //
14154 // // Change (inc mov) to lea
14155 // peephole %{
14156 // // increment preceeded by register-register move
14157 // peepmatch ( incI_eReg movI );
14158 // // require that the destination register of the increment
14159 // // match the destination register of the move
14160 // peepconstraint ( 0.dst == 1.dst );
14161 // // construct a replacement instruction that sets
14162 // // the destination to ( move's source register + one )
14163 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14164 // %}
14165 //
14166 // Implementation no longer uses movX instructions since
14167 // machine-independent system no longer uses CopyX nodes.
14168 //
14169 // peephole %{
14170 // peepmatch ( incI_eReg movI );
14171 // peepconstraint ( 0.dst == 1.dst );
14172 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14173 // %}
14174 //
14175 // peephole %{
14176 // peepmatch ( decI_eReg movI );
14177 // peepconstraint ( 0.dst == 1.dst );
14178 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14179 // %}
14180 //
14181 // peephole %{
14182 // peepmatch ( addI_eReg_imm movI );
14183 // peepconstraint ( 0.dst == 1.dst );
14184 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14185 // %}
14186 //
14187 // peephole %{
14188 // peepmatch ( addP_eReg_imm movP );
14189 // peepconstraint ( 0.dst == 1.dst );
14190 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
14191 // %}
14193 // // Change load of spilled value to only a spill
14194 // instruct storeI(memory mem, eRegI src) %{
14195 // match(Set mem (StoreI mem src));
14196 // %}
14197 //
14198 // instruct loadI(eRegI dst, memory mem) %{
14199 // match(Set dst (LoadI mem));
14200 // %}
14201 //
14202 peephole %{
14203 peepmatch ( loadI storeI );
14204 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
14205 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
14206 %}
14208 //----------SMARTSPILL RULES---------------------------------------------------
14209 // These must follow all instruction definitions as they use the names
14210 // defined in the instructions definitions.