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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp@d804e148cff8
src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
Fri, 12 Oct 2012 09:22:52 -0700
- author
- kvn
- date
- Fri, 12 Oct 2012 09:22:52 -0700
- changeset 4164
- d804e148cff8
- parent 4142
- d8ce2825b193
- parent 4159
- 8e47bac5643a
- child 4318
- cd3d6a6b95d9
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Merge
1 /*
2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc_interface/collectedHeap.hpp"
35 #include "memory/barrierSet.hpp"
36 #include "memory/cardTableModRefBS.hpp"
37 #include "nativeInst_x86.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/sharedRuntime.hpp"
42 // These masks are used to provide 128-bit aligned bitmasks to the XMM
43 // instructions, to allow sign-masking or sign-bit flipping. They allow
44 // fast versions of NegF/NegD and AbsF/AbsD.
46 // Note: 'double' and 'long long' have 32-bits alignment on x86.
47 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
48 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
49 // of 128-bits operands for SSE instructions.
50 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
51 // Store the value to a 128-bits operand.
52 operand[0] = lo;
53 operand[1] = hi;
54 return operand;
55 }
57 // Buffer for 128-bits masks used by SSE instructions.
58 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
60 // Static initialization during VM startup.
61 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
62 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
63 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
64 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
68 NEEDS_CLEANUP // remove this definitions ?
69 const Register IC_Klass = rax; // where the IC klass is cached
70 const Register SYNC_header = rax; // synchronization header
71 const Register SHIFT_count = rcx; // where count for shift operations must be
73 #define __ _masm->
76 static void select_different_registers(Register preserve,
77 Register extra,
78 Register &tmp1,
79 Register &tmp2) {
80 if (tmp1 == preserve) {
81 assert_different_registers(tmp1, tmp2, extra);
82 tmp1 = extra;
83 } else if (tmp2 == preserve) {
84 assert_different_registers(tmp1, tmp2, extra);
85 tmp2 = extra;
86 }
87 assert_different_registers(preserve, tmp1, tmp2);
88 }
92 static void select_different_registers(Register preserve,
93 Register extra,
94 Register &tmp1,
95 Register &tmp2,
96 Register &tmp3) {
97 if (tmp1 == preserve) {
98 assert_different_registers(tmp1, tmp2, tmp3, extra);
99 tmp1 = extra;
100 } else if (tmp2 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp2 = extra;
103 } else if (tmp3 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp3 = extra;
106 }
107 assert_different_registers(preserve, tmp1, tmp2, tmp3);
108 }
112 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
113 if (opr->is_constant()) {
114 LIR_Const* constant = opr->as_constant_ptr();
115 switch (constant->type()) {
116 case T_INT: {
117 return true;
118 }
120 default:
121 return false;
122 }
123 }
124 return false;
125 }
128 LIR_Opr LIR_Assembler::receiverOpr() {
129 return FrameMap::receiver_opr;
130 }
132 LIR_Opr LIR_Assembler::osrBufferPointer() {
133 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
134 }
136 //--------------fpu register translations-----------------------
139 address LIR_Assembler::float_constant(float f) {
140 address const_addr = __ float_constant(f);
141 if (const_addr == NULL) {
142 bailout("const section overflow");
143 return __ code()->consts()->start();
144 } else {
145 return const_addr;
146 }
147 }
150 address LIR_Assembler::double_constant(double d) {
151 address const_addr = __ double_constant(d);
152 if (const_addr == NULL) {
153 bailout("const section overflow");
154 return __ code()->consts()->start();
155 } else {
156 return const_addr;
157 }
158 }
161 void LIR_Assembler::set_24bit_FPU() {
162 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
163 }
165 void LIR_Assembler::reset_FPU() {
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
167 }
169 void LIR_Assembler::fpop() {
170 __ fpop();
171 }
173 void LIR_Assembler::fxch(int i) {
174 __ fxch(i);
175 }
177 void LIR_Assembler::fld(int i) {
178 __ fld_s(i);
179 }
181 void LIR_Assembler::ffree(int i) {
182 __ ffree(i);
183 }
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject());
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
207 } else {
208 ShouldNotReachHere();
209 }
210 }
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
224 //-------------------------------------------
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
243 Register base = addr->base()->as_pointer_register();
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes());
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (2 * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is NULL");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 Register receiver = FrameMap::receiver_opr->as_register();
341 Register ic_klass = IC_Klass;
342 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
343 const bool do_post_padding = VerifyOops || UseCompressedKlassPointers;
344 if (!do_post_padding) {
345 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
346 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
347 __ nop();
348 }
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_mirror_id);
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() {
378 // if rounding, must let FrameMap know!
380 // The frame_map records size in slots (32bit word)
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size);
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
403 int offset = code_offset();
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
416 __ end_a_stub();
418 return offset;
419 }
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
431 int offset = code_offset();
433 // Fetch the exception from TLS and clear out exception related thread state
434 __ get_thread(rsi);
435 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
436 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
437 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439 __ bind(_unwind_handler_entry);
440 __ verify_not_null_oop(rax);
441 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
442 __ mov(rsi, rax); // Preserve the exception
443 }
445 // Preform needed unlocking
446 MonitorExitStub* stub = NULL;
447 if (method()->is_synchronized()) {
448 monitor_address(0, FrameMap::rax_opr);
449 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
450 __ unlock_object(rdi, rbx, rax, *stub->entry());
451 __ bind(*stub->continuation());
452 }
454 if (compilation()->env()->dtrace_method_probes()) {
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
458 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
459 }
461 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
462 __ mov(rax, rsi); // Restore the exception
463 }
465 // remove the activation and dispatch to the unwind handler
466 __ remove_frame(initial_frame_size_in_bytes());
467 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
469 // Emit the slow path assembly
470 if (stub != NULL) {
471 stub->emit_code(this);
472 }
474 return offset;
475 }
478 int LIR_Assembler::emit_deopt_handler() {
479 // if the last instruction is a call (typically to do a throw which
480 // is coming at the end after block reordering) the return address
481 // must still point into the code area in order to avoid assertion
482 // failures when searching for the corresponding bci => add a nop
483 // (was bug 5/14/1999 - gri)
484 __ nop();
486 // generate code for exception handler
487 address handler_base = __ start_a_stub(deopt_handler_size);
488 if (handler_base == NULL) {
489 // not enough space left for the handler
490 bailout("deopt handler overflow");
491 return -1;
492 }
494 int offset = code_offset();
495 InternalAddress here(__ pc());
497 __ pushptr(here.addr());
498 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
499 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
500 __ end_a_stub();
502 return offset;
503 }
506 // This is the fast version of java.lang.String.compare; it has not
507 // OSR-entry and therefore, we generate a slow version for OSR's
508 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
509 __ movptr (rbx, rcx); // receiver is in rcx
510 __ movptr (rax, arg1->as_register());
512 // Get addresses of first characters from both Strings
513 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
514 if (java_lang_String::has_offset_field()) {
515 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
516 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
517 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
518 } else {
519 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
520 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
521 }
523 // rbx, may be NULL
524 add_debug_info_for_null_check_here(info);
525 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
526 if (java_lang_String::has_offset_field()) {
527 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
528 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
529 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
530 } else {
531 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
532 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
533 }
535 // compute minimum length (in rax) and difference of lengths (on top of stack)
536 __ mov (rcx, rbx);
537 __ subptr(rbx, rax); // subtract lengths
538 __ push (rbx); // result
539 __ cmov (Assembler::lessEqual, rax, rcx);
541 // is minimum length 0?
542 Label noLoop, haveResult;
543 __ testptr (rax, rax);
544 __ jcc (Assembler::zero, noLoop);
546 // compare first characters
547 __ load_unsigned_short(rcx, Address(rdi, 0));
548 __ load_unsigned_short(rbx, Address(rsi, 0));
549 __ subl(rcx, rbx);
550 __ jcc(Assembler::notZero, haveResult);
551 // starting loop
552 __ decrement(rax); // we already tested index: skip one
553 __ jcc(Assembler::zero, noLoop);
555 // set rsi.edi to the end of the arrays (arrays have same length)
556 // negate the index
558 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
559 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
560 __ negptr(rax);
562 // compare the strings in a loop
564 Label loop;
565 __ align(wordSize);
566 __ bind(loop);
567 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
568 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
569 __ subl(rcx, rbx);
570 __ jcc(Assembler::notZero, haveResult);
571 __ increment(rax);
572 __ jcc(Assembler::notZero, loop);
574 // strings are equal up to min length
576 __ bind(noLoop);
577 __ pop(rax);
578 return_op(LIR_OprFact::illegalOpr);
580 __ bind(haveResult);
581 // leave instruction is going to discard the TOS value
582 __ mov (rax, rcx); // result of call is in rax,
583 }
586 void LIR_Assembler::return_op(LIR_Opr result) {
587 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
588 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
589 assert(result->fpu() == 0, "result must already be on TOS");
590 }
592 // Pop the stack before the safepoint code
593 __ remove_frame(initial_frame_size_in_bytes());
595 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
597 // Note: we do not need to round double result; float result has the right precision
598 // the poll sets the condition code, but no data registers
599 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
600 relocInfo::poll_return_type);
602 if (Assembler::is_polling_page_far()) {
603 __ lea(rscratch1, polling_page);
604 __ relocate(relocInfo::poll_return_type);
605 __ testl(rax, Address(rscratch1, 0));
606 } else {
607 __ testl(rax, polling_page);
608 }
609 __ ret(0);
610 }
613 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
614 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
615 relocInfo::poll_type);
616 guarantee(info != NULL, "Shouldn't be NULL");
617 int offset = __ offset();
618 if (Assembler::is_polling_page_far()) {
619 __ lea(rscratch1, polling_page);
620 offset = __ offset();
621 add_debug_info_for_branch(info);
622 __ testl(rax, Address(rscratch1, 0));
623 } else {
624 add_debug_info_for_branch(info);
625 __ testl(rax, polling_page);
626 }
627 return offset;
628 }
631 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
632 if (from_reg != to_reg) __ mov(to_reg, from_reg);
633 }
635 void LIR_Assembler::swap_reg(Register a, Register b) {
636 __ xchgptr(a, b);
637 }
640 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
641 assert(src->is_constant(), "should not call otherwise");
642 assert(dest->is_register(), "should not call otherwise");
643 LIR_Const* c = src->as_constant_ptr();
645 switch (c->type()) {
646 case T_INT: {
647 assert(patch_code == lir_patch_none, "no patching handled here");
648 __ movl(dest->as_register(), c->as_jint());
649 break;
650 }
652 case T_ADDRESS: {
653 assert(patch_code == lir_patch_none, "no patching handled here");
654 __ movptr(dest->as_register(), c->as_jint());
655 break;
656 }
658 case T_LONG: {
659 assert(patch_code == lir_patch_none, "no patching handled here");
660 #ifdef _LP64
661 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
662 #else
663 __ movptr(dest->as_register_lo(), c->as_jint_lo());
664 __ movptr(dest->as_register_hi(), c->as_jint_hi());
665 #endif // _LP64
666 break;
667 }
669 case T_OBJECT: {
670 if (patch_code != lir_patch_none) {
671 jobject2reg_with_patching(dest->as_register(), info);
672 } else {
673 __ movoop(dest->as_register(), c->as_jobject());
674 }
675 break;
676 }
678 case T_METADATA: {
679 if (patch_code != lir_patch_none) {
680 klass2reg_with_patching(dest->as_register(), info);
681 } else {
682 __ mov_metadata(dest->as_register(), c->as_metadata());
683 }
684 break;
685 }
687 case T_FLOAT: {
688 if (dest->is_single_xmm()) {
689 if (c->is_zero_float()) {
690 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
691 } else {
692 __ movflt(dest->as_xmm_float_reg(),
693 InternalAddress(float_constant(c->as_jfloat())));
694 }
695 } else {
696 assert(dest->is_single_fpu(), "must be");
697 assert(dest->fpu_regnr() == 0, "dest must be TOS");
698 if (c->is_zero_float()) {
699 __ fldz();
700 } else if (c->is_one_float()) {
701 __ fld1();
702 } else {
703 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
704 }
705 }
706 break;
707 }
709 case T_DOUBLE: {
710 if (dest->is_double_xmm()) {
711 if (c->is_zero_double()) {
712 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
713 } else {
714 __ movdbl(dest->as_xmm_double_reg(),
715 InternalAddress(double_constant(c->as_jdouble())));
716 }
717 } else {
718 assert(dest->is_double_fpu(), "must be");
719 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
720 if (c->is_zero_double()) {
721 __ fldz();
722 } else if (c->is_one_double()) {
723 __ fld1();
724 } else {
725 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
726 }
727 }
728 break;
729 }
731 default:
732 ShouldNotReachHere();
733 }
734 }
736 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
737 assert(src->is_constant(), "should not call otherwise");
738 assert(dest->is_stack(), "should not call otherwise");
739 LIR_Const* c = src->as_constant_ptr();
741 switch (c->type()) {
742 case T_INT: // fall through
743 case T_FLOAT:
744 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
745 break;
747 case T_ADDRESS:
748 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
749 break;
751 case T_OBJECT:
752 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
753 break;
755 case T_LONG: // fall through
756 case T_DOUBLE:
757 #ifdef _LP64
758 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
759 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
760 #else
761 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
762 lo_word_offset_in_bytes), c->as_jint_lo_bits());
763 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
764 hi_word_offset_in_bytes), c->as_jint_hi_bits());
765 #endif // _LP64
766 break;
768 default:
769 ShouldNotReachHere();
770 }
771 }
773 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
774 assert(src->is_constant(), "should not call otherwise");
775 assert(dest->is_address(), "should not call otherwise");
776 LIR_Const* c = src->as_constant_ptr();
777 LIR_Address* addr = dest->as_address_ptr();
779 int null_check_here = code_offset();
780 switch (type) {
781 case T_INT: // fall through
782 case T_FLOAT:
783 __ movl(as_Address(addr), c->as_jint_bits());
784 break;
786 case T_ADDRESS:
787 __ movptr(as_Address(addr), c->as_jint_bits());
788 break;
790 case T_OBJECT: // fall through
791 case T_ARRAY:
792 if (c->as_jobject() == NULL) {
793 if (UseCompressedOops && !wide) {
794 __ movl(as_Address(addr), (int32_t)NULL_WORD);
795 } else {
796 __ movptr(as_Address(addr), NULL_WORD);
797 }
798 } else {
799 if (is_literal_address(addr)) {
800 ShouldNotReachHere();
801 __ movoop(as_Address(addr, noreg), c->as_jobject());
802 } else {
803 #ifdef _LP64
804 __ movoop(rscratch1, c->as_jobject());
805 if (UseCompressedOops && !wide) {
806 __ encode_heap_oop(rscratch1);
807 null_check_here = code_offset();
808 __ movl(as_Address_lo(addr), rscratch1);
809 } else {
810 null_check_here = code_offset();
811 __ movptr(as_Address_lo(addr), rscratch1);
812 }
813 #else
814 __ movoop(as_Address(addr), c->as_jobject());
815 #endif
816 }
817 }
818 break;
820 case T_LONG: // fall through
821 case T_DOUBLE:
822 #ifdef _LP64
823 if (is_literal_address(addr)) {
824 ShouldNotReachHere();
825 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
826 } else {
827 __ movptr(r10, (intptr_t)c->as_jlong_bits());
828 null_check_here = code_offset();
829 __ movptr(as_Address_lo(addr), r10);
830 }
831 #else
832 // Always reachable in 32bit so this doesn't produce useless move literal
833 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
834 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
835 #endif // _LP64
836 break;
838 case T_BOOLEAN: // fall through
839 case T_BYTE:
840 __ movb(as_Address(addr), c->as_jint() & 0xFF);
841 break;
843 case T_CHAR: // fall through
844 case T_SHORT:
845 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
846 break;
848 default:
849 ShouldNotReachHere();
850 };
852 if (info != NULL) {
853 add_debug_info_for_null_check(null_check_here, info);
854 }
855 }
858 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
859 assert(src->is_register(), "should not call otherwise");
860 assert(dest->is_register(), "should not call otherwise");
862 // move between cpu-registers
863 if (dest->is_single_cpu()) {
864 #ifdef _LP64
865 if (src->type() == T_LONG) {
866 // Can do LONG -> OBJECT
867 move_regs(src->as_register_lo(), dest->as_register());
868 return;
869 }
870 #endif
871 assert(src->is_single_cpu(), "must match");
872 if (src->type() == T_OBJECT) {
873 __ verify_oop(src->as_register());
874 }
875 move_regs(src->as_register(), dest->as_register());
877 } else if (dest->is_double_cpu()) {
878 #ifdef _LP64
879 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
880 // Surprising to me but we can see move of a long to t_object
881 __ verify_oop(src->as_register());
882 move_regs(src->as_register(), dest->as_register_lo());
883 return;
884 }
885 #endif
886 assert(src->is_double_cpu(), "must match");
887 Register f_lo = src->as_register_lo();
888 Register f_hi = src->as_register_hi();
889 Register t_lo = dest->as_register_lo();
890 Register t_hi = dest->as_register_hi();
891 #ifdef _LP64
892 assert(f_hi == f_lo, "must be same");
893 assert(t_hi == t_lo, "must be same");
894 move_regs(f_lo, t_lo);
895 #else
896 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
899 if (f_lo == t_hi && f_hi == t_lo) {
900 swap_reg(f_lo, f_hi);
901 } else if (f_hi == t_lo) {
902 assert(f_lo != t_hi, "overwriting register");
903 move_regs(f_hi, t_hi);
904 move_regs(f_lo, t_lo);
905 } else {
906 assert(f_hi != t_lo, "overwriting register");
907 move_regs(f_lo, t_lo);
908 move_regs(f_hi, t_hi);
909 }
910 #endif // LP64
912 // special moves from fpu-register to xmm-register
913 // necessary for method results
914 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
915 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
916 __ fld_s(Address(rsp, 0));
917 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
918 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
919 __ fld_d(Address(rsp, 0));
920 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
921 __ fstp_s(Address(rsp, 0));
922 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
923 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
924 __ fstp_d(Address(rsp, 0));
925 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
927 // move between xmm-registers
928 } else if (dest->is_single_xmm()) {
929 assert(src->is_single_xmm(), "must match");
930 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
931 } else if (dest->is_double_xmm()) {
932 assert(src->is_double_xmm(), "must match");
933 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
935 // move between fpu-registers (no instruction necessary because of fpu-stack)
936 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
937 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
938 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
939 } else {
940 ShouldNotReachHere();
941 }
942 }
944 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
945 assert(src->is_register(), "should not call otherwise");
946 assert(dest->is_stack(), "should not call otherwise");
948 if (src->is_single_cpu()) {
949 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
950 if (type == T_OBJECT || type == T_ARRAY) {
951 __ verify_oop(src->as_register());
952 __ movptr (dst, src->as_register());
953 } else if (type == T_METADATA) {
954 __ movptr (dst, src->as_register());
955 } else {
956 __ movl (dst, src->as_register());
957 }
959 } else if (src->is_double_cpu()) {
960 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
961 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
962 __ movptr (dstLO, src->as_register_lo());
963 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
965 } else if (src->is_single_xmm()) {
966 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
967 __ movflt(dst_addr, src->as_xmm_float_reg());
969 } else if (src->is_double_xmm()) {
970 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
971 __ movdbl(dst_addr, src->as_xmm_double_reg());
973 } else if (src->is_single_fpu()) {
974 assert(src->fpu_regnr() == 0, "argument must be on TOS");
975 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
976 if (pop_fpu_stack) __ fstp_s (dst_addr);
977 else __ fst_s (dst_addr);
979 } else if (src->is_double_fpu()) {
980 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
981 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
982 if (pop_fpu_stack) __ fstp_d (dst_addr);
983 else __ fst_d (dst_addr);
985 } else {
986 ShouldNotReachHere();
987 }
988 }
991 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
992 LIR_Address* to_addr = dest->as_address_ptr();
993 PatchingStub* patch = NULL;
994 Register compressed_src = rscratch1;
996 if (type == T_ARRAY || type == T_OBJECT) {
997 __ verify_oop(src->as_register());
998 #ifdef _LP64
999 if (UseCompressedOops && !wide) {
1000 __ movptr(compressed_src, src->as_register());
1001 __ encode_heap_oop(compressed_src);
1002 }
1003 #endif
1004 }
1006 if (patch_code != lir_patch_none) {
1007 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1008 Address toa = as_Address(to_addr);
1009 assert(toa.disp() != 0, "must have");
1010 }
1012 int null_check_here = code_offset();
1013 switch (type) {
1014 case T_FLOAT: {
1015 if (src->is_single_xmm()) {
1016 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1017 } else {
1018 assert(src->is_single_fpu(), "must be");
1019 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1020 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1021 else __ fst_s (as_Address(to_addr));
1022 }
1023 break;
1024 }
1026 case T_DOUBLE: {
1027 if (src->is_double_xmm()) {
1028 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1029 } else {
1030 assert(src->is_double_fpu(), "must be");
1031 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1032 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1033 else __ fst_d (as_Address(to_addr));
1034 }
1035 break;
1036 }
1038 case T_ARRAY: // fall through
1039 case T_OBJECT: // fall through
1040 if (UseCompressedOops && !wide) {
1041 __ movl(as_Address(to_addr), compressed_src);
1042 } else {
1043 __ movptr(as_Address(to_addr), src->as_register());
1044 }
1045 break;
1046 case T_METADATA:
1047 // We get here to store a method pointer to the stack to pass to
1048 // a dtrace runtime call. This can't work on 64 bit with
1049 // compressed klass ptrs: T_METADATA can be a compressed klass
1050 // ptr or a 64 bit method pointer.
1051 LP64_ONLY(ShouldNotReachHere());
1052 __ movptr(as_Address(to_addr), src->as_register());
1053 break;
1054 case T_ADDRESS:
1055 __ movptr(as_Address(to_addr), src->as_register());
1056 break;
1057 case T_INT:
1058 __ movl(as_Address(to_addr), src->as_register());
1059 break;
1061 case T_LONG: {
1062 Register from_lo = src->as_register_lo();
1063 Register from_hi = src->as_register_hi();
1064 #ifdef _LP64
1065 __ movptr(as_Address_lo(to_addr), from_lo);
1066 #else
1067 Register base = to_addr->base()->as_register();
1068 Register index = noreg;
1069 if (to_addr->index()->is_register()) {
1070 index = to_addr->index()->as_register();
1071 }
1072 if (base == from_lo || index == from_lo) {
1073 assert(base != from_hi, "can't be");
1074 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1075 __ movl(as_Address_hi(to_addr), from_hi);
1076 if (patch != NULL) {
1077 patching_epilog(patch, lir_patch_high, base, info);
1078 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1079 patch_code = lir_patch_low;
1080 }
1081 __ movl(as_Address_lo(to_addr), from_lo);
1082 } else {
1083 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1084 __ movl(as_Address_lo(to_addr), from_lo);
1085 if (patch != NULL) {
1086 patching_epilog(patch, lir_patch_low, base, info);
1087 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1088 patch_code = lir_patch_high;
1089 }
1090 __ movl(as_Address_hi(to_addr), from_hi);
1091 }
1092 #endif // _LP64
1093 break;
1094 }
1096 case T_BYTE: // fall through
1097 case T_BOOLEAN: {
1098 Register src_reg = src->as_register();
1099 Address dst_addr = as_Address(to_addr);
1100 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1101 __ movb(dst_addr, src_reg);
1102 break;
1103 }
1105 case T_CHAR: // fall through
1106 case T_SHORT:
1107 __ movw(as_Address(to_addr), src->as_register());
1108 break;
1110 default:
1111 ShouldNotReachHere();
1112 }
1113 if (info != NULL) {
1114 add_debug_info_for_null_check(null_check_here, info);
1115 }
1117 if (patch_code != lir_patch_none) {
1118 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1119 }
1120 }
1123 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1124 assert(src->is_stack(), "should not call otherwise");
1125 assert(dest->is_register(), "should not call otherwise");
1127 if (dest->is_single_cpu()) {
1128 if (type == T_ARRAY || type == T_OBJECT) {
1129 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1130 __ verify_oop(dest->as_register());
1131 } else if (type == T_METADATA) {
1132 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1133 } else {
1134 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1135 }
1137 } else if (dest->is_double_cpu()) {
1138 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1139 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1140 __ movptr(dest->as_register_lo(), src_addr_LO);
1141 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1143 } else if (dest->is_single_xmm()) {
1144 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1145 __ movflt(dest->as_xmm_float_reg(), src_addr);
1147 } else if (dest->is_double_xmm()) {
1148 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1149 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1151 } else if (dest->is_single_fpu()) {
1152 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1153 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1154 __ fld_s(src_addr);
1156 } else if (dest->is_double_fpu()) {
1157 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1158 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1159 __ fld_d(src_addr);
1161 } else {
1162 ShouldNotReachHere();
1163 }
1164 }
1167 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1168 if (src->is_single_stack()) {
1169 if (type == T_OBJECT || type == T_ARRAY) {
1170 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1171 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1172 } else {
1173 #ifndef _LP64
1174 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1175 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1176 #else
1177 //no pushl on 64bits
1178 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1179 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1180 #endif
1181 }
1183 } else if (src->is_double_stack()) {
1184 #ifdef _LP64
1185 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1186 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1187 #else
1188 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1189 // push and pop the part at src + wordSize, adding wordSize for the previous push
1190 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1191 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1192 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1193 #endif // _LP64
1195 } else {
1196 ShouldNotReachHere();
1197 }
1198 }
1201 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1202 assert(src->is_address(), "should not call otherwise");
1203 assert(dest->is_register(), "should not call otherwise");
1205 LIR_Address* addr = src->as_address_ptr();
1206 Address from_addr = as_Address(addr);
1208 switch (type) {
1209 case T_BOOLEAN: // fall through
1210 case T_BYTE: // fall through
1211 case T_CHAR: // fall through
1212 case T_SHORT:
1213 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1214 // on pre P6 processors we may get partial register stalls
1215 // so blow away the value of to_rinfo before loading a
1216 // partial word into it. Do it here so that it precedes
1217 // the potential patch point below.
1218 __ xorptr(dest->as_register(), dest->as_register());
1219 }
1220 break;
1221 }
1223 PatchingStub* patch = NULL;
1224 if (patch_code != lir_patch_none) {
1225 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1226 assert(from_addr.disp() != 0, "must have");
1227 }
1228 if (info != NULL) {
1229 add_debug_info_for_null_check_here(info);
1230 }
1232 switch (type) {
1233 case T_FLOAT: {
1234 if (dest->is_single_xmm()) {
1235 __ movflt(dest->as_xmm_float_reg(), from_addr);
1236 } else {
1237 assert(dest->is_single_fpu(), "must be");
1238 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1239 __ fld_s(from_addr);
1240 }
1241 break;
1242 }
1244 case T_DOUBLE: {
1245 if (dest->is_double_xmm()) {
1246 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1247 } else {
1248 assert(dest->is_double_fpu(), "must be");
1249 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1250 __ fld_d(from_addr);
1251 }
1252 break;
1253 }
1255 case T_OBJECT: // fall through
1256 case T_ARRAY: // fall through
1257 if (UseCompressedOops && !wide) {
1258 __ movl(dest->as_register(), from_addr);
1259 } else {
1260 __ movptr(dest->as_register(), from_addr);
1261 }
1262 break;
1264 case T_ADDRESS:
1265 if (UseCompressedKlassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1266 __ movl(dest->as_register(), from_addr);
1267 } else {
1268 __ movptr(dest->as_register(), from_addr);
1269 }
1270 break;
1271 case T_INT:
1272 __ movl(dest->as_register(), from_addr);
1273 break;
1275 case T_LONG: {
1276 Register to_lo = dest->as_register_lo();
1277 Register to_hi = dest->as_register_hi();
1278 #ifdef _LP64
1279 __ movptr(to_lo, as_Address_lo(addr));
1280 #else
1281 Register base = addr->base()->as_register();
1282 Register index = noreg;
1283 if (addr->index()->is_register()) {
1284 index = addr->index()->as_register();
1285 }
1286 if ((base == to_lo && index == to_hi) ||
1287 (base == to_hi && index == to_lo)) {
1288 // addresses with 2 registers are only formed as a result of
1289 // array access so this code will never have to deal with
1290 // patches or null checks.
1291 assert(info == NULL && patch == NULL, "must be");
1292 __ lea(to_hi, as_Address(addr));
1293 __ movl(to_lo, Address(to_hi, 0));
1294 __ movl(to_hi, Address(to_hi, BytesPerWord));
1295 } else if (base == to_lo || index == to_lo) {
1296 assert(base != to_hi, "can't be");
1297 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1298 __ movl(to_hi, as_Address_hi(addr));
1299 if (patch != NULL) {
1300 patching_epilog(patch, lir_patch_high, base, info);
1301 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1302 patch_code = lir_patch_low;
1303 }
1304 __ movl(to_lo, as_Address_lo(addr));
1305 } else {
1306 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1307 __ movl(to_lo, as_Address_lo(addr));
1308 if (patch != NULL) {
1309 patching_epilog(patch, lir_patch_low, base, info);
1310 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1311 patch_code = lir_patch_high;
1312 }
1313 __ movl(to_hi, as_Address_hi(addr));
1314 }
1315 #endif // _LP64
1316 break;
1317 }
1319 case T_BOOLEAN: // fall through
1320 case T_BYTE: {
1321 Register dest_reg = dest->as_register();
1322 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1323 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1324 __ movsbl(dest_reg, from_addr);
1325 } else {
1326 __ movb(dest_reg, from_addr);
1327 __ shll(dest_reg, 24);
1328 __ sarl(dest_reg, 24);
1329 }
1330 break;
1331 }
1333 case T_CHAR: {
1334 Register dest_reg = dest->as_register();
1335 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1336 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1337 __ movzwl(dest_reg, from_addr);
1338 } else {
1339 __ movw(dest_reg, from_addr);
1340 }
1341 break;
1342 }
1344 case T_SHORT: {
1345 Register dest_reg = dest->as_register();
1346 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1347 __ movswl(dest_reg, from_addr);
1348 } else {
1349 __ movw(dest_reg, from_addr);
1350 __ shll(dest_reg, 16);
1351 __ sarl(dest_reg, 16);
1352 }
1353 break;
1354 }
1356 default:
1357 ShouldNotReachHere();
1358 }
1360 if (patch != NULL) {
1361 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1362 }
1364 if (type == T_ARRAY || type == T_OBJECT) {
1365 #ifdef _LP64
1366 if (UseCompressedOops && !wide) {
1367 __ decode_heap_oop(dest->as_register());
1368 }
1369 #endif
1370 __ verify_oop(dest->as_register());
1371 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1372 #ifdef _LP64
1373 if (UseCompressedKlassPointers) {
1374 __ decode_klass_not_null(dest->as_register());
1375 }
1376 #endif
1377 }
1378 }
1381 void LIR_Assembler::prefetchr(LIR_Opr src) {
1382 LIR_Address* addr = src->as_address_ptr();
1383 Address from_addr = as_Address(addr);
1385 if (VM_Version::supports_sse()) {
1386 switch (ReadPrefetchInstr) {
1387 case 0:
1388 __ prefetchnta(from_addr); break;
1389 case 1:
1390 __ prefetcht0(from_addr); break;
1391 case 2:
1392 __ prefetcht2(from_addr); break;
1393 default:
1394 ShouldNotReachHere(); break;
1395 }
1396 } else if (VM_Version::supports_3dnow_prefetch()) {
1397 __ prefetchr(from_addr);
1398 }
1399 }
1402 void LIR_Assembler::prefetchw(LIR_Opr src) {
1403 LIR_Address* addr = src->as_address_ptr();
1404 Address from_addr = as_Address(addr);
1406 if (VM_Version::supports_sse()) {
1407 switch (AllocatePrefetchInstr) {
1408 case 0:
1409 __ prefetchnta(from_addr); break;
1410 case 1:
1411 __ prefetcht0(from_addr); break;
1412 case 2:
1413 __ prefetcht2(from_addr); break;
1414 case 3:
1415 __ prefetchw(from_addr); break;
1416 default:
1417 ShouldNotReachHere(); break;
1418 }
1419 } else if (VM_Version::supports_3dnow_prefetch()) {
1420 __ prefetchw(from_addr);
1421 }
1422 }
1425 NEEDS_CLEANUP; // This could be static?
1426 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1427 int elem_size = type2aelembytes(type);
1428 switch (elem_size) {
1429 case 1: return Address::times_1;
1430 case 2: return Address::times_2;
1431 case 4: return Address::times_4;
1432 case 8: return Address::times_8;
1433 }
1434 ShouldNotReachHere();
1435 return Address::no_scale;
1436 }
1439 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1440 switch (op->code()) {
1441 case lir_idiv:
1442 case lir_irem:
1443 arithmetic_idiv(op->code(),
1444 op->in_opr1(),
1445 op->in_opr2(),
1446 op->in_opr3(),
1447 op->result_opr(),
1448 op->info());
1449 break;
1450 default: ShouldNotReachHere(); break;
1451 }
1452 }
1454 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1455 #ifdef ASSERT
1456 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1457 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1458 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1459 #endif
1461 if (op->cond() == lir_cond_always) {
1462 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1463 __ jmp (*(op->label()));
1464 } else {
1465 Assembler::Condition acond = Assembler::zero;
1466 if (op->code() == lir_cond_float_branch) {
1467 assert(op->ublock() != NULL, "must have unordered successor");
1468 __ jcc(Assembler::parity, *(op->ublock()->label()));
1469 switch(op->cond()) {
1470 case lir_cond_equal: acond = Assembler::equal; break;
1471 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1472 case lir_cond_less: acond = Assembler::below; break;
1473 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1474 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1475 case lir_cond_greater: acond = Assembler::above; break;
1476 default: ShouldNotReachHere();
1477 }
1478 } else {
1479 switch (op->cond()) {
1480 case lir_cond_equal: acond = Assembler::equal; break;
1481 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1482 case lir_cond_less: acond = Assembler::less; break;
1483 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1484 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1485 case lir_cond_greater: acond = Assembler::greater; break;
1486 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1487 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1488 default: ShouldNotReachHere();
1489 }
1490 }
1491 __ jcc(acond,*(op->label()));
1492 }
1493 }
1495 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1496 LIR_Opr src = op->in_opr();
1497 LIR_Opr dest = op->result_opr();
1499 switch (op->bytecode()) {
1500 case Bytecodes::_i2l:
1501 #ifdef _LP64
1502 __ movl2ptr(dest->as_register_lo(), src->as_register());
1503 #else
1504 move_regs(src->as_register(), dest->as_register_lo());
1505 move_regs(src->as_register(), dest->as_register_hi());
1506 __ sarl(dest->as_register_hi(), 31);
1507 #endif // LP64
1508 break;
1510 case Bytecodes::_l2i:
1511 #ifdef _LP64
1512 __ movl(dest->as_register(), src->as_register_lo());
1513 #else
1514 move_regs(src->as_register_lo(), dest->as_register());
1515 #endif
1516 break;
1518 case Bytecodes::_i2b:
1519 move_regs(src->as_register(), dest->as_register());
1520 __ sign_extend_byte(dest->as_register());
1521 break;
1523 case Bytecodes::_i2c:
1524 move_regs(src->as_register(), dest->as_register());
1525 __ andl(dest->as_register(), 0xFFFF);
1526 break;
1528 case Bytecodes::_i2s:
1529 move_regs(src->as_register(), dest->as_register());
1530 __ sign_extend_short(dest->as_register());
1531 break;
1534 case Bytecodes::_f2d:
1535 case Bytecodes::_d2f:
1536 if (dest->is_single_xmm()) {
1537 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1538 } else if (dest->is_double_xmm()) {
1539 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1540 } else {
1541 assert(src->fpu() == dest->fpu(), "register must be equal");
1542 // do nothing (float result is rounded later through spilling)
1543 }
1544 break;
1546 case Bytecodes::_i2f:
1547 case Bytecodes::_i2d:
1548 if (dest->is_single_xmm()) {
1549 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1550 } else if (dest->is_double_xmm()) {
1551 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1552 } else {
1553 assert(dest->fpu() == 0, "result must be on TOS");
1554 __ movl(Address(rsp, 0), src->as_register());
1555 __ fild_s(Address(rsp, 0));
1556 }
1557 break;
1559 case Bytecodes::_f2i:
1560 case Bytecodes::_d2i:
1561 if (src->is_single_xmm()) {
1562 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1563 } else if (src->is_double_xmm()) {
1564 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1565 } else {
1566 assert(src->fpu() == 0, "input must be on TOS");
1567 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1568 __ fist_s(Address(rsp, 0));
1569 __ movl(dest->as_register(), Address(rsp, 0));
1570 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1571 }
1573 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1574 assert(op->stub() != NULL, "stub required");
1575 __ cmpl(dest->as_register(), 0x80000000);
1576 __ jcc(Assembler::equal, *op->stub()->entry());
1577 __ bind(*op->stub()->continuation());
1578 break;
1580 case Bytecodes::_l2f:
1581 case Bytecodes::_l2d:
1582 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1583 assert(dest->fpu() == 0, "result must be on TOS");
1585 __ movptr(Address(rsp, 0), src->as_register_lo());
1586 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1587 __ fild_d(Address(rsp, 0));
1588 // float result is rounded later through spilling
1589 break;
1591 case Bytecodes::_f2l:
1592 case Bytecodes::_d2l:
1593 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1594 assert(src->fpu() == 0, "input must be on TOS");
1595 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1597 // instruction sequence too long to inline it here
1598 {
1599 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1600 }
1601 break;
1603 default: ShouldNotReachHere();
1604 }
1605 }
1607 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1608 if (op->init_check()) {
1609 __ cmpb(Address(op->klass()->as_register(),
1610 InstanceKlass::init_state_offset()),
1611 InstanceKlass::fully_initialized);
1612 add_debug_info_for_null_check_here(op->stub()->info());
1613 __ jcc(Assembler::notEqual, *op->stub()->entry());
1614 }
1615 __ allocate_object(op->obj()->as_register(),
1616 op->tmp1()->as_register(),
1617 op->tmp2()->as_register(),
1618 op->header_size(),
1619 op->object_size(),
1620 op->klass()->as_register(),
1621 *op->stub()->entry());
1622 __ bind(*op->stub()->continuation());
1623 }
1625 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1626 Register len = op->len()->as_register();
1627 LP64_ONLY( __ movslq(len, len); )
1629 if (UseSlowPath ||
1630 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1631 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1632 __ jmp(*op->stub()->entry());
1633 } else {
1634 Register tmp1 = op->tmp1()->as_register();
1635 Register tmp2 = op->tmp2()->as_register();
1636 Register tmp3 = op->tmp3()->as_register();
1637 if (len == tmp1) {
1638 tmp1 = tmp3;
1639 } else if (len == tmp2) {
1640 tmp2 = tmp3;
1641 } else if (len == tmp3) {
1642 // everything is ok
1643 } else {
1644 __ mov(tmp3, len);
1645 }
1646 __ allocate_array(op->obj()->as_register(),
1647 len,
1648 tmp1,
1649 tmp2,
1650 arrayOopDesc::header_size(op->type()),
1651 array_element_size(op->type()),
1652 op->klass()->as_register(),
1653 *op->stub()->entry());
1654 }
1655 __ bind(*op->stub()->continuation());
1656 }
1658 void LIR_Assembler::type_profile_helper(Register mdo,
1659 ciMethodData *md, ciProfileData *data,
1660 Register recv, Label* update_done) {
1661 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1662 Label next_test;
1663 // See if the receiver is receiver[n].
1664 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1665 __ jccb(Assembler::notEqual, next_test);
1666 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1667 __ addptr(data_addr, DataLayout::counter_increment);
1668 __ jmp(*update_done);
1669 __ bind(next_test);
1670 }
1672 // Didn't find receiver; find next empty slot and fill it in
1673 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1674 Label next_test;
1675 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1676 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1677 __ jccb(Assembler::notEqual, next_test);
1678 __ movptr(recv_addr, recv);
1679 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1680 __ jmp(*update_done);
1681 __ bind(next_test);
1682 }
1683 }
1685 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1686 // we always need a stub for the failure case.
1687 CodeStub* stub = op->stub();
1688 Register obj = op->object()->as_register();
1689 Register k_RInfo = op->tmp1()->as_register();
1690 Register klass_RInfo = op->tmp2()->as_register();
1691 Register dst = op->result_opr()->as_register();
1692 ciKlass* k = op->klass();
1693 Register Rtmp1 = noreg;
1695 // check if it needs to be profiled
1696 ciMethodData* md;
1697 ciProfileData* data;
1699 if (op->should_profile()) {
1700 ciMethod* method = op->profiled_method();
1701 assert(method != NULL, "Should have method");
1702 int bci = op->profiled_bci();
1703 md = method->method_data_or_null();
1704 assert(md != NULL, "Sanity");
1705 data = md->bci_to_data(bci);
1706 assert(data != NULL, "need data for type check");
1707 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1708 }
1709 Label profile_cast_success, profile_cast_failure;
1710 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1711 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1713 if (obj == k_RInfo) {
1714 k_RInfo = dst;
1715 } else if (obj == klass_RInfo) {
1716 klass_RInfo = dst;
1717 }
1718 if (k->is_loaded() && !UseCompressedKlassPointers) {
1719 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1720 } else {
1721 Rtmp1 = op->tmp3()->as_register();
1722 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1723 }
1725 assert_different_registers(obj, k_RInfo, klass_RInfo);
1726 if (!k->is_loaded()) {
1727 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1728 } else {
1729 #ifdef _LP64
1730 __ mov_metadata(k_RInfo, k->constant_encoding());
1731 #endif // _LP64
1732 }
1733 assert(obj != k_RInfo, "must be different");
1735 __ cmpptr(obj, (int32_t)NULL_WORD);
1736 if (op->should_profile()) {
1737 Label not_null;
1738 __ jccb(Assembler::notEqual, not_null);
1739 // Object is null; update MDO and exit
1740 Register mdo = klass_RInfo;
1741 __ mov_metadata(mdo, md->constant_encoding());
1742 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1743 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1744 __ orl(data_addr, header_bits);
1745 __ jmp(*obj_is_null);
1746 __ bind(not_null);
1747 } else {
1748 __ jcc(Assembler::equal, *obj_is_null);
1749 }
1750 __ verify_oop(obj);
1752 if (op->fast_check()) {
1753 // get object class
1754 // not a safepoint as obj null check happens earlier
1755 #ifdef _LP64
1756 if (UseCompressedKlassPointers) {
1757 __ load_klass(Rtmp1, obj);
1758 __ cmpptr(k_RInfo, Rtmp1);
1759 } else {
1760 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1761 }
1762 #else
1763 if (k->is_loaded()) {
1764 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1765 } else {
1766 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1767 }
1768 #endif
1769 __ jcc(Assembler::notEqual, *failure_target);
1770 // successful cast, fall through to profile or jump
1771 } else {
1772 // get object class
1773 // not a safepoint as obj null check happens earlier
1774 __ load_klass(klass_RInfo, obj);
1775 if (k->is_loaded()) {
1776 // See if we get an immediate positive hit
1777 #ifdef _LP64
1778 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1779 #else
1780 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1781 #endif // _LP64
1782 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1783 __ jcc(Assembler::notEqual, *failure_target);
1784 // successful cast, fall through to profile or jump
1785 } else {
1786 // See if we get an immediate positive hit
1787 __ jcc(Assembler::equal, *success_target);
1788 // check for self
1789 #ifdef _LP64
1790 __ cmpptr(klass_RInfo, k_RInfo);
1791 #else
1792 __ cmpklass(klass_RInfo, k->constant_encoding());
1793 #endif // _LP64
1794 __ jcc(Assembler::equal, *success_target);
1796 __ push(klass_RInfo);
1797 #ifdef _LP64
1798 __ push(k_RInfo);
1799 #else
1800 __ pushklass(k->constant_encoding());
1801 #endif // _LP64
1802 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1803 __ pop(klass_RInfo);
1804 __ pop(klass_RInfo);
1805 // result is a boolean
1806 __ cmpl(klass_RInfo, 0);
1807 __ jcc(Assembler::equal, *failure_target);
1808 // successful cast, fall through to profile or jump
1809 }
1810 } else {
1811 // perform the fast part of the checking logic
1812 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1813 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1814 __ push(klass_RInfo);
1815 __ push(k_RInfo);
1816 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1817 __ pop(klass_RInfo);
1818 __ pop(k_RInfo);
1819 // result is a boolean
1820 __ cmpl(k_RInfo, 0);
1821 __ jcc(Assembler::equal, *failure_target);
1822 // successful cast, fall through to profile or jump
1823 }
1824 }
1825 if (op->should_profile()) {
1826 Register mdo = klass_RInfo, recv = k_RInfo;
1827 __ bind(profile_cast_success);
1828 __ mov_metadata(mdo, md->constant_encoding());
1829 __ load_klass(recv, obj);
1830 Label update_done;
1831 type_profile_helper(mdo, md, data, recv, success);
1832 __ jmp(*success);
1834 __ bind(profile_cast_failure);
1835 __ mov_metadata(mdo, md->constant_encoding());
1836 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1837 __ subptr(counter_addr, DataLayout::counter_increment);
1838 __ jmp(*failure);
1839 }
1840 __ jmp(*success);
1841 }
1844 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1845 LIR_Code code = op->code();
1846 if (code == lir_store_check) {
1847 Register value = op->object()->as_register();
1848 Register array = op->array()->as_register();
1849 Register k_RInfo = op->tmp1()->as_register();
1850 Register klass_RInfo = op->tmp2()->as_register();
1851 Register Rtmp1 = op->tmp3()->as_register();
1853 CodeStub* stub = op->stub();
1855 // check if it needs to be profiled
1856 ciMethodData* md;
1857 ciProfileData* data;
1859 if (op->should_profile()) {
1860 ciMethod* method = op->profiled_method();
1861 assert(method != NULL, "Should have method");
1862 int bci = op->profiled_bci();
1863 md = method->method_data_or_null();
1864 assert(md != NULL, "Sanity");
1865 data = md->bci_to_data(bci);
1866 assert(data != NULL, "need data for type check");
1867 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1868 }
1869 Label profile_cast_success, profile_cast_failure, done;
1870 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1871 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1873 __ cmpptr(value, (int32_t)NULL_WORD);
1874 if (op->should_profile()) {
1875 Label not_null;
1876 __ jccb(Assembler::notEqual, not_null);
1877 // Object is null; update MDO and exit
1878 Register mdo = klass_RInfo;
1879 __ mov_metadata(mdo, md->constant_encoding());
1880 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1881 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1882 __ orl(data_addr, header_bits);
1883 __ jmp(done);
1884 __ bind(not_null);
1885 } else {
1886 __ jcc(Assembler::equal, done);
1887 }
1889 add_debug_info_for_null_check_here(op->info_for_exception());
1890 __ load_klass(k_RInfo, array);
1891 __ load_klass(klass_RInfo, value);
1893 // get instance klass (it's already uncompressed)
1894 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1895 // perform the fast part of the checking logic
1896 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1897 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1898 __ push(klass_RInfo);
1899 __ push(k_RInfo);
1900 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1901 __ pop(klass_RInfo);
1902 __ pop(k_RInfo);
1903 // result is a boolean
1904 __ cmpl(k_RInfo, 0);
1905 __ jcc(Assembler::equal, *failure_target);
1906 // fall through to the success case
1908 if (op->should_profile()) {
1909 Register mdo = klass_RInfo, recv = k_RInfo;
1910 __ bind(profile_cast_success);
1911 __ mov_metadata(mdo, md->constant_encoding());
1912 __ load_klass(recv, value);
1913 Label update_done;
1914 type_profile_helper(mdo, md, data, recv, &done);
1915 __ jmpb(done);
1917 __ bind(profile_cast_failure);
1918 __ mov_metadata(mdo, md->constant_encoding());
1919 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1920 __ subptr(counter_addr, DataLayout::counter_increment);
1921 __ jmp(*stub->entry());
1922 }
1924 __ bind(done);
1925 } else
1926 if (code == lir_checkcast) {
1927 Register obj = op->object()->as_register();
1928 Register dst = op->result_opr()->as_register();
1929 Label success;
1930 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1931 __ bind(success);
1932 if (dst != obj) {
1933 __ mov(dst, obj);
1934 }
1935 } else
1936 if (code == lir_instanceof) {
1937 Register obj = op->object()->as_register();
1938 Register dst = op->result_opr()->as_register();
1939 Label success, failure, done;
1940 emit_typecheck_helper(op, &success, &failure, &failure);
1941 __ bind(failure);
1942 __ xorptr(dst, dst);
1943 __ jmpb(done);
1944 __ bind(success);
1945 __ movptr(dst, 1);
1946 __ bind(done);
1947 } else {
1948 ShouldNotReachHere();
1949 }
1951 }
1954 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1955 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1956 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1957 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1958 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1959 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1960 Register addr = op->addr()->as_register();
1961 if (os::is_MP()) {
1962 __ lock();
1963 }
1964 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1966 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1967 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1968 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1969 Register newval = op->new_value()->as_register();
1970 Register cmpval = op->cmp_value()->as_register();
1971 assert(cmpval == rax, "wrong register");
1972 assert(newval != NULL, "new val must be register");
1973 assert(cmpval != newval, "cmp and new values must be in different registers");
1974 assert(cmpval != addr, "cmp and addr must be in different registers");
1975 assert(newval != addr, "new value and addr must be in different registers");
1977 if ( op->code() == lir_cas_obj) {
1978 #ifdef _LP64
1979 if (UseCompressedOops) {
1980 __ encode_heap_oop(cmpval);
1981 __ mov(rscratch1, newval);
1982 __ encode_heap_oop(rscratch1);
1983 if (os::is_MP()) {
1984 __ lock();
1985 }
1986 // cmpval (rax) is implicitly used by this instruction
1987 __ cmpxchgl(rscratch1, Address(addr, 0));
1988 } else
1989 #endif
1990 {
1991 if (os::is_MP()) {
1992 __ lock();
1993 }
1994 __ cmpxchgptr(newval, Address(addr, 0));
1995 }
1996 } else {
1997 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1998 if (os::is_MP()) {
1999 __ lock();
2000 }
2001 __ cmpxchgl(newval, Address(addr, 0));
2002 }
2003 #ifdef _LP64
2004 } else if (op->code() == lir_cas_long) {
2005 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2006 Register newval = op->new_value()->as_register_lo();
2007 Register cmpval = op->cmp_value()->as_register_lo();
2008 assert(cmpval == rax, "wrong register");
2009 assert(newval != NULL, "new val must be register");
2010 assert(cmpval != newval, "cmp and new values must be in different registers");
2011 assert(cmpval != addr, "cmp and addr must be in different registers");
2012 assert(newval != addr, "new value and addr must be in different registers");
2013 if (os::is_MP()) {
2014 __ lock();
2015 }
2016 __ cmpxchgq(newval, Address(addr, 0));
2017 #endif // _LP64
2018 } else {
2019 Unimplemented();
2020 }
2021 }
2023 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2024 Assembler::Condition acond, ncond;
2025 switch (condition) {
2026 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2027 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2028 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2029 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2030 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2031 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2032 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2033 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2034 default: ShouldNotReachHere();
2035 }
2037 if (opr1->is_cpu_register()) {
2038 reg2reg(opr1, result);
2039 } else if (opr1->is_stack()) {
2040 stack2reg(opr1, result, result->type());
2041 } else if (opr1->is_constant()) {
2042 const2reg(opr1, result, lir_patch_none, NULL);
2043 } else {
2044 ShouldNotReachHere();
2045 }
2047 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2048 // optimized version that does not require a branch
2049 if (opr2->is_single_cpu()) {
2050 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2051 __ cmov(ncond, result->as_register(), opr2->as_register());
2052 } else if (opr2->is_double_cpu()) {
2053 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2054 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2055 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2056 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2057 } else if (opr2->is_single_stack()) {
2058 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2059 } else if (opr2->is_double_stack()) {
2060 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2061 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2062 } else {
2063 ShouldNotReachHere();
2064 }
2066 } else {
2067 Label skip;
2068 __ jcc (acond, skip);
2069 if (opr2->is_cpu_register()) {
2070 reg2reg(opr2, result);
2071 } else if (opr2->is_stack()) {
2072 stack2reg(opr2, result, result->type());
2073 } else if (opr2->is_constant()) {
2074 const2reg(opr2, result, lir_patch_none, NULL);
2075 } else {
2076 ShouldNotReachHere();
2077 }
2078 __ bind(skip);
2079 }
2080 }
2083 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2084 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2086 if (left->is_single_cpu()) {
2087 assert(left == dest, "left and dest must be equal");
2088 Register lreg = left->as_register();
2090 if (right->is_single_cpu()) {
2091 // cpu register - cpu register
2092 Register rreg = right->as_register();
2093 switch (code) {
2094 case lir_add: __ addl (lreg, rreg); break;
2095 case lir_sub: __ subl (lreg, rreg); break;
2096 case lir_mul: __ imull(lreg, rreg); break;
2097 default: ShouldNotReachHere();
2098 }
2100 } else if (right->is_stack()) {
2101 // cpu register - stack
2102 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2103 switch (code) {
2104 case lir_add: __ addl(lreg, raddr); break;
2105 case lir_sub: __ subl(lreg, raddr); break;
2106 default: ShouldNotReachHere();
2107 }
2109 } else if (right->is_constant()) {
2110 // cpu register - constant
2111 jint c = right->as_constant_ptr()->as_jint();
2112 switch (code) {
2113 case lir_add: {
2114 __ incrementl(lreg, c);
2115 break;
2116 }
2117 case lir_sub: {
2118 __ decrementl(lreg, c);
2119 break;
2120 }
2121 default: ShouldNotReachHere();
2122 }
2124 } else {
2125 ShouldNotReachHere();
2126 }
2128 } else if (left->is_double_cpu()) {
2129 assert(left == dest, "left and dest must be equal");
2130 Register lreg_lo = left->as_register_lo();
2131 Register lreg_hi = left->as_register_hi();
2133 if (right->is_double_cpu()) {
2134 // cpu register - cpu register
2135 Register rreg_lo = right->as_register_lo();
2136 Register rreg_hi = right->as_register_hi();
2137 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2138 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2139 switch (code) {
2140 case lir_add:
2141 __ addptr(lreg_lo, rreg_lo);
2142 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2143 break;
2144 case lir_sub:
2145 __ subptr(lreg_lo, rreg_lo);
2146 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2147 break;
2148 case lir_mul:
2149 #ifdef _LP64
2150 __ imulq(lreg_lo, rreg_lo);
2151 #else
2152 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2153 __ imull(lreg_hi, rreg_lo);
2154 __ imull(rreg_hi, lreg_lo);
2155 __ addl (rreg_hi, lreg_hi);
2156 __ mull (rreg_lo);
2157 __ addl (lreg_hi, rreg_hi);
2158 #endif // _LP64
2159 break;
2160 default:
2161 ShouldNotReachHere();
2162 }
2164 } else if (right->is_constant()) {
2165 // cpu register - constant
2166 #ifdef _LP64
2167 jlong c = right->as_constant_ptr()->as_jlong_bits();
2168 __ movptr(r10, (intptr_t) c);
2169 switch (code) {
2170 case lir_add:
2171 __ addptr(lreg_lo, r10);
2172 break;
2173 case lir_sub:
2174 __ subptr(lreg_lo, r10);
2175 break;
2176 default:
2177 ShouldNotReachHere();
2178 }
2179 #else
2180 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2181 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2182 switch (code) {
2183 case lir_add:
2184 __ addptr(lreg_lo, c_lo);
2185 __ adcl(lreg_hi, c_hi);
2186 break;
2187 case lir_sub:
2188 __ subptr(lreg_lo, c_lo);
2189 __ sbbl(lreg_hi, c_hi);
2190 break;
2191 default:
2192 ShouldNotReachHere();
2193 }
2194 #endif // _LP64
2196 } else {
2197 ShouldNotReachHere();
2198 }
2200 } else if (left->is_single_xmm()) {
2201 assert(left == dest, "left and dest must be equal");
2202 XMMRegister lreg = left->as_xmm_float_reg();
2204 if (right->is_single_xmm()) {
2205 XMMRegister rreg = right->as_xmm_float_reg();
2206 switch (code) {
2207 case lir_add: __ addss(lreg, rreg); break;
2208 case lir_sub: __ subss(lreg, rreg); break;
2209 case lir_mul_strictfp: // fall through
2210 case lir_mul: __ mulss(lreg, rreg); break;
2211 case lir_div_strictfp: // fall through
2212 case lir_div: __ divss(lreg, rreg); break;
2213 default: ShouldNotReachHere();
2214 }
2215 } else {
2216 Address raddr;
2217 if (right->is_single_stack()) {
2218 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2219 } else if (right->is_constant()) {
2220 // hack for now
2221 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2222 } else {
2223 ShouldNotReachHere();
2224 }
2225 switch (code) {
2226 case lir_add: __ addss(lreg, raddr); break;
2227 case lir_sub: __ subss(lreg, raddr); break;
2228 case lir_mul_strictfp: // fall through
2229 case lir_mul: __ mulss(lreg, raddr); break;
2230 case lir_div_strictfp: // fall through
2231 case lir_div: __ divss(lreg, raddr); break;
2232 default: ShouldNotReachHere();
2233 }
2234 }
2236 } else if (left->is_double_xmm()) {
2237 assert(left == dest, "left and dest must be equal");
2239 XMMRegister lreg = left->as_xmm_double_reg();
2240 if (right->is_double_xmm()) {
2241 XMMRegister rreg = right->as_xmm_double_reg();
2242 switch (code) {
2243 case lir_add: __ addsd(lreg, rreg); break;
2244 case lir_sub: __ subsd(lreg, rreg); break;
2245 case lir_mul_strictfp: // fall through
2246 case lir_mul: __ mulsd(lreg, rreg); break;
2247 case lir_div_strictfp: // fall through
2248 case lir_div: __ divsd(lreg, rreg); break;
2249 default: ShouldNotReachHere();
2250 }
2251 } else {
2252 Address raddr;
2253 if (right->is_double_stack()) {
2254 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2255 } else if (right->is_constant()) {
2256 // hack for now
2257 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2258 } else {
2259 ShouldNotReachHere();
2260 }
2261 switch (code) {
2262 case lir_add: __ addsd(lreg, raddr); break;
2263 case lir_sub: __ subsd(lreg, raddr); break;
2264 case lir_mul_strictfp: // fall through
2265 case lir_mul: __ mulsd(lreg, raddr); break;
2266 case lir_div_strictfp: // fall through
2267 case lir_div: __ divsd(lreg, raddr); break;
2268 default: ShouldNotReachHere();
2269 }
2270 }
2272 } else if (left->is_single_fpu()) {
2273 assert(dest->is_single_fpu(), "fpu stack allocation required");
2275 if (right->is_single_fpu()) {
2276 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2278 } else {
2279 assert(left->fpu_regnr() == 0, "left must be on TOS");
2280 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2282 Address raddr;
2283 if (right->is_single_stack()) {
2284 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2285 } else if (right->is_constant()) {
2286 address const_addr = float_constant(right->as_jfloat());
2287 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2288 // hack for now
2289 raddr = __ as_Address(InternalAddress(const_addr));
2290 } else {
2291 ShouldNotReachHere();
2292 }
2294 switch (code) {
2295 case lir_add: __ fadd_s(raddr); break;
2296 case lir_sub: __ fsub_s(raddr); break;
2297 case lir_mul_strictfp: // fall through
2298 case lir_mul: __ fmul_s(raddr); break;
2299 case lir_div_strictfp: // fall through
2300 case lir_div: __ fdiv_s(raddr); break;
2301 default: ShouldNotReachHere();
2302 }
2303 }
2305 } else if (left->is_double_fpu()) {
2306 assert(dest->is_double_fpu(), "fpu stack allocation required");
2308 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2309 // Double values require special handling for strictfp mul/div on x86
2310 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2311 __ fmulp(left->fpu_regnrLo() + 1);
2312 }
2314 if (right->is_double_fpu()) {
2315 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2317 } else {
2318 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2319 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2321 Address raddr;
2322 if (right->is_double_stack()) {
2323 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2324 } else if (right->is_constant()) {
2325 // hack for now
2326 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2327 } else {
2328 ShouldNotReachHere();
2329 }
2331 switch (code) {
2332 case lir_add: __ fadd_d(raddr); break;
2333 case lir_sub: __ fsub_d(raddr); break;
2334 case lir_mul_strictfp: // fall through
2335 case lir_mul: __ fmul_d(raddr); break;
2336 case lir_div_strictfp: // fall through
2337 case lir_div: __ fdiv_d(raddr); break;
2338 default: ShouldNotReachHere();
2339 }
2340 }
2342 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2343 // Double values require special handling for strictfp mul/div on x86
2344 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2345 __ fmulp(dest->fpu_regnrLo() + 1);
2346 }
2348 } else if (left->is_single_stack() || left->is_address()) {
2349 assert(left == dest, "left and dest must be equal");
2351 Address laddr;
2352 if (left->is_single_stack()) {
2353 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2354 } else if (left->is_address()) {
2355 laddr = as_Address(left->as_address_ptr());
2356 } else {
2357 ShouldNotReachHere();
2358 }
2360 if (right->is_single_cpu()) {
2361 Register rreg = right->as_register();
2362 switch (code) {
2363 case lir_add: __ addl(laddr, rreg); break;
2364 case lir_sub: __ subl(laddr, rreg); break;
2365 default: ShouldNotReachHere();
2366 }
2367 } else if (right->is_constant()) {
2368 jint c = right->as_constant_ptr()->as_jint();
2369 switch (code) {
2370 case lir_add: {
2371 __ incrementl(laddr, c);
2372 break;
2373 }
2374 case lir_sub: {
2375 __ decrementl(laddr, c);
2376 break;
2377 }
2378 default: ShouldNotReachHere();
2379 }
2380 } else {
2381 ShouldNotReachHere();
2382 }
2384 } else {
2385 ShouldNotReachHere();
2386 }
2387 }
2389 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2390 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2391 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2392 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2394 bool left_is_tos = (left_index == 0);
2395 bool dest_is_tos = (dest_index == 0);
2396 int non_tos_index = (left_is_tos ? right_index : left_index);
2398 switch (code) {
2399 case lir_add:
2400 if (pop_fpu_stack) __ faddp(non_tos_index);
2401 else if (dest_is_tos) __ fadd (non_tos_index);
2402 else __ fadda(non_tos_index);
2403 break;
2405 case lir_sub:
2406 if (left_is_tos) {
2407 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2408 else if (dest_is_tos) __ fsub (non_tos_index);
2409 else __ fsubra(non_tos_index);
2410 } else {
2411 if (pop_fpu_stack) __ fsubp (non_tos_index);
2412 else if (dest_is_tos) __ fsubr (non_tos_index);
2413 else __ fsuba (non_tos_index);
2414 }
2415 break;
2417 case lir_mul_strictfp: // fall through
2418 case lir_mul:
2419 if (pop_fpu_stack) __ fmulp(non_tos_index);
2420 else if (dest_is_tos) __ fmul (non_tos_index);
2421 else __ fmula(non_tos_index);
2422 break;
2424 case lir_div_strictfp: // fall through
2425 case lir_div:
2426 if (left_is_tos) {
2427 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2428 else if (dest_is_tos) __ fdiv (non_tos_index);
2429 else __ fdivra(non_tos_index);
2430 } else {
2431 if (pop_fpu_stack) __ fdivp (non_tos_index);
2432 else if (dest_is_tos) __ fdivr (non_tos_index);
2433 else __ fdiva (non_tos_index);
2434 }
2435 break;
2437 case lir_rem:
2438 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2439 __ fremr(noreg);
2440 break;
2442 default:
2443 ShouldNotReachHere();
2444 }
2445 }
2448 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2449 if (value->is_double_xmm()) {
2450 switch(code) {
2451 case lir_abs :
2452 {
2453 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2454 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2455 }
2456 __ andpd(dest->as_xmm_double_reg(),
2457 ExternalAddress((address)double_signmask_pool));
2458 }
2459 break;
2461 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2462 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2463 default : ShouldNotReachHere();
2464 }
2466 } else if (value->is_double_fpu()) {
2467 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2468 switch(code) {
2469 case lir_log : __ flog() ; break;
2470 case lir_log10 : __ flog10() ; break;
2471 case lir_abs : __ fabs() ; break;
2472 case lir_sqrt : __ fsqrt(); break;
2473 case lir_sin :
2474 // Should consider not saving rbx, if not necessary
2475 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2476 break;
2477 case lir_cos :
2478 // Should consider not saving rbx, if not necessary
2479 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2480 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2481 break;
2482 case lir_tan :
2483 // Should consider not saving rbx, if not necessary
2484 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2485 break;
2486 case lir_exp :
2487 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2488 break;
2489 case lir_pow :
2490 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2491 break;
2492 default : ShouldNotReachHere();
2493 }
2494 } else {
2495 Unimplemented();
2496 }
2497 }
2499 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2500 // assert(left->destroys_register(), "check");
2501 if (left->is_single_cpu()) {
2502 Register reg = left->as_register();
2503 if (right->is_constant()) {
2504 int val = right->as_constant_ptr()->as_jint();
2505 switch (code) {
2506 case lir_logic_and: __ andl (reg, val); break;
2507 case lir_logic_or: __ orl (reg, val); break;
2508 case lir_logic_xor: __ xorl (reg, val); break;
2509 default: ShouldNotReachHere();
2510 }
2511 } else if (right->is_stack()) {
2512 // added support for stack operands
2513 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2514 switch (code) {
2515 case lir_logic_and: __ andl (reg, raddr); break;
2516 case lir_logic_or: __ orl (reg, raddr); break;
2517 case lir_logic_xor: __ xorl (reg, raddr); break;
2518 default: ShouldNotReachHere();
2519 }
2520 } else {
2521 Register rright = right->as_register();
2522 switch (code) {
2523 case lir_logic_and: __ andptr (reg, rright); break;
2524 case lir_logic_or : __ orptr (reg, rright); break;
2525 case lir_logic_xor: __ xorptr (reg, rright); break;
2526 default: ShouldNotReachHere();
2527 }
2528 }
2529 move_regs(reg, dst->as_register());
2530 } else {
2531 Register l_lo = left->as_register_lo();
2532 Register l_hi = left->as_register_hi();
2533 if (right->is_constant()) {
2534 #ifdef _LP64
2535 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2536 switch (code) {
2537 case lir_logic_and:
2538 __ andq(l_lo, rscratch1);
2539 break;
2540 case lir_logic_or:
2541 __ orq(l_lo, rscratch1);
2542 break;
2543 case lir_logic_xor:
2544 __ xorq(l_lo, rscratch1);
2545 break;
2546 default: ShouldNotReachHere();
2547 }
2548 #else
2549 int r_lo = right->as_constant_ptr()->as_jint_lo();
2550 int r_hi = right->as_constant_ptr()->as_jint_hi();
2551 switch (code) {
2552 case lir_logic_and:
2553 __ andl(l_lo, r_lo);
2554 __ andl(l_hi, r_hi);
2555 break;
2556 case lir_logic_or:
2557 __ orl(l_lo, r_lo);
2558 __ orl(l_hi, r_hi);
2559 break;
2560 case lir_logic_xor:
2561 __ xorl(l_lo, r_lo);
2562 __ xorl(l_hi, r_hi);
2563 break;
2564 default: ShouldNotReachHere();
2565 }
2566 #endif // _LP64
2567 } else {
2568 #ifdef _LP64
2569 Register r_lo;
2570 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2571 r_lo = right->as_register();
2572 } else {
2573 r_lo = right->as_register_lo();
2574 }
2575 #else
2576 Register r_lo = right->as_register_lo();
2577 Register r_hi = right->as_register_hi();
2578 assert(l_lo != r_hi, "overwriting registers");
2579 #endif
2580 switch (code) {
2581 case lir_logic_and:
2582 __ andptr(l_lo, r_lo);
2583 NOT_LP64(__ andptr(l_hi, r_hi);)
2584 break;
2585 case lir_logic_or:
2586 __ orptr(l_lo, r_lo);
2587 NOT_LP64(__ orptr(l_hi, r_hi);)
2588 break;
2589 case lir_logic_xor:
2590 __ xorptr(l_lo, r_lo);
2591 NOT_LP64(__ xorptr(l_hi, r_hi);)
2592 break;
2593 default: ShouldNotReachHere();
2594 }
2595 }
2597 Register dst_lo = dst->as_register_lo();
2598 Register dst_hi = dst->as_register_hi();
2600 #ifdef _LP64
2601 move_regs(l_lo, dst_lo);
2602 #else
2603 if (dst_lo == l_hi) {
2604 assert(dst_hi != l_lo, "overwriting registers");
2605 move_regs(l_hi, dst_hi);
2606 move_regs(l_lo, dst_lo);
2607 } else {
2608 assert(dst_lo != l_hi, "overwriting registers");
2609 move_regs(l_lo, dst_lo);
2610 move_regs(l_hi, dst_hi);
2611 }
2612 #endif // _LP64
2613 }
2614 }
2617 // we assume that rax, and rdx can be overwritten
2618 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2620 assert(left->is_single_cpu(), "left must be register");
2621 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2622 assert(result->is_single_cpu(), "result must be register");
2624 // assert(left->destroys_register(), "check");
2625 // assert(right->destroys_register(), "check");
2627 Register lreg = left->as_register();
2628 Register dreg = result->as_register();
2630 if (right->is_constant()) {
2631 int divisor = right->as_constant_ptr()->as_jint();
2632 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2633 if (code == lir_idiv) {
2634 assert(lreg == rax, "must be rax,");
2635 assert(temp->as_register() == rdx, "tmp register must be rdx");
2636 __ cdql(); // sign extend into rdx:rax
2637 if (divisor == 2) {
2638 __ subl(lreg, rdx);
2639 } else {
2640 __ andl(rdx, divisor - 1);
2641 __ addl(lreg, rdx);
2642 }
2643 __ sarl(lreg, log2_intptr(divisor));
2644 move_regs(lreg, dreg);
2645 } else if (code == lir_irem) {
2646 Label done;
2647 __ mov(dreg, lreg);
2648 __ andl(dreg, 0x80000000 | (divisor - 1));
2649 __ jcc(Assembler::positive, done);
2650 __ decrement(dreg);
2651 __ orl(dreg, ~(divisor - 1));
2652 __ increment(dreg);
2653 __ bind(done);
2654 } else {
2655 ShouldNotReachHere();
2656 }
2657 } else {
2658 Register rreg = right->as_register();
2659 assert(lreg == rax, "left register must be rax,");
2660 assert(rreg != rdx, "right register must not be rdx");
2661 assert(temp->as_register() == rdx, "tmp register must be rdx");
2663 move_regs(lreg, rax);
2665 int idivl_offset = __ corrected_idivl(rreg);
2666 add_debug_info_for_div0(idivl_offset, info);
2667 if (code == lir_irem) {
2668 move_regs(rdx, dreg); // result is in rdx
2669 } else {
2670 move_regs(rax, dreg);
2671 }
2672 }
2673 }
2676 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2677 if (opr1->is_single_cpu()) {
2678 Register reg1 = opr1->as_register();
2679 if (opr2->is_single_cpu()) {
2680 // cpu register - cpu register
2681 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2682 __ cmpptr(reg1, opr2->as_register());
2683 } else {
2684 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2685 __ cmpl(reg1, opr2->as_register());
2686 }
2687 } else if (opr2->is_stack()) {
2688 // cpu register - stack
2689 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2690 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2691 } else {
2692 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2693 }
2694 } else if (opr2->is_constant()) {
2695 // cpu register - constant
2696 LIR_Const* c = opr2->as_constant_ptr();
2697 if (c->type() == T_INT) {
2698 __ cmpl(reg1, c->as_jint());
2699 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2700 // In 64bit oops are single register
2701 jobject o = c->as_jobject();
2702 if (o == NULL) {
2703 __ cmpptr(reg1, (int32_t)NULL_WORD);
2704 } else {
2705 #ifdef _LP64
2706 __ movoop(rscratch1, o);
2707 __ cmpptr(reg1, rscratch1);
2708 #else
2709 __ cmpoop(reg1, c->as_jobject());
2710 #endif // _LP64
2711 }
2712 } else {
2713 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2714 }
2715 // cpu register - address
2716 } else if (opr2->is_address()) {
2717 if (op->info() != NULL) {
2718 add_debug_info_for_null_check_here(op->info());
2719 }
2720 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2721 } else {
2722 ShouldNotReachHere();
2723 }
2725 } else if(opr1->is_double_cpu()) {
2726 Register xlo = opr1->as_register_lo();
2727 Register xhi = opr1->as_register_hi();
2728 if (opr2->is_double_cpu()) {
2729 #ifdef _LP64
2730 __ cmpptr(xlo, opr2->as_register_lo());
2731 #else
2732 // cpu register - cpu register
2733 Register ylo = opr2->as_register_lo();
2734 Register yhi = opr2->as_register_hi();
2735 __ subl(xlo, ylo);
2736 __ sbbl(xhi, yhi);
2737 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2738 __ orl(xhi, xlo);
2739 }
2740 #endif // _LP64
2741 } else if (opr2->is_constant()) {
2742 // cpu register - constant 0
2743 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2744 #ifdef _LP64
2745 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2746 #else
2747 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2748 __ orl(xhi, xlo);
2749 #endif // _LP64
2750 } else {
2751 ShouldNotReachHere();
2752 }
2754 } else if (opr1->is_single_xmm()) {
2755 XMMRegister reg1 = opr1->as_xmm_float_reg();
2756 if (opr2->is_single_xmm()) {
2757 // xmm register - xmm register
2758 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2759 } else if (opr2->is_stack()) {
2760 // xmm register - stack
2761 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2762 } else if (opr2->is_constant()) {
2763 // xmm register - constant
2764 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2765 } else if (opr2->is_address()) {
2766 // xmm register - address
2767 if (op->info() != NULL) {
2768 add_debug_info_for_null_check_here(op->info());
2769 }
2770 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2771 } else {
2772 ShouldNotReachHere();
2773 }
2775 } else if (opr1->is_double_xmm()) {
2776 XMMRegister reg1 = opr1->as_xmm_double_reg();
2777 if (opr2->is_double_xmm()) {
2778 // xmm register - xmm register
2779 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2780 } else if (opr2->is_stack()) {
2781 // xmm register - stack
2782 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2783 } else if (opr2->is_constant()) {
2784 // xmm register - constant
2785 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2786 } else if (opr2->is_address()) {
2787 // xmm register - address
2788 if (op->info() != NULL) {
2789 add_debug_info_for_null_check_here(op->info());
2790 }
2791 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2792 } else {
2793 ShouldNotReachHere();
2794 }
2796 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2797 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2798 assert(opr2->is_fpu_register(), "both must be registers");
2799 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2801 } else if (opr1->is_address() && opr2->is_constant()) {
2802 LIR_Const* c = opr2->as_constant_ptr();
2803 #ifdef _LP64
2804 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2805 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2806 __ movoop(rscratch1, c->as_jobject());
2807 }
2808 #endif // LP64
2809 if (op->info() != NULL) {
2810 add_debug_info_for_null_check_here(op->info());
2811 }
2812 // special case: address - constant
2813 LIR_Address* addr = opr1->as_address_ptr();
2814 if (c->type() == T_INT) {
2815 __ cmpl(as_Address(addr), c->as_jint());
2816 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2817 #ifdef _LP64
2818 // %%% Make this explode if addr isn't reachable until we figure out a
2819 // better strategy by giving noreg as the temp for as_Address
2820 __ cmpptr(rscratch1, as_Address(addr, noreg));
2821 #else
2822 __ cmpoop(as_Address(addr), c->as_jobject());
2823 #endif // _LP64
2824 } else {
2825 ShouldNotReachHere();
2826 }
2828 } else {
2829 ShouldNotReachHere();
2830 }
2831 }
2833 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2834 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2835 if (left->is_single_xmm()) {
2836 assert(right->is_single_xmm(), "must match");
2837 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2838 } else if (left->is_double_xmm()) {
2839 assert(right->is_double_xmm(), "must match");
2840 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2842 } else {
2843 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2844 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2846 assert(left->fpu() == 0, "left must be on TOS");
2847 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2848 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2849 }
2850 } else {
2851 assert(code == lir_cmp_l2i, "check");
2852 #ifdef _LP64
2853 Label done;
2854 Register dest = dst->as_register();
2855 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2856 __ movl(dest, -1);
2857 __ jccb(Assembler::less, done);
2858 __ set_byte_if_not_zero(dest);
2859 __ movzbl(dest, dest);
2860 __ bind(done);
2861 #else
2862 __ lcmp2int(left->as_register_hi(),
2863 left->as_register_lo(),
2864 right->as_register_hi(),
2865 right->as_register_lo());
2866 move_regs(left->as_register_hi(), dst->as_register());
2867 #endif // _LP64
2868 }
2869 }
2872 void LIR_Assembler::align_call(LIR_Code code) {
2873 if (os::is_MP()) {
2874 // make sure that the displacement word of the call ends up word aligned
2875 int offset = __ offset();
2876 switch (code) {
2877 case lir_static_call:
2878 case lir_optvirtual_call:
2879 case lir_dynamic_call:
2880 offset += NativeCall::displacement_offset;
2881 break;
2882 case lir_icvirtual_call:
2883 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2884 break;
2885 case lir_virtual_call: // currently, sparc-specific for niagara
2886 default: ShouldNotReachHere();
2887 }
2888 while (offset++ % BytesPerWord != 0) {
2889 __ nop();
2890 }
2891 }
2892 }
2895 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2896 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2897 "must be aligned");
2898 __ call(AddressLiteral(op->addr(), rtype));
2899 add_call_info(code_offset(), op->info());
2900 }
2903 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2904 __ ic_call(op->addr());
2905 add_call_info(code_offset(), op->info());
2906 assert(!os::is_MP() ||
2907 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2908 "must be aligned");
2909 }
2912 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2913 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2914 ShouldNotReachHere();
2915 }
2918 void LIR_Assembler::emit_static_call_stub() {
2919 address call_pc = __ pc();
2920 address stub = __ start_a_stub(call_stub_size);
2921 if (stub == NULL) {
2922 bailout("static call stub overflow");
2923 return;
2924 }
2926 int start = __ offset();
2927 if (os::is_MP()) {
2928 // make sure that the displacement word of the call ends up word aligned
2929 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2930 while (offset++ % BytesPerWord != 0) {
2931 __ nop();
2932 }
2933 }
2934 __ relocate(static_stub_Relocation::spec(call_pc));
2935 __ mov_metadata(rbx, (Metadata*)NULL);
2936 // must be set to -1 at code generation time
2937 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2938 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2939 __ jump(RuntimeAddress(__ pc()));
2941 assert(__ offset() - start <= call_stub_size, "stub too big");
2942 __ end_a_stub();
2943 }
2946 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2947 assert(exceptionOop->as_register() == rax, "must match");
2948 assert(exceptionPC->as_register() == rdx, "must match");
2950 // exception object is not added to oop map by LinearScan
2951 // (LinearScan assumes that no oops are in fixed registers)
2952 info->add_register_oop(exceptionOop);
2953 Runtime1::StubID unwind_id;
2955 // get current pc information
2956 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2957 int pc_for_athrow_offset = __ offset();
2958 InternalAddress pc_for_athrow(__ pc());
2959 __ lea(exceptionPC->as_register(), pc_for_athrow);
2960 add_call_info(pc_for_athrow_offset, info); // for exception handler
2962 __ verify_not_null_oop(rax);
2963 // search an exception handler (rax: exception oop, rdx: throwing pc)
2964 if (compilation()->has_fpu_code()) {
2965 unwind_id = Runtime1::handle_exception_id;
2966 } else {
2967 unwind_id = Runtime1::handle_exception_nofpu_id;
2968 }
2969 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2971 // enough room for two byte trap
2972 __ nop();
2973 }
2976 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2977 assert(exceptionOop->as_register() == rax, "must match");
2979 __ jmp(_unwind_handler_entry);
2980 }
2983 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2985 // optimized version for linear scan:
2986 // * count must be already in ECX (guaranteed by LinearScan)
2987 // * left and dest must be equal
2988 // * tmp must be unused
2989 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2990 assert(left == dest, "left and dest must be equal");
2991 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2993 if (left->is_single_cpu()) {
2994 Register value = left->as_register();
2995 assert(value != SHIFT_count, "left cannot be ECX");
2997 switch (code) {
2998 case lir_shl: __ shll(value); break;
2999 case lir_shr: __ sarl(value); break;
3000 case lir_ushr: __ shrl(value); break;
3001 default: ShouldNotReachHere();
3002 }
3003 } else if (left->is_double_cpu()) {
3004 Register lo = left->as_register_lo();
3005 Register hi = left->as_register_hi();
3006 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3007 #ifdef _LP64
3008 switch (code) {
3009 case lir_shl: __ shlptr(lo); break;
3010 case lir_shr: __ sarptr(lo); break;
3011 case lir_ushr: __ shrptr(lo); break;
3012 default: ShouldNotReachHere();
3013 }
3014 #else
3016 switch (code) {
3017 case lir_shl: __ lshl(hi, lo); break;
3018 case lir_shr: __ lshr(hi, lo, true); break;
3019 case lir_ushr: __ lshr(hi, lo, false); break;
3020 default: ShouldNotReachHere();
3021 }
3022 #endif // LP64
3023 } else {
3024 ShouldNotReachHere();
3025 }
3026 }
3029 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3030 if (dest->is_single_cpu()) {
3031 // first move left into dest so that left is not destroyed by the shift
3032 Register value = dest->as_register();
3033 count = count & 0x1F; // Java spec
3035 move_regs(left->as_register(), value);
3036 switch (code) {
3037 case lir_shl: __ shll(value, count); break;
3038 case lir_shr: __ sarl(value, count); break;
3039 case lir_ushr: __ shrl(value, count); break;
3040 default: ShouldNotReachHere();
3041 }
3042 } else if (dest->is_double_cpu()) {
3043 #ifndef _LP64
3044 Unimplemented();
3045 #else
3046 // first move left into dest so that left is not destroyed by the shift
3047 Register value = dest->as_register_lo();
3048 count = count & 0x1F; // Java spec
3050 move_regs(left->as_register_lo(), value);
3051 switch (code) {
3052 case lir_shl: __ shlptr(value, count); break;
3053 case lir_shr: __ sarptr(value, count); break;
3054 case lir_ushr: __ shrptr(value, count); break;
3055 default: ShouldNotReachHere();
3056 }
3057 #endif // _LP64
3058 } else {
3059 ShouldNotReachHere();
3060 }
3061 }
3064 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3065 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3066 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3067 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3068 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3069 }
3072 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3073 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3074 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3075 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3076 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3077 }
3080 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3081 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3082 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3083 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3084 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3085 }
3088 // This code replaces a call to arraycopy; no exception may
3089 // be thrown in this code, they must be thrown in the System.arraycopy
3090 // activation frame; we could save some checks if this would not be the case
3091 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3092 ciArrayKlass* default_type = op->expected_type();
3093 Register src = op->src()->as_register();
3094 Register dst = op->dst()->as_register();
3095 Register src_pos = op->src_pos()->as_register();
3096 Register dst_pos = op->dst_pos()->as_register();
3097 Register length = op->length()->as_register();
3098 Register tmp = op->tmp()->as_register();
3100 CodeStub* stub = op->stub();
3101 int flags = op->flags();
3102 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3103 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3105 // if we don't know anything, just go through the generic arraycopy
3106 if (default_type == NULL) {
3107 Label done;
3108 // save outgoing arguments on stack in case call to System.arraycopy is needed
3109 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3110 // for interpreter calling conventions. Now we have to do it in new style conventions.
3111 // For the moment until C1 gets the new register allocator I just force all the
3112 // args to the right place (except the register args) and then on the back side
3113 // reload the register args properly if we go slow path. Yuck
3115 // These are proper for the calling convention
3116 store_parameter(length, 2);
3117 store_parameter(dst_pos, 1);
3118 store_parameter(dst, 0);
3120 // these are just temporary placements until we need to reload
3121 store_parameter(src_pos, 3);
3122 store_parameter(src, 4);
3123 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3125 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3127 address copyfunc_addr = StubRoutines::generic_arraycopy();
3129 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3130 #ifdef _LP64
3131 // The arguments are in java calling convention so we can trivially shift them to C
3132 // convention
3133 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3134 __ mov(c_rarg0, j_rarg0);
3135 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3136 __ mov(c_rarg1, j_rarg1);
3137 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3138 __ mov(c_rarg2, j_rarg2);
3139 assert_different_registers(c_rarg3, j_rarg4);
3140 __ mov(c_rarg3, j_rarg3);
3141 #ifdef _WIN64
3142 // Allocate abi space for args but be sure to keep stack aligned
3143 __ subptr(rsp, 6*wordSize);
3144 store_parameter(j_rarg4, 4);
3145 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3146 __ call(RuntimeAddress(C_entry));
3147 } else {
3148 #ifndef PRODUCT
3149 if (PrintC1Statistics) {
3150 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3151 }
3152 #endif
3153 __ call(RuntimeAddress(copyfunc_addr));
3154 }
3155 __ addptr(rsp, 6*wordSize);
3156 #else
3157 __ mov(c_rarg4, j_rarg4);
3158 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3159 __ call(RuntimeAddress(C_entry));
3160 } else {
3161 #ifndef PRODUCT
3162 if (PrintC1Statistics) {
3163 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3164 }
3165 #endif
3166 __ call(RuntimeAddress(copyfunc_addr));
3167 }
3168 #endif // _WIN64
3169 #else
3170 __ push(length);
3171 __ push(dst_pos);
3172 __ push(dst);
3173 __ push(src_pos);
3174 __ push(src);
3176 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3177 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3178 } else {
3179 #ifndef PRODUCT
3180 if (PrintC1Statistics) {
3181 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3182 }
3183 #endif
3184 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3185 }
3187 #endif // _LP64
3189 __ cmpl(rax, 0);
3190 __ jcc(Assembler::equal, *stub->continuation());
3192 if (copyfunc_addr != NULL) {
3193 __ mov(tmp, rax);
3194 __ xorl(tmp, -1);
3195 }
3197 // Reload values from the stack so they are where the stub
3198 // expects them.
3199 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3200 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3201 __ movptr (length, Address(rsp, 2*BytesPerWord));
3202 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3203 __ movptr (src, Address(rsp, 4*BytesPerWord));
3205 if (copyfunc_addr != NULL) {
3206 __ subl(length, tmp);
3207 __ addl(src_pos, tmp);
3208 __ addl(dst_pos, tmp);
3209 }
3210 __ jmp(*stub->entry());
3212 __ bind(*stub->continuation());
3213 return;
3214 }
3216 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3218 int elem_size = type2aelembytes(basic_type);
3219 int shift_amount;
3220 Address::ScaleFactor scale;
3222 switch (elem_size) {
3223 case 1 :
3224 shift_amount = 0;
3225 scale = Address::times_1;
3226 break;
3227 case 2 :
3228 shift_amount = 1;
3229 scale = Address::times_2;
3230 break;
3231 case 4 :
3232 shift_amount = 2;
3233 scale = Address::times_4;
3234 break;
3235 case 8 :
3236 shift_amount = 3;
3237 scale = Address::times_8;
3238 break;
3239 default:
3240 ShouldNotReachHere();
3241 }
3243 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3244 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3245 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3246 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3248 // length and pos's are all sign extended at this point on 64bit
3250 // test for NULL
3251 if (flags & LIR_OpArrayCopy::src_null_check) {
3252 __ testptr(src, src);
3253 __ jcc(Assembler::zero, *stub->entry());
3254 }
3255 if (flags & LIR_OpArrayCopy::dst_null_check) {
3256 __ testptr(dst, dst);
3257 __ jcc(Assembler::zero, *stub->entry());
3258 }
3260 // check if negative
3261 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3262 __ testl(src_pos, src_pos);
3263 __ jcc(Assembler::less, *stub->entry());
3264 }
3265 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3266 __ testl(dst_pos, dst_pos);
3267 __ jcc(Assembler::less, *stub->entry());
3268 }
3270 if (flags & LIR_OpArrayCopy::src_range_check) {
3271 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3272 __ cmpl(tmp, src_length_addr);
3273 __ jcc(Assembler::above, *stub->entry());
3274 }
3275 if (flags & LIR_OpArrayCopy::dst_range_check) {
3276 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3277 __ cmpl(tmp, dst_length_addr);
3278 __ jcc(Assembler::above, *stub->entry());
3279 }
3281 if (flags & LIR_OpArrayCopy::length_positive_check) {
3282 __ testl(length, length);
3283 __ jcc(Assembler::less, *stub->entry());
3284 __ jcc(Assembler::zero, *stub->continuation());
3285 }
3287 #ifdef _LP64
3288 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3289 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3290 #endif
3292 if (flags & LIR_OpArrayCopy::type_check) {
3293 // We don't know the array types are compatible
3294 if (basic_type != T_OBJECT) {
3295 // Simple test for basic type arrays
3296 if (UseCompressedKlassPointers) {
3297 __ movl(tmp, src_klass_addr);
3298 __ cmpl(tmp, dst_klass_addr);
3299 } else {
3300 __ movptr(tmp, src_klass_addr);
3301 __ cmpptr(tmp, dst_klass_addr);
3302 }
3303 __ jcc(Assembler::notEqual, *stub->entry());
3304 } else {
3305 // For object arrays, if src is a sub class of dst then we can
3306 // safely do the copy.
3307 Label cont, slow;
3309 __ push(src);
3310 __ push(dst);
3312 __ load_klass(src, src);
3313 __ load_klass(dst, dst);
3315 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3317 __ push(src);
3318 __ push(dst);
3319 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3320 __ pop(dst);
3321 __ pop(src);
3323 __ cmpl(src, 0);
3324 __ jcc(Assembler::notEqual, cont);
3326 __ bind(slow);
3327 __ pop(dst);
3328 __ pop(src);
3330 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3331 if (copyfunc_addr != NULL) { // use stub if available
3332 // src is not a sub class of dst so we have to do a
3333 // per-element check.
3335 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3336 if ((flags & mask) != mask) {
3337 // Check that at least both of them object arrays.
3338 assert(flags & mask, "one of the two should be known to be an object array");
3340 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3341 __ load_klass(tmp, src);
3342 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3343 __ load_klass(tmp, dst);
3344 }
3345 int lh_offset = in_bytes(Klass::layout_helper_offset());
3346 Address klass_lh_addr(tmp, lh_offset);
3347 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3348 __ cmpl(klass_lh_addr, objArray_lh);
3349 __ jcc(Assembler::notEqual, *stub->entry());
3350 }
3352 // Spill because stubs can use any register they like and it's
3353 // easier to restore just those that we care about.
3354 store_parameter(dst, 0);
3355 store_parameter(dst_pos, 1);
3356 store_parameter(length, 2);
3357 store_parameter(src_pos, 3);
3358 store_parameter(src, 4);
3360 #ifndef _LP64
3361 __ movptr(tmp, dst_klass_addr);
3362 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3363 __ push(tmp);
3364 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3365 __ push(tmp);
3366 __ push(length);
3367 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3368 __ push(tmp);
3369 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3370 __ push(tmp);
3372 __ call_VM_leaf(copyfunc_addr, 5);
3373 #else
3374 __ movl2ptr(length, length); //higher 32bits must be null
3376 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3377 assert_different_registers(c_rarg0, dst, dst_pos, length);
3378 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3379 assert_different_registers(c_rarg1, dst, length);
3381 __ mov(c_rarg2, length);
3382 assert_different_registers(c_rarg2, dst);
3384 #ifdef _WIN64
3385 // Allocate abi space for args but be sure to keep stack aligned
3386 __ subptr(rsp, 6*wordSize);
3387 __ load_klass(c_rarg3, dst);
3388 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3389 store_parameter(c_rarg3, 4);
3390 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3391 __ call(RuntimeAddress(copyfunc_addr));
3392 __ addptr(rsp, 6*wordSize);
3393 #else
3394 __ load_klass(c_rarg4, dst);
3395 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3396 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3397 __ call(RuntimeAddress(copyfunc_addr));
3398 #endif
3400 #endif
3402 #ifndef PRODUCT
3403 if (PrintC1Statistics) {
3404 Label failed;
3405 __ testl(rax, rax);
3406 __ jcc(Assembler::notZero, failed);
3407 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3408 __ bind(failed);
3409 }
3410 #endif
3412 __ testl(rax, rax);
3413 __ jcc(Assembler::zero, *stub->continuation());
3415 #ifndef PRODUCT
3416 if (PrintC1Statistics) {
3417 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3418 }
3419 #endif
3421 __ mov(tmp, rax);
3423 __ xorl(tmp, -1);
3425 // Restore previously spilled arguments
3426 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3427 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3428 __ movptr (length, Address(rsp, 2*BytesPerWord));
3429 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3430 __ movptr (src, Address(rsp, 4*BytesPerWord));
3433 __ subl(length, tmp);
3434 __ addl(src_pos, tmp);
3435 __ addl(dst_pos, tmp);
3436 }
3438 __ jmp(*stub->entry());
3440 __ bind(cont);
3441 __ pop(dst);
3442 __ pop(src);
3443 }
3444 }
3446 #ifdef ASSERT
3447 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3448 // Sanity check the known type with the incoming class. For the
3449 // primitive case the types must match exactly with src.klass and
3450 // dst.klass each exactly matching the default type. For the
3451 // object array case, if no type check is needed then either the
3452 // dst type is exactly the expected type and the src type is a
3453 // subtype which we can't check or src is the same array as dst
3454 // but not necessarily exactly of type default_type.
3455 Label known_ok, halt;
3456 __ mov_metadata(tmp, default_type->constant_encoding());
3457 #ifdef _LP64
3458 if (UseCompressedKlassPointers) {
3459 __ encode_klass_not_null(tmp);
3460 }
3461 #endif
3463 if (basic_type != T_OBJECT) {
3465 if (UseCompressedKlassPointers) __ cmpl(tmp, dst_klass_addr);
3466 else __ cmpptr(tmp, dst_klass_addr);
3467 __ jcc(Assembler::notEqual, halt);
3468 if (UseCompressedKlassPointers) __ cmpl(tmp, src_klass_addr);
3469 else __ cmpptr(tmp, src_klass_addr);
3470 __ jcc(Assembler::equal, known_ok);
3471 } else {
3472 if (UseCompressedKlassPointers) __ cmpl(tmp, dst_klass_addr);
3473 else __ cmpptr(tmp, dst_klass_addr);
3474 __ jcc(Assembler::equal, known_ok);
3475 __ cmpptr(src, dst);
3476 __ jcc(Assembler::equal, known_ok);
3477 }
3478 __ bind(halt);
3479 __ stop("incorrect type information in arraycopy");
3480 __ bind(known_ok);
3481 }
3482 #endif
3484 #ifndef PRODUCT
3485 if (PrintC1Statistics) {
3486 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3487 }
3488 #endif
3490 #ifdef _LP64
3491 assert_different_registers(c_rarg0, dst, dst_pos, length);
3492 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3493 assert_different_registers(c_rarg1, length);
3494 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3495 __ mov(c_rarg2, length);
3497 #else
3498 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3499 store_parameter(tmp, 0);
3500 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3501 store_parameter(tmp, 1);
3502 store_parameter(length, 2);
3503 #endif // _LP64
3505 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3506 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3507 const char *name;
3508 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3509 __ call_VM_leaf(entry, 0);
3511 __ bind(*stub->continuation());
3512 }
3515 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3516 Register obj = op->obj_opr()->as_register(); // may not be an oop
3517 Register hdr = op->hdr_opr()->as_register();
3518 Register lock = op->lock_opr()->as_register();
3519 if (!UseFastLocking) {
3520 __ jmp(*op->stub()->entry());
3521 } else if (op->code() == lir_lock) {
3522 Register scratch = noreg;
3523 if (UseBiasedLocking) {
3524 scratch = op->scratch_opr()->as_register();
3525 }
3526 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3527 // add debug info for NullPointerException only if one is possible
3528 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3529 if (op->info() != NULL) {
3530 add_debug_info_for_null_check(null_check_offset, op->info());
3531 }
3532 // done
3533 } else if (op->code() == lir_unlock) {
3534 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3535 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3536 } else {
3537 Unimplemented();
3538 }
3539 __ bind(*op->stub()->continuation());
3540 }
3543 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3544 ciMethod* method = op->profiled_method();
3545 int bci = op->profiled_bci();
3546 ciMethod* callee = op->profiled_callee();
3548 // Update counter for all call types
3549 ciMethodData* md = method->method_data_or_null();
3550 assert(md != NULL, "Sanity");
3551 ciProfileData* data = md->bci_to_data(bci);
3552 assert(data->is_CounterData(), "need CounterData for calls");
3553 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3554 Register mdo = op->mdo()->as_register();
3555 __ mov_metadata(mdo, md->constant_encoding());
3556 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3557 Bytecodes::Code bc = method->java_code_at_bci(bci);
3558 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3559 // Perform additional virtual call profiling for invokevirtual and
3560 // invokeinterface bytecodes
3561 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3562 !callee_is_static && // required for optimized MH invokes
3563 C1ProfileVirtualCalls) {
3564 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3565 Register recv = op->recv()->as_register();
3566 assert_different_registers(mdo, recv);
3567 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3568 ciKlass* known_klass = op->known_holder();
3569 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3570 // We know the type that will be seen at this call site; we can
3571 // statically update the MethodData* rather than needing to do
3572 // dynamic tests on the receiver type
3574 // NOTE: we should probably put a lock around this search to
3575 // avoid collisions by concurrent compilations
3576 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3577 uint i;
3578 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3579 ciKlass* receiver = vc_data->receiver(i);
3580 if (known_klass->equals(receiver)) {
3581 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3582 __ addptr(data_addr, DataLayout::counter_increment);
3583 return;
3584 }
3585 }
3587 // Receiver type not found in profile data; select an empty slot
3589 // Note that this is less efficient than it should be because it
3590 // always does a write to the receiver part of the
3591 // VirtualCallData rather than just the first time
3592 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3593 ciKlass* receiver = vc_data->receiver(i);
3594 if (receiver == NULL) {
3595 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3596 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3597 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3598 __ addptr(data_addr, DataLayout::counter_increment);
3599 return;
3600 }
3601 }
3602 } else {
3603 __ load_klass(recv, recv);
3604 Label update_done;
3605 type_profile_helper(mdo, md, data, recv, &update_done);
3606 // Receiver did not match any saved receiver and there is no empty row for it.
3607 // Increment total counter to indicate polymorphic case.
3608 __ addptr(counter_addr, DataLayout::counter_increment);
3610 __ bind(update_done);
3611 }
3612 } else {
3613 // Static call
3614 __ addptr(counter_addr, DataLayout::counter_increment);
3615 }
3616 }
3618 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3619 Unimplemented();
3620 }
3623 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3624 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3625 }
3628 void LIR_Assembler::align_backward_branch_target() {
3629 __ align(BytesPerWord);
3630 }
3633 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3634 if (left->is_single_cpu()) {
3635 __ negl(left->as_register());
3636 move_regs(left->as_register(), dest->as_register());
3638 } else if (left->is_double_cpu()) {
3639 Register lo = left->as_register_lo();
3640 #ifdef _LP64
3641 Register dst = dest->as_register_lo();
3642 __ movptr(dst, lo);
3643 __ negptr(dst);
3644 #else
3645 Register hi = left->as_register_hi();
3646 __ lneg(hi, lo);
3647 if (dest->as_register_lo() == hi) {
3648 assert(dest->as_register_hi() != lo, "destroying register");
3649 move_regs(hi, dest->as_register_hi());
3650 move_regs(lo, dest->as_register_lo());
3651 } else {
3652 move_regs(lo, dest->as_register_lo());
3653 move_regs(hi, dest->as_register_hi());
3654 }
3655 #endif // _LP64
3657 } else if (dest->is_single_xmm()) {
3658 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3659 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3660 }
3661 __ xorps(dest->as_xmm_float_reg(),
3662 ExternalAddress((address)float_signflip_pool));
3664 } else if (dest->is_double_xmm()) {
3665 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3666 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3667 }
3668 __ xorpd(dest->as_xmm_double_reg(),
3669 ExternalAddress((address)double_signflip_pool));
3671 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3672 assert(left->fpu() == 0, "arg must be on TOS");
3673 assert(dest->fpu() == 0, "dest must be TOS");
3674 __ fchs();
3676 } else {
3677 ShouldNotReachHere();
3678 }
3679 }
3682 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3683 assert(addr->is_address() && dest->is_register(), "check");
3684 Register reg;
3685 reg = dest->as_pointer_register();
3686 __ lea(reg, as_Address(addr->as_address_ptr()));
3687 }
3691 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3692 assert(!tmp->is_valid(), "don't need temporary");
3693 __ call(RuntimeAddress(dest));
3694 if (info != NULL) {
3695 add_call_info_here(info);
3696 }
3697 }
3700 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3701 assert(type == T_LONG, "only for volatile long fields");
3703 if (info != NULL) {
3704 add_debug_info_for_null_check_here(info);
3705 }
3707 if (src->is_double_xmm()) {
3708 if (dest->is_double_cpu()) {
3709 #ifdef _LP64
3710 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3711 #else
3712 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3713 __ psrlq(src->as_xmm_double_reg(), 32);
3714 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3715 #endif // _LP64
3716 } else if (dest->is_double_stack()) {
3717 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3718 } else if (dest->is_address()) {
3719 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3720 } else {
3721 ShouldNotReachHere();
3722 }
3724 } else if (dest->is_double_xmm()) {
3725 if (src->is_double_stack()) {
3726 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3727 } else if (src->is_address()) {
3728 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3729 } else {
3730 ShouldNotReachHere();
3731 }
3733 } else if (src->is_double_fpu()) {
3734 assert(src->fpu_regnrLo() == 0, "must be TOS");
3735 if (dest->is_double_stack()) {
3736 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3737 } else if (dest->is_address()) {
3738 __ fistp_d(as_Address(dest->as_address_ptr()));
3739 } else {
3740 ShouldNotReachHere();
3741 }
3743 } else if (dest->is_double_fpu()) {
3744 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3745 if (src->is_double_stack()) {
3746 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3747 } else if (src->is_address()) {
3748 __ fild_d(as_Address(src->as_address_ptr()));
3749 } else {
3750 ShouldNotReachHere();
3751 }
3752 } else {
3753 ShouldNotReachHere();
3754 }
3755 }
3758 void LIR_Assembler::membar() {
3759 // QQQ sparc TSO uses this,
3760 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3761 }
3763 void LIR_Assembler::membar_acquire() {
3764 // No x86 machines currently require load fences
3765 // __ load_fence();
3766 }
3768 void LIR_Assembler::membar_release() {
3769 // No x86 machines currently require store fences
3770 // __ store_fence();
3771 }
3773 void LIR_Assembler::membar_loadload() {
3774 // no-op
3775 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3776 }
3778 void LIR_Assembler::membar_storestore() {
3779 // no-op
3780 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3781 }
3783 void LIR_Assembler::membar_loadstore() {
3784 // no-op
3785 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3786 }
3788 void LIR_Assembler::membar_storeload() {
3789 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3790 }
3792 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3793 assert(result_reg->is_register(), "check");
3794 #ifdef _LP64
3795 // __ get_thread(result_reg->as_register_lo());
3796 __ mov(result_reg->as_register(), r15_thread);
3797 #else
3798 __ get_thread(result_reg->as_register());
3799 #endif // _LP64
3800 }
3803 void LIR_Assembler::peephole(LIR_List*) {
3804 // do nothing for now
3805 }
3807 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3808 assert(data == dest, "xchg/xadd uses only 2 operands");
3810 if (data->type() == T_INT) {
3811 if (code == lir_xadd) {
3812 if (os::is_MP()) {
3813 __ lock();
3814 }
3815 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3816 } else {
3817 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3818 }
3819 } else if (data->is_oop()) {
3820 assert (code == lir_xchg, "xadd for oops");
3821 Register obj = data->as_register();
3822 #ifdef _LP64
3823 if (UseCompressedOops) {
3824 __ encode_heap_oop(obj);
3825 __ xchgl(obj, as_Address(src->as_address_ptr()));
3826 __ decode_heap_oop(obj);
3827 } else {
3828 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3829 }
3830 #else
3831 __ xchgl(obj, as_Address(src->as_address_ptr()));
3832 #endif
3833 } else if (data->type() == T_LONG) {
3834 #ifdef _LP64
3835 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3836 if (code == lir_xadd) {
3837 if (os::is_MP()) {
3838 __ lock();
3839 }
3840 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3841 } else {
3842 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3843 }
3844 #else
3845 ShouldNotReachHere();
3846 #endif
3847 } else {
3848 ShouldNotReachHere();
3849 }
3850 }
3852 #undef __
