Wed, 15 Jun 2016 14:21:31 -0700
Merge
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc_implementation/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
48 #ifdef PRODUCT
49 #define BLOCK_COMMENT(str) /* nothing */
50 #define STOP(error) stop(error)
51 #else
52 #define BLOCK_COMMENT(str) block_comment(str)
53 #define STOP(error) block_comment(error); stop(error)
54 #endif
56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
58 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
60 #ifdef ASSERT
61 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
62 #endif
64 static Assembler::Condition reverse[] = {
65 Assembler::noOverflow /* overflow = 0x0 */ ,
66 Assembler::overflow /* noOverflow = 0x1 */ ,
67 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
68 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
69 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
70 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
71 Assembler::above /* belowEqual = 0x6 */ ,
72 Assembler::belowEqual /* above = 0x7 */ ,
73 Assembler::positive /* negative = 0x8 */ ,
74 Assembler::negative /* positive = 0x9 */ ,
75 Assembler::noParity /* parity = 0xa */ ,
76 Assembler::parity /* noParity = 0xb */ ,
77 Assembler::greaterEqual /* less = 0xc */ ,
78 Assembler::less /* greaterEqual = 0xd */ ,
79 Assembler::greater /* lessEqual = 0xe */ ,
80 Assembler::lessEqual /* greater = 0xf, */
82 };
85 // Implementation of MacroAssembler
87 // First all the versions that have distinct versions depending on 32/64 bit
88 // Unless the difference is trivial (1 line or so).
90 #ifndef _LP64
92 // 32bit versions
94 Address MacroAssembler::as_Address(AddressLiteral adr) {
95 return Address(adr.target(), adr.rspec());
96 }
98 Address MacroAssembler::as_Address(ArrayAddress adr) {
99 return Address::make_array(adr);
100 }
102 void MacroAssembler::call_VM_leaf_base(address entry_point,
103 int number_of_arguments) {
104 call(RuntimeAddress(entry_point));
105 increment(rsp, number_of_arguments * wordSize);
106 }
108 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
109 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
110 }
112 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
116 void MacroAssembler::cmpoop(Address src1, jobject obj) {
117 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
118 }
120 void MacroAssembler::cmpoop(Register src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
124 void MacroAssembler::extend_sign(Register hi, Register lo) {
125 // According to Intel Doc. AP-526, "Integer Divide", p.18.
126 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
127 cdql();
128 } else {
129 movl(hi, lo);
130 sarl(hi, 31);
131 }
132 }
134 void MacroAssembler::jC2(Register tmp, Label& L) {
135 // set parity bit if FPU flag C2 is set (via rax)
136 save_rax(tmp);
137 fwait(); fnstsw_ax();
138 sahf();
139 restore_rax(tmp);
140 // branch
141 jcc(Assembler::parity, L);
142 }
144 void MacroAssembler::jnC2(Register tmp, Label& L) {
145 // set parity bit if FPU flag C2 is set (via rax)
146 save_rax(tmp);
147 fwait(); fnstsw_ax();
148 sahf();
149 restore_rax(tmp);
150 // branch
151 jcc(Assembler::noParity, L);
152 }
154 // 32bit can do a case table jump in one instruction but we no longer allow the base
155 // to be installed in the Address class
156 void MacroAssembler::jump(ArrayAddress entry) {
157 jmp(as_Address(entry));
158 }
160 // Note: y_lo will be destroyed
161 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
162 // Long compare for Java (semantics as described in JVM spec.)
163 Label high, low, done;
165 cmpl(x_hi, y_hi);
166 jcc(Assembler::less, low);
167 jcc(Assembler::greater, high);
168 // x_hi is the return register
169 xorl(x_hi, x_hi);
170 cmpl(x_lo, y_lo);
171 jcc(Assembler::below, low);
172 jcc(Assembler::equal, done);
174 bind(high);
175 xorl(x_hi, x_hi);
176 increment(x_hi);
177 jmp(done);
179 bind(low);
180 xorl(x_hi, x_hi);
181 decrementl(x_hi);
183 bind(done);
184 }
186 void MacroAssembler::lea(Register dst, AddressLiteral src) {
187 mov_literal32(dst, (int32_t)src.target(), src.rspec());
188 }
190 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
191 // leal(dst, as_Address(adr));
192 // see note in movl as to why we must use a move
193 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
194 }
196 void MacroAssembler::leave() {
197 mov(rsp, rbp);
198 pop(rbp);
199 }
201 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
202 // Multiplication of two Java long values stored on the stack
203 // as illustrated below. Result is in rdx:rax.
204 //
205 // rsp ---> [ ?? ] \ \
206 // .... | y_rsp_offset |
207 // [ y_lo ] / (in bytes) | x_rsp_offset
208 // [ y_hi ] | (in bytes)
209 // .... |
210 // [ x_lo ] /
211 // [ x_hi ]
212 // ....
213 //
214 // Basic idea: lo(result) = lo(x_lo * y_lo)
215 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
216 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
217 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
218 Label quick;
219 // load x_hi, y_hi and check if quick
220 // multiplication is possible
221 movl(rbx, x_hi);
222 movl(rcx, y_hi);
223 movl(rax, rbx);
224 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
225 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
226 // do full multiplication
227 // 1st step
228 mull(y_lo); // x_hi * y_lo
229 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
230 // 2nd step
231 movl(rax, x_lo);
232 mull(rcx); // x_lo * y_hi
233 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
234 // 3rd step
235 bind(quick); // note: rbx, = 0 if quick multiply!
236 movl(rax, x_lo);
237 mull(y_lo); // x_lo * y_lo
238 addl(rdx, rbx); // correct hi(x_lo * y_lo)
239 }
241 void MacroAssembler::lneg(Register hi, Register lo) {
242 negl(lo);
243 adcl(hi, 0);
244 negl(hi);
245 }
247 void MacroAssembler::lshl(Register hi, Register lo) {
248 // Java shift left long support (semantics as described in JVM spec., p.305)
249 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
250 // shift value is in rcx !
251 assert(hi != rcx, "must not use rcx");
252 assert(lo != rcx, "must not use rcx");
253 const Register s = rcx; // shift count
254 const int n = BitsPerWord;
255 Label L;
256 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
257 cmpl(s, n); // if (s < n)
258 jcc(Assembler::less, L); // else (s >= n)
259 movl(hi, lo); // x := x << n
260 xorl(lo, lo);
261 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
262 bind(L); // s (mod n) < n
263 shldl(hi, lo); // x := x << s
264 shll(lo);
265 }
268 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
269 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
270 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
271 assert(hi != rcx, "must not use rcx");
272 assert(lo != rcx, "must not use rcx");
273 const Register s = rcx; // shift count
274 const int n = BitsPerWord;
275 Label L;
276 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
277 cmpl(s, n); // if (s < n)
278 jcc(Assembler::less, L); // else (s >= n)
279 movl(lo, hi); // x := x >> n
280 if (sign_extension) sarl(hi, 31);
281 else xorl(hi, hi);
282 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
283 bind(L); // s (mod n) < n
284 shrdl(lo, hi); // x := x >> s
285 if (sign_extension) sarl(hi);
286 else shrl(hi);
287 }
289 void MacroAssembler::movoop(Register dst, jobject obj) {
290 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
291 }
293 void MacroAssembler::movoop(Address dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
297 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
298 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
299 }
301 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
305 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
306 // scratch register is not used,
307 // it is defined to match parameters of 64-bit version of this method.
308 if (src.is_lval()) {
309 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
310 } else {
311 movl(dst, as_Address(src));
312 }
313 }
315 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
316 movl(as_Address(dst), src);
317 }
319 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
320 movl(dst, as_Address(src));
321 }
323 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
324 void MacroAssembler::movptr(Address dst, intptr_t src) {
325 movl(dst, src);
326 }
329 void MacroAssembler::pop_callee_saved_registers() {
330 pop(rcx);
331 pop(rdx);
332 pop(rdi);
333 pop(rsi);
334 }
336 void MacroAssembler::pop_fTOS() {
337 fld_d(Address(rsp, 0));
338 addl(rsp, 2 * wordSize);
339 }
341 void MacroAssembler::push_callee_saved_registers() {
342 push(rsi);
343 push(rdi);
344 push(rdx);
345 push(rcx);
346 }
348 void MacroAssembler::push_fTOS() {
349 subl(rsp, 2 * wordSize);
350 fstp_d(Address(rsp, 0));
351 }
354 void MacroAssembler::pushoop(jobject obj) {
355 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
356 }
358 void MacroAssembler::pushklass(Metadata* obj) {
359 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
360 }
362 void MacroAssembler::pushptr(AddressLiteral src) {
363 if (src.is_lval()) {
364 push_literal32((int32_t)src.target(), src.rspec());
365 } else {
366 pushl(as_Address(src));
367 }
368 }
370 void MacroAssembler::set_word_if_not_zero(Register dst) {
371 xorl(dst, dst);
372 set_byte_if_not_zero(dst);
373 }
375 static void pass_arg0(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
379 static void pass_arg1(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
383 static void pass_arg2(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
387 static void pass_arg3(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
391 #ifndef PRODUCT
392 extern "C" void findpc(intptr_t x);
393 #endif
395 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
396 // In order to get locks to work, we need to fake a in_VM state
397 JavaThread* thread = JavaThread::current();
398 JavaThreadState saved_state = thread->thread_state();
399 thread->set_thread_state(_thread_in_vm);
400 if (ShowMessageBoxOnError) {
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
405 ttyLocker ttyl;
406 BytecodeCounter::print();
407 }
408 // To see where a verify_oop failed, get $ebx+40/X for this frame.
409 // This is the value of eip which points to where verify_oop will return.
410 if (os::message_box(msg, "Execution stopped, print registers?")) {
411 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
412 BREAKPOINT;
413 }
414 } else {
415 ttyLocker ttyl;
416 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
417 }
418 // Don't assert holding the ttyLock
419 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
420 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
421 }
423 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
424 ttyLocker ttyl;
425 FlagSetting fs(Debugging, true);
426 tty->print_cr("eip = 0x%08x", eip);
427 #ifndef PRODUCT
428 if ((WizardMode || Verbose) && PrintMiscellaneous) {
429 tty->cr();
430 findpc(eip);
431 tty->cr();
432 }
433 #endif
434 #define PRINT_REG(rax) \
435 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
436 PRINT_REG(rax);
437 PRINT_REG(rbx);
438 PRINT_REG(rcx);
439 PRINT_REG(rdx);
440 PRINT_REG(rdi);
441 PRINT_REG(rsi);
442 PRINT_REG(rbp);
443 PRINT_REG(rsp);
444 #undef PRINT_REG
445 // Print some words near top of staack.
446 int* dump_sp = (int*) rsp;
447 for (int col1 = 0; col1 < 8; col1++) {
448 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
449 os::print_location(tty, *dump_sp++);
450 }
451 for (int row = 0; row < 16; row++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 for (int col = 0; col < 8; col++) {
454 tty->print(" 0x%08x", *dump_sp++);
455 }
456 tty->cr();
457 }
458 // Print some instructions around pc:
459 Disassembler::decode((address)eip-64, (address)eip);
460 tty->print_cr("--------");
461 Disassembler::decode((address)eip, (address)eip+32);
462 }
464 void MacroAssembler::stop(const char* msg) {
465 ExternalAddress message((address)msg);
466 // push address of message
467 pushptr(message.addr());
468 { Label L; call(L, relocInfo::none); bind(L); } // push eip
469 pusha(); // push registers
470 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
471 hlt();
472 }
474 void MacroAssembler::warn(const char* msg) {
475 push_CPU_state();
477 ExternalAddress message((address) msg);
478 // push address of message
479 pushptr(message.addr());
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
482 addl(rsp, wordSize); // discard argument
483 pop_CPU_state();
484 }
486 void MacroAssembler::print_state() {
487 { Label L; call(L, relocInfo::none); bind(L); } // push eip
488 pusha(); // push registers
490 push_CPU_state();
491 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
492 pop_CPU_state();
494 popa();
495 addl(rsp, wordSize);
496 }
498 #else // _LP64
500 // 64 bit versions
502 Address MacroAssembler::as_Address(AddressLiteral adr) {
503 // amd64 always does this as a pc-rel
504 // we can be absolute or disp based on the instruction type
505 // jmp/call are displacements others are absolute
506 assert(!adr.is_lval(), "must be rval");
507 assert(reachable(adr), "must be");
508 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
510 }
512 Address MacroAssembler::as_Address(ArrayAddress adr) {
513 AddressLiteral base = adr.base();
514 lea(rscratch1, base);
515 Address index = adr.index();
516 assert(index._disp == 0, "must not have disp"); // maybe it can?
517 Address array(rscratch1, index._index, index._scale, index._disp);
518 return array;
519 }
521 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
522 Label L, E;
524 #ifdef _WIN64
525 // Windows always allocates space for it's register args
526 assert(num_args <= 4, "only register arguments supported");
527 subq(rsp, frame::arg_reg_save_area_bytes);
528 #endif
530 // Align stack if necessary
531 testl(rsp, 15);
532 jcc(Assembler::zero, L);
534 subq(rsp, 8);
535 {
536 call(RuntimeAddress(entry_point));
537 }
538 addq(rsp, 8);
539 jmp(E);
541 bind(L);
542 {
543 call(RuntimeAddress(entry_point));
544 }
546 bind(E);
548 #ifdef _WIN64
549 // restore stack pointer
550 addq(rsp, frame::arg_reg_save_area_bytes);
551 #endif
553 }
555 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
556 assert(!src2.is_lval(), "should use cmpptr");
558 if (reachable(src2)) {
559 cmpq(src1, as_Address(src2));
560 } else {
561 lea(rscratch1, src2);
562 Assembler::cmpq(src1, Address(rscratch1, 0));
563 }
564 }
566 int MacroAssembler::corrected_idivq(Register reg) {
567 // Full implementation of Java ldiv and lrem; checks for special
568 // case as described in JVM spec., p.243 & p.271. The function
569 // returns the (pc) offset of the idivl instruction - may be needed
570 // for implicit exceptions.
571 //
572 // normal case special case
573 //
574 // input : rax: dividend min_long
575 // reg: divisor (may not be eax/edx) -1
576 //
577 // output: rax: quotient (= rax idiv reg) min_long
578 // rdx: remainder (= rax irem reg) 0
579 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
580 static const int64_t min_long = 0x8000000000000000;
581 Label normal_case, special_case;
583 // check for special case
584 cmp64(rax, ExternalAddress((address) &min_long));
585 jcc(Assembler::notEqual, normal_case);
586 xorl(rdx, rdx); // prepare rdx for possible special case (where
587 // remainder = 0)
588 cmpq(reg, -1);
589 jcc(Assembler::equal, special_case);
591 // handle normal case
592 bind(normal_case);
593 cdqq();
594 int idivq_offset = offset();
595 idivq(reg);
597 // normal and special case exit
598 bind(special_case);
600 return idivq_offset;
601 }
603 void MacroAssembler::decrementq(Register reg, int value) {
604 if (value == min_jint) { subq(reg, value); return; }
605 if (value < 0) { incrementq(reg, -value); return; }
606 if (value == 0) { ; return; }
607 if (value == 1 && UseIncDec) { decq(reg) ; return; }
608 /* else */ { subq(reg, value) ; return; }
609 }
611 void MacroAssembler::decrementq(Address dst, int value) {
612 if (value == min_jint) { subq(dst, value); return; }
613 if (value < 0) { incrementq(dst, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { decq(dst) ; return; }
616 /* else */ { subq(dst, value) ; return; }
617 }
619 void MacroAssembler::incrementq(AddressLiteral dst) {
620 if (reachable(dst)) {
621 incrementq(as_Address(dst));
622 } else {
623 lea(rscratch1, dst);
624 incrementq(Address(rscratch1, 0));
625 }
626 }
628 void MacroAssembler::incrementq(Register reg, int value) {
629 if (value == min_jint) { addq(reg, value); return; }
630 if (value < 0) { decrementq(reg, -value); return; }
631 if (value == 0) { ; return; }
632 if (value == 1 && UseIncDec) { incq(reg) ; return; }
633 /* else */ { addq(reg, value) ; return; }
634 }
636 void MacroAssembler::incrementq(Address dst, int value) {
637 if (value == min_jint) { addq(dst, value); return; }
638 if (value < 0) { decrementq(dst, -value); return; }
639 if (value == 0) { ; return; }
640 if (value == 1 && UseIncDec) { incq(dst) ; return; }
641 /* else */ { addq(dst, value) ; return; }
642 }
644 // 32bit can do a case table jump in one instruction but we no longer allow the base
645 // to be installed in the Address class
646 void MacroAssembler::jump(ArrayAddress entry) {
647 lea(rscratch1, entry.base());
648 Address dispatch = entry.index();
649 assert(dispatch._base == noreg, "must be");
650 dispatch._base = rscratch1;
651 jmp(dispatch);
652 }
654 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 cmpq(x_lo, y_lo);
657 }
659 void MacroAssembler::lea(Register dst, AddressLiteral src) {
660 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
661 }
663 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
664 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
665 movptr(dst, rscratch1);
666 }
668 void MacroAssembler::leave() {
669 // %%% is this really better? Why not on 32bit too?
670 emit_int8((unsigned char)0xC9); // LEAVE
671 }
673 void MacroAssembler::lneg(Register hi, Register lo) {
674 ShouldNotReachHere(); // 64bit doesn't use two regs
675 negq(lo);
676 }
678 void MacroAssembler::movoop(Register dst, jobject obj) {
679 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
680 }
682 void MacroAssembler::movoop(Address dst, jobject obj) {
683 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 movq(dst, rscratch1);
685 }
687 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
688 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
689 }
691 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
692 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 movq(dst, rscratch1);
694 }
696 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
697 if (src.is_lval()) {
698 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
699 } else {
700 if (reachable(src)) {
701 movq(dst, as_Address(src));
702 } else {
703 lea(scratch, src);
704 movq(dst, Address(scratch, 0));
705 }
706 }
707 }
709 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
710 movq(as_Address(dst), src);
711 }
713 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
714 movq(dst, as_Address(src));
715 }
717 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
718 void MacroAssembler::movptr(Address dst, intptr_t src) {
719 mov64(rscratch1, src);
720 movq(dst, rscratch1);
721 }
723 // These are mostly for initializing NULL
724 void MacroAssembler::movptr(Address dst, int32_t src) {
725 movslq(dst, src);
726 }
728 void MacroAssembler::movptr(Register dst, int32_t src) {
729 mov64(dst, (intptr_t)src);
730 }
732 void MacroAssembler::pushoop(jobject obj) {
733 movoop(rscratch1, obj);
734 push(rscratch1);
735 }
737 void MacroAssembler::pushklass(Metadata* obj) {
738 mov_metadata(rscratch1, obj);
739 push(rscratch1);
740 }
742 void MacroAssembler::pushptr(AddressLiteral src) {
743 lea(rscratch1, src);
744 if (src.is_lval()) {
745 push(rscratch1);
746 } else {
747 pushq(Address(rscratch1, 0));
748 }
749 }
751 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
752 bool clear_pc) {
753 // we must set sp to zero to clear frame
754 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
755 // must clear fp, so that compiled frames are not confused; it is
756 // possible that we need it only for debugging
757 if (clear_fp) {
758 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
759 }
761 if (clear_pc) {
762 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
763 }
764 }
766 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
767 Register last_java_fp,
768 address last_java_pc) {
769 // determine last_java_sp register
770 if (!last_java_sp->is_valid()) {
771 last_java_sp = rsp;
772 }
774 // last_java_fp is optional
775 if (last_java_fp->is_valid()) {
776 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
777 last_java_fp);
778 }
780 // last_java_pc is optional
781 if (last_java_pc != NULL) {
782 Address java_pc(r15_thread,
783 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
784 lea(rscratch1, InternalAddress(last_java_pc));
785 movptr(java_pc, rscratch1);
786 }
788 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
789 }
791 static void pass_arg0(MacroAssembler* masm, Register arg) {
792 if (c_rarg0 != arg ) {
793 masm->mov(c_rarg0, arg);
794 }
795 }
797 static void pass_arg1(MacroAssembler* masm, Register arg) {
798 if (c_rarg1 != arg ) {
799 masm->mov(c_rarg1, arg);
800 }
801 }
803 static void pass_arg2(MacroAssembler* masm, Register arg) {
804 if (c_rarg2 != arg ) {
805 masm->mov(c_rarg2, arg);
806 }
807 }
809 static void pass_arg3(MacroAssembler* masm, Register arg) {
810 if (c_rarg3 != arg ) {
811 masm->mov(c_rarg3, arg);
812 }
813 }
815 void MacroAssembler::stop(const char* msg) {
816 address rip = pc();
817 pusha(); // get regs on stack
818 lea(c_rarg0, ExternalAddress((address) msg));
819 lea(c_rarg1, InternalAddress(rip));
820 movq(c_rarg2, rsp); // pass pointer to regs array
821 andq(rsp, -16); // align stack as required by ABI
822 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
823 hlt();
824 }
826 void MacroAssembler::warn(const char* msg) {
827 push(rbp);
828 movq(rbp, rsp);
829 andq(rsp, -16); // align stack as required by push_CPU_state and call
830 push_CPU_state(); // keeps alignment at 16 bytes
831 lea(c_rarg0, ExternalAddress((address) msg));
832 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
833 pop_CPU_state();
834 mov(rsp, rbp);
835 pop(rbp);
836 }
838 void MacroAssembler::print_state() {
839 address rip = pc();
840 pusha(); // get regs on stack
841 push(rbp);
842 movq(rbp, rsp);
843 andq(rsp, -16); // align stack as required by push_CPU_state and call
844 push_CPU_state(); // keeps alignment at 16 bytes
846 lea(c_rarg0, InternalAddress(rip));
847 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
848 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
850 pop_CPU_state();
851 mov(rsp, rbp);
852 pop(rbp);
853 popa();
854 }
856 #ifndef PRODUCT
857 extern "C" void findpc(intptr_t x);
858 #endif
860 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
861 // In order to get locks to work, we need to fake a in_VM state
862 if (ShowMessageBoxOnError) {
863 JavaThread* thread = JavaThread::current();
864 JavaThreadState saved_state = thread->thread_state();
865 thread->set_thread_state(_thread_in_vm);
866 #ifndef PRODUCT
867 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
868 ttyLocker ttyl;
869 BytecodeCounter::print();
870 }
871 #endif
872 // To see where a verify_oop failed, get $ebx+40/X for this frame.
873 // XXX correct this offset for amd64
874 // This is the value of eip which points to where verify_oop will return.
875 if (os::message_box(msg, "Execution stopped, print registers?")) {
876 print_state64(pc, regs);
877 BREAKPOINT;
878 assert(false, "start up GDB");
879 }
880 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
881 } else {
882 ttyLocker ttyl;
883 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
884 msg);
885 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
886 }
887 }
889 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
890 ttyLocker ttyl;
891 FlagSetting fs(Debugging, true);
892 tty->print_cr("rip = 0x%016lx", pc);
893 #ifndef PRODUCT
894 tty->cr();
895 findpc(pc);
896 tty->cr();
897 #endif
898 #define PRINT_REG(rax, value) \
899 { tty->print("%s = ", #rax); os::print_location(tty, value); }
900 PRINT_REG(rax, regs[15]);
901 PRINT_REG(rbx, regs[12]);
902 PRINT_REG(rcx, regs[14]);
903 PRINT_REG(rdx, regs[13]);
904 PRINT_REG(rdi, regs[8]);
905 PRINT_REG(rsi, regs[9]);
906 PRINT_REG(rbp, regs[10]);
907 PRINT_REG(rsp, regs[11]);
908 PRINT_REG(r8 , regs[7]);
909 PRINT_REG(r9 , regs[6]);
910 PRINT_REG(r10, regs[5]);
911 PRINT_REG(r11, regs[4]);
912 PRINT_REG(r12, regs[3]);
913 PRINT_REG(r13, regs[2]);
914 PRINT_REG(r14, regs[1]);
915 PRINT_REG(r15, regs[0]);
916 #undef PRINT_REG
917 // Print some words near top of staack.
918 int64_t* rsp = (int64_t*) regs[11];
919 int64_t* dump_sp = rsp;
920 for (int col1 = 0; col1 < 8; col1++) {
921 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
922 os::print_location(tty, *dump_sp++);
923 }
924 for (int row = 0; row < 25; row++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 for (int col = 0; col < 4; col++) {
927 tty->print(" 0x%016lx", *dump_sp++);
928 }
929 tty->cr();
930 }
931 // Print some instructions around pc:
932 Disassembler::decode((address)pc-64, (address)pc);
933 tty->print_cr("--------");
934 Disassembler::decode((address)pc, (address)pc+32);
935 }
937 #endif // _LP64
939 // Now versions that are common to 32/64 bit
941 void MacroAssembler::addptr(Register dst, int32_t imm32) {
942 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
943 }
945 void MacroAssembler::addptr(Register dst, Register src) {
946 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
947 }
949 void MacroAssembler::addptr(Address dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
953 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
954 if (reachable(src)) {
955 Assembler::addsd(dst, as_Address(src));
956 } else {
957 lea(rscratch1, src);
958 Assembler::addsd(dst, Address(rscratch1, 0));
959 }
960 }
962 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
963 if (reachable(src)) {
964 addss(dst, as_Address(src));
965 } else {
966 lea(rscratch1, src);
967 addss(dst, Address(rscratch1, 0));
968 }
969 }
971 void MacroAssembler::align(int modulus) {
972 if (offset() % modulus != 0) {
973 nop(modulus - (offset() % modulus));
974 }
975 }
977 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
978 // Used in sign-masking with aligned address.
979 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
980 if (reachable(src)) {
981 Assembler::andpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::andpd(dst, Address(rscratch1, 0));
985 }
986 }
988 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
989 // Used in sign-masking with aligned address.
990 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
991 if (reachable(src)) {
992 Assembler::andps(dst, as_Address(src));
993 } else {
994 lea(rscratch1, src);
995 Assembler::andps(dst, Address(rscratch1, 0));
996 }
997 }
999 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1000 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1001 }
1003 void MacroAssembler::atomic_incl(Address counter_addr) {
1004 if (os::is_MP())
1005 lock();
1006 incrementl(counter_addr);
1007 }
1009 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1010 if (reachable(counter_addr)) {
1011 atomic_incl(as_Address(counter_addr));
1012 } else {
1013 lea(scr, counter_addr);
1014 atomic_incl(Address(scr, 0));
1015 }
1016 }
1018 #ifdef _LP64
1019 void MacroAssembler::atomic_incq(Address counter_addr) {
1020 if (os::is_MP())
1021 lock();
1022 incrementq(counter_addr);
1023 }
1025 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1026 if (reachable(counter_addr)) {
1027 atomic_incq(as_Address(counter_addr));
1028 } else {
1029 lea(scr, counter_addr);
1030 atomic_incq(Address(scr, 0));
1031 }
1032 }
1033 #endif
1035 // Writes to stack successive pages until offset reached to check for
1036 // stack overflow + shadow pages. This clobbers tmp.
1037 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1038 movptr(tmp, rsp);
1039 // Bang stack for total size given plus shadow page size.
1040 // Bang one page at a time because large size can bang beyond yellow and
1041 // red zones.
1042 Label loop;
1043 bind(loop);
1044 movl(Address(tmp, (-os::vm_page_size())), size );
1045 subptr(tmp, os::vm_page_size());
1046 subl(size, os::vm_page_size());
1047 jcc(Assembler::greater, loop);
1049 // Bang down shadow pages too.
1050 // At this point, (tmp-0) is the last address touched, so don't
1051 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1052 // was post-decremented.) Skip this address by starting at i=1, and
1053 // touch a few more pages below. N.B. It is important to touch all
1054 // the way down to and including i=StackShadowPages.
1055 for (int i = 1; i < StackShadowPages; i++) {
1056 // this could be any sized move but this is can be a debugging crumb
1057 // so the bigger the better.
1058 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1059 }
1060 }
1062 int MacroAssembler::biased_locking_enter(Register lock_reg,
1063 Register obj_reg,
1064 Register swap_reg,
1065 Register tmp_reg,
1066 bool swap_reg_contains_mark,
1067 Label& done,
1068 Label* slow_case,
1069 BiasedLockingCounters* counters) {
1070 assert(UseBiasedLocking, "why call this otherwise?");
1071 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1072 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1073 bool need_tmp_reg = false;
1074 if (tmp_reg == noreg) {
1075 need_tmp_reg = true;
1076 tmp_reg = lock_reg;
1077 assert_different_registers(lock_reg, obj_reg, swap_reg);
1078 } else {
1079 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1080 }
1081 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1082 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1083 Address saved_mark_addr(lock_reg, 0);
1085 if (PrintBiasedLockingStatistics && counters == NULL) {
1086 counters = BiasedLocking::counters();
1087 }
1088 // Biased locking
1089 // See whether the lock is currently biased toward our thread and
1090 // whether the epoch is still valid
1091 // Note that the runtime guarantees sufficient alignment of JavaThread
1092 // pointers to allow age to be placed into low bits
1093 // First check to see whether biasing is even enabled for this object
1094 Label cas_label;
1095 int null_check_offset = -1;
1096 if (!swap_reg_contains_mark) {
1097 null_check_offset = offset();
1098 movptr(swap_reg, mark_addr);
1099 }
1100 if (need_tmp_reg) {
1101 push(tmp_reg);
1102 }
1103 movptr(tmp_reg, swap_reg);
1104 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1105 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1106 if (need_tmp_reg) {
1107 pop(tmp_reg);
1108 }
1109 jcc(Assembler::notEqual, cas_label);
1110 // The bias pattern is present in the object's header. Need to check
1111 // whether the bias owner and the epoch are both still current.
1112 #ifndef _LP64
1113 // Note that because there is no current thread register on x86_32 we
1114 // need to store off the mark word we read out of the object to
1115 // avoid reloading it and needing to recheck invariants below. This
1116 // store is unfortunate but it makes the overall code shorter and
1117 // simpler.
1118 movptr(saved_mark_addr, swap_reg);
1119 #endif
1120 if (need_tmp_reg) {
1121 push(tmp_reg);
1122 }
1123 if (swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 }
1126 load_prototype_header(tmp_reg, obj_reg);
1127 #ifdef _LP64
1128 orptr(tmp_reg, r15_thread);
1129 xorptr(tmp_reg, swap_reg);
1130 Register header_reg = tmp_reg;
1131 #else
1132 xorptr(tmp_reg, swap_reg);
1133 get_thread(swap_reg);
1134 xorptr(swap_reg, tmp_reg);
1135 Register header_reg = swap_reg;
1136 #endif
1137 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1138 if (need_tmp_reg) {
1139 pop(tmp_reg);
1140 }
1141 if (counters != NULL) {
1142 cond_inc32(Assembler::zero,
1143 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1144 }
1145 jcc(Assembler::equal, done);
1147 Label try_revoke_bias;
1148 Label try_rebias;
1150 // At this point we know that the header has the bias pattern and
1151 // that we are not the bias owner in the current epoch. We need to
1152 // figure out more details about the state of the header in order to
1153 // know what operations can be legally performed on the object's
1154 // header.
1156 // If the low three bits in the xor result aren't clear, that means
1157 // the prototype header is no longer biased and we have to revoke
1158 // the bias on this object.
1159 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1160 jccb(Assembler::notZero, try_revoke_bias);
1162 // Biasing is still enabled for this data type. See whether the
1163 // epoch of the current bias is still valid, meaning that the epoch
1164 // bits of the mark word are equal to the epoch bits of the
1165 // prototype header. (Note that the prototype header's epoch bits
1166 // only change at a safepoint.) If not, attempt to rebias the object
1167 // toward the current thread. Note that we must be absolutely sure
1168 // that the current epoch is invalid in order to do this because
1169 // otherwise the manipulations it performs on the mark word are
1170 // illegal.
1171 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1172 jccb(Assembler::notZero, try_rebias);
1174 // The epoch of the current bias is still valid but we know nothing
1175 // about the owner; it might be set or it might be clear. Try to
1176 // acquire the bias of the object using an atomic operation. If this
1177 // fails we will go in to the runtime to revoke the object's bias.
1178 // Note that we first construct the presumed unbiased header so we
1179 // don't accidentally blow away another thread's valid bias.
1180 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1181 andptr(swap_reg,
1182 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1183 if (need_tmp_reg) {
1184 push(tmp_reg);
1185 }
1186 #ifdef _LP64
1187 movptr(tmp_reg, swap_reg);
1188 orptr(tmp_reg, r15_thread);
1189 #else
1190 get_thread(tmp_reg);
1191 orptr(tmp_reg, swap_reg);
1192 #endif
1193 if (os::is_MP()) {
1194 lock();
1195 }
1196 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1197 if (need_tmp_reg) {
1198 pop(tmp_reg);
1199 }
1200 // If the biasing toward our thread failed, this means that
1201 // another thread succeeded in biasing it toward itself and we
1202 // need to revoke that bias. The revocation will occur in the
1203 // interpreter runtime in the slow case.
1204 if (counters != NULL) {
1205 cond_inc32(Assembler::zero,
1206 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1207 }
1208 if (slow_case != NULL) {
1209 jcc(Assembler::notZero, *slow_case);
1210 }
1211 jmp(done);
1213 bind(try_rebias);
1214 // At this point we know the epoch has expired, meaning that the
1215 // current "bias owner", if any, is actually invalid. Under these
1216 // circumstances _only_, we are allowed to use the current header's
1217 // value as the comparison value when doing the cas to acquire the
1218 // bias in the current epoch. In other words, we allow transfer of
1219 // the bias from one thread to another directly in this situation.
1220 //
1221 // FIXME: due to a lack of registers we currently blow away the age
1222 // bits in this situation. Should attempt to preserve them.
1223 if (need_tmp_reg) {
1224 push(tmp_reg);
1225 }
1226 load_prototype_header(tmp_reg, obj_reg);
1227 #ifdef _LP64
1228 orptr(tmp_reg, r15_thread);
1229 #else
1230 get_thread(swap_reg);
1231 orptr(tmp_reg, swap_reg);
1232 movptr(swap_reg, saved_mark_addr);
1233 #endif
1234 if (os::is_MP()) {
1235 lock();
1236 }
1237 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1238 if (need_tmp_reg) {
1239 pop(tmp_reg);
1240 }
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 if (need_tmp_reg) {
1267 push(tmp_reg);
1268 }
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 if (need_tmp_reg) {
1275 pop(tmp_reg);
1276 }
1277 // Fall through to the normal CAS-based lock, because no matter what
1278 // the result of the above CAS, some thread must have succeeded in
1279 // removing the bias bit from the object's header.
1280 if (counters != NULL) {
1281 cond_inc32(Assembler::zero,
1282 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1283 }
1285 bind(cas_label);
1287 return null_check_offset;
1288 }
1290 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1291 assert(UseBiasedLocking, "why call this otherwise?");
1293 // Check for biased locking unlock case, which is a no-op
1294 // Note: we do not have to check the thread ID for two reasons.
1295 // First, the interpreter checks for IllegalMonitorStateException at
1296 // a higher level. Second, if the bias was revoked while we held the
1297 // lock, the object could not be rebiased toward another thread, so
1298 // the bias bit would be clear.
1299 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1300 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1301 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1302 jcc(Assembler::equal, done);
1303 }
1305 #ifdef COMPILER2
1307 #if INCLUDE_RTM_OPT
1309 // Update rtm_counters based on abort status
1310 // input: abort_status
1311 // rtm_counters (RTMLockingCounters*)
1312 // flags are killed
1313 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1316 if (PrintPreciseRTMLockingStatistics) {
1317 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1318 Label check_abort;
1319 testl(abort_status, (1<<i));
1320 jccb(Assembler::equal, check_abort);
1321 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1322 bind(check_abort);
1323 }
1324 }
1325 }
1327 // Branch if (random & (count-1) != 0), count is 2^n
1328 // tmp, scr and flags are killed
1329 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1330 assert(tmp == rax, "");
1331 assert(scr == rdx, "");
1332 rdtsc(); // modifies EDX:EAX
1333 andptr(tmp, count-1);
1334 jccb(Assembler::notZero, brLabel);
1335 }
1337 // Perform abort ratio calculation, set no_rtm bit if high ratio
1338 // input: rtm_counters_Reg (RTMLockingCounters* address)
1339 // tmpReg, rtm_counters_Reg and flags are killed
1340 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1341 Register rtm_counters_Reg,
1342 RTMLockingCounters* rtm_counters,
1343 Metadata* method_data) {
1344 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1346 if (RTMLockingCalculationDelay > 0) {
1347 // Delay calculation
1348 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1349 testptr(tmpReg, tmpReg);
1350 jccb(Assembler::equal, L_done);
1351 }
1352 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1353 // Aborted transactions = abort_count * 100
1354 // All transactions = total_count * RTMTotalCountIncrRate
1355 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1357 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1358 cmpptr(tmpReg, RTMAbortThreshold);
1359 jccb(Assembler::below, L_check_always_rtm2);
1360 imulptr(tmpReg, tmpReg, 100);
1362 Register scrReg = rtm_counters_Reg;
1363 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1364 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1365 imulptr(scrReg, scrReg, RTMAbortRatio);
1366 cmpptr(tmpReg, scrReg);
1367 jccb(Assembler::below, L_check_always_rtm1);
1368 if (method_data != NULL) {
1369 // set rtm_state to "no rtm" in MDO
1370 mov_metadata(tmpReg, method_data);
1371 if (os::is_MP()) {
1372 lock();
1373 }
1374 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1375 }
1376 jmpb(L_done);
1377 bind(L_check_always_rtm1);
1378 // Reload RTMLockingCounters* address
1379 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1380 bind(L_check_always_rtm2);
1381 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1382 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1383 jccb(Assembler::below, L_done);
1384 if (method_data != NULL) {
1385 // set rtm_state to "always rtm" in MDO
1386 mov_metadata(tmpReg, method_data);
1387 if (os::is_MP()) {
1388 lock();
1389 }
1390 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1391 }
1392 bind(L_done);
1393 }
1395 // Update counters and perform abort ratio calculation
1396 // input: abort_status_Reg
1397 // rtm_counters_Reg, flags are killed
1398 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1399 Register rtm_counters_Reg,
1400 RTMLockingCounters* rtm_counters,
1401 Metadata* method_data,
1402 bool profile_rtm) {
1404 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1405 // update rtm counters based on rax value at abort
1406 // reads abort_status_Reg, updates flags
1407 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1408 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1409 if (profile_rtm) {
1410 // Save abort status because abort_status_Reg is used by following code.
1411 if (RTMRetryCount > 0) {
1412 push(abort_status_Reg);
1413 }
1414 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1415 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1416 // restore abort status
1417 if (RTMRetryCount > 0) {
1418 pop(abort_status_Reg);
1419 }
1420 }
1421 }
1423 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1424 // inputs: retry_count_Reg
1425 // : abort_status_Reg
1426 // output: retry_count_Reg decremented by 1
1427 // flags are killed
1428 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1429 Label doneRetry;
1430 assert(abort_status_Reg == rax, "");
1431 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1432 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1433 // if reason is in 0x6 and retry count != 0 then retry
1434 andptr(abort_status_Reg, 0x6);
1435 jccb(Assembler::zero, doneRetry);
1436 testl(retry_count_Reg, retry_count_Reg);
1437 jccb(Assembler::zero, doneRetry);
1438 pause();
1439 decrementl(retry_count_Reg);
1440 jmp(retryLabel);
1441 bind(doneRetry);
1442 }
1444 // Spin and retry if lock is busy,
1445 // inputs: box_Reg (monitor address)
1446 // : retry_count_Reg
1447 // output: retry_count_Reg decremented by 1
1448 // : clear z flag if retry count exceeded
1449 // tmp_Reg, scr_Reg, flags are killed
1450 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1451 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1452 Label SpinLoop, SpinExit, doneRetry;
1453 // Clean monitor_value bit to get valid pointer
1454 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1456 testl(retry_count_Reg, retry_count_Reg);
1457 jccb(Assembler::zero, doneRetry);
1458 decrementl(retry_count_Reg);
1459 movptr(scr_Reg, RTMSpinLoopCount);
1461 bind(SpinLoop);
1462 pause();
1463 decrementl(scr_Reg);
1464 jccb(Assembler::lessEqual, SpinExit);
1465 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1466 testptr(tmp_Reg, tmp_Reg);
1467 jccb(Assembler::notZero, SpinLoop);
1469 bind(SpinExit);
1470 jmp(retryLabel);
1471 bind(doneRetry);
1472 incrementl(retry_count_Reg); // clear z flag
1473 }
1475 // Use RTM for normal stack locks
1476 // Input: objReg (object to lock)
1477 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1478 Register retry_on_abort_count_Reg,
1479 RTMLockingCounters* stack_rtm_counters,
1480 Metadata* method_data, bool profile_rtm,
1481 Label& DONE_LABEL, Label& IsInflated) {
1482 assert(UseRTMForStackLocks, "why call this otherwise?");
1483 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1484 assert(tmpReg == rax, "");
1485 assert(scrReg == rdx, "");
1486 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1488 if (RTMRetryCount > 0) {
1489 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1490 bind(L_rtm_retry);
1491 }
1492 movptr(tmpReg, Address(objReg, 0));
1493 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1494 jcc(Assembler::notZero, IsInflated);
1496 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1497 Label L_noincrement;
1498 if (RTMTotalCountIncrRate > 1) {
1499 // tmpReg, scrReg and flags are killed
1500 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1501 }
1502 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1503 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1504 bind(L_noincrement);
1505 }
1506 xbegin(L_on_abort);
1507 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1508 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1509 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1510 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1512 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1513 if (UseRTMXendForLockBusy) {
1514 xend();
1515 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1516 jmp(L_decrement_retry);
1517 }
1518 else {
1519 xabort(0);
1520 }
1521 bind(L_on_abort);
1522 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1523 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1524 }
1525 bind(L_decrement_retry);
1526 if (RTMRetryCount > 0) {
1527 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1528 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1529 }
1530 }
1532 // Use RTM for inflating locks
1533 // inputs: objReg (object to lock)
1534 // boxReg (on-stack box address (displaced header location) - KILLED)
1535 // tmpReg (ObjectMonitor address + 2(monitor_value))
1536 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1537 Register scrReg, Register retry_on_busy_count_Reg,
1538 Register retry_on_abort_count_Reg,
1539 RTMLockingCounters* rtm_counters,
1540 Metadata* method_data, bool profile_rtm,
1541 Label& DONE_LABEL) {
1542 assert(UseRTMLocking, "why call this otherwise?");
1543 assert(tmpReg == rax, "");
1544 assert(scrReg == rdx, "");
1545 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1546 // Clean monitor_value bit to get valid pointer
1547 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1549 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1550 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1551 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1553 if (RTMRetryCount > 0) {
1554 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1555 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1556 bind(L_rtm_retry);
1557 }
1558 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1559 Label L_noincrement;
1560 if (RTMTotalCountIncrRate > 1) {
1561 // tmpReg, scrReg and flags are killed
1562 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1563 }
1564 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1565 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1566 bind(L_noincrement);
1567 }
1568 xbegin(L_on_abort);
1569 movptr(tmpReg, Address(objReg, 0));
1570 movptr(tmpReg, Address(tmpReg, owner_offset));
1571 testptr(tmpReg, tmpReg);
1572 jcc(Assembler::zero, DONE_LABEL);
1573 if (UseRTMXendForLockBusy) {
1574 xend();
1575 jmp(L_decrement_retry);
1576 }
1577 else {
1578 xabort(0);
1579 }
1580 bind(L_on_abort);
1581 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1582 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1583 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1584 }
1585 if (RTMRetryCount > 0) {
1586 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1587 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1588 }
1590 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1591 testptr(tmpReg, tmpReg) ;
1592 jccb(Assembler::notZero, L_decrement_retry) ;
1594 // Appears unlocked - try to swing _owner from null to non-null.
1595 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1596 #ifdef _LP64
1597 Register threadReg = r15_thread;
1598 #else
1599 get_thread(scrReg);
1600 Register threadReg = scrReg;
1601 #endif
1602 if (os::is_MP()) {
1603 lock();
1604 }
1605 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1607 if (RTMRetryCount > 0) {
1608 // success done else retry
1609 jccb(Assembler::equal, DONE_LABEL) ;
1610 bind(L_decrement_retry);
1611 // Spin and retry if lock is busy.
1612 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1613 }
1614 else {
1615 bind(L_decrement_retry);
1616 }
1617 }
1619 #endif // INCLUDE_RTM_OPT
1621 // Fast_Lock and Fast_Unlock used by C2
1623 // Because the transitions from emitted code to the runtime
1624 // monitorenter/exit helper stubs are so slow it's critical that
1625 // we inline both the stack-locking fast-path and the inflated fast path.
1626 //
1627 // See also: cmpFastLock and cmpFastUnlock.
1628 //
1629 // What follows is a specialized inline transliteration of the code
1630 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1631 // another option would be to emit TrySlowEnter and TrySlowExit methods
1632 // at startup-time. These methods would accept arguments as
1633 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1634 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1635 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1636 // In practice, however, the # of lock sites is bounded and is usually small.
1637 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1638 // if the processor uses simple bimodal branch predictors keyed by EIP
1639 // Since the helper routines would be called from multiple synchronization
1640 // sites.
1641 //
1642 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1643 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1644 // to those specialized methods. That'd give us a mostly platform-independent
1645 // implementation that the JITs could optimize and inline at their pleasure.
1646 // Done correctly, the only time we'd need to cross to native could would be
1647 // to park() or unpark() threads. We'd also need a few more unsafe operators
1648 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1649 // (b) explicit barriers or fence operations.
1650 //
1651 // TODO:
1652 //
1653 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1654 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1655 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1656 // the lock operators would typically be faster than reifying Self.
1657 //
1658 // * Ideally I'd define the primitives as:
1659 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1660 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1661 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1662 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1663 // Furthermore the register assignments are overconstrained, possibly resulting in
1664 // sub-optimal code near the synchronization site.
1665 //
1666 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1667 // Alternately, use a better sp-proximity test.
1668 //
1669 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1670 // Either one is sufficient to uniquely identify a thread.
1671 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1672 //
1673 // * Intrinsify notify() and notifyAll() for the common cases where the
1674 // object is locked by the calling thread but the waitlist is empty.
1675 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1676 //
1677 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1678 // But beware of excessive branch density on AMD Opterons.
1679 //
1680 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1681 // or failure of the fast-path. If the fast-path fails then we pass
1682 // control to the slow-path, typically in C. In Fast_Lock and
1683 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1684 // will emit a conditional branch immediately after the node.
1685 // So we have branches to branches and lots of ICC.ZF games.
1686 // Instead, it might be better to have C2 pass a "FailureLabel"
1687 // into Fast_Lock and Fast_Unlock. In the case of success, control
1688 // will drop through the node. ICC.ZF is undefined at exit.
1689 // In the case of failure, the node will branch directly to the
1690 // FailureLabel
1693 // obj: object to lock
1694 // box: on-stack box address (displaced header location) - KILLED
1695 // rax,: tmp -- KILLED
1696 // scr: tmp -- KILLED
1697 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1698 Register scrReg, Register cx1Reg, Register cx2Reg,
1699 BiasedLockingCounters* counters,
1700 RTMLockingCounters* rtm_counters,
1701 RTMLockingCounters* stack_rtm_counters,
1702 Metadata* method_data,
1703 bool use_rtm, bool profile_rtm) {
1704 // Ensure the register assignents are disjoint
1705 assert(tmpReg == rax, "");
1707 if (use_rtm) {
1708 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1709 } else {
1710 assert(cx1Reg == noreg, "");
1711 assert(cx2Reg == noreg, "");
1712 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1713 }
1715 if (counters != NULL) {
1716 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1717 }
1718 if (EmitSync & 1) {
1719 // set box->dhw = unused_mark (3)
1720 // Force all sync thru slow-path: slow_enter() and slow_exit()
1721 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1722 cmpptr (rsp, (int32_t)NULL_WORD);
1723 } else
1724 if (EmitSync & 2) {
1725 Label DONE_LABEL ;
1726 if (UseBiasedLocking) {
1727 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
1728 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1729 }
1731 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1732 orptr (tmpReg, 0x1);
1733 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1734 if (os::is_MP()) {
1735 lock();
1736 }
1737 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1738 jccb(Assembler::equal, DONE_LABEL);
1739 // Recursive locking
1740 subptr(tmpReg, rsp);
1741 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1742 movptr(Address(boxReg, 0), tmpReg);
1743 bind(DONE_LABEL);
1744 } else {
1745 // Possible cases that we'll encounter in fast_lock
1746 // ------------------------------------------------
1747 // * Inflated
1748 // -- unlocked
1749 // -- Locked
1750 // = by self
1751 // = by other
1752 // * biased
1753 // -- by Self
1754 // -- by other
1755 // * neutral
1756 // * stack-locked
1757 // -- by self
1758 // = sp-proximity test hits
1759 // = sp-proximity test generates false-negative
1760 // -- by other
1761 //
1763 Label IsInflated, DONE_LABEL;
1765 // it's stack-locked, biased or neutral
1766 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1767 // order to reduce the number of conditional branches in the most common cases.
1768 // Beware -- there's a subtle invariant that fetch of the markword
1769 // at [FETCH], below, will never observe a biased encoding (*101b).
1770 // If this invariant is not held we risk exclusion (safety) failure.
1771 if (UseBiasedLocking && !UseOptoBiasInlining) {
1772 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1773 }
1775 #if INCLUDE_RTM_OPT
1776 if (UseRTMForStackLocks && use_rtm) {
1777 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1778 stack_rtm_counters, method_data, profile_rtm,
1779 DONE_LABEL, IsInflated);
1780 }
1781 #endif // INCLUDE_RTM_OPT
1783 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1784 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1785 jccb(Assembler::notZero, IsInflated);
1787 // Attempt stack-locking ...
1788 orptr (tmpReg, markOopDesc::unlocked_value);
1789 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1790 if (os::is_MP()) {
1791 lock();
1792 }
1793 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1794 if (counters != NULL) {
1795 cond_inc32(Assembler::equal,
1796 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1797 }
1798 jcc(Assembler::equal, DONE_LABEL); // Success
1800 // Recursive locking.
1801 // The object is stack-locked: markword contains stack pointer to BasicLock.
1802 // Locked by current thread if difference with current SP is less than one page.
1803 subptr(tmpReg, rsp);
1804 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1805 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1806 movptr(Address(boxReg, 0), tmpReg);
1807 if (counters != NULL) {
1808 cond_inc32(Assembler::equal,
1809 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1810 }
1811 jmp(DONE_LABEL);
1813 bind(IsInflated);
1814 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + 2(monitor_value)
1816 #if INCLUDE_RTM_OPT
1817 // Use the same RTM locking code in 32- and 64-bit VM.
1818 if (use_rtm) {
1819 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1820 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1821 } else {
1822 #endif // INCLUDE_RTM_OPT
1824 #ifndef _LP64
1825 // The object is inflated.
1826 //
1827 // TODO-FIXME: eliminate the ugly use of manifest constants:
1828 // Use markOopDesc::monitor_value instead of "2".
1829 // use markOop::unused_mark() instead of "3".
1830 // The tmpReg value is an objectMonitor reference ORed with
1831 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
1832 // objectmonitor pointer by masking off the "2" bit or we can just
1833 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
1834 // field offsets with "-2" to compensate for and annul the low-order tag bit.
1835 //
1836 // I use the latter as it avoids AGI stalls.
1837 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
1838 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
1839 //
1840 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
1842 // boxReg refers to the on-stack BasicLock in the current frame.
1843 // We'd like to write:
1844 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
1845 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1846 // additional latency as we have another ST in the store buffer that must drain.
1848 if (EmitSync & 8192) {
1849 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1850 get_thread (scrReg);
1851 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1852 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1853 if (os::is_MP()) {
1854 lock();
1855 }
1856 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1857 } else
1858 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1859 movptr(scrReg, boxReg);
1860 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1862 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1863 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1864 // prefetchw [eax + Offset(_owner)-2]
1865 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1866 }
1868 if ((EmitSync & 64) == 0) {
1869 // Optimistic form: consider XORL tmpReg,tmpReg
1870 movptr(tmpReg, NULL_WORD);
1871 } else {
1872 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1873 // Test-And-CAS instead of CAS
1874 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1875 testptr(tmpReg, tmpReg); // Locked ?
1876 jccb (Assembler::notZero, DONE_LABEL);
1877 }
1879 // Appears unlocked - try to swing _owner from null to non-null.
1880 // Ideally, I'd manifest "Self" with get_thread and then attempt
1881 // to CAS the register containing Self into m->Owner.
1882 // But we don't have enough registers, so instead we can either try to CAS
1883 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1884 // we later store "Self" into m->Owner. Transiently storing a stack address
1885 // (rsp or the address of the box) into m->owner is harmless.
1886 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1887 if (os::is_MP()) {
1888 lock();
1889 }
1890 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1891 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1892 jccb (Assembler::notZero, DONE_LABEL);
1893 get_thread (scrReg); // beware: clobbers ICCs
1894 movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg);
1895 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1897 // If the CAS fails we can either retry or pass control to the slow-path.
1898 // We use the latter tactic.
1899 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1900 // If the CAS was successful ...
1901 // Self has acquired the lock
1902 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1903 // Intentional fall-through into DONE_LABEL ...
1904 } else {
1905 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1906 movptr(boxReg, tmpReg);
1908 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1909 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1910 // prefetchw [eax + Offset(_owner)-2]
1911 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1912 }
1914 if ((EmitSync & 64) == 0) {
1915 // Optimistic form
1916 xorptr (tmpReg, tmpReg);
1917 } else {
1918 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1919 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1920 testptr(tmpReg, tmpReg); // Locked ?
1921 jccb (Assembler::notZero, DONE_LABEL);
1922 }
1924 // Appears unlocked - try to swing _owner from null to non-null.
1925 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1926 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1927 get_thread (scrReg);
1928 if (os::is_MP()) {
1929 lock();
1930 }
1931 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1933 // If the CAS fails we can either retry or pass control to the slow-path.
1934 // We use the latter tactic.
1935 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1936 // If the CAS was successful ...
1937 // Self has acquired the lock
1938 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1939 // Intentional fall-through into DONE_LABEL ...
1940 }
1941 #else // _LP64
1942 // It's inflated
1944 // TODO: someday avoid the ST-before-CAS penalty by
1945 // relocating (deferring) the following ST.
1946 // We should also think about trying a CAS without having
1947 // fetched _owner. If the CAS is successful we may
1948 // avoid an RTO->RTS upgrade on the $line.
1950 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1951 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1953 movptr (boxReg, tmpReg);
1954 movptr (tmpReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1955 testptr(tmpReg, tmpReg);
1956 jccb (Assembler::notZero, DONE_LABEL);
1958 // It's inflated and appears unlocked
1959 if (os::is_MP()) {
1960 lock();
1961 }
1962 cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1963 // Intentional fall-through into DONE_LABEL ...
1964 #endif // _LP64
1966 #if INCLUDE_RTM_OPT
1967 } // use_rtm()
1968 #endif
1969 // DONE_LABEL is a hot target - we'd really like to place it at the
1970 // start of cache line by padding with NOPs.
1971 // See the AMD and Intel software optimization manuals for the
1972 // most efficient "long" NOP encodings.
1973 // Unfortunately none of our alignment mechanisms suffice.
1974 bind(DONE_LABEL);
1976 // At DONE_LABEL the icc ZFlag is set as follows ...
1977 // Fast_Unlock uses the same protocol.
1978 // ZFlag == 1 -> Success
1979 // ZFlag == 0 -> Failure - force control through the slow-path
1980 }
1981 }
1983 // obj: object to unlock
1984 // box: box address (displaced header location), killed. Must be EAX.
1985 // tmp: killed, cannot be obj nor box.
1986 //
1987 // Some commentary on balanced locking:
1988 //
1989 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1990 // Methods that don't have provably balanced locking are forced to run in the
1991 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1992 // The interpreter provides two properties:
1993 // I1: At return-time the interpreter automatically and quietly unlocks any
1994 // objects acquired the current activation (frame). Recall that the
1995 // interpreter maintains an on-stack list of locks currently held by
1996 // a frame.
1997 // I2: If a method attempts to unlock an object that is not held by the
1998 // the frame the interpreter throws IMSX.
1999 //
2000 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
2001 // B() doesn't have provably balanced locking so it runs in the interpreter.
2002 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
2003 // is still locked by A().
2004 //
2005 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
2006 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
2007 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
2008 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
2010 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
2011 assert(boxReg == rax, "");
2012 assert_different_registers(objReg, boxReg, tmpReg);
2014 if (EmitSync & 4) {
2015 // Disable - inhibit all inlining. Force control through the slow-path
2016 cmpptr (rsp, 0);
2017 } else
2018 if (EmitSync & 8) {
2019 Label DONE_LABEL;
2020 if (UseBiasedLocking) {
2021 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2022 }
2023 // Classic stack-locking code ...
2024 // Check whether the displaced header is 0
2025 //(=> recursive unlock)
2026 movptr(tmpReg, Address(boxReg, 0));
2027 testptr(tmpReg, tmpReg);
2028 jccb(Assembler::zero, DONE_LABEL);
2029 // If not recursive lock, reset the header to displaced header
2030 if (os::is_MP()) {
2031 lock();
2032 }
2033 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2034 bind(DONE_LABEL);
2035 } else {
2036 Label DONE_LABEL, Stacked, CheckSucc;
2038 // Critically, the biased locking test must have precedence over
2039 // and appear before the (box->dhw == 0) recursive stack-lock test.
2040 if (UseBiasedLocking && !UseOptoBiasInlining) {
2041 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2042 }
2044 #if INCLUDE_RTM_OPT
2045 if (UseRTMForStackLocks && use_rtm) {
2046 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2047 Label L_regular_unlock;
2048 movptr(tmpReg, Address(objReg, 0)); // fetch markword
2049 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2050 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2051 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2052 xend(); // otherwise end...
2053 jmp(DONE_LABEL); // ... and we're done
2054 bind(L_regular_unlock);
2055 }
2056 #endif
2058 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2059 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2060 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2061 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2062 jccb (Assembler::zero, Stacked);
2064 // It's inflated.
2065 #if INCLUDE_RTM_OPT
2066 if (use_rtm) {
2067 Label L_regular_inflated_unlock;
2068 // Clean monitor_value bit to get valid pointer
2069 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
2070 movptr(boxReg, Address(tmpReg, owner_offset));
2071 testptr(boxReg, boxReg);
2072 jccb(Assembler::notZero, L_regular_inflated_unlock);
2073 xend();
2074 jmpb(DONE_LABEL);
2075 bind(L_regular_inflated_unlock);
2076 }
2077 #endif
2079 // Despite our balanced locking property we still check that m->_owner == Self
2080 // as java routines or native JNI code called by this thread might
2081 // have released the lock.
2082 // Refer to the comments in synchronizer.cpp for how we might encode extra
2083 // state in _succ so we can avoid fetching EntryList|cxq.
2084 //
2085 // I'd like to add more cases in fast_lock() and fast_unlock() --
2086 // such as recursive enter and exit -- but we have to be wary of
2087 // I$ bloat, T$ effects and BP$ effects.
2088 //
2089 // If there's no contention try a 1-0 exit. That is, exit without
2090 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2091 // we detect and recover from the race that the 1-0 exit admits.
2092 //
2093 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2094 // before it STs null into _owner, releasing the lock. Updates
2095 // to data protected by the critical section must be visible before
2096 // we drop the lock (and thus before any other thread could acquire
2097 // the lock and observe the fields protected by the lock).
2098 // IA32's memory-model is SPO, so STs are ordered with respect to
2099 // each other and there's no need for an explicit barrier (fence).
2100 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2101 #ifndef _LP64
2102 get_thread (boxReg);
2103 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2104 // prefetchw [ebx + Offset(_owner)-2]
2105 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2106 }
2108 // Note that we could employ various encoding schemes to reduce
2109 // the number of loads below (currently 4) to just 2 or 3.
2110 // Refer to the comments in synchronizer.cpp.
2111 // In practice the chain of fetches doesn't seem to impact performance, however.
2112 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2113 // Attempt to reduce branch density - AMD's branch predictor.
2114 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2115 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2116 orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2117 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2118 jccb (Assembler::notZero, DONE_LABEL);
2119 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2120 jmpb (DONE_LABEL);
2121 } else {
2122 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2123 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2124 jccb (Assembler::notZero, DONE_LABEL);
2125 movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2126 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2127 jccb (Assembler::notZero, CheckSucc);
2128 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2129 jmpb (DONE_LABEL);
2130 }
2132 // The Following code fragment (EmitSync & 65536) improves the performance of
2133 // contended applications and contended synchronization microbenchmarks.
2134 // Unfortunately the emission of the code - even though not executed - causes regressions
2135 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2136 // with an equal number of never-executed NOPs results in the same regression.
2137 // We leave it off by default.
2139 if ((EmitSync & 65536) != 0) {
2140 Label LSuccess, LGoSlowPath ;
2142 bind (CheckSucc);
2144 // Optional pre-test ... it's safe to elide this
2145 if ((EmitSync & 16) == 0) {
2146 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2147 jccb (Assembler::zero, LGoSlowPath);
2148 }
2150 // We have a classic Dekker-style idiom:
2151 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2152 // There are a number of ways to implement the barrier:
2153 // (1) lock:andl &m->_owner, 0
2154 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2155 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2156 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2157 // (2) If supported, an explicit MFENCE is appealing.
2158 // In older IA32 processors MFENCE is slower than lock:add or xchg
2159 // particularly if the write-buffer is full as might be the case if
2160 // if stores closely precede the fence or fence-equivalent instruction.
2161 // In more modern implementations MFENCE appears faster, however.
2162 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2163 // The $lines underlying the top-of-stack should be in M-state.
2164 // The locked add instruction is serializing, of course.
2165 // (4) Use xchg, which is serializing
2166 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2167 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2168 // The integer condition codes will tell us if succ was 0.
2169 // Since _succ and _owner should reside in the same $line and
2170 // we just stored into _owner, it's likely that the $line
2171 // remains in M-state for the lock:orl.
2172 //
2173 // We currently use (3), although it's likely that switching to (2)
2174 // is correct for the future.
2176 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2177 if (os::is_MP()) {
2178 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2179 mfence();
2180 } else {
2181 lock (); addptr(Address(rsp, 0), 0);
2182 }
2183 }
2184 // Ratify _succ remains non-null
2185 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0);
2186 jccb (Assembler::notZero, LSuccess);
2188 xorptr(boxReg, boxReg); // box is really EAX
2189 if (os::is_MP()) { lock(); }
2190 cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2191 jccb (Assembler::notEqual, LSuccess);
2192 // Since we're low on registers we installed rsp as a placeholding in _owner.
2193 // Now install Self over rsp. This is safe as we're transitioning from
2194 // non-null to non=null
2195 get_thread (boxReg);
2196 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg);
2197 // Intentional fall-through into LGoSlowPath ...
2199 bind (LGoSlowPath);
2200 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2201 jmpb (DONE_LABEL);
2203 bind (LSuccess);
2204 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2205 jmpb (DONE_LABEL);
2206 }
2208 bind (Stacked);
2209 // It's not inflated and it's not recursively stack-locked and it's not biased.
2210 // It must be stack-locked.
2211 // Try to reset the header to displaced header.
2212 // The "box" value on the stack is stable, so we can reload
2213 // and be assured we observe the same value as above.
2214 movptr(tmpReg, Address(boxReg, 0));
2215 if (os::is_MP()) {
2216 lock();
2217 }
2218 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2219 // Intention fall-thru into DONE_LABEL
2221 // DONE_LABEL is a hot target - we'd really like to place it at the
2222 // start of cache line by padding with NOPs.
2223 // See the AMD and Intel software optimization manuals for the
2224 // most efficient "long" NOP encodings.
2225 // Unfortunately none of our alignment mechanisms suffice.
2226 if ((EmitSync & 65536) == 0) {
2227 bind (CheckSucc);
2228 }
2229 #else // _LP64
2230 // It's inflated
2231 movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2232 xorptr(boxReg, r15_thread);
2233 orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2234 jccb (Assembler::notZero, DONE_LABEL);
2235 movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2236 orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2237 jccb (Assembler::notZero, CheckSucc);
2238 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2239 jmpb (DONE_LABEL);
2241 if ((EmitSync & 65536) == 0) {
2242 Label LSuccess, LGoSlowPath ;
2243 bind (CheckSucc);
2244 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2245 jccb (Assembler::zero, LGoSlowPath);
2247 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2248 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2249 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2250 // are all faster when the write buffer is populated.
2251 movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2252 if (os::is_MP()) {
2253 lock (); addl (Address(rsp, 0), 0);
2254 }
2255 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2256 jccb (Assembler::notZero, LSuccess);
2258 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX
2259 if (os::is_MP()) { lock(); }
2260 cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2261 jccb (Assembler::notEqual, LSuccess);
2262 // Intentional fall-through into slow-path
2264 bind (LGoSlowPath);
2265 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2266 jmpb (DONE_LABEL);
2268 bind (LSuccess);
2269 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2270 jmpb (DONE_LABEL);
2271 }
2273 bind (Stacked);
2274 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2275 if (os::is_MP()) { lock(); }
2276 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2278 if (EmitSync & 65536) {
2279 bind (CheckSucc);
2280 }
2281 #endif
2282 bind(DONE_LABEL);
2283 // Avoid branch to branch on AMD processors
2284 if (EmitSync & 32768) {
2285 nop();
2286 }
2287 }
2288 }
2289 #endif // COMPILER2
2291 void MacroAssembler::c2bool(Register x) {
2292 // implements x == 0 ? 0 : 1
2293 // note: must only look at least-significant byte of x
2294 // since C-style booleans are stored in one byte
2295 // only! (was bug)
2296 andl(x, 0xFF);
2297 setb(Assembler::notZero, x);
2298 }
2300 // Wouldn't need if AddressLiteral version had new name
2301 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2302 Assembler::call(L, rtype);
2303 }
2305 void MacroAssembler::call(Register entry) {
2306 Assembler::call(entry);
2307 }
2309 void MacroAssembler::call(AddressLiteral entry) {
2310 if (reachable(entry)) {
2311 Assembler::call_literal(entry.target(), entry.rspec());
2312 } else {
2313 lea(rscratch1, entry);
2314 Assembler::call(rscratch1);
2315 }
2316 }
2318 void MacroAssembler::ic_call(address entry) {
2319 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2320 movptr(rax, (intptr_t)Universe::non_oop_word());
2321 call(AddressLiteral(entry, rh));
2322 }
2324 // Implementation of call_VM versions
2326 void MacroAssembler::call_VM(Register oop_result,
2327 address entry_point,
2328 bool check_exceptions) {
2329 Label C, E;
2330 call(C, relocInfo::none);
2331 jmp(E);
2333 bind(C);
2334 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2335 ret(0);
2337 bind(E);
2338 }
2340 void MacroAssembler::call_VM(Register oop_result,
2341 address entry_point,
2342 Register arg_1,
2343 bool check_exceptions) {
2344 Label C, E;
2345 call(C, relocInfo::none);
2346 jmp(E);
2348 bind(C);
2349 pass_arg1(this, arg_1);
2350 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2351 ret(0);
2353 bind(E);
2354 }
2356 void MacroAssembler::call_VM(Register oop_result,
2357 address entry_point,
2358 Register arg_1,
2359 Register arg_2,
2360 bool check_exceptions) {
2361 Label C, E;
2362 call(C, relocInfo::none);
2363 jmp(E);
2365 bind(C);
2367 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2369 pass_arg2(this, arg_2);
2370 pass_arg1(this, arg_1);
2371 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2372 ret(0);
2374 bind(E);
2375 }
2377 void MacroAssembler::call_VM(Register oop_result,
2378 address entry_point,
2379 Register arg_1,
2380 Register arg_2,
2381 Register arg_3,
2382 bool check_exceptions) {
2383 Label C, E;
2384 call(C, relocInfo::none);
2385 jmp(E);
2387 bind(C);
2389 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2390 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2391 pass_arg3(this, arg_3);
2393 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2394 pass_arg2(this, arg_2);
2396 pass_arg1(this, arg_1);
2397 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2398 ret(0);
2400 bind(E);
2401 }
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 int number_of_arguments,
2407 bool check_exceptions) {
2408 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2409 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2410 }
2412 void MacroAssembler::call_VM(Register oop_result,
2413 Register last_java_sp,
2414 address entry_point,
2415 Register arg_1,
2416 bool check_exceptions) {
2417 pass_arg1(this, arg_1);
2418 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2419 }
2421 void MacroAssembler::call_VM(Register oop_result,
2422 Register last_java_sp,
2423 address entry_point,
2424 Register arg_1,
2425 Register arg_2,
2426 bool check_exceptions) {
2428 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2429 pass_arg2(this, arg_2);
2430 pass_arg1(this, arg_1);
2431 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2432 }
2434 void MacroAssembler::call_VM(Register oop_result,
2435 Register last_java_sp,
2436 address entry_point,
2437 Register arg_1,
2438 Register arg_2,
2439 Register arg_3,
2440 bool check_exceptions) {
2441 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2442 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2443 pass_arg3(this, arg_3);
2444 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2445 pass_arg2(this, arg_2);
2446 pass_arg1(this, arg_1);
2447 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2448 }
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 int number_of_arguments,
2454 bool check_exceptions) {
2455 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2456 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2457 }
2459 void MacroAssembler::super_call_VM(Register oop_result,
2460 Register last_java_sp,
2461 address entry_point,
2462 Register arg_1,
2463 bool check_exceptions) {
2464 pass_arg1(this, arg_1);
2465 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2466 }
2468 void MacroAssembler::super_call_VM(Register oop_result,
2469 Register last_java_sp,
2470 address entry_point,
2471 Register arg_1,
2472 Register arg_2,
2473 bool check_exceptions) {
2475 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2476 pass_arg2(this, arg_2);
2477 pass_arg1(this, arg_1);
2478 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2479 }
2481 void MacroAssembler::super_call_VM(Register oop_result,
2482 Register last_java_sp,
2483 address entry_point,
2484 Register arg_1,
2485 Register arg_2,
2486 Register arg_3,
2487 bool check_exceptions) {
2488 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2489 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2490 pass_arg3(this, arg_3);
2491 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2492 pass_arg2(this, arg_2);
2493 pass_arg1(this, arg_1);
2494 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2495 }
2497 void MacroAssembler::call_VM_base(Register oop_result,
2498 Register java_thread,
2499 Register last_java_sp,
2500 address entry_point,
2501 int number_of_arguments,
2502 bool check_exceptions) {
2503 // determine java_thread register
2504 if (!java_thread->is_valid()) {
2505 #ifdef _LP64
2506 java_thread = r15_thread;
2507 #else
2508 java_thread = rdi;
2509 get_thread(java_thread);
2510 #endif // LP64
2511 }
2512 // determine last_java_sp register
2513 if (!last_java_sp->is_valid()) {
2514 last_java_sp = rsp;
2515 }
2516 // debugging support
2517 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2518 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2519 #ifdef ASSERT
2520 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2521 // r12 is the heapbase.
2522 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2523 #endif // ASSERT
2525 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2526 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2528 // push java thread (becomes first argument of C function)
2530 NOT_LP64(push(java_thread); number_of_arguments++);
2531 LP64_ONLY(mov(c_rarg0, r15_thread));
2533 // set last Java frame before call
2534 assert(last_java_sp != rbp, "can't use ebp/rbp");
2536 // Only interpreter should have to set fp
2537 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2539 // do the call, remove parameters
2540 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2542 // restore the thread (cannot use the pushed argument since arguments
2543 // may be overwritten by C code generated by an optimizing compiler);
2544 // however can use the register value directly if it is callee saved.
2545 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2546 // rdi & rsi (also r15) are callee saved -> nothing to do
2547 #ifdef ASSERT
2548 guarantee(java_thread != rax, "change this code");
2549 push(rax);
2550 { Label L;
2551 get_thread(rax);
2552 cmpptr(java_thread, rax);
2553 jcc(Assembler::equal, L);
2554 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2555 bind(L);
2556 }
2557 pop(rax);
2558 #endif
2559 } else {
2560 get_thread(java_thread);
2561 }
2562 // reset last Java frame
2563 // Only interpreter should have to clear fp
2564 reset_last_Java_frame(java_thread, true, false);
2566 #ifndef CC_INTERP
2567 // C++ interp handles this in the interpreter
2568 check_and_handle_popframe(java_thread);
2569 check_and_handle_earlyret(java_thread);
2570 #endif /* CC_INTERP */
2572 if (check_exceptions) {
2573 // check for pending exceptions (java_thread is set upon return)
2574 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2575 #ifndef _LP64
2576 jump_cc(Assembler::notEqual,
2577 RuntimeAddress(StubRoutines::forward_exception_entry()));
2578 #else
2579 // This used to conditionally jump to forward_exception however it is
2580 // possible if we relocate that the branch will not reach. So we must jump
2581 // around so we can always reach
2583 Label ok;
2584 jcc(Assembler::equal, ok);
2585 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2586 bind(ok);
2587 #endif // LP64
2588 }
2590 // get oop result if there is one and reset the value in the thread
2591 if (oop_result->is_valid()) {
2592 get_vm_result(oop_result, java_thread);
2593 }
2594 }
2596 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2598 // Calculate the value for last_Java_sp
2599 // somewhat subtle. call_VM does an intermediate call
2600 // which places a return address on the stack just under the
2601 // stack pointer as the user finsihed with it. This allows
2602 // use to retrieve last_Java_pc from last_Java_sp[-1].
2603 // On 32bit we then have to push additional args on the stack to accomplish
2604 // the actual requested call. On 64bit call_VM only can use register args
2605 // so the only extra space is the return address that call_VM created.
2606 // This hopefully explains the calculations here.
2608 #ifdef _LP64
2609 // We've pushed one address, correct last_Java_sp
2610 lea(rax, Address(rsp, wordSize));
2611 #else
2612 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2613 #endif // LP64
2615 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2617 }
2619 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2620 call_VM_leaf_base(entry_point, number_of_arguments);
2621 }
2623 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2624 pass_arg0(this, arg_0);
2625 call_VM_leaf(entry_point, 1);
2626 }
2628 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2630 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2631 pass_arg1(this, arg_1);
2632 pass_arg0(this, arg_0);
2633 call_VM_leaf(entry_point, 2);
2634 }
2636 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2637 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2638 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2639 pass_arg2(this, arg_2);
2640 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2641 pass_arg1(this, arg_1);
2642 pass_arg0(this, arg_0);
2643 call_VM_leaf(entry_point, 3);
2644 }
2646 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2647 pass_arg0(this, arg_0);
2648 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2649 }
2651 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2653 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2654 pass_arg1(this, arg_1);
2655 pass_arg0(this, arg_0);
2656 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2657 }
2659 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2660 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2661 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2662 pass_arg2(this, arg_2);
2663 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2664 pass_arg1(this, arg_1);
2665 pass_arg0(this, arg_0);
2666 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2667 }
2669 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2670 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2671 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2672 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2673 pass_arg3(this, arg_3);
2674 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2675 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2676 pass_arg2(this, arg_2);
2677 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2678 pass_arg1(this, arg_1);
2679 pass_arg0(this, arg_0);
2680 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2681 }
2683 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2684 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2685 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2686 verify_oop(oop_result, "broken oop in call_VM_base");
2687 }
2689 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2690 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2691 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2692 }
2694 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2695 }
2697 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2698 }
2700 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2701 if (reachable(src1)) {
2702 cmpl(as_Address(src1), imm);
2703 } else {
2704 lea(rscratch1, src1);
2705 cmpl(Address(rscratch1, 0), imm);
2706 }
2707 }
2709 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2710 assert(!src2.is_lval(), "use cmpptr");
2711 if (reachable(src2)) {
2712 cmpl(src1, as_Address(src2));
2713 } else {
2714 lea(rscratch1, src2);
2715 cmpl(src1, Address(rscratch1, 0));
2716 }
2717 }
2719 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2720 Assembler::cmpl(src1, imm);
2721 }
2723 void MacroAssembler::cmp32(Register src1, Address src2) {
2724 Assembler::cmpl(src1, src2);
2725 }
2727 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2728 ucomisd(opr1, opr2);
2730 Label L;
2731 if (unordered_is_less) {
2732 movl(dst, -1);
2733 jcc(Assembler::parity, L);
2734 jcc(Assembler::below , L);
2735 movl(dst, 0);
2736 jcc(Assembler::equal , L);
2737 increment(dst);
2738 } else { // unordered is greater
2739 movl(dst, 1);
2740 jcc(Assembler::parity, L);
2741 jcc(Assembler::above , L);
2742 movl(dst, 0);
2743 jcc(Assembler::equal , L);
2744 decrementl(dst);
2745 }
2746 bind(L);
2747 }
2749 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2750 ucomiss(opr1, opr2);
2752 Label L;
2753 if (unordered_is_less) {
2754 movl(dst, -1);
2755 jcc(Assembler::parity, L);
2756 jcc(Assembler::below , L);
2757 movl(dst, 0);
2758 jcc(Assembler::equal , L);
2759 increment(dst);
2760 } else { // unordered is greater
2761 movl(dst, 1);
2762 jcc(Assembler::parity, L);
2763 jcc(Assembler::above , L);
2764 movl(dst, 0);
2765 jcc(Assembler::equal , L);
2766 decrementl(dst);
2767 }
2768 bind(L);
2769 }
2772 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2773 if (reachable(src1)) {
2774 cmpb(as_Address(src1), imm);
2775 } else {
2776 lea(rscratch1, src1);
2777 cmpb(Address(rscratch1, 0), imm);
2778 }
2779 }
2781 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2782 #ifdef _LP64
2783 if (src2.is_lval()) {
2784 movptr(rscratch1, src2);
2785 Assembler::cmpq(src1, rscratch1);
2786 } else if (reachable(src2)) {
2787 cmpq(src1, as_Address(src2));
2788 } else {
2789 lea(rscratch1, src2);
2790 Assembler::cmpq(src1, Address(rscratch1, 0));
2791 }
2792 #else
2793 if (src2.is_lval()) {
2794 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2795 } else {
2796 cmpl(src1, as_Address(src2));
2797 }
2798 #endif // _LP64
2799 }
2801 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2802 assert(src2.is_lval(), "not a mem-mem compare");
2803 #ifdef _LP64
2804 // moves src2's literal address
2805 movptr(rscratch1, src2);
2806 Assembler::cmpq(src1, rscratch1);
2807 #else
2808 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2809 #endif // _LP64
2810 }
2812 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2813 if (reachable(adr)) {
2814 if (os::is_MP())
2815 lock();
2816 cmpxchgptr(reg, as_Address(adr));
2817 } else {
2818 lea(rscratch1, adr);
2819 if (os::is_MP())
2820 lock();
2821 cmpxchgptr(reg, Address(rscratch1, 0));
2822 }
2823 }
2825 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2826 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2827 }
2829 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2830 if (reachable(src)) {
2831 Assembler::comisd(dst, as_Address(src));
2832 } else {
2833 lea(rscratch1, src);
2834 Assembler::comisd(dst, Address(rscratch1, 0));
2835 }
2836 }
2838 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2839 if (reachable(src)) {
2840 Assembler::comiss(dst, as_Address(src));
2841 } else {
2842 lea(rscratch1, src);
2843 Assembler::comiss(dst, Address(rscratch1, 0));
2844 }
2845 }
2848 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2849 Condition negated_cond = negate_condition(cond);
2850 Label L;
2851 jcc(negated_cond, L);
2852 pushf(); // Preserve flags
2853 atomic_incl(counter_addr);
2854 popf();
2855 bind(L);
2856 }
2858 int MacroAssembler::corrected_idivl(Register reg) {
2859 // Full implementation of Java idiv and irem; checks for
2860 // special case as described in JVM spec., p.243 & p.271.
2861 // The function returns the (pc) offset of the idivl
2862 // instruction - may be needed for implicit exceptions.
2863 //
2864 // normal case special case
2865 //
2866 // input : rax,: dividend min_int
2867 // reg: divisor (may not be rax,/rdx) -1
2868 //
2869 // output: rax,: quotient (= rax, idiv reg) min_int
2870 // rdx: remainder (= rax, irem reg) 0
2871 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2872 const int min_int = 0x80000000;
2873 Label normal_case, special_case;
2875 // check for special case
2876 cmpl(rax, min_int);
2877 jcc(Assembler::notEqual, normal_case);
2878 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2879 cmpl(reg, -1);
2880 jcc(Assembler::equal, special_case);
2882 // handle normal case
2883 bind(normal_case);
2884 cdql();
2885 int idivl_offset = offset();
2886 idivl(reg);
2888 // normal and special case exit
2889 bind(special_case);
2891 return idivl_offset;
2892 }
2896 void MacroAssembler::decrementl(Register reg, int value) {
2897 if (value == min_jint) {subl(reg, value) ; return; }
2898 if (value < 0) { incrementl(reg, -value); return; }
2899 if (value == 0) { ; return; }
2900 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2901 /* else */ { subl(reg, value) ; return; }
2902 }
2904 void MacroAssembler::decrementl(Address dst, int value) {
2905 if (value == min_jint) {subl(dst, value) ; return; }
2906 if (value < 0) { incrementl(dst, -value); return; }
2907 if (value == 0) { ; return; }
2908 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2909 /* else */ { subl(dst, value) ; return; }
2910 }
2912 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2913 assert (shift_value > 0, "illegal shift value");
2914 Label _is_positive;
2915 testl (reg, reg);
2916 jcc (Assembler::positive, _is_positive);
2917 int offset = (1 << shift_value) - 1 ;
2919 if (offset == 1) {
2920 incrementl(reg);
2921 } else {
2922 addl(reg, offset);
2923 }
2925 bind (_is_positive);
2926 sarl(reg, shift_value);
2927 }
2929 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2930 if (reachable(src)) {
2931 Assembler::divsd(dst, as_Address(src));
2932 } else {
2933 lea(rscratch1, src);
2934 Assembler::divsd(dst, Address(rscratch1, 0));
2935 }
2936 }
2938 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2939 if (reachable(src)) {
2940 Assembler::divss(dst, as_Address(src));
2941 } else {
2942 lea(rscratch1, src);
2943 Assembler::divss(dst, Address(rscratch1, 0));
2944 }
2945 }
2947 // !defined(COMPILER2) is because of stupid core builds
2948 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2949 void MacroAssembler::empty_FPU_stack() {
2950 if (VM_Version::supports_mmx()) {
2951 emms();
2952 } else {
2953 for (int i = 8; i-- > 0; ) ffree(i);
2954 }
2955 }
2956 #endif // !LP64 || C1 || !C2
2959 // Defines obj, preserves var_size_in_bytes
2960 void MacroAssembler::eden_allocate(Register obj,
2961 Register var_size_in_bytes,
2962 int con_size_in_bytes,
2963 Register t1,
2964 Label& slow_case) {
2965 assert(obj == rax, "obj must be in rax, for cmpxchg");
2966 assert_different_registers(obj, var_size_in_bytes, t1);
2967 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
2968 jmp(slow_case);
2969 } else {
2970 Register end = t1;
2971 Label retry;
2972 bind(retry);
2973 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2974 movptr(obj, heap_top);
2975 if (var_size_in_bytes == noreg) {
2976 lea(end, Address(obj, con_size_in_bytes));
2977 } else {
2978 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2979 }
2980 // if end < obj then we wrapped around => object too long => slow case
2981 cmpptr(end, obj);
2982 jcc(Assembler::below, slow_case);
2983 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2984 jcc(Assembler::above, slow_case);
2985 // Compare obj with the top addr, and if still equal, store the new top addr in
2986 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2987 // it otherwise. Use lock prefix for atomicity on MPs.
2988 locked_cmpxchgptr(end, heap_top);
2989 jcc(Assembler::notEqual, retry);
2990 }
2991 }
2993 void MacroAssembler::enter() {
2994 push(rbp);
2995 mov(rbp, rsp);
2996 }
2998 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2999 void MacroAssembler::fat_nop() {
3000 if (UseAddressNop) {
3001 addr_nop_5();
3002 } else {
3003 emit_int8(0x26); // es:
3004 emit_int8(0x2e); // cs:
3005 emit_int8(0x64); // fs:
3006 emit_int8(0x65); // gs:
3007 emit_int8((unsigned char)0x90);
3008 }
3009 }
3011 void MacroAssembler::fcmp(Register tmp) {
3012 fcmp(tmp, 1, true, true);
3013 }
3015 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3016 assert(!pop_right || pop_left, "usage error");
3017 if (VM_Version::supports_cmov()) {
3018 assert(tmp == noreg, "unneeded temp");
3019 if (pop_left) {
3020 fucomip(index);
3021 } else {
3022 fucomi(index);
3023 }
3024 if (pop_right) {
3025 fpop();
3026 }
3027 } else {
3028 assert(tmp != noreg, "need temp");
3029 if (pop_left) {
3030 if (pop_right) {
3031 fcompp();
3032 } else {
3033 fcomp(index);
3034 }
3035 } else {
3036 fcom(index);
3037 }
3038 // convert FPU condition into eflags condition via rax,
3039 save_rax(tmp);
3040 fwait(); fnstsw_ax();
3041 sahf();
3042 restore_rax(tmp);
3043 }
3044 // condition codes set as follows:
3045 //
3046 // CF (corresponds to C0) if x < y
3047 // PF (corresponds to C2) if unordered
3048 // ZF (corresponds to C3) if x = y
3049 }
3051 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3052 fcmp2int(dst, unordered_is_less, 1, true, true);
3053 }
3055 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3056 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3057 Label L;
3058 if (unordered_is_less) {
3059 movl(dst, -1);
3060 jcc(Assembler::parity, L);
3061 jcc(Assembler::below , L);
3062 movl(dst, 0);
3063 jcc(Assembler::equal , L);
3064 increment(dst);
3065 } else { // unordered is greater
3066 movl(dst, 1);
3067 jcc(Assembler::parity, L);
3068 jcc(Assembler::above , L);
3069 movl(dst, 0);
3070 jcc(Assembler::equal , L);
3071 decrementl(dst);
3072 }
3073 bind(L);
3074 }
3076 void MacroAssembler::fld_d(AddressLiteral src) {
3077 fld_d(as_Address(src));
3078 }
3080 void MacroAssembler::fld_s(AddressLiteral src) {
3081 fld_s(as_Address(src));
3082 }
3084 void MacroAssembler::fld_x(AddressLiteral src) {
3085 Assembler::fld_x(as_Address(src));
3086 }
3088 void MacroAssembler::fldcw(AddressLiteral src) {
3089 Assembler::fldcw(as_Address(src));
3090 }
3092 void MacroAssembler::pow_exp_core_encoding() {
3093 // kills rax, rcx, rdx
3094 subptr(rsp,sizeof(jdouble));
3095 // computes 2^X. Stack: X ...
3096 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3097 // keep it on the thread's stack to compute 2^int(X) later
3098 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3099 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3100 fld_s(0); // Stack: X X ...
3101 frndint(); // Stack: int(X) X ...
3102 fsuba(1); // Stack: int(X) X-int(X) ...
3103 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3104 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3105 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3106 faddp(1); // Stack: 2^(X-int(X))
3107 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3108 // shift int(X)+1023 to exponent position.
3109 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3110 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3111 // values so detect them and set result to NaN.
3112 movl(rax,Address(rsp,0));
3113 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3114 addl(rax, 1023);
3115 movl(rdx,rax);
3116 shll(rax,20);
3117 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3118 addl(rdx,1);
3119 // Check that 1 < int(X)+1023+1 < 2048
3120 // in 3 steps:
3121 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3122 // 2- (int(X)+1023+1)&-2048 != 0
3123 // 3- (int(X)+1023+1)&-2048 != 1
3124 // Do 2- first because addl just updated the flags.
3125 cmov32(Assembler::equal,rax,rcx);
3126 cmpl(rdx,1);
3127 cmov32(Assembler::equal,rax,rcx);
3128 testl(rdx,rcx);
3129 cmov32(Assembler::notEqual,rax,rcx);
3130 movl(Address(rsp,4),rax);
3131 movl(Address(rsp,0),0);
3132 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3133 addptr(rsp,sizeof(jdouble));
3134 }
3136 void MacroAssembler::increase_precision() {
3137 subptr(rsp, BytesPerWord);
3138 fnstcw(Address(rsp, 0));
3139 movl(rax, Address(rsp, 0));
3140 orl(rax, 0x300);
3141 push(rax);
3142 fldcw(Address(rsp, 0));
3143 pop(rax);
3144 }
3146 void MacroAssembler::restore_precision() {
3147 fldcw(Address(rsp, 0));
3148 addptr(rsp, BytesPerWord);
3149 }
3151 void MacroAssembler::fast_pow() {
3152 // computes X^Y = 2^(Y * log2(X))
3153 // if fast computation is not possible, result is NaN. Requires
3154 // fallback from user of this macro.
3155 // increase precision for intermediate steps of the computation
3156 BLOCK_COMMENT("fast_pow {");
3157 increase_precision();
3158 fyl2x(); // Stack: (Y*log2(X)) ...
3159 pow_exp_core_encoding(); // Stack: exp(X) ...
3160 restore_precision();
3161 BLOCK_COMMENT("} fast_pow");
3162 }
3164 void MacroAssembler::fast_exp() {
3165 // computes exp(X) = 2^(X * log2(e))
3166 // if fast computation is not possible, result is NaN. Requires
3167 // fallback from user of this macro.
3168 // increase precision for intermediate steps of the computation
3169 increase_precision();
3170 fldl2e(); // Stack: log2(e) X ...
3171 fmulp(1); // Stack: (X*log2(e)) ...
3172 pow_exp_core_encoding(); // Stack: exp(X) ...
3173 restore_precision();
3174 }
3176 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3177 // kills rax, rcx, rdx
3178 // pow and exp needs 2 extra registers on the fpu stack.
3179 Label slow_case, done;
3180 Register tmp = noreg;
3181 if (!VM_Version::supports_cmov()) {
3182 // fcmp needs a temporary so preserve rdx,
3183 tmp = rdx;
3184 }
3185 Register tmp2 = rax;
3186 Register tmp3 = rcx;
3188 if (is_exp) {
3189 // Stack: X
3190 fld_s(0); // duplicate argument for runtime call. Stack: X X
3191 fast_exp(); // Stack: exp(X) X
3192 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3193 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3194 jcc(Assembler::parity, slow_case);
3195 // get rid of duplicate argument. Stack: exp(X)
3196 if (num_fpu_regs_in_use > 0) {
3197 fxch();
3198 fpop();
3199 } else {
3200 ffree(1);
3201 }
3202 jmp(done);
3203 } else {
3204 // Stack: X Y
3205 Label x_negative, y_not_2;
3207 static double two = 2.0;
3208 ExternalAddress two_addr((address)&two);
3210 // constant maybe too far on 64 bit
3211 lea(tmp2, two_addr);
3212 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3213 fcmp(tmp, 2, true, false); // Stack: X Y
3214 jcc(Assembler::parity, y_not_2);
3215 jcc(Assembler::notEqual, y_not_2);
3217 fxch(); fpop(); // Stack: X
3218 fmul(0); // Stack: X*X
3220 jmp(done);
3222 bind(y_not_2);
3224 fldz(); // Stack: 0 X Y
3225 fcmp(tmp, 1, true, false); // Stack: X Y
3226 jcc(Assembler::above, x_negative);
3228 // X >= 0
3230 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3231 fld_s(1); // Stack: X Y X Y
3232 fast_pow(); // Stack: X^Y X Y
3233 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3234 // X^Y not equal to itself: X^Y is NaN go to slow case.
3235 jcc(Assembler::parity, slow_case);
3236 // get rid of duplicate arguments. Stack: X^Y
3237 if (num_fpu_regs_in_use > 0) {
3238 fxch(); fpop();
3239 fxch(); fpop();
3240 } else {
3241 ffree(2);
3242 ffree(1);
3243 }
3244 jmp(done);
3246 // X <= 0
3247 bind(x_negative);
3249 fld_s(1); // Stack: Y X Y
3250 frndint(); // Stack: int(Y) X Y
3251 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3252 jcc(Assembler::notEqual, slow_case);
3254 subptr(rsp, 8);
3256 // For X^Y, when X < 0, Y has to be an integer and the final
3257 // result depends on whether it's odd or even. We just checked
3258 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3259 // integer to test its parity. If int(Y) is huge and doesn't fit
3260 // in the 64 bit integer range, the integer indefinite value will
3261 // end up in the gp registers. Huge numbers are all even, the
3262 // integer indefinite number is even so it's fine.
3264 #ifdef ASSERT
3265 // Let's check we don't end up with an integer indefinite number
3266 // when not expected. First test for huge numbers: check whether
3267 // int(Y)+1 == int(Y) which is true for very large numbers and
3268 // those are all even. A 64 bit integer is guaranteed to not
3269 // overflow for numbers where y+1 != y (when precision is set to
3270 // double precision).
3271 Label y_not_huge;
3273 fld1(); // Stack: 1 int(Y) X Y
3274 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3276 #ifdef _LP64
3277 // trip to memory to force the precision down from double extended
3278 // precision
3279 fstp_d(Address(rsp, 0));
3280 fld_d(Address(rsp, 0));
3281 #endif
3283 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3284 #endif
3286 // move int(Y) as 64 bit integer to thread's stack
3287 fistp_d(Address(rsp,0)); // Stack: X Y
3289 #ifdef ASSERT
3290 jcc(Assembler::notEqual, y_not_huge);
3292 // Y is huge so we know it's even. It may not fit in a 64 bit
3293 // integer and we don't want the debug code below to see the
3294 // integer indefinite value so overwrite int(Y) on the thread's
3295 // stack with 0.
3296 movl(Address(rsp, 0), 0);
3297 movl(Address(rsp, 4), 0);
3299 bind(y_not_huge);
3300 #endif
3302 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3303 fld_s(1); // Stack: X Y X Y
3304 fabs(); // Stack: abs(X) Y X Y
3305 fast_pow(); // Stack: abs(X)^Y X Y
3306 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3307 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3309 pop(tmp2);
3310 NOT_LP64(pop(tmp3));
3311 jcc(Assembler::parity, slow_case);
3313 #ifdef ASSERT
3314 // Check that int(Y) is not integer indefinite value (int
3315 // overflow). Shouldn't happen because for values that would
3316 // overflow, 1+int(Y)==Y which was tested earlier.
3317 #ifndef _LP64
3318 {
3319 Label integer;
3320 testl(tmp2, tmp2);
3321 jcc(Assembler::notZero, integer);
3322 cmpl(tmp3, 0x80000000);
3323 jcc(Assembler::notZero, integer);
3324 STOP("integer indefinite value shouldn't be seen here");
3325 bind(integer);
3326 }
3327 #else
3328 {
3329 Label integer;
3330 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3331 shlq(tmp3, 1);
3332 jcc(Assembler::carryClear, integer);
3333 jcc(Assembler::notZero, integer);
3334 STOP("integer indefinite value shouldn't be seen here");
3335 bind(integer);
3336 }
3337 #endif
3338 #endif
3340 // get rid of duplicate arguments. Stack: X^Y
3341 if (num_fpu_regs_in_use > 0) {
3342 fxch(); fpop();
3343 fxch(); fpop();
3344 } else {
3345 ffree(2);
3346 ffree(1);
3347 }
3349 testl(tmp2, 1);
3350 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3351 // X <= 0, Y even: X^Y = -abs(X)^Y
3353 fchs(); // Stack: -abs(X)^Y Y
3354 jmp(done);
3355 }
3357 // slow case: runtime call
3358 bind(slow_case);
3360 fpop(); // pop incorrect result or int(Y)
3362 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3363 is_exp ? 1 : 2, num_fpu_regs_in_use);
3365 // Come here with result in F-TOS
3366 bind(done);
3367 }
3369 void MacroAssembler::fpop() {
3370 ffree();
3371 fincstp();
3372 }
3374 void MacroAssembler::fremr(Register tmp) {
3375 save_rax(tmp);
3376 { Label L;
3377 bind(L);
3378 fprem();
3379 fwait(); fnstsw_ax();
3380 #ifdef _LP64
3381 testl(rax, 0x400);
3382 jcc(Assembler::notEqual, L);
3383 #else
3384 sahf();
3385 jcc(Assembler::parity, L);
3386 #endif // _LP64
3387 }
3388 restore_rax(tmp);
3389 // Result is in ST0.
3390 // Note: fxch & fpop to get rid of ST1
3391 // (otherwise FPU stack could overflow eventually)
3392 fxch(1);
3393 fpop();
3394 }
3397 void MacroAssembler::incrementl(AddressLiteral dst) {
3398 if (reachable(dst)) {
3399 incrementl(as_Address(dst));
3400 } else {
3401 lea(rscratch1, dst);
3402 incrementl(Address(rscratch1, 0));
3403 }
3404 }
3406 void MacroAssembler::incrementl(ArrayAddress dst) {
3407 incrementl(as_Address(dst));
3408 }
3410 void MacroAssembler::incrementl(Register reg, int value) {
3411 if (value == min_jint) {addl(reg, value) ; return; }
3412 if (value < 0) { decrementl(reg, -value); return; }
3413 if (value == 0) { ; return; }
3414 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3415 /* else */ { addl(reg, value) ; return; }
3416 }
3418 void MacroAssembler::incrementl(Address dst, int value) {
3419 if (value == min_jint) {addl(dst, value) ; return; }
3420 if (value < 0) { decrementl(dst, -value); return; }
3421 if (value == 0) { ; return; }
3422 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3423 /* else */ { addl(dst, value) ; return; }
3424 }
3426 void MacroAssembler::jump(AddressLiteral dst) {
3427 if (reachable(dst)) {
3428 jmp_literal(dst.target(), dst.rspec());
3429 } else {
3430 lea(rscratch1, dst);
3431 jmp(rscratch1);
3432 }
3433 }
3435 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3436 if (reachable(dst)) {
3437 InstructionMark im(this);
3438 relocate(dst.reloc());
3439 const int short_size = 2;
3440 const int long_size = 6;
3441 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3442 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3443 // 0111 tttn #8-bit disp
3444 emit_int8(0x70 | cc);
3445 emit_int8((offs - short_size) & 0xFF);
3446 } else {
3447 // 0000 1111 1000 tttn #32-bit disp
3448 emit_int8(0x0F);
3449 emit_int8((unsigned char)(0x80 | cc));
3450 emit_int32(offs - long_size);
3451 }
3452 } else {
3453 #ifdef ASSERT
3454 warning("reversing conditional branch");
3455 #endif /* ASSERT */
3456 Label skip;
3457 jccb(reverse[cc], skip);
3458 lea(rscratch1, dst);
3459 Assembler::jmp(rscratch1);
3460 bind(skip);
3461 }
3462 }
3464 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3465 if (reachable(src)) {
3466 Assembler::ldmxcsr(as_Address(src));
3467 } else {
3468 lea(rscratch1, src);
3469 Assembler::ldmxcsr(Address(rscratch1, 0));
3470 }
3471 }
3473 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3474 int off;
3475 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3476 off = offset();
3477 movsbl(dst, src); // movsxb
3478 } else {
3479 off = load_unsigned_byte(dst, src);
3480 shll(dst, 24);
3481 sarl(dst, 24);
3482 }
3483 return off;
3484 }
3486 // Note: load_signed_short used to be called load_signed_word.
3487 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3488 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3489 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3490 int MacroAssembler::load_signed_short(Register dst, Address src) {
3491 int off;
3492 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3493 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3494 // version but this is what 64bit has always done. This seems to imply
3495 // that users are only using 32bits worth.
3496 off = offset();
3497 movswl(dst, src); // movsxw
3498 } else {
3499 off = load_unsigned_short(dst, src);
3500 shll(dst, 16);
3501 sarl(dst, 16);
3502 }
3503 return off;
3504 }
3506 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3507 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3508 // and "3.9 Partial Register Penalties", p. 22).
3509 int off;
3510 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3511 off = offset();
3512 movzbl(dst, src); // movzxb
3513 } else {
3514 xorl(dst, dst);
3515 off = offset();
3516 movb(dst, src);
3517 }
3518 return off;
3519 }
3521 // Note: load_unsigned_short used to be called load_unsigned_word.
3522 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3523 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3524 // and "3.9 Partial Register Penalties", p. 22).
3525 int off;
3526 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3527 off = offset();
3528 movzwl(dst, src); // movzxw
3529 } else {
3530 xorl(dst, dst);
3531 off = offset();
3532 movw(dst, src);
3533 }
3534 return off;
3535 }
3537 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3538 switch (size_in_bytes) {
3539 #ifndef _LP64
3540 case 8:
3541 assert(dst2 != noreg, "second dest register required");
3542 movl(dst, src);
3543 movl(dst2, src.plus_disp(BytesPerInt));
3544 break;
3545 #else
3546 case 8: movq(dst, src); break;
3547 #endif
3548 case 4: movl(dst, src); break;
3549 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3550 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3551 default: ShouldNotReachHere();
3552 }
3553 }
3555 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3556 switch (size_in_bytes) {
3557 #ifndef _LP64
3558 case 8:
3559 assert(src2 != noreg, "second source register required");
3560 movl(dst, src);
3561 movl(dst.plus_disp(BytesPerInt), src2);
3562 break;
3563 #else
3564 case 8: movq(dst, src); break;
3565 #endif
3566 case 4: movl(dst, src); break;
3567 case 2: movw(dst, src); break;
3568 case 1: movb(dst, src); break;
3569 default: ShouldNotReachHere();
3570 }
3571 }
3573 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3574 if (reachable(dst)) {
3575 movl(as_Address(dst), src);
3576 } else {
3577 lea(rscratch1, dst);
3578 movl(Address(rscratch1, 0), src);
3579 }
3580 }
3582 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3583 if (reachable(src)) {
3584 movl(dst, as_Address(src));
3585 } else {
3586 lea(rscratch1, src);
3587 movl(dst, Address(rscratch1, 0));
3588 }
3589 }
3591 // C++ bool manipulation
3593 void MacroAssembler::movbool(Register dst, Address src) {
3594 if(sizeof(bool) == 1)
3595 movb(dst, src);
3596 else if(sizeof(bool) == 2)
3597 movw(dst, src);
3598 else if(sizeof(bool) == 4)
3599 movl(dst, src);
3600 else
3601 // unsupported
3602 ShouldNotReachHere();
3603 }
3605 void MacroAssembler::movbool(Address dst, bool boolconst) {
3606 if(sizeof(bool) == 1)
3607 movb(dst, (int) boolconst);
3608 else if(sizeof(bool) == 2)
3609 movw(dst, (int) boolconst);
3610 else if(sizeof(bool) == 4)
3611 movl(dst, (int) boolconst);
3612 else
3613 // unsupported
3614 ShouldNotReachHere();
3615 }
3617 void MacroAssembler::movbool(Address dst, Register src) {
3618 if(sizeof(bool) == 1)
3619 movb(dst, src);
3620 else if(sizeof(bool) == 2)
3621 movw(dst, src);
3622 else if(sizeof(bool) == 4)
3623 movl(dst, src);
3624 else
3625 // unsupported
3626 ShouldNotReachHere();
3627 }
3629 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3630 movb(as_Address(dst), src);
3631 }
3633 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3634 if (reachable(src)) {
3635 movdl(dst, as_Address(src));
3636 } else {
3637 lea(rscratch1, src);
3638 movdl(dst, Address(rscratch1, 0));
3639 }
3640 }
3642 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3643 if (reachable(src)) {
3644 movq(dst, as_Address(src));
3645 } else {
3646 lea(rscratch1, src);
3647 movq(dst, Address(rscratch1, 0));
3648 }
3649 }
3651 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3652 if (reachable(src)) {
3653 if (UseXmmLoadAndClearUpper) {
3654 movsd (dst, as_Address(src));
3655 } else {
3656 movlpd(dst, as_Address(src));
3657 }
3658 } else {
3659 lea(rscratch1, src);
3660 if (UseXmmLoadAndClearUpper) {
3661 movsd (dst, Address(rscratch1, 0));
3662 } else {
3663 movlpd(dst, Address(rscratch1, 0));
3664 }
3665 }
3666 }
3668 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3669 if (reachable(src)) {
3670 movss(dst, as_Address(src));
3671 } else {
3672 lea(rscratch1, src);
3673 movss(dst, Address(rscratch1, 0));
3674 }
3675 }
3677 void MacroAssembler::movptr(Register dst, Register src) {
3678 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3679 }
3681 void MacroAssembler::movptr(Register dst, Address src) {
3682 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3683 }
3685 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3686 void MacroAssembler::movptr(Register dst, intptr_t src) {
3687 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3688 }
3690 void MacroAssembler::movptr(Address dst, Register src) {
3691 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3692 }
3694 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3695 if (reachable(src)) {
3696 Assembler::movdqu(dst, as_Address(src));
3697 } else {
3698 lea(rscratch1, src);
3699 Assembler::movdqu(dst, Address(rscratch1, 0));
3700 }
3701 }
3703 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3704 if (reachable(src)) {
3705 Assembler::movdqa(dst, as_Address(src));
3706 } else {
3707 lea(rscratch1, src);
3708 Assembler::movdqa(dst, Address(rscratch1, 0));
3709 }
3710 }
3712 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3713 if (reachable(src)) {
3714 Assembler::movsd(dst, as_Address(src));
3715 } else {
3716 lea(rscratch1, src);
3717 Assembler::movsd(dst, Address(rscratch1, 0));
3718 }
3719 }
3721 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3722 if (reachable(src)) {
3723 Assembler::movss(dst, as_Address(src));
3724 } else {
3725 lea(rscratch1, src);
3726 Assembler::movss(dst, Address(rscratch1, 0));
3727 }
3728 }
3730 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3731 if (reachable(src)) {
3732 Assembler::mulsd(dst, as_Address(src));
3733 } else {
3734 lea(rscratch1, src);
3735 Assembler::mulsd(dst, Address(rscratch1, 0));
3736 }
3737 }
3739 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3740 if (reachable(src)) {
3741 Assembler::mulss(dst, as_Address(src));
3742 } else {
3743 lea(rscratch1, src);
3744 Assembler::mulss(dst, Address(rscratch1, 0));
3745 }
3746 }
3748 void MacroAssembler::null_check(Register reg, int offset) {
3749 if (needs_explicit_null_check(offset)) {
3750 // provoke OS NULL exception if reg = NULL by
3751 // accessing M[reg] w/o changing any (non-CC) registers
3752 // NOTE: cmpl is plenty here to provoke a segv
3753 cmpptr(rax, Address(reg, 0));
3754 // Note: should probably use testl(rax, Address(reg, 0));
3755 // may be shorter code (however, this version of
3756 // testl needs to be implemented first)
3757 } else {
3758 // nothing to do, (later) access of M[reg + offset]
3759 // will provoke OS NULL exception if reg = NULL
3760 }
3761 }
3763 void MacroAssembler::os_breakpoint() {
3764 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3765 // (e.g., MSVC can't call ps() otherwise)
3766 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3767 }
3769 void MacroAssembler::pop_CPU_state() {
3770 pop_FPU_state();
3771 pop_IU_state();
3772 }
3774 void MacroAssembler::pop_FPU_state() {
3775 NOT_LP64(frstor(Address(rsp, 0));)
3776 LP64_ONLY(fxrstor(Address(rsp, 0));)
3777 addptr(rsp, FPUStateSizeInWords * wordSize);
3778 }
3780 void MacroAssembler::pop_IU_state() {
3781 popa();
3782 LP64_ONLY(addq(rsp, 8));
3783 popf();
3784 }
3786 // Save Integer and Float state
3787 // Warning: Stack must be 16 byte aligned (64bit)
3788 void MacroAssembler::push_CPU_state() {
3789 push_IU_state();
3790 push_FPU_state();
3791 }
3793 void MacroAssembler::push_FPU_state() {
3794 subptr(rsp, FPUStateSizeInWords * wordSize);
3795 #ifndef _LP64
3796 fnsave(Address(rsp, 0));
3797 fwait();
3798 #else
3799 fxsave(Address(rsp, 0));
3800 #endif // LP64
3801 }
3803 void MacroAssembler::push_IU_state() {
3804 // Push flags first because pusha kills them
3805 pushf();
3806 // Make sure rsp stays 16-byte aligned
3807 LP64_ONLY(subq(rsp, 8));
3808 pusha();
3809 }
3811 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3812 // determine java_thread register
3813 if (!java_thread->is_valid()) {
3814 java_thread = rdi;
3815 get_thread(java_thread);
3816 }
3817 // we must set sp to zero to clear frame
3818 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3819 if (clear_fp) {
3820 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3821 }
3823 if (clear_pc)
3824 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3826 }
3828 void MacroAssembler::restore_rax(Register tmp) {
3829 if (tmp == noreg) pop(rax);
3830 else if (tmp != rax) mov(rax, tmp);
3831 }
3833 void MacroAssembler::round_to(Register reg, int modulus) {
3834 addptr(reg, modulus - 1);
3835 andptr(reg, -modulus);
3836 }
3838 void MacroAssembler::save_rax(Register tmp) {
3839 if (tmp == noreg) push(rax);
3840 else if (tmp != rax) mov(tmp, rax);
3841 }
3843 // Write serialization page so VM thread can do a pseudo remote membar.
3844 // We use the current thread pointer to calculate a thread specific
3845 // offset to write to within the page. This minimizes bus traffic
3846 // due to cache line collision.
3847 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3848 movl(tmp, thread);
3849 shrl(tmp, os::get_serialize_page_shift_count());
3850 andl(tmp, (os::vm_page_size() - sizeof(int)));
3852 Address index(noreg, tmp, Address::times_1);
3853 ExternalAddress page(os::get_memory_serialize_page());
3855 // Size of store must match masking code above
3856 movl(as_Address(ArrayAddress(page, index)), tmp);
3857 }
3859 // Calls to C land
3860 //
3861 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3862 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3863 // has to be reset to 0. This is required to allow proper stack traversal.
3864 void MacroAssembler::set_last_Java_frame(Register java_thread,
3865 Register last_java_sp,
3866 Register last_java_fp,
3867 address last_java_pc) {
3868 // determine java_thread register
3869 if (!java_thread->is_valid()) {
3870 java_thread = rdi;
3871 get_thread(java_thread);
3872 }
3873 // determine last_java_sp register
3874 if (!last_java_sp->is_valid()) {
3875 last_java_sp = rsp;
3876 }
3878 // last_java_fp is optional
3880 if (last_java_fp->is_valid()) {
3881 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3882 }
3884 // last_java_pc is optional
3886 if (last_java_pc != NULL) {
3887 lea(Address(java_thread,
3888 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3889 InternalAddress(last_java_pc));
3891 }
3892 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3893 }
3895 void MacroAssembler::shlptr(Register dst, int imm8) {
3896 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3897 }
3899 void MacroAssembler::shrptr(Register dst, int imm8) {
3900 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3901 }
3903 void MacroAssembler::sign_extend_byte(Register reg) {
3904 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3905 movsbl(reg, reg); // movsxb
3906 } else {
3907 shll(reg, 24);
3908 sarl(reg, 24);
3909 }
3910 }
3912 void MacroAssembler::sign_extend_short(Register reg) {
3913 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3914 movswl(reg, reg); // movsxw
3915 } else {
3916 shll(reg, 16);
3917 sarl(reg, 16);
3918 }
3919 }
3921 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3922 assert(reachable(src), "Address should be reachable");
3923 testl(dst, as_Address(src));
3924 }
3926 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3927 if (reachable(src)) {
3928 Assembler::sqrtsd(dst, as_Address(src));
3929 } else {
3930 lea(rscratch1, src);
3931 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3932 }
3933 }
3935 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3936 if (reachable(src)) {
3937 Assembler::sqrtss(dst, as_Address(src));
3938 } else {
3939 lea(rscratch1, src);
3940 Assembler::sqrtss(dst, Address(rscratch1, 0));
3941 }
3942 }
3944 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3945 if (reachable(src)) {
3946 Assembler::subsd(dst, as_Address(src));
3947 } else {
3948 lea(rscratch1, src);
3949 Assembler::subsd(dst, Address(rscratch1, 0));
3950 }
3951 }
3953 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3954 if (reachable(src)) {
3955 Assembler::subss(dst, as_Address(src));
3956 } else {
3957 lea(rscratch1, src);
3958 Assembler::subss(dst, Address(rscratch1, 0));
3959 }
3960 }
3962 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3963 if (reachable(src)) {
3964 Assembler::ucomisd(dst, as_Address(src));
3965 } else {
3966 lea(rscratch1, src);
3967 Assembler::ucomisd(dst, Address(rscratch1, 0));
3968 }
3969 }
3971 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3972 if (reachable(src)) {
3973 Assembler::ucomiss(dst, as_Address(src));
3974 } else {
3975 lea(rscratch1, src);
3976 Assembler::ucomiss(dst, Address(rscratch1, 0));
3977 }
3978 }
3980 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3981 // Used in sign-bit flipping with aligned address.
3982 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3983 if (reachable(src)) {
3984 Assembler::xorpd(dst, as_Address(src));
3985 } else {
3986 lea(rscratch1, src);
3987 Assembler::xorpd(dst, Address(rscratch1, 0));
3988 }
3989 }
3991 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3992 // Used in sign-bit flipping with aligned address.
3993 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3994 if (reachable(src)) {
3995 Assembler::xorps(dst, as_Address(src));
3996 } else {
3997 lea(rscratch1, src);
3998 Assembler::xorps(dst, Address(rscratch1, 0));
3999 }
4000 }
4002 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4003 // Used in sign-bit flipping with aligned address.
4004 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4005 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4006 if (reachable(src)) {
4007 Assembler::pshufb(dst, as_Address(src));
4008 } else {
4009 lea(rscratch1, src);
4010 Assembler::pshufb(dst, Address(rscratch1, 0));
4011 }
4012 }
4014 // AVX 3-operands instructions
4016 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4017 if (reachable(src)) {
4018 vaddsd(dst, nds, as_Address(src));
4019 } else {
4020 lea(rscratch1, src);
4021 vaddsd(dst, nds, Address(rscratch1, 0));
4022 }
4023 }
4025 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4026 if (reachable(src)) {
4027 vaddss(dst, nds, as_Address(src));
4028 } else {
4029 lea(rscratch1, src);
4030 vaddss(dst, nds, Address(rscratch1, 0));
4031 }
4032 }
4034 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4035 if (reachable(src)) {
4036 vandpd(dst, nds, as_Address(src), vector256);
4037 } else {
4038 lea(rscratch1, src);
4039 vandpd(dst, nds, Address(rscratch1, 0), vector256);
4040 }
4041 }
4043 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4044 if (reachable(src)) {
4045 vandps(dst, nds, as_Address(src), vector256);
4046 } else {
4047 lea(rscratch1, src);
4048 vandps(dst, nds, Address(rscratch1, 0), vector256);
4049 }
4050 }
4052 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4053 if (reachable(src)) {
4054 vdivsd(dst, nds, as_Address(src));
4055 } else {
4056 lea(rscratch1, src);
4057 vdivsd(dst, nds, Address(rscratch1, 0));
4058 }
4059 }
4061 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4062 if (reachable(src)) {
4063 vdivss(dst, nds, as_Address(src));
4064 } else {
4065 lea(rscratch1, src);
4066 vdivss(dst, nds, Address(rscratch1, 0));
4067 }
4068 }
4070 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4071 if (reachable(src)) {
4072 vmulsd(dst, nds, as_Address(src));
4073 } else {
4074 lea(rscratch1, src);
4075 vmulsd(dst, nds, Address(rscratch1, 0));
4076 }
4077 }
4079 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4080 if (reachable(src)) {
4081 vmulss(dst, nds, as_Address(src));
4082 } else {
4083 lea(rscratch1, src);
4084 vmulss(dst, nds, Address(rscratch1, 0));
4085 }
4086 }
4088 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4089 if (reachable(src)) {
4090 vsubsd(dst, nds, as_Address(src));
4091 } else {
4092 lea(rscratch1, src);
4093 vsubsd(dst, nds, Address(rscratch1, 0));
4094 }
4095 }
4097 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4098 if (reachable(src)) {
4099 vsubss(dst, nds, as_Address(src));
4100 } else {
4101 lea(rscratch1, src);
4102 vsubss(dst, nds, Address(rscratch1, 0));
4103 }
4104 }
4106 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4107 if (reachable(src)) {
4108 vxorpd(dst, nds, as_Address(src), vector256);
4109 } else {
4110 lea(rscratch1, src);
4111 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
4112 }
4113 }
4115 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4116 if (reachable(src)) {
4117 vxorps(dst, nds, as_Address(src), vector256);
4118 } else {
4119 lea(rscratch1, src);
4120 vxorps(dst, nds, Address(rscratch1, 0), vector256);
4121 }
4122 }
4125 //////////////////////////////////////////////////////////////////////////////////
4126 #if INCLUDE_ALL_GCS
4128 void MacroAssembler::g1_write_barrier_pre(Register obj,
4129 Register pre_val,
4130 Register thread,
4131 Register tmp,
4132 bool tosca_live,
4133 bool expand_call) {
4135 // If expand_call is true then we expand the call_VM_leaf macro
4136 // directly to skip generating the check by
4137 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4139 #ifdef _LP64
4140 assert(thread == r15_thread, "must be");
4141 #endif // _LP64
4143 Label done;
4144 Label runtime;
4146 assert(pre_val != noreg, "check this code");
4148 if (obj != noreg) {
4149 assert_different_registers(obj, pre_val, tmp);
4150 assert(pre_val != rax, "check this code");
4151 }
4153 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4154 PtrQueue::byte_offset_of_active()));
4155 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4156 PtrQueue::byte_offset_of_index()));
4157 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4158 PtrQueue::byte_offset_of_buf()));
4161 // Is marking active?
4162 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4163 cmpl(in_progress, 0);
4164 } else {
4165 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4166 cmpb(in_progress, 0);
4167 }
4168 jcc(Assembler::equal, done);
4170 // Do we need to load the previous value?
4171 if (obj != noreg) {
4172 load_heap_oop(pre_val, Address(obj, 0));
4173 }
4175 // Is the previous value null?
4176 cmpptr(pre_val, (int32_t) NULL_WORD);
4177 jcc(Assembler::equal, done);
4179 // Can we store original value in the thread's buffer?
4180 // Is index == 0?
4181 // (The index field is typed as size_t.)
4183 movptr(tmp, index); // tmp := *index_adr
4184 cmpptr(tmp, 0); // tmp == 0?
4185 jcc(Assembler::equal, runtime); // If yes, goto runtime
4187 subptr(tmp, wordSize); // tmp := tmp - wordSize
4188 movptr(index, tmp); // *index_adr := tmp
4189 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4191 // Record the previous value
4192 movptr(Address(tmp, 0), pre_val);
4193 jmp(done);
4195 bind(runtime);
4196 // save the live input values
4197 if(tosca_live) push(rax);
4199 if (obj != noreg && obj != rax)
4200 push(obj);
4202 if (pre_val != rax)
4203 push(pre_val);
4205 // Calling the runtime using the regular call_VM_leaf mechanism generates
4206 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4207 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4208 //
4209 // If we care generating the pre-barrier without a frame (e.g. in the
4210 // intrinsified Reference.get() routine) then ebp might be pointing to
4211 // the caller frame and so this check will most likely fail at runtime.
4212 //
4213 // Expanding the call directly bypasses the generation of the check.
4214 // So when we do not have have a full interpreter frame on the stack
4215 // expand_call should be passed true.
4217 NOT_LP64( push(thread); )
4219 if (expand_call) {
4220 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4221 pass_arg1(this, thread);
4222 pass_arg0(this, pre_val);
4223 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4224 } else {
4225 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4226 }
4228 NOT_LP64( pop(thread); )
4230 // save the live input values
4231 if (pre_val != rax)
4232 pop(pre_val);
4234 if (obj != noreg && obj != rax)
4235 pop(obj);
4237 if(tosca_live) pop(rax);
4239 bind(done);
4240 }
4242 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4243 Register new_val,
4244 Register thread,
4245 Register tmp,
4246 Register tmp2) {
4247 #ifdef _LP64
4248 assert(thread == r15_thread, "must be");
4249 #endif // _LP64
4251 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4252 PtrQueue::byte_offset_of_index()));
4253 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4254 PtrQueue::byte_offset_of_buf()));
4256 BarrierSet* bs = Universe::heap()->barrier_set();
4257 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4258 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4260 Label done;
4261 Label runtime;
4263 // Does store cross heap regions?
4265 movptr(tmp, store_addr);
4266 xorptr(tmp, new_val);
4267 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4268 jcc(Assembler::equal, done);
4270 // crosses regions, storing NULL?
4272 cmpptr(new_val, (int32_t) NULL_WORD);
4273 jcc(Assembler::equal, done);
4275 // storing region crossing non-NULL, is card already dirty?
4277 const Register card_addr = tmp;
4278 const Register cardtable = tmp2;
4280 movptr(card_addr, store_addr);
4281 shrptr(card_addr, CardTableModRefBS::card_shift);
4282 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4283 // a valid address and therefore is not properly handled by the relocation code.
4284 movptr(cardtable, (intptr_t)ct->byte_map_base);
4285 addptr(card_addr, cardtable);
4287 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4288 jcc(Assembler::equal, done);
4290 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4291 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4292 jcc(Assembler::equal, done);
4295 // storing a region crossing, non-NULL oop, card is clean.
4296 // dirty card and log.
4298 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4300 cmpl(queue_index, 0);
4301 jcc(Assembler::equal, runtime);
4302 subl(queue_index, wordSize);
4303 movptr(tmp2, buffer);
4304 #ifdef _LP64
4305 movslq(rscratch1, queue_index);
4306 addq(tmp2, rscratch1);
4307 movq(Address(tmp2, 0), card_addr);
4308 #else
4309 addl(tmp2, queue_index);
4310 movl(Address(tmp2, 0), card_addr);
4311 #endif
4312 jmp(done);
4314 bind(runtime);
4315 // save the live input values
4316 push(store_addr);
4317 push(new_val);
4318 #ifdef _LP64
4319 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4320 #else
4321 push(thread);
4322 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4323 pop(thread);
4324 #endif
4325 pop(new_val);
4326 pop(store_addr);
4328 bind(done);
4329 }
4331 #endif // INCLUDE_ALL_GCS
4332 //////////////////////////////////////////////////////////////////////////////////
4335 void MacroAssembler::store_check(Register obj) {
4336 // Does a store check for the oop in register obj. The content of
4337 // register obj is destroyed afterwards.
4338 store_check_part_1(obj);
4339 store_check_part_2(obj);
4340 }
4342 void MacroAssembler::store_check(Register obj, Address dst) {
4343 store_check(obj);
4344 }
4347 // split the store check operation so that other instructions can be scheduled inbetween
4348 void MacroAssembler::store_check_part_1(Register obj) {
4349 BarrierSet* bs = Universe::heap()->barrier_set();
4350 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4351 shrptr(obj, CardTableModRefBS::card_shift);
4352 }
4354 void MacroAssembler::store_check_part_2(Register obj) {
4355 BarrierSet* bs = Universe::heap()->barrier_set();
4356 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4357 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4358 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4360 // The calculation for byte_map_base is as follows:
4361 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4362 // So this essentially converts an address to a displacement and it will
4363 // never need to be relocated. On 64bit however the value may be too
4364 // large for a 32bit displacement.
4365 intptr_t disp = (intptr_t) ct->byte_map_base;
4366 if (is_simm32(disp)) {
4367 Address cardtable(noreg, obj, Address::times_1, disp);
4368 movb(cardtable, 0);
4369 } else {
4370 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4371 // displacement and done in a single instruction given favorable mapping and a
4372 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4373 // entry and that entry is not properly handled by the relocation code.
4374 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4375 Address index(noreg, obj, Address::times_1);
4376 movb(as_Address(ArrayAddress(cardtable, index)), 0);
4377 }
4378 }
4380 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4381 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4382 }
4384 // Force generation of a 4 byte immediate value even if it fits into 8bit
4385 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4386 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4387 }
4389 void MacroAssembler::subptr(Register dst, Register src) {
4390 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4391 }
4393 // C++ bool manipulation
4394 void MacroAssembler::testbool(Register dst) {
4395 if(sizeof(bool) == 1)
4396 testb(dst, 0xff);
4397 else if(sizeof(bool) == 2) {
4398 // testw implementation needed for two byte bools
4399 ShouldNotReachHere();
4400 } else if(sizeof(bool) == 4)
4401 testl(dst, dst);
4402 else
4403 // unsupported
4404 ShouldNotReachHere();
4405 }
4407 void MacroAssembler::testptr(Register dst, Register src) {
4408 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4409 }
4411 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4412 void MacroAssembler::tlab_allocate(Register obj,
4413 Register var_size_in_bytes,
4414 int con_size_in_bytes,
4415 Register t1,
4416 Register t2,
4417 Label& slow_case) {
4418 assert_different_registers(obj, t1, t2);
4419 assert_different_registers(obj, var_size_in_bytes, t1);
4420 Register end = t2;
4421 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4423 verify_tlab();
4425 NOT_LP64(get_thread(thread));
4427 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4428 if (var_size_in_bytes == noreg) {
4429 lea(end, Address(obj, con_size_in_bytes));
4430 } else {
4431 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4432 }
4433 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4434 jcc(Assembler::above, slow_case);
4436 // update the tlab top pointer
4437 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4439 // recover var_size_in_bytes if necessary
4440 if (var_size_in_bytes == end) {
4441 subptr(var_size_in_bytes, obj);
4442 }
4443 verify_tlab();
4444 }
4446 // Preserves rbx, and rdx.
4447 Register MacroAssembler::tlab_refill(Label& retry,
4448 Label& try_eden,
4449 Label& slow_case) {
4450 Register top = rax;
4451 Register t1 = rcx;
4452 Register t2 = rsi;
4453 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4454 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4455 Label do_refill, discard_tlab;
4457 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4458 // No allocation in the shared eden.
4459 jmp(slow_case);
4460 }
4462 NOT_LP64(get_thread(thread_reg));
4464 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4465 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4467 // calculate amount of free space
4468 subptr(t1, top);
4469 shrptr(t1, LogHeapWordSize);
4471 // Retain tlab and allocate object in shared space if
4472 // the amount free in the tlab is too large to discard.
4473 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4474 jcc(Assembler::lessEqual, discard_tlab);
4476 // Retain
4477 // %%% yuck as movptr...
4478 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4479 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4480 if (TLABStats) {
4481 // increment number of slow_allocations
4482 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4483 }
4484 jmp(try_eden);
4486 bind(discard_tlab);
4487 if (TLABStats) {
4488 // increment number of refills
4489 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4490 // accumulate wastage -- t1 is amount free in tlab
4491 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4492 }
4494 // if tlab is currently allocated (top or end != null) then
4495 // fill [top, end + alignment_reserve) with array object
4496 testptr(top, top);
4497 jcc(Assembler::zero, do_refill);
4499 // set up the mark word
4500 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4501 // set the length to the remaining space
4502 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4503 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4504 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4505 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4506 // set klass to intArrayKlass
4507 // dubious reloc why not an oop reloc?
4508 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4509 // store klass last. concurrent gcs assumes klass length is valid if
4510 // klass field is not null.
4511 store_klass(top, t1);
4513 movptr(t1, top);
4514 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4515 incr_allocated_bytes(thread_reg, t1, 0);
4517 // refill the tlab with an eden allocation
4518 bind(do_refill);
4519 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4520 shlptr(t1, LogHeapWordSize);
4521 // allocate new tlab, address returned in top
4522 eden_allocate(top, t1, 0, t2, slow_case);
4524 // Check that t1 was preserved in eden_allocate.
4525 #ifdef ASSERT
4526 if (UseTLAB) {
4527 Label ok;
4528 Register tsize = rsi;
4529 assert_different_registers(tsize, thread_reg, t1);
4530 push(tsize);
4531 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4532 shlptr(tsize, LogHeapWordSize);
4533 cmpptr(t1, tsize);
4534 jcc(Assembler::equal, ok);
4535 STOP("assert(t1 != tlab size)");
4536 should_not_reach_here();
4538 bind(ok);
4539 pop(tsize);
4540 }
4541 #endif
4542 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4543 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4544 addptr(top, t1);
4545 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4546 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4547 verify_tlab();
4548 jmp(retry);
4550 return thread_reg; // for use by caller
4551 }
4553 void MacroAssembler::incr_allocated_bytes(Register thread,
4554 Register var_size_in_bytes,
4555 int con_size_in_bytes,
4556 Register t1) {
4557 if (!thread->is_valid()) {
4558 #ifdef _LP64
4559 thread = r15_thread;
4560 #else
4561 assert(t1->is_valid(), "need temp reg");
4562 thread = t1;
4563 get_thread(thread);
4564 #endif
4565 }
4567 #ifdef _LP64
4568 if (var_size_in_bytes->is_valid()) {
4569 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4570 } else {
4571 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4572 }
4573 #else
4574 if (var_size_in_bytes->is_valid()) {
4575 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4576 } else {
4577 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4578 }
4579 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4580 #endif
4581 }
4583 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4584 pusha();
4586 // if we are coming from c1, xmm registers may be live
4587 int off = 0;
4588 if (UseSSE == 1) {
4589 subptr(rsp, sizeof(jdouble)*8);
4590 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4591 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4592 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4593 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4594 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4595 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4596 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4597 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4598 } else if (UseSSE >= 2) {
4599 #ifdef COMPILER2
4600 if (MaxVectorSize > 16) {
4601 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4602 // Save upper half of YMM registes
4603 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4604 vextractf128h(Address(rsp, 0),xmm0);
4605 vextractf128h(Address(rsp, 16),xmm1);
4606 vextractf128h(Address(rsp, 32),xmm2);
4607 vextractf128h(Address(rsp, 48),xmm3);
4608 vextractf128h(Address(rsp, 64),xmm4);
4609 vextractf128h(Address(rsp, 80),xmm5);
4610 vextractf128h(Address(rsp, 96),xmm6);
4611 vextractf128h(Address(rsp,112),xmm7);
4612 #ifdef _LP64
4613 vextractf128h(Address(rsp,128),xmm8);
4614 vextractf128h(Address(rsp,144),xmm9);
4615 vextractf128h(Address(rsp,160),xmm10);
4616 vextractf128h(Address(rsp,176),xmm11);
4617 vextractf128h(Address(rsp,192),xmm12);
4618 vextractf128h(Address(rsp,208),xmm13);
4619 vextractf128h(Address(rsp,224),xmm14);
4620 vextractf128h(Address(rsp,240),xmm15);
4621 #endif
4622 }
4623 #endif
4624 // Save whole 128bit (16 bytes) XMM regiters
4625 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4626 movdqu(Address(rsp,off++*16),xmm0);
4627 movdqu(Address(rsp,off++*16),xmm1);
4628 movdqu(Address(rsp,off++*16),xmm2);
4629 movdqu(Address(rsp,off++*16),xmm3);
4630 movdqu(Address(rsp,off++*16),xmm4);
4631 movdqu(Address(rsp,off++*16),xmm5);
4632 movdqu(Address(rsp,off++*16),xmm6);
4633 movdqu(Address(rsp,off++*16),xmm7);
4634 #ifdef _LP64
4635 movdqu(Address(rsp,off++*16),xmm8);
4636 movdqu(Address(rsp,off++*16),xmm9);
4637 movdqu(Address(rsp,off++*16),xmm10);
4638 movdqu(Address(rsp,off++*16),xmm11);
4639 movdqu(Address(rsp,off++*16),xmm12);
4640 movdqu(Address(rsp,off++*16),xmm13);
4641 movdqu(Address(rsp,off++*16),xmm14);
4642 movdqu(Address(rsp,off++*16),xmm15);
4643 #endif
4644 }
4646 // Preserve registers across runtime call
4647 int incoming_argument_and_return_value_offset = -1;
4648 if (num_fpu_regs_in_use > 1) {
4649 // Must preserve all other FPU regs (could alternatively convert
4650 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4651 // FPU state, but can not trust C compiler)
4652 NEEDS_CLEANUP;
4653 // NOTE that in this case we also push the incoming argument(s) to
4654 // the stack and restore it later; we also use this stack slot to
4655 // hold the return value from dsin, dcos etc.
4656 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4657 subptr(rsp, sizeof(jdouble));
4658 fstp_d(Address(rsp, 0));
4659 }
4660 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4661 for (int i = nb_args-1; i >= 0; i--) {
4662 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4663 }
4664 }
4666 subptr(rsp, nb_args*sizeof(jdouble));
4667 for (int i = 0; i < nb_args; i++) {
4668 fstp_d(Address(rsp, i*sizeof(jdouble)));
4669 }
4671 #ifdef _LP64
4672 if (nb_args > 0) {
4673 movdbl(xmm0, Address(rsp, 0));
4674 }
4675 if (nb_args > 1) {
4676 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4677 }
4678 assert(nb_args <= 2, "unsupported number of args");
4679 #endif // _LP64
4681 // NOTE: we must not use call_VM_leaf here because that requires a
4682 // complete interpreter frame in debug mode -- same bug as 4387334
4683 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4684 // do proper 64bit abi
4686 NEEDS_CLEANUP;
4687 // Need to add stack banging before this runtime call if it needs to
4688 // be taken; however, there is no generic stack banging routine at
4689 // the MacroAssembler level
4691 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4693 #ifdef _LP64
4694 movsd(Address(rsp, 0), xmm0);
4695 fld_d(Address(rsp, 0));
4696 #endif // _LP64
4697 addptr(rsp, sizeof(jdouble) * nb_args);
4698 if (num_fpu_regs_in_use > 1) {
4699 // Must save return value to stack and then restore entire FPU
4700 // stack except incoming arguments
4701 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4702 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4703 fld_d(Address(rsp, 0));
4704 addptr(rsp, sizeof(jdouble));
4705 }
4706 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4707 addptr(rsp, sizeof(jdouble) * nb_args);
4708 }
4710 off = 0;
4711 if (UseSSE == 1) {
4712 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4713 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4714 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4715 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4716 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4717 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4718 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4719 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4720 addptr(rsp, sizeof(jdouble)*8);
4721 } else if (UseSSE >= 2) {
4722 // Restore whole 128bit (16 bytes) XMM regiters
4723 movdqu(xmm0, Address(rsp,off++*16));
4724 movdqu(xmm1, Address(rsp,off++*16));
4725 movdqu(xmm2, Address(rsp,off++*16));
4726 movdqu(xmm3, Address(rsp,off++*16));
4727 movdqu(xmm4, Address(rsp,off++*16));
4728 movdqu(xmm5, Address(rsp,off++*16));
4729 movdqu(xmm6, Address(rsp,off++*16));
4730 movdqu(xmm7, Address(rsp,off++*16));
4731 #ifdef _LP64
4732 movdqu(xmm8, Address(rsp,off++*16));
4733 movdqu(xmm9, Address(rsp,off++*16));
4734 movdqu(xmm10, Address(rsp,off++*16));
4735 movdqu(xmm11, Address(rsp,off++*16));
4736 movdqu(xmm12, Address(rsp,off++*16));
4737 movdqu(xmm13, Address(rsp,off++*16));
4738 movdqu(xmm14, Address(rsp,off++*16));
4739 movdqu(xmm15, Address(rsp,off++*16));
4740 #endif
4741 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4742 #ifdef COMPILER2
4743 if (MaxVectorSize > 16) {
4744 // Restore upper half of YMM registes.
4745 vinsertf128h(xmm0, Address(rsp, 0));
4746 vinsertf128h(xmm1, Address(rsp, 16));
4747 vinsertf128h(xmm2, Address(rsp, 32));
4748 vinsertf128h(xmm3, Address(rsp, 48));
4749 vinsertf128h(xmm4, Address(rsp, 64));
4750 vinsertf128h(xmm5, Address(rsp, 80));
4751 vinsertf128h(xmm6, Address(rsp, 96));
4752 vinsertf128h(xmm7, Address(rsp,112));
4753 #ifdef _LP64
4754 vinsertf128h(xmm8, Address(rsp,128));
4755 vinsertf128h(xmm9, Address(rsp,144));
4756 vinsertf128h(xmm10, Address(rsp,160));
4757 vinsertf128h(xmm11, Address(rsp,176));
4758 vinsertf128h(xmm12, Address(rsp,192));
4759 vinsertf128h(xmm13, Address(rsp,208));
4760 vinsertf128h(xmm14, Address(rsp,224));
4761 vinsertf128h(xmm15, Address(rsp,240));
4762 #endif
4763 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4764 }
4765 #endif
4766 }
4767 popa();
4768 }
4770 static const double pi_4 = 0.7853981633974483;
4772 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4773 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4774 // was attempted in this code; unfortunately it appears that the
4775 // switch to 80-bit precision and back causes this to be
4776 // unprofitable compared with simply performing a runtime call if
4777 // the argument is out of the (-pi/4, pi/4) range.
4779 Register tmp = noreg;
4780 if (!VM_Version::supports_cmov()) {
4781 // fcmp needs a temporary so preserve rbx,
4782 tmp = rbx;
4783 push(tmp);
4784 }
4786 Label slow_case, done;
4788 ExternalAddress pi4_adr = (address)&pi_4;
4789 if (reachable(pi4_adr)) {
4790 // x ?<= pi/4
4791 fld_d(pi4_adr);
4792 fld_s(1); // Stack: X PI/4 X
4793 fabs(); // Stack: |X| PI/4 X
4794 fcmp(tmp);
4795 jcc(Assembler::above, slow_case);
4797 // fastest case: -pi/4 <= x <= pi/4
4798 switch(trig) {
4799 case 's':
4800 fsin();
4801 break;
4802 case 'c':
4803 fcos();
4804 break;
4805 case 't':
4806 ftan();
4807 break;
4808 default:
4809 assert(false, "bad intrinsic");
4810 break;
4811 }
4812 jmp(done);
4813 }
4815 // slow case: runtime call
4816 bind(slow_case);
4818 switch(trig) {
4819 case 's':
4820 {
4821 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4822 }
4823 break;
4824 case 'c':
4825 {
4826 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4827 }
4828 break;
4829 case 't':
4830 {
4831 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4832 }
4833 break;
4834 default:
4835 assert(false, "bad intrinsic");
4836 break;
4837 }
4839 // Come here with result in F-TOS
4840 bind(done);
4842 if (tmp != noreg) {
4843 pop(tmp);
4844 }
4845 }
4848 // Look up the method for a megamorphic invokeinterface call.
4849 // The target method is determined by <intf_klass, itable_index>.
4850 // The receiver klass is in recv_klass.
4851 // On success, the result will be in method_result, and execution falls through.
4852 // On failure, execution transfers to the given label.
4853 void MacroAssembler::lookup_interface_method(Register recv_klass,
4854 Register intf_klass,
4855 RegisterOrConstant itable_index,
4856 Register method_result,
4857 Register scan_temp,
4858 Label& L_no_such_interface) {
4859 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4860 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4861 "caller must use same register for non-constant itable index as for method");
4863 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4864 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4865 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4866 int scan_step = itableOffsetEntry::size() * wordSize;
4867 int vte_size = vtableEntry::size() * wordSize;
4868 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4869 assert(vte_size == wordSize, "else adjust times_vte_scale");
4871 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4873 // %%% Could store the aligned, prescaled offset in the klassoop.
4874 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4875 if (HeapWordsPerLong > 1) {
4876 // Round up to align_object_offset boundary
4877 // see code for InstanceKlass::start_of_itable!
4878 round_to(scan_temp, BytesPerLong);
4879 }
4881 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4882 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4883 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4885 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4886 // if (scan->interface() == intf) {
4887 // result = (klass + scan->offset() + itable_index);
4888 // }
4889 // }
4890 Label search, found_method;
4892 for (int peel = 1; peel >= 0; peel--) {
4893 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4894 cmpptr(intf_klass, method_result);
4896 if (peel) {
4897 jccb(Assembler::equal, found_method);
4898 } else {
4899 jccb(Assembler::notEqual, search);
4900 // (invert the test to fall through to found_method...)
4901 }
4903 if (!peel) break;
4905 bind(search);
4907 // Check that the previous entry is non-null. A null entry means that
4908 // the receiver class doesn't implement the interface, and wasn't the
4909 // same as when the caller was compiled.
4910 testptr(method_result, method_result);
4911 jcc(Assembler::zero, L_no_such_interface);
4912 addptr(scan_temp, scan_step);
4913 }
4915 bind(found_method);
4917 // Got a hit.
4918 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4919 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4920 }
4923 // virtual method calling
4924 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4925 RegisterOrConstant vtable_index,
4926 Register method_result) {
4927 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4928 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4929 Address vtable_entry_addr(recv_klass,
4930 vtable_index, Address::times_ptr,
4931 base + vtableEntry::method_offset_in_bytes());
4932 movptr(method_result, vtable_entry_addr);
4933 }
4936 void MacroAssembler::check_klass_subtype(Register sub_klass,
4937 Register super_klass,
4938 Register temp_reg,
4939 Label& L_success) {
4940 Label L_failure;
4941 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4942 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4943 bind(L_failure);
4944 }
4947 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4948 Register super_klass,
4949 Register temp_reg,
4950 Label* L_success,
4951 Label* L_failure,
4952 Label* L_slow_path,
4953 RegisterOrConstant super_check_offset) {
4954 assert_different_registers(sub_klass, super_klass, temp_reg);
4955 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4956 if (super_check_offset.is_register()) {
4957 assert_different_registers(sub_klass, super_klass,
4958 super_check_offset.as_register());
4959 } else if (must_load_sco) {
4960 assert(temp_reg != noreg, "supply either a temp or a register offset");
4961 }
4963 Label L_fallthrough;
4964 int label_nulls = 0;
4965 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4966 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4967 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4968 assert(label_nulls <= 1, "at most one NULL in the batch");
4970 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4971 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4972 Address super_check_offset_addr(super_klass, sco_offset);
4974 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4975 // range of a jccb. If this routine grows larger, reconsider at
4976 // least some of these.
4977 #define local_jcc(assembler_cond, label) \
4978 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4979 else jcc( assembler_cond, label) /*omit semi*/
4981 // Hacked jmp, which may only be used just before L_fallthrough.
4982 #define final_jmp(label) \
4983 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4984 else jmp(label) /*omit semi*/
4986 // If the pointers are equal, we are done (e.g., String[] elements).
4987 // This self-check enables sharing of secondary supertype arrays among
4988 // non-primary types such as array-of-interface. Otherwise, each such
4989 // type would need its own customized SSA.
4990 // We move this check to the front of the fast path because many
4991 // type checks are in fact trivially successful in this manner,
4992 // so we get a nicely predicted branch right at the start of the check.
4993 cmpptr(sub_klass, super_klass);
4994 local_jcc(Assembler::equal, *L_success);
4996 // Check the supertype display:
4997 if (must_load_sco) {
4998 // Positive movl does right thing on LP64.
4999 movl(temp_reg, super_check_offset_addr);
5000 super_check_offset = RegisterOrConstant(temp_reg);
5001 }
5002 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5003 cmpptr(super_klass, super_check_addr); // load displayed supertype
5005 // This check has worked decisively for primary supers.
5006 // Secondary supers are sought in the super_cache ('super_cache_addr').
5007 // (Secondary supers are interfaces and very deeply nested subtypes.)
5008 // This works in the same check above because of a tricky aliasing
5009 // between the super_cache and the primary super display elements.
5010 // (The 'super_check_addr' can address either, as the case requires.)
5011 // Note that the cache is updated below if it does not help us find
5012 // what we need immediately.
5013 // So if it was a primary super, we can just fail immediately.
5014 // Otherwise, it's the slow path for us (no success at this point).
5016 if (super_check_offset.is_register()) {
5017 local_jcc(Assembler::equal, *L_success);
5018 cmpl(super_check_offset.as_register(), sc_offset);
5019 if (L_failure == &L_fallthrough) {
5020 local_jcc(Assembler::equal, *L_slow_path);
5021 } else {
5022 local_jcc(Assembler::notEqual, *L_failure);
5023 final_jmp(*L_slow_path);
5024 }
5025 } else if (super_check_offset.as_constant() == sc_offset) {
5026 // Need a slow path; fast failure is impossible.
5027 if (L_slow_path == &L_fallthrough) {
5028 local_jcc(Assembler::equal, *L_success);
5029 } else {
5030 local_jcc(Assembler::notEqual, *L_slow_path);
5031 final_jmp(*L_success);
5032 }
5033 } else {
5034 // No slow path; it's a fast decision.
5035 if (L_failure == &L_fallthrough) {
5036 local_jcc(Assembler::equal, *L_success);
5037 } else {
5038 local_jcc(Assembler::notEqual, *L_failure);
5039 final_jmp(*L_success);
5040 }
5041 }
5043 bind(L_fallthrough);
5045 #undef local_jcc
5046 #undef final_jmp
5047 }
5050 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5051 Register super_klass,
5052 Register temp_reg,
5053 Register temp2_reg,
5054 Label* L_success,
5055 Label* L_failure,
5056 bool set_cond_codes) {
5057 assert_different_registers(sub_klass, super_klass, temp_reg);
5058 if (temp2_reg != noreg)
5059 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5060 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5062 Label L_fallthrough;
5063 int label_nulls = 0;
5064 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5065 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5066 assert(label_nulls <= 1, "at most one NULL in the batch");
5068 // a couple of useful fields in sub_klass:
5069 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5070 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5071 Address secondary_supers_addr(sub_klass, ss_offset);
5072 Address super_cache_addr( sub_klass, sc_offset);
5074 // Do a linear scan of the secondary super-klass chain.
5075 // This code is rarely used, so simplicity is a virtue here.
5076 // The repne_scan instruction uses fixed registers, which we must spill.
5077 // Don't worry too much about pre-existing connections with the input regs.
5079 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5080 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5082 // Get super_klass value into rax (even if it was in rdi or rcx).
5083 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5084 if (super_klass != rax || UseCompressedOops) {
5085 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5086 mov(rax, super_klass);
5087 }
5088 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5089 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5091 #ifndef PRODUCT
5092 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5093 ExternalAddress pst_counter_addr((address) pst_counter);
5094 NOT_LP64( incrementl(pst_counter_addr) );
5095 LP64_ONLY( lea(rcx, pst_counter_addr) );
5096 LP64_ONLY( incrementl(Address(rcx, 0)) );
5097 #endif //PRODUCT
5099 // We will consult the secondary-super array.
5100 movptr(rdi, secondary_supers_addr);
5101 // Load the array length. (Positive movl does right thing on LP64.)
5102 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5103 // Skip to start of data.
5104 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5106 // Scan RCX words at [RDI] for an occurrence of RAX.
5107 // Set NZ/Z based on last compare.
5108 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5109 // not change flags (only scas instruction which is repeated sets flags).
5110 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5112 testptr(rax,rax); // Set Z = 0
5113 repne_scan();
5115 // Unspill the temp. registers:
5116 if (pushed_rdi) pop(rdi);
5117 if (pushed_rcx) pop(rcx);
5118 if (pushed_rax) pop(rax);
5120 if (set_cond_codes) {
5121 // Special hack for the AD files: rdi is guaranteed non-zero.
5122 assert(!pushed_rdi, "rdi must be left non-NULL");
5123 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5124 }
5126 if (L_failure == &L_fallthrough)
5127 jccb(Assembler::notEqual, *L_failure);
5128 else jcc(Assembler::notEqual, *L_failure);
5130 // Success. Cache the super we found and proceed in triumph.
5131 movptr(super_cache_addr, super_klass);
5133 if (L_success != &L_fallthrough) {
5134 jmp(*L_success);
5135 }
5137 #undef IS_A_TEMP
5139 bind(L_fallthrough);
5140 }
5143 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5144 if (VM_Version::supports_cmov()) {
5145 cmovl(cc, dst, src);
5146 } else {
5147 Label L;
5148 jccb(negate_condition(cc), L);
5149 movl(dst, src);
5150 bind(L);
5151 }
5152 }
5154 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5155 if (VM_Version::supports_cmov()) {
5156 cmovl(cc, dst, src);
5157 } else {
5158 Label L;
5159 jccb(negate_condition(cc), L);
5160 movl(dst, src);
5161 bind(L);
5162 }
5163 }
5165 void MacroAssembler::verify_oop(Register reg, const char* s) {
5166 if (!VerifyOops) return;
5168 // Pass register number to verify_oop_subroutine
5169 const char* b = NULL;
5170 {
5171 ResourceMark rm;
5172 stringStream ss;
5173 ss.print("verify_oop: %s: %s", reg->name(), s);
5174 b = code_string(ss.as_string());
5175 }
5176 BLOCK_COMMENT("verify_oop {");
5177 #ifdef _LP64
5178 push(rscratch1); // save r10, trashed by movptr()
5179 #endif
5180 push(rax); // save rax,
5181 push(reg); // pass register argument
5182 ExternalAddress buffer((address) b);
5183 // avoid using pushptr, as it modifies scratch registers
5184 // and our contract is not to modify anything
5185 movptr(rax, buffer.addr());
5186 push(rax);
5187 // call indirectly to solve generation ordering problem
5188 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5189 call(rax);
5190 // Caller pops the arguments (oop, message) and restores rax, r10
5191 BLOCK_COMMENT("} verify_oop");
5192 }
5195 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5196 Register tmp,
5197 int offset) {
5198 intptr_t value = *delayed_value_addr;
5199 if (value != 0)
5200 return RegisterOrConstant(value + offset);
5202 // load indirectly to solve generation ordering problem
5203 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5205 #ifdef ASSERT
5206 { Label L;
5207 testptr(tmp, tmp);
5208 if (WizardMode) {
5209 const char* buf = NULL;
5210 {
5211 ResourceMark rm;
5212 stringStream ss;
5213 ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
5214 buf = code_string(ss.as_string());
5215 }
5216 jcc(Assembler::notZero, L);
5217 STOP(buf);
5218 } else {
5219 jccb(Assembler::notZero, L);
5220 hlt();
5221 }
5222 bind(L);
5223 }
5224 #endif
5226 if (offset != 0)
5227 addptr(tmp, offset);
5229 return RegisterOrConstant(tmp);
5230 }
5233 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5234 int extra_slot_offset) {
5235 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5236 int stackElementSize = Interpreter::stackElementSize;
5237 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5238 #ifdef ASSERT
5239 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5240 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5241 #endif
5242 Register scale_reg = noreg;
5243 Address::ScaleFactor scale_factor = Address::no_scale;
5244 if (arg_slot.is_constant()) {
5245 offset += arg_slot.as_constant() * stackElementSize;
5246 } else {
5247 scale_reg = arg_slot.as_register();
5248 scale_factor = Address::times(stackElementSize);
5249 }
5250 offset += wordSize; // return PC is on stack
5251 return Address(rsp, scale_reg, scale_factor, offset);
5252 }
5255 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5256 if (!VerifyOops) return;
5258 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5259 // Pass register number to verify_oop_subroutine
5260 const char* b = NULL;
5261 {
5262 ResourceMark rm;
5263 stringStream ss;
5264 ss.print("verify_oop_addr: %s", s);
5265 b = code_string(ss.as_string());
5266 }
5267 #ifdef _LP64
5268 push(rscratch1); // save r10, trashed by movptr()
5269 #endif
5270 push(rax); // save rax,
5271 // addr may contain rsp so we will have to adjust it based on the push
5272 // we just did (and on 64 bit we do two pushes)
5273 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5274 // stores rax into addr which is backwards of what was intended.
5275 if (addr.uses(rsp)) {
5276 lea(rax, addr);
5277 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5278 } else {
5279 pushptr(addr);
5280 }
5282 ExternalAddress buffer((address) b);
5283 // pass msg argument
5284 // avoid using pushptr, as it modifies scratch registers
5285 // and our contract is not to modify anything
5286 movptr(rax, buffer.addr());
5287 push(rax);
5289 // call indirectly to solve generation ordering problem
5290 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5291 call(rax);
5292 // Caller pops the arguments (addr, message) and restores rax, r10.
5293 }
5295 void MacroAssembler::verify_tlab() {
5296 #ifdef ASSERT
5297 if (UseTLAB && VerifyOops) {
5298 Label next, ok;
5299 Register t1 = rsi;
5300 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5302 push(t1);
5303 NOT_LP64(push(thread_reg));
5304 NOT_LP64(get_thread(thread_reg));
5306 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5307 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5308 jcc(Assembler::aboveEqual, next);
5309 STOP("assert(top >= start)");
5310 should_not_reach_here();
5312 bind(next);
5313 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5314 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5315 jcc(Assembler::aboveEqual, ok);
5316 STOP("assert(top <= end)");
5317 should_not_reach_here();
5319 bind(ok);
5320 NOT_LP64(pop(thread_reg));
5321 pop(t1);
5322 }
5323 #endif
5324 }
5326 class ControlWord {
5327 public:
5328 int32_t _value;
5330 int rounding_control() const { return (_value >> 10) & 3 ; }
5331 int precision_control() const { return (_value >> 8) & 3 ; }
5332 bool precision() const { return ((_value >> 5) & 1) != 0; }
5333 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5334 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5335 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5336 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5337 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5339 void print() const {
5340 // rounding control
5341 const char* rc;
5342 switch (rounding_control()) {
5343 case 0: rc = "round near"; break;
5344 case 1: rc = "round down"; break;
5345 case 2: rc = "round up "; break;
5346 case 3: rc = "chop "; break;
5347 };
5348 // precision control
5349 const char* pc;
5350 switch (precision_control()) {
5351 case 0: pc = "24 bits "; break;
5352 case 1: pc = "reserved"; break;
5353 case 2: pc = "53 bits "; break;
5354 case 3: pc = "64 bits "; break;
5355 };
5356 // flags
5357 char f[9];
5358 f[0] = ' ';
5359 f[1] = ' ';
5360 f[2] = (precision ()) ? 'P' : 'p';
5361 f[3] = (underflow ()) ? 'U' : 'u';
5362 f[4] = (overflow ()) ? 'O' : 'o';
5363 f[5] = (zero_divide ()) ? 'Z' : 'z';
5364 f[6] = (denormalized()) ? 'D' : 'd';
5365 f[7] = (invalid ()) ? 'I' : 'i';
5366 f[8] = '\x0';
5367 // output
5368 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5369 }
5371 };
5373 class StatusWord {
5374 public:
5375 int32_t _value;
5377 bool busy() const { return ((_value >> 15) & 1) != 0; }
5378 bool C3() const { return ((_value >> 14) & 1) != 0; }
5379 bool C2() const { return ((_value >> 10) & 1) != 0; }
5380 bool C1() const { return ((_value >> 9) & 1) != 0; }
5381 bool C0() const { return ((_value >> 8) & 1) != 0; }
5382 int top() const { return (_value >> 11) & 7 ; }
5383 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5384 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5385 bool precision() const { return ((_value >> 5) & 1) != 0; }
5386 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5387 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5388 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5389 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5390 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5392 void print() const {
5393 // condition codes
5394 char c[5];
5395 c[0] = (C3()) ? '3' : '-';
5396 c[1] = (C2()) ? '2' : '-';
5397 c[2] = (C1()) ? '1' : '-';
5398 c[3] = (C0()) ? '0' : '-';
5399 c[4] = '\x0';
5400 // flags
5401 char f[9];
5402 f[0] = (error_status()) ? 'E' : '-';
5403 f[1] = (stack_fault ()) ? 'S' : '-';
5404 f[2] = (precision ()) ? 'P' : '-';
5405 f[3] = (underflow ()) ? 'U' : '-';
5406 f[4] = (overflow ()) ? 'O' : '-';
5407 f[5] = (zero_divide ()) ? 'Z' : '-';
5408 f[6] = (denormalized()) ? 'D' : '-';
5409 f[7] = (invalid ()) ? 'I' : '-';
5410 f[8] = '\x0';
5411 // output
5412 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5413 }
5415 };
5417 class TagWord {
5418 public:
5419 int32_t _value;
5421 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5423 void print() const {
5424 printf("%04x", _value & 0xFFFF);
5425 }
5427 };
5429 class FPU_Register {
5430 public:
5431 int32_t _m0;
5432 int32_t _m1;
5433 int16_t _ex;
5435 bool is_indefinite() const {
5436 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5437 }
5439 void print() const {
5440 char sign = (_ex < 0) ? '-' : '+';
5441 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5442 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5443 };
5445 };
5447 class FPU_State {
5448 public:
5449 enum {
5450 register_size = 10,
5451 number_of_registers = 8,
5452 register_mask = 7
5453 };
5455 ControlWord _control_word;
5456 StatusWord _status_word;
5457 TagWord _tag_word;
5458 int32_t _error_offset;
5459 int32_t _error_selector;
5460 int32_t _data_offset;
5461 int32_t _data_selector;
5462 int8_t _register[register_size * number_of_registers];
5464 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5465 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5467 const char* tag_as_string(int tag) const {
5468 switch (tag) {
5469 case 0: return "valid";
5470 case 1: return "zero";
5471 case 2: return "special";
5472 case 3: return "empty";
5473 }
5474 ShouldNotReachHere();
5475 return NULL;
5476 }
5478 void print() const {
5479 // print computation registers
5480 { int t = _status_word.top();
5481 for (int i = 0; i < number_of_registers; i++) {
5482 int j = (i - t) & register_mask;
5483 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5484 st(j)->print();
5485 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5486 }
5487 }
5488 printf("\n");
5489 // print control registers
5490 printf("ctrl = "); _control_word.print(); printf("\n");
5491 printf("stat = "); _status_word .print(); printf("\n");
5492 printf("tags = "); _tag_word .print(); printf("\n");
5493 }
5495 };
5497 class Flag_Register {
5498 public:
5499 int32_t _value;
5501 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5502 bool direction() const { return ((_value >> 10) & 1) != 0; }
5503 bool sign() const { return ((_value >> 7) & 1) != 0; }
5504 bool zero() const { return ((_value >> 6) & 1) != 0; }
5505 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5506 bool parity() const { return ((_value >> 2) & 1) != 0; }
5507 bool carry() const { return ((_value >> 0) & 1) != 0; }
5509 void print() const {
5510 // flags
5511 char f[8];
5512 f[0] = (overflow ()) ? 'O' : '-';
5513 f[1] = (direction ()) ? 'D' : '-';
5514 f[2] = (sign ()) ? 'S' : '-';
5515 f[3] = (zero ()) ? 'Z' : '-';
5516 f[4] = (auxiliary_carry()) ? 'A' : '-';
5517 f[5] = (parity ()) ? 'P' : '-';
5518 f[6] = (carry ()) ? 'C' : '-';
5519 f[7] = '\x0';
5520 // output
5521 printf("%08x flags = %s", _value, f);
5522 }
5524 };
5526 class IU_Register {
5527 public:
5528 int32_t _value;
5530 void print() const {
5531 printf("%08x %11d", _value, _value);
5532 }
5534 };
5536 class IU_State {
5537 public:
5538 Flag_Register _eflags;
5539 IU_Register _rdi;
5540 IU_Register _rsi;
5541 IU_Register _rbp;
5542 IU_Register _rsp;
5543 IU_Register _rbx;
5544 IU_Register _rdx;
5545 IU_Register _rcx;
5546 IU_Register _rax;
5548 void print() const {
5549 // computation registers
5550 printf("rax, = "); _rax.print(); printf("\n");
5551 printf("rbx, = "); _rbx.print(); printf("\n");
5552 printf("rcx = "); _rcx.print(); printf("\n");
5553 printf("rdx = "); _rdx.print(); printf("\n");
5554 printf("rdi = "); _rdi.print(); printf("\n");
5555 printf("rsi = "); _rsi.print(); printf("\n");
5556 printf("rbp, = "); _rbp.print(); printf("\n");
5557 printf("rsp = "); _rsp.print(); printf("\n");
5558 printf("\n");
5559 // control registers
5560 printf("flgs = "); _eflags.print(); printf("\n");
5561 }
5562 };
5565 class CPU_State {
5566 public:
5567 FPU_State _fpu_state;
5568 IU_State _iu_state;
5570 void print() const {
5571 printf("--------------------------------------------------\n");
5572 _iu_state .print();
5573 printf("\n");
5574 _fpu_state.print();
5575 printf("--------------------------------------------------\n");
5576 }
5578 };
5581 static void _print_CPU_state(CPU_State* state) {
5582 state->print();
5583 };
5586 void MacroAssembler::print_CPU_state() {
5587 push_CPU_state();
5588 push(rsp); // pass CPU state
5589 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5590 addptr(rsp, wordSize); // discard argument
5591 pop_CPU_state();
5592 }
5595 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5596 static int counter = 0;
5597 FPU_State* fs = &state->_fpu_state;
5598 counter++;
5599 // For leaf calls, only verify that the top few elements remain empty.
5600 // We only need 1 empty at the top for C2 code.
5601 if( stack_depth < 0 ) {
5602 if( fs->tag_for_st(7) != 3 ) {
5603 printf("FPR7 not empty\n");
5604 state->print();
5605 assert(false, "error");
5606 return false;
5607 }
5608 return true; // All other stack states do not matter
5609 }
5611 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5612 "bad FPU control word");
5614 // compute stack depth
5615 int i = 0;
5616 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5617 int d = i;
5618 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5619 // verify findings
5620 if (i != FPU_State::number_of_registers) {
5621 // stack not contiguous
5622 printf("%s: stack not contiguous at ST%d\n", s, i);
5623 state->print();
5624 assert(false, "error");
5625 return false;
5626 }
5627 // check if computed stack depth corresponds to expected stack depth
5628 if (stack_depth < 0) {
5629 // expected stack depth is -stack_depth or less
5630 if (d > -stack_depth) {
5631 // too many elements on the stack
5632 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5633 state->print();
5634 assert(false, "error");
5635 return false;
5636 }
5637 } else {
5638 // expected stack depth is stack_depth
5639 if (d != stack_depth) {
5640 // wrong stack depth
5641 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5642 state->print();
5643 assert(false, "error");
5644 return false;
5645 }
5646 }
5647 // everything is cool
5648 return true;
5649 }
5652 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5653 if (!VerifyFPU) return;
5654 push_CPU_state();
5655 push(rsp); // pass CPU state
5656 ExternalAddress msg((address) s);
5657 // pass message string s
5658 pushptr(msg.addr());
5659 push(stack_depth); // pass stack depth
5660 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5661 addptr(rsp, 3 * wordSize); // discard arguments
5662 // check for error
5663 { Label L;
5664 testl(rax, rax);
5665 jcc(Assembler::notZero, L);
5666 int3(); // break if error condition
5667 bind(L);
5668 }
5669 pop_CPU_state();
5670 }
5672 void MacroAssembler::restore_cpu_control_state_after_jni() {
5673 // Either restore the MXCSR register after returning from the JNI Call
5674 // or verify that it wasn't changed (with -Xcheck:jni flag).
5675 if (VM_Version::supports_sse()) {
5676 if (RestoreMXCSROnJNICalls) {
5677 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5678 } else if (CheckJNICalls) {
5679 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5680 }
5681 }
5682 if (VM_Version::supports_avx()) {
5683 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5684 vzeroupper();
5685 }
5687 #ifndef _LP64
5688 // Either restore the x87 floating pointer control word after returning
5689 // from the JNI call or verify that it wasn't changed.
5690 if (CheckJNICalls) {
5691 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5692 }
5693 #endif // _LP64
5694 }
5697 void MacroAssembler::load_klass(Register dst, Register src) {
5698 #ifdef _LP64
5699 if (UseCompressedClassPointers) {
5700 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5701 decode_klass_not_null(dst);
5702 } else
5703 #endif
5704 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5705 }
5707 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5708 load_klass(dst, src);
5709 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5710 }
5712 void MacroAssembler::store_klass(Register dst, Register src) {
5713 #ifdef _LP64
5714 if (UseCompressedClassPointers) {
5715 encode_klass_not_null(src);
5716 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5717 } else
5718 #endif
5719 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5720 }
5722 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5723 #ifdef _LP64
5724 // FIXME: Must change all places where we try to load the klass.
5725 if (UseCompressedOops) {
5726 movl(dst, src);
5727 decode_heap_oop(dst);
5728 } else
5729 #endif
5730 movptr(dst, src);
5731 }
5733 // Doesn't do verfication, generates fixed size code
5734 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5735 #ifdef _LP64
5736 if (UseCompressedOops) {
5737 movl(dst, src);
5738 decode_heap_oop_not_null(dst);
5739 } else
5740 #endif
5741 movptr(dst, src);
5742 }
5744 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5745 #ifdef _LP64
5746 if (UseCompressedOops) {
5747 assert(!dst.uses(src), "not enough registers");
5748 encode_heap_oop(src);
5749 movl(dst, src);
5750 } else
5751 #endif
5752 movptr(dst, src);
5753 }
5755 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5756 assert_different_registers(src1, tmp);
5757 #ifdef _LP64
5758 if (UseCompressedOops) {
5759 bool did_push = false;
5760 if (tmp == noreg) {
5761 tmp = rax;
5762 push(tmp);
5763 did_push = true;
5764 assert(!src2.uses(rsp), "can't push");
5765 }
5766 load_heap_oop(tmp, src2);
5767 cmpptr(src1, tmp);
5768 if (did_push) pop(tmp);
5769 } else
5770 #endif
5771 cmpptr(src1, src2);
5772 }
5774 // Used for storing NULLs.
5775 void MacroAssembler::store_heap_oop_null(Address dst) {
5776 #ifdef _LP64
5777 if (UseCompressedOops) {
5778 movl(dst, (int32_t)NULL_WORD);
5779 } else {
5780 movslq(dst, (int32_t)NULL_WORD);
5781 }
5782 #else
5783 movl(dst, (int32_t)NULL_WORD);
5784 #endif
5785 }
5787 #ifdef _LP64
5788 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5789 if (UseCompressedClassPointers) {
5790 // Store to klass gap in destination
5791 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5792 }
5793 }
5795 #ifdef ASSERT
5796 void MacroAssembler::verify_heapbase(const char* msg) {
5797 assert (UseCompressedOops, "should be compressed");
5798 assert (Universe::heap() != NULL, "java heap should be initialized");
5799 if (CheckCompressedOops) {
5800 Label ok;
5801 push(rscratch1); // cmpptr trashes rscratch1
5802 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5803 jcc(Assembler::equal, ok);
5804 STOP(msg);
5805 bind(ok);
5806 pop(rscratch1);
5807 }
5808 }
5809 #endif
5811 // Algorithm must match oop.inline.hpp encode_heap_oop.
5812 void MacroAssembler::encode_heap_oop(Register r) {
5813 #ifdef ASSERT
5814 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5815 #endif
5816 verify_oop(r, "broken oop in encode_heap_oop");
5817 if (Universe::narrow_oop_base() == NULL) {
5818 if (Universe::narrow_oop_shift() != 0) {
5819 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5820 shrq(r, LogMinObjAlignmentInBytes);
5821 }
5822 return;
5823 }
5824 testq(r, r);
5825 cmovq(Assembler::equal, r, r12_heapbase);
5826 subq(r, r12_heapbase);
5827 shrq(r, LogMinObjAlignmentInBytes);
5828 }
5830 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5831 #ifdef ASSERT
5832 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5833 if (CheckCompressedOops) {
5834 Label ok;
5835 testq(r, r);
5836 jcc(Assembler::notEqual, ok);
5837 STOP("null oop passed to encode_heap_oop_not_null");
5838 bind(ok);
5839 }
5840 #endif
5841 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5842 if (Universe::narrow_oop_base() != NULL) {
5843 subq(r, r12_heapbase);
5844 }
5845 if (Universe::narrow_oop_shift() != 0) {
5846 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5847 shrq(r, LogMinObjAlignmentInBytes);
5848 }
5849 }
5851 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5852 #ifdef ASSERT
5853 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5854 if (CheckCompressedOops) {
5855 Label ok;
5856 testq(src, src);
5857 jcc(Assembler::notEqual, ok);
5858 STOP("null oop passed to encode_heap_oop_not_null2");
5859 bind(ok);
5860 }
5861 #endif
5862 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5863 if (dst != src) {
5864 movq(dst, src);
5865 }
5866 if (Universe::narrow_oop_base() != NULL) {
5867 subq(dst, r12_heapbase);
5868 }
5869 if (Universe::narrow_oop_shift() != 0) {
5870 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5871 shrq(dst, LogMinObjAlignmentInBytes);
5872 }
5873 }
5875 void MacroAssembler::decode_heap_oop(Register r) {
5876 #ifdef ASSERT
5877 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5878 #endif
5879 if (Universe::narrow_oop_base() == NULL) {
5880 if (Universe::narrow_oop_shift() != 0) {
5881 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5882 shlq(r, LogMinObjAlignmentInBytes);
5883 }
5884 } else {
5885 Label done;
5886 shlq(r, LogMinObjAlignmentInBytes);
5887 jccb(Assembler::equal, done);
5888 addq(r, r12_heapbase);
5889 bind(done);
5890 }
5891 verify_oop(r, "broken oop in decode_heap_oop");
5892 }
5894 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5895 // Note: it will change flags
5896 assert (UseCompressedOops, "should only be used for compressed headers");
5897 assert (Universe::heap() != NULL, "java heap should be initialized");
5898 // Cannot assert, unverified entry point counts instructions (see .ad file)
5899 // vtableStubs also counts instructions in pd_code_size_limit.
5900 // Also do not verify_oop as this is called by verify_oop.
5901 if (Universe::narrow_oop_shift() != 0) {
5902 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5903 shlq(r, LogMinObjAlignmentInBytes);
5904 if (Universe::narrow_oop_base() != NULL) {
5905 addq(r, r12_heapbase);
5906 }
5907 } else {
5908 assert (Universe::narrow_oop_base() == NULL, "sanity");
5909 }
5910 }
5912 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5913 // Note: it will change flags
5914 assert (UseCompressedOops, "should only be used for compressed headers");
5915 assert (Universe::heap() != NULL, "java heap should be initialized");
5916 // Cannot assert, unverified entry point counts instructions (see .ad file)
5917 // vtableStubs also counts instructions in pd_code_size_limit.
5918 // Also do not verify_oop as this is called by verify_oop.
5919 if (Universe::narrow_oop_shift() != 0) {
5920 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5921 if (LogMinObjAlignmentInBytes == Address::times_8) {
5922 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5923 } else {
5924 if (dst != src) {
5925 movq(dst, src);
5926 }
5927 shlq(dst, LogMinObjAlignmentInBytes);
5928 if (Universe::narrow_oop_base() != NULL) {
5929 addq(dst, r12_heapbase);
5930 }
5931 }
5932 } else {
5933 assert (Universe::narrow_oop_base() == NULL, "sanity");
5934 if (dst != src) {
5935 movq(dst, src);
5936 }
5937 }
5938 }
5940 void MacroAssembler::encode_klass_not_null(Register r) {
5941 if (Universe::narrow_klass_base() != NULL) {
5942 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5943 assert(r != r12_heapbase, "Encoding a klass in r12");
5944 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5945 subq(r, r12_heapbase);
5946 }
5947 if (Universe::narrow_klass_shift() != 0) {
5948 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5949 shrq(r, LogKlassAlignmentInBytes);
5950 }
5951 if (Universe::narrow_klass_base() != NULL) {
5952 reinit_heapbase();
5953 }
5954 }
5956 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5957 if (dst == src) {
5958 encode_klass_not_null(src);
5959 } else {
5960 if (Universe::narrow_klass_base() != NULL) {
5961 mov64(dst, (int64_t)Universe::narrow_klass_base());
5962 negq(dst);
5963 addq(dst, src);
5964 } else {
5965 movptr(dst, src);
5966 }
5967 if (Universe::narrow_klass_shift() != 0) {
5968 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5969 shrq(dst, LogKlassAlignmentInBytes);
5970 }
5971 }
5972 }
5974 // Function instr_size_for_decode_klass_not_null() counts the instructions
5975 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5976 // when (Universe::heap() != NULL). Hence, if the instructions they
5977 // generate change, then this method needs to be updated.
5978 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5979 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5980 if (Universe::narrow_klass_base() != NULL) {
5981 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5982 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5983 } else {
5984 // longest load decode klass function, mov64, leaq
5985 return 16;
5986 }
5987 }
5989 // !!! If the instructions that get generated here change then function
5990 // instr_size_for_decode_klass_not_null() needs to get updated.
5991 void MacroAssembler::decode_klass_not_null(Register r) {
5992 // Note: it will change flags
5993 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5994 assert(r != r12_heapbase, "Decoding a klass in r12");
5995 // Cannot assert, unverified entry point counts instructions (see .ad file)
5996 // vtableStubs also counts instructions in pd_code_size_limit.
5997 // Also do not verify_oop as this is called by verify_oop.
5998 if (Universe::narrow_klass_shift() != 0) {
5999 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6000 shlq(r, LogKlassAlignmentInBytes);
6001 }
6002 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6003 if (Universe::narrow_klass_base() != NULL) {
6004 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6005 addq(r, r12_heapbase);
6006 reinit_heapbase();
6007 }
6008 }
6010 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6011 // Note: it will change flags
6012 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6013 if (dst == src) {
6014 decode_klass_not_null(dst);
6015 } else {
6016 // Cannot assert, unverified entry point counts instructions (see .ad file)
6017 // vtableStubs also counts instructions in pd_code_size_limit.
6018 // Also do not verify_oop as this is called by verify_oop.
6019 mov64(dst, (int64_t)Universe::narrow_klass_base());
6020 if (Universe::narrow_klass_shift() != 0) {
6021 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6022 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6023 leaq(dst, Address(dst, src, Address::times_8, 0));
6024 } else {
6025 addq(dst, src);
6026 }
6027 }
6028 }
6030 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6031 assert (UseCompressedOops, "should only be used for compressed headers");
6032 assert (Universe::heap() != NULL, "java heap should be initialized");
6033 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6034 int oop_index = oop_recorder()->find_index(obj);
6035 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6036 mov_narrow_oop(dst, oop_index, rspec);
6037 }
6039 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6040 assert (UseCompressedOops, "should only be used for compressed headers");
6041 assert (Universe::heap() != NULL, "java heap should be initialized");
6042 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6043 int oop_index = oop_recorder()->find_index(obj);
6044 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6045 mov_narrow_oop(dst, oop_index, rspec);
6046 }
6048 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6049 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6050 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6051 int klass_index = oop_recorder()->find_index(k);
6052 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6053 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6054 }
6056 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6057 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6058 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6059 int klass_index = oop_recorder()->find_index(k);
6060 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6061 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6062 }
6064 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6065 assert (UseCompressedOops, "should only be used for compressed headers");
6066 assert (Universe::heap() != NULL, "java heap should be initialized");
6067 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6068 int oop_index = oop_recorder()->find_index(obj);
6069 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6070 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6071 }
6073 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6074 assert (UseCompressedOops, "should only be used for compressed headers");
6075 assert (Universe::heap() != NULL, "java heap should be initialized");
6076 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6077 int oop_index = oop_recorder()->find_index(obj);
6078 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6079 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6080 }
6082 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6083 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6084 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6085 int klass_index = oop_recorder()->find_index(k);
6086 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6087 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6088 }
6090 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6091 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6092 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6093 int klass_index = oop_recorder()->find_index(k);
6094 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6095 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6096 }
6098 void MacroAssembler::reinit_heapbase() {
6099 if (UseCompressedOops || UseCompressedClassPointers) {
6100 if (Universe::heap() != NULL) {
6101 if (Universe::narrow_oop_base() == NULL) {
6102 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6103 } else {
6104 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6105 }
6106 } else {
6107 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6108 }
6109 }
6110 }
6112 #endif // _LP64
6115 // C2 compiled method's prolog code.
6116 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6118 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6119 // NativeJump::patch_verified_entry will be able to patch out the entry
6120 // code safely. The push to verify stack depth is ok at 5 bytes,
6121 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6122 // stack bang then we must use the 6 byte frame allocation even if
6123 // we have no frame. :-(
6124 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6126 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6127 // Remove word for return addr
6128 framesize -= wordSize;
6129 stack_bang_size -= wordSize;
6131 // Calls to C2R adapters often do not accept exceptional returns.
6132 // We require that their callers must bang for them. But be careful, because
6133 // some VM calls (such as call site linkage) can use several kilobytes of
6134 // stack. But the stack safety zone should account for that.
6135 // See bugs 4446381, 4468289, 4497237.
6136 if (stack_bang_size > 0) {
6137 generate_stack_overflow_check(stack_bang_size);
6139 // We always push rbp, so that on return to interpreter rbp, will be
6140 // restored correctly and we can correct the stack.
6141 push(rbp);
6142 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6143 if (PreserveFramePointer) {
6144 mov(rbp, rsp);
6145 }
6146 // Remove word for ebp
6147 framesize -= wordSize;
6149 // Create frame
6150 if (framesize) {
6151 subptr(rsp, framesize);
6152 }
6153 } else {
6154 // Create frame (force generation of a 4 byte immediate value)
6155 subptr_imm32(rsp, framesize);
6157 // Save RBP register now.
6158 framesize -= wordSize;
6159 movptr(Address(rsp, framesize), rbp);
6160 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6161 if (PreserveFramePointer) {
6162 movptr(rbp, rsp);
6163 if (framesize > 0) {
6164 addptr(rbp, framesize);
6165 }
6166 }
6167 }
6169 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6170 framesize -= wordSize;
6171 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6172 }
6174 #ifndef _LP64
6175 // If method sets FPU control word do it now
6176 if (fp_mode_24b) {
6177 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6178 }
6179 if (UseSSE >= 2 && VerifyFPU) {
6180 verify_FPU(0, "FPU stack must be clean on entry");
6181 }
6182 #endif
6184 #ifdef ASSERT
6185 if (VerifyStackAtCalls) {
6186 Label L;
6187 push(rax);
6188 mov(rax, rsp);
6189 andptr(rax, StackAlignmentInBytes-1);
6190 cmpptr(rax, StackAlignmentInBytes-wordSize);
6191 pop(rax);
6192 jcc(Assembler::equal, L);
6193 STOP("Stack is not properly aligned!");
6194 bind(L);
6195 }
6196 #endif
6198 }
6200 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6201 // cnt - number of qwords (8-byte words).
6202 // base - start address, qword aligned.
6203 assert(base==rdi, "base register must be edi for rep stos");
6204 assert(tmp==rax, "tmp register must be eax for rep stos");
6205 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6207 xorptr(tmp, tmp);
6208 if (UseFastStosb) {
6209 shlptr(cnt,3); // convert to number of bytes
6210 rep_stosb();
6211 } else {
6212 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6213 rep_stos();
6214 }
6215 }
6217 // IndexOf for constant substrings with size >= 8 chars
6218 // which don't need to be loaded through stack.
6219 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6220 Register cnt1, Register cnt2,
6221 int int_cnt2, Register result,
6222 XMMRegister vec, Register tmp) {
6223 ShortBranchVerifier sbv(this);
6224 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6226 // This method uses pcmpestri inxtruction with bound registers
6227 // inputs:
6228 // xmm - substring
6229 // rax - substring length (elements count)
6230 // mem - scanned string
6231 // rdx - string length (elements count)
6232 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6233 // outputs:
6234 // rcx - matched index in string
6235 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6237 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6238 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6239 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6241 // Note, inline_string_indexOf() generates checks:
6242 // if (substr.count > string.count) return -1;
6243 // if (substr.count == 0) return 0;
6244 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6246 // Load substring.
6247 movdqu(vec, Address(str2, 0));
6248 movl(cnt2, int_cnt2);
6249 movptr(result, str1); // string addr
6251 if (int_cnt2 > 8) {
6252 jmpb(SCAN_TO_SUBSTR);
6254 // Reload substr for rescan, this code
6255 // is executed only for large substrings (> 8 chars)
6256 bind(RELOAD_SUBSTR);
6257 movdqu(vec, Address(str2, 0));
6258 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6260 bind(RELOAD_STR);
6261 // We came here after the beginning of the substring was
6262 // matched but the rest of it was not so we need to search
6263 // again. Start from the next element after the previous match.
6265 // cnt2 is number of substring reminding elements and
6266 // cnt1 is number of string reminding elements when cmp failed.
6267 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6268 subl(cnt1, cnt2);
6269 addl(cnt1, int_cnt2);
6270 movl(cnt2, int_cnt2); // Now restore cnt2
6272 decrementl(cnt1); // Shift to next element
6273 cmpl(cnt1, cnt2);
6274 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6276 addptr(result, 2);
6278 } // (int_cnt2 > 8)
6280 // Scan string for start of substr in 16-byte vectors
6281 bind(SCAN_TO_SUBSTR);
6282 pcmpestri(vec, Address(result, 0), 0x0d);
6283 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6284 subl(cnt1, 8);
6285 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6286 cmpl(cnt1, cnt2);
6287 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6288 addptr(result, 16);
6289 jmpb(SCAN_TO_SUBSTR);
6291 // Found a potential substr
6292 bind(FOUND_CANDIDATE);
6293 // Matched whole vector if first element matched (tmp(rcx) == 0).
6294 if (int_cnt2 == 8) {
6295 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6296 } else { // int_cnt2 > 8
6297 jccb(Assembler::overflow, FOUND_SUBSTR);
6298 }
6299 // After pcmpestri tmp(rcx) contains matched element index
6300 // Compute start addr of substr
6301 lea(result, Address(result, tmp, Address::times_2));
6303 // Make sure string is still long enough
6304 subl(cnt1, tmp);
6305 cmpl(cnt1, cnt2);
6306 if (int_cnt2 == 8) {
6307 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6308 } else { // int_cnt2 > 8
6309 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6310 }
6311 // Left less then substring.
6313 bind(RET_NOT_FOUND);
6314 movl(result, -1);
6315 jmpb(EXIT);
6317 if (int_cnt2 > 8) {
6318 // This code is optimized for the case when whole substring
6319 // is matched if its head is matched.
6320 bind(MATCH_SUBSTR_HEAD);
6321 pcmpestri(vec, Address(result, 0), 0x0d);
6322 // Reload only string if does not match
6323 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6325 Label CONT_SCAN_SUBSTR;
6326 // Compare the rest of substring (> 8 chars).
6327 bind(FOUND_SUBSTR);
6328 // First 8 chars are already matched.
6329 negptr(cnt2);
6330 addptr(cnt2, 8);
6332 bind(SCAN_SUBSTR);
6333 subl(cnt1, 8);
6334 cmpl(cnt2, -8); // Do not read beyond substring
6335 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6336 // Back-up strings to avoid reading beyond substring:
6337 // cnt1 = cnt1 - cnt2 + 8
6338 addl(cnt1, cnt2); // cnt2 is negative
6339 addl(cnt1, 8);
6340 movl(cnt2, 8); negptr(cnt2);
6341 bind(CONT_SCAN_SUBSTR);
6342 if (int_cnt2 < (int)G) {
6343 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6344 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6345 } else {
6346 // calculate index in register to avoid integer overflow (int_cnt2*2)
6347 movl(tmp, int_cnt2);
6348 addptr(tmp, cnt2);
6349 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6350 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6351 }
6352 // Need to reload strings pointers if not matched whole vector
6353 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6354 addptr(cnt2, 8);
6355 jcc(Assembler::negative, SCAN_SUBSTR);
6356 // Fall through if found full substring
6358 } // (int_cnt2 > 8)
6360 bind(RET_FOUND);
6361 // Found result if we matched full small substring.
6362 // Compute substr offset
6363 subptr(result, str1);
6364 shrl(result, 1); // index
6365 bind(EXIT);
6367 } // string_indexofC8
6369 // Small strings are loaded through stack if they cross page boundary.
6370 void MacroAssembler::string_indexof(Register str1, Register str2,
6371 Register cnt1, Register cnt2,
6372 int int_cnt2, Register result,
6373 XMMRegister vec, Register tmp) {
6374 ShortBranchVerifier sbv(this);
6375 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6376 //
6377 // int_cnt2 is length of small (< 8 chars) constant substring
6378 // or (-1) for non constant substring in which case its length
6379 // is in cnt2 register.
6380 //
6381 // Note, inline_string_indexOf() generates checks:
6382 // if (substr.count > string.count) return -1;
6383 // if (substr.count == 0) return 0;
6384 //
6385 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6387 // This method uses pcmpestri inxtruction with bound registers
6388 // inputs:
6389 // xmm - substring
6390 // rax - substring length (elements count)
6391 // mem - scanned string
6392 // rdx - string length (elements count)
6393 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6394 // outputs:
6395 // rcx - matched index in string
6396 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6398 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6399 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6400 FOUND_CANDIDATE;
6402 { //========================================================
6403 // We don't know where these strings are located
6404 // and we can't read beyond them. Load them through stack.
6405 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6407 movptr(tmp, rsp); // save old SP
6409 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6410 if (int_cnt2 == 1) { // One char
6411 load_unsigned_short(result, Address(str2, 0));
6412 movdl(vec, result); // move 32 bits
6413 } else if (int_cnt2 == 2) { // Two chars
6414 movdl(vec, Address(str2, 0)); // move 32 bits
6415 } else if (int_cnt2 == 4) { // Four chars
6416 movq(vec, Address(str2, 0)); // move 64 bits
6417 } else { // cnt2 = { 3, 5, 6, 7 }
6418 // Array header size is 12 bytes in 32-bit VM
6419 // + 6 bytes for 3 chars == 18 bytes,
6420 // enough space to load vec and shift.
6421 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6422 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6423 psrldq(vec, 16-(int_cnt2*2));
6424 }
6425 } else { // not constant substring
6426 cmpl(cnt2, 8);
6427 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6429 // We can read beyond string if srt+16 does not cross page boundary
6430 // since heaps are aligned and mapped by pages.
6431 assert(os::vm_page_size() < (int)G, "default page should be small");
6432 movl(result, str2); // We need only low 32 bits
6433 andl(result, (os::vm_page_size()-1));
6434 cmpl(result, (os::vm_page_size()-16));
6435 jccb(Assembler::belowEqual, CHECK_STR);
6437 // Move small strings to stack to allow load 16 bytes into vec.
6438 subptr(rsp, 16);
6439 int stk_offset = wordSize-2;
6440 push(cnt2);
6442 bind(COPY_SUBSTR);
6443 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6444 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6445 decrement(cnt2);
6446 jccb(Assembler::notZero, COPY_SUBSTR);
6448 pop(cnt2);
6449 movptr(str2, rsp); // New substring address
6450 } // non constant
6452 bind(CHECK_STR);
6453 cmpl(cnt1, 8);
6454 jccb(Assembler::aboveEqual, BIG_STRINGS);
6456 // Check cross page boundary.
6457 movl(result, str1); // We need only low 32 bits
6458 andl(result, (os::vm_page_size()-1));
6459 cmpl(result, (os::vm_page_size()-16));
6460 jccb(Assembler::belowEqual, BIG_STRINGS);
6462 subptr(rsp, 16);
6463 int stk_offset = -2;
6464 if (int_cnt2 < 0) { // not constant
6465 push(cnt2);
6466 stk_offset += wordSize;
6467 }
6468 movl(cnt2, cnt1);
6470 bind(COPY_STR);
6471 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6472 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6473 decrement(cnt2);
6474 jccb(Assembler::notZero, COPY_STR);
6476 if (int_cnt2 < 0) { // not constant
6477 pop(cnt2);
6478 }
6479 movptr(str1, rsp); // New string address
6481 bind(BIG_STRINGS);
6482 // Load substring.
6483 if (int_cnt2 < 0) { // -1
6484 movdqu(vec, Address(str2, 0));
6485 push(cnt2); // substr count
6486 push(str2); // substr addr
6487 push(str1); // string addr
6488 } else {
6489 // Small (< 8 chars) constant substrings are loaded already.
6490 movl(cnt2, int_cnt2);
6491 }
6492 push(tmp); // original SP
6494 } // Finished loading
6496 //========================================================
6497 // Start search
6498 //
6500 movptr(result, str1); // string addr
6502 if (int_cnt2 < 0) { // Only for non constant substring
6503 jmpb(SCAN_TO_SUBSTR);
6505 // SP saved at sp+0
6506 // String saved at sp+1*wordSize
6507 // Substr saved at sp+2*wordSize
6508 // Substr count saved at sp+3*wordSize
6510 // Reload substr for rescan, this code
6511 // is executed only for large substrings (> 8 chars)
6512 bind(RELOAD_SUBSTR);
6513 movptr(str2, Address(rsp, 2*wordSize));
6514 movl(cnt2, Address(rsp, 3*wordSize));
6515 movdqu(vec, Address(str2, 0));
6516 // We came here after the beginning of the substring was
6517 // matched but the rest of it was not so we need to search
6518 // again. Start from the next element after the previous match.
6519 subptr(str1, result); // Restore counter
6520 shrl(str1, 1);
6521 addl(cnt1, str1);
6522 decrementl(cnt1); // Shift to next element
6523 cmpl(cnt1, cnt2);
6524 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6526 addptr(result, 2);
6527 } // non constant
6529 // Scan string for start of substr in 16-byte vectors
6530 bind(SCAN_TO_SUBSTR);
6531 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6532 pcmpestri(vec, Address(result, 0), 0x0d);
6533 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6534 subl(cnt1, 8);
6535 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6536 cmpl(cnt1, cnt2);
6537 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6538 addptr(result, 16);
6540 bind(ADJUST_STR);
6541 cmpl(cnt1, 8); // Do not read beyond string
6542 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6543 // Back-up string to avoid reading beyond string.
6544 lea(result, Address(result, cnt1, Address::times_2, -16));
6545 movl(cnt1, 8);
6546 jmpb(SCAN_TO_SUBSTR);
6548 // Found a potential substr
6549 bind(FOUND_CANDIDATE);
6550 // After pcmpestri tmp(rcx) contains matched element index
6552 // Make sure string is still long enough
6553 subl(cnt1, tmp);
6554 cmpl(cnt1, cnt2);
6555 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6556 // Left less then substring.
6558 bind(RET_NOT_FOUND);
6559 movl(result, -1);
6560 jmpb(CLEANUP);
6562 bind(FOUND_SUBSTR);
6563 // Compute start addr of substr
6564 lea(result, Address(result, tmp, Address::times_2));
6566 if (int_cnt2 > 0) { // Constant substring
6567 // Repeat search for small substring (< 8 chars)
6568 // from new point without reloading substring.
6569 // Have to check that we don't read beyond string.
6570 cmpl(tmp, 8-int_cnt2);
6571 jccb(Assembler::greater, ADJUST_STR);
6572 // Fall through if matched whole substring.
6573 } else { // non constant
6574 assert(int_cnt2 == -1, "should be != 0");
6576 addl(tmp, cnt2);
6577 // Found result if we matched whole substring.
6578 cmpl(tmp, 8);
6579 jccb(Assembler::lessEqual, RET_FOUND);
6581 // Repeat search for small substring (<= 8 chars)
6582 // from new point 'str1' without reloading substring.
6583 cmpl(cnt2, 8);
6584 // Have to check that we don't read beyond string.
6585 jccb(Assembler::lessEqual, ADJUST_STR);
6587 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6588 // Compare the rest of substring (> 8 chars).
6589 movptr(str1, result);
6591 cmpl(tmp, cnt2);
6592 // First 8 chars are already matched.
6593 jccb(Assembler::equal, CHECK_NEXT);
6595 bind(SCAN_SUBSTR);
6596 pcmpestri(vec, Address(str1, 0), 0x0d);
6597 // Need to reload strings pointers if not matched whole vector
6598 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6600 bind(CHECK_NEXT);
6601 subl(cnt2, 8);
6602 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6603 addptr(str1, 16);
6604 addptr(str2, 16);
6605 subl(cnt1, 8);
6606 cmpl(cnt2, 8); // Do not read beyond substring
6607 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6608 // Back-up strings to avoid reading beyond substring.
6609 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6610 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6611 subl(cnt1, cnt2);
6612 movl(cnt2, 8);
6613 addl(cnt1, 8);
6614 bind(CONT_SCAN_SUBSTR);
6615 movdqu(vec, Address(str2, 0));
6616 jmpb(SCAN_SUBSTR);
6618 bind(RET_FOUND_LONG);
6619 movptr(str1, Address(rsp, wordSize));
6620 } // non constant
6622 bind(RET_FOUND);
6623 // Compute substr offset
6624 subptr(result, str1);
6625 shrl(result, 1); // index
6627 bind(CLEANUP);
6628 pop(rsp); // restore SP
6630 } // string_indexof
6632 // Compare strings.
6633 void MacroAssembler::string_compare(Register str1, Register str2,
6634 Register cnt1, Register cnt2, Register result,
6635 XMMRegister vec1) {
6636 ShortBranchVerifier sbv(this);
6637 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6639 // Compute the minimum of the string lengths and the
6640 // difference of the string lengths (stack).
6641 // Do the conditional move stuff
6642 movl(result, cnt1);
6643 subl(cnt1, cnt2);
6644 push(cnt1);
6645 cmov32(Assembler::lessEqual, cnt2, result);
6647 // Is the minimum length zero?
6648 testl(cnt2, cnt2);
6649 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6651 // Compare first characters
6652 load_unsigned_short(result, Address(str1, 0));
6653 load_unsigned_short(cnt1, Address(str2, 0));
6654 subl(result, cnt1);
6655 jcc(Assembler::notZero, POP_LABEL);
6656 cmpl(cnt2, 1);
6657 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6659 // Check if the strings start at the same location.
6660 cmpptr(str1, str2);
6661 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6663 Address::ScaleFactor scale = Address::times_2;
6664 int stride = 8;
6666 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6667 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6668 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6669 Label COMPARE_TAIL_LONG;
6670 int pcmpmask = 0x19;
6672 // Setup to compare 16-chars (32-bytes) vectors,
6673 // start from first character again because it has aligned address.
6674 int stride2 = 16;
6675 int adr_stride = stride << scale;
6676 int adr_stride2 = stride2 << scale;
6678 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6679 // rax and rdx are used by pcmpestri as elements counters
6680 movl(result, cnt2);
6681 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6682 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6684 // fast path : compare first 2 8-char vectors.
6685 bind(COMPARE_16_CHARS);
6686 movdqu(vec1, Address(str1, 0));
6687 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6688 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6690 movdqu(vec1, Address(str1, adr_stride));
6691 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6692 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6693 addl(cnt1, stride);
6695 // Compare the characters at index in cnt1
6696 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6697 load_unsigned_short(result, Address(str1, cnt1, scale));
6698 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6699 subl(result, cnt2);
6700 jmp(POP_LABEL);
6702 // Setup the registers to start vector comparison loop
6703 bind(COMPARE_WIDE_VECTORS);
6704 lea(str1, Address(str1, result, scale));
6705 lea(str2, Address(str2, result, scale));
6706 subl(result, stride2);
6707 subl(cnt2, stride2);
6708 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6709 negptr(result);
6711 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6712 bind(COMPARE_WIDE_VECTORS_LOOP);
6713 vmovdqu(vec1, Address(str1, result, scale));
6714 vpxor(vec1, Address(str2, result, scale));
6715 vptest(vec1, vec1);
6716 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6717 addptr(result, stride2);
6718 subl(cnt2, stride2);
6719 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6720 // clean upper bits of YMM registers
6721 vpxor(vec1, vec1);
6723 // compare wide vectors tail
6724 bind(COMPARE_WIDE_TAIL);
6725 testptr(result, result);
6726 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6728 movl(result, stride2);
6729 movl(cnt2, result);
6730 negptr(result);
6731 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6733 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6734 bind(VECTOR_NOT_EQUAL);
6735 // clean upper bits of YMM registers
6736 vpxor(vec1, vec1);
6737 lea(str1, Address(str1, result, scale));
6738 lea(str2, Address(str2, result, scale));
6739 jmp(COMPARE_16_CHARS);
6741 // Compare tail chars, length between 1 to 15 chars
6742 bind(COMPARE_TAIL_LONG);
6743 movl(cnt2, result);
6744 cmpl(cnt2, stride);
6745 jccb(Assembler::less, COMPARE_SMALL_STR);
6747 movdqu(vec1, Address(str1, 0));
6748 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6749 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6750 subptr(cnt2, stride);
6751 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6752 lea(str1, Address(str1, result, scale));
6753 lea(str2, Address(str2, result, scale));
6754 negptr(cnt2);
6755 jmpb(WHILE_HEAD_LABEL);
6757 bind(COMPARE_SMALL_STR);
6758 } else if (UseSSE42Intrinsics) {
6759 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6760 int pcmpmask = 0x19;
6761 // Setup to compare 8-char (16-byte) vectors,
6762 // start from first character again because it has aligned address.
6763 movl(result, cnt2);
6764 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6765 jccb(Assembler::zero, COMPARE_TAIL);
6767 lea(str1, Address(str1, result, scale));
6768 lea(str2, Address(str2, result, scale));
6769 negptr(result);
6771 // pcmpestri
6772 // inputs:
6773 // vec1- substring
6774 // rax - negative string length (elements count)
6775 // mem - scaned string
6776 // rdx - string length (elements count)
6777 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6778 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6779 // outputs:
6780 // rcx - first mismatched element index
6781 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6783 bind(COMPARE_WIDE_VECTORS);
6784 movdqu(vec1, Address(str1, result, scale));
6785 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6786 // After pcmpestri cnt1(rcx) contains mismatched element index
6788 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6789 addptr(result, stride);
6790 subptr(cnt2, stride);
6791 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6793 // compare wide vectors tail
6794 testptr(result, result);
6795 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6797 movl(cnt2, stride);
6798 movl(result, stride);
6799 negptr(result);
6800 movdqu(vec1, Address(str1, result, scale));
6801 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6802 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6804 // Mismatched characters in the vectors
6805 bind(VECTOR_NOT_EQUAL);
6806 addptr(cnt1, result);
6807 load_unsigned_short(result, Address(str1, cnt1, scale));
6808 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6809 subl(result, cnt2);
6810 jmpb(POP_LABEL);
6812 bind(COMPARE_TAIL); // limit is zero
6813 movl(cnt2, result);
6814 // Fallthru to tail compare
6815 }
6816 // Shift str2 and str1 to the end of the arrays, negate min
6817 lea(str1, Address(str1, cnt2, scale));
6818 lea(str2, Address(str2, cnt2, scale));
6819 decrementl(cnt2); // first character was compared already
6820 negptr(cnt2);
6822 // Compare the rest of the elements
6823 bind(WHILE_HEAD_LABEL);
6824 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6825 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6826 subl(result, cnt1);
6827 jccb(Assembler::notZero, POP_LABEL);
6828 increment(cnt2);
6829 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6831 // Strings are equal up to min length. Return the length difference.
6832 bind(LENGTH_DIFF_LABEL);
6833 pop(result);
6834 jmpb(DONE_LABEL);
6836 // Discard the stored length difference
6837 bind(POP_LABEL);
6838 pop(cnt1);
6840 // That's it
6841 bind(DONE_LABEL);
6842 }
6844 // Compare char[] arrays aligned to 4 bytes or substrings.
6845 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6846 Register limit, Register result, Register chr,
6847 XMMRegister vec1, XMMRegister vec2) {
6848 ShortBranchVerifier sbv(this);
6849 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6851 int length_offset = arrayOopDesc::length_offset_in_bytes();
6852 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6854 // Check the input args
6855 cmpptr(ary1, ary2);
6856 jcc(Assembler::equal, TRUE_LABEL);
6858 if (is_array_equ) {
6859 // Need additional checks for arrays_equals.
6860 testptr(ary1, ary1);
6861 jcc(Assembler::zero, FALSE_LABEL);
6862 testptr(ary2, ary2);
6863 jcc(Assembler::zero, FALSE_LABEL);
6865 // Check the lengths
6866 movl(limit, Address(ary1, length_offset));
6867 cmpl(limit, Address(ary2, length_offset));
6868 jcc(Assembler::notEqual, FALSE_LABEL);
6869 }
6871 // count == 0
6872 testl(limit, limit);
6873 jcc(Assembler::zero, TRUE_LABEL);
6875 if (is_array_equ) {
6876 // Load array address
6877 lea(ary1, Address(ary1, base_offset));
6878 lea(ary2, Address(ary2, base_offset));
6879 }
6881 shll(limit, 1); // byte count != 0
6882 movl(result, limit); // copy
6884 if (UseAVX >= 2) {
6885 // With AVX2, use 32-byte vector compare
6886 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6888 // Compare 32-byte vectors
6889 andl(result, 0x0000001e); // tail count (in bytes)
6890 andl(limit, 0xffffffe0); // vector count (in bytes)
6891 jccb(Assembler::zero, COMPARE_TAIL);
6893 lea(ary1, Address(ary1, limit, Address::times_1));
6894 lea(ary2, Address(ary2, limit, Address::times_1));
6895 negptr(limit);
6897 bind(COMPARE_WIDE_VECTORS);
6898 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6899 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6900 vpxor(vec1, vec2);
6902 vptest(vec1, vec1);
6903 jccb(Assembler::notZero, FALSE_LABEL);
6904 addptr(limit, 32);
6905 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6907 testl(result, result);
6908 jccb(Assembler::zero, TRUE_LABEL);
6910 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6911 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6912 vpxor(vec1, vec2);
6914 vptest(vec1, vec1);
6915 jccb(Assembler::notZero, FALSE_LABEL);
6916 jmpb(TRUE_LABEL);
6918 bind(COMPARE_TAIL); // limit is zero
6919 movl(limit, result);
6920 // Fallthru to tail compare
6921 } else if (UseSSE42Intrinsics) {
6922 // With SSE4.2, use double quad vector compare
6923 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6925 // Compare 16-byte vectors
6926 andl(result, 0x0000000e); // tail count (in bytes)
6927 andl(limit, 0xfffffff0); // vector count (in bytes)
6928 jccb(Assembler::zero, COMPARE_TAIL);
6930 lea(ary1, Address(ary1, limit, Address::times_1));
6931 lea(ary2, Address(ary2, limit, Address::times_1));
6932 negptr(limit);
6934 bind(COMPARE_WIDE_VECTORS);
6935 movdqu(vec1, Address(ary1, limit, Address::times_1));
6936 movdqu(vec2, Address(ary2, limit, Address::times_1));
6937 pxor(vec1, vec2);
6939 ptest(vec1, vec1);
6940 jccb(Assembler::notZero, FALSE_LABEL);
6941 addptr(limit, 16);
6942 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6944 testl(result, result);
6945 jccb(Assembler::zero, TRUE_LABEL);
6947 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6948 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6949 pxor(vec1, vec2);
6951 ptest(vec1, vec1);
6952 jccb(Assembler::notZero, FALSE_LABEL);
6953 jmpb(TRUE_LABEL);
6955 bind(COMPARE_TAIL); // limit is zero
6956 movl(limit, result);
6957 // Fallthru to tail compare
6958 }
6960 // Compare 4-byte vectors
6961 andl(limit, 0xfffffffc); // vector count (in bytes)
6962 jccb(Assembler::zero, COMPARE_CHAR);
6964 lea(ary1, Address(ary1, limit, Address::times_1));
6965 lea(ary2, Address(ary2, limit, Address::times_1));
6966 negptr(limit);
6968 bind(COMPARE_VECTORS);
6969 movl(chr, Address(ary1, limit, Address::times_1));
6970 cmpl(chr, Address(ary2, limit, Address::times_1));
6971 jccb(Assembler::notEqual, FALSE_LABEL);
6972 addptr(limit, 4);
6973 jcc(Assembler::notZero, COMPARE_VECTORS);
6975 // Compare trailing char (final 2 bytes), if any
6976 bind(COMPARE_CHAR);
6977 testl(result, 0x2); // tail char
6978 jccb(Assembler::zero, TRUE_LABEL);
6979 load_unsigned_short(chr, Address(ary1, 0));
6980 load_unsigned_short(limit, Address(ary2, 0));
6981 cmpl(chr, limit);
6982 jccb(Assembler::notEqual, FALSE_LABEL);
6984 bind(TRUE_LABEL);
6985 movl(result, 1); // return true
6986 jmpb(DONE);
6988 bind(FALSE_LABEL);
6989 xorl(result, result); // return false
6991 // That's it
6992 bind(DONE);
6993 if (UseAVX >= 2) {
6994 // clean upper bits of YMM registers
6995 vpxor(vec1, vec1);
6996 vpxor(vec2, vec2);
6997 }
6998 }
7000 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7001 Register to, Register value, Register count,
7002 Register rtmp, XMMRegister xtmp) {
7003 ShortBranchVerifier sbv(this);
7004 assert_different_registers(to, value, count, rtmp);
7005 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
7006 Label L_fill_2_bytes, L_fill_4_bytes;
7008 int shift = -1;
7009 switch (t) {
7010 case T_BYTE:
7011 shift = 2;
7012 break;
7013 case T_SHORT:
7014 shift = 1;
7015 break;
7016 case T_INT:
7017 shift = 0;
7018 break;
7019 default: ShouldNotReachHere();
7020 }
7022 if (t == T_BYTE) {
7023 andl(value, 0xff);
7024 movl(rtmp, value);
7025 shll(rtmp, 8);
7026 orl(value, rtmp);
7027 }
7028 if (t == T_SHORT) {
7029 andl(value, 0xffff);
7030 }
7031 if (t == T_BYTE || t == T_SHORT) {
7032 movl(rtmp, value);
7033 shll(rtmp, 16);
7034 orl(value, rtmp);
7035 }
7037 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7038 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7039 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7040 // align source address at 4 bytes address boundary
7041 if (t == T_BYTE) {
7042 // One byte misalignment happens only for byte arrays
7043 testptr(to, 1);
7044 jccb(Assembler::zero, L_skip_align1);
7045 movb(Address(to, 0), value);
7046 increment(to);
7047 decrement(count);
7048 BIND(L_skip_align1);
7049 }
7050 // Two bytes misalignment happens only for byte and short (char) arrays
7051 testptr(to, 2);
7052 jccb(Assembler::zero, L_skip_align2);
7053 movw(Address(to, 0), value);
7054 addptr(to, 2);
7055 subl(count, 1<<(shift-1));
7056 BIND(L_skip_align2);
7057 }
7058 if (UseSSE < 2) {
7059 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7060 // Fill 32-byte chunks
7061 subl(count, 8 << shift);
7062 jcc(Assembler::less, L_check_fill_8_bytes);
7063 align(16);
7065 BIND(L_fill_32_bytes_loop);
7067 for (int i = 0; i < 32; i += 4) {
7068 movl(Address(to, i), value);
7069 }
7071 addptr(to, 32);
7072 subl(count, 8 << shift);
7073 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7074 BIND(L_check_fill_8_bytes);
7075 addl(count, 8 << shift);
7076 jccb(Assembler::zero, L_exit);
7077 jmpb(L_fill_8_bytes);
7079 //
7080 // length is too short, just fill qwords
7081 //
7082 BIND(L_fill_8_bytes_loop);
7083 movl(Address(to, 0), value);
7084 movl(Address(to, 4), value);
7085 addptr(to, 8);
7086 BIND(L_fill_8_bytes);
7087 subl(count, 1 << (shift + 1));
7088 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7089 // fall through to fill 4 bytes
7090 } else {
7091 Label L_fill_32_bytes;
7092 if (!UseUnalignedLoadStores) {
7093 // align to 8 bytes, we know we are 4 byte aligned to start
7094 testptr(to, 4);
7095 jccb(Assembler::zero, L_fill_32_bytes);
7096 movl(Address(to, 0), value);
7097 addptr(to, 4);
7098 subl(count, 1<<shift);
7099 }
7100 BIND(L_fill_32_bytes);
7101 {
7102 assert( UseSSE >= 2, "supported cpu only" );
7103 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7104 movdl(xtmp, value);
7105 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7106 // Fill 64-byte chunks
7107 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7108 vpbroadcastd(xtmp, xtmp);
7110 subl(count, 16 << shift);
7111 jcc(Assembler::less, L_check_fill_32_bytes);
7112 align(16);
7114 BIND(L_fill_64_bytes_loop);
7115 vmovdqu(Address(to, 0), xtmp);
7116 vmovdqu(Address(to, 32), xtmp);
7117 addptr(to, 64);
7118 subl(count, 16 << shift);
7119 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7121 BIND(L_check_fill_32_bytes);
7122 addl(count, 8 << shift);
7123 jccb(Assembler::less, L_check_fill_8_bytes);
7124 vmovdqu(Address(to, 0), xtmp);
7125 addptr(to, 32);
7126 subl(count, 8 << shift);
7128 BIND(L_check_fill_8_bytes);
7129 // clean upper bits of YMM registers
7130 movdl(xtmp, value);
7131 pshufd(xtmp, xtmp, 0);
7132 } else {
7133 // Fill 32-byte chunks
7134 pshufd(xtmp, xtmp, 0);
7136 subl(count, 8 << shift);
7137 jcc(Assembler::less, L_check_fill_8_bytes);
7138 align(16);
7140 BIND(L_fill_32_bytes_loop);
7142 if (UseUnalignedLoadStores) {
7143 movdqu(Address(to, 0), xtmp);
7144 movdqu(Address(to, 16), xtmp);
7145 } else {
7146 movq(Address(to, 0), xtmp);
7147 movq(Address(to, 8), xtmp);
7148 movq(Address(to, 16), xtmp);
7149 movq(Address(to, 24), xtmp);
7150 }
7152 addptr(to, 32);
7153 subl(count, 8 << shift);
7154 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7156 BIND(L_check_fill_8_bytes);
7157 }
7158 addl(count, 8 << shift);
7159 jccb(Assembler::zero, L_exit);
7160 jmpb(L_fill_8_bytes);
7162 //
7163 // length is too short, just fill qwords
7164 //
7165 BIND(L_fill_8_bytes_loop);
7166 movq(Address(to, 0), xtmp);
7167 addptr(to, 8);
7168 BIND(L_fill_8_bytes);
7169 subl(count, 1 << (shift + 1));
7170 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7171 }
7172 }
7173 // fill trailing 4 bytes
7174 BIND(L_fill_4_bytes);
7175 testl(count, 1<<shift);
7176 jccb(Assembler::zero, L_fill_2_bytes);
7177 movl(Address(to, 0), value);
7178 if (t == T_BYTE || t == T_SHORT) {
7179 addptr(to, 4);
7180 BIND(L_fill_2_bytes);
7181 // fill trailing 2 bytes
7182 testl(count, 1<<(shift-1));
7183 jccb(Assembler::zero, L_fill_byte);
7184 movw(Address(to, 0), value);
7185 if (t == T_BYTE) {
7186 addptr(to, 2);
7187 BIND(L_fill_byte);
7188 // fill trailing byte
7189 testl(count, 1);
7190 jccb(Assembler::zero, L_exit);
7191 movb(Address(to, 0), value);
7192 } else {
7193 BIND(L_fill_byte);
7194 }
7195 } else {
7196 BIND(L_fill_2_bytes);
7197 }
7198 BIND(L_exit);
7199 }
7201 // encode char[] to byte[] in ISO_8859_1
7202 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7203 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7204 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7205 Register tmp5, Register result) {
7206 // rsi: src
7207 // rdi: dst
7208 // rdx: len
7209 // rcx: tmp5
7210 // rax: result
7211 ShortBranchVerifier sbv(this);
7212 assert_different_registers(src, dst, len, tmp5, result);
7213 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7215 // set result
7216 xorl(result, result);
7217 // check for zero length
7218 testl(len, len);
7219 jcc(Assembler::zero, L_done);
7220 movl(result, len);
7222 // Setup pointers
7223 lea(src, Address(src, len, Address::times_2)); // char[]
7224 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7225 negptr(len);
7227 if (UseSSE42Intrinsics || UseAVX >= 2) {
7228 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7229 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7231 if (UseAVX >= 2) {
7232 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7233 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7234 movdl(tmp1Reg, tmp5);
7235 vpbroadcastd(tmp1Reg, tmp1Reg);
7236 jmpb(L_chars_32_check);
7238 bind(L_copy_32_chars);
7239 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7240 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7241 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7242 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7243 jccb(Assembler::notZero, L_copy_32_chars_exit);
7244 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7245 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
7246 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7248 bind(L_chars_32_check);
7249 addptr(len, 32);
7250 jccb(Assembler::lessEqual, L_copy_32_chars);
7252 bind(L_copy_32_chars_exit);
7253 subptr(len, 16);
7254 jccb(Assembler::greater, L_copy_16_chars_exit);
7256 } else if (UseSSE42Intrinsics) {
7257 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7258 movdl(tmp1Reg, tmp5);
7259 pshufd(tmp1Reg, tmp1Reg, 0);
7260 jmpb(L_chars_16_check);
7261 }
7263 bind(L_copy_16_chars);
7264 if (UseAVX >= 2) {
7265 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7266 vptest(tmp2Reg, tmp1Reg);
7267 jccb(Assembler::notZero, L_copy_16_chars_exit);
7268 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
7269 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
7270 } else {
7271 if (UseAVX > 0) {
7272 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7273 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7274 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
7275 } else {
7276 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7277 por(tmp2Reg, tmp3Reg);
7278 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7279 por(tmp2Reg, tmp4Reg);
7280 }
7281 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7282 jccb(Assembler::notZero, L_copy_16_chars_exit);
7283 packuswb(tmp3Reg, tmp4Reg);
7284 }
7285 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7287 bind(L_chars_16_check);
7288 addptr(len, 16);
7289 jccb(Assembler::lessEqual, L_copy_16_chars);
7291 bind(L_copy_16_chars_exit);
7292 if (UseAVX >= 2) {
7293 // clean upper bits of YMM registers
7294 vpxor(tmp2Reg, tmp2Reg);
7295 vpxor(tmp3Reg, tmp3Reg);
7296 vpxor(tmp4Reg, tmp4Reg);
7297 movdl(tmp1Reg, tmp5);
7298 pshufd(tmp1Reg, tmp1Reg, 0);
7299 }
7300 subptr(len, 8);
7301 jccb(Assembler::greater, L_copy_8_chars_exit);
7303 bind(L_copy_8_chars);
7304 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7305 ptest(tmp3Reg, tmp1Reg);
7306 jccb(Assembler::notZero, L_copy_8_chars_exit);
7307 packuswb(tmp3Reg, tmp1Reg);
7308 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7309 addptr(len, 8);
7310 jccb(Assembler::lessEqual, L_copy_8_chars);
7312 bind(L_copy_8_chars_exit);
7313 subptr(len, 8);
7314 jccb(Assembler::zero, L_done);
7315 }
7317 bind(L_copy_1_char);
7318 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7319 testl(tmp5, 0xff00); // check if Unicode char
7320 jccb(Assembler::notZero, L_copy_1_char_exit);
7321 movb(Address(dst, len, Address::times_1, 0), tmp5);
7322 addptr(len, 1);
7323 jccb(Assembler::less, L_copy_1_char);
7325 bind(L_copy_1_char_exit);
7326 addptr(result, len); // len is negative count of not processed elements
7327 bind(L_done);
7328 }
7330 #ifdef _LP64
7331 /**
7332 * Helper for multiply_to_len().
7333 */
7334 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7335 addq(dest_lo, src1);
7336 adcq(dest_hi, 0);
7337 addq(dest_lo, src2);
7338 adcq(dest_hi, 0);
7339 }
7341 /**
7342 * Multiply 64 bit by 64 bit first loop.
7343 */
7344 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7345 Register y, Register y_idx, Register z,
7346 Register carry, Register product,
7347 Register idx, Register kdx) {
7348 //
7349 // jlong carry, x[], y[], z[];
7350 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7351 // huge_128 product = y[idx] * x[xstart] + carry;
7352 // z[kdx] = (jlong)product;
7353 // carry = (jlong)(product >>> 64);
7354 // }
7355 // z[xstart] = carry;
7356 //
7358 Label L_first_loop, L_first_loop_exit;
7359 Label L_one_x, L_one_y, L_multiply;
7361 decrementl(xstart);
7362 jcc(Assembler::negative, L_one_x);
7364 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7365 rorq(x_xstart, 32); // convert big-endian to little-endian
7367 bind(L_first_loop);
7368 decrementl(idx);
7369 jcc(Assembler::negative, L_first_loop_exit);
7370 decrementl(idx);
7371 jcc(Assembler::negative, L_one_y);
7372 movq(y_idx, Address(y, idx, Address::times_4, 0));
7373 rorq(y_idx, 32); // convert big-endian to little-endian
7374 bind(L_multiply);
7375 movq(product, x_xstart);
7376 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7377 addq(product, carry);
7378 adcq(rdx, 0);
7379 subl(kdx, 2);
7380 movl(Address(z, kdx, Address::times_4, 4), product);
7381 shrq(product, 32);
7382 movl(Address(z, kdx, Address::times_4, 0), product);
7383 movq(carry, rdx);
7384 jmp(L_first_loop);
7386 bind(L_one_y);
7387 movl(y_idx, Address(y, 0));
7388 jmp(L_multiply);
7390 bind(L_one_x);
7391 movl(x_xstart, Address(x, 0));
7392 jmp(L_first_loop);
7394 bind(L_first_loop_exit);
7395 }
7397 /**
7398 * Multiply 64 bit by 64 bit and add 128 bit.
7399 */
7400 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7401 Register yz_idx, Register idx,
7402 Register carry, Register product, int offset) {
7403 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7404 // z[kdx] = (jlong)product;
7406 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7407 rorq(yz_idx, 32); // convert big-endian to little-endian
7408 movq(product, x_xstart);
7409 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7410 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7411 rorq(yz_idx, 32); // convert big-endian to little-endian
7413 add2_with_carry(rdx, product, carry, yz_idx);
7415 movl(Address(z, idx, Address::times_4, offset+4), product);
7416 shrq(product, 32);
7417 movl(Address(z, idx, Address::times_4, offset), product);
7419 }
7421 /**
7422 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7423 */
7424 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7425 Register yz_idx, Register idx, Register jdx,
7426 Register carry, Register product,
7427 Register carry2) {
7428 // jlong carry, x[], y[], z[];
7429 // int kdx = ystart+1;
7430 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7431 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7432 // z[kdx+idx+1] = (jlong)product;
7433 // jlong carry2 = (jlong)(product >>> 64);
7434 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7435 // z[kdx+idx] = (jlong)product;
7436 // carry = (jlong)(product >>> 64);
7437 // }
7438 // idx += 2;
7439 // if (idx > 0) {
7440 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7441 // z[kdx+idx] = (jlong)product;
7442 // carry = (jlong)(product >>> 64);
7443 // }
7444 //
7446 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7448 movl(jdx, idx);
7449 andl(jdx, 0xFFFFFFFC);
7450 shrl(jdx, 2);
7452 bind(L_third_loop);
7453 subl(jdx, 1);
7454 jcc(Assembler::negative, L_third_loop_exit);
7455 subl(idx, 4);
7457 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7458 movq(carry2, rdx);
7460 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7461 movq(carry, rdx);
7462 jmp(L_third_loop);
7464 bind (L_third_loop_exit);
7466 andl (idx, 0x3);
7467 jcc(Assembler::zero, L_post_third_loop_done);
7469 Label L_check_1;
7470 subl(idx, 2);
7471 jcc(Assembler::negative, L_check_1);
7473 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7474 movq(carry, rdx);
7476 bind (L_check_1);
7477 addl (idx, 0x2);
7478 andl (idx, 0x1);
7479 subl(idx, 1);
7480 jcc(Assembler::negative, L_post_third_loop_done);
7482 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7483 movq(product, x_xstart);
7484 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7485 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7487 add2_with_carry(rdx, product, yz_idx, carry);
7489 movl(Address(z, idx, Address::times_4, 0), product);
7490 shrq(product, 32);
7492 shlq(rdx, 32);
7493 orq(product, rdx);
7494 movq(carry, product);
7496 bind(L_post_third_loop_done);
7497 }
7499 /**
7500 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7501 *
7502 */
7503 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7504 Register carry, Register carry2,
7505 Register idx, Register jdx,
7506 Register yz_idx1, Register yz_idx2,
7507 Register tmp, Register tmp3, Register tmp4) {
7508 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7510 // jlong carry, x[], y[], z[];
7511 // int kdx = ystart+1;
7512 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7513 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7514 // jlong carry2 = (jlong)(tmp3 >>> 64);
7515 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7516 // carry = (jlong)(tmp4 >>> 64);
7517 // z[kdx+idx+1] = (jlong)tmp3;
7518 // z[kdx+idx] = (jlong)tmp4;
7519 // }
7520 // idx += 2;
7521 // if (idx > 0) {
7522 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7523 // z[kdx+idx] = (jlong)yz_idx1;
7524 // carry = (jlong)(yz_idx1 >>> 64);
7525 // }
7526 //
7528 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7530 movl(jdx, idx);
7531 andl(jdx, 0xFFFFFFFC);
7532 shrl(jdx, 2);
7534 bind(L_third_loop);
7535 subl(jdx, 1);
7536 jcc(Assembler::negative, L_third_loop_exit);
7537 subl(idx, 4);
7539 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7540 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7541 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7542 rorxq(yz_idx2, yz_idx2, 32);
7544 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7545 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7547 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7548 rorxq(yz_idx1, yz_idx1, 32);
7549 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7550 rorxq(yz_idx2, yz_idx2, 32);
7552 if (VM_Version::supports_adx()) {
7553 adcxq(tmp3, carry);
7554 adoxq(tmp3, yz_idx1);
7556 adcxq(tmp4, tmp);
7557 adoxq(tmp4, yz_idx2);
7559 movl(carry, 0); // does not affect flags
7560 adcxq(carry2, carry);
7561 adoxq(carry2, carry);
7562 } else {
7563 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7564 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7565 }
7566 movq(carry, carry2);
7568 movl(Address(z, idx, Address::times_4, 12), tmp3);
7569 shrq(tmp3, 32);
7570 movl(Address(z, idx, Address::times_4, 8), tmp3);
7572 movl(Address(z, idx, Address::times_4, 4), tmp4);
7573 shrq(tmp4, 32);
7574 movl(Address(z, idx, Address::times_4, 0), tmp4);
7576 jmp(L_third_loop);
7578 bind (L_third_loop_exit);
7580 andl (idx, 0x3);
7581 jcc(Assembler::zero, L_post_third_loop_done);
7583 Label L_check_1;
7584 subl(idx, 2);
7585 jcc(Assembler::negative, L_check_1);
7587 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7588 rorxq(yz_idx1, yz_idx1, 32);
7589 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7590 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7591 rorxq(yz_idx2, yz_idx2, 32);
7593 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7595 movl(Address(z, idx, Address::times_4, 4), tmp3);
7596 shrq(tmp3, 32);
7597 movl(Address(z, idx, Address::times_4, 0), tmp3);
7598 movq(carry, tmp4);
7600 bind (L_check_1);
7601 addl (idx, 0x2);
7602 andl (idx, 0x1);
7603 subl(idx, 1);
7604 jcc(Assembler::negative, L_post_third_loop_done);
7605 movl(tmp4, Address(y, idx, Address::times_4, 0));
7606 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7607 movl(tmp4, Address(z, idx, Address::times_4, 0));
7609 add2_with_carry(carry2, tmp3, tmp4, carry);
7611 movl(Address(z, idx, Address::times_4, 0), tmp3);
7612 shrq(tmp3, 32);
7614 shlq(carry2, 32);
7615 orq(tmp3, carry2);
7616 movq(carry, tmp3);
7618 bind(L_post_third_loop_done);
7619 }
7621 /**
7622 * Code for BigInteger::multiplyToLen() instrinsic.
7623 *
7624 * rdi: x
7625 * rax: xlen
7626 * rsi: y
7627 * rcx: ylen
7628 * r8: z
7629 * r11: zlen
7630 * r12: tmp1
7631 * r13: tmp2
7632 * r14: tmp3
7633 * r15: tmp4
7634 * rbx: tmp5
7635 *
7636 */
7637 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7638 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7639 ShortBranchVerifier sbv(this);
7640 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7642 push(tmp1);
7643 push(tmp2);
7644 push(tmp3);
7645 push(tmp4);
7646 push(tmp5);
7648 push(xlen);
7649 push(zlen);
7651 const Register idx = tmp1;
7652 const Register kdx = tmp2;
7653 const Register xstart = tmp3;
7655 const Register y_idx = tmp4;
7656 const Register carry = tmp5;
7657 const Register product = xlen;
7658 const Register x_xstart = zlen; // reuse register
7660 // First Loop.
7661 //
7662 // final static long LONG_MASK = 0xffffffffL;
7663 // int xstart = xlen - 1;
7664 // int ystart = ylen - 1;
7665 // long carry = 0;
7666 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7667 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7668 // z[kdx] = (int)product;
7669 // carry = product >>> 32;
7670 // }
7671 // z[xstart] = (int)carry;
7672 //
7674 movl(idx, ylen); // idx = ylen;
7675 movl(kdx, zlen); // kdx = xlen+ylen;
7676 xorq(carry, carry); // carry = 0;
7678 Label L_done;
7680 movl(xstart, xlen);
7681 decrementl(xstart);
7682 jcc(Assembler::negative, L_done);
7684 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7686 Label L_second_loop;
7687 testl(kdx, kdx);
7688 jcc(Assembler::zero, L_second_loop);
7690 Label L_carry;
7691 subl(kdx, 1);
7692 jcc(Assembler::zero, L_carry);
7694 movl(Address(z, kdx, Address::times_4, 0), carry);
7695 shrq(carry, 32);
7696 subl(kdx, 1);
7698 bind(L_carry);
7699 movl(Address(z, kdx, Address::times_4, 0), carry);
7701 // Second and third (nested) loops.
7702 //
7703 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7704 // carry = 0;
7705 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7706 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7707 // (z[k] & LONG_MASK) + carry;
7708 // z[k] = (int)product;
7709 // carry = product >>> 32;
7710 // }
7711 // z[i] = (int)carry;
7712 // }
7713 //
7714 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7716 const Register jdx = tmp1;
7718 bind(L_second_loop);
7719 xorl(carry, carry); // carry = 0;
7720 movl(jdx, ylen); // j = ystart+1
7722 subl(xstart, 1); // i = xstart-1;
7723 jcc(Assembler::negative, L_done);
7725 push (z);
7727 Label L_last_x;
7728 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7729 subl(xstart, 1); // i = xstart-1;
7730 jcc(Assembler::negative, L_last_x);
7732 if (UseBMI2Instructions) {
7733 movq(rdx, Address(x, xstart, Address::times_4, 0));
7734 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7735 } else {
7736 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7737 rorq(x_xstart, 32); // convert big-endian to little-endian
7738 }
7740 Label L_third_loop_prologue;
7741 bind(L_third_loop_prologue);
7743 push (x);
7744 push (xstart);
7745 push (ylen);
7748 if (UseBMI2Instructions) {
7749 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7750 } else { // !UseBMI2Instructions
7751 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7752 }
7754 pop(ylen);
7755 pop(xlen);
7756 pop(x);
7757 pop(z);
7759 movl(tmp3, xlen);
7760 addl(tmp3, 1);
7761 movl(Address(z, tmp3, Address::times_4, 0), carry);
7762 subl(tmp3, 1);
7763 jccb(Assembler::negative, L_done);
7765 shrq(carry, 32);
7766 movl(Address(z, tmp3, Address::times_4, 0), carry);
7767 jmp(L_second_loop);
7769 // Next infrequent code is moved outside loops.
7770 bind(L_last_x);
7771 if (UseBMI2Instructions) {
7772 movl(rdx, Address(x, 0));
7773 } else {
7774 movl(x_xstart, Address(x, 0));
7775 }
7776 jmp(L_third_loop_prologue);
7778 bind(L_done);
7780 pop(zlen);
7781 pop(xlen);
7783 pop(tmp5);
7784 pop(tmp4);
7785 pop(tmp3);
7786 pop(tmp2);
7787 pop(tmp1);
7788 }
7790 //Helper functions for square_to_len()
7792 /**
7793 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7794 * Preserves x and z and modifies rest of the registers.
7795 */
7797 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7798 // Perform square and right shift by 1
7799 // Handle odd xlen case first, then for even xlen do the following
7800 // jlong carry = 0;
7801 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7802 // huge_128 product = x[j:j+1] * x[j:j+1];
7803 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7804 // z[i+2:i+3] = (jlong)(product >>> 1);
7805 // carry = (jlong)product;
7806 // }
7808 xorq(tmp5, tmp5); // carry
7809 xorq(rdxReg, rdxReg);
7810 xorl(tmp1, tmp1); // index for x
7811 xorl(tmp4, tmp4); // index for z
7813 Label L_first_loop, L_first_loop_exit;
7815 testl(xlen, 1);
7816 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7818 // Square and right shift by 1 the odd element using 32 bit multiply
7819 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7820 imulq(raxReg, raxReg);
7821 shrq(raxReg, 1);
7822 adcq(tmp5, 0);
7823 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7824 incrementl(tmp1);
7825 addl(tmp4, 2);
7827 // Square and right shift by 1 the rest using 64 bit multiply
7828 bind(L_first_loop);
7829 cmpptr(tmp1, xlen);
7830 jccb(Assembler::equal, L_first_loop_exit);
7832 // Square
7833 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7834 rorq(raxReg, 32); // convert big-endian to little-endian
7835 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7837 // Right shift by 1 and save carry
7838 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7839 rcrq(rdxReg, 1);
7840 rcrq(raxReg, 1);
7841 adcq(tmp5, 0);
7843 // Store result in z
7844 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7845 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7847 // Update indices for x and z
7848 addl(tmp1, 2);
7849 addl(tmp4, 4);
7850 jmp(L_first_loop);
7852 bind(L_first_loop_exit);
7853 }
7856 /**
7857 * Perform the following multiply add operation using BMI2 instructions
7858 * carry:sum = sum + op1*op2 + carry
7859 * op2 should be in rdx
7860 * op2 is preserved, all other registers are modified
7861 */
7862 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7863 // assert op2 is rdx
7864 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7865 addq(sum, carry);
7866 adcq(tmp2, 0);
7867 addq(sum, op1);
7868 adcq(tmp2, 0);
7869 movq(carry, tmp2);
7870 }
7872 /**
7873 * Perform the following multiply add operation:
7874 * carry:sum = sum + op1*op2 + carry
7875 * Preserves op1, op2 and modifies rest of registers
7876 */
7877 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7878 // rdx:rax = op1 * op2
7879 movq(raxReg, op2);
7880 mulq(op1);
7882 // rdx:rax = sum + carry + rdx:rax
7883 addq(sum, carry);
7884 adcq(rdxReg, 0);
7885 addq(sum, raxReg);
7886 adcq(rdxReg, 0);
7888 // carry:sum = rdx:sum
7889 movq(carry, rdxReg);
7890 }
7892 /**
7893 * Add 64 bit long carry into z[] with carry propogation.
7894 * Preserves z and carry register values and modifies rest of registers.
7895 *
7896 */
7897 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7898 Label L_fourth_loop, L_fourth_loop_exit;
7900 movl(tmp1, 1);
7901 subl(zlen, 2);
7902 addq(Address(z, zlen, Address::times_4, 0), carry);
7904 bind(L_fourth_loop);
7905 jccb(Assembler::carryClear, L_fourth_loop_exit);
7906 subl(zlen, 2);
7907 jccb(Assembler::negative, L_fourth_loop_exit);
7908 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7909 jmp(L_fourth_loop);
7910 bind(L_fourth_loop_exit);
7911 }
7913 /**
7914 * Shift z[] left by 1 bit.
7915 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7916 *
7917 */
7918 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7920 Label L_fifth_loop, L_fifth_loop_exit;
7922 // Fifth loop
7923 // Perform primitiveLeftShift(z, zlen, 1)
7925 const Register prev_carry = tmp1;
7926 const Register new_carry = tmp4;
7927 const Register value = tmp2;
7928 const Register zidx = tmp3;
7930 // int zidx, carry;
7931 // long value;
7932 // carry = 0;
7933 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7934 // (carry:value) = (z[i] << 1) | carry ;
7935 // z[i] = value;
7936 // }
7938 movl(zidx, zlen);
7939 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7941 bind(L_fifth_loop);
7942 decl(zidx); // Use decl to preserve carry flag
7943 decl(zidx);
7944 jccb(Assembler::negative, L_fifth_loop_exit);
7946 if (UseBMI2Instructions) {
7947 movq(value, Address(z, zidx, Address::times_4, 0));
7948 rclq(value, 1);
7949 rorxq(value, value, 32);
7950 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7951 }
7952 else {
7953 // clear new_carry
7954 xorl(new_carry, new_carry);
7956 // Shift z[i] by 1, or in previous carry and save new carry
7957 movq(value, Address(z, zidx, Address::times_4, 0));
7958 shlq(value, 1);
7959 adcl(new_carry, 0);
7961 orq(value, prev_carry);
7962 rorq(value, 0x20);
7963 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7965 // Set previous carry = new carry
7966 movl(prev_carry, new_carry);
7967 }
7968 jmp(L_fifth_loop);
7970 bind(L_fifth_loop_exit);
7971 }
7974 /**
7975 * Code for BigInteger::squareToLen() intrinsic
7976 *
7977 * rdi: x
7978 * rsi: len
7979 * r8: z
7980 * rcx: zlen
7981 * r12: tmp1
7982 * r13: tmp2
7983 * r14: tmp3
7984 * r15: tmp4
7985 * rbx: tmp5
7986 *
7987 */
7988 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7990 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
7991 push(tmp1);
7992 push(tmp2);
7993 push(tmp3);
7994 push(tmp4);
7995 push(tmp5);
7997 // First loop
7998 // Store the squares, right shifted one bit (i.e., divided by 2).
7999 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8001 // Add in off-diagonal sums.
8002 //
8003 // Second, third (nested) and fourth loops.
8004 // zlen +=2;
8005 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8006 // carry = 0;
8007 // long op2 = x[xidx:xidx+1];
8008 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8009 // k -= 2;
8010 // long op1 = x[j:j+1];
8011 // long sum = z[k:k+1];
8012 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8013 // z[k:k+1] = sum;
8014 // }
8015 // add_one_64(z, k, carry, tmp_regs);
8016 // }
8018 const Register carry = tmp5;
8019 const Register sum = tmp3;
8020 const Register op1 = tmp4;
8021 Register op2 = tmp2;
8023 push(zlen);
8024 push(len);
8025 addl(zlen,2);
8026 bind(L_second_loop);
8027 xorq(carry, carry);
8028 subl(zlen, 4);
8029 subl(len, 2);
8030 push(zlen);
8031 push(len);
8032 cmpl(len, 0);
8033 jccb(Assembler::lessEqual, L_second_loop_exit);
8035 // Multiply an array by one 64 bit long.
8036 if (UseBMI2Instructions) {
8037 op2 = rdxReg;
8038 movq(op2, Address(x, len, Address::times_4, 0));
8039 rorxq(op2, op2, 32);
8040 }
8041 else {
8042 movq(op2, Address(x, len, Address::times_4, 0));
8043 rorq(op2, 32);
8044 }
8046 bind(L_third_loop);
8047 decrementl(len);
8048 jccb(Assembler::negative, L_third_loop_exit);
8049 decrementl(len);
8050 jccb(Assembler::negative, L_last_x);
8052 movq(op1, Address(x, len, Address::times_4, 0));
8053 rorq(op1, 32);
8055 bind(L_multiply);
8056 subl(zlen, 2);
8057 movq(sum, Address(z, zlen, Address::times_4, 0));
8059 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8060 if (UseBMI2Instructions) {
8061 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8062 }
8063 else {
8064 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8065 }
8067 movq(Address(z, zlen, Address::times_4, 0), sum);
8069 jmp(L_third_loop);
8070 bind(L_third_loop_exit);
8072 // Fourth loop
8073 // Add 64 bit long carry into z with carry propogation.
8074 // Uses offsetted zlen.
8075 add_one_64(z, zlen, carry, tmp1);
8077 pop(len);
8078 pop(zlen);
8079 jmp(L_second_loop);
8081 // Next infrequent code is moved outside loops.
8082 bind(L_last_x);
8083 movl(op1, Address(x, 0));
8084 jmp(L_multiply);
8086 bind(L_second_loop_exit);
8087 pop(len);
8088 pop(zlen);
8089 pop(len);
8090 pop(zlen);
8092 // Fifth loop
8093 // Shift z left 1 bit.
8094 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8096 // z[zlen-1] |= x[len-1] & 1;
8097 movl(tmp3, Address(x, len, Address::times_4, -4));
8098 andl(tmp3, 1);
8099 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8101 pop(tmp5);
8102 pop(tmp4);
8103 pop(tmp3);
8104 pop(tmp2);
8105 pop(tmp1);
8106 }
8108 /**
8109 * Helper function for mul_add()
8110 * Multiply the in[] by int k and add to out[] starting at offset offs using
8111 * 128 bit by 32 bit multiply and return the carry in tmp5.
8112 * Only quad int aligned length of in[] is operated on in this function.
8113 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8114 * This function preserves out, in and k registers.
8115 * len and offset point to the appropriate index in "in" & "out" correspondingly
8116 * tmp5 has the carry.
8117 * other registers are temporary and are modified.
8118 *
8119 */
8120 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8121 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8122 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8124 Label L_first_loop, L_first_loop_exit;
8126 movl(tmp1, len);
8127 shrl(tmp1, 2);
8129 bind(L_first_loop);
8130 subl(tmp1, 1);
8131 jccb(Assembler::negative, L_first_loop_exit);
8133 subl(len, 4);
8134 subl(offset, 4);
8136 Register op2 = tmp2;
8137 const Register sum = tmp3;
8138 const Register op1 = tmp4;
8139 const Register carry = tmp5;
8141 if (UseBMI2Instructions) {
8142 op2 = rdxReg;
8143 }
8145 movq(op1, Address(in, len, Address::times_4, 8));
8146 rorq(op1, 32);
8147 movq(sum, Address(out, offset, Address::times_4, 8));
8148 rorq(sum, 32);
8149 if (UseBMI2Instructions) {
8150 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8151 }
8152 else {
8153 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8154 }
8155 // Store back in big endian from little endian
8156 rorq(sum, 0x20);
8157 movq(Address(out, offset, Address::times_4, 8), sum);
8159 movq(op1, Address(in, len, Address::times_4, 0));
8160 rorq(op1, 32);
8161 movq(sum, Address(out, offset, Address::times_4, 0));
8162 rorq(sum, 32);
8163 if (UseBMI2Instructions) {
8164 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8165 }
8166 else {
8167 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8168 }
8169 // Store back in big endian from little endian
8170 rorq(sum, 0x20);
8171 movq(Address(out, offset, Address::times_4, 0), sum);
8173 jmp(L_first_loop);
8174 bind(L_first_loop_exit);
8175 }
8177 /**
8178 * Code for BigInteger::mulAdd() intrinsic
8179 *
8180 * rdi: out
8181 * rsi: in
8182 * r11: offs (out.length - offset)
8183 * rcx: len
8184 * r8: k
8185 * r12: tmp1
8186 * r13: tmp2
8187 * r14: tmp3
8188 * r15: tmp4
8189 * rbx: tmp5
8190 * Multiply the in[] by word k and add to out[], return the carry in rax
8191 */
8192 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8193 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8194 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8196 Label L_carry, L_last_in, L_done;
8198 // carry = 0;
8199 // for (int j=len-1; j >= 0; j--) {
8200 // long product = (in[j] & LONG_MASK) * kLong +
8201 // (out[offs] & LONG_MASK) + carry;
8202 // out[offs--] = (int)product;
8203 // carry = product >>> 32;
8204 // }
8205 //
8206 push(tmp1);
8207 push(tmp2);
8208 push(tmp3);
8209 push(tmp4);
8210 push(tmp5);
8212 Register op2 = tmp2;
8213 const Register sum = tmp3;
8214 const Register op1 = tmp4;
8215 const Register carry = tmp5;
8217 if (UseBMI2Instructions) {
8218 op2 = rdxReg;
8219 movl(op2, k);
8220 }
8221 else {
8222 movl(op2, k);
8223 }
8225 xorq(carry, carry);
8227 //First loop
8229 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8230 //The carry is in tmp5
8231 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8233 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8234 decrementl(len);
8235 jccb(Assembler::negative, L_carry);
8236 decrementl(len);
8237 jccb(Assembler::negative, L_last_in);
8239 movq(op1, Address(in, len, Address::times_4, 0));
8240 rorq(op1, 32);
8242 subl(offs, 2);
8243 movq(sum, Address(out, offs, Address::times_4, 0));
8244 rorq(sum, 32);
8246 if (UseBMI2Instructions) {
8247 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8248 }
8249 else {
8250 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8251 }
8253 // Store back in big endian from little endian
8254 rorq(sum, 0x20);
8255 movq(Address(out, offs, Address::times_4, 0), sum);
8257 testl(len, len);
8258 jccb(Assembler::zero, L_carry);
8260 //Multiply the last in[] entry, if any
8261 bind(L_last_in);
8262 movl(op1, Address(in, 0));
8263 movl(sum, Address(out, offs, Address::times_4, -4));
8265 movl(raxReg, k);
8266 mull(op1); //tmp4 * eax -> edx:eax
8267 addl(sum, carry);
8268 adcl(rdxReg, 0);
8269 addl(sum, raxReg);
8270 adcl(rdxReg, 0);
8271 movl(carry, rdxReg);
8273 movl(Address(out, offs, Address::times_4, -4), sum);
8275 bind(L_carry);
8276 //return tmp5/carry as carry in rax
8277 movl(rax, carry);
8279 bind(L_done);
8280 pop(tmp5);
8281 pop(tmp4);
8282 pop(tmp3);
8283 pop(tmp2);
8284 pop(tmp1);
8285 }
8286 #endif
8288 /**
8289 * Emits code to update CRC-32 with a byte value according to constants in table
8290 *
8291 * @param [in,out]crc Register containing the crc.
8292 * @param [in]val Register containing the byte to fold into the CRC.
8293 * @param [in]table Register containing the table of crc constants.
8294 *
8295 * uint32_t crc;
8296 * val = crc_table[(val ^ crc) & 0xFF];
8297 * crc = val ^ (crc >> 8);
8298 *
8299 */
8300 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8301 xorl(val, crc);
8302 andl(val, 0xFF);
8303 shrl(crc, 8); // unsigned shift
8304 xorl(crc, Address(table, val, Address::times_4, 0));
8305 }
8307 /**
8308 * Fold 128-bit data chunk
8309 */
8310 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8311 if (UseAVX > 0) {
8312 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8313 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8314 vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
8315 pxor(xcrc, xtmp);
8316 } else {
8317 movdqa(xtmp, xcrc);
8318 pclmulhdq(xtmp, xK); // [123:64]
8319 pclmulldq(xcrc, xK); // [63:0]
8320 pxor(xcrc, xtmp);
8321 movdqu(xtmp, Address(buf, offset));
8322 pxor(xcrc, xtmp);
8323 }
8324 }
8326 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8327 if (UseAVX > 0) {
8328 vpclmulhdq(xtmp, xK, xcrc);
8329 vpclmulldq(xcrc, xK, xcrc);
8330 pxor(xcrc, xbuf);
8331 pxor(xcrc, xtmp);
8332 } else {
8333 movdqa(xtmp, xcrc);
8334 pclmulhdq(xtmp, xK);
8335 pclmulldq(xcrc, xK);
8336 pxor(xcrc, xbuf);
8337 pxor(xcrc, xtmp);
8338 }
8339 }
8341 /**
8342 * 8-bit folds to compute 32-bit CRC
8343 *
8344 * uint64_t xcrc;
8345 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8346 */
8347 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8348 movdl(tmp, xcrc);
8349 andl(tmp, 0xFF);
8350 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8351 psrldq(xcrc, 1); // unsigned shift one byte
8352 pxor(xcrc, xtmp);
8353 }
8355 /**
8356 * uint32_t crc;
8357 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8358 */
8359 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8360 movl(tmp, crc);
8361 andl(tmp, 0xFF);
8362 shrl(crc, 8);
8363 xorl(crc, Address(table, tmp, Address::times_4, 0));
8364 }
8366 /**
8367 * @param crc register containing existing CRC (32-bit)
8368 * @param buf register pointing to input byte buffer (byte*)
8369 * @param len register containing number of bytes
8370 * @param table register that will contain address of CRC table
8371 * @param tmp scratch register
8372 */
8373 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8374 assert_different_registers(crc, buf, len, table, tmp, rax);
8376 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8377 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8379 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8380 notl(crc); // ~crc
8381 cmpl(len, 16);
8382 jcc(Assembler::less, L_tail);
8384 // Align buffer to 16 bytes
8385 movl(tmp, buf);
8386 andl(tmp, 0xF);
8387 jccb(Assembler::zero, L_aligned);
8388 subl(tmp, 16);
8389 addl(len, tmp);
8391 align(4);
8392 BIND(L_align_loop);
8393 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8394 update_byte_crc32(crc, rax, table);
8395 increment(buf);
8396 incrementl(tmp);
8397 jccb(Assembler::less, L_align_loop);
8399 BIND(L_aligned);
8400 movl(tmp, len); // save
8401 shrl(len, 4);
8402 jcc(Assembler::zero, L_tail_restore);
8404 // Fold crc into first bytes of vector
8405 movdqa(xmm1, Address(buf, 0));
8406 movdl(rax, xmm1);
8407 xorl(crc, rax);
8408 pinsrd(xmm1, crc, 0);
8409 addptr(buf, 16);
8410 subl(len, 4); // len > 0
8411 jcc(Assembler::less, L_fold_tail);
8413 movdqa(xmm2, Address(buf, 0));
8414 movdqa(xmm3, Address(buf, 16));
8415 movdqa(xmm4, Address(buf, 32));
8416 addptr(buf, 48);
8417 subl(len, 3);
8418 jcc(Assembler::lessEqual, L_fold_512b);
8420 // Fold total 512 bits of polynomial on each iteration,
8421 // 128 bits per each of 4 parallel streams.
8422 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8424 align(32);
8425 BIND(L_fold_512b_loop);
8426 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8427 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8428 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8429 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8430 addptr(buf, 64);
8431 subl(len, 4);
8432 jcc(Assembler::greater, L_fold_512b_loop);
8434 // Fold 512 bits to 128 bits.
8435 BIND(L_fold_512b);
8436 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8437 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8438 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8439 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8441 // Fold the rest of 128 bits data chunks
8442 BIND(L_fold_tail);
8443 addl(len, 3);
8444 jccb(Assembler::lessEqual, L_fold_128b);
8445 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8447 BIND(L_fold_tail_loop);
8448 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8449 addptr(buf, 16);
8450 decrementl(len);
8451 jccb(Assembler::greater, L_fold_tail_loop);
8453 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8454 BIND(L_fold_128b);
8455 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8456 if (UseAVX > 0) {
8457 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8458 vpand(xmm3, xmm0, xmm2, false /* vector256 */);
8459 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8460 } else {
8461 movdqa(xmm2, xmm0);
8462 pclmulqdq(xmm2, xmm1, 0x1);
8463 movdqa(xmm3, xmm0);
8464 pand(xmm3, xmm2);
8465 pclmulqdq(xmm0, xmm3, 0x1);
8466 }
8467 psrldq(xmm1, 8);
8468 psrldq(xmm2, 4);
8469 pxor(xmm0, xmm1);
8470 pxor(xmm0, xmm2);
8472 // 8 8-bit folds to compute 32-bit CRC.
8473 for (int j = 0; j < 4; j++) {
8474 fold_8bit_crc32(xmm0, table, xmm1, rax);
8475 }
8476 movdl(crc, xmm0); // mov 32 bits to general register
8477 for (int j = 0; j < 4; j++) {
8478 fold_8bit_crc32(crc, table, rax);
8479 }
8481 BIND(L_tail_restore);
8482 movl(len, tmp); // restore
8483 BIND(L_tail);
8484 andl(len, 0xf);
8485 jccb(Assembler::zero, L_exit);
8487 // Fold the rest of bytes
8488 align(4);
8489 BIND(L_tail_loop);
8490 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8491 update_byte_crc32(crc, rax, table);
8492 increment(buf);
8493 decrementl(len);
8494 jccb(Assembler::greater, L_tail_loop);
8496 BIND(L_exit);
8497 notl(crc); // ~c
8498 }
8500 #undef BIND
8501 #undef BLOCK_COMMENT
8504 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8505 switch (cond) {
8506 // Note some conditions are synonyms for others
8507 case Assembler::zero: return Assembler::notZero;
8508 case Assembler::notZero: return Assembler::zero;
8509 case Assembler::less: return Assembler::greaterEqual;
8510 case Assembler::lessEqual: return Assembler::greater;
8511 case Assembler::greater: return Assembler::lessEqual;
8512 case Assembler::greaterEqual: return Assembler::less;
8513 case Assembler::below: return Assembler::aboveEqual;
8514 case Assembler::belowEqual: return Assembler::above;
8515 case Assembler::above: return Assembler::belowEqual;
8516 case Assembler::aboveEqual: return Assembler::below;
8517 case Assembler::overflow: return Assembler::noOverflow;
8518 case Assembler::noOverflow: return Assembler::overflow;
8519 case Assembler::negative: return Assembler::positive;
8520 case Assembler::positive: return Assembler::negative;
8521 case Assembler::parity: return Assembler::noParity;
8522 case Assembler::noParity: return Assembler::parity;
8523 }
8524 ShouldNotReachHere(); return Assembler::overflow;
8525 }
8527 SkipIfEqual::SkipIfEqual(
8528 MacroAssembler* masm, const bool* flag_addr, bool value) {
8529 _masm = masm;
8530 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8531 _masm->jcc(Assembler::equal, _label);
8532 }
8534 SkipIfEqual::~SkipIfEqual() {
8535 _masm->bind(_label);
8536 }