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src/cpu/x86/vm/x86_64.ad@d6f45b55c972
src/cpu/x86/vm/x86_64.ad
Fri, 27 Aug 2010 17:33:49 -0700
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- Fri, 27 Aug 2010 17:33:49 -0700
- changeset 2118
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4809552: Optimize Arrays.fill(...)
Reviewed-by: kvn
1 //
2 // Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // AMD64 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
89 #ifdef _WIN64
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
97 #else
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
105 #endif
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
132 // Floating Point Registers
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
135 // Word a in each register holds a Float, words ab hold a Double. We
136 // currently do not use the SIMD capabilities, so registers cd are
137 // unused at the moment.
138 // XMM8-XMM15 must be encoded with REX.
139 // Linux ABI: No register preserved across function calls
140 // XMM0-XMM7 might hold parameters
141 // Windows ABI: XMM6-XMM15 preserved across function calls
142 // XMM0-XMM3 might hold parameters
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
162 #ifdef _WIN64
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
194 #else
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
226 #endif // _WIN64
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
230 // Specify priority of register selection within phases of register
231 // allocation. Highest priority is first. A useful heuristic is to
232 // give registers a low priority when they are required by machine
233 // instructions, like EAX and EDX on I486, and choose no-save registers
234 // before save-on-call, & save-on-call before save-on-entry. Registers
235 // which participate in fixed calling sequences should come last.
236 // Registers which are used as pairs must fall on an even boundary.
238 alloc_class chunk0(R10, R10_H,
239 R11, R11_H,
240 R8, R8_H,
241 R9, R9_H,
242 R12, R12_H,
243 RCX, RCX_H,
244 RBX, RBX_H,
245 RDI, RDI_H,
246 RDX, RDX_H,
247 RSI, RSI_H,
248 RAX, RAX_H,
249 RBP, RBP_H,
250 R13, R13_H,
251 R14, R14_H,
252 R15, R15_H,
253 RSP, RSP_H);
255 // XXX probably use 8-15 first on Linux
256 alloc_class chunk1(XMM0, XMM0_H,
257 XMM1, XMM1_H,
258 XMM2, XMM2_H,
259 XMM3, XMM3_H,
260 XMM4, XMM4_H,
261 XMM5, XMM5_H,
262 XMM6, XMM6_H,
263 XMM7, XMM7_H,
264 XMM8, XMM8_H,
265 XMM9, XMM9_H,
266 XMM10, XMM10_H,
267 XMM11, XMM11_H,
268 XMM12, XMM12_H,
269 XMM13, XMM13_H,
270 XMM14, XMM14_H,
271 XMM15, XMM15_H);
273 alloc_class chunk2(RFLAGS);
276 //----------Architecture Description Register Classes--------------------------
277 // Several register classes are automatically defined based upon information in
278 // this architecture description.
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // Class for all pointer registers (including RSP)
286 reg_class any_reg(RAX, RAX_H,
287 RDX, RDX_H,
288 RBP, RBP_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 RBX, RBX_H,
293 RSP, RSP_H,
294 R8, R8_H,
295 R9, R9_H,
296 R10, R10_H,
297 R11, R11_H,
298 R12, R12_H,
299 R13, R13_H,
300 R14, R14_H,
301 R15, R15_H);
303 // Class for all pointer registers except RSP
304 reg_class ptr_reg(RAX, RAX_H,
305 RDX, RDX_H,
306 RBP, RBP_H,
307 RDI, RDI_H,
308 RSI, RSI_H,
309 RCX, RCX_H,
310 RBX, RBX_H,
311 R8, R8_H,
312 R9, R9_H,
313 R10, R10_H,
314 R11, R11_H,
315 R13, R13_H,
316 R14, R14_H);
318 // Class for all pointer registers except RAX and RSP
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
320 RBP, RBP_H,
321 RDI, RDI_H,
322 RSI, RSI_H,
323 RCX, RCX_H,
324 RBX, RBX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R13, R13_H,
330 R14, R14_H);
332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
333 RAX, RAX_H,
334 RDI, RDI_H,
335 RSI, RSI_H,
336 RCX, RCX_H,
337 RBX, RBX_H,
338 R8, R8_H,
339 R9, R9_H,
340 R10, R10_H,
341 R11, R11_H,
342 R13, R13_H,
343 R14, R14_H);
345 // Class for all pointer registers except RAX, RBX and RSP
346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
347 RBP, RBP_H,
348 RDI, RDI_H,
349 RSI, RSI_H,
350 RCX, RCX_H,
351 R8, R8_H,
352 R9, R9_H,
353 R10, R10_H,
354 R11, R11_H,
355 R13, R13_H,
356 R14, R14_H);
358 // Singleton class for RAX pointer register
359 reg_class ptr_rax_reg(RAX, RAX_H);
361 // Singleton class for RBX pointer register
362 reg_class ptr_rbx_reg(RBX, RBX_H);
364 // Singleton class for RSI pointer register
365 reg_class ptr_rsi_reg(RSI, RSI_H);
367 // Singleton class for RDI pointer register
368 reg_class ptr_rdi_reg(RDI, RDI_H);
370 // Singleton class for RBP pointer register
371 reg_class ptr_rbp_reg(RBP, RBP_H);
373 // Singleton class for stack pointer
374 reg_class ptr_rsp_reg(RSP, RSP_H);
376 // Singleton class for TLS pointer
377 reg_class ptr_r15_reg(R15, R15_H);
379 // Class for all long registers (except RSP)
380 reg_class long_reg(RAX, RAX_H,
381 RDX, RDX_H,
382 RBP, RBP_H,
383 RDI, RDI_H,
384 RSI, RSI_H,
385 RCX, RCX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
394 // Class for all long registers except RAX, RDX (and RSP)
395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
396 RDI, RDI_H,
397 RSI, RSI_H,
398 RCX, RCX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
407 // Class for all long registers except RCX (and RSP)
408 reg_class long_no_rcx_reg(RBP, RBP_H,
409 RDI, RDI_H,
410 RSI, RSI_H,
411 RAX, RAX_H,
412 RDX, RDX_H,
413 RBX, RBX_H,
414 R8, R8_H,
415 R9, R9_H,
416 R10, R10_H,
417 R11, R11_H,
418 R13, R13_H,
419 R14, R14_H);
421 // Class for all long registers except RAX (and RSP)
422 reg_class long_no_rax_reg(RBP, RBP_H,
423 RDX, RDX_H,
424 RDI, RDI_H,
425 RSI, RSI_H,
426 RCX, RCX_H,
427 RBX, RBX_H,
428 R8, R8_H,
429 R9, R9_H,
430 R10, R10_H,
431 R11, R11_H,
432 R13, R13_H,
433 R14, R14_H);
435 // Singleton class for RAX long register
436 reg_class long_rax_reg(RAX, RAX_H);
438 // Singleton class for RCX long register
439 reg_class long_rcx_reg(RCX, RCX_H);
441 // Singleton class for RDX long register
442 reg_class long_rdx_reg(RDX, RDX_H);
444 // Class for all int registers (except RSP)
445 reg_class int_reg(RAX,
446 RDX,
447 RBP,
448 RDI,
449 RSI,
450 RCX,
451 RBX,
452 R8,
453 R9,
454 R10,
455 R11,
456 R13,
457 R14);
459 // Class for all int registers except RCX (and RSP)
460 reg_class int_no_rcx_reg(RAX,
461 RDX,
462 RBP,
463 RDI,
464 RSI,
465 RBX,
466 R8,
467 R9,
468 R10,
469 R11,
470 R13,
471 R14);
473 // Class for all int registers except RAX, RDX (and RSP)
474 reg_class int_no_rax_rdx_reg(RBP,
475 RDI,
476 RSI,
477 RCX,
478 RBX,
479 R8,
480 R9,
481 R10,
482 R11,
483 R13,
484 R14);
486 // Singleton class for RAX int register
487 reg_class int_rax_reg(RAX);
489 // Singleton class for RBX int register
490 reg_class int_rbx_reg(RBX);
492 // Singleton class for RCX int register
493 reg_class int_rcx_reg(RCX);
495 // Singleton class for RCX int register
496 reg_class int_rdx_reg(RDX);
498 // Singleton class for RCX int register
499 reg_class int_rdi_reg(RDI);
501 // Singleton class for instruction pointer
502 // reg_class ip_reg(RIP);
504 // Singleton class for condition codes
505 reg_class int_flags(RFLAGS);
507 // Class for all float registers
508 reg_class float_reg(XMM0,
509 XMM1,
510 XMM2,
511 XMM3,
512 XMM4,
513 XMM5,
514 XMM6,
515 XMM7,
516 XMM8,
517 XMM9,
518 XMM10,
519 XMM11,
520 XMM12,
521 XMM13,
522 XMM14,
523 XMM15);
525 // Class for all double registers
526 reg_class double_reg(XMM0, XMM0_H,
527 XMM1, XMM1_H,
528 XMM2, XMM2_H,
529 XMM3, XMM3_H,
530 XMM4, XMM4_H,
531 XMM5, XMM5_H,
532 XMM6, XMM6_H,
533 XMM7, XMM7_H,
534 XMM8, XMM8_H,
535 XMM9, XMM9_H,
536 XMM10, XMM10_H,
537 XMM11, XMM11_H,
538 XMM12, XMM12_H,
539 XMM13, XMM13_H,
540 XMM14, XMM14_H,
541 XMM15, XMM15_H);
542 %}
545 //----------SOURCE BLOCK-------------------------------------------------------
546 // This is a block of C++ code which provides values, functions, and
547 // definitions necessary in the rest of the architecture description
548 source %{
549 #define RELOC_IMM64 Assembler::imm_operand
550 #define RELOC_DISP32 Assembler::disp32_operand
552 #define __ _masm.
554 static int preserve_SP_size() {
555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
556 }
558 // !!!!! Special hack to get all types of calls to specify the byte offset
559 // from the start of the call to the point where the return address
560 // will point.
561 int MachCallStaticJavaNode::ret_addr_offset()
562 {
563 int offset = 5; // 5 bytes from start of call to where return address points
564 if (_method_handle_invoke)
565 offset += preserve_SP_size();
566 return offset;
567 }
569 int MachCallDynamicJavaNode::ret_addr_offset()
570 {
571 return 15; // 15 bytes from start of call to where return address points
572 }
574 // In os_cpu .ad file
575 // int MachCallRuntimeNode::ret_addr_offset()
577 // Indicate if the safepoint node needs the polling page as an input.
578 // Since amd64 does not have absolute addressing but RIP-relative
579 // addressing and the polling page is within 2G, it doesn't.
580 bool SafePointNode::needs_polling_address_input()
581 {
582 return false;
583 }
585 //
586 // Compute padding required for nodes which need alignment
587 //
589 // The address of the call instruction needs to be 4-byte aligned to
590 // ensure that it does not span a cache line so that it can be patched.
591 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
592 {
593 current_offset += 1; // skip call opcode byte
594 return round_to(current_offset, alignment_required()) - current_offset;
595 }
597 // The address of the call instruction needs to be 4-byte aligned to
598 // ensure that it does not span a cache line so that it can be patched.
599 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
600 {
601 current_offset += preserve_SP_size(); // skip mov rbp, rsp
602 current_offset += 1; // skip call opcode byte
603 return round_to(current_offset, alignment_required()) - current_offset;
604 }
606 // The address of the call instruction needs to be 4-byte aligned to
607 // ensure that it does not span a cache line so that it can be patched.
608 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
609 {
610 current_offset += 11; // skip movq instruction + call opcode byte
611 return round_to(current_offset, alignment_required()) - current_offset;
612 }
614 #ifndef PRODUCT
615 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
616 {
617 st->print("INT3");
618 }
619 #endif
621 // EMIT_RM()
622 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3)
623 {
624 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
625 *(cbuf.code_end()) = c;
626 cbuf.set_code_end(cbuf.code_end() + 1);
627 }
629 // EMIT_CC()
630 void emit_cc(CodeBuffer &cbuf, int f1, int f2)
631 {
632 unsigned char c = (unsigned char) (f1 | f2);
633 *(cbuf.code_end()) = c;
634 cbuf.set_code_end(cbuf.code_end() + 1);
635 }
637 // EMIT_OPCODE()
638 void emit_opcode(CodeBuffer &cbuf, int code)
639 {
640 *(cbuf.code_end()) = (unsigned char) code;
641 cbuf.set_code_end(cbuf.code_end() + 1);
642 }
644 // EMIT_OPCODE() w/ relocation information
645 void emit_opcode(CodeBuffer &cbuf,
646 int code, relocInfo::relocType reloc, int offset, int format)
647 {
648 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format);
649 emit_opcode(cbuf, code);
650 }
652 // EMIT_D8()
653 void emit_d8(CodeBuffer &cbuf, int d8)
654 {
655 *(cbuf.code_end()) = (unsigned char) d8;
656 cbuf.set_code_end(cbuf.code_end() + 1);
657 }
659 // EMIT_D16()
660 void emit_d16(CodeBuffer &cbuf, int d16)
661 {
662 *((short *)(cbuf.code_end())) = d16;
663 cbuf.set_code_end(cbuf.code_end() + 2);
664 }
666 // EMIT_D32()
667 void emit_d32(CodeBuffer &cbuf, int d32)
668 {
669 *((int *)(cbuf.code_end())) = d32;
670 cbuf.set_code_end(cbuf.code_end() + 4);
671 }
673 // EMIT_D64()
674 void emit_d64(CodeBuffer &cbuf, int64_t d64)
675 {
676 *((int64_t*) (cbuf.code_end())) = d64;
677 cbuf.set_code_end(cbuf.code_end() + 8);
678 }
680 // emit 32 bit value and construct relocation entry from relocInfo::relocType
681 void emit_d32_reloc(CodeBuffer& cbuf,
682 int d32,
683 relocInfo::relocType reloc,
684 int format)
685 {
686 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
687 cbuf.relocate(cbuf.inst_mark(), reloc, format);
689 *((int*) (cbuf.code_end())) = d32;
690 cbuf.set_code_end(cbuf.code_end() + 4);
691 }
693 // emit 32 bit value and construct relocation entry from RelocationHolder
694 void emit_d32_reloc(CodeBuffer& cbuf,
695 int d32,
696 RelocationHolder const& rspec,
697 int format)
698 {
699 #ifdef ASSERT
700 if (rspec.reloc()->type() == relocInfo::oop_type &&
701 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
702 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
703 }
704 #endif
705 cbuf.relocate(cbuf.inst_mark(), rspec, format);
707 *((int* )(cbuf.code_end())) = d32;
708 cbuf.set_code_end(cbuf.code_end() + 4);
709 }
711 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
712 address next_ip = cbuf.code_end() + 4;
713 emit_d32_reloc(cbuf, (int) (addr - next_ip),
714 external_word_Relocation::spec(addr),
715 RELOC_DISP32);
716 }
719 // emit 64 bit value and construct relocation entry from relocInfo::relocType
720 void emit_d64_reloc(CodeBuffer& cbuf,
721 int64_t d64,
722 relocInfo::relocType reloc,
723 int format)
724 {
725 cbuf.relocate(cbuf.inst_mark(), reloc, format);
727 *((int64_t*) (cbuf.code_end())) = d64;
728 cbuf.set_code_end(cbuf.code_end() + 8);
729 }
731 // emit 64 bit value and construct relocation entry from RelocationHolder
732 void emit_d64_reloc(CodeBuffer& cbuf,
733 int64_t d64,
734 RelocationHolder const& rspec,
735 int format)
736 {
737 #ifdef ASSERT
738 if (rspec.reloc()->type() == relocInfo::oop_type &&
739 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
740 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
741 "cannot embed scavengable oops in code");
742 }
743 #endif
744 cbuf.relocate(cbuf.inst_mark(), rspec, format);
746 *((int64_t*) (cbuf.code_end())) = d64;
747 cbuf.set_code_end(cbuf.code_end() + 8);
748 }
750 // Access stack slot for load or store
751 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
752 {
753 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
754 if (-0x80 <= disp && disp < 0x80) {
755 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
756 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
757 emit_d8(cbuf, disp); // Displacement // R/M byte
758 } else {
759 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
760 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
761 emit_d32(cbuf, disp); // Displacement // R/M byte
762 }
763 }
765 // rRegI ereg, memory mem) %{ // emit_reg_mem
766 void encode_RegMem(CodeBuffer &cbuf,
767 int reg,
768 int base, int index, int scale, int disp, bool disp_is_oop)
769 {
770 assert(!disp_is_oop, "cannot have disp");
771 int regenc = reg & 7;
772 int baseenc = base & 7;
773 int indexenc = index & 7;
775 // There is no index & no scale, use form without SIB byte
776 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
777 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
778 if (disp == 0 && base != RBP_enc && base != R13_enc) {
779 emit_rm(cbuf, 0x0, regenc, baseenc); // *
780 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
781 // If 8-bit displacement, mode 0x1
782 emit_rm(cbuf, 0x1, regenc, baseenc); // *
783 emit_d8(cbuf, disp);
784 } else {
785 // If 32-bit displacement
786 if (base == -1) { // Special flag for absolute address
787 emit_rm(cbuf, 0x0, regenc, 0x5); // *
788 if (disp_is_oop) {
789 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
790 } else {
791 emit_d32(cbuf, disp);
792 }
793 } else {
794 // Normal base + offset
795 emit_rm(cbuf, 0x2, regenc, baseenc); // *
796 if (disp_is_oop) {
797 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
798 } else {
799 emit_d32(cbuf, disp);
800 }
801 }
802 }
803 } else {
804 // Else, encode with the SIB byte
805 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
806 if (disp == 0 && base != RBP_enc && base != R13_enc) {
807 // If no displacement
808 emit_rm(cbuf, 0x0, regenc, 0x4); // *
809 emit_rm(cbuf, scale, indexenc, baseenc);
810 } else {
811 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
812 // If 8-bit displacement, mode 0x1
813 emit_rm(cbuf, 0x1, regenc, 0x4); // *
814 emit_rm(cbuf, scale, indexenc, baseenc);
815 emit_d8(cbuf, disp);
816 } else {
817 // If 32-bit displacement
818 if (base == 0x04 ) {
819 emit_rm(cbuf, 0x2, regenc, 0x4);
820 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
821 } else {
822 emit_rm(cbuf, 0x2, regenc, 0x4);
823 emit_rm(cbuf, scale, indexenc, baseenc); // *
824 }
825 if (disp_is_oop) {
826 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
827 } else {
828 emit_d32(cbuf, disp);
829 }
830 }
831 }
832 }
833 }
835 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
836 {
837 if (dstenc != srcenc) {
838 if (dstenc < 8) {
839 if (srcenc >= 8) {
840 emit_opcode(cbuf, Assembler::REX_B);
841 srcenc -= 8;
842 }
843 } else {
844 if (srcenc < 8) {
845 emit_opcode(cbuf, Assembler::REX_R);
846 } else {
847 emit_opcode(cbuf, Assembler::REX_RB);
848 srcenc -= 8;
849 }
850 dstenc -= 8;
851 }
853 emit_opcode(cbuf, 0x8B);
854 emit_rm(cbuf, 0x3, dstenc, srcenc);
855 }
856 }
858 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
859 if( dst_encoding == src_encoding ) {
860 // reg-reg copy, use an empty encoding
861 } else {
862 MacroAssembler _masm(&cbuf);
864 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
865 }
866 }
869 //=============================================================================
870 #ifndef PRODUCT
871 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
872 {
873 Compile* C = ra_->C;
875 int framesize = C->frame_slots() << LogBytesPerInt;
876 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
877 // Remove wordSize for return adr already pushed
878 // and another for the RBP we are going to save
879 framesize -= 2*wordSize;
880 bool need_nop = true;
882 // Calls to C2R adapters often do not accept exceptional returns.
883 // We require that their callers must bang for them. But be
884 // careful, because some VM calls (such as call site linkage) can
885 // use several kilobytes of stack. But the stack safety zone should
886 // account for that. See bugs 4446381, 4468289, 4497237.
887 if (C->need_stack_bang(framesize)) {
888 st->print_cr("# stack bang"); st->print("\t");
889 need_nop = false;
890 }
891 st->print_cr("pushq rbp"); st->print("\t");
893 if (VerifyStackAtCalls) {
894 // Majik cookie to verify stack depth
895 st->print_cr("pushq 0xffffffffbadb100d"
896 "\t# Majik cookie for stack depth check");
897 st->print("\t");
898 framesize -= wordSize; // Remove 2 for cookie
899 need_nop = false;
900 }
902 if (framesize) {
903 st->print("subq rsp, #%d\t# Create frame", framesize);
904 if (framesize < 0x80 && need_nop) {
905 st->print("\n\tnop\t# nop for patch_verified_entry");
906 }
907 }
908 }
909 #endif
911 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
912 {
913 Compile* C = ra_->C;
915 // WARNING: Initial instruction MUST be 5 bytes or longer so that
916 // NativeJump::patch_verified_entry will be able to patch out the entry
917 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
918 // depth is ok at 5 bytes, the frame allocation can be either 3 or
919 // 6 bytes. So if we don't do the fldcw or the push then we must
920 // use the 6 byte frame allocation even if we have no frame. :-(
921 // If method sets FPU control word do it now
923 int framesize = C->frame_slots() << LogBytesPerInt;
924 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
925 // Remove wordSize for return adr already pushed
926 // and another for the RBP we are going to save
927 framesize -= 2*wordSize;
928 bool need_nop = true;
930 // Calls to C2R adapters often do not accept exceptional returns.
931 // We require that their callers must bang for them. But be
932 // careful, because some VM calls (such as call site linkage) can
933 // use several kilobytes of stack. But the stack safety zone should
934 // account for that. See bugs 4446381, 4468289, 4497237.
935 if (C->need_stack_bang(framesize)) {
936 MacroAssembler masm(&cbuf);
937 masm.generate_stack_overflow_check(framesize);
938 need_nop = false;
939 }
941 // We always push rbp so that on return to interpreter rbp will be
942 // restored correctly and we can correct the stack.
943 emit_opcode(cbuf, 0x50 | RBP_enc);
945 if (VerifyStackAtCalls) {
946 // Majik cookie to verify stack depth
947 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
948 emit_d32(cbuf, 0xbadb100d);
949 framesize -= wordSize; // Remove 2 for cookie
950 need_nop = false;
951 }
953 if (framesize) {
954 emit_opcode(cbuf, Assembler::REX_W);
955 if (framesize < 0x80) {
956 emit_opcode(cbuf, 0x83); // sub SP,#framesize
957 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
958 emit_d8(cbuf, framesize);
959 if (need_nop) {
960 emit_opcode(cbuf, 0x90); // nop
961 }
962 } else {
963 emit_opcode(cbuf, 0x81); // sub SP,#framesize
964 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
965 emit_d32(cbuf, framesize);
966 }
967 }
969 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
971 #ifdef ASSERT
972 if (VerifyStackAtCalls) {
973 Label L;
974 MacroAssembler masm(&cbuf);
975 masm.push(rax);
976 masm.mov(rax, rsp);
977 masm.andptr(rax, StackAlignmentInBytes-1);
978 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
979 masm.pop(rax);
980 masm.jcc(Assembler::equal, L);
981 masm.stop("Stack is not properly aligned!");
982 masm.bind(L);
983 }
984 #endif
985 }
987 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
988 {
989 return MachNode::size(ra_); // too many variables; just compute it
990 // the hard way
991 }
993 int MachPrologNode::reloc() const
994 {
995 return 0; // a large enough number
996 }
998 //=============================================================================
999 #ifndef PRODUCT
1000 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1001 {
1002 Compile* C = ra_->C;
1003 int framesize = C->frame_slots() << LogBytesPerInt;
1004 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1005 // Remove word for return adr already pushed
1006 // and RBP
1007 framesize -= 2*wordSize;
1009 if (framesize) {
1010 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
1011 st->print("\t");
1012 }
1014 st->print_cr("popq\trbp");
1015 if (do_polling() && C->is_method_compilation()) {
1016 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
1017 "# Safepoint: poll for GC");
1018 st->print("\t");
1019 }
1020 }
1021 #endif
1023 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1024 {
1025 Compile* C = ra_->C;
1026 int framesize = C->frame_slots() << LogBytesPerInt;
1027 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1028 // Remove word for return adr already pushed
1029 // and RBP
1030 framesize -= 2*wordSize;
1032 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1034 if (framesize) {
1035 emit_opcode(cbuf, Assembler::REX_W);
1036 if (framesize < 0x80) {
1037 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1038 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1039 emit_d8(cbuf, framesize);
1040 } else {
1041 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1042 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1043 emit_d32(cbuf, framesize);
1044 }
1045 }
1047 // popq rbp
1048 emit_opcode(cbuf, 0x58 | RBP_enc);
1050 if (do_polling() && C->is_method_compilation()) {
1051 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
1052 // XXX reg_mem doesn't support RIP-relative addressing yet
1053 cbuf.set_inst_mark();
1054 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX
1055 emit_opcode(cbuf, 0x85); // testl
1056 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
1057 // cbuf.inst_mark() is beginning of instruction
1058 emit_d32_reloc(cbuf, os::get_polling_page());
1059 // relocInfo::poll_return_type,
1060 }
1061 }
1063 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1064 {
1065 Compile* C = ra_->C;
1066 int framesize = C->frame_slots() << LogBytesPerInt;
1067 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1068 // Remove word for return adr already pushed
1069 // and RBP
1070 framesize -= 2*wordSize;
1072 uint size = 0;
1074 if (do_polling() && C->is_method_compilation()) {
1075 size += 6;
1076 }
1078 // count popq rbp
1079 size++;
1081 if (framesize) {
1082 if (framesize < 0x80) {
1083 size += 4;
1084 } else if (framesize) {
1085 size += 7;
1086 }
1087 }
1089 return size;
1090 }
1092 int MachEpilogNode::reloc() const
1093 {
1094 return 2; // a large enough number
1095 }
1097 const Pipeline* MachEpilogNode::pipeline() const
1098 {
1099 return MachNode::pipeline_class();
1100 }
1102 int MachEpilogNode::safepoint_offset() const
1103 {
1104 return 0;
1105 }
1107 //=============================================================================
1109 enum RC {
1110 rc_bad,
1111 rc_int,
1112 rc_float,
1113 rc_stack
1114 };
1116 static enum RC rc_class(OptoReg::Name reg)
1117 {
1118 if( !OptoReg::is_valid(reg) ) return rc_bad;
1120 if (OptoReg::is_stack(reg)) return rc_stack;
1122 VMReg r = OptoReg::as_VMReg(reg);
1124 if (r->is_Register()) return rc_int;
1126 assert(r->is_XMMRegister(), "must be");
1127 return rc_float;
1128 }
1130 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1131 PhaseRegAlloc* ra_,
1132 bool do_size,
1133 outputStream* st) const
1134 {
1136 // Get registers to move
1137 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1138 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1139 OptoReg::Name dst_second = ra_->get_reg_second(this);
1140 OptoReg::Name dst_first = ra_->get_reg_first(this);
1142 enum RC src_second_rc = rc_class(src_second);
1143 enum RC src_first_rc = rc_class(src_first);
1144 enum RC dst_second_rc = rc_class(dst_second);
1145 enum RC dst_first_rc = rc_class(dst_first);
1147 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1148 "must move at least 1 register" );
1150 if (src_first == dst_first && src_second == dst_second) {
1151 // Self copy, no move
1152 return 0;
1153 } else if (src_first_rc == rc_stack) {
1154 // mem ->
1155 if (dst_first_rc == rc_stack) {
1156 // mem -> mem
1157 assert(src_second != dst_first, "overlap");
1158 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1159 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1160 // 64-bit
1161 int src_offset = ra_->reg2offset(src_first);
1162 int dst_offset = ra_->reg2offset(dst_first);
1163 if (cbuf) {
1164 emit_opcode(*cbuf, 0xFF);
1165 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
1167 emit_opcode(*cbuf, 0x8F);
1168 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
1170 #ifndef PRODUCT
1171 } else if (!do_size) {
1172 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1173 "popq [rsp + #%d]",
1174 src_offset,
1175 dst_offset);
1176 #endif
1177 }
1178 return
1179 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
1180 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
1181 } else {
1182 // 32-bit
1183 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1184 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1185 // No pushl/popl, so:
1186 int src_offset = ra_->reg2offset(src_first);
1187 int dst_offset = ra_->reg2offset(dst_first);
1188 if (cbuf) {
1189 emit_opcode(*cbuf, Assembler::REX_W);
1190 emit_opcode(*cbuf, 0x89);
1191 emit_opcode(*cbuf, 0x44);
1192 emit_opcode(*cbuf, 0x24);
1193 emit_opcode(*cbuf, 0xF8);
1195 emit_opcode(*cbuf, 0x8B);
1196 encode_RegMem(*cbuf,
1197 RAX_enc,
1198 RSP_enc, 0x4, 0, src_offset,
1199 false);
1201 emit_opcode(*cbuf, 0x89);
1202 encode_RegMem(*cbuf,
1203 RAX_enc,
1204 RSP_enc, 0x4, 0, dst_offset,
1205 false);
1207 emit_opcode(*cbuf, Assembler::REX_W);
1208 emit_opcode(*cbuf, 0x8B);
1209 emit_opcode(*cbuf, 0x44);
1210 emit_opcode(*cbuf, 0x24);
1211 emit_opcode(*cbuf, 0xF8);
1213 #ifndef PRODUCT
1214 } else if (!do_size) {
1215 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1216 "movl rax, [rsp + #%d]\n\t"
1217 "movl [rsp + #%d], rax\n\t"
1218 "movq rax, [rsp - #8]",
1219 src_offset,
1220 dst_offset);
1221 #endif
1222 }
1223 return
1224 5 + // movq
1225 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
1226 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
1227 5; // movq
1228 }
1229 } else if (dst_first_rc == rc_int) {
1230 // mem -> gpr
1231 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1232 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1233 // 64-bit
1234 int offset = ra_->reg2offset(src_first);
1235 if (cbuf) {
1236 if (Matcher::_regEncode[dst_first] < 8) {
1237 emit_opcode(*cbuf, Assembler::REX_W);
1238 } else {
1239 emit_opcode(*cbuf, Assembler::REX_WR);
1240 }
1241 emit_opcode(*cbuf, 0x8B);
1242 encode_RegMem(*cbuf,
1243 Matcher::_regEncode[dst_first],
1244 RSP_enc, 0x4, 0, offset,
1245 false);
1246 #ifndef PRODUCT
1247 } else if (!do_size) {
1248 st->print("movq %s, [rsp + #%d]\t# spill",
1249 Matcher::regName[dst_first],
1250 offset);
1251 #endif
1252 }
1253 return
1254 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1255 } else {
1256 // 32-bit
1257 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1258 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1259 int offset = ra_->reg2offset(src_first);
1260 if (cbuf) {
1261 if (Matcher::_regEncode[dst_first] >= 8) {
1262 emit_opcode(*cbuf, Assembler::REX_R);
1263 }
1264 emit_opcode(*cbuf, 0x8B);
1265 encode_RegMem(*cbuf,
1266 Matcher::_regEncode[dst_first],
1267 RSP_enc, 0x4, 0, offset,
1268 false);
1269 #ifndef PRODUCT
1270 } else if (!do_size) {
1271 st->print("movl %s, [rsp + #%d]\t# spill",
1272 Matcher::regName[dst_first],
1273 offset);
1274 #endif
1275 }
1276 return
1277 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1278 ((Matcher::_regEncode[dst_first] < 8)
1279 ? 3
1280 : 4); // REX
1281 }
1282 } else if (dst_first_rc == rc_float) {
1283 // mem-> xmm
1284 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1285 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1286 // 64-bit
1287 int offset = ra_->reg2offset(src_first);
1288 if (cbuf) {
1289 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1290 if (Matcher::_regEncode[dst_first] >= 8) {
1291 emit_opcode(*cbuf, Assembler::REX_R);
1292 }
1293 emit_opcode(*cbuf, 0x0F);
1294 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1295 encode_RegMem(*cbuf,
1296 Matcher::_regEncode[dst_first],
1297 RSP_enc, 0x4, 0, offset,
1298 false);
1299 #ifndef PRODUCT
1300 } else if (!do_size) {
1301 st->print("%s %s, [rsp + #%d]\t# spill",
1302 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1303 Matcher::regName[dst_first],
1304 offset);
1305 #endif
1306 }
1307 return
1308 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1309 ((Matcher::_regEncode[dst_first] < 8)
1310 ? 5
1311 : 6); // REX
1312 } else {
1313 // 32-bit
1314 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1315 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1316 int offset = ra_->reg2offset(src_first);
1317 if (cbuf) {
1318 emit_opcode(*cbuf, 0xF3);
1319 if (Matcher::_regEncode[dst_first] >= 8) {
1320 emit_opcode(*cbuf, Assembler::REX_R);
1321 }
1322 emit_opcode(*cbuf, 0x0F);
1323 emit_opcode(*cbuf, 0x10);
1324 encode_RegMem(*cbuf,
1325 Matcher::_regEncode[dst_first],
1326 RSP_enc, 0x4, 0, offset,
1327 false);
1328 #ifndef PRODUCT
1329 } else if (!do_size) {
1330 st->print("movss %s, [rsp + #%d]\t# spill",
1331 Matcher::regName[dst_first],
1332 offset);
1333 #endif
1334 }
1335 return
1336 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1337 ((Matcher::_regEncode[dst_first] < 8)
1338 ? 5
1339 : 6); // REX
1340 }
1341 }
1342 } else if (src_first_rc == rc_int) {
1343 // gpr ->
1344 if (dst_first_rc == rc_stack) {
1345 // gpr -> mem
1346 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1347 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1348 // 64-bit
1349 int offset = ra_->reg2offset(dst_first);
1350 if (cbuf) {
1351 if (Matcher::_regEncode[src_first] < 8) {
1352 emit_opcode(*cbuf, Assembler::REX_W);
1353 } else {
1354 emit_opcode(*cbuf, Assembler::REX_WR);
1355 }
1356 emit_opcode(*cbuf, 0x89);
1357 encode_RegMem(*cbuf,
1358 Matcher::_regEncode[src_first],
1359 RSP_enc, 0x4, 0, offset,
1360 false);
1361 #ifndef PRODUCT
1362 } else if (!do_size) {
1363 st->print("movq [rsp + #%d], %s\t# spill",
1364 offset,
1365 Matcher::regName[src_first]);
1366 #endif
1367 }
1368 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1369 } else {
1370 // 32-bit
1371 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1372 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1373 int offset = ra_->reg2offset(dst_first);
1374 if (cbuf) {
1375 if (Matcher::_regEncode[src_first] >= 8) {
1376 emit_opcode(*cbuf, Assembler::REX_R);
1377 }
1378 emit_opcode(*cbuf, 0x89);
1379 encode_RegMem(*cbuf,
1380 Matcher::_regEncode[src_first],
1381 RSP_enc, 0x4, 0, offset,
1382 false);
1383 #ifndef PRODUCT
1384 } else if (!do_size) {
1385 st->print("movl [rsp + #%d], %s\t# spill",
1386 offset,
1387 Matcher::regName[src_first]);
1388 #endif
1389 }
1390 return
1391 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1392 ((Matcher::_regEncode[src_first] < 8)
1393 ? 3
1394 : 4); // REX
1395 }
1396 } else if (dst_first_rc == rc_int) {
1397 // gpr -> gpr
1398 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1399 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1400 // 64-bit
1401 if (cbuf) {
1402 if (Matcher::_regEncode[dst_first] < 8) {
1403 if (Matcher::_regEncode[src_first] < 8) {
1404 emit_opcode(*cbuf, Assembler::REX_W);
1405 } else {
1406 emit_opcode(*cbuf, Assembler::REX_WB);
1407 }
1408 } else {
1409 if (Matcher::_regEncode[src_first] < 8) {
1410 emit_opcode(*cbuf, Assembler::REX_WR);
1411 } else {
1412 emit_opcode(*cbuf, Assembler::REX_WRB);
1413 }
1414 }
1415 emit_opcode(*cbuf, 0x8B);
1416 emit_rm(*cbuf, 0x3,
1417 Matcher::_regEncode[dst_first] & 7,
1418 Matcher::_regEncode[src_first] & 7);
1419 #ifndef PRODUCT
1420 } else if (!do_size) {
1421 st->print("movq %s, %s\t# spill",
1422 Matcher::regName[dst_first],
1423 Matcher::regName[src_first]);
1424 #endif
1425 }
1426 return 3; // REX
1427 } else {
1428 // 32-bit
1429 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1430 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1431 if (cbuf) {
1432 if (Matcher::_regEncode[dst_first] < 8) {
1433 if (Matcher::_regEncode[src_first] >= 8) {
1434 emit_opcode(*cbuf, Assembler::REX_B);
1435 }
1436 } else {
1437 if (Matcher::_regEncode[src_first] < 8) {
1438 emit_opcode(*cbuf, Assembler::REX_R);
1439 } else {
1440 emit_opcode(*cbuf, Assembler::REX_RB);
1441 }
1442 }
1443 emit_opcode(*cbuf, 0x8B);
1444 emit_rm(*cbuf, 0x3,
1445 Matcher::_regEncode[dst_first] & 7,
1446 Matcher::_regEncode[src_first] & 7);
1447 #ifndef PRODUCT
1448 } else if (!do_size) {
1449 st->print("movl %s, %s\t# spill",
1450 Matcher::regName[dst_first],
1451 Matcher::regName[src_first]);
1452 #endif
1453 }
1454 return
1455 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1456 ? 2
1457 : 3; // REX
1458 }
1459 } else if (dst_first_rc == rc_float) {
1460 // gpr -> xmm
1461 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1462 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1463 // 64-bit
1464 if (cbuf) {
1465 emit_opcode(*cbuf, 0x66);
1466 if (Matcher::_regEncode[dst_first] < 8) {
1467 if (Matcher::_regEncode[src_first] < 8) {
1468 emit_opcode(*cbuf, Assembler::REX_W);
1469 } else {
1470 emit_opcode(*cbuf, Assembler::REX_WB);
1471 }
1472 } else {
1473 if (Matcher::_regEncode[src_first] < 8) {
1474 emit_opcode(*cbuf, Assembler::REX_WR);
1475 } else {
1476 emit_opcode(*cbuf, Assembler::REX_WRB);
1477 }
1478 }
1479 emit_opcode(*cbuf, 0x0F);
1480 emit_opcode(*cbuf, 0x6E);
1481 emit_rm(*cbuf, 0x3,
1482 Matcher::_regEncode[dst_first] & 7,
1483 Matcher::_regEncode[src_first] & 7);
1484 #ifndef PRODUCT
1485 } else if (!do_size) {
1486 st->print("movdq %s, %s\t# spill",
1487 Matcher::regName[dst_first],
1488 Matcher::regName[src_first]);
1489 #endif
1490 }
1491 return 5; // REX
1492 } else {
1493 // 32-bit
1494 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1495 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1496 if (cbuf) {
1497 emit_opcode(*cbuf, 0x66);
1498 if (Matcher::_regEncode[dst_first] < 8) {
1499 if (Matcher::_regEncode[src_first] >= 8) {
1500 emit_opcode(*cbuf, Assembler::REX_B);
1501 }
1502 } else {
1503 if (Matcher::_regEncode[src_first] < 8) {
1504 emit_opcode(*cbuf, Assembler::REX_R);
1505 } else {
1506 emit_opcode(*cbuf, Assembler::REX_RB);
1507 }
1508 }
1509 emit_opcode(*cbuf, 0x0F);
1510 emit_opcode(*cbuf, 0x6E);
1511 emit_rm(*cbuf, 0x3,
1512 Matcher::_regEncode[dst_first] & 7,
1513 Matcher::_regEncode[src_first] & 7);
1514 #ifndef PRODUCT
1515 } else if (!do_size) {
1516 st->print("movdl %s, %s\t# spill",
1517 Matcher::regName[dst_first],
1518 Matcher::regName[src_first]);
1519 #endif
1520 }
1521 return
1522 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1523 ? 4
1524 : 5; // REX
1525 }
1526 }
1527 } else if (src_first_rc == rc_float) {
1528 // xmm ->
1529 if (dst_first_rc == rc_stack) {
1530 // xmm -> mem
1531 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1532 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1533 // 64-bit
1534 int offset = ra_->reg2offset(dst_first);
1535 if (cbuf) {
1536 emit_opcode(*cbuf, 0xF2);
1537 if (Matcher::_regEncode[src_first] >= 8) {
1538 emit_opcode(*cbuf, Assembler::REX_R);
1539 }
1540 emit_opcode(*cbuf, 0x0F);
1541 emit_opcode(*cbuf, 0x11);
1542 encode_RegMem(*cbuf,
1543 Matcher::_regEncode[src_first],
1544 RSP_enc, 0x4, 0, offset,
1545 false);
1546 #ifndef PRODUCT
1547 } else if (!do_size) {
1548 st->print("movsd [rsp + #%d], %s\t# spill",
1549 offset,
1550 Matcher::regName[src_first]);
1551 #endif
1552 }
1553 return
1554 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1555 ((Matcher::_regEncode[src_first] < 8)
1556 ? 5
1557 : 6); // REX
1558 } else {
1559 // 32-bit
1560 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1561 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1562 int offset = ra_->reg2offset(dst_first);
1563 if (cbuf) {
1564 emit_opcode(*cbuf, 0xF3);
1565 if (Matcher::_regEncode[src_first] >= 8) {
1566 emit_opcode(*cbuf, Assembler::REX_R);
1567 }
1568 emit_opcode(*cbuf, 0x0F);
1569 emit_opcode(*cbuf, 0x11);
1570 encode_RegMem(*cbuf,
1571 Matcher::_regEncode[src_first],
1572 RSP_enc, 0x4, 0, offset,
1573 false);
1574 #ifndef PRODUCT
1575 } else if (!do_size) {
1576 st->print("movss [rsp + #%d], %s\t# spill",
1577 offset,
1578 Matcher::regName[src_first]);
1579 #endif
1580 }
1581 return
1582 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1583 ((Matcher::_regEncode[src_first] < 8)
1584 ? 5
1585 : 6); // REX
1586 }
1587 } else if (dst_first_rc == rc_int) {
1588 // xmm -> gpr
1589 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1590 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1591 // 64-bit
1592 if (cbuf) {
1593 emit_opcode(*cbuf, 0x66);
1594 if (Matcher::_regEncode[dst_first] < 8) {
1595 if (Matcher::_regEncode[src_first] < 8) {
1596 emit_opcode(*cbuf, Assembler::REX_W);
1597 } else {
1598 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
1599 }
1600 } else {
1601 if (Matcher::_regEncode[src_first] < 8) {
1602 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
1603 } else {
1604 emit_opcode(*cbuf, Assembler::REX_WRB);
1605 }
1606 }
1607 emit_opcode(*cbuf, 0x0F);
1608 emit_opcode(*cbuf, 0x7E);
1609 emit_rm(*cbuf, 0x3,
1610 Matcher::_regEncode[src_first] & 7,
1611 Matcher::_regEncode[dst_first] & 7);
1612 #ifndef PRODUCT
1613 } else if (!do_size) {
1614 st->print("movdq %s, %s\t# spill",
1615 Matcher::regName[dst_first],
1616 Matcher::regName[src_first]);
1617 #endif
1618 }
1619 return 5; // REX
1620 } else {
1621 // 32-bit
1622 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1623 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1624 if (cbuf) {
1625 emit_opcode(*cbuf, 0x66);
1626 if (Matcher::_regEncode[dst_first] < 8) {
1627 if (Matcher::_regEncode[src_first] >= 8) {
1628 emit_opcode(*cbuf, Assembler::REX_R); // attention!
1629 }
1630 } else {
1631 if (Matcher::_regEncode[src_first] < 8) {
1632 emit_opcode(*cbuf, Assembler::REX_B); // attention!
1633 } else {
1634 emit_opcode(*cbuf, Assembler::REX_RB);
1635 }
1636 }
1637 emit_opcode(*cbuf, 0x0F);
1638 emit_opcode(*cbuf, 0x7E);
1639 emit_rm(*cbuf, 0x3,
1640 Matcher::_regEncode[src_first] & 7,
1641 Matcher::_regEncode[dst_first] & 7);
1642 #ifndef PRODUCT
1643 } else if (!do_size) {
1644 st->print("movdl %s, %s\t# spill",
1645 Matcher::regName[dst_first],
1646 Matcher::regName[src_first]);
1647 #endif
1648 }
1649 return
1650 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1651 ? 4
1652 : 5; // REX
1653 }
1654 } else if (dst_first_rc == rc_float) {
1655 // xmm -> xmm
1656 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1657 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1658 // 64-bit
1659 if (cbuf) {
1660 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
1661 if (Matcher::_regEncode[dst_first] < 8) {
1662 if (Matcher::_regEncode[src_first] >= 8) {
1663 emit_opcode(*cbuf, Assembler::REX_B);
1664 }
1665 } else {
1666 if (Matcher::_regEncode[src_first] < 8) {
1667 emit_opcode(*cbuf, Assembler::REX_R);
1668 } else {
1669 emit_opcode(*cbuf, Assembler::REX_RB);
1670 }
1671 }
1672 emit_opcode(*cbuf, 0x0F);
1673 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1674 emit_rm(*cbuf, 0x3,
1675 Matcher::_regEncode[dst_first] & 7,
1676 Matcher::_regEncode[src_first] & 7);
1677 #ifndef PRODUCT
1678 } else if (!do_size) {
1679 st->print("%s %s, %s\t# spill",
1680 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1681 Matcher::regName[dst_first],
1682 Matcher::regName[src_first]);
1683 #endif
1684 }
1685 return
1686 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1687 ? 4
1688 : 5; // REX
1689 } else {
1690 // 32-bit
1691 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1692 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1693 if (cbuf) {
1694 if (!UseXmmRegToRegMoveAll)
1695 emit_opcode(*cbuf, 0xF3);
1696 if (Matcher::_regEncode[dst_first] < 8) {
1697 if (Matcher::_regEncode[src_first] >= 8) {
1698 emit_opcode(*cbuf, Assembler::REX_B);
1699 }
1700 } else {
1701 if (Matcher::_regEncode[src_first] < 8) {
1702 emit_opcode(*cbuf, Assembler::REX_R);
1703 } else {
1704 emit_opcode(*cbuf, Assembler::REX_RB);
1705 }
1706 }
1707 emit_opcode(*cbuf, 0x0F);
1708 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1709 emit_rm(*cbuf, 0x3,
1710 Matcher::_regEncode[dst_first] & 7,
1711 Matcher::_regEncode[src_first] & 7);
1712 #ifndef PRODUCT
1713 } else if (!do_size) {
1714 st->print("%s %s, %s\t# spill",
1715 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1716 Matcher::regName[dst_first],
1717 Matcher::regName[src_first]);
1718 #endif
1719 }
1720 return
1721 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1722 ? (UseXmmRegToRegMoveAll ? 3 : 4)
1723 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
1724 }
1725 }
1726 }
1728 assert(0," foo ");
1729 Unimplemented();
1731 return 0;
1732 }
1734 #ifndef PRODUCT
1735 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1736 {
1737 implementation(NULL, ra_, false, st);
1738 }
1739 #endif
1741 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1742 {
1743 implementation(&cbuf, ra_, false, NULL);
1744 }
1746 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1747 {
1748 return implementation(NULL, ra_, true, NULL);
1749 }
1751 //=============================================================================
1752 #ifndef PRODUCT
1753 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
1754 {
1755 st->print("nop \t# %d bytes pad for loops and calls", _count);
1756 }
1757 #endif
1759 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
1760 {
1761 MacroAssembler _masm(&cbuf);
1762 __ nop(_count);
1763 }
1765 uint MachNopNode::size(PhaseRegAlloc*) const
1766 {
1767 return _count;
1768 }
1771 //=============================================================================
1772 #ifndef PRODUCT
1773 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1774 {
1775 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1776 int reg = ra_->get_reg_first(this);
1777 st->print("leaq %s, [rsp + #%d]\t# box lock",
1778 Matcher::regName[reg], offset);
1779 }
1780 #endif
1782 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1783 {
1784 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1785 int reg = ra_->get_encode(this);
1786 if (offset >= 0x80) {
1787 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1788 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1789 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1790 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1791 emit_d32(cbuf, offset);
1792 } else {
1793 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1794 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1795 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1796 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1797 emit_d8(cbuf, offset);
1798 }
1799 }
1801 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1802 {
1803 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1804 return (offset < 0x80) ? 5 : 8; // REX
1805 }
1807 //=============================================================================
1809 // emit call stub, compiled java to interpreter
1810 void emit_java_to_interp(CodeBuffer& cbuf)
1811 {
1812 // Stub is fixed up when the corresponding call is converted from
1813 // calling compiled code to calling interpreted code.
1814 // movq rbx, 0
1815 // jmp -5 # to self
1817 address mark = cbuf.inst_mark(); // get mark within main instrs section
1819 // Note that the code buffer's inst_mark is always relative to insts.
1820 // That's why we must use the macroassembler to generate a stub.
1821 MacroAssembler _masm(&cbuf);
1823 address base =
1824 __ start_a_stub(Compile::MAX_stubs_size);
1825 if (base == NULL) return; // CodeBuffer::expand failed
1826 // static stub relocation stores the instruction address of the call
1827 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1828 // static stub relocation also tags the methodOop in the code-stream.
1829 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1830 // This is recognized as unresolved by relocs/nativeinst/ic code
1831 __ jump(RuntimeAddress(__ pc()));
1833 // Update current stubs pointer and restore code_end.
1834 __ end_a_stub();
1835 }
1837 // size of call stub, compiled java to interpretor
1838 uint size_java_to_interp()
1839 {
1840 return 15; // movq (1+1+8); jmp (1+4)
1841 }
1843 // relocation entries for call stub, compiled java to interpretor
1844 uint reloc_java_to_interp()
1845 {
1846 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1847 }
1849 //=============================================================================
1850 #ifndef PRODUCT
1851 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1852 {
1853 if (UseCompressedOops) {
1854 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1855 if (Universe::narrow_oop_shift() != 0) {
1856 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
1857 }
1858 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1859 } else {
1860 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1861 "# Inline cache check");
1862 }
1863 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1864 st->print_cr("\tnop\t# nops to align entry point");
1865 }
1866 #endif
1868 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1869 {
1870 MacroAssembler masm(&cbuf);
1871 uint code_size = cbuf.code_size();
1872 if (UseCompressedOops) {
1873 masm.load_klass(rscratch1, j_rarg0);
1874 masm.cmpptr(rax, rscratch1);
1875 } else {
1876 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1877 }
1879 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1881 /* WARNING these NOPs are critical so that verified entry point is properly
1882 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1883 int nops_cnt = 4 - ((cbuf.code_size() - code_size) & 0x3);
1884 if (OptoBreakpoint) {
1885 // Leave space for int3
1886 nops_cnt -= 1;
1887 }
1888 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1889 if (nops_cnt > 0)
1890 masm.nop(nops_cnt);
1891 }
1893 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1894 {
1895 return MachNode::size(ra_); // too many variables; just compute it
1896 // the hard way
1897 }
1900 //=============================================================================
1901 uint size_exception_handler()
1902 {
1903 // NativeCall instruction size is the same as NativeJump.
1904 // Note that this value is also credited (in output.cpp) to
1905 // the size of the code section.
1906 return NativeJump::instruction_size;
1907 }
1909 // Emit exception handler code.
1910 int emit_exception_handler(CodeBuffer& cbuf)
1911 {
1913 // Note that the code buffer's inst_mark is always relative to insts.
1914 // That's why we must use the macroassembler to generate a handler.
1915 MacroAssembler _masm(&cbuf);
1916 address base =
1917 __ start_a_stub(size_exception_handler());
1918 if (base == NULL) return 0; // CodeBuffer::expand failed
1919 int offset = __ offset();
1920 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1921 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1922 __ end_a_stub();
1923 return offset;
1924 }
1926 uint size_deopt_handler()
1927 {
1928 // three 5 byte instructions
1929 return 15;
1930 }
1932 // Emit deopt handler code.
1933 int emit_deopt_handler(CodeBuffer& cbuf)
1934 {
1936 // Note that the code buffer's inst_mark is always relative to insts.
1937 // That's why we must use the macroassembler to generate a handler.
1938 MacroAssembler _masm(&cbuf);
1939 address base =
1940 __ start_a_stub(size_deopt_handler());
1941 if (base == NULL) return 0; // CodeBuffer::expand failed
1942 int offset = __ offset();
1943 address the_pc = (address) __ pc();
1944 Label next;
1945 // push a "the_pc" on the stack without destroying any registers
1946 // as they all may be live.
1948 // push address of "next"
1949 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1950 __ bind(next);
1951 // adjust it so it matches "the_pc"
1952 __ subptr(Address(rsp, 0), __ offset() - offset);
1953 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1954 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1955 __ end_a_stub();
1956 return offset;
1957 }
1959 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1960 int mark = cbuf.insts()->mark_off();
1961 MacroAssembler _masm(&cbuf);
1962 address double_address = __ double_constant(x);
1963 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1964 emit_d32_reloc(cbuf,
1965 (int) (double_address - cbuf.code_end() - 4),
1966 internal_word_Relocation::spec(double_address),
1967 RELOC_DISP32);
1968 }
1970 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1971 int mark = cbuf.insts()->mark_off();
1972 MacroAssembler _masm(&cbuf);
1973 address float_address = __ float_constant(x);
1974 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1975 emit_d32_reloc(cbuf,
1976 (int) (float_address - cbuf.code_end() - 4),
1977 internal_word_Relocation::spec(float_address),
1978 RELOC_DISP32);
1979 }
1982 const bool Matcher::match_rule_supported(int opcode) {
1983 if (!has_match_rule(opcode))
1984 return false;
1986 return true; // Per default match rules are supported.
1987 }
1989 int Matcher::regnum_to_fpu_offset(int regnum)
1990 {
1991 return regnum - 32; // The FP registers are in the second chunk
1992 }
1994 // This is UltraSparc specific, true just means we have fast l2f conversion
1995 const bool Matcher::convL2FSupported(void) {
1996 return true;
1997 }
1999 // Vector width in bytes
2000 const uint Matcher::vector_width_in_bytes(void) {
2001 return 8;
2002 }
2004 // Vector ideal reg
2005 const uint Matcher::vector_ideal_reg(void) {
2006 return Op_RegD;
2007 }
2009 // Is this branch offset short enough that a short branch can be used?
2010 //
2011 // NOTE: If the platform does not provide any short branch variants, then
2012 // this method should return false for offset 0.
2013 bool Matcher::is_short_branch_offset(int rule, int offset) {
2014 // the short version of jmpConUCF2 contains multiple branches,
2015 // making the reach slightly less
2016 if (rule == jmpConUCF2_rule)
2017 return (-126 <= offset && offset <= 125);
2018 return (-128 <= offset && offset <= 127);
2019 }
2021 const bool Matcher::isSimpleConstant64(jlong value) {
2022 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
2023 //return value == (int) value; // Cf. storeImmL and immL32.
2025 // Probably always true, even if a temp register is required.
2026 return true;
2027 }
2029 // The ecx parameter to rep stosq for the ClearArray node is in words.
2030 const bool Matcher::init_array_count_is_in_bytes = false;
2032 // Threshold size for cleararray.
2033 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2035 // Should the Matcher clone shifts on addressing modes, expecting them
2036 // to be subsumed into complex addressing expressions or compute them
2037 // into registers? True for Intel but false for most RISCs
2038 const bool Matcher::clone_shift_expressions = true;
2040 bool Matcher::narrow_oop_use_complex_address() {
2041 assert(UseCompressedOops, "only for compressed oops code");
2042 return (LogMinObjAlignmentInBytes <= 3);
2043 }
2045 // Is it better to copy float constants, or load them directly from
2046 // memory? Intel can load a float constant from a direct address,
2047 // requiring no extra registers. Most RISCs will have to materialize
2048 // an address into a register first, so they would do better to copy
2049 // the constant from stack.
2050 const bool Matcher::rematerialize_float_constants = true; // XXX
2052 // If CPU can load and store mis-aligned doubles directly then no
2053 // fixup is needed. Else we split the double into 2 integer pieces
2054 // and move it piece-by-piece. Only happens when passing doubles into
2055 // C code as the Java calling convention forces doubles to be aligned.
2056 const bool Matcher::misaligned_doubles_ok = true;
2058 // No-op on amd64
2059 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
2061 // Advertise here if the CPU requires explicit rounding operations to
2062 // implement the UseStrictFP mode.
2063 const bool Matcher::strict_fp_requires_explicit_rounding = true;
2065 // Are floats conerted to double when stored to stack during deoptimization?
2066 // On x64 it is stored without convertion so we can use normal access.
2067 bool Matcher::float_in_double() { return false; }
2069 // Do ints take an entire long register or just half?
2070 const bool Matcher::int_in_long = true;
2072 // Return whether or not this register is ever used as an argument.
2073 // This function is used on startup to build the trampoline stubs in
2074 // generateOptoStub. Registers not mentioned will be killed by the VM
2075 // call in the trampoline, and arguments in those registers not be
2076 // available to the callee.
2077 bool Matcher::can_be_java_arg(int reg)
2078 {
2079 return
2080 reg == RDI_num || reg == RDI_H_num ||
2081 reg == RSI_num || reg == RSI_H_num ||
2082 reg == RDX_num || reg == RDX_H_num ||
2083 reg == RCX_num || reg == RCX_H_num ||
2084 reg == R8_num || reg == R8_H_num ||
2085 reg == R9_num || reg == R9_H_num ||
2086 reg == R12_num || reg == R12_H_num ||
2087 reg == XMM0_num || reg == XMM0_H_num ||
2088 reg == XMM1_num || reg == XMM1_H_num ||
2089 reg == XMM2_num || reg == XMM2_H_num ||
2090 reg == XMM3_num || reg == XMM3_H_num ||
2091 reg == XMM4_num || reg == XMM4_H_num ||
2092 reg == XMM5_num || reg == XMM5_H_num ||
2093 reg == XMM6_num || reg == XMM6_H_num ||
2094 reg == XMM7_num || reg == XMM7_H_num;
2095 }
2097 bool Matcher::is_spillable_arg(int reg)
2098 {
2099 return can_be_java_arg(reg);
2100 }
2102 // Register for DIVI projection of divmodI
2103 RegMask Matcher::divI_proj_mask() {
2104 return INT_RAX_REG_mask;
2105 }
2107 // Register for MODI projection of divmodI
2108 RegMask Matcher::modI_proj_mask() {
2109 return INT_RDX_REG_mask;
2110 }
2112 // Register for DIVL projection of divmodL
2113 RegMask Matcher::divL_proj_mask() {
2114 return LONG_RAX_REG_mask;
2115 }
2117 // Register for MODL projection of divmodL
2118 RegMask Matcher::modL_proj_mask() {
2119 return LONG_RDX_REG_mask;
2120 }
2122 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2123 return PTR_RBP_REG_mask;
2124 }
2126 static Address build_address(int b, int i, int s, int d) {
2127 Register index = as_Register(i);
2128 Address::ScaleFactor scale = (Address::ScaleFactor)s;
2129 if (index == rsp) {
2130 index = noreg;
2131 scale = Address::no_scale;
2132 }
2133 Address addr(as_Register(b), index, scale, d);
2134 return addr;
2135 }
2137 %}
2139 //----------ENCODING BLOCK-----------------------------------------------------
2140 // This block specifies the encoding classes used by the compiler to
2141 // output byte streams. Encoding classes are parameterized macros
2142 // used by Machine Instruction Nodes in order to generate the bit
2143 // encoding of the instruction. Operands specify their base encoding
2144 // interface with the interface keyword. There are currently
2145 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2146 // COND_INTER. REG_INTER causes an operand to generate a function
2147 // which returns its register number when queried. CONST_INTER causes
2148 // an operand to generate a function which returns the value of the
2149 // constant when queried. MEMORY_INTER causes an operand to generate
2150 // four functions which return the Base Register, the Index Register,
2151 // the Scale Value, and the Offset Value of the operand when queried.
2152 // COND_INTER causes an operand to generate six functions which return
2153 // the encoding code (ie - encoding bits for the instruction)
2154 // associated with each basic boolean condition for a conditional
2155 // instruction.
2156 //
2157 // Instructions specify two basic values for encoding. Again, a
2158 // function is available to check if the constant displacement is an
2159 // oop. They use the ins_encode keyword to specify their encoding
2160 // classes (which must be a sequence of enc_class names, and their
2161 // parameters, specified in the encoding block), and they use the
2162 // opcode keyword to specify, in order, their primary, secondary, and
2163 // tertiary opcode. Only the opcode sections which a particular
2164 // instruction needs for encoding need to be specified.
2165 encode %{
2166 // Build emit functions for each basic byte or larger field in the
2167 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2168 // from C++ code in the enc_class source block. Emit functions will
2169 // live in the main source block for now. In future, we can
2170 // generalize this by adding a syntax that specifies the sizes of
2171 // fields in an order, so that the adlc can build the emit functions
2172 // automagically
2174 // Emit primary opcode
2175 enc_class OpcP
2176 %{
2177 emit_opcode(cbuf, $primary);
2178 %}
2180 // Emit secondary opcode
2181 enc_class OpcS
2182 %{
2183 emit_opcode(cbuf, $secondary);
2184 %}
2186 // Emit tertiary opcode
2187 enc_class OpcT
2188 %{
2189 emit_opcode(cbuf, $tertiary);
2190 %}
2192 // Emit opcode directly
2193 enc_class Opcode(immI d8)
2194 %{
2195 emit_opcode(cbuf, $d8$$constant);
2196 %}
2198 // Emit size prefix
2199 enc_class SizePrefix
2200 %{
2201 emit_opcode(cbuf, 0x66);
2202 %}
2204 enc_class reg(rRegI reg)
2205 %{
2206 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
2207 %}
2209 enc_class reg_reg(rRegI dst, rRegI src)
2210 %{
2211 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2212 %}
2214 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
2215 %{
2216 emit_opcode(cbuf, $opcode$$constant);
2217 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2218 %}
2220 enc_class cmpfp_fixup()
2221 %{
2222 // jnp,s exit
2223 emit_opcode(cbuf, 0x7B);
2224 emit_d8(cbuf, 0x0A);
2226 // pushfq
2227 emit_opcode(cbuf, 0x9C);
2229 // andq $0xffffff2b, (%rsp)
2230 emit_opcode(cbuf, Assembler::REX_W);
2231 emit_opcode(cbuf, 0x81);
2232 emit_opcode(cbuf, 0x24);
2233 emit_opcode(cbuf, 0x24);
2234 emit_d32(cbuf, 0xffffff2b);
2236 // popfq
2237 emit_opcode(cbuf, 0x9D);
2239 // nop (target for branch to avoid branch to branch)
2240 emit_opcode(cbuf, 0x90);
2241 %}
2243 enc_class cmpfp3(rRegI dst)
2244 %{
2245 int dstenc = $dst$$reg;
2247 // movl $dst, -1
2248 if (dstenc >= 8) {
2249 emit_opcode(cbuf, Assembler::REX_B);
2250 }
2251 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2252 emit_d32(cbuf, -1);
2254 // jp,s done
2255 emit_opcode(cbuf, 0x7A);
2256 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
2258 // jb,s done
2259 emit_opcode(cbuf, 0x72);
2260 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2262 // setne $dst
2263 if (dstenc >= 4) {
2264 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2265 }
2266 emit_opcode(cbuf, 0x0F);
2267 emit_opcode(cbuf, 0x95);
2268 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2270 // movzbl $dst, $dst
2271 if (dstenc >= 4) {
2272 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2273 }
2274 emit_opcode(cbuf, 0x0F);
2275 emit_opcode(cbuf, 0xB6);
2276 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2277 %}
2279 enc_class cdql_enc(no_rax_rdx_RegI div)
2280 %{
2281 // Full implementation of Java idiv and irem; checks for
2282 // special case as described in JVM spec., p.243 & p.271.
2283 //
2284 // normal case special case
2285 //
2286 // input : rax: dividend min_int
2287 // reg: divisor -1
2288 //
2289 // output: rax: quotient (= rax idiv reg) min_int
2290 // rdx: remainder (= rax irem reg) 0
2291 //
2292 // Code sequnce:
2293 //
2294 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
2295 // 5: 75 07/08 jne e <normal>
2296 // 7: 33 d2 xor %edx,%edx
2297 // [div >= 8 -> offset + 1]
2298 // [REX_B]
2299 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
2300 // c: 74 03/04 je 11 <done>
2301 // 000000000000000e <normal>:
2302 // e: 99 cltd
2303 // [div >= 8 -> offset + 1]
2304 // [REX_B]
2305 // f: f7 f9 idiv $div
2306 // 0000000000000011 <done>:
2308 // cmp $0x80000000,%eax
2309 emit_opcode(cbuf, 0x3d);
2310 emit_d8(cbuf, 0x00);
2311 emit_d8(cbuf, 0x00);
2312 emit_d8(cbuf, 0x00);
2313 emit_d8(cbuf, 0x80);
2315 // jne e <normal>
2316 emit_opcode(cbuf, 0x75);
2317 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
2319 // xor %edx,%edx
2320 emit_opcode(cbuf, 0x33);
2321 emit_d8(cbuf, 0xD2);
2323 // cmp $0xffffffffffffffff,%ecx
2324 if ($div$$reg >= 8) {
2325 emit_opcode(cbuf, Assembler::REX_B);
2326 }
2327 emit_opcode(cbuf, 0x83);
2328 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2329 emit_d8(cbuf, 0xFF);
2331 // je 11 <done>
2332 emit_opcode(cbuf, 0x74);
2333 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2335 // <normal>
2336 // cltd
2337 emit_opcode(cbuf, 0x99);
2339 // idivl (note: must be emitted by the user of this rule)
2340 // <done>
2341 %}
2343 enc_class cdqq_enc(no_rax_rdx_RegL div)
2344 %{
2345 // Full implementation of Java ldiv and lrem; checks for
2346 // special case as described in JVM spec., p.243 & p.271.
2347 //
2348 // normal case special case
2349 //
2350 // input : rax: dividend min_long
2351 // reg: divisor -1
2352 //
2353 // output: rax: quotient (= rax idiv reg) min_long
2354 // rdx: remainder (= rax irem reg) 0
2355 //
2356 // Code sequnce:
2357 //
2358 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2359 // 7: 00 00 80
2360 // a: 48 39 d0 cmp %rdx,%rax
2361 // d: 75 08 jne 17 <normal>
2362 // f: 33 d2 xor %edx,%edx
2363 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2364 // 15: 74 05 je 1c <done>
2365 // 0000000000000017 <normal>:
2366 // 17: 48 99 cqto
2367 // 19: 48 f7 f9 idiv $div
2368 // 000000000000001c <done>:
2370 // mov $0x8000000000000000,%rdx
2371 emit_opcode(cbuf, Assembler::REX_W);
2372 emit_opcode(cbuf, 0xBA);
2373 emit_d8(cbuf, 0x00);
2374 emit_d8(cbuf, 0x00);
2375 emit_d8(cbuf, 0x00);
2376 emit_d8(cbuf, 0x00);
2377 emit_d8(cbuf, 0x00);
2378 emit_d8(cbuf, 0x00);
2379 emit_d8(cbuf, 0x00);
2380 emit_d8(cbuf, 0x80);
2382 // cmp %rdx,%rax
2383 emit_opcode(cbuf, Assembler::REX_W);
2384 emit_opcode(cbuf, 0x39);
2385 emit_d8(cbuf, 0xD0);
2387 // jne 17 <normal>
2388 emit_opcode(cbuf, 0x75);
2389 emit_d8(cbuf, 0x08);
2391 // xor %edx,%edx
2392 emit_opcode(cbuf, 0x33);
2393 emit_d8(cbuf, 0xD2);
2395 // cmp $0xffffffffffffffff,$div
2396 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2397 emit_opcode(cbuf, 0x83);
2398 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2399 emit_d8(cbuf, 0xFF);
2401 // je 1e <done>
2402 emit_opcode(cbuf, 0x74);
2403 emit_d8(cbuf, 0x05);
2405 // <normal>
2406 // cqto
2407 emit_opcode(cbuf, Assembler::REX_W);
2408 emit_opcode(cbuf, 0x99);
2410 // idivq (note: must be emitted by the user of this rule)
2411 // <done>
2412 %}
2414 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2415 enc_class OpcSE(immI imm)
2416 %{
2417 // Emit primary opcode and set sign-extend bit
2418 // Check for 8-bit immediate, and set sign extend bit in opcode
2419 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2420 emit_opcode(cbuf, $primary | 0x02);
2421 } else {
2422 // 32-bit immediate
2423 emit_opcode(cbuf, $primary);
2424 }
2425 %}
2427 enc_class OpcSErm(rRegI dst, immI imm)
2428 %{
2429 // OpcSEr/m
2430 int dstenc = $dst$$reg;
2431 if (dstenc >= 8) {
2432 emit_opcode(cbuf, Assembler::REX_B);
2433 dstenc -= 8;
2434 }
2435 // Emit primary opcode and set sign-extend bit
2436 // Check for 8-bit immediate, and set sign extend bit in opcode
2437 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2438 emit_opcode(cbuf, $primary | 0x02);
2439 } else {
2440 // 32-bit immediate
2441 emit_opcode(cbuf, $primary);
2442 }
2443 // Emit r/m byte with secondary opcode, after primary opcode.
2444 emit_rm(cbuf, 0x3, $secondary, dstenc);
2445 %}
2447 enc_class OpcSErm_wide(rRegL dst, immI imm)
2448 %{
2449 // OpcSEr/m
2450 int dstenc = $dst$$reg;
2451 if (dstenc < 8) {
2452 emit_opcode(cbuf, Assembler::REX_W);
2453 } else {
2454 emit_opcode(cbuf, Assembler::REX_WB);
2455 dstenc -= 8;
2456 }
2457 // Emit primary opcode and set sign-extend bit
2458 // Check for 8-bit immediate, and set sign extend bit in opcode
2459 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2460 emit_opcode(cbuf, $primary | 0x02);
2461 } else {
2462 // 32-bit immediate
2463 emit_opcode(cbuf, $primary);
2464 }
2465 // Emit r/m byte with secondary opcode, after primary opcode.
2466 emit_rm(cbuf, 0x3, $secondary, dstenc);
2467 %}
2469 enc_class Con8or32(immI imm)
2470 %{
2471 // Check for 8-bit immediate, and set sign extend bit in opcode
2472 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2473 $$$emit8$imm$$constant;
2474 } else {
2475 // 32-bit immediate
2476 $$$emit32$imm$$constant;
2477 }
2478 %}
2480 enc_class Lbl(label labl)
2481 %{
2482 // JMP, CALL
2483 Label* l = $labl$$label;
2484 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2485 %}
2487 enc_class LblShort(label labl)
2488 %{
2489 // JMP, CALL
2490 Label* l = $labl$$label;
2491 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2492 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2493 emit_d8(cbuf, disp);
2494 %}
2496 enc_class opc2_reg(rRegI dst)
2497 %{
2498 // BSWAP
2499 emit_cc(cbuf, $secondary, $dst$$reg);
2500 %}
2502 enc_class opc3_reg(rRegI dst)
2503 %{
2504 // BSWAP
2505 emit_cc(cbuf, $tertiary, $dst$$reg);
2506 %}
2508 enc_class reg_opc(rRegI div)
2509 %{
2510 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2511 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2512 %}
2514 enc_class Jcc(cmpOp cop, label labl)
2515 %{
2516 // JCC
2517 Label* l = $labl$$label;
2518 $$$emit8$primary;
2519 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2520 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2521 %}
2523 enc_class JccShort (cmpOp cop, label labl)
2524 %{
2525 // JCC
2526 Label *l = $labl$$label;
2527 emit_cc(cbuf, $primary, $cop$$cmpcode);
2528 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2529 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2530 emit_d8(cbuf, disp);
2531 %}
2533 enc_class enc_cmov(cmpOp cop)
2534 %{
2535 // CMOV
2536 $$$emit8$primary;
2537 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2538 %}
2540 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
2541 %{
2542 // Invert sense of branch from sense of cmov
2543 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2544 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
2545 ? (UseXmmRegToRegMoveAll ? 3 : 4)
2546 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
2547 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
2548 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
2549 if ($dst$$reg < 8) {
2550 if ($src$$reg >= 8) {
2551 emit_opcode(cbuf, Assembler::REX_B);
2552 }
2553 } else {
2554 if ($src$$reg < 8) {
2555 emit_opcode(cbuf, Assembler::REX_R);
2556 } else {
2557 emit_opcode(cbuf, Assembler::REX_RB);
2558 }
2559 }
2560 emit_opcode(cbuf, 0x0F);
2561 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2562 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2563 %}
2565 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
2566 %{
2567 // Invert sense of branch from sense of cmov
2568 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2569 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
2571 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
2572 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
2573 if ($dst$$reg < 8) {
2574 if ($src$$reg >= 8) {
2575 emit_opcode(cbuf, Assembler::REX_B);
2576 }
2577 } else {
2578 if ($src$$reg < 8) {
2579 emit_opcode(cbuf, Assembler::REX_R);
2580 } else {
2581 emit_opcode(cbuf, Assembler::REX_RB);
2582 }
2583 }
2584 emit_opcode(cbuf, 0x0F);
2585 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2586 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2587 %}
2589 enc_class enc_PartialSubtypeCheck()
2590 %{
2591 Register Rrdi = as_Register(RDI_enc); // result register
2592 Register Rrax = as_Register(RAX_enc); // super class
2593 Register Rrcx = as_Register(RCX_enc); // killed
2594 Register Rrsi = as_Register(RSI_enc); // sub class
2595 Label miss;
2596 const bool set_cond_codes = true;
2598 MacroAssembler _masm(&cbuf);
2599 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2600 NULL, &miss,
2601 /*set_cond_codes:*/ true);
2602 if ($primary) {
2603 __ xorptr(Rrdi, Rrdi);
2604 }
2605 __ bind(miss);
2606 %}
2608 enc_class Java_To_Interpreter(method meth)
2609 %{
2610 // CALL Java_To_Interpreter
2611 // This is the instruction starting address for relocation info.
2612 cbuf.set_inst_mark();
2613 $$$emit8$primary;
2614 // CALL directly to the runtime
2615 emit_d32_reloc(cbuf,
2616 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2617 runtime_call_Relocation::spec(),
2618 RELOC_DISP32);
2619 %}
2621 enc_class preserve_SP %{
2622 debug_only(int off0 = cbuf.code_size());
2623 MacroAssembler _masm(&cbuf);
2624 // RBP is preserved across all calls, even compiled calls.
2625 // Use it to preserve RSP in places where the callee might change the SP.
2626 __ movptr(rbp_mh_SP_save, rsp);
2627 debug_only(int off1 = cbuf.code_size());
2628 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
2629 %}
2631 enc_class restore_SP %{
2632 MacroAssembler _masm(&cbuf);
2633 __ movptr(rsp, rbp_mh_SP_save);
2634 %}
2636 enc_class Java_Static_Call(method meth)
2637 %{
2638 // JAVA STATIC CALL
2639 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2640 // determine who we intended to call.
2641 cbuf.set_inst_mark();
2642 $$$emit8$primary;
2644 if (!_method) {
2645 emit_d32_reloc(cbuf,
2646 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2647 runtime_call_Relocation::spec(),
2648 RELOC_DISP32);
2649 } else if (_optimized_virtual) {
2650 emit_d32_reloc(cbuf,
2651 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2652 opt_virtual_call_Relocation::spec(),
2653 RELOC_DISP32);
2654 } else {
2655 emit_d32_reloc(cbuf,
2656 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2657 static_call_Relocation::spec(),
2658 RELOC_DISP32);
2659 }
2660 if (_method) {
2661 // Emit stub for static call
2662 emit_java_to_interp(cbuf);
2663 }
2664 %}
2666 enc_class Java_Dynamic_Call(method meth)
2667 %{
2668 // JAVA DYNAMIC CALL
2669 // !!!!!
2670 // Generate "movq rax, -1", placeholder instruction to load oop-info
2671 // emit_call_dynamic_prologue( cbuf );
2672 cbuf.set_inst_mark();
2674 // movq rax, -1
2675 emit_opcode(cbuf, Assembler::REX_W);
2676 emit_opcode(cbuf, 0xB8 | RAX_enc);
2677 emit_d64_reloc(cbuf,
2678 (int64_t) Universe::non_oop_word(),
2679 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2680 address virtual_call_oop_addr = cbuf.inst_mark();
2681 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2682 // who we intended to call.
2683 cbuf.set_inst_mark();
2684 $$$emit8$primary;
2685 emit_d32_reloc(cbuf,
2686 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2687 virtual_call_Relocation::spec(virtual_call_oop_addr),
2688 RELOC_DISP32);
2689 %}
2691 enc_class Java_Compiled_Call(method meth)
2692 %{
2693 // JAVA COMPILED CALL
2694 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2696 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2697 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2699 // callq *disp(%rax)
2700 cbuf.set_inst_mark();
2701 $$$emit8$primary;
2702 if (disp < 0x80) {
2703 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2704 emit_d8(cbuf, disp); // Displacement
2705 } else {
2706 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2707 emit_d32(cbuf, disp); // Displacement
2708 }
2709 %}
2711 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2712 %{
2713 // SAL, SAR, SHR
2714 int dstenc = $dst$$reg;
2715 if (dstenc >= 8) {
2716 emit_opcode(cbuf, Assembler::REX_B);
2717 dstenc -= 8;
2718 }
2719 $$$emit8$primary;
2720 emit_rm(cbuf, 0x3, $secondary, dstenc);
2721 $$$emit8$shift$$constant;
2722 %}
2724 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2725 %{
2726 // SAL, SAR, SHR
2727 int dstenc = $dst$$reg;
2728 if (dstenc < 8) {
2729 emit_opcode(cbuf, Assembler::REX_W);
2730 } else {
2731 emit_opcode(cbuf, Assembler::REX_WB);
2732 dstenc -= 8;
2733 }
2734 $$$emit8$primary;
2735 emit_rm(cbuf, 0x3, $secondary, dstenc);
2736 $$$emit8$shift$$constant;
2737 %}
2739 enc_class load_immI(rRegI dst, immI src)
2740 %{
2741 int dstenc = $dst$$reg;
2742 if (dstenc >= 8) {
2743 emit_opcode(cbuf, Assembler::REX_B);
2744 dstenc -= 8;
2745 }
2746 emit_opcode(cbuf, 0xB8 | dstenc);
2747 $$$emit32$src$$constant;
2748 %}
2750 enc_class load_immL(rRegL dst, immL src)
2751 %{
2752 int dstenc = $dst$$reg;
2753 if (dstenc < 8) {
2754 emit_opcode(cbuf, Assembler::REX_W);
2755 } else {
2756 emit_opcode(cbuf, Assembler::REX_WB);
2757 dstenc -= 8;
2758 }
2759 emit_opcode(cbuf, 0xB8 | dstenc);
2760 emit_d64(cbuf, $src$$constant);
2761 %}
2763 enc_class load_immUL32(rRegL dst, immUL32 src)
2764 %{
2765 // same as load_immI, but this time we care about zeroes in the high word
2766 int dstenc = $dst$$reg;
2767 if (dstenc >= 8) {
2768 emit_opcode(cbuf, Assembler::REX_B);
2769 dstenc -= 8;
2770 }
2771 emit_opcode(cbuf, 0xB8 | dstenc);
2772 $$$emit32$src$$constant;
2773 %}
2775 enc_class load_immL32(rRegL dst, immL32 src)
2776 %{
2777 int dstenc = $dst$$reg;
2778 if (dstenc < 8) {
2779 emit_opcode(cbuf, Assembler::REX_W);
2780 } else {
2781 emit_opcode(cbuf, Assembler::REX_WB);
2782 dstenc -= 8;
2783 }
2784 emit_opcode(cbuf, 0xC7);
2785 emit_rm(cbuf, 0x03, 0x00, dstenc);
2786 $$$emit32$src$$constant;
2787 %}
2789 enc_class load_immP31(rRegP dst, immP32 src)
2790 %{
2791 // same as load_immI, but this time we care about zeroes in the high word
2792 int dstenc = $dst$$reg;
2793 if (dstenc >= 8) {
2794 emit_opcode(cbuf, Assembler::REX_B);
2795 dstenc -= 8;
2796 }
2797 emit_opcode(cbuf, 0xB8 | dstenc);
2798 $$$emit32$src$$constant;
2799 %}
2801 enc_class load_immP(rRegP dst, immP src)
2802 %{
2803 int dstenc = $dst$$reg;
2804 if (dstenc < 8) {
2805 emit_opcode(cbuf, Assembler::REX_W);
2806 } else {
2807 emit_opcode(cbuf, Assembler::REX_WB);
2808 dstenc -= 8;
2809 }
2810 emit_opcode(cbuf, 0xB8 | dstenc);
2811 // This next line should be generated from ADLC
2812 if ($src->constant_is_oop()) {
2813 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2814 } else {
2815 emit_d64(cbuf, $src$$constant);
2816 }
2817 %}
2819 enc_class load_immF(regF dst, immF con)
2820 %{
2821 // XXX reg_mem doesn't support RIP-relative addressing yet
2822 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2823 emit_float_constant(cbuf, $con$$constant);
2824 %}
2826 enc_class load_immD(regD dst, immD con)
2827 %{
2828 // XXX reg_mem doesn't support RIP-relative addressing yet
2829 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2830 emit_double_constant(cbuf, $con$$constant);
2831 %}
2833 enc_class load_conF (regF dst, immF con) %{ // Load float constant
2834 emit_opcode(cbuf, 0xF3);
2835 if ($dst$$reg >= 8) {
2836 emit_opcode(cbuf, Assembler::REX_R);
2837 }
2838 emit_opcode(cbuf, 0x0F);
2839 emit_opcode(cbuf, 0x10);
2840 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2841 emit_float_constant(cbuf, $con$$constant);
2842 %}
2844 enc_class load_conD (regD dst, immD con) %{ // Load double constant
2845 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2846 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2847 if ($dst$$reg >= 8) {
2848 emit_opcode(cbuf, Assembler::REX_R);
2849 }
2850 emit_opcode(cbuf, 0x0F);
2851 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2852 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2853 emit_double_constant(cbuf, $con$$constant);
2854 %}
2856 // Encode a reg-reg copy. If it is useless, then empty encoding.
2857 enc_class enc_copy(rRegI dst, rRegI src)
2858 %{
2859 encode_copy(cbuf, $dst$$reg, $src$$reg);
2860 %}
2862 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2863 enc_class enc_CopyXD( RegD dst, RegD src ) %{
2864 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2865 %}
2867 enc_class enc_copy_always(rRegI dst, rRegI src)
2868 %{
2869 int srcenc = $src$$reg;
2870 int dstenc = $dst$$reg;
2872 if (dstenc < 8) {
2873 if (srcenc >= 8) {
2874 emit_opcode(cbuf, Assembler::REX_B);
2875 srcenc -= 8;
2876 }
2877 } else {
2878 if (srcenc < 8) {
2879 emit_opcode(cbuf, Assembler::REX_R);
2880 } else {
2881 emit_opcode(cbuf, Assembler::REX_RB);
2882 srcenc -= 8;
2883 }
2884 dstenc -= 8;
2885 }
2887 emit_opcode(cbuf, 0x8B);
2888 emit_rm(cbuf, 0x3, dstenc, srcenc);
2889 %}
2891 enc_class enc_copy_wide(rRegL dst, rRegL src)
2892 %{
2893 int srcenc = $src$$reg;
2894 int dstenc = $dst$$reg;
2896 if (dstenc != srcenc) {
2897 if (dstenc < 8) {
2898 if (srcenc < 8) {
2899 emit_opcode(cbuf, Assembler::REX_W);
2900 } else {
2901 emit_opcode(cbuf, Assembler::REX_WB);
2902 srcenc -= 8;
2903 }
2904 } else {
2905 if (srcenc < 8) {
2906 emit_opcode(cbuf, Assembler::REX_WR);
2907 } else {
2908 emit_opcode(cbuf, Assembler::REX_WRB);
2909 srcenc -= 8;
2910 }
2911 dstenc -= 8;
2912 }
2913 emit_opcode(cbuf, 0x8B);
2914 emit_rm(cbuf, 0x3, dstenc, srcenc);
2915 }
2916 %}
2918 enc_class Con32(immI src)
2919 %{
2920 // Output immediate
2921 $$$emit32$src$$constant;
2922 %}
2924 enc_class Con64(immL src)
2925 %{
2926 // Output immediate
2927 emit_d64($src$$constant);
2928 %}
2930 enc_class Con32F_as_bits(immF src)
2931 %{
2932 // Output Float immediate bits
2933 jfloat jf = $src$$constant;
2934 jint jf_as_bits = jint_cast(jf);
2935 emit_d32(cbuf, jf_as_bits);
2936 %}
2938 enc_class Con16(immI src)
2939 %{
2940 // Output immediate
2941 $$$emit16$src$$constant;
2942 %}
2944 // How is this different from Con32??? XXX
2945 enc_class Con_d32(immI src)
2946 %{
2947 emit_d32(cbuf,$src$$constant);
2948 %}
2950 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2951 // Output immediate memory reference
2952 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2953 emit_d32(cbuf, 0x00);
2954 %}
2956 enc_class jump_enc(rRegL switch_val, rRegI dest) %{
2957 MacroAssembler masm(&cbuf);
2959 Register switch_reg = as_Register($switch_val$$reg);
2960 Register dest_reg = as_Register($dest$$reg);
2961 address table_base = masm.address_table_constant(_index2label);
2963 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2964 // to do that and the compiler is using that register as one it can allocate.
2965 // So we build it all by hand.
2966 // Address index(noreg, switch_reg, Address::times_1);
2967 // ArrayAddress dispatch(table, index);
2969 Address dispatch(dest_reg, switch_reg, Address::times_1);
2971 masm.lea(dest_reg, InternalAddress(table_base));
2972 masm.jmp(dispatch);
2973 %}
2975 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
2976 MacroAssembler masm(&cbuf);
2978 Register switch_reg = as_Register($switch_val$$reg);
2979 Register dest_reg = as_Register($dest$$reg);
2980 address table_base = masm.address_table_constant(_index2label);
2982 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2983 // to do that and the compiler is using that register as one it can allocate.
2984 // So we build it all by hand.
2985 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2986 // ArrayAddress dispatch(table, index);
2988 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2990 masm.lea(dest_reg, InternalAddress(table_base));
2991 masm.jmp(dispatch);
2992 %}
2994 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
2995 MacroAssembler masm(&cbuf);
2997 Register switch_reg = as_Register($switch_val$$reg);
2998 Register dest_reg = as_Register($dest$$reg);
2999 address table_base = masm.address_table_constant(_index2label);
3001 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
3002 // to do that and the compiler is using that register as one it can allocate.
3003 // So we build it all by hand.
3004 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3005 // ArrayAddress dispatch(table, index);
3007 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3008 masm.lea(dest_reg, InternalAddress(table_base));
3009 masm.jmp(dispatch);
3011 %}
3013 enc_class lock_prefix()
3014 %{
3015 if (os::is_MP()) {
3016 emit_opcode(cbuf, 0xF0); // lock
3017 }
3018 %}
3020 enc_class REX_mem(memory mem)
3021 %{
3022 if ($mem$$base >= 8) {
3023 if ($mem$$index < 8) {
3024 emit_opcode(cbuf, Assembler::REX_B);
3025 } else {
3026 emit_opcode(cbuf, Assembler::REX_XB);
3027 }
3028 } else {
3029 if ($mem$$index >= 8) {
3030 emit_opcode(cbuf, Assembler::REX_X);
3031 }
3032 }
3033 %}
3035 enc_class REX_mem_wide(memory mem)
3036 %{
3037 if ($mem$$base >= 8) {
3038 if ($mem$$index < 8) {
3039 emit_opcode(cbuf, Assembler::REX_WB);
3040 } else {
3041 emit_opcode(cbuf, Assembler::REX_WXB);
3042 }
3043 } else {
3044 if ($mem$$index < 8) {
3045 emit_opcode(cbuf, Assembler::REX_W);
3046 } else {
3047 emit_opcode(cbuf, Assembler::REX_WX);
3048 }
3049 }
3050 %}
3052 // for byte regs
3053 enc_class REX_breg(rRegI reg)
3054 %{
3055 if ($reg$$reg >= 4) {
3056 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3057 }
3058 %}
3060 // for byte regs
3061 enc_class REX_reg_breg(rRegI dst, rRegI src)
3062 %{
3063 if ($dst$$reg < 8) {
3064 if ($src$$reg >= 4) {
3065 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3066 }
3067 } else {
3068 if ($src$$reg < 8) {
3069 emit_opcode(cbuf, Assembler::REX_R);
3070 } else {
3071 emit_opcode(cbuf, Assembler::REX_RB);
3072 }
3073 }
3074 %}
3076 // for byte regs
3077 enc_class REX_breg_mem(rRegI reg, memory mem)
3078 %{
3079 if ($reg$$reg < 8) {
3080 if ($mem$$base < 8) {
3081 if ($mem$$index >= 8) {
3082 emit_opcode(cbuf, Assembler::REX_X);
3083 } else if ($reg$$reg >= 4) {
3084 emit_opcode(cbuf, Assembler::REX);
3085 }
3086 } else {
3087 if ($mem$$index < 8) {
3088 emit_opcode(cbuf, Assembler::REX_B);
3089 } else {
3090 emit_opcode(cbuf, Assembler::REX_XB);
3091 }
3092 }
3093 } else {
3094 if ($mem$$base < 8) {
3095 if ($mem$$index < 8) {
3096 emit_opcode(cbuf, Assembler::REX_R);
3097 } else {
3098 emit_opcode(cbuf, Assembler::REX_RX);
3099 }
3100 } else {
3101 if ($mem$$index < 8) {
3102 emit_opcode(cbuf, Assembler::REX_RB);
3103 } else {
3104 emit_opcode(cbuf, Assembler::REX_RXB);
3105 }
3106 }
3107 }
3108 %}
3110 enc_class REX_reg(rRegI reg)
3111 %{
3112 if ($reg$$reg >= 8) {
3113 emit_opcode(cbuf, Assembler::REX_B);
3114 }
3115 %}
3117 enc_class REX_reg_wide(rRegI reg)
3118 %{
3119 if ($reg$$reg < 8) {
3120 emit_opcode(cbuf, Assembler::REX_W);
3121 } else {
3122 emit_opcode(cbuf, Assembler::REX_WB);
3123 }
3124 %}
3126 enc_class REX_reg_reg(rRegI dst, rRegI src)
3127 %{
3128 if ($dst$$reg < 8) {
3129 if ($src$$reg >= 8) {
3130 emit_opcode(cbuf, Assembler::REX_B);
3131 }
3132 } else {
3133 if ($src$$reg < 8) {
3134 emit_opcode(cbuf, Assembler::REX_R);
3135 } else {
3136 emit_opcode(cbuf, Assembler::REX_RB);
3137 }
3138 }
3139 %}
3141 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
3142 %{
3143 if ($dst$$reg < 8) {
3144 if ($src$$reg < 8) {
3145 emit_opcode(cbuf, Assembler::REX_W);
3146 } else {
3147 emit_opcode(cbuf, Assembler::REX_WB);
3148 }
3149 } else {
3150 if ($src$$reg < 8) {
3151 emit_opcode(cbuf, Assembler::REX_WR);
3152 } else {
3153 emit_opcode(cbuf, Assembler::REX_WRB);
3154 }
3155 }
3156 %}
3158 enc_class REX_reg_mem(rRegI reg, memory mem)
3159 %{
3160 if ($reg$$reg < 8) {
3161 if ($mem$$base < 8) {
3162 if ($mem$$index >= 8) {
3163 emit_opcode(cbuf, Assembler::REX_X);
3164 }
3165 } else {
3166 if ($mem$$index < 8) {
3167 emit_opcode(cbuf, Assembler::REX_B);
3168 } else {
3169 emit_opcode(cbuf, Assembler::REX_XB);
3170 }
3171 }
3172 } else {
3173 if ($mem$$base < 8) {
3174 if ($mem$$index < 8) {
3175 emit_opcode(cbuf, Assembler::REX_R);
3176 } else {
3177 emit_opcode(cbuf, Assembler::REX_RX);
3178 }
3179 } else {
3180 if ($mem$$index < 8) {
3181 emit_opcode(cbuf, Assembler::REX_RB);
3182 } else {
3183 emit_opcode(cbuf, Assembler::REX_RXB);
3184 }
3185 }
3186 }
3187 %}
3189 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
3190 %{
3191 if ($reg$$reg < 8) {
3192 if ($mem$$base < 8) {
3193 if ($mem$$index < 8) {
3194 emit_opcode(cbuf, Assembler::REX_W);
3195 } else {
3196 emit_opcode(cbuf, Assembler::REX_WX);
3197 }
3198 } else {
3199 if ($mem$$index < 8) {
3200 emit_opcode(cbuf, Assembler::REX_WB);
3201 } else {
3202 emit_opcode(cbuf, Assembler::REX_WXB);
3203 }
3204 }
3205 } else {
3206 if ($mem$$base < 8) {
3207 if ($mem$$index < 8) {
3208 emit_opcode(cbuf, Assembler::REX_WR);
3209 } else {
3210 emit_opcode(cbuf, Assembler::REX_WRX);
3211 }
3212 } else {
3213 if ($mem$$index < 8) {
3214 emit_opcode(cbuf, Assembler::REX_WRB);
3215 } else {
3216 emit_opcode(cbuf, Assembler::REX_WRXB);
3217 }
3218 }
3219 }
3220 %}
3222 enc_class reg_mem(rRegI ereg, memory mem)
3223 %{
3224 // High registers handle in encode_RegMem
3225 int reg = $ereg$$reg;
3226 int base = $mem$$base;
3227 int index = $mem$$index;
3228 int scale = $mem$$scale;
3229 int disp = $mem$$disp;
3230 bool disp_is_oop = $mem->disp_is_oop();
3232 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
3233 %}
3235 enc_class RM_opc_mem(immI rm_opcode, memory mem)
3236 %{
3237 int rm_byte_opcode = $rm_opcode$$constant;
3239 // High registers handle in encode_RegMem
3240 int base = $mem$$base;
3241 int index = $mem$$index;
3242 int scale = $mem$$scale;
3243 int displace = $mem$$disp;
3245 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
3246 // working with static
3247 // globals
3248 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
3249 disp_is_oop);
3250 %}
3252 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
3253 %{
3254 int reg_encoding = $dst$$reg;
3255 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
3256 int index = 0x04; // 0x04 indicates no index
3257 int scale = 0x00; // 0x00 indicates no scale
3258 int displace = $src1$$constant; // 0x00 indicates no displacement
3259 bool disp_is_oop = false;
3260 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
3261 disp_is_oop);
3262 %}
3264 enc_class neg_reg(rRegI dst)
3265 %{
3266 int dstenc = $dst$$reg;
3267 if (dstenc >= 8) {
3268 emit_opcode(cbuf, Assembler::REX_B);
3269 dstenc -= 8;
3270 }
3271 // NEG $dst
3272 emit_opcode(cbuf, 0xF7);
3273 emit_rm(cbuf, 0x3, 0x03, dstenc);
3274 %}
3276 enc_class neg_reg_wide(rRegI dst)
3277 %{
3278 int dstenc = $dst$$reg;
3279 if (dstenc < 8) {
3280 emit_opcode(cbuf, Assembler::REX_W);
3281 } else {
3282 emit_opcode(cbuf, Assembler::REX_WB);
3283 dstenc -= 8;
3284 }
3285 // NEG $dst
3286 emit_opcode(cbuf, 0xF7);
3287 emit_rm(cbuf, 0x3, 0x03, dstenc);
3288 %}
3290 enc_class setLT_reg(rRegI dst)
3291 %{
3292 int dstenc = $dst$$reg;
3293 if (dstenc >= 8) {
3294 emit_opcode(cbuf, Assembler::REX_B);
3295 dstenc -= 8;
3296 } else if (dstenc >= 4) {
3297 emit_opcode(cbuf, Assembler::REX);
3298 }
3299 // SETLT $dst
3300 emit_opcode(cbuf, 0x0F);
3301 emit_opcode(cbuf, 0x9C);
3302 emit_rm(cbuf, 0x3, 0x0, dstenc);
3303 %}
3305 enc_class setNZ_reg(rRegI dst)
3306 %{
3307 int dstenc = $dst$$reg;
3308 if (dstenc >= 8) {
3309 emit_opcode(cbuf, Assembler::REX_B);
3310 dstenc -= 8;
3311 } else if (dstenc >= 4) {
3312 emit_opcode(cbuf, Assembler::REX);
3313 }
3314 // SETNZ $dst
3315 emit_opcode(cbuf, 0x0F);
3316 emit_opcode(cbuf, 0x95);
3317 emit_rm(cbuf, 0x3, 0x0, dstenc);
3318 %}
3320 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
3321 rcx_RegI tmp)
3322 %{
3323 // cadd_cmpLT
3325 int tmpReg = $tmp$$reg;
3327 int penc = $p$$reg;
3328 int qenc = $q$$reg;
3329 int yenc = $y$$reg;
3331 // subl $p,$q
3332 if (penc < 8) {
3333 if (qenc >= 8) {
3334 emit_opcode(cbuf, Assembler::REX_B);
3335 }
3336 } else {
3337 if (qenc < 8) {
3338 emit_opcode(cbuf, Assembler::REX_R);
3339 } else {
3340 emit_opcode(cbuf, Assembler::REX_RB);
3341 }
3342 }
3343 emit_opcode(cbuf, 0x2B);
3344 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
3346 // sbbl $tmp, $tmp
3347 emit_opcode(cbuf, 0x1B);
3348 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
3350 // andl $tmp, $y
3351 if (yenc >= 8) {
3352 emit_opcode(cbuf, Assembler::REX_B);
3353 }
3354 emit_opcode(cbuf, 0x23);
3355 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
3357 // addl $p,$tmp
3358 if (penc >= 8) {
3359 emit_opcode(cbuf, Assembler::REX_R);
3360 }
3361 emit_opcode(cbuf, 0x03);
3362 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
3363 %}
3365 // Compare the lonogs and set -1, 0, or 1 into dst
3366 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
3367 %{
3368 int src1enc = $src1$$reg;
3369 int src2enc = $src2$$reg;
3370 int dstenc = $dst$$reg;
3372 // cmpq $src1, $src2
3373 if (src1enc < 8) {
3374 if (src2enc < 8) {
3375 emit_opcode(cbuf, Assembler::REX_W);
3376 } else {
3377 emit_opcode(cbuf, Assembler::REX_WB);
3378 }
3379 } else {
3380 if (src2enc < 8) {
3381 emit_opcode(cbuf, Assembler::REX_WR);
3382 } else {
3383 emit_opcode(cbuf, Assembler::REX_WRB);
3384 }
3385 }
3386 emit_opcode(cbuf, 0x3B);
3387 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
3389 // movl $dst, -1
3390 if (dstenc >= 8) {
3391 emit_opcode(cbuf, Assembler::REX_B);
3392 }
3393 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
3394 emit_d32(cbuf, -1);
3396 // jl,s done
3397 emit_opcode(cbuf, 0x7C);
3398 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
3400 // setne $dst
3401 if (dstenc >= 4) {
3402 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
3403 }
3404 emit_opcode(cbuf, 0x0F);
3405 emit_opcode(cbuf, 0x95);
3406 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
3408 // movzbl $dst, $dst
3409 if (dstenc >= 4) {
3410 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
3411 }
3412 emit_opcode(cbuf, 0x0F);
3413 emit_opcode(cbuf, 0xB6);
3414 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
3415 %}
3417 enc_class Push_ResultXD(regD dst) %{
3418 int dstenc = $dst$$reg;
3420 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
3422 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
3423 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
3424 if (dstenc >= 8) {
3425 emit_opcode(cbuf, Assembler::REX_R);
3426 }
3427 emit_opcode (cbuf, 0x0F );
3428 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
3429 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
3431 // add rsp,8
3432 emit_opcode(cbuf, Assembler::REX_W);
3433 emit_opcode(cbuf,0x83);
3434 emit_rm(cbuf,0x3, 0x0, RSP_enc);
3435 emit_d8(cbuf,0x08);
3436 %}
3438 enc_class Push_SrcXD(regD src) %{
3439 int srcenc = $src$$reg;
3441 // subq rsp,#8
3442 emit_opcode(cbuf, Assembler::REX_W);
3443 emit_opcode(cbuf, 0x83);
3444 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3445 emit_d8(cbuf, 0x8);
3447 // movsd [rsp],src
3448 emit_opcode(cbuf, 0xF2);
3449 if (srcenc >= 8) {
3450 emit_opcode(cbuf, Assembler::REX_R);
3451 }
3452 emit_opcode(cbuf, 0x0F);
3453 emit_opcode(cbuf, 0x11);
3454 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
3456 // fldd [rsp]
3457 emit_opcode(cbuf, 0x66);
3458 emit_opcode(cbuf, 0xDD);
3459 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
3460 %}
3463 enc_class movq_ld(regD dst, memory mem) %{
3464 MacroAssembler _masm(&cbuf);
3465 __ movq($dst$$XMMRegister, $mem$$Address);
3466 %}
3468 enc_class movq_st(memory mem, regD src) %{
3469 MacroAssembler _masm(&cbuf);
3470 __ movq($mem$$Address, $src$$XMMRegister);
3471 %}
3473 enc_class pshufd_8x8(regF dst, regF src) %{
3474 MacroAssembler _masm(&cbuf);
3476 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3477 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3478 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3479 %}
3481 enc_class pshufd_4x16(regF dst, regF src) %{
3482 MacroAssembler _masm(&cbuf);
3484 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3485 %}
3487 enc_class pshufd(regD dst, regD src, int mode) %{
3488 MacroAssembler _masm(&cbuf);
3490 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3491 %}
3493 enc_class pxor(regD dst, regD src) %{
3494 MacroAssembler _masm(&cbuf);
3496 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3497 %}
3499 enc_class mov_i2x(regD dst, rRegI src) %{
3500 MacroAssembler _masm(&cbuf);
3502 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3503 %}
3505 // obj: object to lock
3506 // box: box address (header location) -- killed
3507 // tmp: rax -- killed
3508 // scr: rbx -- killed
3509 //
3510 // What follows is a direct transliteration of fast_lock() and fast_unlock()
3511 // from i486.ad. See that file for comments.
3512 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
3513 // use the shorter encoding. (Movl clears the high-order 32-bits).
3516 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
3517 %{
3518 Register objReg = as_Register((int)$obj$$reg);
3519 Register boxReg = as_Register((int)$box$$reg);
3520 Register tmpReg = as_Register($tmp$$reg);
3521 Register scrReg = as_Register($scr$$reg);
3522 MacroAssembler masm(&cbuf);
3524 // Verify uniqueness of register assignments -- necessary but not sufficient
3525 assert (objReg != boxReg && objReg != tmpReg &&
3526 objReg != scrReg && tmpReg != scrReg, "invariant") ;
3528 if (_counters != NULL) {
3529 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3530 }
3531 if (EmitSync & 1) {
3532 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3533 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3534 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
3535 } else
3536 if (EmitSync & 2) {
3537 Label DONE_LABEL;
3538 if (UseBiasedLocking) {
3539 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3540 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3541 }
3542 // QQQ was movl...
3543 masm.movptr(tmpReg, 0x1);
3544 masm.orptr(tmpReg, Address(objReg, 0));
3545 masm.movptr(Address(boxReg, 0), tmpReg);
3546 if (os::is_MP()) {
3547 masm.lock();
3548 }
3549 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3550 masm.jcc(Assembler::equal, DONE_LABEL);
3552 // Recursive locking
3553 masm.subptr(tmpReg, rsp);
3554 masm.andptr(tmpReg, 7 - os::vm_page_size());
3555 masm.movptr(Address(boxReg, 0), tmpReg);
3557 masm.bind(DONE_LABEL);
3558 masm.nop(); // avoid branch to branch
3559 } else {
3560 Label DONE_LABEL, IsInflated, Egress;
3562 masm.movptr(tmpReg, Address(objReg, 0)) ;
3563 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
3564 masm.jcc (Assembler::notZero, IsInflated) ;
3566 // it's stack-locked, biased or neutral
3567 // TODO: optimize markword triage order to reduce the number of
3568 // conditional branches in the most common cases.
3569 // Beware -- there's a subtle invariant that fetch of the markword
3570 // at [FETCH], below, will never observe a biased encoding (*101b).
3571 // If this invariant is not held we'll suffer exclusion (safety) failure.
3573 if (UseBiasedLocking && !UseOptoBiasInlining) {
3574 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
3575 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3576 }
3578 // was q will it destroy high?
3579 masm.orl (tmpReg, 1) ;
3580 masm.movptr(Address(boxReg, 0), tmpReg) ;
3581 if (os::is_MP()) { masm.lock(); }
3582 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3583 if (_counters != NULL) {
3584 masm.cond_inc32(Assembler::equal,
3585 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3586 }
3587 masm.jcc (Assembler::equal, DONE_LABEL);
3589 // Recursive locking
3590 masm.subptr(tmpReg, rsp);
3591 masm.andptr(tmpReg, 7 - os::vm_page_size());
3592 masm.movptr(Address(boxReg, 0), tmpReg);
3593 if (_counters != NULL) {
3594 masm.cond_inc32(Assembler::equal,
3595 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3596 }
3597 masm.jmp (DONE_LABEL) ;
3599 masm.bind (IsInflated) ;
3600 // It's inflated
3602 // TODO: someday avoid the ST-before-CAS penalty by
3603 // relocating (deferring) the following ST.
3604 // We should also think about trying a CAS without having
3605 // fetched _owner. If the CAS is successful we may
3606 // avoid an RTO->RTS upgrade on the $line.
3607 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3608 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3610 masm.mov (boxReg, tmpReg) ;
3611 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3612 masm.testptr(tmpReg, tmpReg) ;
3613 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3615 // It's inflated and appears unlocked
3616 if (os::is_MP()) { masm.lock(); }
3617 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3618 // Intentional fall-through into DONE_LABEL ...
3620 masm.bind (DONE_LABEL) ;
3621 masm.nop () ; // avoid jmp to jmp
3622 }
3623 %}
3625 // obj: object to unlock
3626 // box: box address (displaced header location), killed
3627 // RBX: killed tmp; cannot be obj nor box
3628 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
3629 %{
3631 Register objReg = as_Register($obj$$reg);
3632 Register boxReg = as_Register($box$$reg);
3633 Register tmpReg = as_Register($tmp$$reg);
3634 MacroAssembler masm(&cbuf);
3636 if (EmitSync & 4) {
3637 masm.cmpptr(rsp, 0) ;
3638 } else
3639 if (EmitSync & 8) {
3640 Label DONE_LABEL;
3641 if (UseBiasedLocking) {
3642 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3643 }
3645 // Check whether the displaced header is 0
3646 //(=> recursive unlock)
3647 masm.movptr(tmpReg, Address(boxReg, 0));
3648 masm.testptr(tmpReg, tmpReg);
3649 masm.jcc(Assembler::zero, DONE_LABEL);
3651 // If not recursive lock, reset the header to displaced header
3652 if (os::is_MP()) {
3653 masm.lock();
3654 }
3655 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3656 masm.bind(DONE_LABEL);
3657 masm.nop(); // avoid branch to branch
3658 } else {
3659 Label DONE_LABEL, Stacked, CheckSucc ;
3661 if (UseBiasedLocking && !UseOptoBiasInlining) {
3662 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3663 }
3665 masm.movptr(tmpReg, Address(objReg, 0)) ;
3666 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
3667 masm.jcc (Assembler::zero, DONE_LABEL) ;
3668 masm.testl (tmpReg, 0x02) ;
3669 masm.jcc (Assembler::zero, Stacked) ;
3671 // It's inflated
3672 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3673 masm.xorptr(boxReg, r15_thread) ;
3674 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3675 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3676 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3677 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3678 masm.jcc (Assembler::notZero, CheckSucc) ;
3679 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3680 masm.jmp (DONE_LABEL) ;
3682 if ((EmitSync & 65536) == 0) {
3683 Label LSuccess, LGoSlowPath ;
3684 masm.bind (CheckSucc) ;
3685 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3686 masm.jcc (Assembler::zero, LGoSlowPath) ;
3688 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
3689 // the explicit ST;MEMBAR combination, but masm doesn't currently support
3690 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
3691 // are all faster when the write buffer is populated.
3692 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3693 if (os::is_MP()) {
3694 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
3695 }
3696 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3697 masm.jcc (Assembler::notZero, LSuccess) ;
3699 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
3700 if (os::is_MP()) { masm.lock(); }
3701 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3702 masm.jcc (Assembler::notEqual, LSuccess) ;
3703 // Intentional fall-through into slow-path
3705 masm.bind (LGoSlowPath) ;
3706 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3707 masm.jmp (DONE_LABEL) ;
3709 masm.bind (LSuccess) ;
3710 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
3711 masm.jmp (DONE_LABEL) ;
3712 }
3714 masm.bind (Stacked) ;
3715 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
3716 if (os::is_MP()) { masm.lock(); }
3717 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3719 if (EmitSync & 65536) {
3720 masm.bind (CheckSucc) ;
3721 }
3722 masm.bind(DONE_LABEL);
3723 if (EmitSync & 32768) {
3724 masm.nop(); // avoid branch to branch
3725 }
3726 }
3727 %}
3730 enc_class enc_rethrow()
3731 %{
3732 cbuf.set_inst_mark();
3733 emit_opcode(cbuf, 0xE9); // jmp entry
3734 emit_d32_reloc(cbuf,
3735 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4),
3736 runtime_call_Relocation::spec(),
3737 RELOC_DISP32);
3738 %}
3740 enc_class absF_encoding(regF dst)
3741 %{
3742 int dstenc = $dst$$reg;
3743 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
3745 cbuf.set_inst_mark();
3746 if (dstenc >= 8) {
3747 emit_opcode(cbuf, Assembler::REX_R);
3748 dstenc -= 8;
3749 }
3750 // XXX reg_mem doesn't support RIP-relative addressing yet
3751 emit_opcode(cbuf, 0x0F);
3752 emit_opcode(cbuf, 0x54);
3753 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3754 emit_d32_reloc(cbuf, signmask_address);
3755 %}
3757 enc_class absD_encoding(regD dst)
3758 %{
3759 int dstenc = $dst$$reg;
3760 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
3762 cbuf.set_inst_mark();
3763 emit_opcode(cbuf, 0x66);
3764 if (dstenc >= 8) {
3765 emit_opcode(cbuf, Assembler::REX_R);
3766 dstenc -= 8;
3767 }
3768 // XXX reg_mem doesn't support RIP-relative addressing yet
3769 emit_opcode(cbuf, 0x0F);
3770 emit_opcode(cbuf, 0x54);
3771 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3772 emit_d32_reloc(cbuf, signmask_address);
3773 %}
3775 enc_class negF_encoding(regF dst)
3776 %{
3777 int dstenc = $dst$$reg;
3778 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
3780 cbuf.set_inst_mark();
3781 if (dstenc >= 8) {
3782 emit_opcode(cbuf, Assembler::REX_R);
3783 dstenc -= 8;
3784 }
3785 // XXX reg_mem doesn't support RIP-relative addressing yet
3786 emit_opcode(cbuf, 0x0F);
3787 emit_opcode(cbuf, 0x57);
3788 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3789 emit_d32_reloc(cbuf, signflip_address);
3790 %}
3792 enc_class negD_encoding(regD dst)
3793 %{
3794 int dstenc = $dst$$reg;
3795 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
3797 cbuf.set_inst_mark();
3798 emit_opcode(cbuf, 0x66);
3799 if (dstenc >= 8) {
3800 emit_opcode(cbuf, Assembler::REX_R);
3801 dstenc -= 8;
3802 }
3803 // XXX reg_mem doesn't support RIP-relative addressing yet
3804 emit_opcode(cbuf, 0x0F);
3805 emit_opcode(cbuf, 0x57);
3806 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3807 emit_d32_reloc(cbuf, signflip_address);
3808 %}
3810 enc_class f2i_fixup(rRegI dst, regF src)
3811 %{
3812 int dstenc = $dst$$reg;
3813 int srcenc = $src$$reg;
3815 // cmpl $dst, #0x80000000
3816 if (dstenc >= 8) {
3817 emit_opcode(cbuf, Assembler::REX_B);
3818 }
3819 emit_opcode(cbuf, 0x81);
3820 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
3821 emit_d32(cbuf, 0x80000000);
3823 // jne,s done
3824 emit_opcode(cbuf, 0x75);
3825 if (srcenc < 8 && dstenc < 8) {
3826 emit_d8(cbuf, 0xF);
3827 } else if (srcenc >= 8 && dstenc >= 8) {
3828 emit_d8(cbuf, 0x11);
3829 } else {
3830 emit_d8(cbuf, 0x10);
3831 }
3833 // subq rsp, #8
3834 emit_opcode(cbuf, Assembler::REX_W);
3835 emit_opcode(cbuf, 0x83);
3836 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3837 emit_d8(cbuf, 8);
3839 // movss [rsp], $src
3840 emit_opcode(cbuf, 0xF3);
3841 if (srcenc >= 8) {
3842 emit_opcode(cbuf, Assembler::REX_R);
3843 }
3844 emit_opcode(cbuf, 0x0F);
3845 emit_opcode(cbuf, 0x11);
3846 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3848 // call f2i_fixup
3849 cbuf.set_inst_mark();
3850 emit_opcode(cbuf, 0xE8);
3851 emit_d32_reloc(cbuf,
3852 (int)
3853 (StubRoutines::x86::f2i_fixup() - cbuf.code_end() - 4),
3854 runtime_call_Relocation::spec(),
3855 RELOC_DISP32);
3857 // popq $dst
3858 if (dstenc >= 8) {
3859 emit_opcode(cbuf, Assembler::REX_B);
3860 }
3861 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3863 // done:
3864 %}
3866 enc_class f2l_fixup(rRegL dst, regF src)
3867 %{
3868 int dstenc = $dst$$reg;
3869 int srcenc = $src$$reg;
3870 address const_address = (address) StubRoutines::x86::double_sign_flip();
3872 // cmpq $dst, [0x8000000000000000]
3873 cbuf.set_inst_mark();
3874 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
3875 emit_opcode(cbuf, 0x39);
3876 // XXX reg_mem doesn't support RIP-relative addressing yet
3877 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
3878 emit_d32_reloc(cbuf, const_address);
3881 // jne,s done
3882 emit_opcode(cbuf, 0x75);
3883 if (srcenc < 8 && dstenc < 8) {
3884 emit_d8(cbuf, 0xF);
3885 } else if (srcenc >= 8 && dstenc >= 8) {
3886 emit_d8(cbuf, 0x11);
3887 } else {
3888 emit_d8(cbuf, 0x10);
3889 }
3891 // subq rsp, #8
3892 emit_opcode(cbuf, Assembler::REX_W);
3893 emit_opcode(cbuf, 0x83);
3894 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3895 emit_d8(cbuf, 8);
3897 // movss [rsp], $src
3898 emit_opcode(cbuf, 0xF3);
3899 if (srcenc >= 8) {
3900 emit_opcode(cbuf, Assembler::REX_R);
3901 }
3902 emit_opcode(cbuf, 0x0F);
3903 emit_opcode(cbuf, 0x11);
3904 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3906 // call f2l_fixup
3907 cbuf.set_inst_mark();
3908 emit_opcode(cbuf, 0xE8);
3909 emit_d32_reloc(cbuf,
3910 (int)
3911 (StubRoutines::x86::f2l_fixup() - cbuf.code_end() - 4),
3912 runtime_call_Relocation::spec(),
3913 RELOC_DISP32);
3915 // popq $dst
3916 if (dstenc >= 8) {
3917 emit_opcode(cbuf, Assembler::REX_B);
3918 }
3919 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3921 // done:
3922 %}
3924 enc_class d2i_fixup(rRegI dst, regD src)
3925 %{
3926 int dstenc = $dst$$reg;
3927 int srcenc = $src$$reg;
3929 // cmpl $dst, #0x80000000
3930 if (dstenc >= 8) {
3931 emit_opcode(cbuf, Assembler::REX_B);
3932 }
3933 emit_opcode(cbuf, 0x81);
3934 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
3935 emit_d32(cbuf, 0x80000000);
3937 // jne,s done
3938 emit_opcode(cbuf, 0x75);
3939 if (srcenc < 8 && dstenc < 8) {
3940 emit_d8(cbuf, 0xF);
3941 } else if (srcenc >= 8 && dstenc >= 8) {
3942 emit_d8(cbuf, 0x11);
3943 } else {
3944 emit_d8(cbuf, 0x10);
3945 }
3947 // subq rsp, #8
3948 emit_opcode(cbuf, Assembler::REX_W);
3949 emit_opcode(cbuf, 0x83);
3950 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3951 emit_d8(cbuf, 8);
3953 // movsd [rsp], $src
3954 emit_opcode(cbuf, 0xF2);
3955 if (srcenc >= 8) {
3956 emit_opcode(cbuf, Assembler::REX_R);
3957 }
3958 emit_opcode(cbuf, 0x0F);
3959 emit_opcode(cbuf, 0x11);
3960 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3962 // call d2i_fixup
3963 cbuf.set_inst_mark();
3964 emit_opcode(cbuf, 0xE8);
3965 emit_d32_reloc(cbuf,
3966 (int)
3967 (StubRoutines::x86::d2i_fixup() - cbuf.code_end() - 4),
3968 runtime_call_Relocation::spec(),
3969 RELOC_DISP32);
3971 // popq $dst
3972 if (dstenc >= 8) {
3973 emit_opcode(cbuf, Assembler::REX_B);
3974 }
3975 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3977 // done:
3978 %}
3980 enc_class d2l_fixup(rRegL dst, regD src)
3981 %{
3982 int dstenc = $dst$$reg;
3983 int srcenc = $src$$reg;
3984 address const_address = (address) StubRoutines::x86::double_sign_flip();
3986 // cmpq $dst, [0x8000000000000000]
3987 cbuf.set_inst_mark();
3988 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
3989 emit_opcode(cbuf, 0x39);
3990 // XXX reg_mem doesn't support RIP-relative addressing yet
3991 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
3992 emit_d32_reloc(cbuf, const_address);
3995 // jne,s done
3996 emit_opcode(cbuf, 0x75);
3997 if (srcenc < 8 && dstenc < 8) {
3998 emit_d8(cbuf, 0xF);
3999 } else if (srcenc >= 8 && dstenc >= 8) {
4000 emit_d8(cbuf, 0x11);
4001 } else {
4002 emit_d8(cbuf, 0x10);
4003 }
4005 // subq rsp, #8
4006 emit_opcode(cbuf, Assembler::REX_W);
4007 emit_opcode(cbuf, 0x83);
4008 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4009 emit_d8(cbuf, 8);
4011 // movsd [rsp], $src
4012 emit_opcode(cbuf, 0xF2);
4013 if (srcenc >= 8) {
4014 emit_opcode(cbuf, Assembler::REX_R);
4015 }
4016 emit_opcode(cbuf, 0x0F);
4017 emit_opcode(cbuf, 0x11);
4018 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4020 // call d2l_fixup
4021 cbuf.set_inst_mark();
4022 emit_opcode(cbuf, 0xE8);
4023 emit_d32_reloc(cbuf,
4024 (int)
4025 (StubRoutines::x86::d2l_fixup() - cbuf.code_end() - 4),
4026 runtime_call_Relocation::spec(),
4027 RELOC_DISP32);
4029 // popq $dst
4030 if (dstenc >= 8) {
4031 emit_opcode(cbuf, Assembler::REX_B);
4032 }
4033 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4035 // done:
4036 %}
4038 // Safepoint Poll. This polls the safepoint page, and causes an
4039 // exception if it is not readable. Unfortunately, it kills
4040 // RFLAGS in the process.
4041 enc_class enc_safepoint_poll
4042 %{
4043 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
4044 // XXX reg_mem doesn't support RIP-relative addressing yet
4045 cbuf.set_inst_mark();
4046 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); // XXX
4047 emit_opcode(cbuf, 0x85); // testl
4048 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
4049 // cbuf.inst_mark() is beginning of instruction
4050 emit_d32_reloc(cbuf, os::get_polling_page());
4051 // relocInfo::poll_type,
4052 %}
4053 %}
4057 //----------FRAME--------------------------------------------------------------
4058 // Definition of frame structure and management information.
4059 //
4060 // S T A C K L A Y O U T Allocators stack-slot number
4061 // | (to get allocators register number
4062 // G Owned by | | v add OptoReg::stack0())
4063 // r CALLER | |
4064 // o | +--------+ pad to even-align allocators stack-slot
4065 // w V | pad0 | numbers; owned by CALLER
4066 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4067 // h ^ | in | 5
4068 // | | args | 4 Holes in incoming args owned by SELF
4069 // | | | | 3
4070 // | | +--------+
4071 // V | | old out| Empty on Intel, window on Sparc
4072 // | old |preserve| Must be even aligned.
4073 // | SP-+--------+----> Matcher::_old_SP, even aligned
4074 // | | in | 3 area for Intel ret address
4075 // Owned by |preserve| Empty on Sparc.
4076 // SELF +--------+
4077 // | | pad2 | 2 pad to align old SP
4078 // | +--------+ 1
4079 // | | locks | 0
4080 // | +--------+----> OptoReg::stack0(), even aligned
4081 // | | pad1 | 11 pad to align new SP
4082 // | +--------+
4083 // | | | 10
4084 // | | spills | 9 spills
4085 // V | | 8 (pad0 slot for callee)
4086 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4087 // ^ | out | 7
4088 // | | args | 6 Holes in outgoing args owned by CALLEE
4089 // Owned by +--------+
4090 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4091 // | new |preserve| Must be even-aligned.
4092 // | SP-+--------+----> Matcher::_new_SP, even aligned
4093 // | | |
4094 //
4095 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4096 // known from SELF's arguments and the Java calling convention.
4097 // Region 6-7 is determined per call site.
4098 // Note 2: If the calling convention leaves holes in the incoming argument
4099 // area, those holes are owned by SELF. Holes in the outgoing area
4100 // are owned by the CALLEE. Holes should not be nessecary in the
4101 // incoming area, as the Java calling convention is completely under
4102 // the control of the AD file. Doubles can be sorted and packed to
4103 // avoid holes. Holes in the outgoing arguments may be nessecary for
4104 // varargs C calling conventions.
4105 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4106 // even aligned with pad0 as needed.
4107 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4108 // region 6-11 is even aligned; it may be padded out more so that
4109 // the region from SP to FP meets the minimum stack alignment.
4110 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
4111 // alignment. Region 11, pad1, may be dynamically extended so that
4112 // SP meets the minimum alignment.
4114 frame
4115 %{
4116 // What direction does stack grow in (assumed to be same for C & Java)
4117 stack_direction(TOWARDS_LOW);
4119 // These three registers define part of the calling convention
4120 // between compiled code and the interpreter.
4121 inline_cache_reg(RAX); // Inline Cache Register
4122 interpreter_method_oop_reg(RBX); // Method Oop Register when
4123 // calling interpreter
4125 // Optional: name the operand used by cisc-spilling to access
4126 // [stack_pointer + offset]
4127 cisc_spilling_operand_name(indOffset32);
4129 // Number of stack slots consumed by locking an object
4130 sync_stack_slots(2);
4132 // Compiled code's Frame Pointer
4133 frame_pointer(RSP);
4135 // Interpreter stores its frame pointer in a register which is
4136 // stored to the stack by I2CAdaptors.
4137 // I2CAdaptors convert from interpreted java to compiled java.
4138 interpreter_frame_pointer(RBP);
4140 // Stack alignment requirement
4141 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
4143 // Number of stack slots between incoming argument block and the start of
4144 // a new frame. The PROLOG must add this many slots to the stack. The
4145 // EPILOG must remove this many slots. amd64 needs two slots for
4146 // return address.
4147 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
4149 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4150 // for calls to C. Supports the var-args backing area for register parms.
4151 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
4153 // The after-PROLOG location of the return address. Location of
4154 // return address specifies a type (REG or STACK) and a number
4155 // representing the register number (i.e. - use a register name) or
4156 // stack slot.
4157 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4158 // Otherwise, it is above the locks and verification slot and alignment word
4159 return_addr(STACK - 2 +
4160 round_to(2 + 2 * VerifyStackAtCalls +
4161 Compile::current()->fixed_slots(),
4162 WordsPerLong * 2));
4164 // Body of function which returns an integer array locating
4165 // arguments either in registers or in stack slots. Passed an array
4166 // of ideal registers called "sig" and a "length" count. Stack-slot
4167 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4168 // arguments for a CALLEE. Incoming stack arguments are
4169 // automatically biased by the preserve_stack_slots field above.
4171 calling_convention
4172 %{
4173 // No difference between ingoing/outgoing just pass false
4174 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4175 %}
4177 c_calling_convention
4178 %{
4179 // This is obviously always outgoing
4180 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4181 %}
4183 // Location of compiled Java return values. Same as C for now.
4184 return_value
4185 %{
4186 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
4187 "only return normal values");
4189 static const int lo[Op_RegL + 1] = {
4190 0,
4191 0,
4192 RAX_num, // Op_RegN
4193 RAX_num, // Op_RegI
4194 RAX_num, // Op_RegP
4195 XMM0_num, // Op_RegF
4196 XMM0_num, // Op_RegD
4197 RAX_num // Op_RegL
4198 };
4199 static const int hi[Op_RegL + 1] = {
4200 0,
4201 0,
4202 OptoReg::Bad, // Op_RegN
4203 OptoReg::Bad, // Op_RegI
4204 RAX_H_num, // Op_RegP
4205 OptoReg::Bad, // Op_RegF
4206 XMM0_H_num, // Op_RegD
4207 RAX_H_num // Op_RegL
4208 };
4209 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
4210 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
4211 %}
4212 %}
4214 //----------ATTRIBUTES---------------------------------------------------------
4215 //----------Operand Attributes-------------------------------------------------
4216 op_attrib op_cost(0); // Required cost attribute
4218 //----------Instruction Attributes---------------------------------------------
4219 ins_attrib ins_cost(100); // Required cost attribute
4220 ins_attrib ins_size(8); // Required size attribute (in bits)
4221 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4222 ins_attrib ins_short_branch(0); // Required flag: is this instruction
4223 // a non-matching short branch variant
4224 // of some long branch?
4225 ins_attrib ins_alignment(1); // Required alignment attribute (must
4226 // be a power of 2) specifies the
4227 // alignment that some part of the
4228 // instruction (not necessarily the
4229 // start) requires. If > 1, a
4230 // compute_padding() function must be
4231 // provided for the instruction
4233 //----------OPERANDS-----------------------------------------------------------
4234 // Operand definitions must precede instruction definitions for correct parsing
4235 // in the ADLC because operands constitute user defined types which are used in
4236 // instruction definitions.
4238 //----------Simple Operands----------------------------------------------------
4239 // Immediate Operands
4240 // Integer Immediate
4241 operand immI()
4242 %{
4243 match(ConI);
4245 op_cost(10);
4246 format %{ %}
4247 interface(CONST_INTER);
4248 %}
4250 // Constant for test vs zero
4251 operand immI0()
4252 %{
4253 predicate(n->get_int() == 0);
4254 match(ConI);
4256 op_cost(0);
4257 format %{ %}
4258 interface(CONST_INTER);
4259 %}
4261 // Constant for increment
4262 operand immI1()
4263 %{
4264 predicate(n->get_int() == 1);
4265 match(ConI);
4267 op_cost(0);
4268 format %{ %}
4269 interface(CONST_INTER);
4270 %}
4272 // Constant for decrement
4273 operand immI_M1()
4274 %{
4275 predicate(n->get_int() == -1);
4276 match(ConI);
4278 op_cost(0);
4279 format %{ %}
4280 interface(CONST_INTER);
4281 %}
4283 // Valid scale values for addressing modes
4284 operand immI2()
4285 %{
4286 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4287 match(ConI);
4289 format %{ %}
4290 interface(CONST_INTER);
4291 %}
4293 operand immI8()
4294 %{
4295 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
4296 match(ConI);
4298 op_cost(5);
4299 format %{ %}
4300 interface(CONST_INTER);
4301 %}
4303 operand immI16()
4304 %{
4305 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4306 match(ConI);
4308 op_cost(10);
4309 format %{ %}
4310 interface(CONST_INTER);
4311 %}
4313 // Constant for long shifts
4314 operand immI_32()
4315 %{
4316 predicate( n->get_int() == 32 );
4317 match(ConI);
4319 op_cost(0);
4320 format %{ %}
4321 interface(CONST_INTER);
4322 %}
4324 // Constant for long shifts
4325 operand immI_64()
4326 %{
4327 predicate( n->get_int() == 64 );
4328 match(ConI);
4330 op_cost(0);
4331 format %{ %}
4332 interface(CONST_INTER);
4333 %}
4335 // Pointer Immediate
4336 operand immP()
4337 %{
4338 match(ConP);
4340 op_cost(10);
4341 format %{ %}
4342 interface(CONST_INTER);
4343 %}
4345 // NULL Pointer Immediate
4346 operand immP0()
4347 %{
4348 predicate(n->get_ptr() == 0);
4349 match(ConP);
4351 op_cost(5);
4352 format %{ %}
4353 interface(CONST_INTER);
4354 %}
4356 // Pointer Immediate
4357 operand immN() %{
4358 match(ConN);
4360 op_cost(10);
4361 format %{ %}
4362 interface(CONST_INTER);
4363 %}
4365 // NULL Pointer Immediate
4366 operand immN0() %{
4367 predicate(n->get_narrowcon() == 0);
4368 match(ConN);
4370 op_cost(5);
4371 format %{ %}
4372 interface(CONST_INTER);
4373 %}
4375 operand immP31()
4376 %{
4377 predicate(!n->as_Type()->type()->isa_oopptr()
4378 && (n->get_ptr() >> 31) == 0);
4379 match(ConP);
4381 op_cost(5);
4382 format %{ %}
4383 interface(CONST_INTER);
4384 %}
4387 // Long Immediate
4388 operand immL()
4389 %{
4390 match(ConL);
4392 op_cost(20);
4393 format %{ %}
4394 interface(CONST_INTER);
4395 %}
4397 // Long Immediate 8-bit
4398 operand immL8()
4399 %{
4400 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
4401 match(ConL);
4403 op_cost(5);
4404 format %{ %}
4405 interface(CONST_INTER);
4406 %}
4408 // Long Immediate 32-bit unsigned
4409 operand immUL32()
4410 %{
4411 predicate(n->get_long() == (unsigned int) (n->get_long()));
4412 match(ConL);
4414 op_cost(10);
4415 format %{ %}
4416 interface(CONST_INTER);
4417 %}
4419 // Long Immediate 32-bit signed
4420 operand immL32()
4421 %{
4422 predicate(n->get_long() == (int) (n->get_long()));
4423 match(ConL);
4425 op_cost(15);
4426 format %{ %}
4427 interface(CONST_INTER);
4428 %}
4430 // Long Immediate zero
4431 operand immL0()
4432 %{
4433 predicate(n->get_long() == 0L);
4434 match(ConL);
4436 op_cost(10);
4437 format %{ %}
4438 interface(CONST_INTER);
4439 %}
4441 // Constant for increment
4442 operand immL1()
4443 %{
4444 predicate(n->get_long() == 1);
4445 match(ConL);
4447 format %{ %}
4448 interface(CONST_INTER);
4449 %}
4451 // Constant for decrement
4452 operand immL_M1()
4453 %{
4454 predicate(n->get_long() == -1);
4455 match(ConL);
4457 format %{ %}
4458 interface(CONST_INTER);
4459 %}
4461 // Long Immediate: the value 10
4462 operand immL10()
4463 %{
4464 predicate(n->get_long() == 10);
4465 match(ConL);
4467 format %{ %}
4468 interface(CONST_INTER);
4469 %}
4471 // Long immediate from 0 to 127.
4472 // Used for a shorter form of long mul by 10.
4473 operand immL_127()
4474 %{
4475 predicate(0 <= n->get_long() && n->get_long() < 0x80);
4476 match(ConL);
4478 op_cost(10);
4479 format %{ %}
4480 interface(CONST_INTER);
4481 %}
4483 // Long Immediate: low 32-bit mask
4484 operand immL_32bits()
4485 %{
4486 predicate(n->get_long() == 0xFFFFFFFFL);
4487 match(ConL);
4488 op_cost(20);
4490 format %{ %}
4491 interface(CONST_INTER);
4492 %}
4494 // Float Immediate zero
4495 operand immF0()
4496 %{
4497 predicate(jint_cast(n->getf()) == 0);
4498 match(ConF);
4500 op_cost(5);
4501 format %{ %}
4502 interface(CONST_INTER);
4503 %}
4505 // Float Immediate
4506 operand immF()
4507 %{
4508 match(ConF);
4510 op_cost(15);
4511 format %{ %}
4512 interface(CONST_INTER);
4513 %}
4515 // Double Immediate zero
4516 operand immD0()
4517 %{
4518 predicate(jlong_cast(n->getd()) == 0);
4519 match(ConD);
4521 op_cost(5);
4522 format %{ %}
4523 interface(CONST_INTER);
4524 %}
4526 // Double Immediate
4527 operand immD()
4528 %{
4529 match(ConD);
4531 op_cost(15);
4532 format %{ %}
4533 interface(CONST_INTER);
4534 %}
4536 // Immediates for special shifts (sign extend)
4538 // Constants for increment
4539 operand immI_16()
4540 %{
4541 predicate(n->get_int() == 16);
4542 match(ConI);
4544 format %{ %}
4545 interface(CONST_INTER);
4546 %}
4548 operand immI_24()
4549 %{
4550 predicate(n->get_int() == 24);
4551 match(ConI);
4553 format %{ %}
4554 interface(CONST_INTER);
4555 %}
4557 // Constant for byte-wide masking
4558 operand immI_255()
4559 %{
4560 predicate(n->get_int() == 255);
4561 match(ConI);
4563 format %{ %}
4564 interface(CONST_INTER);
4565 %}
4567 // Constant for short-wide masking
4568 operand immI_65535()
4569 %{
4570 predicate(n->get_int() == 65535);
4571 match(ConI);
4573 format %{ %}
4574 interface(CONST_INTER);
4575 %}
4577 // Constant for byte-wide masking
4578 operand immL_255()
4579 %{
4580 predicate(n->get_long() == 255);
4581 match(ConL);
4583 format %{ %}
4584 interface(CONST_INTER);
4585 %}
4587 // Constant for short-wide masking
4588 operand immL_65535()
4589 %{
4590 predicate(n->get_long() == 65535);
4591 match(ConL);
4593 format %{ %}
4594 interface(CONST_INTER);
4595 %}
4597 // Register Operands
4598 // Integer Register
4599 operand rRegI()
4600 %{
4601 constraint(ALLOC_IN_RC(int_reg));
4602 match(RegI);
4604 match(rax_RegI);
4605 match(rbx_RegI);
4606 match(rcx_RegI);
4607 match(rdx_RegI);
4608 match(rdi_RegI);
4610 format %{ %}
4611 interface(REG_INTER);
4612 %}
4614 // Special Registers
4615 operand rax_RegI()
4616 %{
4617 constraint(ALLOC_IN_RC(int_rax_reg));
4618 match(RegI);
4619 match(rRegI);
4621 format %{ "RAX" %}
4622 interface(REG_INTER);
4623 %}
4625 // Special Registers
4626 operand rbx_RegI()
4627 %{
4628 constraint(ALLOC_IN_RC(int_rbx_reg));
4629 match(RegI);
4630 match(rRegI);
4632 format %{ "RBX" %}
4633 interface(REG_INTER);
4634 %}
4636 operand rcx_RegI()
4637 %{
4638 constraint(ALLOC_IN_RC(int_rcx_reg));
4639 match(RegI);
4640 match(rRegI);
4642 format %{ "RCX" %}
4643 interface(REG_INTER);
4644 %}
4646 operand rdx_RegI()
4647 %{
4648 constraint(ALLOC_IN_RC(int_rdx_reg));
4649 match(RegI);
4650 match(rRegI);
4652 format %{ "RDX" %}
4653 interface(REG_INTER);
4654 %}
4656 operand rdi_RegI()
4657 %{
4658 constraint(ALLOC_IN_RC(int_rdi_reg));
4659 match(RegI);
4660 match(rRegI);
4662 format %{ "RDI" %}
4663 interface(REG_INTER);
4664 %}
4666 operand no_rcx_RegI()
4667 %{
4668 constraint(ALLOC_IN_RC(int_no_rcx_reg));
4669 match(RegI);
4670 match(rax_RegI);
4671 match(rbx_RegI);
4672 match(rdx_RegI);
4673 match(rdi_RegI);
4675 format %{ %}
4676 interface(REG_INTER);
4677 %}
4679 operand no_rax_rdx_RegI()
4680 %{
4681 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
4682 match(RegI);
4683 match(rbx_RegI);
4684 match(rcx_RegI);
4685 match(rdi_RegI);
4687 format %{ %}
4688 interface(REG_INTER);
4689 %}
4691 // Pointer Register
4692 operand any_RegP()
4693 %{
4694 constraint(ALLOC_IN_RC(any_reg));
4695 match(RegP);
4696 match(rax_RegP);
4697 match(rbx_RegP);
4698 match(rdi_RegP);
4699 match(rsi_RegP);
4700 match(rbp_RegP);
4701 match(r15_RegP);
4702 match(rRegP);
4704 format %{ %}
4705 interface(REG_INTER);
4706 %}
4708 operand rRegP()
4709 %{
4710 constraint(ALLOC_IN_RC(ptr_reg));
4711 match(RegP);
4712 match(rax_RegP);
4713 match(rbx_RegP);
4714 match(rdi_RegP);
4715 match(rsi_RegP);
4716 match(rbp_RegP);
4717 match(r15_RegP); // See Q&A below about r15_RegP.
4719 format %{ %}
4720 interface(REG_INTER);
4721 %}
4723 operand rRegN() %{
4724 constraint(ALLOC_IN_RC(int_reg));
4725 match(RegN);
4727 format %{ %}
4728 interface(REG_INTER);
4729 %}
4731 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
4732 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
4733 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
4734 // The output of an instruction is controlled by the allocator, which respects
4735 // register class masks, not match rules. Unless an instruction mentions
4736 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
4737 // by the allocator as an input.
4739 operand no_rax_RegP()
4740 %{
4741 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
4742 match(RegP);
4743 match(rbx_RegP);
4744 match(rsi_RegP);
4745 match(rdi_RegP);
4747 format %{ %}
4748 interface(REG_INTER);
4749 %}
4751 operand no_rbp_RegP()
4752 %{
4753 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
4754 match(RegP);
4755 match(rbx_RegP);
4756 match(rsi_RegP);
4757 match(rdi_RegP);
4759 format %{ %}
4760 interface(REG_INTER);
4761 %}
4763 operand no_rax_rbx_RegP()
4764 %{
4765 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
4766 match(RegP);
4767 match(rsi_RegP);
4768 match(rdi_RegP);
4770 format %{ %}
4771 interface(REG_INTER);
4772 %}
4774 // Special Registers
4775 // Return a pointer value
4776 operand rax_RegP()
4777 %{
4778 constraint(ALLOC_IN_RC(ptr_rax_reg));
4779 match(RegP);
4780 match(rRegP);
4782 format %{ %}
4783 interface(REG_INTER);
4784 %}
4786 // Special Registers
4787 // Return a compressed pointer value
4788 operand rax_RegN()
4789 %{
4790 constraint(ALLOC_IN_RC(int_rax_reg));
4791 match(RegN);
4792 match(rRegN);
4794 format %{ %}
4795 interface(REG_INTER);
4796 %}
4798 // Used in AtomicAdd
4799 operand rbx_RegP()
4800 %{
4801 constraint(ALLOC_IN_RC(ptr_rbx_reg));
4802 match(RegP);
4803 match(rRegP);
4805 format %{ %}
4806 interface(REG_INTER);
4807 %}
4809 operand rsi_RegP()
4810 %{
4811 constraint(ALLOC_IN_RC(ptr_rsi_reg));
4812 match(RegP);
4813 match(rRegP);
4815 format %{ %}
4816 interface(REG_INTER);
4817 %}
4819 // Used in rep stosq
4820 operand rdi_RegP()
4821 %{
4822 constraint(ALLOC_IN_RC(ptr_rdi_reg));
4823 match(RegP);
4824 match(rRegP);
4826 format %{ %}
4827 interface(REG_INTER);
4828 %}
4830 operand rbp_RegP()
4831 %{
4832 constraint(ALLOC_IN_RC(ptr_rbp_reg));
4833 match(RegP);
4834 match(rRegP);
4836 format %{ %}
4837 interface(REG_INTER);
4838 %}
4840 operand r15_RegP()
4841 %{
4842 constraint(ALLOC_IN_RC(ptr_r15_reg));
4843 match(RegP);
4844 match(rRegP);
4846 format %{ %}
4847 interface(REG_INTER);
4848 %}
4850 operand rRegL()
4851 %{
4852 constraint(ALLOC_IN_RC(long_reg));
4853 match(RegL);
4854 match(rax_RegL);
4855 match(rdx_RegL);
4857 format %{ %}
4858 interface(REG_INTER);
4859 %}
4861 // Special Registers
4862 operand no_rax_rdx_RegL()
4863 %{
4864 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
4865 match(RegL);
4866 match(rRegL);
4868 format %{ %}
4869 interface(REG_INTER);
4870 %}
4872 operand no_rax_RegL()
4873 %{
4874 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
4875 match(RegL);
4876 match(rRegL);
4877 match(rdx_RegL);
4879 format %{ %}
4880 interface(REG_INTER);
4881 %}
4883 operand no_rcx_RegL()
4884 %{
4885 constraint(ALLOC_IN_RC(long_no_rcx_reg));
4886 match(RegL);
4887 match(rRegL);
4889 format %{ %}
4890 interface(REG_INTER);
4891 %}
4893 operand rax_RegL()
4894 %{
4895 constraint(ALLOC_IN_RC(long_rax_reg));
4896 match(RegL);
4897 match(rRegL);
4899 format %{ "RAX" %}
4900 interface(REG_INTER);
4901 %}
4903 operand rcx_RegL()
4904 %{
4905 constraint(ALLOC_IN_RC(long_rcx_reg));
4906 match(RegL);
4907 match(rRegL);
4909 format %{ %}
4910 interface(REG_INTER);
4911 %}
4913 operand rdx_RegL()
4914 %{
4915 constraint(ALLOC_IN_RC(long_rdx_reg));
4916 match(RegL);
4917 match(rRegL);
4919 format %{ %}
4920 interface(REG_INTER);
4921 %}
4923 // Flags register, used as output of compare instructions
4924 operand rFlagsReg()
4925 %{
4926 constraint(ALLOC_IN_RC(int_flags));
4927 match(RegFlags);
4929 format %{ "RFLAGS" %}
4930 interface(REG_INTER);
4931 %}
4933 // Flags register, used as output of FLOATING POINT compare instructions
4934 operand rFlagsRegU()
4935 %{
4936 constraint(ALLOC_IN_RC(int_flags));
4937 match(RegFlags);
4939 format %{ "RFLAGS_U" %}
4940 interface(REG_INTER);
4941 %}
4943 operand rFlagsRegUCF() %{
4944 constraint(ALLOC_IN_RC(int_flags));
4945 match(RegFlags);
4946 predicate(false);
4948 format %{ "RFLAGS_U_CF" %}
4949 interface(REG_INTER);
4950 %}
4952 // Float register operands
4953 operand regF()
4954 %{
4955 constraint(ALLOC_IN_RC(float_reg));
4956 match(RegF);
4958 format %{ %}
4959 interface(REG_INTER);
4960 %}
4962 // Double register operands
4963 operand regD()
4964 %{
4965 constraint(ALLOC_IN_RC(double_reg));
4966 match(RegD);
4968 format %{ %}
4969 interface(REG_INTER);
4970 %}
4973 //----------Memory Operands----------------------------------------------------
4974 // Direct Memory Operand
4975 // operand direct(immP addr)
4976 // %{
4977 // match(addr);
4979 // format %{ "[$addr]" %}
4980 // interface(MEMORY_INTER) %{
4981 // base(0xFFFFFFFF);
4982 // index(0x4);
4983 // scale(0x0);
4984 // disp($addr);
4985 // %}
4986 // %}
4988 // Indirect Memory Operand
4989 operand indirect(any_RegP reg)
4990 %{
4991 constraint(ALLOC_IN_RC(ptr_reg));
4992 match(reg);
4994 format %{ "[$reg]" %}
4995 interface(MEMORY_INTER) %{
4996 base($reg);
4997 index(0x4);
4998 scale(0x0);
4999 disp(0x0);
5000 %}
5001 %}
5003 // Indirect Memory Plus Short Offset Operand
5004 operand indOffset8(any_RegP reg, immL8 off)
5005 %{
5006 constraint(ALLOC_IN_RC(ptr_reg));
5007 match(AddP reg off);
5009 format %{ "[$reg + $off (8-bit)]" %}
5010 interface(MEMORY_INTER) %{
5011 base($reg);
5012 index(0x4);
5013 scale(0x0);
5014 disp($off);
5015 %}
5016 %}
5018 // Indirect Memory Plus Long Offset Operand
5019 operand indOffset32(any_RegP reg, immL32 off)
5020 %{
5021 constraint(ALLOC_IN_RC(ptr_reg));
5022 match(AddP reg off);
5024 format %{ "[$reg + $off (32-bit)]" %}
5025 interface(MEMORY_INTER) %{
5026 base($reg);
5027 index(0x4);
5028 scale(0x0);
5029 disp($off);
5030 %}
5031 %}
5033 // Indirect Memory Plus Index Register Plus Offset Operand
5034 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
5035 %{
5036 constraint(ALLOC_IN_RC(ptr_reg));
5037 match(AddP (AddP reg lreg) off);
5039 op_cost(10);
5040 format %{"[$reg + $off + $lreg]" %}
5041 interface(MEMORY_INTER) %{
5042 base($reg);
5043 index($lreg);
5044 scale(0x0);
5045 disp($off);
5046 %}
5047 %}
5049 // Indirect Memory Plus Index Register Plus Offset Operand
5050 operand indIndex(any_RegP reg, rRegL lreg)
5051 %{
5052 constraint(ALLOC_IN_RC(ptr_reg));
5053 match(AddP reg lreg);
5055 op_cost(10);
5056 format %{"[$reg + $lreg]" %}
5057 interface(MEMORY_INTER) %{
5058 base($reg);
5059 index($lreg);
5060 scale(0x0);
5061 disp(0x0);
5062 %}
5063 %}
5065 // Indirect Memory Times Scale Plus Index Register
5066 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
5067 %{
5068 constraint(ALLOC_IN_RC(ptr_reg));
5069 match(AddP reg (LShiftL lreg scale));
5071 op_cost(10);
5072 format %{"[$reg + $lreg << $scale]" %}
5073 interface(MEMORY_INTER) %{
5074 base($reg);
5075 index($lreg);
5076 scale($scale);
5077 disp(0x0);
5078 %}
5079 %}
5081 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5082 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
5083 %{
5084 constraint(ALLOC_IN_RC(ptr_reg));
5085 match(AddP (AddP reg (LShiftL lreg scale)) off);
5087 op_cost(10);
5088 format %{"[$reg + $off + $lreg << $scale]" %}
5089 interface(MEMORY_INTER) %{
5090 base($reg);
5091 index($lreg);
5092 scale($scale);
5093 disp($off);
5094 %}
5095 %}
5097 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
5098 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
5099 %{
5100 constraint(ALLOC_IN_RC(ptr_reg));
5101 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5102 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
5104 op_cost(10);
5105 format %{"[$reg + $off + $idx << $scale]" %}
5106 interface(MEMORY_INTER) %{
5107 base($reg);
5108 index($idx);
5109 scale($scale);
5110 disp($off);
5111 %}
5112 %}
5114 // Indirect Narrow Oop Plus Offset Operand
5115 // Note: x86 architecture doesn't support "scale * index + offset" without a base
5116 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
5117 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
5118 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
5119 constraint(ALLOC_IN_RC(ptr_reg));
5120 match(AddP (DecodeN reg) off);
5122 op_cost(10);
5123 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
5124 interface(MEMORY_INTER) %{
5125 base(0xc); // R12
5126 index($reg);
5127 scale(0x3);
5128 disp($off);
5129 %}
5130 %}
5132 // Indirect Memory Operand
5133 operand indirectNarrow(rRegN reg)
5134 %{
5135 predicate(Universe::narrow_oop_shift() == 0);
5136 constraint(ALLOC_IN_RC(ptr_reg));
5137 match(DecodeN reg);
5139 format %{ "[$reg]" %}
5140 interface(MEMORY_INTER) %{
5141 base($reg);
5142 index(0x4);
5143 scale(0x0);
5144 disp(0x0);
5145 %}
5146 %}
5148 // Indirect Memory Plus Short Offset Operand
5149 operand indOffset8Narrow(rRegN reg, immL8 off)
5150 %{
5151 predicate(Universe::narrow_oop_shift() == 0);
5152 constraint(ALLOC_IN_RC(ptr_reg));
5153 match(AddP (DecodeN reg) off);
5155 format %{ "[$reg + $off (8-bit)]" %}
5156 interface(MEMORY_INTER) %{
5157 base($reg);
5158 index(0x4);
5159 scale(0x0);
5160 disp($off);
5161 %}
5162 %}
5164 // Indirect Memory Plus Long Offset Operand
5165 operand indOffset32Narrow(rRegN reg, immL32 off)
5166 %{
5167 predicate(Universe::narrow_oop_shift() == 0);
5168 constraint(ALLOC_IN_RC(ptr_reg));
5169 match(AddP (DecodeN reg) off);
5171 format %{ "[$reg + $off (32-bit)]" %}
5172 interface(MEMORY_INTER) %{
5173 base($reg);
5174 index(0x4);
5175 scale(0x0);
5176 disp($off);
5177 %}
5178 %}
5180 // Indirect Memory Plus Index Register Plus Offset Operand
5181 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
5182 %{
5183 predicate(Universe::narrow_oop_shift() == 0);
5184 constraint(ALLOC_IN_RC(ptr_reg));
5185 match(AddP (AddP (DecodeN reg) lreg) off);
5187 op_cost(10);
5188 format %{"[$reg + $off + $lreg]" %}
5189 interface(MEMORY_INTER) %{
5190 base($reg);
5191 index($lreg);
5192 scale(0x0);
5193 disp($off);
5194 %}
5195 %}
5197 // Indirect Memory Plus Index Register Plus Offset Operand
5198 operand indIndexNarrow(rRegN reg, rRegL lreg)
5199 %{
5200 predicate(Universe::narrow_oop_shift() == 0);
5201 constraint(ALLOC_IN_RC(ptr_reg));
5202 match(AddP (DecodeN reg) lreg);
5204 op_cost(10);
5205 format %{"[$reg + $lreg]" %}
5206 interface(MEMORY_INTER) %{
5207 base($reg);
5208 index($lreg);
5209 scale(0x0);
5210 disp(0x0);
5211 %}
5212 %}
5214 // Indirect Memory Times Scale Plus Index Register
5215 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
5216 %{
5217 predicate(Universe::narrow_oop_shift() == 0);
5218 constraint(ALLOC_IN_RC(ptr_reg));
5219 match(AddP (DecodeN reg) (LShiftL lreg scale));
5221 op_cost(10);
5222 format %{"[$reg + $lreg << $scale]" %}
5223 interface(MEMORY_INTER) %{
5224 base($reg);
5225 index($lreg);
5226 scale($scale);
5227 disp(0x0);
5228 %}
5229 %}
5231 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5232 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
5233 %{
5234 predicate(Universe::narrow_oop_shift() == 0);
5235 constraint(ALLOC_IN_RC(ptr_reg));
5236 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
5238 op_cost(10);
5239 format %{"[$reg + $off + $lreg << $scale]" %}
5240 interface(MEMORY_INTER) %{
5241 base($reg);
5242 index($lreg);
5243 scale($scale);
5244 disp($off);
5245 %}
5246 %}
5248 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
5249 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
5250 %{
5251 constraint(ALLOC_IN_RC(ptr_reg));
5252 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5253 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
5255 op_cost(10);
5256 format %{"[$reg + $off + $idx << $scale]" %}
5257 interface(MEMORY_INTER) %{
5258 base($reg);
5259 index($idx);
5260 scale($scale);
5261 disp($off);
5262 %}
5263 %}
5266 //----------Special Memory Operands--------------------------------------------
5267 // Stack Slot Operand - This operand is used for loading and storing temporary
5268 // values on the stack where a match requires a value to
5269 // flow through memory.
5270 operand stackSlotP(sRegP reg)
5271 %{
5272 constraint(ALLOC_IN_RC(stack_slots));
5273 // No match rule because this operand is only generated in matching
5275 format %{ "[$reg]" %}
5276 interface(MEMORY_INTER) %{
5277 base(0x4); // RSP
5278 index(0x4); // No Index
5279 scale(0x0); // No Scale
5280 disp($reg); // Stack Offset
5281 %}
5282 %}
5284 operand stackSlotI(sRegI reg)
5285 %{
5286 constraint(ALLOC_IN_RC(stack_slots));
5287 // No match rule because this operand is only generated in matching
5289 format %{ "[$reg]" %}
5290 interface(MEMORY_INTER) %{
5291 base(0x4); // RSP
5292 index(0x4); // No Index
5293 scale(0x0); // No Scale
5294 disp($reg); // Stack Offset
5295 %}
5296 %}
5298 operand stackSlotF(sRegF reg)
5299 %{
5300 constraint(ALLOC_IN_RC(stack_slots));
5301 // No match rule because this operand is only generated in matching
5303 format %{ "[$reg]" %}
5304 interface(MEMORY_INTER) %{
5305 base(0x4); // RSP
5306 index(0x4); // No Index
5307 scale(0x0); // No Scale
5308 disp($reg); // Stack Offset
5309 %}
5310 %}
5312 operand stackSlotD(sRegD reg)
5313 %{
5314 constraint(ALLOC_IN_RC(stack_slots));
5315 // No match rule because this operand is only generated in matching
5317 format %{ "[$reg]" %}
5318 interface(MEMORY_INTER) %{
5319 base(0x4); // RSP
5320 index(0x4); // No Index
5321 scale(0x0); // No Scale
5322 disp($reg); // Stack Offset
5323 %}
5324 %}
5325 operand stackSlotL(sRegL reg)
5326 %{
5327 constraint(ALLOC_IN_RC(stack_slots));
5328 // No match rule because this operand is only generated in matching
5330 format %{ "[$reg]" %}
5331 interface(MEMORY_INTER) %{
5332 base(0x4); // RSP
5333 index(0x4); // No Index
5334 scale(0x0); // No Scale
5335 disp($reg); // Stack Offset
5336 %}
5337 %}
5339 //----------Conditional Branch Operands----------------------------------------
5340 // Comparison Op - This is the operation of the comparison, and is limited to
5341 // the following set of codes:
5342 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5343 //
5344 // Other attributes of the comparison, such as unsignedness, are specified
5345 // by the comparison instruction that sets a condition code flags register.
5346 // That result is represented by a flags operand whose subtype is appropriate
5347 // to the unsignedness (etc.) of the comparison.
5348 //
5349 // Later, the instruction which matches both the Comparison Op (a Bool) and
5350 // the flags (produced by the Cmp) specifies the coding of the comparison op
5351 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5353 // Comparision Code
5354 operand cmpOp()
5355 %{
5356 match(Bool);
5358 format %{ "" %}
5359 interface(COND_INTER) %{
5360 equal(0x4, "e");
5361 not_equal(0x5, "ne");
5362 less(0xC, "l");
5363 greater_equal(0xD, "ge");
5364 less_equal(0xE, "le");
5365 greater(0xF, "g");
5366 %}
5367 %}
5369 // Comparison Code, unsigned compare. Used by FP also, with
5370 // C2 (unordered) turned into GT or LT already. The other bits
5371 // C0 and C3 are turned into Carry & Zero flags.
5372 operand cmpOpU()
5373 %{
5374 match(Bool);
5376 format %{ "" %}
5377 interface(COND_INTER) %{
5378 equal(0x4, "e");
5379 not_equal(0x5, "ne");
5380 less(0x2, "b");
5381 greater_equal(0x3, "nb");
5382 less_equal(0x6, "be");
5383 greater(0x7, "nbe");
5384 %}
5385 %}
5388 // Floating comparisons that don't require any fixup for the unordered case
5389 operand cmpOpUCF() %{
5390 match(Bool);
5391 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5392 n->as_Bool()->_test._test == BoolTest::ge ||
5393 n->as_Bool()->_test._test == BoolTest::le ||
5394 n->as_Bool()->_test._test == BoolTest::gt);
5395 format %{ "" %}
5396 interface(COND_INTER) %{
5397 equal(0x4, "e");
5398 not_equal(0x5, "ne");
5399 less(0x2, "b");
5400 greater_equal(0x3, "nb");
5401 less_equal(0x6, "be");
5402 greater(0x7, "nbe");
5403 %}
5404 %}
5407 // Floating comparisons that can be fixed up with extra conditional jumps
5408 operand cmpOpUCF2() %{
5409 match(Bool);
5410 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5411 n->as_Bool()->_test._test == BoolTest::eq);
5412 format %{ "" %}
5413 interface(COND_INTER) %{
5414 equal(0x4, "e");
5415 not_equal(0x5, "ne");
5416 less(0x2, "b");
5417 greater_equal(0x3, "nb");
5418 less_equal(0x6, "be");
5419 greater(0x7, "nbe");
5420 %}
5421 %}
5424 //----------OPERAND CLASSES----------------------------------------------------
5425 // Operand Classes are groups of operands that are used as to simplify
5426 // instruction definitions by not requiring the AD writer to specify separate
5427 // instructions for every form of operand when the instruction accepts
5428 // multiple operand types with the same basic encoding and format. The classic
5429 // case of this is memory operands.
5431 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
5432 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
5433 indCompressedOopOffset,
5434 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
5435 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
5436 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
5438 //----------PIPELINE-----------------------------------------------------------
5439 // Rules which define the behavior of the target architectures pipeline.
5440 pipeline %{
5442 //----------ATTRIBUTES---------------------------------------------------------
5443 attributes %{
5444 variable_size_instructions; // Fixed size instructions
5445 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5446 instruction_unit_size = 1; // An instruction is 1 bytes long
5447 instruction_fetch_unit_size = 16; // The processor fetches one line
5448 instruction_fetch_units = 1; // of 16 bytes
5450 // List of nop instructions
5451 nops( MachNop );
5452 %}
5454 //----------RESOURCES----------------------------------------------------------
5455 // Resources are the functional units available to the machine
5457 // Generic P2/P3 pipeline
5458 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5459 // 3 instructions decoded per cycle.
5460 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5461 // 3 ALU op, only ALU0 handles mul instructions.
5462 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5463 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
5464 BR, FPU,
5465 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
5467 //----------PIPELINE DESCRIPTION-----------------------------------------------
5468 // Pipeline Description specifies the stages in the machine's pipeline
5470 // Generic P2/P3 pipeline
5471 pipe_desc(S0, S1, S2, S3, S4, S5);
5473 //----------PIPELINE CLASSES---------------------------------------------------
5474 // Pipeline Classes describe the stages in which input and output are
5475 // referenced by the hardware pipeline.
5477 // Naming convention: ialu or fpu
5478 // Then: _reg
5479 // Then: _reg if there is a 2nd register
5480 // Then: _long if it's a pair of instructions implementing a long
5481 // Then: _fat if it requires the big decoder
5482 // Or: _mem if it requires the big decoder and a memory unit.
5484 // Integer ALU reg operation
5485 pipe_class ialu_reg(rRegI dst)
5486 %{
5487 single_instruction;
5488 dst : S4(write);
5489 dst : S3(read);
5490 DECODE : S0; // any decoder
5491 ALU : S3; // any alu
5492 %}
5494 // Long ALU reg operation
5495 pipe_class ialu_reg_long(rRegL dst)
5496 %{
5497 instruction_count(2);
5498 dst : S4(write);
5499 dst : S3(read);
5500 DECODE : S0(2); // any 2 decoders
5501 ALU : S3(2); // both alus
5502 %}
5504 // Integer ALU reg operation using big decoder
5505 pipe_class ialu_reg_fat(rRegI dst)
5506 %{
5507 single_instruction;
5508 dst : S4(write);
5509 dst : S3(read);
5510 D0 : S0; // big decoder only
5511 ALU : S3; // any alu
5512 %}
5514 // Long ALU reg operation using big decoder
5515 pipe_class ialu_reg_long_fat(rRegL dst)
5516 %{
5517 instruction_count(2);
5518 dst : S4(write);
5519 dst : S3(read);
5520 D0 : S0(2); // big decoder only; twice
5521 ALU : S3(2); // any 2 alus
5522 %}
5524 // Integer ALU reg-reg operation
5525 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
5526 %{
5527 single_instruction;
5528 dst : S4(write);
5529 src : S3(read);
5530 DECODE : S0; // any decoder
5531 ALU : S3; // any alu
5532 %}
5534 // Long ALU reg-reg operation
5535 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
5536 %{
5537 instruction_count(2);
5538 dst : S4(write);
5539 src : S3(read);
5540 DECODE : S0(2); // any 2 decoders
5541 ALU : S3(2); // both alus
5542 %}
5544 // Integer ALU reg-reg operation
5545 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
5546 %{
5547 single_instruction;
5548 dst : S4(write);
5549 src : S3(read);
5550 D0 : S0; // big decoder only
5551 ALU : S3; // any alu
5552 %}
5554 // Long ALU reg-reg operation
5555 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
5556 %{
5557 instruction_count(2);
5558 dst : S4(write);
5559 src : S3(read);
5560 D0 : S0(2); // big decoder only; twice
5561 ALU : S3(2); // both alus
5562 %}
5564 // Integer ALU reg-mem operation
5565 pipe_class ialu_reg_mem(rRegI dst, memory mem)
5566 %{
5567 single_instruction;
5568 dst : S5(write);
5569 mem : S3(read);
5570 D0 : S0; // big decoder only
5571 ALU : S4; // any alu
5572 MEM : S3; // any mem
5573 %}
5575 // Integer mem operation (prefetch)
5576 pipe_class ialu_mem(memory mem)
5577 %{
5578 single_instruction;
5579 mem : S3(read);
5580 D0 : S0; // big decoder only
5581 MEM : S3; // any mem
5582 %}
5584 // Integer Store to Memory
5585 pipe_class ialu_mem_reg(memory mem, rRegI src)
5586 %{
5587 single_instruction;
5588 mem : S3(read);
5589 src : S5(read);
5590 D0 : S0; // big decoder only
5591 ALU : S4; // any alu
5592 MEM : S3;
5593 %}
5595 // // Long Store to Memory
5596 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
5597 // %{
5598 // instruction_count(2);
5599 // mem : S3(read);
5600 // src : S5(read);
5601 // D0 : S0(2); // big decoder only; twice
5602 // ALU : S4(2); // any 2 alus
5603 // MEM : S3(2); // Both mems
5604 // %}
5606 // Integer Store to Memory
5607 pipe_class ialu_mem_imm(memory mem)
5608 %{
5609 single_instruction;
5610 mem : S3(read);
5611 D0 : S0; // big decoder only
5612 ALU : S4; // any alu
5613 MEM : S3;
5614 %}
5616 // Integer ALU0 reg-reg operation
5617 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
5618 %{
5619 single_instruction;
5620 dst : S4(write);
5621 src : S3(read);
5622 D0 : S0; // Big decoder only
5623 ALU0 : S3; // only alu0
5624 %}
5626 // Integer ALU0 reg-mem operation
5627 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
5628 %{
5629 single_instruction;
5630 dst : S5(write);
5631 mem : S3(read);
5632 D0 : S0; // big decoder only
5633 ALU0 : S4; // ALU0 only
5634 MEM : S3; // any mem
5635 %}
5637 // Integer ALU reg-reg operation
5638 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
5639 %{
5640 single_instruction;
5641 cr : S4(write);
5642 src1 : S3(read);
5643 src2 : S3(read);
5644 DECODE : S0; // any decoder
5645 ALU : S3; // any alu
5646 %}
5648 // Integer ALU reg-imm operation
5649 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
5650 %{
5651 single_instruction;
5652 cr : S4(write);
5653 src1 : S3(read);
5654 DECODE : S0; // any decoder
5655 ALU : S3; // any alu
5656 %}
5658 // Integer ALU reg-mem operation
5659 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
5660 %{
5661 single_instruction;
5662 cr : S4(write);
5663 src1 : S3(read);
5664 src2 : S3(read);
5665 D0 : S0; // big decoder only
5666 ALU : S4; // any alu
5667 MEM : S3;
5668 %}
5670 // Conditional move reg-reg
5671 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
5672 %{
5673 instruction_count(4);
5674 y : S4(read);
5675 q : S3(read);
5676 p : S3(read);
5677 DECODE : S0(4); // any decoder
5678 %}
5680 // Conditional move reg-reg
5681 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
5682 %{
5683 single_instruction;
5684 dst : S4(write);
5685 src : S3(read);
5686 cr : S3(read);
5687 DECODE : S0; // any decoder
5688 %}
5690 // Conditional move reg-mem
5691 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
5692 %{
5693 single_instruction;
5694 dst : S4(write);
5695 src : S3(read);
5696 cr : S3(read);
5697 DECODE : S0; // any decoder
5698 MEM : S3;
5699 %}
5701 // Conditional move reg-reg long
5702 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
5703 %{
5704 single_instruction;
5705 dst : S4(write);
5706 src : S3(read);
5707 cr : S3(read);
5708 DECODE : S0(2); // any 2 decoders
5709 %}
5711 // XXX
5712 // // Conditional move double reg-reg
5713 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
5714 // %{
5715 // single_instruction;
5716 // dst : S4(write);
5717 // src : S3(read);
5718 // cr : S3(read);
5719 // DECODE : S0; // any decoder
5720 // %}
5722 // Float reg-reg operation
5723 pipe_class fpu_reg(regD dst)
5724 %{
5725 instruction_count(2);
5726 dst : S3(read);
5727 DECODE : S0(2); // any 2 decoders
5728 FPU : S3;
5729 %}
5731 // Float reg-reg operation
5732 pipe_class fpu_reg_reg(regD dst, regD src)
5733 %{
5734 instruction_count(2);
5735 dst : S4(write);
5736 src : S3(read);
5737 DECODE : S0(2); // any 2 decoders
5738 FPU : S3;
5739 %}
5741 // Float reg-reg operation
5742 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
5743 %{
5744 instruction_count(3);
5745 dst : S4(write);
5746 src1 : S3(read);
5747 src2 : S3(read);
5748 DECODE : S0(3); // any 3 decoders
5749 FPU : S3(2);
5750 %}
5752 // Float reg-reg operation
5753 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
5754 %{
5755 instruction_count(4);
5756 dst : S4(write);
5757 src1 : S3(read);
5758 src2 : S3(read);
5759 src3 : S3(read);
5760 DECODE : S0(4); // any 3 decoders
5761 FPU : S3(2);
5762 %}
5764 // Float reg-reg operation
5765 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
5766 %{
5767 instruction_count(4);
5768 dst : S4(write);
5769 src1 : S3(read);
5770 src2 : S3(read);
5771 src3 : S3(read);
5772 DECODE : S1(3); // any 3 decoders
5773 D0 : S0; // Big decoder only
5774 FPU : S3(2);
5775 MEM : S3;
5776 %}
5778 // Float reg-mem operation
5779 pipe_class fpu_reg_mem(regD dst, memory mem)
5780 %{
5781 instruction_count(2);
5782 dst : S5(write);
5783 mem : S3(read);
5784 D0 : S0; // big decoder only
5785 DECODE : S1; // any decoder for FPU POP
5786 FPU : S4;
5787 MEM : S3; // any mem
5788 %}
5790 // Float reg-mem operation
5791 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
5792 %{
5793 instruction_count(3);
5794 dst : S5(write);
5795 src1 : S3(read);
5796 mem : S3(read);
5797 D0 : S0; // big decoder only
5798 DECODE : S1(2); // any decoder for FPU POP
5799 FPU : S4;
5800 MEM : S3; // any mem
5801 %}
5803 // Float mem-reg operation
5804 pipe_class fpu_mem_reg(memory mem, regD src)
5805 %{
5806 instruction_count(2);
5807 src : S5(read);
5808 mem : S3(read);
5809 DECODE : S0; // any decoder for FPU PUSH
5810 D0 : S1; // big decoder only
5811 FPU : S4;
5812 MEM : S3; // any mem
5813 %}
5815 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
5816 %{
5817 instruction_count(3);
5818 src1 : S3(read);
5819 src2 : S3(read);
5820 mem : S3(read);
5821 DECODE : S0(2); // any decoder for FPU PUSH
5822 D0 : S1; // big decoder only
5823 FPU : S4;
5824 MEM : S3; // any mem
5825 %}
5827 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
5828 %{
5829 instruction_count(3);
5830 src1 : S3(read);
5831 src2 : S3(read);
5832 mem : S4(read);
5833 DECODE : S0; // any decoder for FPU PUSH
5834 D0 : S0(2); // big decoder only
5835 FPU : S4;
5836 MEM : S3(2); // any mem
5837 %}
5839 pipe_class fpu_mem_mem(memory dst, memory src1)
5840 %{
5841 instruction_count(2);
5842 src1 : S3(read);
5843 dst : S4(read);
5844 D0 : S0(2); // big decoder only
5845 MEM : S3(2); // any mem
5846 %}
5848 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
5849 %{
5850 instruction_count(3);
5851 src1 : S3(read);
5852 src2 : S3(read);
5853 dst : S4(read);
5854 D0 : S0(3); // big decoder only
5855 FPU : S4;
5856 MEM : S3(3); // any mem
5857 %}
5859 pipe_class fpu_mem_reg_con(memory mem, regD src1)
5860 %{
5861 instruction_count(3);
5862 src1 : S4(read);
5863 mem : S4(read);
5864 DECODE : S0; // any decoder for FPU PUSH
5865 D0 : S0(2); // big decoder only
5866 FPU : S4;
5867 MEM : S3(2); // any mem
5868 %}
5870 // Float load constant
5871 pipe_class fpu_reg_con(regD dst)
5872 %{
5873 instruction_count(2);
5874 dst : S5(write);
5875 D0 : S0; // big decoder only for the load
5876 DECODE : S1; // any decoder for FPU POP
5877 FPU : S4;
5878 MEM : S3; // any mem
5879 %}
5881 // Float load constant
5882 pipe_class fpu_reg_reg_con(regD dst, regD src)
5883 %{
5884 instruction_count(3);
5885 dst : S5(write);
5886 src : S3(read);
5887 D0 : S0; // big decoder only for the load
5888 DECODE : S1(2); // any decoder for FPU POP
5889 FPU : S4;
5890 MEM : S3; // any mem
5891 %}
5893 // UnConditional branch
5894 pipe_class pipe_jmp(label labl)
5895 %{
5896 single_instruction;
5897 BR : S3;
5898 %}
5900 // Conditional branch
5901 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
5902 %{
5903 single_instruction;
5904 cr : S1(read);
5905 BR : S3;
5906 %}
5908 // Allocation idiom
5909 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
5910 %{
5911 instruction_count(1); force_serialization;
5912 fixed_latency(6);
5913 heap_ptr : S3(read);
5914 DECODE : S0(3);
5915 D0 : S2;
5916 MEM : S3;
5917 ALU : S3(2);
5918 dst : S5(write);
5919 BR : S5;
5920 %}
5922 // Generic big/slow expanded idiom
5923 pipe_class pipe_slow()
5924 %{
5925 instruction_count(10); multiple_bundles; force_serialization;
5926 fixed_latency(100);
5927 D0 : S0(2);
5928 MEM : S3(2);
5929 %}
5931 // The real do-nothing guy
5932 pipe_class empty()
5933 %{
5934 instruction_count(0);
5935 %}
5937 // Define the class for the Nop node
5938 define
5939 %{
5940 MachNop = empty;
5941 %}
5943 %}
5945 //----------INSTRUCTIONS-------------------------------------------------------
5946 //
5947 // match -- States which machine-independent subtree may be replaced
5948 // by this instruction.
5949 // ins_cost -- The estimated cost of this instruction is used by instruction
5950 // selection to identify a minimum cost tree of machine
5951 // instructions that matches a tree of machine-independent
5952 // instructions.
5953 // format -- A string providing the disassembly for this instruction.
5954 // The value of an instruction's operand may be inserted
5955 // by referring to it with a '$' prefix.
5956 // opcode -- Three instruction opcodes may be provided. These are referred
5957 // to within an encode class as $primary, $secondary, and $tertiary
5958 // rrspectively. The primary opcode is commonly used to
5959 // indicate the type of machine instruction, while secondary
5960 // and tertiary are often used for prefix options or addressing
5961 // modes.
5962 // ins_encode -- A list of encode classes with parameters. The encode class
5963 // name must have been defined in an 'enc_class' specification
5964 // in the encode section of the architecture description.
5967 //----------Load/Store/Move Instructions---------------------------------------
5968 //----------Load Instructions--------------------------------------------------
5970 // Load Byte (8 bit signed)
5971 instruct loadB(rRegI dst, memory mem)
5972 %{
5973 match(Set dst (LoadB mem));
5975 ins_cost(125);
5976 format %{ "movsbl $dst, $mem\t# byte" %}
5978 ins_encode %{
5979 __ movsbl($dst$$Register, $mem$$Address);
5980 %}
5982 ins_pipe(ialu_reg_mem);
5983 %}
5985 // Load Byte (8 bit signed) into Long Register
5986 instruct loadB2L(rRegL dst, memory mem)
5987 %{
5988 match(Set dst (ConvI2L (LoadB mem)));
5990 ins_cost(125);
5991 format %{ "movsbq $dst, $mem\t# byte -> long" %}
5993 ins_encode %{
5994 __ movsbq($dst$$Register, $mem$$Address);
5995 %}
5997 ins_pipe(ialu_reg_mem);
5998 %}
6000 // Load Unsigned Byte (8 bit UNsigned)
6001 instruct loadUB(rRegI dst, memory mem)
6002 %{
6003 match(Set dst (LoadUB mem));
6005 ins_cost(125);
6006 format %{ "movzbl $dst, $mem\t# ubyte" %}
6008 ins_encode %{
6009 __ movzbl($dst$$Register, $mem$$Address);
6010 %}
6012 ins_pipe(ialu_reg_mem);
6013 %}
6015 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6016 instruct loadUB2L(rRegL dst, memory mem)
6017 %{
6018 match(Set dst (ConvI2L (LoadUB mem)));
6020 ins_cost(125);
6021 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
6023 ins_encode %{
6024 __ movzbq($dst$$Register, $mem$$Address);
6025 %}
6027 ins_pipe(ialu_reg_mem);
6028 %}
6030 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
6031 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
6032 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6033 effect(KILL cr);
6035 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
6036 "andl $dst, $mask" %}
6037 ins_encode %{
6038 Register Rdst = $dst$$Register;
6039 __ movzbq(Rdst, $mem$$Address);
6040 __ andl(Rdst, $mask$$constant);
6041 %}
6042 ins_pipe(ialu_reg_mem);
6043 %}
6045 // Load Short (16 bit signed)
6046 instruct loadS(rRegI dst, memory mem)
6047 %{
6048 match(Set dst (LoadS mem));
6050 ins_cost(125);
6051 format %{ "movswl $dst, $mem\t# short" %}
6053 ins_encode %{
6054 __ movswl($dst$$Register, $mem$$Address);
6055 %}
6057 ins_pipe(ialu_reg_mem);
6058 %}
6060 // Load Short (16 bit signed) to Byte (8 bit signed)
6061 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6062 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6064 ins_cost(125);
6065 format %{ "movsbl $dst, $mem\t# short -> byte" %}
6066 ins_encode %{
6067 __ movsbl($dst$$Register, $mem$$Address);
6068 %}
6069 ins_pipe(ialu_reg_mem);
6070 %}
6072 // Load Short (16 bit signed) into Long Register
6073 instruct loadS2L(rRegL dst, memory mem)
6074 %{
6075 match(Set dst (ConvI2L (LoadS mem)));
6077 ins_cost(125);
6078 format %{ "movswq $dst, $mem\t# short -> long" %}
6080 ins_encode %{
6081 __ movswq($dst$$Register, $mem$$Address);
6082 %}
6084 ins_pipe(ialu_reg_mem);
6085 %}
6087 // Load Unsigned Short/Char (16 bit UNsigned)
6088 instruct loadUS(rRegI dst, memory mem)
6089 %{
6090 match(Set dst (LoadUS mem));
6092 ins_cost(125);
6093 format %{ "movzwl $dst, $mem\t# ushort/char" %}
6095 ins_encode %{
6096 __ movzwl($dst$$Register, $mem$$Address);
6097 %}
6099 ins_pipe(ialu_reg_mem);
6100 %}
6102 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6103 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6104 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6106 ins_cost(125);
6107 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
6108 ins_encode %{
6109 __ movsbl($dst$$Register, $mem$$Address);
6110 %}
6111 ins_pipe(ialu_reg_mem);
6112 %}
6114 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6115 instruct loadUS2L(rRegL dst, memory mem)
6116 %{
6117 match(Set dst (ConvI2L (LoadUS mem)));
6119 ins_cost(125);
6120 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
6122 ins_encode %{
6123 __ movzwq($dst$$Register, $mem$$Address);
6124 %}
6126 ins_pipe(ialu_reg_mem);
6127 %}
6129 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6130 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
6131 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6133 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
6134 ins_encode %{
6135 __ movzbq($dst$$Register, $mem$$Address);
6136 %}
6137 ins_pipe(ialu_reg_mem);
6138 %}
6140 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
6141 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
6142 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6143 effect(KILL cr);
6145 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6146 "andl $dst, $mask" %}
6147 ins_encode %{
6148 Register Rdst = $dst$$Register;
6149 __ movzwq(Rdst, $mem$$Address);
6150 __ andl(Rdst, $mask$$constant);
6151 %}
6152 ins_pipe(ialu_reg_mem);
6153 %}
6155 // Load Integer
6156 instruct loadI(rRegI dst, memory mem)
6157 %{
6158 match(Set dst (LoadI mem));
6160 ins_cost(125);
6161 format %{ "movl $dst, $mem\t# int" %}
6163 ins_encode %{
6164 __ movl($dst$$Register, $mem$$Address);
6165 %}
6167 ins_pipe(ialu_reg_mem);
6168 %}
6170 // Load Integer (32 bit signed) to Byte (8 bit signed)
6171 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6172 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6174 ins_cost(125);
6175 format %{ "movsbl $dst, $mem\t# int -> byte" %}
6176 ins_encode %{
6177 __ movsbl($dst$$Register, $mem$$Address);
6178 %}
6179 ins_pipe(ialu_reg_mem);
6180 %}
6182 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6183 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6184 match(Set dst (AndI (LoadI mem) mask));
6186 ins_cost(125);
6187 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
6188 ins_encode %{
6189 __ movzbl($dst$$Register, $mem$$Address);
6190 %}
6191 ins_pipe(ialu_reg_mem);
6192 %}
6194 // Load Integer (32 bit signed) to Short (16 bit signed)
6195 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6196 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6198 ins_cost(125);
6199 format %{ "movswl $dst, $mem\t# int -> short" %}
6200 ins_encode %{
6201 __ movswl($dst$$Register, $mem$$Address);
6202 %}
6203 ins_pipe(ialu_reg_mem);
6204 %}
6206 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6207 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6208 match(Set dst (AndI (LoadI mem) mask));
6210 ins_cost(125);
6211 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
6212 ins_encode %{
6213 __ movzwl($dst$$Register, $mem$$Address);
6214 %}
6215 ins_pipe(ialu_reg_mem);
6216 %}
6218 // Load Integer into Long Register
6219 instruct loadI2L(rRegL dst, memory mem)
6220 %{
6221 match(Set dst (ConvI2L (LoadI mem)));
6223 ins_cost(125);
6224 format %{ "movslq $dst, $mem\t# int -> long" %}
6226 ins_encode %{
6227 __ movslq($dst$$Register, $mem$$Address);
6228 %}
6230 ins_pipe(ialu_reg_mem);
6231 %}
6233 // Load Integer with mask 0xFF into Long Register
6234 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
6235 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6237 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
6238 ins_encode %{
6239 __ movzbq($dst$$Register, $mem$$Address);
6240 %}
6241 ins_pipe(ialu_reg_mem);
6242 %}
6244 // Load Integer with mask 0xFFFF into Long Register
6245 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
6246 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6248 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
6249 ins_encode %{
6250 __ movzwq($dst$$Register, $mem$$Address);
6251 %}
6252 ins_pipe(ialu_reg_mem);
6253 %}
6255 // Load Integer with a 32-bit mask into Long Register
6256 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
6257 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6258 effect(KILL cr);
6260 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
6261 "andl $dst, $mask" %}
6262 ins_encode %{
6263 Register Rdst = $dst$$Register;
6264 __ movl(Rdst, $mem$$Address);
6265 __ andl(Rdst, $mask$$constant);
6266 %}
6267 ins_pipe(ialu_reg_mem);
6268 %}
6270 // Load Unsigned Integer into Long Register
6271 instruct loadUI2L(rRegL dst, memory mem)
6272 %{
6273 match(Set dst (LoadUI2L mem));
6275 ins_cost(125);
6276 format %{ "movl $dst, $mem\t# uint -> long" %}
6278 ins_encode %{
6279 __ movl($dst$$Register, $mem$$Address);
6280 %}
6282 ins_pipe(ialu_reg_mem);
6283 %}
6285 // Load Long
6286 instruct loadL(rRegL dst, memory mem)
6287 %{
6288 match(Set dst (LoadL mem));
6290 ins_cost(125);
6291 format %{ "movq $dst, $mem\t# long" %}
6293 ins_encode %{
6294 __ movq($dst$$Register, $mem$$Address);
6295 %}
6297 ins_pipe(ialu_reg_mem); // XXX
6298 %}
6300 // Load Range
6301 instruct loadRange(rRegI dst, memory mem)
6302 %{
6303 match(Set dst (LoadRange mem));
6305 ins_cost(125); // XXX
6306 format %{ "movl $dst, $mem\t# range" %}
6307 opcode(0x8B);
6308 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6309 ins_pipe(ialu_reg_mem);
6310 %}
6312 // Load Pointer
6313 instruct loadP(rRegP dst, memory mem)
6314 %{
6315 match(Set dst (LoadP mem));
6317 ins_cost(125); // XXX
6318 format %{ "movq $dst, $mem\t# ptr" %}
6319 opcode(0x8B);
6320 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6321 ins_pipe(ialu_reg_mem); // XXX
6322 %}
6324 // Load Compressed Pointer
6325 instruct loadN(rRegN dst, memory mem)
6326 %{
6327 match(Set dst (LoadN mem));
6329 ins_cost(125); // XXX
6330 format %{ "movl $dst, $mem\t# compressed ptr" %}
6331 ins_encode %{
6332 __ movl($dst$$Register, $mem$$Address);
6333 %}
6334 ins_pipe(ialu_reg_mem); // XXX
6335 %}
6338 // Load Klass Pointer
6339 instruct loadKlass(rRegP dst, memory mem)
6340 %{
6341 match(Set dst (LoadKlass mem));
6343 ins_cost(125); // XXX
6344 format %{ "movq $dst, $mem\t# class" %}
6345 opcode(0x8B);
6346 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6347 ins_pipe(ialu_reg_mem); // XXX
6348 %}
6350 // Load narrow Klass Pointer
6351 instruct loadNKlass(rRegN dst, memory mem)
6352 %{
6353 match(Set dst (LoadNKlass mem));
6355 ins_cost(125); // XXX
6356 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
6357 ins_encode %{
6358 __ movl($dst$$Register, $mem$$Address);
6359 %}
6360 ins_pipe(ialu_reg_mem); // XXX
6361 %}
6363 // Load Float
6364 instruct loadF(regF dst, memory mem)
6365 %{
6366 match(Set dst (LoadF mem));
6368 ins_cost(145); // XXX
6369 format %{ "movss $dst, $mem\t# float" %}
6370 opcode(0xF3, 0x0F, 0x10);
6371 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6372 ins_pipe(pipe_slow); // XXX
6373 %}
6375 // Load Double
6376 instruct loadD_partial(regD dst, memory mem)
6377 %{
6378 predicate(!UseXmmLoadAndClearUpper);
6379 match(Set dst (LoadD mem));
6381 ins_cost(145); // XXX
6382 format %{ "movlpd $dst, $mem\t# double" %}
6383 opcode(0x66, 0x0F, 0x12);
6384 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6385 ins_pipe(pipe_slow); // XXX
6386 %}
6388 instruct loadD(regD dst, memory mem)
6389 %{
6390 predicate(UseXmmLoadAndClearUpper);
6391 match(Set dst (LoadD mem));
6393 ins_cost(145); // XXX
6394 format %{ "movsd $dst, $mem\t# double" %}
6395 opcode(0xF2, 0x0F, 0x10);
6396 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6397 ins_pipe(pipe_slow); // XXX
6398 %}
6400 // Load Aligned Packed Byte to XMM register
6401 instruct loadA8B(regD dst, memory mem) %{
6402 match(Set dst (Load8B mem));
6403 ins_cost(125);
6404 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6405 ins_encode( movq_ld(dst, mem));
6406 ins_pipe( pipe_slow );
6407 %}
6409 // Load Aligned Packed Short to XMM register
6410 instruct loadA4S(regD dst, memory mem) %{
6411 match(Set dst (Load4S mem));
6412 ins_cost(125);
6413 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6414 ins_encode( movq_ld(dst, mem));
6415 ins_pipe( pipe_slow );
6416 %}
6418 // Load Aligned Packed Char to XMM register
6419 instruct loadA4C(regD dst, memory mem) %{
6420 match(Set dst (Load4C mem));
6421 ins_cost(125);
6422 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6423 ins_encode( movq_ld(dst, mem));
6424 ins_pipe( pipe_slow );
6425 %}
6427 // Load Aligned Packed Integer to XMM register
6428 instruct load2IU(regD dst, memory mem) %{
6429 match(Set dst (Load2I mem));
6430 ins_cost(125);
6431 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6432 ins_encode( movq_ld(dst, mem));
6433 ins_pipe( pipe_slow );
6434 %}
6436 // Load Aligned Packed Single to XMM
6437 instruct loadA2F(regD dst, memory mem) %{
6438 match(Set dst (Load2F mem));
6439 ins_cost(145);
6440 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6441 ins_encode( movq_ld(dst, mem));
6442 ins_pipe( pipe_slow );
6443 %}
6445 // Load Effective Address
6446 instruct leaP8(rRegP dst, indOffset8 mem)
6447 %{
6448 match(Set dst mem);
6450 ins_cost(110); // XXX
6451 format %{ "leaq $dst, $mem\t# ptr 8" %}
6452 opcode(0x8D);
6453 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6454 ins_pipe(ialu_reg_reg_fat);
6455 %}
6457 instruct leaP32(rRegP dst, indOffset32 mem)
6458 %{
6459 match(Set dst mem);
6461 ins_cost(110);
6462 format %{ "leaq $dst, $mem\t# ptr 32" %}
6463 opcode(0x8D);
6464 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6465 ins_pipe(ialu_reg_reg_fat);
6466 %}
6468 // instruct leaPIdx(rRegP dst, indIndex mem)
6469 // %{
6470 // match(Set dst mem);
6472 // ins_cost(110);
6473 // format %{ "leaq $dst, $mem\t# ptr idx" %}
6474 // opcode(0x8D);
6475 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6476 // ins_pipe(ialu_reg_reg_fat);
6477 // %}
6479 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
6480 %{
6481 match(Set dst mem);
6483 ins_cost(110);
6484 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
6485 opcode(0x8D);
6486 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6487 ins_pipe(ialu_reg_reg_fat);
6488 %}
6490 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
6491 %{
6492 match(Set dst mem);
6494 ins_cost(110);
6495 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
6496 opcode(0x8D);
6497 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6498 ins_pipe(ialu_reg_reg_fat);
6499 %}
6501 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
6502 %{
6503 match(Set dst mem);
6505 ins_cost(110);
6506 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
6507 opcode(0x8D);
6508 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6509 ins_pipe(ialu_reg_reg_fat);
6510 %}
6512 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
6513 %{
6514 match(Set dst mem);
6516 ins_cost(110);
6517 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
6518 opcode(0x8D);
6519 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6520 ins_pipe(ialu_reg_reg_fat);
6521 %}
6523 // Load Effective Address which uses Narrow (32-bits) oop
6524 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
6525 %{
6526 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
6527 match(Set dst mem);
6529 ins_cost(110);
6530 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
6531 opcode(0x8D);
6532 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6533 ins_pipe(ialu_reg_reg_fat);
6534 %}
6536 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
6537 %{
6538 predicate(Universe::narrow_oop_shift() == 0);
6539 match(Set dst mem);
6541 ins_cost(110); // XXX
6542 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
6543 opcode(0x8D);
6544 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6545 ins_pipe(ialu_reg_reg_fat);
6546 %}
6548 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
6549 %{
6550 predicate(Universe::narrow_oop_shift() == 0);
6551 match(Set dst mem);
6553 ins_cost(110);
6554 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
6555 opcode(0x8D);
6556 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6557 ins_pipe(ialu_reg_reg_fat);
6558 %}
6560 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
6561 %{
6562 predicate(Universe::narrow_oop_shift() == 0);
6563 match(Set dst mem);
6565 ins_cost(110);
6566 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
6567 opcode(0x8D);
6568 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6569 ins_pipe(ialu_reg_reg_fat);
6570 %}
6572 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
6573 %{
6574 predicate(Universe::narrow_oop_shift() == 0);
6575 match(Set dst mem);
6577 ins_cost(110);
6578 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
6579 opcode(0x8D);
6580 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6581 ins_pipe(ialu_reg_reg_fat);
6582 %}
6584 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
6585 %{
6586 predicate(Universe::narrow_oop_shift() == 0);
6587 match(Set dst mem);
6589 ins_cost(110);
6590 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
6591 opcode(0x8D);
6592 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6593 ins_pipe(ialu_reg_reg_fat);
6594 %}
6596 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
6597 %{
6598 predicate(Universe::narrow_oop_shift() == 0);
6599 match(Set dst mem);
6601 ins_cost(110);
6602 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
6603 opcode(0x8D);
6604 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6605 ins_pipe(ialu_reg_reg_fat);
6606 %}
6608 instruct loadConI(rRegI dst, immI src)
6609 %{
6610 match(Set dst src);
6612 format %{ "movl $dst, $src\t# int" %}
6613 ins_encode(load_immI(dst, src));
6614 ins_pipe(ialu_reg_fat); // XXX
6615 %}
6617 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
6618 %{
6619 match(Set dst src);
6620 effect(KILL cr);
6622 ins_cost(50);
6623 format %{ "xorl $dst, $dst\t# int" %}
6624 opcode(0x33); /* + rd */
6625 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6626 ins_pipe(ialu_reg);
6627 %}
6629 instruct loadConL(rRegL dst, immL src)
6630 %{
6631 match(Set dst src);
6633 ins_cost(150);
6634 format %{ "movq $dst, $src\t# long" %}
6635 ins_encode(load_immL(dst, src));
6636 ins_pipe(ialu_reg);
6637 %}
6639 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
6640 %{
6641 match(Set dst src);
6642 effect(KILL cr);
6644 ins_cost(50);
6645 format %{ "xorl $dst, $dst\t# long" %}
6646 opcode(0x33); /* + rd */
6647 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6648 ins_pipe(ialu_reg); // XXX
6649 %}
6651 instruct loadConUL32(rRegL dst, immUL32 src)
6652 %{
6653 match(Set dst src);
6655 ins_cost(60);
6656 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
6657 ins_encode(load_immUL32(dst, src));
6658 ins_pipe(ialu_reg);
6659 %}
6661 instruct loadConL32(rRegL dst, immL32 src)
6662 %{
6663 match(Set dst src);
6665 ins_cost(70);
6666 format %{ "movq $dst, $src\t# long (32-bit)" %}
6667 ins_encode(load_immL32(dst, src));
6668 ins_pipe(ialu_reg);
6669 %}
6671 instruct loadConP(rRegP dst, immP src)
6672 %{
6673 match(Set dst src);
6675 format %{ "movq $dst, $src\t# ptr" %}
6676 ins_encode(load_immP(dst, src));
6677 ins_pipe(ialu_reg_fat); // XXX
6678 %}
6680 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
6681 %{
6682 match(Set dst src);
6683 effect(KILL cr);
6685 ins_cost(50);
6686 format %{ "xorl $dst, $dst\t# ptr" %}
6687 opcode(0x33); /* + rd */
6688 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6689 ins_pipe(ialu_reg);
6690 %}
6692 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
6693 %{
6694 match(Set dst src);
6695 effect(KILL cr);
6697 ins_cost(60);
6698 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
6699 ins_encode(load_immP31(dst, src));
6700 ins_pipe(ialu_reg);
6701 %}
6703 instruct loadConF(regF dst, immF src)
6704 %{
6705 match(Set dst src);
6706 ins_cost(125);
6708 format %{ "movss $dst, [$src]" %}
6709 ins_encode(load_conF(dst, src));
6710 ins_pipe(pipe_slow);
6711 %}
6713 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6714 match(Set dst src);
6715 effect(KILL cr);
6716 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
6717 ins_encode %{
6718 __ xorq($dst$$Register, $dst$$Register);
6719 %}
6720 ins_pipe(ialu_reg);
6721 %}
6723 instruct loadConN(rRegN dst, immN src) %{
6724 match(Set dst src);
6726 ins_cost(125);
6727 format %{ "movl $dst, $src\t# compressed ptr" %}
6728 ins_encode %{
6729 address con = (address)$src$$constant;
6730 if (con == NULL) {
6731 ShouldNotReachHere();
6732 } else {
6733 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
6734 }
6735 %}
6736 ins_pipe(ialu_reg_fat); // XXX
6737 %}
6739 instruct loadConF0(regF dst, immF0 src)
6740 %{
6741 match(Set dst src);
6742 ins_cost(100);
6744 format %{ "xorps $dst, $dst\t# float 0.0" %}
6745 opcode(0x0F, 0x57);
6746 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
6747 ins_pipe(pipe_slow);
6748 %}
6750 // Use the same format since predicate() can not be used here.
6751 instruct loadConD(regD dst, immD src)
6752 %{
6753 match(Set dst src);
6754 ins_cost(125);
6756 format %{ "movsd $dst, [$src]" %}
6757 ins_encode(load_conD(dst, src));
6758 ins_pipe(pipe_slow);
6759 %}
6761 instruct loadConD0(regD dst, immD0 src)
6762 %{
6763 match(Set dst src);
6764 ins_cost(100);
6766 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6767 opcode(0x66, 0x0F, 0x57);
6768 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst));
6769 ins_pipe(pipe_slow);
6770 %}
6772 instruct loadSSI(rRegI dst, stackSlotI src)
6773 %{
6774 match(Set dst src);
6776 ins_cost(125);
6777 format %{ "movl $dst, $src\t# int stk" %}
6778 opcode(0x8B);
6779 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6780 ins_pipe(ialu_reg_mem);
6781 %}
6783 instruct loadSSL(rRegL dst, stackSlotL src)
6784 %{
6785 match(Set dst src);
6787 ins_cost(125);
6788 format %{ "movq $dst, $src\t# long stk" %}
6789 opcode(0x8B);
6790 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6791 ins_pipe(ialu_reg_mem);
6792 %}
6794 instruct loadSSP(rRegP dst, stackSlotP src)
6795 %{
6796 match(Set dst src);
6798 ins_cost(125);
6799 format %{ "movq $dst, $src\t# ptr stk" %}
6800 opcode(0x8B);
6801 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6802 ins_pipe(ialu_reg_mem);
6803 %}
6805 instruct loadSSF(regF dst, stackSlotF src)
6806 %{
6807 match(Set dst src);
6809 ins_cost(125);
6810 format %{ "movss $dst, $src\t# float stk" %}
6811 opcode(0xF3, 0x0F, 0x10);
6812 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
6813 ins_pipe(pipe_slow); // XXX
6814 %}
6816 // Use the same format since predicate() can not be used here.
6817 instruct loadSSD(regD dst, stackSlotD src)
6818 %{
6819 match(Set dst src);
6821 ins_cost(125);
6822 format %{ "movsd $dst, $src\t# double stk" %}
6823 ins_encode %{
6824 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6825 %}
6826 ins_pipe(pipe_slow); // XXX
6827 %}
6829 // Prefetch instructions.
6830 // Must be safe to execute with invalid address (cannot fault).
6832 instruct prefetchr( memory mem ) %{
6833 predicate(ReadPrefetchInstr==3);
6834 match(PrefetchRead mem);
6835 ins_cost(125);
6837 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6838 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
6839 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6840 ins_pipe(ialu_mem);
6841 %}
6843 instruct prefetchrNTA( memory mem ) %{
6844 predicate(ReadPrefetchInstr==0);
6845 match(PrefetchRead mem);
6846 ins_cost(125);
6848 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6849 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6850 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6851 ins_pipe(ialu_mem);
6852 %}
6854 instruct prefetchrT0( memory mem ) %{
6855 predicate(ReadPrefetchInstr==1);
6856 match(PrefetchRead mem);
6857 ins_cost(125);
6859 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6860 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6861 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6862 ins_pipe(ialu_mem);
6863 %}
6865 instruct prefetchrT2( memory mem ) %{
6866 predicate(ReadPrefetchInstr==2);
6867 match(PrefetchRead mem);
6868 ins_cost(125);
6870 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6871 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6872 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6873 ins_pipe(ialu_mem);
6874 %}
6876 instruct prefetchw( memory mem ) %{
6877 predicate(AllocatePrefetchInstr==3);
6878 match(PrefetchWrite mem);
6879 ins_cost(125);
6881 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
6882 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6883 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6884 ins_pipe(ialu_mem);
6885 %}
6887 instruct prefetchwNTA( memory mem ) %{
6888 predicate(AllocatePrefetchInstr==0);
6889 match(PrefetchWrite mem);
6890 ins_cost(125);
6892 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6893 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6894 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6895 ins_pipe(ialu_mem);
6896 %}
6898 instruct prefetchwT0( memory mem ) %{
6899 predicate(AllocatePrefetchInstr==1);
6900 match(PrefetchWrite mem);
6901 ins_cost(125);
6903 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
6904 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6905 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6906 ins_pipe(ialu_mem);
6907 %}
6909 instruct prefetchwT2( memory mem ) %{
6910 predicate(AllocatePrefetchInstr==2);
6911 match(PrefetchWrite mem);
6912 ins_cost(125);
6914 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
6915 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6916 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6917 ins_pipe(ialu_mem);
6918 %}
6920 //----------Store Instructions-------------------------------------------------
6922 // Store Byte
6923 instruct storeB(memory mem, rRegI src)
6924 %{
6925 match(Set mem (StoreB mem src));
6927 ins_cost(125); // XXX
6928 format %{ "movb $mem, $src\t# byte" %}
6929 opcode(0x88);
6930 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6931 ins_pipe(ialu_mem_reg);
6932 %}
6934 // Store Char/Short
6935 instruct storeC(memory mem, rRegI src)
6936 %{
6937 match(Set mem (StoreC mem src));
6939 ins_cost(125); // XXX
6940 format %{ "movw $mem, $src\t# char/short" %}
6941 opcode(0x89);
6942 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6943 ins_pipe(ialu_mem_reg);
6944 %}
6946 // Store Integer
6947 instruct storeI(memory mem, rRegI src)
6948 %{
6949 match(Set mem (StoreI mem src));
6951 ins_cost(125); // XXX
6952 format %{ "movl $mem, $src\t# int" %}
6953 opcode(0x89);
6954 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6955 ins_pipe(ialu_mem_reg);
6956 %}
6958 // Store Long
6959 instruct storeL(memory mem, rRegL src)
6960 %{
6961 match(Set mem (StoreL mem src));
6963 ins_cost(125); // XXX
6964 format %{ "movq $mem, $src\t# long" %}
6965 opcode(0x89);
6966 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6967 ins_pipe(ialu_mem_reg); // XXX
6968 %}
6970 // Store Pointer
6971 instruct storeP(memory mem, any_RegP src)
6972 %{
6973 match(Set mem (StoreP mem src));
6975 ins_cost(125); // XXX
6976 format %{ "movq $mem, $src\t# ptr" %}
6977 opcode(0x89);
6978 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6979 ins_pipe(ialu_mem_reg);
6980 %}
6982 instruct storeImmP0(memory mem, immP0 zero)
6983 %{
6984 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6985 match(Set mem (StoreP mem zero));
6987 ins_cost(125); // XXX
6988 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6989 ins_encode %{
6990 __ movq($mem$$Address, r12);
6991 %}
6992 ins_pipe(ialu_mem_reg);
6993 %}
6995 // Store NULL Pointer, mark word, or other simple pointer constant.
6996 instruct storeImmP(memory mem, immP31 src)
6997 %{
6998 match(Set mem (StoreP mem src));
7000 ins_cost(150); // XXX
7001 format %{ "movq $mem, $src\t# ptr" %}
7002 opcode(0xC7); /* C7 /0 */
7003 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
7004 ins_pipe(ialu_mem_imm);
7005 %}
7007 // Store Compressed Pointer
7008 instruct storeN(memory mem, rRegN src)
7009 %{
7010 match(Set mem (StoreN mem src));
7012 ins_cost(125); // XXX
7013 format %{ "movl $mem, $src\t# compressed ptr" %}
7014 ins_encode %{
7015 __ movl($mem$$Address, $src$$Register);
7016 %}
7017 ins_pipe(ialu_mem_reg);
7018 %}
7020 instruct storeImmN0(memory mem, immN0 zero)
7021 %{
7022 predicate(Universe::narrow_oop_base() == NULL);
7023 match(Set mem (StoreN mem zero));
7025 ins_cost(125); // XXX
7026 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
7027 ins_encode %{
7028 __ movl($mem$$Address, r12);
7029 %}
7030 ins_pipe(ialu_mem_reg);
7031 %}
7033 instruct storeImmN(memory mem, immN src)
7034 %{
7035 match(Set mem (StoreN mem src));
7037 ins_cost(150); // XXX
7038 format %{ "movl $mem, $src\t# compressed ptr" %}
7039 ins_encode %{
7040 address con = (address)$src$$constant;
7041 if (con == NULL) {
7042 __ movl($mem$$Address, (int32_t)0);
7043 } else {
7044 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
7045 }
7046 %}
7047 ins_pipe(ialu_mem_imm);
7048 %}
7050 // Store Integer Immediate
7051 instruct storeImmI0(memory mem, immI0 zero)
7052 %{
7053 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7054 match(Set mem (StoreI mem zero));
7056 ins_cost(125); // XXX
7057 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
7058 ins_encode %{
7059 __ movl($mem$$Address, r12);
7060 %}
7061 ins_pipe(ialu_mem_reg);
7062 %}
7064 instruct storeImmI(memory mem, immI src)
7065 %{
7066 match(Set mem (StoreI mem src));
7068 ins_cost(150);
7069 format %{ "movl $mem, $src\t# int" %}
7070 opcode(0xC7); /* C7 /0 */
7071 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
7072 ins_pipe(ialu_mem_imm);
7073 %}
7075 // Store Long Immediate
7076 instruct storeImmL0(memory mem, immL0 zero)
7077 %{
7078 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7079 match(Set mem (StoreL mem zero));
7081 ins_cost(125); // XXX
7082 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
7083 ins_encode %{
7084 __ movq($mem$$Address, r12);
7085 %}
7086 ins_pipe(ialu_mem_reg);
7087 %}
7089 instruct storeImmL(memory mem, immL32 src)
7090 %{
7091 match(Set mem (StoreL mem src));
7093 ins_cost(150);
7094 format %{ "movq $mem, $src\t# long" %}
7095 opcode(0xC7); /* C7 /0 */
7096 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
7097 ins_pipe(ialu_mem_imm);
7098 %}
7100 // Store Short/Char Immediate
7101 instruct storeImmC0(memory mem, immI0 zero)
7102 %{
7103 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7104 match(Set mem (StoreC mem zero));
7106 ins_cost(125); // XXX
7107 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
7108 ins_encode %{
7109 __ movw($mem$$Address, r12);
7110 %}
7111 ins_pipe(ialu_mem_reg);
7112 %}
7114 instruct storeImmI16(memory mem, immI16 src)
7115 %{
7116 predicate(UseStoreImmI16);
7117 match(Set mem (StoreC mem src));
7119 ins_cost(150);
7120 format %{ "movw $mem, $src\t# short/char" %}
7121 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7122 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
7123 ins_pipe(ialu_mem_imm);
7124 %}
7126 // Store Byte Immediate
7127 instruct storeImmB0(memory mem, immI0 zero)
7128 %{
7129 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7130 match(Set mem (StoreB mem zero));
7132 ins_cost(125); // XXX
7133 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
7134 ins_encode %{
7135 __ movb($mem$$Address, r12);
7136 %}
7137 ins_pipe(ialu_mem_reg);
7138 %}
7140 instruct storeImmB(memory mem, immI8 src)
7141 %{
7142 match(Set mem (StoreB mem src));
7144 ins_cost(150); // XXX
7145 format %{ "movb $mem, $src\t# byte" %}
7146 opcode(0xC6); /* C6 /0 */
7147 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
7148 ins_pipe(ialu_mem_imm);
7149 %}
7151 // Store Aligned Packed Byte XMM register to memory
7152 instruct storeA8B(memory mem, regD src) %{
7153 match(Set mem (Store8B mem src));
7154 ins_cost(145);
7155 format %{ "MOVQ $mem,$src\t! packed8B" %}
7156 ins_encode( movq_st(mem, src));
7157 ins_pipe( pipe_slow );
7158 %}
7160 // Store Aligned Packed Char/Short XMM register to memory
7161 instruct storeA4C(memory mem, regD src) %{
7162 match(Set mem (Store4C mem src));
7163 ins_cost(145);
7164 format %{ "MOVQ $mem,$src\t! packed4C" %}
7165 ins_encode( movq_st(mem, src));
7166 ins_pipe( pipe_slow );
7167 %}
7169 // Store Aligned Packed Integer XMM register to memory
7170 instruct storeA2I(memory mem, regD src) %{
7171 match(Set mem (Store2I mem src));
7172 ins_cost(145);
7173 format %{ "MOVQ $mem,$src\t! packed2I" %}
7174 ins_encode( movq_st(mem, src));
7175 ins_pipe( pipe_slow );
7176 %}
7178 // Store CMS card-mark Immediate
7179 instruct storeImmCM0_reg(memory mem, immI0 zero)
7180 %{
7181 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7182 match(Set mem (StoreCM mem zero));
7184 ins_cost(125); // XXX
7185 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
7186 ins_encode %{
7187 __ movb($mem$$Address, r12);
7188 %}
7189 ins_pipe(ialu_mem_reg);
7190 %}
7192 instruct storeImmCM0(memory mem, immI0 src)
7193 %{
7194 match(Set mem (StoreCM mem src));
7196 ins_cost(150); // XXX
7197 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
7198 opcode(0xC6); /* C6 /0 */
7199 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
7200 ins_pipe(ialu_mem_imm);
7201 %}
7203 // Store Aligned Packed Single Float XMM register to memory
7204 instruct storeA2F(memory mem, regD src) %{
7205 match(Set mem (Store2F mem src));
7206 ins_cost(145);
7207 format %{ "MOVQ $mem,$src\t! packed2F" %}
7208 ins_encode( movq_st(mem, src));
7209 ins_pipe( pipe_slow );
7210 %}
7212 // Store Float
7213 instruct storeF(memory mem, regF src)
7214 %{
7215 match(Set mem (StoreF mem src));
7217 ins_cost(95); // XXX
7218 format %{ "movss $mem, $src\t# float" %}
7219 opcode(0xF3, 0x0F, 0x11);
7220 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
7221 ins_pipe(pipe_slow); // XXX
7222 %}
7224 // Store immediate Float value (it is faster than store from XMM register)
7225 instruct storeF0(memory mem, immF0 zero)
7226 %{
7227 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7228 match(Set mem (StoreF mem zero));
7230 ins_cost(25); // XXX
7231 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
7232 ins_encode %{
7233 __ movl($mem$$Address, r12);
7234 %}
7235 ins_pipe(ialu_mem_reg);
7236 %}
7238 instruct storeF_imm(memory mem, immF src)
7239 %{
7240 match(Set mem (StoreF mem src));
7242 ins_cost(50);
7243 format %{ "movl $mem, $src\t# float" %}
7244 opcode(0xC7); /* C7 /0 */
7245 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
7246 ins_pipe(ialu_mem_imm);
7247 %}
7249 // Store Double
7250 instruct storeD(memory mem, regD src)
7251 %{
7252 match(Set mem (StoreD mem src));
7254 ins_cost(95); // XXX
7255 format %{ "movsd $mem, $src\t# double" %}
7256 opcode(0xF2, 0x0F, 0x11);
7257 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
7258 ins_pipe(pipe_slow); // XXX
7259 %}
7261 // Store immediate double 0.0 (it is faster than store from XMM register)
7262 instruct storeD0_imm(memory mem, immD0 src)
7263 %{
7264 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
7265 match(Set mem (StoreD mem src));
7267 ins_cost(50);
7268 format %{ "movq $mem, $src\t# double 0." %}
7269 opcode(0xC7); /* C7 /0 */
7270 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
7271 ins_pipe(ialu_mem_imm);
7272 %}
7274 instruct storeD0(memory mem, immD0 zero)
7275 %{
7276 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
7277 match(Set mem (StoreD mem zero));
7279 ins_cost(25); // XXX
7280 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
7281 ins_encode %{
7282 __ movq($mem$$Address, r12);
7283 %}
7284 ins_pipe(ialu_mem_reg);
7285 %}
7287 instruct storeSSI(stackSlotI dst, rRegI src)
7288 %{
7289 match(Set dst src);
7291 ins_cost(100);
7292 format %{ "movl $dst, $src\t# int stk" %}
7293 opcode(0x89);
7294 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7295 ins_pipe( ialu_mem_reg );
7296 %}
7298 instruct storeSSL(stackSlotL dst, rRegL src)
7299 %{
7300 match(Set dst src);
7302 ins_cost(100);
7303 format %{ "movq $dst, $src\t# long stk" %}
7304 opcode(0x89);
7305 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7306 ins_pipe(ialu_mem_reg);
7307 %}
7309 instruct storeSSP(stackSlotP dst, rRegP src)
7310 %{
7311 match(Set dst src);
7313 ins_cost(100);
7314 format %{ "movq $dst, $src\t# ptr stk" %}
7315 opcode(0x89);
7316 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7317 ins_pipe(ialu_mem_reg);
7318 %}
7320 instruct storeSSF(stackSlotF dst, regF src)
7321 %{
7322 match(Set dst src);
7324 ins_cost(95); // XXX
7325 format %{ "movss $dst, $src\t# float stk" %}
7326 opcode(0xF3, 0x0F, 0x11);
7327 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
7328 ins_pipe(pipe_slow); // XXX
7329 %}
7331 instruct storeSSD(stackSlotD dst, regD src)
7332 %{
7333 match(Set dst src);
7335 ins_cost(95); // XXX
7336 format %{ "movsd $dst, $src\t# double stk" %}
7337 opcode(0xF2, 0x0F, 0x11);
7338 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
7339 ins_pipe(pipe_slow); // XXX
7340 %}
7342 //----------BSWAP Instructions-------------------------------------------------
7343 instruct bytes_reverse_int(rRegI dst) %{
7344 match(Set dst (ReverseBytesI dst));
7346 format %{ "bswapl $dst" %}
7347 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
7348 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
7349 ins_pipe( ialu_reg );
7350 %}
7352 instruct bytes_reverse_long(rRegL dst) %{
7353 match(Set dst (ReverseBytesL dst));
7355 format %{ "bswapq $dst" %}
7357 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
7358 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
7359 ins_pipe( ialu_reg);
7360 %}
7362 instruct bytes_reverse_unsigned_short(rRegI dst) %{
7363 match(Set dst (ReverseBytesUS dst));
7365 format %{ "bswapl $dst\n\t"
7366 "shrl $dst,16\n\t" %}
7367 ins_encode %{
7368 __ bswapl($dst$$Register);
7369 __ shrl($dst$$Register, 16);
7370 %}
7371 ins_pipe( ialu_reg );
7372 %}
7374 instruct bytes_reverse_short(rRegI dst) %{
7375 match(Set dst (ReverseBytesS dst));
7377 format %{ "bswapl $dst\n\t"
7378 "sar $dst,16\n\t" %}
7379 ins_encode %{
7380 __ bswapl($dst$$Register);
7381 __ sarl($dst$$Register, 16);
7382 %}
7383 ins_pipe( ialu_reg );
7384 %}
7386 instruct loadI_reversed(rRegI dst, memory src) %{
7387 match(Set dst (ReverseBytesI (LoadI src)));
7389 format %{ "bswap_movl $dst, $src" %}
7390 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
7391 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst));
7392 ins_pipe( ialu_reg_mem );
7393 %}
7395 instruct loadL_reversed(rRegL dst, memory src) %{
7396 match(Set dst (ReverseBytesL (LoadL src)));
7398 format %{ "bswap_movq $dst, $src" %}
7399 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
7400 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst));
7401 ins_pipe( ialu_reg_mem );
7402 %}
7404 instruct storeI_reversed(memory dst, rRegI src) %{
7405 match(Set dst (StoreI dst (ReverseBytesI src)));
7407 format %{ "movl_bswap $dst, $src" %}
7408 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7409 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
7410 ins_pipe( ialu_mem_reg );
7411 %}
7413 instruct storeL_reversed(memory dst, rRegL src) %{
7414 match(Set dst (StoreL dst (ReverseBytesL src)));
7416 format %{ "movq_bswap $dst, $src" %}
7417 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7418 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
7419 ins_pipe( ialu_mem_reg );
7420 %}
7423 //---------- Zeros Count Instructions ------------------------------------------
7425 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
7426 predicate(UseCountLeadingZerosInstruction);
7427 match(Set dst (CountLeadingZerosI src));
7428 effect(KILL cr);
7430 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
7431 ins_encode %{
7432 __ lzcntl($dst$$Register, $src$$Register);
7433 %}
7434 ins_pipe(ialu_reg);
7435 %}
7437 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
7438 predicate(!UseCountLeadingZerosInstruction);
7439 match(Set dst (CountLeadingZerosI src));
7440 effect(KILL cr);
7442 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
7443 "jnz skip\n\t"
7444 "movl $dst, -1\n"
7445 "skip:\n\t"
7446 "negl $dst\n\t"
7447 "addl $dst, 31" %}
7448 ins_encode %{
7449 Register Rdst = $dst$$Register;
7450 Register Rsrc = $src$$Register;
7451 Label skip;
7452 __ bsrl(Rdst, Rsrc);
7453 __ jccb(Assembler::notZero, skip);
7454 __ movl(Rdst, -1);
7455 __ bind(skip);
7456 __ negl(Rdst);
7457 __ addl(Rdst, BitsPerInt - 1);
7458 %}
7459 ins_pipe(ialu_reg);
7460 %}
7462 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
7463 predicate(UseCountLeadingZerosInstruction);
7464 match(Set dst (CountLeadingZerosL src));
7465 effect(KILL cr);
7467 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
7468 ins_encode %{
7469 __ lzcntq($dst$$Register, $src$$Register);
7470 %}
7471 ins_pipe(ialu_reg);
7472 %}
7474 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
7475 predicate(!UseCountLeadingZerosInstruction);
7476 match(Set dst (CountLeadingZerosL src));
7477 effect(KILL cr);
7479 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
7480 "jnz skip\n\t"
7481 "movl $dst, -1\n"
7482 "skip:\n\t"
7483 "negl $dst\n\t"
7484 "addl $dst, 63" %}
7485 ins_encode %{
7486 Register Rdst = $dst$$Register;
7487 Register Rsrc = $src$$Register;
7488 Label skip;
7489 __ bsrq(Rdst, Rsrc);
7490 __ jccb(Assembler::notZero, skip);
7491 __ movl(Rdst, -1);
7492 __ bind(skip);
7493 __ negl(Rdst);
7494 __ addl(Rdst, BitsPerLong - 1);
7495 %}
7496 ins_pipe(ialu_reg);
7497 %}
7499 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
7500 match(Set dst (CountTrailingZerosI src));
7501 effect(KILL cr);
7503 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
7504 "jnz done\n\t"
7505 "movl $dst, 32\n"
7506 "done:" %}
7507 ins_encode %{
7508 Register Rdst = $dst$$Register;
7509 Label done;
7510 __ bsfl(Rdst, $src$$Register);
7511 __ jccb(Assembler::notZero, done);
7512 __ movl(Rdst, BitsPerInt);
7513 __ bind(done);
7514 %}
7515 ins_pipe(ialu_reg);
7516 %}
7518 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
7519 match(Set dst (CountTrailingZerosL src));
7520 effect(KILL cr);
7522 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
7523 "jnz done\n\t"
7524 "movl $dst, 64\n"
7525 "done:" %}
7526 ins_encode %{
7527 Register Rdst = $dst$$Register;
7528 Label done;
7529 __ bsfq(Rdst, $src$$Register);
7530 __ jccb(Assembler::notZero, done);
7531 __ movl(Rdst, BitsPerLong);
7532 __ bind(done);
7533 %}
7534 ins_pipe(ialu_reg);
7535 %}
7538 //---------- Population Count Instructions -------------------------------------
7540 instruct popCountI(rRegI dst, rRegI src) %{
7541 predicate(UsePopCountInstruction);
7542 match(Set dst (PopCountI src));
7544 format %{ "popcnt $dst, $src" %}
7545 ins_encode %{
7546 __ popcntl($dst$$Register, $src$$Register);
7547 %}
7548 ins_pipe(ialu_reg);
7549 %}
7551 instruct popCountI_mem(rRegI dst, memory mem) %{
7552 predicate(UsePopCountInstruction);
7553 match(Set dst (PopCountI (LoadI mem)));
7555 format %{ "popcnt $dst, $mem" %}
7556 ins_encode %{
7557 __ popcntl($dst$$Register, $mem$$Address);
7558 %}
7559 ins_pipe(ialu_reg);
7560 %}
7562 // Note: Long.bitCount(long) returns an int.
7563 instruct popCountL(rRegI dst, rRegL src) %{
7564 predicate(UsePopCountInstruction);
7565 match(Set dst (PopCountL src));
7567 format %{ "popcnt $dst, $src" %}
7568 ins_encode %{
7569 __ popcntq($dst$$Register, $src$$Register);
7570 %}
7571 ins_pipe(ialu_reg);
7572 %}
7574 // Note: Long.bitCount(long) returns an int.
7575 instruct popCountL_mem(rRegI dst, memory mem) %{
7576 predicate(UsePopCountInstruction);
7577 match(Set dst (PopCountL (LoadL mem)));
7579 format %{ "popcnt $dst, $mem" %}
7580 ins_encode %{
7581 __ popcntq($dst$$Register, $mem$$Address);
7582 %}
7583 ins_pipe(ialu_reg);
7584 %}
7587 //----------MemBar Instructions-----------------------------------------------
7588 // Memory barrier flavors
7590 instruct membar_acquire()
7591 %{
7592 match(MemBarAcquire);
7593 ins_cost(0);
7595 size(0);
7596 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7597 ins_encode();
7598 ins_pipe(empty);
7599 %}
7601 instruct membar_acquire_lock()
7602 %{
7603 match(MemBarAcquire);
7604 predicate(Matcher::prior_fast_lock(n));
7605 ins_cost(0);
7607 size(0);
7608 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7609 ins_encode();
7610 ins_pipe(empty);
7611 %}
7613 instruct membar_release()
7614 %{
7615 match(MemBarRelease);
7616 ins_cost(0);
7618 size(0);
7619 format %{ "MEMBAR-release ! (empty encoding)" %}
7620 ins_encode();
7621 ins_pipe(empty);
7622 %}
7624 instruct membar_release_lock()
7625 %{
7626 match(MemBarRelease);
7627 predicate(Matcher::post_fast_unlock(n));
7628 ins_cost(0);
7630 size(0);
7631 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7632 ins_encode();
7633 ins_pipe(empty);
7634 %}
7636 instruct membar_volatile(rFlagsReg cr) %{
7637 match(MemBarVolatile);
7638 effect(KILL cr);
7639 ins_cost(400);
7641 format %{
7642 $$template
7643 if (os::is_MP()) {
7644 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
7645 } else {
7646 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7647 }
7648 %}
7649 ins_encode %{
7650 __ membar(Assembler::StoreLoad);
7651 %}
7652 ins_pipe(pipe_slow);
7653 %}
7655 instruct unnecessary_membar_volatile()
7656 %{
7657 match(MemBarVolatile);
7658 predicate(Matcher::post_store_load_barrier(n));
7659 ins_cost(0);
7661 size(0);
7662 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7663 ins_encode();
7664 ins_pipe(empty);
7665 %}
7667 //----------Move Instructions--------------------------------------------------
7669 instruct castX2P(rRegP dst, rRegL src)
7670 %{
7671 match(Set dst (CastX2P src));
7673 format %{ "movq $dst, $src\t# long->ptr" %}
7674 ins_encode(enc_copy_wide(dst, src));
7675 ins_pipe(ialu_reg_reg); // XXX
7676 %}
7678 instruct castP2X(rRegL dst, rRegP src)
7679 %{
7680 match(Set dst (CastP2X src));
7682 format %{ "movq $dst, $src\t# ptr -> long" %}
7683 ins_encode(enc_copy_wide(dst, src));
7684 ins_pipe(ialu_reg_reg); // XXX
7685 %}
7688 // Convert oop pointer into compressed form
7689 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
7690 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
7691 match(Set dst (EncodeP src));
7692 effect(KILL cr);
7693 format %{ "encode_heap_oop $dst,$src" %}
7694 ins_encode %{
7695 Register s = $src$$Register;
7696 Register d = $dst$$Register;
7697 if (s != d) {
7698 __ movq(d, s);
7699 }
7700 __ encode_heap_oop(d);
7701 %}
7702 ins_pipe(ialu_reg_long);
7703 %}
7705 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7706 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
7707 match(Set dst (EncodeP src));
7708 effect(KILL cr);
7709 format %{ "encode_heap_oop_not_null $dst,$src" %}
7710 ins_encode %{
7711 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
7712 %}
7713 ins_pipe(ialu_reg_long);
7714 %}
7716 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7717 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
7718 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
7719 match(Set dst (DecodeN src));
7720 effect(KILL cr);
7721 format %{ "decode_heap_oop $dst,$src" %}
7722 ins_encode %{
7723 Register s = $src$$Register;
7724 Register d = $dst$$Register;
7725 if (s != d) {
7726 __ movq(d, s);
7727 }
7728 __ decode_heap_oop(d);
7729 %}
7730 ins_pipe(ialu_reg_long);
7731 %}
7733 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
7734 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
7735 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
7736 match(Set dst (DecodeN src));
7737 effect(KILL cr);
7738 format %{ "decode_heap_oop_not_null $dst,$src" %}
7739 ins_encode %{
7740 Register s = $src$$Register;
7741 Register d = $dst$$Register;
7742 if (s != d) {
7743 __ decode_heap_oop_not_null(d, s);
7744 } else {
7745 __ decode_heap_oop_not_null(d);
7746 }
7747 %}
7748 ins_pipe(ialu_reg_long);
7749 %}
7752 //----------Conditional Move---------------------------------------------------
7753 // Jump
7754 // dummy instruction for generating temp registers
7755 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7756 match(Jump (LShiftL switch_val shift));
7757 ins_cost(350);
7758 predicate(false);
7759 effect(TEMP dest);
7761 format %{ "leaq $dest, table_base\n\t"
7762 "jmp [$dest + $switch_val << $shift]\n\t" %}
7763 ins_encode(jump_enc_offset(switch_val, shift, dest));
7764 ins_pipe(pipe_jmp);
7765 ins_pc_relative(1);
7766 %}
7768 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7769 match(Jump (AddL (LShiftL switch_val shift) offset));
7770 ins_cost(350);
7771 effect(TEMP dest);
7773 format %{ "leaq $dest, table_base\n\t"
7774 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7775 ins_encode(jump_enc_addr(switch_val, shift, offset, dest));
7776 ins_pipe(pipe_jmp);
7777 ins_pc_relative(1);
7778 %}
7780 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7781 match(Jump switch_val);
7782 ins_cost(350);
7783 effect(TEMP dest);
7785 format %{ "leaq $dest, table_base\n\t"
7786 "jmp [$dest + $switch_val]\n\t" %}
7787 ins_encode(jump_enc(switch_val, dest));
7788 ins_pipe(pipe_jmp);
7789 ins_pc_relative(1);
7790 %}
7792 // Conditional move
7793 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7794 %{
7795 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7797 ins_cost(200); // XXX
7798 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7799 opcode(0x0F, 0x40);
7800 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7801 ins_pipe(pipe_cmov_reg);
7802 %}
7804 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7805 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7807 ins_cost(200); // XXX
7808 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7809 opcode(0x0F, 0x40);
7810 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7811 ins_pipe(pipe_cmov_reg);
7812 %}
7814 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7815 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7816 ins_cost(200);
7817 expand %{
7818 cmovI_regU(cop, cr, dst, src);
7819 %}
7820 %}
7822 // Conditional move
7823 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7824 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7826 ins_cost(250); // XXX
7827 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7828 opcode(0x0F, 0x40);
7829 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7830 ins_pipe(pipe_cmov_mem);
7831 %}
7833 // Conditional move
7834 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7835 %{
7836 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7838 ins_cost(250); // XXX
7839 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7840 opcode(0x0F, 0x40);
7841 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7842 ins_pipe(pipe_cmov_mem);
7843 %}
7845 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7846 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7847 ins_cost(250);
7848 expand %{
7849 cmovI_memU(cop, cr, dst, src);
7850 %}
7851 %}
7853 // Conditional move
7854 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7855 %{
7856 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7858 ins_cost(200); // XXX
7859 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7860 opcode(0x0F, 0x40);
7861 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7862 ins_pipe(pipe_cmov_reg);
7863 %}
7865 // Conditional move
7866 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7867 %{
7868 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7870 ins_cost(200); // XXX
7871 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7872 opcode(0x0F, 0x40);
7873 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7874 ins_pipe(pipe_cmov_reg);
7875 %}
7877 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7878 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7879 ins_cost(200);
7880 expand %{
7881 cmovN_regU(cop, cr, dst, src);
7882 %}
7883 %}
7885 // Conditional move
7886 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7887 %{
7888 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7890 ins_cost(200); // XXX
7891 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7892 opcode(0x0F, 0x40);
7893 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7894 ins_pipe(pipe_cmov_reg); // XXX
7895 %}
7897 // Conditional move
7898 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7899 %{
7900 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7902 ins_cost(200); // XXX
7903 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7904 opcode(0x0F, 0x40);
7905 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7906 ins_pipe(pipe_cmov_reg); // XXX
7907 %}
7909 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7910 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7911 ins_cost(200);
7912 expand %{
7913 cmovP_regU(cop, cr, dst, src);
7914 %}
7915 %}
7917 // DISABLED: Requires the ADLC to emit a bottom_type call that
7918 // correctly meets the two pointer arguments; one is an incoming
7919 // register but the other is a memory operand. ALSO appears to
7920 // be buggy with implicit null checks.
7921 //
7922 //// Conditional move
7923 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7924 //%{
7925 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7926 // ins_cost(250);
7927 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7928 // opcode(0x0F,0x40);
7929 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7930 // ins_pipe( pipe_cmov_mem );
7931 //%}
7932 //
7933 //// Conditional move
7934 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7935 //%{
7936 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7937 // ins_cost(250);
7938 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7939 // opcode(0x0F,0x40);
7940 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7941 // ins_pipe( pipe_cmov_mem );
7942 //%}
7944 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7945 %{
7946 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7948 ins_cost(200); // XXX
7949 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7950 opcode(0x0F, 0x40);
7951 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7952 ins_pipe(pipe_cmov_reg); // XXX
7953 %}
7955 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7956 %{
7957 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7959 ins_cost(200); // XXX
7960 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7961 opcode(0x0F, 0x40);
7962 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7963 ins_pipe(pipe_cmov_mem); // XXX
7964 %}
7966 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7967 %{
7968 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7970 ins_cost(200); // XXX
7971 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7972 opcode(0x0F, 0x40);
7973 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7974 ins_pipe(pipe_cmov_reg); // XXX
7975 %}
7977 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7978 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7979 ins_cost(200);
7980 expand %{
7981 cmovL_regU(cop, cr, dst, src);
7982 %}
7983 %}
7985 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7986 %{
7987 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7989 ins_cost(200); // XXX
7990 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7991 opcode(0x0F, 0x40);
7992 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7993 ins_pipe(pipe_cmov_mem); // XXX
7994 %}
7996 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7997 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7998 ins_cost(200);
7999 expand %{
8000 cmovL_memU(cop, cr, dst, src);
8001 %}
8002 %}
8004 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
8005 %{
8006 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8008 ins_cost(200); // XXX
8009 format %{ "jn$cop skip\t# signed cmove float\n\t"
8010 "movss $dst, $src\n"
8011 "skip:" %}
8012 ins_encode(enc_cmovf_branch(cop, dst, src));
8013 ins_pipe(pipe_slow);
8014 %}
8016 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
8017 // %{
8018 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
8020 // ins_cost(200); // XXX
8021 // format %{ "jn$cop skip\t# signed cmove float\n\t"
8022 // "movss $dst, $src\n"
8023 // "skip:" %}
8024 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
8025 // ins_pipe(pipe_slow);
8026 // %}
8028 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
8029 %{
8030 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8032 ins_cost(200); // XXX
8033 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
8034 "movss $dst, $src\n"
8035 "skip:" %}
8036 ins_encode(enc_cmovf_branch(cop, dst, src));
8037 ins_pipe(pipe_slow);
8038 %}
8040 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
8041 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8042 ins_cost(200);
8043 expand %{
8044 cmovF_regU(cop, cr, dst, src);
8045 %}
8046 %}
8048 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
8049 %{
8050 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8052 ins_cost(200); // XXX
8053 format %{ "jn$cop skip\t# signed cmove double\n\t"
8054 "movsd $dst, $src\n"
8055 "skip:" %}
8056 ins_encode(enc_cmovd_branch(cop, dst, src));
8057 ins_pipe(pipe_slow);
8058 %}
8060 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
8061 %{
8062 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8064 ins_cost(200); // XXX
8065 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
8066 "movsd $dst, $src\n"
8067 "skip:" %}
8068 ins_encode(enc_cmovd_branch(cop, dst, src));
8069 ins_pipe(pipe_slow);
8070 %}
8072 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
8073 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8074 ins_cost(200);
8075 expand %{
8076 cmovD_regU(cop, cr, dst, src);
8077 %}
8078 %}
8080 //----------Arithmetic Instructions--------------------------------------------
8081 //----------Addition Instructions----------------------------------------------
8083 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8084 %{
8085 match(Set dst (AddI dst src));
8086 effect(KILL cr);
8088 format %{ "addl $dst, $src\t# int" %}
8089 opcode(0x03);
8090 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8091 ins_pipe(ialu_reg_reg);
8092 %}
8094 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8095 %{
8096 match(Set dst (AddI dst src));
8097 effect(KILL cr);
8099 format %{ "addl $dst, $src\t# int" %}
8100 opcode(0x81, 0x00); /* /0 id */
8101 ins_encode(OpcSErm(dst, src), Con8or32(src));
8102 ins_pipe( ialu_reg );
8103 %}
8105 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8106 %{
8107 match(Set dst (AddI dst (LoadI src)));
8108 effect(KILL cr);
8110 ins_cost(125); // XXX
8111 format %{ "addl $dst, $src\t# int" %}
8112 opcode(0x03);
8113 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8114 ins_pipe(ialu_reg_mem);
8115 %}
8117 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8118 %{
8119 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8120 effect(KILL cr);
8122 ins_cost(150); // XXX
8123 format %{ "addl $dst, $src\t# int" %}
8124 opcode(0x01); /* Opcode 01 /r */
8125 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8126 ins_pipe(ialu_mem_reg);
8127 %}
8129 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
8130 %{
8131 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8132 effect(KILL cr);
8134 ins_cost(125); // XXX
8135 format %{ "addl $dst, $src\t# int" %}
8136 opcode(0x81); /* Opcode 81 /0 id */
8137 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
8138 ins_pipe(ialu_mem_imm);
8139 %}
8141 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
8142 %{
8143 predicate(UseIncDec);
8144 match(Set dst (AddI dst src));
8145 effect(KILL cr);
8147 format %{ "incl $dst\t# int" %}
8148 opcode(0xFF, 0x00); // FF /0
8149 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8150 ins_pipe(ialu_reg);
8151 %}
8153 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
8154 %{
8155 predicate(UseIncDec);
8156 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8157 effect(KILL cr);
8159 ins_cost(125); // XXX
8160 format %{ "incl $dst\t# int" %}
8161 opcode(0xFF); /* Opcode FF /0 */
8162 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
8163 ins_pipe(ialu_mem_imm);
8164 %}
8166 // XXX why does that use AddI
8167 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
8168 %{
8169 predicate(UseIncDec);
8170 match(Set dst (AddI dst src));
8171 effect(KILL cr);
8173 format %{ "decl $dst\t# int" %}
8174 opcode(0xFF, 0x01); // FF /1
8175 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8176 ins_pipe(ialu_reg);
8177 %}
8179 // XXX why does that use AddI
8180 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
8181 %{
8182 predicate(UseIncDec);
8183 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8184 effect(KILL cr);
8186 ins_cost(125); // XXX
8187 format %{ "decl $dst\t# int" %}
8188 opcode(0xFF); /* Opcode FF /1 */
8189 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
8190 ins_pipe(ialu_mem_imm);
8191 %}
8193 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
8194 %{
8195 match(Set dst (AddI src0 src1));
8197 ins_cost(110);
8198 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
8199 opcode(0x8D); /* 0x8D /r */
8200 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
8201 ins_pipe(ialu_reg_reg);
8202 %}
8204 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8205 %{
8206 match(Set dst (AddL dst src));
8207 effect(KILL cr);
8209 format %{ "addq $dst, $src\t# long" %}
8210 opcode(0x03);
8211 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8212 ins_pipe(ialu_reg_reg);
8213 %}
8215 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8216 %{
8217 match(Set dst (AddL dst src));
8218 effect(KILL cr);
8220 format %{ "addq $dst, $src\t# long" %}
8221 opcode(0x81, 0x00); /* /0 id */
8222 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8223 ins_pipe( ialu_reg );
8224 %}
8226 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8227 %{
8228 match(Set dst (AddL dst (LoadL src)));
8229 effect(KILL cr);
8231 ins_cost(125); // XXX
8232 format %{ "addq $dst, $src\t# long" %}
8233 opcode(0x03);
8234 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8235 ins_pipe(ialu_reg_mem);
8236 %}
8238 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8239 %{
8240 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8241 effect(KILL cr);
8243 ins_cost(150); // XXX
8244 format %{ "addq $dst, $src\t# long" %}
8245 opcode(0x01); /* Opcode 01 /r */
8246 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8247 ins_pipe(ialu_mem_reg);
8248 %}
8250 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8251 %{
8252 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8253 effect(KILL cr);
8255 ins_cost(125); // XXX
8256 format %{ "addq $dst, $src\t# long" %}
8257 opcode(0x81); /* Opcode 81 /0 id */
8258 ins_encode(REX_mem_wide(dst),
8259 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
8260 ins_pipe(ialu_mem_imm);
8261 %}
8263 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
8264 %{
8265 predicate(UseIncDec);
8266 match(Set dst (AddL dst src));
8267 effect(KILL cr);
8269 format %{ "incq $dst\t# long" %}
8270 opcode(0xFF, 0x00); // FF /0
8271 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8272 ins_pipe(ialu_reg);
8273 %}
8275 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
8276 %{
8277 predicate(UseIncDec);
8278 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8279 effect(KILL cr);
8281 ins_cost(125); // XXX
8282 format %{ "incq $dst\t# long" %}
8283 opcode(0xFF); /* Opcode FF /0 */
8284 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
8285 ins_pipe(ialu_mem_imm);
8286 %}
8288 // XXX why does that use AddL
8289 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
8290 %{
8291 predicate(UseIncDec);
8292 match(Set dst (AddL dst src));
8293 effect(KILL cr);
8295 format %{ "decq $dst\t# long" %}
8296 opcode(0xFF, 0x01); // FF /1
8297 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8298 ins_pipe(ialu_reg);
8299 %}
8301 // XXX why does that use AddL
8302 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
8303 %{
8304 predicate(UseIncDec);
8305 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8306 effect(KILL cr);
8308 ins_cost(125); // XXX
8309 format %{ "decq $dst\t# long" %}
8310 opcode(0xFF); /* Opcode FF /1 */
8311 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
8312 ins_pipe(ialu_mem_imm);
8313 %}
8315 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
8316 %{
8317 match(Set dst (AddL src0 src1));
8319 ins_cost(110);
8320 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
8321 opcode(0x8D); /* 0x8D /r */
8322 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
8323 ins_pipe(ialu_reg_reg);
8324 %}
8326 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
8327 %{
8328 match(Set dst (AddP dst src));
8329 effect(KILL cr);
8331 format %{ "addq $dst, $src\t# ptr" %}
8332 opcode(0x03);
8333 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8334 ins_pipe(ialu_reg_reg);
8335 %}
8337 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
8338 %{
8339 match(Set dst (AddP dst src));
8340 effect(KILL cr);
8342 format %{ "addq $dst, $src\t# ptr" %}
8343 opcode(0x81, 0x00); /* /0 id */
8344 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8345 ins_pipe( ialu_reg );
8346 %}
8348 // XXX addP mem ops ????
8350 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
8351 %{
8352 match(Set dst (AddP src0 src1));
8354 ins_cost(110);
8355 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
8356 opcode(0x8D); /* 0x8D /r */
8357 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
8358 ins_pipe(ialu_reg_reg);
8359 %}
8361 instruct checkCastPP(rRegP dst)
8362 %{
8363 match(Set dst (CheckCastPP dst));
8365 size(0);
8366 format %{ "# checkcastPP of $dst" %}
8367 ins_encode(/* empty encoding */);
8368 ins_pipe(empty);
8369 %}
8371 instruct castPP(rRegP dst)
8372 %{
8373 match(Set dst (CastPP dst));
8375 size(0);
8376 format %{ "# castPP of $dst" %}
8377 ins_encode(/* empty encoding */);
8378 ins_pipe(empty);
8379 %}
8381 instruct castII(rRegI dst)
8382 %{
8383 match(Set dst (CastII dst));
8385 size(0);
8386 format %{ "# castII of $dst" %}
8387 ins_encode(/* empty encoding */);
8388 ins_cost(0);
8389 ins_pipe(empty);
8390 %}
8392 // LoadP-locked same as a regular LoadP when used with compare-swap
8393 instruct loadPLocked(rRegP dst, memory mem)
8394 %{
8395 match(Set dst (LoadPLocked mem));
8397 ins_cost(125); // XXX
8398 format %{ "movq $dst, $mem\t# ptr locked" %}
8399 opcode(0x8B);
8400 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
8401 ins_pipe(ialu_reg_mem); // XXX
8402 %}
8404 // LoadL-locked - same as a regular LoadL when used with compare-swap
8405 instruct loadLLocked(rRegL dst, memory mem)
8406 %{
8407 match(Set dst (LoadLLocked mem));
8409 ins_cost(125); // XXX
8410 format %{ "movq $dst, $mem\t# long locked" %}
8411 opcode(0x8B);
8412 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
8413 ins_pipe(ialu_reg_mem); // XXX
8414 %}
8416 // Conditional-store of the updated heap-top.
8417 // Used during allocation of the shared heap.
8418 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8420 instruct storePConditional(memory heap_top_ptr,
8421 rax_RegP oldval, rRegP newval,
8422 rFlagsReg cr)
8423 %{
8424 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8426 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
8427 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
8428 opcode(0x0F, 0xB1);
8429 ins_encode(lock_prefix,
8430 REX_reg_mem_wide(newval, heap_top_ptr),
8431 OpcP, OpcS,
8432 reg_mem(newval, heap_top_ptr));
8433 ins_pipe(pipe_cmpxchg);
8434 %}
8436 // Conditional-store of an int value.
8437 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
8438 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
8439 %{
8440 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8441 effect(KILL oldval);
8443 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
8444 opcode(0x0F, 0xB1);
8445 ins_encode(lock_prefix,
8446 REX_reg_mem(newval, mem),
8447 OpcP, OpcS,
8448 reg_mem(newval, mem));
8449 ins_pipe(pipe_cmpxchg);
8450 %}
8452 // Conditional-store of a long value.
8453 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
8454 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
8455 %{
8456 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8457 effect(KILL oldval);
8459 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
8460 opcode(0x0F, 0xB1);
8461 ins_encode(lock_prefix,
8462 REX_reg_mem_wide(newval, mem),
8463 OpcP, OpcS,
8464 reg_mem(newval, mem));
8465 ins_pipe(pipe_cmpxchg);
8466 %}
8469 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8470 instruct compareAndSwapP(rRegI res,
8471 memory mem_ptr,
8472 rax_RegP oldval, rRegP newval,
8473 rFlagsReg cr)
8474 %{
8475 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8476 effect(KILL cr, KILL oldval);
8478 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8479 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8480 "sete $res\n\t"
8481 "movzbl $res, $res" %}
8482 opcode(0x0F, 0xB1);
8483 ins_encode(lock_prefix,
8484 REX_reg_mem_wide(newval, mem_ptr),
8485 OpcP, OpcS,
8486 reg_mem(newval, mem_ptr),
8487 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8488 REX_reg_breg(res, res), // movzbl
8489 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8490 ins_pipe( pipe_cmpxchg );
8491 %}
8493 instruct compareAndSwapL(rRegI res,
8494 memory mem_ptr,
8495 rax_RegL oldval, rRegL newval,
8496 rFlagsReg cr)
8497 %{
8498 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8499 effect(KILL cr, KILL oldval);
8501 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8502 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8503 "sete $res\n\t"
8504 "movzbl $res, $res" %}
8505 opcode(0x0F, 0xB1);
8506 ins_encode(lock_prefix,
8507 REX_reg_mem_wide(newval, mem_ptr),
8508 OpcP, OpcS,
8509 reg_mem(newval, mem_ptr),
8510 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8511 REX_reg_breg(res, res), // movzbl
8512 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8513 ins_pipe( pipe_cmpxchg );
8514 %}
8516 instruct compareAndSwapI(rRegI res,
8517 memory mem_ptr,
8518 rax_RegI oldval, rRegI newval,
8519 rFlagsReg cr)
8520 %{
8521 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8522 effect(KILL cr, KILL oldval);
8524 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8525 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8526 "sete $res\n\t"
8527 "movzbl $res, $res" %}
8528 opcode(0x0F, 0xB1);
8529 ins_encode(lock_prefix,
8530 REX_reg_mem(newval, mem_ptr),
8531 OpcP, OpcS,
8532 reg_mem(newval, mem_ptr),
8533 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8534 REX_reg_breg(res, res), // movzbl
8535 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8536 ins_pipe( pipe_cmpxchg );
8537 %}
8540 instruct compareAndSwapN(rRegI res,
8541 memory mem_ptr,
8542 rax_RegN oldval, rRegN newval,
8543 rFlagsReg cr) %{
8544 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
8545 effect(KILL cr, KILL oldval);
8547 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8548 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8549 "sete $res\n\t"
8550 "movzbl $res, $res" %}
8551 opcode(0x0F, 0xB1);
8552 ins_encode(lock_prefix,
8553 REX_reg_mem(newval, mem_ptr),
8554 OpcP, OpcS,
8555 reg_mem(newval, mem_ptr),
8556 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8557 REX_reg_breg(res, res), // movzbl
8558 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8559 ins_pipe( pipe_cmpxchg );
8560 %}
8562 //----------Subtraction Instructions-------------------------------------------
8564 // Integer Subtraction Instructions
8565 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8566 %{
8567 match(Set dst (SubI dst src));
8568 effect(KILL cr);
8570 format %{ "subl $dst, $src\t# int" %}
8571 opcode(0x2B);
8572 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8573 ins_pipe(ialu_reg_reg);
8574 %}
8576 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8577 %{
8578 match(Set dst (SubI dst src));
8579 effect(KILL cr);
8581 format %{ "subl $dst, $src\t# int" %}
8582 opcode(0x81, 0x05); /* Opcode 81 /5 */
8583 ins_encode(OpcSErm(dst, src), Con8or32(src));
8584 ins_pipe(ialu_reg);
8585 %}
8587 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8588 %{
8589 match(Set dst (SubI dst (LoadI src)));
8590 effect(KILL cr);
8592 ins_cost(125);
8593 format %{ "subl $dst, $src\t# int" %}
8594 opcode(0x2B);
8595 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8596 ins_pipe(ialu_reg_mem);
8597 %}
8599 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8600 %{
8601 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8602 effect(KILL cr);
8604 ins_cost(150);
8605 format %{ "subl $dst, $src\t# int" %}
8606 opcode(0x29); /* Opcode 29 /r */
8607 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8608 ins_pipe(ialu_mem_reg);
8609 %}
8611 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8612 %{
8613 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8614 effect(KILL cr);
8616 ins_cost(125); // XXX
8617 format %{ "subl $dst, $src\t# int" %}
8618 opcode(0x81); /* Opcode 81 /5 id */
8619 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8620 ins_pipe(ialu_mem_imm);
8621 %}
8623 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8624 %{
8625 match(Set dst (SubL dst src));
8626 effect(KILL cr);
8628 format %{ "subq $dst, $src\t# long" %}
8629 opcode(0x2B);
8630 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8631 ins_pipe(ialu_reg_reg);
8632 %}
8634 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8635 %{
8636 match(Set dst (SubL dst src));
8637 effect(KILL cr);
8639 format %{ "subq $dst, $src\t# long" %}
8640 opcode(0x81, 0x05); /* Opcode 81 /5 */
8641 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8642 ins_pipe(ialu_reg);
8643 %}
8645 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8646 %{
8647 match(Set dst (SubL dst (LoadL src)));
8648 effect(KILL cr);
8650 ins_cost(125);
8651 format %{ "subq $dst, $src\t# long" %}
8652 opcode(0x2B);
8653 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8654 ins_pipe(ialu_reg_mem);
8655 %}
8657 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8658 %{
8659 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8660 effect(KILL cr);
8662 ins_cost(150);
8663 format %{ "subq $dst, $src\t# long" %}
8664 opcode(0x29); /* Opcode 29 /r */
8665 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8666 ins_pipe(ialu_mem_reg);
8667 %}
8669 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8670 %{
8671 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8672 effect(KILL cr);
8674 ins_cost(125); // XXX
8675 format %{ "subq $dst, $src\t# long" %}
8676 opcode(0x81); /* Opcode 81 /5 id */
8677 ins_encode(REX_mem_wide(dst),
8678 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8679 ins_pipe(ialu_mem_imm);
8680 %}
8682 // Subtract from a pointer
8683 // XXX hmpf???
8684 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8685 %{
8686 match(Set dst (AddP dst (SubI zero src)));
8687 effect(KILL cr);
8689 format %{ "subq $dst, $src\t# ptr - int" %}
8690 opcode(0x2B);
8691 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8692 ins_pipe(ialu_reg_reg);
8693 %}
8695 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8696 %{
8697 match(Set dst (SubI zero dst));
8698 effect(KILL cr);
8700 format %{ "negl $dst\t# int" %}
8701 opcode(0xF7, 0x03); // Opcode F7 /3
8702 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8703 ins_pipe(ialu_reg);
8704 %}
8706 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8707 %{
8708 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8709 effect(KILL cr);
8711 format %{ "negl $dst\t# int" %}
8712 opcode(0xF7, 0x03); // Opcode F7 /3
8713 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8714 ins_pipe(ialu_reg);
8715 %}
8717 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8718 %{
8719 match(Set dst (SubL zero dst));
8720 effect(KILL cr);
8722 format %{ "negq $dst\t# long" %}
8723 opcode(0xF7, 0x03); // Opcode F7 /3
8724 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8725 ins_pipe(ialu_reg);
8726 %}
8728 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8729 %{
8730 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8731 effect(KILL cr);
8733 format %{ "negq $dst\t# long" %}
8734 opcode(0xF7, 0x03); // Opcode F7 /3
8735 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8736 ins_pipe(ialu_reg);
8737 %}
8740 //----------Multiplication/Division Instructions-------------------------------
8741 // Integer Multiplication Instructions
8742 // Multiply Register
8744 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8745 %{
8746 match(Set dst (MulI dst src));
8747 effect(KILL cr);
8749 ins_cost(300);
8750 format %{ "imull $dst, $src\t# int" %}
8751 opcode(0x0F, 0xAF);
8752 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8753 ins_pipe(ialu_reg_reg_alu0);
8754 %}
8756 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8757 %{
8758 match(Set dst (MulI src imm));
8759 effect(KILL cr);
8761 ins_cost(300);
8762 format %{ "imull $dst, $src, $imm\t# int" %}
8763 opcode(0x69); /* 69 /r id */
8764 ins_encode(REX_reg_reg(dst, src),
8765 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8766 ins_pipe(ialu_reg_reg_alu0);
8767 %}
8769 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8770 %{
8771 match(Set dst (MulI dst (LoadI src)));
8772 effect(KILL cr);
8774 ins_cost(350);
8775 format %{ "imull $dst, $src\t# int" %}
8776 opcode(0x0F, 0xAF);
8777 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8778 ins_pipe(ialu_reg_mem_alu0);
8779 %}
8781 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8782 %{
8783 match(Set dst (MulI (LoadI src) imm));
8784 effect(KILL cr);
8786 ins_cost(300);
8787 format %{ "imull $dst, $src, $imm\t# int" %}
8788 opcode(0x69); /* 69 /r id */
8789 ins_encode(REX_reg_mem(dst, src),
8790 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8791 ins_pipe(ialu_reg_mem_alu0);
8792 %}
8794 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8795 %{
8796 match(Set dst (MulL dst src));
8797 effect(KILL cr);
8799 ins_cost(300);
8800 format %{ "imulq $dst, $src\t# long" %}
8801 opcode(0x0F, 0xAF);
8802 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8803 ins_pipe(ialu_reg_reg_alu0);
8804 %}
8806 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8807 %{
8808 match(Set dst (MulL src imm));
8809 effect(KILL cr);
8811 ins_cost(300);
8812 format %{ "imulq $dst, $src, $imm\t# long" %}
8813 opcode(0x69); /* 69 /r id */
8814 ins_encode(REX_reg_reg_wide(dst, src),
8815 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8816 ins_pipe(ialu_reg_reg_alu0);
8817 %}
8819 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8820 %{
8821 match(Set dst (MulL dst (LoadL src)));
8822 effect(KILL cr);
8824 ins_cost(350);
8825 format %{ "imulq $dst, $src\t# long" %}
8826 opcode(0x0F, 0xAF);
8827 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8828 ins_pipe(ialu_reg_mem_alu0);
8829 %}
8831 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8832 %{
8833 match(Set dst (MulL (LoadL src) imm));
8834 effect(KILL cr);
8836 ins_cost(300);
8837 format %{ "imulq $dst, $src, $imm\t# long" %}
8838 opcode(0x69); /* 69 /r id */
8839 ins_encode(REX_reg_mem_wide(dst, src),
8840 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8841 ins_pipe(ialu_reg_mem_alu0);
8842 %}
8844 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8845 %{
8846 match(Set dst (MulHiL src rax));
8847 effect(USE_KILL rax, KILL cr);
8849 ins_cost(300);
8850 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8851 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8852 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8853 ins_pipe(ialu_reg_reg_alu0);
8854 %}
8856 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8857 rFlagsReg cr)
8858 %{
8859 match(Set rax (DivI rax div));
8860 effect(KILL rdx, KILL cr);
8862 ins_cost(30*100+10*100); // XXX
8863 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8864 "jne,s normal\n\t"
8865 "xorl rdx, rdx\n\t"
8866 "cmpl $div, -1\n\t"
8867 "je,s done\n"
8868 "normal: cdql\n\t"
8869 "idivl $div\n"
8870 "done:" %}
8871 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8872 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8873 ins_pipe(ialu_reg_reg_alu0);
8874 %}
8876 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8877 rFlagsReg cr)
8878 %{
8879 match(Set rax (DivL rax div));
8880 effect(KILL rdx, KILL cr);
8882 ins_cost(30*100+10*100); // XXX
8883 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8884 "cmpq rax, rdx\n\t"
8885 "jne,s normal\n\t"
8886 "xorl rdx, rdx\n\t"
8887 "cmpq $div, -1\n\t"
8888 "je,s done\n"
8889 "normal: cdqq\n\t"
8890 "idivq $div\n"
8891 "done:" %}
8892 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8893 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8894 ins_pipe(ialu_reg_reg_alu0);
8895 %}
8897 // Integer DIVMOD with Register, both quotient and mod results
8898 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8899 rFlagsReg cr)
8900 %{
8901 match(DivModI rax div);
8902 effect(KILL cr);
8904 ins_cost(30*100+10*100); // XXX
8905 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8906 "jne,s normal\n\t"
8907 "xorl rdx, rdx\n\t"
8908 "cmpl $div, -1\n\t"
8909 "je,s done\n"
8910 "normal: cdql\n\t"
8911 "idivl $div\n"
8912 "done:" %}
8913 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8914 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8915 ins_pipe(pipe_slow);
8916 %}
8918 // Long DIVMOD with Register, both quotient and mod results
8919 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8920 rFlagsReg cr)
8921 %{
8922 match(DivModL rax div);
8923 effect(KILL cr);
8925 ins_cost(30*100+10*100); // XXX
8926 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8927 "cmpq rax, rdx\n\t"
8928 "jne,s normal\n\t"
8929 "xorl rdx, rdx\n\t"
8930 "cmpq $div, -1\n\t"
8931 "je,s done\n"
8932 "normal: cdqq\n\t"
8933 "idivq $div\n"
8934 "done:" %}
8935 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8936 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8937 ins_pipe(pipe_slow);
8938 %}
8940 //----------- DivL-By-Constant-Expansions--------------------------------------
8941 // DivI cases are handled by the compiler
8943 // Magic constant, reciprocal of 10
8944 instruct loadConL_0x6666666666666667(rRegL dst)
8945 %{
8946 effect(DEF dst);
8948 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8949 ins_encode(load_immL(dst, 0x6666666666666667));
8950 ins_pipe(ialu_reg);
8951 %}
8953 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8954 %{
8955 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8957 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8958 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8959 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8960 ins_pipe(ialu_reg_reg_alu0);
8961 %}
8963 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8964 %{
8965 effect(USE_DEF dst, KILL cr);
8967 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8968 opcode(0xC1, 0x7); /* C1 /7 ib */
8969 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8970 ins_pipe(ialu_reg);
8971 %}
8973 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8974 %{
8975 effect(USE_DEF dst, KILL cr);
8977 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8978 opcode(0xC1, 0x7); /* C1 /7 ib */
8979 ins_encode(reg_opc_imm_wide(dst, 0x2));
8980 ins_pipe(ialu_reg);
8981 %}
8983 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8984 %{
8985 match(Set dst (DivL src div));
8987 ins_cost((5+8)*100);
8988 expand %{
8989 rax_RegL rax; // Killed temp
8990 rFlagsReg cr; // Killed
8991 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8992 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8993 sarL_rReg_63(src, cr); // sarq src, 63
8994 sarL_rReg_2(dst, cr); // sarq rdx, 2
8995 subL_rReg(dst, src, cr); // subl rdx, src
8996 %}
8997 %}
8999 //-----------------------------------------------------------------------------
9001 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
9002 rFlagsReg cr)
9003 %{
9004 match(Set rdx (ModI rax div));
9005 effect(KILL rax, KILL cr);
9007 ins_cost(300); // XXX
9008 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
9009 "jne,s normal\n\t"
9010 "xorl rdx, rdx\n\t"
9011 "cmpl $div, -1\n\t"
9012 "je,s done\n"
9013 "normal: cdql\n\t"
9014 "idivl $div\n"
9015 "done:" %}
9016 opcode(0xF7, 0x7); /* Opcode F7 /7 */
9017 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
9018 ins_pipe(ialu_reg_reg_alu0);
9019 %}
9021 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
9022 rFlagsReg cr)
9023 %{
9024 match(Set rdx (ModL rax div));
9025 effect(KILL rax, KILL cr);
9027 ins_cost(300); // XXX
9028 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
9029 "cmpq rax, rdx\n\t"
9030 "jne,s normal\n\t"
9031 "xorl rdx, rdx\n\t"
9032 "cmpq $div, -1\n\t"
9033 "je,s done\n"
9034 "normal: cdqq\n\t"
9035 "idivq $div\n"
9036 "done:" %}
9037 opcode(0xF7, 0x7); /* Opcode F7 /7 */
9038 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
9039 ins_pipe(ialu_reg_reg_alu0);
9040 %}
9042 // Integer Shift Instructions
9043 // Shift Left by one
9044 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
9045 %{
9046 match(Set dst (LShiftI dst shift));
9047 effect(KILL cr);
9049 format %{ "sall $dst, $shift" %}
9050 opcode(0xD1, 0x4); /* D1 /4 */
9051 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9052 ins_pipe(ialu_reg);
9053 %}
9055 // Shift Left by one
9056 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9057 %{
9058 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9059 effect(KILL cr);
9061 format %{ "sall $dst, $shift\t" %}
9062 opcode(0xD1, 0x4); /* D1 /4 */
9063 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9064 ins_pipe(ialu_mem_imm);
9065 %}
9067 // Shift Left by 8-bit immediate
9068 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9069 %{
9070 match(Set dst (LShiftI dst shift));
9071 effect(KILL cr);
9073 format %{ "sall $dst, $shift" %}
9074 opcode(0xC1, 0x4); /* C1 /4 ib */
9075 ins_encode(reg_opc_imm(dst, shift));
9076 ins_pipe(ialu_reg);
9077 %}
9079 // Shift Left by 8-bit immediate
9080 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9081 %{
9082 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9083 effect(KILL cr);
9085 format %{ "sall $dst, $shift" %}
9086 opcode(0xC1, 0x4); /* C1 /4 ib */
9087 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
9088 ins_pipe(ialu_mem_imm);
9089 %}
9091 // Shift Left by variable
9092 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9093 %{
9094 match(Set dst (LShiftI dst shift));
9095 effect(KILL cr);
9097 format %{ "sall $dst, $shift" %}
9098 opcode(0xD3, 0x4); /* D3 /4 */
9099 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9100 ins_pipe(ialu_reg_reg);
9101 %}
9103 // Shift Left by variable
9104 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9105 %{
9106 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9107 effect(KILL cr);
9109 format %{ "sall $dst, $shift" %}
9110 opcode(0xD3, 0x4); /* D3 /4 */
9111 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9112 ins_pipe(ialu_mem_reg);
9113 %}
9115 // Arithmetic shift right by one
9116 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
9117 %{
9118 match(Set dst (RShiftI dst shift));
9119 effect(KILL cr);
9121 format %{ "sarl $dst, $shift" %}
9122 opcode(0xD1, 0x7); /* D1 /7 */
9123 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9124 ins_pipe(ialu_reg);
9125 %}
9127 // Arithmetic shift right by one
9128 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9129 %{
9130 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9131 effect(KILL cr);
9133 format %{ "sarl $dst, $shift" %}
9134 opcode(0xD1, 0x7); /* D1 /7 */
9135 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9136 ins_pipe(ialu_mem_imm);
9137 %}
9139 // Arithmetic Shift Right by 8-bit immediate
9140 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9141 %{
9142 match(Set dst (RShiftI dst shift));
9143 effect(KILL cr);
9145 format %{ "sarl $dst, $shift" %}
9146 opcode(0xC1, 0x7); /* C1 /7 ib */
9147 ins_encode(reg_opc_imm(dst, shift));
9148 ins_pipe(ialu_mem_imm);
9149 %}
9151 // Arithmetic Shift Right by 8-bit immediate
9152 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9153 %{
9154 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9155 effect(KILL cr);
9157 format %{ "sarl $dst, $shift" %}
9158 opcode(0xC1, 0x7); /* C1 /7 ib */
9159 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
9160 ins_pipe(ialu_mem_imm);
9161 %}
9163 // Arithmetic Shift Right by variable
9164 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9165 %{
9166 match(Set dst (RShiftI dst shift));
9167 effect(KILL cr);
9169 format %{ "sarl $dst, $shift" %}
9170 opcode(0xD3, 0x7); /* D3 /7 */
9171 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9172 ins_pipe(ialu_reg_reg);
9173 %}
9175 // Arithmetic Shift Right by variable
9176 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9177 %{
9178 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9179 effect(KILL cr);
9181 format %{ "sarl $dst, $shift" %}
9182 opcode(0xD3, 0x7); /* D3 /7 */
9183 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9184 ins_pipe(ialu_mem_reg);
9185 %}
9187 // Logical shift right by one
9188 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
9189 %{
9190 match(Set dst (URShiftI dst shift));
9191 effect(KILL cr);
9193 format %{ "shrl $dst, $shift" %}
9194 opcode(0xD1, 0x5); /* D1 /5 */
9195 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9196 ins_pipe(ialu_reg);
9197 %}
9199 // Logical shift right by one
9200 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9201 %{
9202 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9203 effect(KILL cr);
9205 format %{ "shrl $dst, $shift" %}
9206 opcode(0xD1, 0x5); /* D1 /5 */
9207 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9208 ins_pipe(ialu_mem_imm);
9209 %}
9211 // Logical Shift Right by 8-bit immediate
9212 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9213 %{
9214 match(Set dst (URShiftI dst shift));
9215 effect(KILL cr);
9217 format %{ "shrl $dst, $shift" %}
9218 opcode(0xC1, 0x5); /* C1 /5 ib */
9219 ins_encode(reg_opc_imm(dst, shift));
9220 ins_pipe(ialu_reg);
9221 %}
9223 // Logical Shift Right by 8-bit immediate
9224 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9225 %{
9226 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9227 effect(KILL cr);
9229 format %{ "shrl $dst, $shift" %}
9230 opcode(0xC1, 0x5); /* C1 /5 ib */
9231 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
9232 ins_pipe(ialu_mem_imm);
9233 %}
9235 // Logical Shift Right by variable
9236 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9237 %{
9238 match(Set dst (URShiftI dst shift));
9239 effect(KILL cr);
9241 format %{ "shrl $dst, $shift" %}
9242 opcode(0xD3, 0x5); /* D3 /5 */
9243 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9244 ins_pipe(ialu_reg_reg);
9245 %}
9247 // Logical Shift Right by variable
9248 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9249 %{
9250 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9251 effect(KILL cr);
9253 format %{ "shrl $dst, $shift" %}
9254 opcode(0xD3, 0x5); /* D3 /5 */
9255 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
9256 ins_pipe(ialu_mem_reg);
9257 %}
9259 // Long Shift Instructions
9260 // Shift Left by one
9261 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9262 %{
9263 match(Set dst (LShiftL dst shift));
9264 effect(KILL cr);
9266 format %{ "salq $dst, $shift" %}
9267 opcode(0xD1, 0x4); /* D1 /4 */
9268 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9269 ins_pipe(ialu_reg);
9270 %}
9272 // Shift Left by one
9273 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9274 %{
9275 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9276 effect(KILL cr);
9278 format %{ "salq $dst, $shift" %}
9279 opcode(0xD1, 0x4); /* D1 /4 */
9280 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9281 ins_pipe(ialu_mem_imm);
9282 %}
9284 // Shift Left by 8-bit immediate
9285 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9286 %{
9287 match(Set dst (LShiftL dst shift));
9288 effect(KILL cr);
9290 format %{ "salq $dst, $shift" %}
9291 opcode(0xC1, 0x4); /* C1 /4 ib */
9292 ins_encode(reg_opc_imm_wide(dst, shift));
9293 ins_pipe(ialu_reg);
9294 %}
9296 // Shift Left by 8-bit immediate
9297 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9298 %{
9299 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9300 effect(KILL cr);
9302 format %{ "salq $dst, $shift" %}
9303 opcode(0xC1, 0x4); /* C1 /4 ib */
9304 ins_encode(REX_mem_wide(dst), OpcP,
9305 RM_opc_mem(secondary, dst), Con8or32(shift));
9306 ins_pipe(ialu_mem_imm);
9307 %}
9309 // Shift Left by variable
9310 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9311 %{
9312 match(Set dst (LShiftL dst shift));
9313 effect(KILL cr);
9315 format %{ "salq $dst, $shift" %}
9316 opcode(0xD3, 0x4); /* D3 /4 */
9317 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9318 ins_pipe(ialu_reg_reg);
9319 %}
9321 // Shift Left by variable
9322 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9323 %{
9324 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9325 effect(KILL cr);
9327 format %{ "salq $dst, $shift" %}
9328 opcode(0xD3, 0x4); /* D3 /4 */
9329 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9330 ins_pipe(ialu_mem_reg);
9331 %}
9333 // Arithmetic shift right by one
9334 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9335 %{
9336 match(Set dst (RShiftL dst shift));
9337 effect(KILL cr);
9339 format %{ "sarq $dst, $shift" %}
9340 opcode(0xD1, 0x7); /* D1 /7 */
9341 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9342 ins_pipe(ialu_reg);
9343 %}
9345 // Arithmetic shift right by one
9346 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9347 %{
9348 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9349 effect(KILL cr);
9351 format %{ "sarq $dst, $shift" %}
9352 opcode(0xD1, 0x7); /* D1 /7 */
9353 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9354 ins_pipe(ialu_mem_imm);
9355 %}
9357 // Arithmetic Shift Right by 8-bit immediate
9358 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9359 %{
9360 match(Set dst (RShiftL dst shift));
9361 effect(KILL cr);
9363 format %{ "sarq $dst, $shift" %}
9364 opcode(0xC1, 0x7); /* C1 /7 ib */
9365 ins_encode(reg_opc_imm_wide(dst, shift));
9366 ins_pipe(ialu_mem_imm);
9367 %}
9369 // Arithmetic Shift Right by 8-bit immediate
9370 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9371 %{
9372 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9373 effect(KILL cr);
9375 format %{ "sarq $dst, $shift" %}
9376 opcode(0xC1, 0x7); /* C1 /7 ib */
9377 ins_encode(REX_mem_wide(dst), OpcP,
9378 RM_opc_mem(secondary, dst), Con8or32(shift));
9379 ins_pipe(ialu_mem_imm);
9380 %}
9382 // Arithmetic Shift Right by variable
9383 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9384 %{
9385 match(Set dst (RShiftL dst shift));
9386 effect(KILL cr);
9388 format %{ "sarq $dst, $shift" %}
9389 opcode(0xD3, 0x7); /* D3 /7 */
9390 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9391 ins_pipe(ialu_reg_reg);
9392 %}
9394 // Arithmetic Shift Right by variable
9395 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9396 %{
9397 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9398 effect(KILL cr);
9400 format %{ "sarq $dst, $shift" %}
9401 opcode(0xD3, 0x7); /* D3 /7 */
9402 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9403 ins_pipe(ialu_mem_reg);
9404 %}
9406 // Logical shift right by one
9407 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9408 %{
9409 match(Set dst (URShiftL dst shift));
9410 effect(KILL cr);
9412 format %{ "shrq $dst, $shift" %}
9413 opcode(0xD1, 0x5); /* D1 /5 */
9414 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
9415 ins_pipe(ialu_reg);
9416 %}
9418 // Logical shift right by one
9419 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9420 %{
9421 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9422 effect(KILL cr);
9424 format %{ "shrq $dst, $shift" %}
9425 opcode(0xD1, 0x5); /* D1 /5 */
9426 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9427 ins_pipe(ialu_mem_imm);
9428 %}
9430 // Logical Shift Right by 8-bit immediate
9431 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9432 %{
9433 match(Set dst (URShiftL dst shift));
9434 effect(KILL cr);
9436 format %{ "shrq $dst, $shift" %}
9437 opcode(0xC1, 0x5); /* C1 /5 ib */
9438 ins_encode(reg_opc_imm_wide(dst, shift));
9439 ins_pipe(ialu_reg);
9440 %}
9443 // Logical Shift Right by 8-bit immediate
9444 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9445 %{
9446 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9447 effect(KILL cr);
9449 format %{ "shrq $dst, $shift" %}
9450 opcode(0xC1, 0x5); /* C1 /5 ib */
9451 ins_encode(REX_mem_wide(dst), OpcP,
9452 RM_opc_mem(secondary, dst), Con8or32(shift));
9453 ins_pipe(ialu_mem_imm);
9454 %}
9456 // Logical Shift Right by variable
9457 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9458 %{
9459 match(Set dst (URShiftL dst shift));
9460 effect(KILL cr);
9462 format %{ "shrq $dst, $shift" %}
9463 opcode(0xD3, 0x5); /* D3 /5 */
9464 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9465 ins_pipe(ialu_reg_reg);
9466 %}
9468 // Logical Shift Right by variable
9469 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9470 %{
9471 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9472 effect(KILL cr);
9474 format %{ "shrq $dst, $shift" %}
9475 opcode(0xD3, 0x5); /* D3 /5 */
9476 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9477 ins_pipe(ialu_mem_reg);
9478 %}
9480 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9481 // This idiom is used by the compiler for the i2b bytecode.
9482 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9483 %{
9484 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9486 format %{ "movsbl $dst, $src\t# i2b" %}
9487 opcode(0x0F, 0xBE);
9488 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9489 ins_pipe(ialu_reg_reg);
9490 %}
9492 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9493 // This idiom is used by the compiler the i2s bytecode.
9494 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9495 %{
9496 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9498 format %{ "movswl $dst, $src\t# i2s" %}
9499 opcode(0x0F, 0xBF);
9500 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9501 ins_pipe(ialu_reg_reg);
9502 %}
9504 // ROL/ROR instructions
9506 // ROL expand
9507 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9508 effect(KILL cr, USE_DEF dst);
9510 format %{ "roll $dst" %}
9511 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9512 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9513 ins_pipe(ialu_reg);
9514 %}
9516 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9517 effect(USE_DEF dst, USE shift, KILL cr);
9519 format %{ "roll $dst, $shift" %}
9520 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9521 ins_encode( reg_opc_imm(dst, shift) );
9522 ins_pipe(ialu_reg);
9523 %}
9525 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9526 %{
9527 effect(USE_DEF dst, USE shift, KILL cr);
9529 format %{ "roll $dst, $shift" %}
9530 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9531 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9532 ins_pipe(ialu_reg_reg);
9533 %}
9534 // end of ROL expand
9536 // Rotate Left by one
9537 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9538 %{
9539 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9541 expand %{
9542 rolI_rReg_imm1(dst, cr);
9543 %}
9544 %}
9546 // Rotate Left by 8-bit immediate
9547 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9548 %{
9549 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9550 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9552 expand %{
9553 rolI_rReg_imm8(dst, lshift, cr);
9554 %}
9555 %}
9557 // Rotate Left by variable
9558 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9559 %{
9560 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9562 expand %{
9563 rolI_rReg_CL(dst, shift, cr);
9564 %}
9565 %}
9567 // Rotate Left by variable
9568 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9569 %{
9570 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9572 expand %{
9573 rolI_rReg_CL(dst, shift, cr);
9574 %}
9575 %}
9577 // ROR expand
9578 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9579 %{
9580 effect(USE_DEF dst, KILL cr);
9582 format %{ "rorl $dst" %}
9583 opcode(0xD1, 0x1); /* D1 /1 */
9584 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9585 ins_pipe(ialu_reg);
9586 %}
9588 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9589 %{
9590 effect(USE_DEF dst, USE shift, KILL cr);
9592 format %{ "rorl $dst, $shift" %}
9593 opcode(0xC1, 0x1); /* C1 /1 ib */
9594 ins_encode(reg_opc_imm(dst, shift));
9595 ins_pipe(ialu_reg);
9596 %}
9598 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9599 %{
9600 effect(USE_DEF dst, USE shift, KILL cr);
9602 format %{ "rorl $dst, $shift" %}
9603 opcode(0xD3, 0x1); /* D3 /1 */
9604 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9605 ins_pipe(ialu_reg_reg);
9606 %}
9607 // end of ROR expand
9609 // Rotate Right by one
9610 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9611 %{
9612 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9614 expand %{
9615 rorI_rReg_imm1(dst, cr);
9616 %}
9617 %}
9619 // Rotate Right by 8-bit immediate
9620 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9621 %{
9622 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9623 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9625 expand %{
9626 rorI_rReg_imm8(dst, rshift, cr);
9627 %}
9628 %}
9630 // Rotate Right by variable
9631 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9632 %{
9633 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9635 expand %{
9636 rorI_rReg_CL(dst, shift, cr);
9637 %}
9638 %}
9640 // Rotate Right by variable
9641 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9642 %{
9643 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9645 expand %{
9646 rorI_rReg_CL(dst, shift, cr);
9647 %}
9648 %}
9650 // for long rotate
9651 // ROL expand
9652 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9653 effect(USE_DEF dst, KILL cr);
9655 format %{ "rolq $dst" %}
9656 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9657 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9658 ins_pipe(ialu_reg);
9659 %}
9661 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9662 effect(USE_DEF dst, USE shift, KILL cr);
9664 format %{ "rolq $dst, $shift" %}
9665 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9666 ins_encode( reg_opc_imm_wide(dst, shift) );
9667 ins_pipe(ialu_reg);
9668 %}
9670 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9671 %{
9672 effect(USE_DEF dst, USE shift, KILL cr);
9674 format %{ "rolq $dst, $shift" %}
9675 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9676 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9677 ins_pipe(ialu_reg_reg);
9678 %}
9679 // end of ROL expand
9681 // Rotate Left by one
9682 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9683 %{
9684 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9686 expand %{
9687 rolL_rReg_imm1(dst, cr);
9688 %}
9689 %}
9691 // Rotate Left by 8-bit immediate
9692 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9693 %{
9694 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9695 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9697 expand %{
9698 rolL_rReg_imm8(dst, lshift, cr);
9699 %}
9700 %}
9702 // Rotate Left by variable
9703 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9704 %{
9705 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9707 expand %{
9708 rolL_rReg_CL(dst, shift, cr);
9709 %}
9710 %}
9712 // Rotate Left by variable
9713 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9714 %{
9715 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9717 expand %{
9718 rolL_rReg_CL(dst, shift, cr);
9719 %}
9720 %}
9722 // ROR expand
9723 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9724 %{
9725 effect(USE_DEF dst, KILL cr);
9727 format %{ "rorq $dst" %}
9728 opcode(0xD1, 0x1); /* D1 /1 */
9729 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9730 ins_pipe(ialu_reg);
9731 %}
9733 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9734 %{
9735 effect(USE_DEF dst, USE shift, KILL cr);
9737 format %{ "rorq $dst, $shift" %}
9738 opcode(0xC1, 0x1); /* C1 /1 ib */
9739 ins_encode(reg_opc_imm_wide(dst, shift));
9740 ins_pipe(ialu_reg);
9741 %}
9743 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9744 %{
9745 effect(USE_DEF dst, USE shift, KILL cr);
9747 format %{ "rorq $dst, $shift" %}
9748 opcode(0xD3, 0x1); /* D3 /1 */
9749 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9750 ins_pipe(ialu_reg_reg);
9751 %}
9752 // end of ROR expand
9754 // Rotate Right by one
9755 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9756 %{
9757 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9759 expand %{
9760 rorL_rReg_imm1(dst, cr);
9761 %}
9762 %}
9764 // Rotate Right by 8-bit immediate
9765 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9766 %{
9767 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9768 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9770 expand %{
9771 rorL_rReg_imm8(dst, rshift, cr);
9772 %}
9773 %}
9775 // Rotate Right by variable
9776 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9777 %{
9778 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9780 expand %{
9781 rorL_rReg_CL(dst, shift, cr);
9782 %}
9783 %}
9785 // Rotate Right by variable
9786 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9787 %{
9788 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9790 expand %{
9791 rorL_rReg_CL(dst, shift, cr);
9792 %}
9793 %}
9795 // Logical Instructions
9797 // Integer Logical Instructions
9799 // And Instructions
9800 // And Register with Register
9801 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9802 %{
9803 match(Set dst (AndI dst src));
9804 effect(KILL cr);
9806 format %{ "andl $dst, $src\t# int" %}
9807 opcode(0x23);
9808 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9809 ins_pipe(ialu_reg_reg);
9810 %}
9812 // And Register with Immediate 255
9813 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9814 %{
9815 match(Set dst (AndI dst src));
9817 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9818 opcode(0x0F, 0xB6);
9819 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9820 ins_pipe(ialu_reg);
9821 %}
9823 // And Register with Immediate 255 and promote to long
9824 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9825 %{
9826 match(Set dst (ConvI2L (AndI src mask)));
9828 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9829 opcode(0x0F, 0xB6);
9830 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9831 ins_pipe(ialu_reg);
9832 %}
9834 // And Register with Immediate 65535
9835 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9836 %{
9837 match(Set dst (AndI dst src));
9839 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9840 opcode(0x0F, 0xB7);
9841 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9842 ins_pipe(ialu_reg);
9843 %}
9845 // And Register with Immediate 65535 and promote to long
9846 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9847 %{
9848 match(Set dst (ConvI2L (AndI src mask)));
9850 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9851 opcode(0x0F, 0xB7);
9852 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9853 ins_pipe(ialu_reg);
9854 %}
9856 // And Register with Immediate
9857 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9858 %{
9859 match(Set dst (AndI dst src));
9860 effect(KILL cr);
9862 format %{ "andl $dst, $src\t# int" %}
9863 opcode(0x81, 0x04); /* Opcode 81 /4 */
9864 ins_encode(OpcSErm(dst, src), Con8or32(src));
9865 ins_pipe(ialu_reg);
9866 %}
9868 // And Register with Memory
9869 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9870 %{
9871 match(Set dst (AndI dst (LoadI src)));
9872 effect(KILL cr);
9874 ins_cost(125);
9875 format %{ "andl $dst, $src\t# int" %}
9876 opcode(0x23);
9877 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9878 ins_pipe(ialu_reg_mem);
9879 %}
9881 // And Memory with Register
9882 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9883 %{
9884 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9885 effect(KILL cr);
9887 ins_cost(150);
9888 format %{ "andl $dst, $src\t# int" %}
9889 opcode(0x21); /* Opcode 21 /r */
9890 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9891 ins_pipe(ialu_mem_reg);
9892 %}
9894 // And Memory with Immediate
9895 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9896 %{
9897 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9898 effect(KILL cr);
9900 ins_cost(125);
9901 format %{ "andl $dst, $src\t# int" %}
9902 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9903 ins_encode(REX_mem(dst), OpcSE(src),
9904 RM_opc_mem(secondary, dst), Con8or32(src));
9905 ins_pipe(ialu_mem_imm);
9906 %}
9908 // Or Instructions
9909 // Or Register with Register
9910 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9911 %{
9912 match(Set dst (OrI dst src));
9913 effect(KILL cr);
9915 format %{ "orl $dst, $src\t# int" %}
9916 opcode(0x0B);
9917 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9918 ins_pipe(ialu_reg_reg);
9919 %}
9921 // Or Register with Immediate
9922 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9923 %{
9924 match(Set dst (OrI dst src));
9925 effect(KILL cr);
9927 format %{ "orl $dst, $src\t# int" %}
9928 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9929 ins_encode(OpcSErm(dst, src), Con8or32(src));
9930 ins_pipe(ialu_reg);
9931 %}
9933 // Or Register with Memory
9934 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9935 %{
9936 match(Set dst (OrI dst (LoadI src)));
9937 effect(KILL cr);
9939 ins_cost(125);
9940 format %{ "orl $dst, $src\t# int" %}
9941 opcode(0x0B);
9942 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9943 ins_pipe(ialu_reg_mem);
9944 %}
9946 // Or Memory with Register
9947 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9948 %{
9949 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9950 effect(KILL cr);
9952 ins_cost(150);
9953 format %{ "orl $dst, $src\t# int" %}
9954 opcode(0x09); /* Opcode 09 /r */
9955 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9956 ins_pipe(ialu_mem_reg);
9957 %}
9959 // Or Memory with Immediate
9960 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9961 %{
9962 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9963 effect(KILL cr);
9965 ins_cost(125);
9966 format %{ "orl $dst, $src\t# int" %}
9967 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9968 ins_encode(REX_mem(dst), OpcSE(src),
9969 RM_opc_mem(secondary, dst), Con8or32(src));
9970 ins_pipe(ialu_mem_imm);
9971 %}
9973 // Xor Instructions
9974 // Xor Register with Register
9975 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9976 %{
9977 match(Set dst (XorI dst src));
9978 effect(KILL cr);
9980 format %{ "xorl $dst, $src\t# int" %}
9981 opcode(0x33);
9982 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9983 ins_pipe(ialu_reg_reg);
9984 %}
9986 // Xor Register with Immediate -1
9987 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9988 match(Set dst (XorI dst imm));
9990 format %{ "not $dst" %}
9991 ins_encode %{
9992 __ notl($dst$$Register);
9993 %}
9994 ins_pipe(ialu_reg);
9995 %}
9997 // Xor Register with Immediate
9998 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9999 %{
10000 match(Set dst (XorI dst src));
10001 effect(KILL cr);
10003 format %{ "xorl $dst, $src\t# int" %}
10004 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10005 ins_encode(OpcSErm(dst, src), Con8or32(src));
10006 ins_pipe(ialu_reg);
10007 %}
10009 // Xor Register with Memory
10010 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10011 %{
10012 match(Set dst (XorI dst (LoadI src)));
10013 effect(KILL cr);
10015 ins_cost(125);
10016 format %{ "xorl $dst, $src\t# int" %}
10017 opcode(0x33);
10018 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
10019 ins_pipe(ialu_reg_mem);
10020 %}
10022 // Xor Memory with Register
10023 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10024 %{
10025 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10026 effect(KILL cr);
10028 ins_cost(150);
10029 format %{ "xorl $dst, $src\t# int" %}
10030 opcode(0x31); /* Opcode 31 /r */
10031 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
10032 ins_pipe(ialu_mem_reg);
10033 %}
10035 // Xor Memory with Immediate
10036 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
10037 %{
10038 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10039 effect(KILL cr);
10041 ins_cost(125);
10042 format %{ "xorl $dst, $src\t# int" %}
10043 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10044 ins_encode(REX_mem(dst), OpcSE(src),
10045 RM_opc_mem(secondary, dst), Con8or32(src));
10046 ins_pipe(ialu_mem_imm);
10047 %}
10050 // Long Logical Instructions
10052 // And Instructions
10053 // And Register with Register
10054 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10055 %{
10056 match(Set dst (AndL dst src));
10057 effect(KILL cr);
10059 format %{ "andq $dst, $src\t# long" %}
10060 opcode(0x23);
10061 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10062 ins_pipe(ialu_reg_reg);
10063 %}
10065 // And Register with Immediate 255
10066 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
10067 %{
10068 match(Set dst (AndL dst src));
10070 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
10071 opcode(0x0F, 0xB6);
10072 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
10073 ins_pipe(ialu_reg);
10074 %}
10076 // And Register with Immediate 65535
10077 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
10078 %{
10079 match(Set dst (AndL dst src));
10081 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
10082 opcode(0x0F, 0xB7);
10083 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
10084 ins_pipe(ialu_reg);
10085 %}
10087 // And Register with Immediate
10088 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10089 %{
10090 match(Set dst (AndL dst src));
10091 effect(KILL cr);
10093 format %{ "andq $dst, $src\t# long" %}
10094 opcode(0x81, 0x04); /* Opcode 81 /4 */
10095 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10096 ins_pipe(ialu_reg);
10097 %}
10099 // And Register with Memory
10100 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10101 %{
10102 match(Set dst (AndL dst (LoadL src)));
10103 effect(KILL cr);
10105 ins_cost(125);
10106 format %{ "andq $dst, $src\t# long" %}
10107 opcode(0x23);
10108 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10109 ins_pipe(ialu_reg_mem);
10110 %}
10112 // And Memory with Register
10113 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10114 %{
10115 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10116 effect(KILL cr);
10118 ins_cost(150);
10119 format %{ "andq $dst, $src\t# long" %}
10120 opcode(0x21); /* Opcode 21 /r */
10121 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10122 ins_pipe(ialu_mem_reg);
10123 %}
10125 // And Memory with Immediate
10126 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10127 %{
10128 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10129 effect(KILL cr);
10131 ins_cost(125);
10132 format %{ "andq $dst, $src\t# long" %}
10133 opcode(0x81, 0x4); /* Opcode 81 /4 id */
10134 ins_encode(REX_mem_wide(dst), OpcSE(src),
10135 RM_opc_mem(secondary, dst), Con8or32(src));
10136 ins_pipe(ialu_mem_imm);
10137 %}
10139 // Or Instructions
10140 // Or Register with Register
10141 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10142 %{
10143 match(Set dst (OrL dst src));
10144 effect(KILL cr);
10146 format %{ "orq $dst, $src\t# long" %}
10147 opcode(0x0B);
10148 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10149 ins_pipe(ialu_reg_reg);
10150 %}
10152 // Use any_RegP to match R15 (TLS register) without spilling.
10153 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10154 match(Set dst (OrL dst (CastP2X src)));
10155 effect(KILL cr);
10157 format %{ "orq $dst, $src\t# long" %}
10158 opcode(0x0B);
10159 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10160 ins_pipe(ialu_reg_reg);
10161 %}
10164 // Or Register with Immediate
10165 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10166 %{
10167 match(Set dst (OrL dst src));
10168 effect(KILL cr);
10170 format %{ "orq $dst, $src\t# long" %}
10171 opcode(0x81, 0x01); /* Opcode 81 /1 id */
10172 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10173 ins_pipe(ialu_reg);
10174 %}
10176 // Or Register with Memory
10177 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10178 %{
10179 match(Set dst (OrL dst (LoadL src)));
10180 effect(KILL cr);
10182 ins_cost(125);
10183 format %{ "orq $dst, $src\t# long" %}
10184 opcode(0x0B);
10185 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10186 ins_pipe(ialu_reg_mem);
10187 %}
10189 // Or Memory with Register
10190 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10191 %{
10192 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10193 effect(KILL cr);
10195 ins_cost(150);
10196 format %{ "orq $dst, $src\t# long" %}
10197 opcode(0x09); /* Opcode 09 /r */
10198 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10199 ins_pipe(ialu_mem_reg);
10200 %}
10202 // Or Memory with Immediate
10203 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10204 %{
10205 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10206 effect(KILL cr);
10208 ins_cost(125);
10209 format %{ "orq $dst, $src\t# long" %}
10210 opcode(0x81, 0x1); /* Opcode 81 /1 id */
10211 ins_encode(REX_mem_wide(dst), OpcSE(src),
10212 RM_opc_mem(secondary, dst), Con8or32(src));
10213 ins_pipe(ialu_mem_imm);
10214 %}
10216 // Xor Instructions
10217 // Xor Register with Register
10218 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10219 %{
10220 match(Set dst (XorL dst src));
10221 effect(KILL cr);
10223 format %{ "xorq $dst, $src\t# long" %}
10224 opcode(0x33);
10225 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10226 ins_pipe(ialu_reg_reg);
10227 %}
10229 // Xor Register with Immediate -1
10230 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10231 match(Set dst (XorL dst imm));
10233 format %{ "notq $dst" %}
10234 ins_encode %{
10235 __ notq($dst$$Register);
10236 %}
10237 ins_pipe(ialu_reg);
10238 %}
10240 // Xor Register with Immediate
10241 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10242 %{
10243 match(Set dst (XorL dst src));
10244 effect(KILL cr);
10246 format %{ "xorq $dst, $src\t# long" %}
10247 opcode(0x81, 0x06); /* Opcode 81 /6 id */
10248 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10249 ins_pipe(ialu_reg);
10250 %}
10252 // Xor Register with Memory
10253 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10254 %{
10255 match(Set dst (XorL dst (LoadL src)));
10256 effect(KILL cr);
10258 ins_cost(125);
10259 format %{ "xorq $dst, $src\t# long" %}
10260 opcode(0x33);
10261 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10262 ins_pipe(ialu_reg_mem);
10263 %}
10265 // Xor Memory with Register
10266 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10267 %{
10268 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10269 effect(KILL cr);
10271 ins_cost(150);
10272 format %{ "xorq $dst, $src\t# long" %}
10273 opcode(0x31); /* Opcode 31 /r */
10274 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10275 ins_pipe(ialu_mem_reg);
10276 %}
10278 // Xor Memory with Immediate
10279 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10280 %{
10281 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10282 effect(KILL cr);
10284 ins_cost(125);
10285 format %{ "xorq $dst, $src\t# long" %}
10286 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10287 ins_encode(REX_mem_wide(dst), OpcSE(src),
10288 RM_opc_mem(secondary, dst), Con8or32(src));
10289 ins_pipe(ialu_mem_imm);
10290 %}
10292 // Convert Int to Boolean
10293 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10294 %{
10295 match(Set dst (Conv2B src));
10296 effect(KILL cr);
10298 format %{ "testl $src, $src\t# ci2b\n\t"
10299 "setnz $dst\n\t"
10300 "movzbl $dst, $dst" %}
10301 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10302 setNZ_reg(dst),
10303 REX_reg_breg(dst, dst), // movzbl
10304 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10305 ins_pipe(pipe_slow); // XXX
10306 %}
10308 // Convert Pointer to Boolean
10309 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10310 %{
10311 match(Set dst (Conv2B src));
10312 effect(KILL cr);
10314 format %{ "testq $src, $src\t# cp2b\n\t"
10315 "setnz $dst\n\t"
10316 "movzbl $dst, $dst" %}
10317 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10318 setNZ_reg(dst),
10319 REX_reg_breg(dst, dst), // movzbl
10320 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10321 ins_pipe(pipe_slow); // XXX
10322 %}
10324 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10325 %{
10326 match(Set dst (CmpLTMask p q));
10327 effect(KILL cr);
10329 ins_cost(400); // XXX
10330 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10331 "setlt $dst\n\t"
10332 "movzbl $dst, $dst\n\t"
10333 "negl $dst" %}
10334 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10335 setLT_reg(dst),
10336 REX_reg_breg(dst, dst), // movzbl
10337 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10338 neg_reg(dst));
10339 ins_pipe(pipe_slow);
10340 %}
10342 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10343 %{
10344 match(Set dst (CmpLTMask dst zero));
10345 effect(KILL cr);
10347 ins_cost(100); // XXX
10348 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10349 opcode(0xC1, 0x7); /* C1 /7 ib */
10350 ins_encode(reg_opc_imm(dst, 0x1F));
10351 ins_pipe(ialu_reg);
10352 %}
10355 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y,
10356 rRegI tmp,
10357 rFlagsReg cr)
10358 %{
10359 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10360 effect(TEMP tmp, KILL cr);
10362 ins_cost(400); // XXX
10363 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
10364 "sbbl $tmp, $tmp\n\t"
10365 "andl $tmp, $y\n\t"
10366 "addl $p, $tmp" %}
10367 ins_encode(enc_cmpLTP(p, q, y, tmp));
10368 ins_pipe(pipe_cmplt);
10369 %}
10371 /* If I enable this, I encourage spilling in the inner loop of compress.
10372 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr )
10373 %{
10374 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
10375 effect( TEMP tmp, KILL cr );
10376 ins_cost(400);
10378 format %{ "SUB $p,$q\n\t"
10379 "SBB RCX,RCX\n\t"
10380 "AND RCX,$y\n\t"
10381 "ADD $p,RCX" %}
10382 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
10383 %}
10384 */
10386 //---------- FP Instructions------------------------------------------------
10388 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10389 %{
10390 match(Set cr (CmpF src1 src2));
10392 ins_cost(145);
10393 format %{ "ucomiss $src1, $src2\n\t"
10394 "jnp,s exit\n\t"
10395 "pushfq\t# saw NaN, set CF\n\t"
10396 "andq [rsp], #0xffffff2b\n\t"
10397 "popfq\n"
10398 "exit: nop\t# avoid branch to branch" %}
10399 opcode(0x0F, 0x2E);
10400 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
10401 cmpfp_fixup);
10402 ins_pipe(pipe_slow);
10403 %}
10405 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10406 match(Set cr (CmpF src1 src2));
10408 ins_cost(145);
10409 format %{ "ucomiss $src1, $src2" %}
10410 ins_encode %{
10411 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10412 %}
10413 ins_pipe(pipe_slow);
10414 %}
10416 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10417 %{
10418 match(Set cr (CmpF src1 (LoadF src2)));
10420 ins_cost(145);
10421 format %{ "ucomiss $src1, $src2\n\t"
10422 "jnp,s exit\n\t"
10423 "pushfq\t# saw NaN, set CF\n\t"
10424 "andq [rsp], #0xffffff2b\n\t"
10425 "popfq\n"
10426 "exit: nop\t# avoid branch to branch" %}
10427 opcode(0x0F, 0x2E);
10428 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
10429 cmpfp_fixup);
10430 ins_pipe(pipe_slow);
10431 %}
10433 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10434 match(Set cr (CmpF src1 (LoadF src2)));
10436 ins_cost(100);
10437 format %{ "ucomiss $src1, $src2" %}
10438 opcode(0x0F, 0x2E);
10439 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2));
10440 ins_pipe(pipe_slow);
10441 %}
10443 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2)
10444 %{
10445 match(Set cr (CmpF src1 src2));
10447 ins_cost(145);
10448 format %{ "ucomiss $src1, $src2\n\t"
10449 "jnp,s exit\n\t"
10450 "pushfq\t# saw NaN, set CF\n\t"
10451 "andq [rsp], #0xffffff2b\n\t"
10452 "popfq\n"
10453 "exit: nop\t# avoid branch to branch" %}
10454 opcode(0x0F, 0x2E);
10455 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
10456 cmpfp_fixup);
10457 ins_pipe(pipe_slow);
10458 %}
10460 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src1, immF src2) %{
10461 match(Set cr (CmpF src1 src2));
10463 ins_cost(100);
10464 format %{ "ucomiss $src1, $src2" %}
10465 opcode(0x0F, 0x2E);
10466 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2));
10467 ins_pipe(pipe_slow);
10468 %}
10470 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10471 %{
10472 match(Set cr (CmpD src1 src2));
10474 ins_cost(145);
10475 format %{ "ucomisd $src1, $src2\n\t"
10476 "jnp,s exit\n\t"
10477 "pushfq\t# saw NaN, set CF\n\t"
10478 "andq [rsp], #0xffffff2b\n\t"
10479 "popfq\n"
10480 "exit: nop\t# avoid branch to branch" %}
10481 opcode(0x66, 0x0F, 0x2E);
10482 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
10483 cmpfp_fixup);
10484 ins_pipe(pipe_slow);
10485 %}
10487 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10488 match(Set cr (CmpD src1 src2));
10490 ins_cost(100);
10491 format %{ "ucomisd $src1, $src2 test" %}
10492 ins_encode %{
10493 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10494 %}
10495 ins_pipe(pipe_slow);
10496 %}
10498 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10499 %{
10500 match(Set cr (CmpD src1 (LoadD src2)));
10502 ins_cost(145);
10503 format %{ "ucomisd $src1, $src2\n\t"
10504 "jnp,s exit\n\t"
10505 "pushfq\t# saw NaN, set CF\n\t"
10506 "andq [rsp], #0xffffff2b\n\t"
10507 "popfq\n"
10508 "exit: nop\t# avoid branch to branch" %}
10509 opcode(0x66, 0x0F, 0x2E);
10510 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
10511 cmpfp_fixup);
10512 ins_pipe(pipe_slow);
10513 %}
10515 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10516 match(Set cr (CmpD src1 (LoadD src2)));
10518 ins_cost(100);
10519 format %{ "ucomisd $src1, $src2" %}
10520 opcode(0x66, 0x0F, 0x2E);
10521 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2));
10522 ins_pipe(pipe_slow);
10523 %}
10525 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2)
10526 %{
10527 match(Set cr (CmpD src1 src2));
10529 ins_cost(145);
10530 format %{ "ucomisd $src1, [$src2]\n\t"
10531 "jnp,s exit\n\t"
10532 "pushfq\t# saw NaN, set CF\n\t"
10533 "andq [rsp], #0xffffff2b\n\t"
10534 "popfq\n"
10535 "exit: nop\t# avoid branch to branch" %}
10536 opcode(0x66, 0x0F, 0x2E);
10537 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
10538 cmpfp_fixup);
10539 ins_pipe(pipe_slow);
10540 %}
10542 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src1, immD src2) %{
10543 match(Set cr (CmpD src1 src2));
10545 ins_cost(100);
10546 format %{ "ucomisd $src1, [$src2]" %}
10547 opcode(0x66, 0x0F, 0x2E);
10548 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2));
10549 ins_pipe(pipe_slow);
10550 %}
10552 // Compare into -1,0,1
10553 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10554 %{
10555 match(Set dst (CmpF3 src1 src2));
10556 effect(KILL cr);
10558 ins_cost(275);
10559 format %{ "ucomiss $src1, $src2\n\t"
10560 "movl $dst, #-1\n\t"
10561 "jp,s done\n\t"
10562 "jb,s done\n\t"
10563 "setne $dst\n\t"
10564 "movzbl $dst, $dst\n"
10565 "done:" %}
10567 opcode(0x0F, 0x2E);
10568 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
10569 cmpfp3(dst));
10570 ins_pipe(pipe_slow);
10571 %}
10573 // Compare into -1,0,1
10574 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10575 %{
10576 match(Set dst (CmpF3 src1 (LoadF src2)));
10577 effect(KILL cr);
10579 ins_cost(275);
10580 format %{ "ucomiss $src1, $src2\n\t"
10581 "movl $dst, #-1\n\t"
10582 "jp,s done\n\t"
10583 "jb,s done\n\t"
10584 "setne $dst\n\t"
10585 "movzbl $dst, $dst\n"
10586 "done:" %}
10588 opcode(0x0F, 0x2E);
10589 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
10590 cmpfp3(dst));
10591 ins_pipe(pipe_slow);
10592 %}
10594 // Compare into -1,0,1
10595 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr)
10596 %{
10597 match(Set dst (CmpF3 src1 src2));
10598 effect(KILL cr);
10600 ins_cost(275);
10601 format %{ "ucomiss $src1, [$src2]\n\t"
10602 "movl $dst, #-1\n\t"
10603 "jp,s done\n\t"
10604 "jb,s done\n\t"
10605 "setne $dst\n\t"
10606 "movzbl $dst, $dst\n"
10607 "done:" %}
10609 opcode(0x0F, 0x2E);
10610 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
10611 cmpfp3(dst));
10612 ins_pipe(pipe_slow);
10613 %}
10615 // Compare into -1,0,1
10616 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10617 %{
10618 match(Set dst (CmpD3 src1 src2));
10619 effect(KILL cr);
10621 ins_cost(275);
10622 format %{ "ucomisd $src1, $src2\n\t"
10623 "movl $dst, #-1\n\t"
10624 "jp,s done\n\t"
10625 "jb,s done\n\t"
10626 "setne $dst\n\t"
10627 "movzbl $dst, $dst\n"
10628 "done:" %}
10630 opcode(0x66, 0x0F, 0x2E);
10631 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
10632 cmpfp3(dst));
10633 ins_pipe(pipe_slow);
10634 %}
10636 // Compare into -1,0,1
10637 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10638 %{
10639 match(Set dst (CmpD3 src1 (LoadD src2)));
10640 effect(KILL cr);
10642 ins_cost(275);
10643 format %{ "ucomisd $src1, $src2\n\t"
10644 "movl $dst, #-1\n\t"
10645 "jp,s done\n\t"
10646 "jb,s done\n\t"
10647 "setne $dst\n\t"
10648 "movzbl $dst, $dst\n"
10649 "done:" %}
10651 opcode(0x66, 0x0F, 0x2E);
10652 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
10653 cmpfp3(dst));
10654 ins_pipe(pipe_slow);
10655 %}
10657 // Compare into -1,0,1
10658 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr)
10659 %{
10660 match(Set dst (CmpD3 src1 src2));
10661 effect(KILL cr);
10663 ins_cost(275);
10664 format %{ "ucomisd $src1, [$src2]\n\t"
10665 "movl $dst, #-1\n\t"
10666 "jp,s done\n\t"
10667 "jb,s done\n\t"
10668 "setne $dst\n\t"
10669 "movzbl $dst, $dst\n"
10670 "done:" %}
10672 opcode(0x66, 0x0F, 0x2E);
10673 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
10674 cmpfp3(dst));
10675 ins_pipe(pipe_slow);
10676 %}
10678 instruct addF_reg(regF dst, regF src)
10679 %{
10680 match(Set dst (AddF dst src));
10682 format %{ "addss $dst, $src" %}
10683 ins_cost(150); // XXX
10684 opcode(0xF3, 0x0F, 0x58);
10685 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10686 ins_pipe(pipe_slow);
10687 %}
10689 instruct addF_mem(regF dst, memory src)
10690 %{
10691 match(Set dst (AddF dst (LoadF src)));
10693 format %{ "addss $dst, $src" %}
10694 ins_cost(150); // XXX
10695 opcode(0xF3, 0x0F, 0x58);
10696 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10697 ins_pipe(pipe_slow);
10698 %}
10700 instruct addF_imm(regF dst, immF src)
10701 %{
10702 match(Set dst (AddF dst src));
10704 format %{ "addss $dst, [$src]" %}
10705 ins_cost(150); // XXX
10706 opcode(0xF3, 0x0F, 0x58);
10707 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10708 ins_pipe(pipe_slow);
10709 %}
10711 instruct addD_reg(regD dst, regD src)
10712 %{
10713 match(Set dst (AddD dst src));
10715 format %{ "addsd $dst, $src" %}
10716 ins_cost(150); // XXX
10717 opcode(0xF2, 0x0F, 0x58);
10718 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10719 ins_pipe(pipe_slow);
10720 %}
10722 instruct addD_mem(regD dst, memory src)
10723 %{
10724 match(Set dst (AddD dst (LoadD src)));
10726 format %{ "addsd $dst, $src" %}
10727 ins_cost(150); // XXX
10728 opcode(0xF2, 0x0F, 0x58);
10729 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10730 ins_pipe(pipe_slow);
10731 %}
10733 instruct addD_imm(regD dst, immD src)
10734 %{
10735 match(Set dst (AddD dst src));
10737 format %{ "addsd $dst, [$src]" %}
10738 ins_cost(150); // XXX
10739 opcode(0xF2, 0x0F, 0x58);
10740 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10741 ins_pipe(pipe_slow);
10742 %}
10744 instruct subF_reg(regF dst, regF src)
10745 %{
10746 match(Set dst (SubF dst src));
10748 format %{ "subss $dst, $src" %}
10749 ins_cost(150); // XXX
10750 opcode(0xF3, 0x0F, 0x5C);
10751 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10752 ins_pipe(pipe_slow);
10753 %}
10755 instruct subF_mem(regF dst, memory src)
10756 %{
10757 match(Set dst (SubF dst (LoadF src)));
10759 format %{ "subss $dst, $src" %}
10760 ins_cost(150); // XXX
10761 opcode(0xF3, 0x0F, 0x5C);
10762 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10763 ins_pipe(pipe_slow);
10764 %}
10766 instruct subF_imm(regF dst, immF src)
10767 %{
10768 match(Set dst (SubF dst src));
10770 format %{ "subss $dst, [$src]" %}
10771 ins_cost(150); // XXX
10772 opcode(0xF3, 0x0F, 0x5C);
10773 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10774 ins_pipe(pipe_slow);
10775 %}
10777 instruct subD_reg(regD dst, regD src)
10778 %{
10779 match(Set dst (SubD dst src));
10781 format %{ "subsd $dst, $src" %}
10782 ins_cost(150); // XXX
10783 opcode(0xF2, 0x0F, 0x5C);
10784 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10785 ins_pipe(pipe_slow);
10786 %}
10788 instruct subD_mem(regD dst, memory src)
10789 %{
10790 match(Set dst (SubD dst (LoadD src)));
10792 format %{ "subsd $dst, $src" %}
10793 ins_cost(150); // XXX
10794 opcode(0xF2, 0x0F, 0x5C);
10795 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10796 ins_pipe(pipe_slow);
10797 %}
10799 instruct subD_imm(regD dst, immD src)
10800 %{
10801 match(Set dst (SubD dst src));
10803 format %{ "subsd $dst, [$src]" %}
10804 ins_cost(150); // XXX
10805 opcode(0xF2, 0x0F, 0x5C);
10806 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10807 ins_pipe(pipe_slow);
10808 %}
10810 instruct mulF_reg(regF dst, regF src)
10811 %{
10812 match(Set dst (MulF dst src));
10814 format %{ "mulss $dst, $src" %}
10815 ins_cost(150); // XXX
10816 opcode(0xF3, 0x0F, 0x59);
10817 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10818 ins_pipe(pipe_slow);
10819 %}
10821 instruct mulF_mem(regF dst, memory src)
10822 %{
10823 match(Set dst (MulF dst (LoadF src)));
10825 format %{ "mulss $dst, $src" %}
10826 ins_cost(150); // XXX
10827 opcode(0xF3, 0x0F, 0x59);
10828 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10829 ins_pipe(pipe_slow);
10830 %}
10832 instruct mulF_imm(regF dst, immF src)
10833 %{
10834 match(Set dst (MulF dst src));
10836 format %{ "mulss $dst, [$src]" %}
10837 ins_cost(150); // XXX
10838 opcode(0xF3, 0x0F, 0x59);
10839 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10840 ins_pipe(pipe_slow);
10841 %}
10843 instruct mulD_reg(regD dst, regD src)
10844 %{
10845 match(Set dst (MulD dst src));
10847 format %{ "mulsd $dst, $src" %}
10848 ins_cost(150); // XXX
10849 opcode(0xF2, 0x0F, 0x59);
10850 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10851 ins_pipe(pipe_slow);
10852 %}
10854 instruct mulD_mem(regD dst, memory src)
10855 %{
10856 match(Set dst (MulD dst (LoadD src)));
10858 format %{ "mulsd $dst, $src" %}
10859 ins_cost(150); // XXX
10860 opcode(0xF2, 0x0F, 0x59);
10861 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10862 ins_pipe(pipe_slow);
10863 %}
10865 instruct mulD_imm(regD dst, immD src)
10866 %{
10867 match(Set dst (MulD dst src));
10869 format %{ "mulsd $dst, [$src]" %}
10870 ins_cost(150); // XXX
10871 opcode(0xF2, 0x0F, 0x59);
10872 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10873 ins_pipe(pipe_slow);
10874 %}
10876 instruct divF_reg(regF dst, regF src)
10877 %{
10878 match(Set dst (DivF dst src));
10880 format %{ "divss $dst, $src" %}
10881 ins_cost(150); // XXX
10882 opcode(0xF3, 0x0F, 0x5E);
10883 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10884 ins_pipe(pipe_slow);
10885 %}
10887 instruct divF_mem(regF dst, memory src)
10888 %{
10889 match(Set dst (DivF dst (LoadF src)));
10891 format %{ "divss $dst, $src" %}
10892 ins_cost(150); // XXX
10893 opcode(0xF3, 0x0F, 0x5E);
10894 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10895 ins_pipe(pipe_slow);
10896 %}
10898 instruct divF_imm(regF dst, immF src)
10899 %{
10900 match(Set dst (DivF dst src));
10902 format %{ "divss $dst, [$src]" %}
10903 ins_cost(150); // XXX
10904 opcode(0xF3, 0x0F, 0x5E);
10905 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10906 ins_pipe(pipe_slow);
10907 %}
10909 instruct divD_reg(regD dst, regD src)
10910 %{
10911 match(Set dst (DivD dst src));
10913 format %{ "divsd $dst, $src" %}
10914 ins_cost(150); // XXX
10915 opcode(0xF2, 0x0F, 0x5E);
10916 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10917 ins_pipe(pipe_slow);
10918 %}
10920 instruct divD_mem(regD dst, memory src)
10921 %{
10922 match(Set dst (DivD dst (LoadD src)));
10924 format %{ "divsd $dst, $src" %}
10925 ins_cost(150); // XXX
10926 opcode(0xF2, 0x0F, 0x5E);
10927 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10928 ins_pipe(pipe_slow);
10929 %}
10931 instruct divD_imm(regD dst, immD src)
10932 %{
10933 match(Set dst (DivD dst src));
10935 format %{ "divsd $dst, [$src]" %}
10936 ins_cost(150); // XXX
10937 opcode(0xF2, 0x0F, 0x5E);
10938 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10939 ins_pipe(pipe_slow);
10940 %}
10942 instruct sqrtF_reg(regF dst, regF src)
10943 %{
10944 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10946 format %{ "sqrtss $dst, $src" %}
10947 ins_cost(150); // XXX
10948 opcode(0xF3, 0x0F, 0x51);
10949 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10950 ins_pipe(pipe_slow);
10951 %}
10953 instruct sqrtF_mem(regF dst, memory src)
10954 %{
10955 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
10957 format %{ "sqrtss $dst, $src" %}
10958 ins_cost(150); // XXX
10959 opcode(0xF3, 0x0F, 0x51);
10960 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10961 ins_pipe(pipe_slow);
10962 %}
10964 instruct sqrtF_imm(regF dst, immF src)
10965 %{
10966 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10968 format %{ "sqrtss $dst, [$src]" %}
10969 ins_cost(150); // XXX
10970 opcode(0xF3, 0x0F, 0x51);
10971 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10972 ins_pipe(pipe_slow);
10973 %}
10975 instruct sqrtD_reg(regD dst, regD src)
10976 %{
10977 match(Set dst (SqrtD src));
10979 format %{ "sqrtsd $dst, $src" %}
10980 ins_cost(150); // XXX
10981 opcode(0xF2, 0x0F, 0x51);
10982 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10983 ins_pipe(pipe_slow);
10984 %}
10986 instruct sqrtD_mem(regD dst, memory src)
10987 %{
10988 match(Set dst (SqrtD (LoadD src)));
10990 format %{ "sqrtsd $dst, $src" %}
10991 ins_cost(150); // XXX
10992 opcode(0xF2, 0x0F, 0x51);
10993 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10994 ins_pipe(pipe_slow);
10995 %}
10997 instruct sqrtD_imm(regD dst, immD src)
10998 %{
10999 match(Set dst (SqrtD src));
11001 format %{ "sqrtsd $dst, [$src]" %}
11002 ins_cost(150); // XXX
11003 opcode(0xF2, 0x0F, 0x51);
11004 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
11005 ins_pipe(pipe_slow);
11006 %}
11008 instruct absF_reg(regF dst)
11009 %{
11010 match(Set dst (AbsF dst));
11012 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
11013 ins_encode(absF_encoding(dst));
11014 ins_pipe(pipe_slow);
11015 %}
11017 instruct absD_reg(regD dst)
11018 %{
11019 match(Set dst (AbsD dst));
11021 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
11022 "# abs double by sign masking" %}
11023 ins_encode(absD_encoding(dst));
11024 ins_pipe(pipe_slow);
11025 %}
11027 instruct negF_reg(regF dst)
11028 %{
11029 match(Set dst (NegF dst));
11031 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
11032 ins_encode(negF_encoding(dst));
11033 ins_pipe(pipe_slow);
11034 %}
11036 instruct negD_reg(regD dst)
11037 %{
11038 match(Set dst (NegD dst));
11040 format %{ "xorpd $dst, [0x8000000000000000]\t"
11041 "# neg double by sign flipping" %}
11042 ins_encode(negD_encoding(dst));
11043 ins_pipe(pipe_slow);
11044 %}
11046 // -----------Trig and Trancendental Instructions------------------------------
11047 instruct cosD_reg(regD dst) %{
11048 match(Set dst (CosD dst));
11050 format %{ "dcos $dst\n\t" %}
11051 opcode(0xD9, 0xFF);
11052 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
11053 ins_pipe( pipe_slow );
11054 %}
11056 instruct sinD_reg(regD dst) %{
11057 match(Set dst (SinD dst));
11059 format %{ "dsin $dst\n\t" %}
11060 opcode(0xD9, 0xFE);
11061 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
11062 ins_pipe( pipe_slow );
11063 %}
11065 instruct tanD_reg(regD dst) %{
11066 match(Set dst (TanD dst));
11068 format %{ "dtan $dst\n\t" %}
11069 ins_encode( Push_SrcXD(dst),
11070 Opcode(0xD9), Opcode(0xF2), //fptan
11071 Opcode(0xDD), Opcode(0xD8), //fstp st
11072 Push_ResultXD(dst) );
11073 ins_pipe( pipe_slow );
11074 %}
11076 instruct log10D_reg(regD dst) %{
11077 // The source and result Double operands in XMM registers
11078 match(Set dst (Log10D dst));
11079 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
11080 // fyl2x ; compute log_10(2) * log_2(x)
11081 format %{ "fldlg2\t\t\t#Log10\n\t"
11082 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
11083 %}
11084 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
11085 Push_SrcXD(dst),
11086 Opcode(0xD9), Opcode(0xF1), // fyl2x
11087 Push_ResultXD(dst));
11089 ins_pipe( pipe_slow );
11090 %}
11092 instruct logD_reg(regD dst) %{
11093 // The source and result Double operands in XMM registers
11094 match(Set dst (LogD dst));
11095 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
11096 // fyl2x ; compute log_e(2) * log_2(x)
11097 format %{ "fldln2\t\t\t#Log_e\n\t"
11098 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
11099 %}
11100 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
11101 Push_SrcXD(dst),
11102 Opcode(0xD9), Opcode(0xF1), // fyl2x
11103 Push_ResultXD(dst));
11104 ins_pipe( pipe_slow );
11105 %}
11109 //----------Arithmetic Conversion Instructions---------------------------------
11111 instruct roundFloat_nop(regF dst)
11112 %{
11113 match(Set dst (RoundFloat dst));
11115 ins_cost(0);
11116 ins_encode();
11117 ins_pipe(empty);
11118 %}
11120 instruct roundDouble_nop(regD dst)
11121 %{
11122 match(Set dst (RoundDouble dst));
11124 ins_cost(0);
11125 ins_encode();
11126 ins_pipe(empty);
11127 %}
11129 instruct convF2D_reg_reg(regD dst, regF src)
11130 %{
11131 match(Set dst (ConvF2D src));
11133 format %{ "cvtss2sd $dst, $src" %}
11134 opcode(0xF3, 0x0F, 0x5A);
11135 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
11136 ins_pipe(pipe_slow); // XXX
11137 %}
11139 instruct convF2D_reg_mem(regD dst, memory src)
11140 %{
11141 match(Set dst (ConvF2D (LoadF src)));
11143 format %{ "cvtss2sd $dst, $src" %}
11144 opcode(0xF3, 0x0F, 0x5A);
11145 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11146 ins_pipe(pipe_slow); // XXX
11147 %}
11149 instruct convD2F_reg_reg(regF dst, regD src)
11150 %{
11151 match(Set dst (ConvD2F src));
11153 format %{ "cvtsd2ss $dst, $src" %}
11154 opcode(0xF2, 0x0F, 0x5A);
11155 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
11156 ins_pipe(pipe_slow); // XXX
11157 %}
11159 instruct convD2F_reg_mem(regF dst, memory src)
11160 %{
11161 match(Set dst (ConvD2F (LoadD src)));
11163 format %{ "cvtsd2ss $dst, $src" %}
11164 opcode(0xF2, 0x0F, 0x5A);
11165 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11166 ins_pipe(pipe_slow); // XXX
11167 %}
11169 // XXX do mem variants
11170 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
11171 %{
11172 match(Set dst (ConvF2I src));
11173 effect(KILL cr);
11175 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
11176 "cmpl $dst, #0x80000000\n\t"
11177 "jne,s done\n\t"
11178 "subq rsp, #8\n\t"
11179 "movss [rsp], $src\n\t"
11180 "call f2i_fixup\n\t"
11181 "popq $dst\n"
11182 "done: "%}
11183 opcode(0xF3, 0x0F, 0x2C);
11184 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
11185 f2i_fixup(dst, src));
11186 ins_pipe(pipe_slow);
11187 %}
11189 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
11190 %{
11191 match(Set dst (ConvF2L src));
11192 effect(KILL cr);
11194 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
11195 "cmpq $dst, [0x8000000000000000]\n\t"
11196 "jne,s done\n\t"
11197 "subq rsp, #8\n\t"
11198 "movss [rsp], $src\n\t"
11199 "call f2l_fixup\n\t"
11200 "popq $dst\n"
11201 "done: "%}
11202 opcode(0xF3, 0x0F, 0x2C);
11203 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
11204 f2l_fixup(dst, src));
11205 ins_pipe(pipe_slow);
11206 %}
11208 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
11209 %{
11210 match(Set dst (ConvD2I src));
11211 effect(KILL cr);
11213 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
11214 "cmpl $dst, #0x80000000\n\t"
11215 "jne,s done\n\t"
11216 "subq rsp, #8\n\t"
11217 "movsd [rsp], $src\n\t"
11218 "call d2i_fixup\n\t"
11219 "popq $dst\n"
11220 "done: "%}
11221 opcode(0xF2, 0x0F, 0x2C);
11222 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
11223 d2i_fixup(dst, src));
11224 ins_pipe(pipe_slow);
11225 %}
11227 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
11228 %{
11229 match(Set dst (ConvD2L src));
11230 effect(KILL cr);
11232 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
11233 "cmpq $dst, [0x8000000000000000]\n\t"
11234 "jne,s done\n\t"
11235 "subq rsp, #8\n\t"
11236 "movsd [rsp], $src\n\t"
11237 "call d2l_fixup\n\t"
11238 "popq $dst\n"
11239 "done: "%}
11240 opcode(0xF2, 0x0F, 0x2C);
11241 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
11242 d2l_fixup(dst, src));
11243 ins_pipe(pipe_slow);
11244 %}
11246 instruct convI2F_reg_reg(regF dst, rRegI src)
11247 %{
11248 predicate(!UseXmmI2F);
11249 match(Set dst (ConvI2F src));
11251 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11252 opcode(0xF3, 0x0F, 0x2A);
11253 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
11254 ins_pipe(pipe_slow); // XXX
11255 %}
11257 instruct convI2F_reg_mem(regF dst, memory src)
11258 %{
11259 match(Set dst (ConvI2F (LoadI src)));
11261 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11262 opcode(0xF3, 0x0F, 0x2A);
11263 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11264 ins_pipe(pipe_slow); // XXX
11265 %}
11267 instruct convI2D_reg_reg(regD dst, rRegI src)
11268 %{
11269 predicate(!UseXmmI2D);
11270 match(Set dst (ConvI2D src));
11272 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11273 opcode(0xF2, 0x0F, 0x2A);
11274 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
11275 ins_pipe(pipe_slow); // XXX
11276 %}
11278 instruct convI2D_reg_mem(regD dst, memory src)
11279 %{
11280 match(Set dst (ConvI2D (LoadI src)));
11282 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11283 opcode(0xF2, 0x0F, 0x2A);
11284 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11285 ins_pipe(pipe_slow); // XXX
11286 %}
11288 instruct convXI2F_reg(regF dst, rRegI src)
11289 %{
11290 predicate(UseXmmI2F);
11291 match(Set dst (ConvI2F src));
11293 format %{ "movdl $dst, $src\n\t"
11294 "cvtdq2psl $dst, $dst\t# i2f" %}
11295 ins_encode %{
11296 __ movdl($dst$$XMMRegister, $src$$Register);
11297 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11298 %}
11299 ins_pipe(pipe_slow); // XXX
11300 %}
11302 instruct convXI2D_reg(regD dst, rRegI src)
11303 %{
11304 predicate(UseXmmI2D);
11305 match(Set dst (ConvI2D src));
11307 format %{ "movdl $dst, $src\n\t"
11308 "cvtdq2pdl $dst, $dst\t# i2d" %}
11309 ins_encode %{
11310 __ movdl($dst$$XMMRegister, $src$$Register);
11311 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11312 %}
11313 ins_pipe(pipe_slow); // XXX
11314 %}
11316 instruct convL2F_reg_reg(regF dst, rRegL src)
11317 %{
11318 match(Set dst (ConvL2F src));
11320 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11321 opcode(0xF3, 0x0F, 0x2A);
11322 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
11323 ins_pipe(pipe_slow); // XXX
11324 %}
11326 instruct convL2F_reg_mem(regF dst, memory src)
11327 %{
11328 match(Set dst (ConvL2F (LoadL src)));
11330 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11331 opcode(0xF3, 0x0F, 0x2A);
11332 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
11333 ins_pipe(pipe_slow); // XXX
11334 %}
11336 instruct convL2D_reg_reg(regD dst, rRegL src)
11337 %{
11338 match(Set dst (ConvL2D src));
11340 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11341 opcode(0xF2, 0x0F, 0x2A);
11342 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
11343 ins_pipe(pipe_slow); // XXX
11344 %}
11346 instruct convL2D_reg_mem(regD dst, memory src)
11347 %{
11348 match(Set dst (ConvL2D (LoadL src)));
11350 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11351 opcode(0xF2, 0x0F, 0x2A);
11352 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
11353 ins_pipe(pipe_slow); // XXX
11354 %}
11356 instruct convI2L_reg_reg(rRegL dst, rRegI src)
11357 %{
11358 match(Set dst (ConvI2L src));
11360 ins_cost(125);
11361 format %{ "movslq $dst, $src\t# i2l" %}
11362 ins_encode %{
11363 __ movslq($dst$$Register, $src$$Register);
11364 %}
11365 ins_pipe(ialu_reg_reg);
11366 %}
11368 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
11369 // %{
11370 // match(Set dst (ConvI2L src));
11371 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
11372 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
11373 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
11374 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
11375 // ((const TypeNode*) n)->type()->is_long()->_lo ==
11376 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
11378 // format %{ "movl $dst, $src\t# unsigned i2l" %}
11379 // ins_encode(enc_copy(dst, src));
11380 // // opcode(0x63); // needs REX.W
11381 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
11382 // ins_pipe(ialu_reg_reg);
11383 // %}
11385 // Zero-extend convert int to long
11386 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
11387 %{
11388 match(Set dst (AndL (ConvI2L src) mask));
11390 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11391 ins_encode(enc_copy(dst, src));
11392 ins_pipe(ialu_reg_reg);
11393 %}
11395 // Zero-extend convert int to long
11396 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
11397 %{
11398 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
11400 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11401 opcode(0x8B);
11402 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
11403 ins_pipe(ialu_reg_mem);
11404 %}
11406 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
11407 %{
11408 match(Set dst (AndL src mask));
11410 format %{ "movl $dst, $src\t# zero-extend long" %}
11411 ins_encode(enc_copy_always(dst, src));
11412 ins_pipe(ialu_reg_reg);
11413 %}
11415 instruct convL2I_reg_reg(rRegI dst, rRegL src)
11416 %{
11417 match(Set dst (ConvL2I src));
11419 format %{ "movl $dst, $src\t# l2i" %}
11420 ins_encode(enc_copy_always(dst, src));
11421 ins_pipe(ialu_reg_reg);
11422 %}
11425 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11426 match(Set dst (MoveF2I src));
11427 effect(DEF dst, USE src);
11429 ins_cost(125);
11430 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
11431 opcode(0x8B);
11432 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
11433 ins_pipe(ialu_reg_mem);
11434 %}
11436 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11437 match(Set dst (MoveI2F src));
11438 effect(DEF dst, USE src);
11440 ins_cost(125);
11441 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
11442 opcode(0xF3, 0x0F, 0x10);
11443 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11444 ins_pipe(pipe_slow);
11445 %}
11447 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
11448 match(Set dst (MoveD2L src));
11449 effect(DEF dst, USE src);
11451 ins_cost(125);
11452 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
11453 opcode(0x8B);
11454 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
11455 ins_pipe(ialu_reg_mem);
11456 %}
11458 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
11459 predicate(!UseXmmLoadAndClearUpper);
11460 match(Set dst (MoveL2D src));
11461 effect(DEF dst, USE src);
11463 ins_cost(125);
11464 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
11465 opcode(0x66, 0x0F, 0x12);
11466 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11467 ins_pipe(pipe_slow);
11468 %}
11470 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11471 predicate(UseXmmLoadAndClearUpper);
11472 match(Set dst (MoveL2D src));
11473 effect(DEF dst, USE src);
11475 ins_cost(125);
11476 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
11477 opcode(0xF2, 0x0F, 0x10);
11478 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11479 ins_pipe(pipe_slow);
11480 %}
11483 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11484 match(Set dst (MoveF2I src));
11485 effect(DEF dst, USE src);
11487 ins_cost(95); // XXX
11488 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
11489 opcode(0xF3, 0x0F, 0x11);
11490 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
11491 ins_pipe(pipe_slow);
11492 %}
11494 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11495 match(Set dst (MoveI2F src));
11496 effect(DEF dst, USE src);
11498 ins_cost(100);
11499 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
11500 opcode(0x89);
11501 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
11502 ins_pipe( ialu_mem_reg );
11503 %}
11505 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11506 match(Set dst (MoveD2L src));
11507 effect(DEF dst, USE src);
11509 ins_cost(95); // XXX
11510 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
11511 opcode(0xF2, 0x0F, 0x11);
11512 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
11513 ins_pipe(pipe_slow);
11514 %}
11516 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11517 match(Set dst (MoveL2D src));
11518 effect(DEF dst, USE src);
11520 ins_cost(100);
11521 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
11522 opcode(0x89);
11523 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
11524 ins_pipe(ialu_mem_reg);
11525 %}
11527 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11528 match(Set dst (MoveF2I src));
11529 effect(DEF dst, USE src);
11530 ins_cost(85);
11531 format %{ "movd $dst,$src\t# MoveF2I" %}
11532 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %}
11533 ins_pipe( pipe_slow );
11534 %}
11536 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11537 match(Set dst (MoveD2L src));
11538 effect(DEF dst, USE src);
11539 ins_cost(85);
11540 format %{ "movd $dst,$src\t# MoveD2L" %}
11541 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %}
11542 ins_pipe( pipe_slow );
11543 %}
11545 // The next instructions have long latency and use Int unit. Set high cost.
11546 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11547 match(Set dst (MoveI2F src));
11548 effect(DEF dst, USE src);
11549 ins_cost(300);
11550 format %{ "movd $dst,$src\t# MoveI2F" %}
11551 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %}
11552 ins_pipe( pipe_slow );
11553 %}
11555 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11556 match(Set dst (MoveL2D src));
11557 effect(DEF dst, USE src);
11558 ins_cost(300);
11559 format %{ "movd $dst,$src\t# MoveL2D" %}
11560 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %}
11561 ins_pipe( pipe_slow );
11562 %}
11564 // Replicate scalar to packed byte (1 byte) values in xmm
11565 instruct Repl8B_reg(regD dst, regD src) %{
11566 match(Set dst (Replicate8B src));
11567 format %{ "MOVDQA $dst,$src\n\t"
11568 "PUNPCKLBW $dst,$dst\n\t"
11569 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11570 ins_encode( pshufd_8x8(dst, src));
11571 ins_pipe( pipe_slow );
11572 %}
11574 // Replicate scalar to packed byte (1 byte) values in xmm
11575 instruct Repl8B_rRegI(regD dst, rRegI src) %{
11576 match(Set dst (Replicate8B src));
11577 format %{ "MOVD $dst,$src\n\t"
11578 "PUNPCKLBW $dst,$dst\n\t"
11579 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11580 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11581 ins_pipe( pipe_slow );
11582 %}
11584 // Replicate scalar zero to packed byte (1 byte) values in xmm
11585 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11586 match(Set dst (Replicate8B zero));
11587 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11588 ins_encode( pxor(dst, dst));
11589 ins_pipe( fpu_reg_reg );
11590 %}
11592 // Replicate scalar to packed shore (2 byte) values in xmm
11593 instruct Repl4S_reg(regD dst, regD src) %{
11594 match(Set dst (Replicate4S src));
11595 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11596 ins_encode( pshufd_4x16(dst, src));
11597 ins_pipe( fpu_reg_reg );
11598 %}
11600 // Replicate scalar to packed shore (2 byte) values in xmm
11601 instruct Repl4S_rRegI(regD dst, rRegI src) %{
11602 match(Set dst (Replicate4S src));
11603 format %{ "MOVD $dst,$src\n\t"
11604 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11605 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11606 ins_pipe( fpu_reg_reg );
11607 %}
11609 // Replicate scalar zero to packed short (2 byte) values in xmm
11610 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11611 match(Set dst (Replicate4S zero));
11612 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11613 ins_encode( pxor(dst, dst));
11614 ins_pipe( fpu_reg_reg );
11615 %}
11617 // Replicate scalar to packed char (2 byte) values in xmm
11618 instruct Repl4C_reg(regD dst, regD src) %{
11619 match(Set dst (Replicate4C src));
11620 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11621 ins_encode( pshufd_4x16(dst, src));
11622 ins_pipe( fpu_reg_reg );
11623 %}
11625 // Replicate scalar to packed char (2 byte) values in xmm
11626 instruct Repl4C_rRegI(regD dst, rRegI src) %{
11627 match(Set dst (Replicate4C src));
11628 format %{ "MOVD $dst,$src\n\t"
11629 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11630 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11631 ins_pipe( fpu_reg_reg );
11632 %}
11634 // Replicate scalar zero to packed char (2 byte) values in xmm
11635 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11636 match(Set dst (Replicate4C zero));
11637 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11638 ins_encode( pxor(dst, dst));
11639 ins_pipe( fpu_reg_reg );
11640 %}
11642 // Replicate scalar to packed integer (4 byte) values in xmm
11643 instruct Repl2I_reg(regD dst, regD src) %{
11644 match(Set dst (Replicate2I src));
11645 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11646 ins_encode( pshufd(dst, src, 0x00));
11647 ins_pipe( fpu_reg_reg );
11648 %}
11650 // Replicate scalar to packed integer (4 byte) values in xmm
11651 instruct Repl2I_rRegI(regD dst, rRegI src) %{
11652 match(Set dst (Replicate2I src));
11653 format %{ "MOVD $dst,$src\n\t"
11654 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11655 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
11656 ins_pipe( fpu_reg_reg );
11657 %}
11659 // Replicate scalar zero to packed integer (2 byte) values in xmm
11660 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11661 match(Set dst (Replicate2I zero));
11662 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11663 ins_encode( pxor(dst, dst));
11664 ins_pipe( fpu_reg_reg );
11665 %}
11667 // Replicate scalar to packed single precision floating point values in xmm
11668 instruct Repl2F_reg(regD dst, regD src) %{
11669 match(Set dst (Replicate2F src));
11670 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11671 ins_encode( pshufd(dst, src, 0xe0));
11672 ins_pipe( fpu_reg_reg );
11673 %}
11675 // Replicate scalar to packed single precision floating point values in xmm
11676 instruct Repl2F_regF(regD dst, regF src) %{
11677 match(Set dst (Replicate2F src));
11678 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11679 ins_encode( pshufd(dst, src, 0xe0));
11680 ins_pipe( fpu_reg_reg );
11681 %}
11683 // Replicate scalar to packed single precision floating point values in xmm
11684 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11685 match(Set dst (Replicate2F zero));
11686 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11687 ins_encode( pxor(dst, dst));
11688 ins_pipe( fpu_reg_reg );
11689 %}
11692 // =======================================================================
11693 // fast clearing of an array
11694 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
11695 rFlagsReg cr)
11696 %{
11697 match(Set dummy (ClearArray cnt base));
11698 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11700 format %{ "xorl rax, rax\t# ClearArray:\n\t"
11701 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
11702 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
11703 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
11704 ins_pipe(pipe_slow);
11705 %}
11707 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rbx_RegI cnt2,
11708 rax_RegI result, regD tmp1, regD tmp2, rFlagsReg cr)
11709 %{
11710 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11711 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11713 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %}
11714 ins_encode %{
11715 __ string_compare($str1$$Register, $str2$$Register,
11716 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11717 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11718 %}
11719 ins_pipe( pipe_slow );
11720 %}
11722 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11723 rbx_RegI result, regD tmp1, rcx_RegI tmp2, rFlagsReg cr)
11724 %{
11725 predicate(UseSSE42Intrinsics);
11726 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11727 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr);
11729 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %}
11730 ins_encode %{
11731 __ string_indexof($str1$$Register, $str2$$Register,
11732 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11733 $tmp1$$XMMRegister, $tmp2$$Register);
11734 %}
11735 ins_pipe( pipe_slow );
11736 %}
11738 // fast string equals
11739 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11740 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11741 %{
11742 match(Set result (StrEquals (Binary str1 str2) cnt));
11743 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11745 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11746 ins_encode %{
11747 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11748 $cnt$$Register, $result$$Register, $tmp3$$Register,
11749 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11750 %}
11751 ins_pipe( pipe_slow );
11752 %}
11754 // fast array equals
11755 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11756 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11757 %{
11758 match(Set result (AryEq ary1 ary2));
11759 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11760 //ins_cost(300);
11762 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11763 ins_encode %{
11764 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11765 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11766 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11767 %}
11768 ins_pipe( pipe_slow );
11769 %}
11771 //----------Control Flow Instructions------------------------------------------
11772 // Signed compare Instructions
11774 // XXX more variants!!
11775 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11776 %{
11777 match(Set cr (CmpI op1 op2));
11778 effect(DEF cr, USE op1, USE op2);
11780 format %{ "cmpl $op1, $op2" %}
11781 opcode(0x3B); /* Opcode 3B /r */
11782 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11783 ins_pipe(ialu_cr_reg_reg);
11784 %}
11786 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11787 %{
11788 match(Set cr (CmpI op1 op2));
11790 format %{ "cmpl $op1, $op2" %}
11791 opcode(0x81, 0x07); /* Opcode 81 /7 */
11792 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11793 ins_pipe(ialu_cr_reg_imm);
11794 %}
11796 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11797 %{
11798 match(Set cr (CmpI op1 (LoadI op2)));
11800 ins_cost(500); // XXX
11801 format %{ "cmpl $op1, $op2" %}
11802 opcode(0x3B); /* Opcode 3B /r */
11803 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11804 ins_pipe(ialu_cr_reg_mem);
11805 %}
11807 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11808 %{
11809 match(Set cr (CmpI src zero));
11811 format %{ "testl $src, $src" %}
11812 opcode(0x85);
11813 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11814 ins_pipe(ialu_cr_reg_imm);
11815 %}
11817 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11818 %{
11819 match(Set cr (CmpI (AndI src con) zero));
11821 format %{ "testl $src, $con" %}
11822 opcode(0xF7, 0x00);
11823 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11824 ins_pipe(ialu_cr_reg_imm);
11825 %}
11827 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11828 %{
11829 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11831 format %{ "testl $src, $mem" %}
11832 opcode(0x85);
11833 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11834 ins_pipe(ialu_cr_reg_mem);
11835 %}
11837 // Unsigned compare Instructions; really, same as signed except they
11838 // produce an rFlagsRegU instead of rFlagsReg.
11839 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11840 %{
11841 match(Set cr (CmpU op1 op2));
11843 format %{ "cmpl $op1, $op2\t# unsigned" %}
11844 opcode(0x3B); /* Opcode 3B /r */
11845 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11846 ins_pipe(ialu_cr_reg_reg);
11847 %}
11849 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11850 %{
11851 match(Set cr (CmpU op1 op2));
11853 format %{ "cmpl $op1, $op2\t# unsigned" %}
11854 opcode(0x81,0x07); /* Opcode 81 /7 */
11855 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11856 ins_pipe(ialu_cr_reg_imm);
11857 %}
11859 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11860 %{
11861 match(Set cr (CmpU op1 (LoadI op2)));
11863 ins_cost(500); // XXX
11864 format %{ "cmpl $op1, $op2\t# unsigned" %}
11865 opcode(0x3B); /* Opcode 3B /r */
11866 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11867 ins_pipe(ialu_cr_reg_mem);
11868 %}
11870 // // // Cisc-spilled version of cmpU_rReg
11871 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11872 // //%{
11873 // // match(Set cr (CmpU (LoadI op1) op2));
11874 // //
11875 // // format %{ "CMPu $op1,$op2" %}
11876 // // ins_cost(500);
11877 // // opcode(0x39); /* Opcode 39 /r */
11878 // // ins_encode( OpcP, reg_mem( op1, op2) );
11879 // //%}
11881 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11882 %{
11883 match(Set cr (CmpU src zero));
11885 format %{ "testl $src, $src\t# unsigned" %}
11886 opcode(0x85);
11887 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11888 ins_pipe(ialu_cr_reg_imm);
11889 %}
11891 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11892 %{
11893 match(Set cr (CmpP op1 op2));
11895 format %{ "cmpq $op1, $op2\t# ptr" %}
11896 opcode(0x3B); /* Opcode 3B /r */
11897 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11898 ins_pipe(ialu_cr_reg_reg);
11899 %}
11901 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11902 %{
11903 match(Set cr (CmpP op1 (LoadP op2)));
11905 ins_cost(500); // XXX
11906 format %{ "cmpq $op1, $op2\t# ptr" %}
11907 opcode(0x3B); /* Opcode 3B /r */
11908 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11909 ins_pipe(ialu_cr_reg_mem);
11910 %}
11912 // // // Cisc-spilled version of cmpP_rReg
11913 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11914 // //%{
11915 // // match(Set cr (CmpP (LoadP op1) op2));
11916 // //
11917 // // format %{ "CMPu $op1,$op2" %}
11918 // // ins_cost(500);
11919 // // opcode(0x39); /* Opcode 39 /r */
11920 // // ins_encode( OpcP, reg_mem( op1, op2) );
11921 // //%}
11923 // XXX this is generalized by compP_rReg_mem???
11924 // Compare raw pointer (used in out-of-heap check).
11925 // Only works because non-oop pointers must be raw pointers
11926 // and raw pointers have no anti-dependencies.
11927 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11928 %{
11929 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
11930 match(Set cr (CmpP op1 (LoadP op2)));
11932 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11933 opcode(0x3B); /* Opcode 3B /r */
11934 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11935 ins_pipe(ialu_cr_reg_mem);
11936 %}
11938 // This will generate a signed flags result. This should be OK since
11939 // any compare to a zero should be eq/neq.
11940 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11941 %{
11942 match(Set cr (CmpP src zero));
11944 format %{ "testq $src, $src\t# ptr" %}
11945 opcode(0x85);
11946 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11947 ins_pipe(ialu_cr_reg_imm);
11948 %}
11950 // This will generate a signed flags result. This should be OK since
11951 // any compare to a zero should be eq/neq.
11952 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11953 %{
11954 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11955 match(Set cr (CmpP (LoadP op) zero));
11957 ins_cost(500); // XXX
11958 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11959 opcode(0xF7); /* Opcode F7 /0 */
11960 ins_encode(REX_mem_wide(op),
11961 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11962 ins_pipe(ialu_cr_reg_imm);
11963 %}
11965 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11966 %{
11967 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
11968 match(Set cr (CmpP (LoadP mem) zero));
11970 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11971 ins_encode %{
11972 __ cmpq(r12, $mem$$Address);
11973 %}
11974 ins_pipe(ialu_cr_reg_mem);
11975 %}
11977 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11978 %{
11979 match(Set cr (CmpN op1 op2));
11981 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11982 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11983 ins_pipe(ialu_cr_reg_reg);
11984 %}
11986 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11987 %{
11988 match(Set cr (CmpN src (LoadN mem)));
11990 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11991 ins_encode %{
11992 __ cmpl($src$$Register, $mem$$Address);
11993 %}
11994 ins_pipe(ialu_cr_reg_mem);
11995 %}
11997 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11998 match(Set cr (CmpN op1 op2));
12000 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12001 ins_encode %{
12002 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
12003 %}
12004 ins_pipe(ialu_cr_reg_imm);
12005 %}
12007 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
12008 %{
12009 match(Set cr (CmpN src (LoadN mem)));
12011 format %{ "cmpl $mem, $src\t# compressed ptr" %}
12012 ins_encode %{
12013 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
12014 %}
12015 ins_pipe(ialu_cr_reg_mem);
12016 %}
12018 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12019 match(Set cr (CmpN src zero));
12021 format %{ "testl $src, $src\t# compressed ptr" %}
12022 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12023 ins_pipe(ialu_cr_reg_imm);
12024 %}
12026 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12027 %{
12028 predicate(Universe::narrow_oop_base() != NULL);
12029 match(Set cr (CmpN (LoadN mem) zero));
12031 ins_cost(500); // XXX
12032 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
12033 ins_encode %{
12034 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12035 %}
12036 ins_pipe(ialu_cr_reg_mem);
12037 %}
12039 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12040 %{
12041 predicate(Universe::narrow_oop_base() == NULL);
12042 match(Set cr (CmpN (LoadN mem) zero));
12044 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12045 ins_encode %{
12046 __ cmpl(r12, $mem$$Address);
12047 %}
12048 ins_pipe(ialu_cr_reg_mem);
12049 %}
12051 // Yanked all unsigned pointer compare operations.
12052 // Pointer compares are done with CmpP which is already unsigned.
12054 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12055 %{
12056 match(Set cr (CmpL op1 op2));
12058 format %{ "cmpq $op1, $op2" %}
12059 opcode(0x3B); /* Opcode 3B /r */
12060 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12061 ins_pipe(ialu_cr_reg_reg);
12062 %}
12064 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12065 %{
12066 match(Set cr (CmpL op1 op2));
12068 format %{ "cmpq $op1, $op2" %}
12069 opcode(0x81, 0x07); /* Opcode 81 /7 */
12070 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12071 ins_pipe(ialu_cr_reg_imm);
12072 %}
12074 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12075 %{
12076 match(Set cr (CmpL op1 (LoadL op2)));
12078 format %{ "cmpq $op1, $op2" %}
12079 opcode(0x3B); /* Opcode 3B /r */
12080 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12081 ins_pipe(ialu_cr_reg_mem);
12082 %}
12084 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12085 %{
12086 match(Set cr (CmpL src zero));
12088 format %{ "testq $src, $src" %}
12089 opcode(0x85);
12090 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12091 ins_pipe(ialu_cr_reg_imm);
12092 %}
12094 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12095 %{
12096 match(Set cr (CmpL (AndL src con) zero));
12098 format %{ "testq $src, $con\t# long" %}
12099 opcode(0xF7, 0x00);
12100 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
12101 ins_pipe(ialu_cr_reg_imm);
12102 %}
12104 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12105 %{
12106 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12108 format %{ "testq $src, $mem" %}
12109 opcode(0x85);
12110 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12111 ins_pipe(ialu_cr_reg_mem);
12112 %}
12114 // Manifest a CmpL result in an integer register. Very painful.
12115 // This is the test to avoid.
12116 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12117 %{
12118 match(Set dst (CmpL3 src1 src2));
12119 effect(KILL flags);
12121 ins_cost(275); // XXX
12122 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12123 "movl $dst, -1\n\t"
12124 "jl,s done\n\t"
12125 "setne $dst\n\t"
12126 "movzbl $dst, $dst\n\t"
12127 "done:" %}
12128 ins_encode(cmpl3_flag(src1, src2, dst));
12129 ins_pipe(pipe_slow);
12130 %}
12132 //----------Max and Min--------------------------------------------------------
12133 // Min Instructions
12135 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12136 %{
12137 effect(USE_DEF dst, USE src, USE cr);
12139 format %{ "cmovlgt $dst, $src\t# min" %}
12140 opcode(0x0F, 0x4F);
12141 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12142 ins_pipe(pipe_cmov_reg);
12143 %}
12146 instruct minI_rReg(rRegI dst, rRegI src)
12147 %{
12148 match(Set dst (MinI dst src));
12150 ins_cost(200);
12151 expand %{
12152 rFlagsReg cr;
12153 compI_rReg(cr, dst, src);
12154 cmovI_reg_g(dst, src, cr);
12155 %}
12156 %}
12158 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12159 %{
12160 effect(USE_DEF dst, USE src, USE cr);
12162 format %{ "cmovllt $dst, $src\t# max" %}
12163 opcode(0x0F, 0x4C);
12164 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12165 ins_pipe(pipe_cmov_reg);
12166 %}
12169 instruct maxI_rReg(rRegI dst, rRegI src)
12170 %{
12171 match(Set dst (MaxI dst src));
12173 ins_cost(200);
12174 expand %{
12175 rFlagsReg cr;
12176 compI_rReg(cr, dst, src);
12177 cmovI_reg_l(dst, src, cr);
12178 %}
12179 %}
12181 // ============================================================================
12182 // Branch Instructions
12184 // Jump Direct - Label defines a relative address from JMP+1
12185 instruct jmpDir(label labl)
12186 %{
12187 match(Goto);
12188 effect(USE labl);
12190 ins_cost(300);
12191 format %{ "jmp $labl" %}
12192 size(5);
12193 opcode(0xE9);
12194 ins_encode(OpcP, Lbl(labl));
12195 ins_pipe(pipe_jmp);
12196 ins_pc_relative(1);
12197 %}
12199 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12200 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12201 %{
12202 match(If cop cr);
12203 effect(USE labl);
12205 ins_cost(300);
12206 format %{ "j$cop $labl" %}
12207 size(6);
12208 opcode(0x0F, 0x80);
12209 ins_encode(Jcc(cop, labl));
12210 ins_pipe(pipe_jcc);
12211 ins_pc_relative(1);
12212 %}
12214 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12215 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12216 %{
12217 match(CountedLoopEnd cop cr);
12218 effect(USE labl);
12220 ins_cost(300);
12221 format %{ "j$cop $labl\t# loop end" %}
12222 size(6);
12223 opcode(0x0F, 0x80);
12224 ins_encode(Jcc(cop, labl));
12225 ins_pipe(pipe_jcc);
12226 ins_pc_relative(1);
12227 %}
12229 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12230 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12231 match(CountedLoopEnd cop cmp);
12232 effect(USE labl);
12234 ins_cost(300);
12235 format %{ "j$cop,u $labl\t# loop end" %}
12236 size(6);
12237 opcode(0x0F, 0x80);
12238 ins_encode(Jcc(cop, labl));
12239 ins_pipe(pipe_jcc);
12240 ins_pc_relative(1);
12241 %}
12243 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12244 match(CountedLoopEnd cop cmp);
12245 effect(USE labl);
12247 ins_cost(200);
12248 format %{ "j$cop,u $labl\t# loop end" %}
12249 size(6);
12250 opcode(0x0F, 0x80);
12251 ins_encode(Jcc(cop, labl));
12252 ins_pipe(pipe_jcc);
12253 ins_pc_relative(1);
12254 %}
12256 // Jump Direct Conditional - using unsigned comparison
12257 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12258 match(If cop cmp);
12259 effect(USE labl);
12261 ins_cost(300);
12262 format %{ "j$cop,u $labl" %}
12263 size(6);
12264 opcode(0x0F, 0x80);
12265 ins_encode(Jcc(cop, labl));
12266 ins_pipe(pipe_jcc);
12267 ins_pc_relative(1);
12268 %}
12270 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12271 match(If cop cmp);
12272 effect(USE labl);
12274 ins_cost(200);
12275 format %{ "j$cop,u $labl" %}
12276 size(6);
12277 opcode(0x0F, 0x80);
12278 ins_encode(Jcc(cop, labl));
12279 ins_pipe(pipe_jcc);
12280 ins_pc_relative(1);
12281 %}
12283 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12284 match(If cop cmp);
12285 effect(USE labl);
12287 ins_cost(200);
12288 format %{ $$template
12289 if ($cop$$cmpcode == Assembler::notEqual) {
12290 $$emit$$"jp,u $labl\n\t"
12291 $$emit$$"j$cop,u $labl"
12292 } else {
12293 $$emit$$"jp,u done\n\t"
12294 $$emit$$"j$cop,u $labl\n\t"
12295 $$emit$$"done:"
12296 }
12297 %}
12298 size(12);
12299 opcode(0x0F, 0x80);
12300 ins_encode %{
12301 Label* l = $labl$$label;
12302 $$$emit8$primary;
12303 emit_cc(cbuf, $secondary, Assembler::parity);
12304 int parity_disp = -1;
12305 if ($cop$$cmpcode == Assembler::notEqual) {
12306 // the two jumps 6 bytes apart so the jump distances are too
12307 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12308 } else if ($cop$$cmpcode == Assembler::equal) {
12309 parity_disp = 6;
12310 } else {
12311 ShouldNotReachHere();
12312 }
12313 emit_d32(cbuf, parity_disp);
12314 $$$emit8$primary;
12315 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12316 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12317 emit_d32(cbuf, disp);
12318 %}
12319 ins_pipe(pipe_jcc);
12320 ins_pc_relative(1);
12321 %}
12323 // ============================================================================
12324 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12325 // superklass array for an instance of the superklass. Set a hidden
12326 // internal cache on a hit (cache is checked with exposed code in
12327 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12328 // encoding ALSO sets flags.
12330 instruct partialSubtypeCheck(rdi_RegP result,
12331 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12332 rFlagsReg cr)
12333 %{
12334 match(Set result (PartialSubtypeCheck sub super));
12335 effect(KILL rcx, KILL cr);
12337 ins_cost(1100); // slightly larger than the next version
12338 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
12339 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
12340 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
12341 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12342 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12343 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
12344 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12345 "miss:\t" %}
12347 opcode(0x1); // Force a XOR of RDI
12348 ins_encode(enc_PartialSubtypeCheck());
12349 ins_pipe(pipe_slow);
12350 %}
12352 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12353 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12354 immP0 zero,
12355 rdi_RegP result)
12356 %{
12357 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12358 effect(KILL rcx, KILL result);
12360 ins_cost(1000);
12361 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
12362 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
12363 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
12364 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12365 "jne,s miss\t\t# Missed: flags nz\n\t"
12366 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
12367 "miss:\t" %}
12369 opcode(0x0); // No need to XOR RDI
12370 ins_encode(enc_PartialSubtypeCheck());
12371 ins_pipe(pipe_slow);
12372 %}
12374 // ============================================================================
12375 // Branch Instructions -- short offset versions
12376 //
12377 // These instructions are used to replace jumps of a long offset (the default
12378 // match) with jumps of a shorter offset. These instructions are all tagged
12379 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12380 // match rules in general matching. Instead, the ADLC generates a conversion
12381 // method in the MachNode which can be used to do in-place replacement of the
12382 // long variant with the shorter variant. The compiler will determine if a
12383 // branch can be taken by the is_short_branch_offset() predicate in the machine
12384 // specific code section of the file.
12386 // Jump Direct - Label defines a relative address from JMP+1
12387 instruct jmpDir_short(label labl) %{
12388 match(Goto);
12389 effect(USE labl);
12391 ins_cost(300);
12392 format %{ "jmp,s $labl" %}
12393 size(2);
12394 opcode(0xEB);
12395 ins_encode(OpcP, LblShort(labl));
12396 ins_pipe(pipe_jmp);
12397 ins_pc_relative(1);
12398 ins_short_branch(1);
12399 %}
12401 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12402 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12403 match(If cop cr);
12404 effect(USE labl);
12406 ins_cost(300);
12407 format %{ "j$cop,s $labl" %}
12408 size(2);
12409 opcode(0x70);
12410 ins_encode(JccShort(cop, labl));
12411 ins_pipe(pipe_jcc);
12412 ins_pc_relative(1);
12413 ins_short_branch(1);
12414 %}
12416 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12417 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12418 match(CountedLoopEnd cop cr);
12419 effect(USE labl);
12421 ins_cost(300);
12422 format %{ "j$cop,s $labl\t# loop end" %}
12423 size(2);
12424 opcode(0x70);
12425 ins_encode(JccShort(cop, labl));
12426 ins_pipe(pipe_jcc);
12427 ins_pc_relative(1);
12428 ins_short_branch(1);
12429 %}
12431 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12432 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12433 match(CountedLoopEnd cop cmp);
12434 effect(USE labl);
12436 ins_cost(300);
12437 format %{ "j$cop,us $labl\t# loop end" %}
12438 size(2);
12439 opcode(0x70);
12440 ins_encode(JccShort(cop, labl));
12441 ins_pipe(pipe_jcc);
12442 ins_pc_relative(1);
12443 ins_short_branch(1);
12444 %}
12446 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12447 match(CountedLoopEnd cop cmp);
12448 effect(USE labl);
12450 ins_cost(300);
12451 format %{ "j$cop,us $labl\t# loop end" %}
12452 size(2);
12453 opcode(0x70);
12454 ins_encode(JccShort(cop, labl));
12455 ins_pipe(pipe_jcc);
12456 ins_pc_relative(1);
12457 ins_short_branch(1);
12458 %}
12460 // Jump Direct Conditional - using unsigned comparison
12461 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12462 match(If cop cmp);
12463 effect(USE labl);
12465 ins_cost(300);
12466 format %{ "j$cop,us $labl" %}
12467 size(2);
12468 opcode(0x70);
12469 ins_encode(JccShort(cop, labl));
12470 ins_pipe(pipe_jcc);
12471 ins_pc_relative(1);
12472 ins_short_branch(1);
12473 %}
12475 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12476 match(If cop cmp);
12477 effect(USE labl);
12479 ins_cost(300);
12480 format %{ "j$cop,us $labl" %}
12481 size(2);
12482 opcode(0x70);
12483 ins_encode(JccShort(cop, labl));
12484 ins_pipe(pipe_jcc);
12485 ins_pc_relative(1);
12486 ins_short_branch(1);
12487 %}
12489 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12490 match(If cop cmp);
12491 effect(USE labl);
12493 ins_cost(300);
12494 format %{ $$template
12495 if ($cop$$cmpcode == Assembler::notEqual) {
12496 $$emit$$"jp,u,s $labl\n\t"
12497 $$emit$$"j$cop,u,s $labl"
12498 } else {
12499 $$emit$$"jp,u,s done\n\t"
12500 $$emit$$"j$cop,u,s $labl\n\t"
12501 $$emit$$"done:"
12502 }
12503 %}
12504 size(4);
12505 opcode(0x70);
12506 ins_encode %{
12507 Label* l = $labl$$label;
12508 emit_cc(cbuf, $primary, Assembler::parity);
12509 int parity_disp = -1;
12510 if ($cop$$cmpcode == Assembler::notEqual) {
12511 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12512 } else if ($cop$$cmpcode == Assembler::equal) {
12513 parity_disp = 2;
12514 } else {
12515 ShouldNotReachHere();
12516 }
12517 emit_d8(cbuf, parity_disp);
12518 emit_cc(cbuf, $primary, $cop$$cmpcode);
12519 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12520 emit_d8(cbuf, disp);
12521 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12522 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12523 %}
12524 ins_pipe(pipe_jcc);
12525 ins_pc_relative(1);
12526 ins_short_branch(1);
12527 %}
12529 // ============================================================================
12530 // inlined locking and unlocking
12532 instruct cmpFastLock(rFlagsReg cr,
12533 rRegP object, rRegP box, rax_RegI tmp, rRegP scr)
12534 %{
12535 match(Set cr (FastLock object box));
12536 effect(TEMP tmp, TEMP scr);
12538 ins_cost(300);
12539 format %{ "fastlock $object,$box,$tmp,$scr" %}
12540 ins_encode(Fast_Lock(object, box, tmp, scr));
12541 ins_pipe(pipe_slow);
12542 ins_pc_relative(1);
12543 %}
12545 instruct cmpFastUnlock(rFlagsReg cr,
12546 rRegP object, rax_RegP box, rRegP tmp)
12547 %{
12548 match(Set cr (FastUnlock object box));
12549 effect(TEMP tmp);
12551 ins_cost(300);
12552 format %{ "fastunlock $object, $box, $tmp" %}
12553 ins_encode(Fast_Unlock(object, box, tmp));
12554 ins_pipe(pipe_slow);
12555 ins_pc_relative(1);
12556 %}
12559 // ============================================================================
12560 // Safepoint Instructions
12561 instruct safePoint_poll(rFlagsReg cr)
12562 %{
12563 match(SafePoint);
12564 effect(KILL cr);
12566 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12567 "# Safepoint: poll for GC" %}
12568 size(6); // Opcode + ModRM + Disp32 == 6 bytes
12569 ins_cost(125);
12570 ins_encode(enc_safepoint_poll);
12571 ins_pipe(ialu_reg_mem);
12572 %}
12574 // ============================================================================
12575 // Procedure Call/Return Instructions
12576 // Call Java Static Instruction
12577 // Note: If this code changes, the corresponding ret_addr_offset() and
12578 // compute_padding() functions will have to be adjusted.
12579 instruct CallStaticJavaDirect(method meth) %{
12580 match(CallStaticJava);
12581 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
12582 effect(USE meth);
12584 ins_cost(300);
12585 format %{ "call,static " %}
12586 opcode(0xE8); /* E8 cd */
12587 ins_encode(Java_Static_Call(meth), call_epilog);
12588 ins_pipe(pipe_slow);
12589 ins_pc_relative(1);
12590 ins_alignment(4);
12591 %}
12593 // Call Java Static Instruction (method handle version)
12594 // Note: If this code changes, the corresponding ret_addr_offset() and
12595 // compute_padding() functions will have to be adjusted.
12596 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
12597 match(CallStaticJava);
12598 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
12599 effect(USE meth);
12600 // RBP is saved by all callees (for interpreter stack correction).
12601 // We use it here for a similar purpose, in {preserve,restore}_SP.
12603 ins_cost(300);
12604 format %{ "call,static/MethodHandle " %}
12605 opcode(0xE8); /* E8 cd */
12606 ins_encode(preserve_SP,
12607 Java_Static_Call(meth),
12608 restore_SP,
12609 call_epilog);
12610 ins_pipe(pipe_slow);
12611 ins_pc_relative(1);
12612 ins_alignment(4);
12613 %}
12615 // Call Java Dynamic Instruction
12616 // Note: If this code changes, the corresponding ret_addr_offset() and
12617 // compute_padding() functions will have to be adjusted.
12618 instruct CallDynamicJavaDirect(method meth)
12619 %{
12620 match(CallDynamicJava);
12621 effect(USE meth);
12623 ins_cost(300);
12624 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12625 "call,dynamic " %}
12626 opcode(0xE8); /* E8 cd */
12627 ins_encode(Java_Dynamic_Call(meth), call_epilog);
12628 ins_pipe(pipe_slow);
12629 ins_pc_relative(1);
12630 ins_alignment(4);
12631 %}
12633 // Call Runtime Instruction
12634 instruct CallRuntimeDirect(method meth)
12635 %{
12636 match(CallRuntime);
12637 effect(USE meth);
12639 ins_cost(300);
12640 format %{ "call,runtime " %}
12641 opcode(0xE8); /* E8 cd */
12642 ins_encode(Java_To_Runtime(meth));
12643 ins_pipe(pipe_slow);
12644 ins_pc_relative(1);
12645 %}
12647 // Call runtime without safepoint
12648 instruct CallLeafDirect(method meth)
12649 %{
12650 match(CallLeaf);
12651 effect(USE meth);
12653 ins_cost(300);
12654 format %{ "call_leaf,runtime " %}
12655 opcode(0xE8); /* E8 cd */
12656 ins_encode(Java_To_Runtime(meth));
12657 ins_pipe(pipe_slow);
12658 ins_pc_relative(1);
12659 %}
12661 // Call runtime without safepoint
12662 instruct CallLeafNoFPDirect(method meth)
12663 %{
12664 match(CallLeafNoFP);
12665 effect(USE meth);
12667 ins_cost(300);
12668 format %{ "call_leaf_nofp,runtime " %}
12669 opcode(0xE8); /* E8 cd */
12670 ins_encode(Java_To_Runtime(meth));
12671 ins_pipe(pipe_slow);
12672 ins_pc_relative(1);
12673 %}
12675 // Return Instruction
12676 // Remove the return address & jump to it.
12677 // Notice: We always emit a nop after a ret to make sure there is room
12678 // for safepoint patching
12679 instruct Ret()
12680 %{
12681 match(Return);
12683 format %{ "ret" %}
12684 opcode(0xC3);
12685 ins_encode(OpcP);
12686 ins_pipe(pipe_jmp);
12687 %}
12689 // Tail Call; Jump from runtime stub to Java code.
12690 // Also known as an 'interprocedural jump'.
12691 // Target of jump will eventually return to caller.
12692 // TailJump below removes the return address.
12693 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12694 %{
12695 match(TailCall jump_target method_oop);
12697 ins_cost(300);
12698 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12699 opcode(0xFF, 0x4); /* Opcode FF /4 */
12700 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12701 ins_pipe(pipe_jmp);
12702 %}
12704 // Tail Jump; remove the return address; jump to target.
12705 // TailCall above leaves the return address around.
12706 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12707 %{
12708 match(TailJump jump_target ex_oop);
12710 ins_cost(300);
12711 format %{ "popq rdx\t# pop return address\n\t"
12712 "jmp $jump_target" %}
12713 opcode(0xFF, 0x4); /* Opcode FF /4 */
12714 ins_encode(Opcode(0x5a), // popq rdx
12715 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12716 ins_pipe(pipe_jmp);
12717 %}
12719 // Create exception oop: created by stack-crawling runtime code.
12720 // Created exception is now available to this handler, and is setup
12721 // just prior to jumping to this handler. No code emitted.
12722 instruct CreateException(rax_RegP ex_oop)
12723 %{
12724 match(Set ex_oop (CreateEx));
12726 size(0);
12727 // use the following format syntax
12728 format %{ "# exception oop is in rax; no code emitted" %}
12729 ins_encode();
12730 ins_pipe(empty);
12731 %}
12733 // Rethrow exception:
12734 // The exception oop will come in the first argument position.
12735 // Then JUMP (not call) to the rethrow stub code.
12736 instruct RethrowException()
12737 %{
12738 match(Rethrow);
12740 // use the following format syntax
12741 format %{ "jmp rethrow_stub" %}
12742 ins_encode(enc_rethrow);
12743 ins_pipe(pipe_jmp);
12744 %}
12747 //----------PEEPHOLE RULES-----------------------------------------------------
12748 // These must follow all instruction definitions as they use the names
12749 // defined in the instructions definitions.
12750 //
12751 // peepmatch ( root_instr_name [preceding_instruction]* );
12752 //
12753 // peepconstraint %{
12754 // (instruction_number.operand_name relational_op instruction_number.operand_name
12755 // [, ...] );
12756 // // instruction numbers are zero-based using left to right order in peepmatch
12757 //
12758 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12759 // // provide an instruction_number.operand_name for each operand that appears
12760 // // in the replacement instruction's match rule
12761 //
12762 // ---------VM FLAGS---------------------------------------------------------
12763 //
12764 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12765 //
12766 // Each peephole rule is given an identifying number starting with zero and
12767 // increasing by one in the order seen by the parser. An individual peephole
12768 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12769 // on the command-line.
12770 //
12771 // ---------CURRENT LIMITATIONS----------------------------------------------
12772 //
12773 // Only match adjacent instructions in same basic block
12774 // Only equality constraints
12775 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12776 // Only one replacement instruction
12777 //
12778 // ---------EXAMPLE----------------------------------------------------------
12779 //
12780 // // pertinent parts of existing instructions in architecture description
12781 // instruct movI(rRegI dst, rRegI src)
12782 // %{
12783 // match(Set dst (CopyI src));
12784 // %}
12785 //
12786 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12787 // %{
12788 // match(Set dst (AddI dst src));
12789 // effect(KILL cr);
12790 // %}
12791 //
12792 // // Change (inc mov) to lea
12793 // peephole %{
12794 // // increment preceeded by register-register move
12795 // peepmatch ( incI_rReg movI );
12796 // // require that the destination register of the increment
12797 // // match the destination register of the move
12798 // peepconstraint ( 0.dst == 1.dst );
12799 // // construct a replacement instruction that sets
12800 // // the destination to ( move's source register + one )
12801 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12802 // %}
12803 //
12805 // Implementation no longer uses movX instructions since
12806 // machine-independent system no longer uses CopyX nodes.
12807 //
12808 // peephole
12809 // %{
12810 // peepmatch (incI_rReg movI);
12811 // peepconstraint (0.dst == 1.dst);
12812 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12813 // %}
12815 // peephole
12816 // %{
12817 // peepmatch (decI_rReg movI);
12818 // peepconstraint (0.dst == 1.dst);
12819 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12820 // %}
12822 // peephole
12823 // %{
12824 // peepmatch (addI_rReg_imm movI);
12825 // peepconstraint (0.dst == 1.dst);
12826 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12827 // %}
12829 // peephole
12830 // %{
12831 // peepmatch (incL_rReg movL);
12832 // peepconstraint (0.dst == 1.dst);
12833 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12834 // %}
12836 // peephole
12837 // %{
12838 // peepmatch (decL_rReg movL);
12839 // peepconstraint (0.dst == 1.dst);
12840 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12841 // %}
12843 // peephole
12844 // %{
12845 // peepmatch (addL_rReg_imm movL);
12846 // peepconstraint (0.dst == 1.dst);
12847 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12848 // %}
12850 // peephole
12851 // %{
12852 // peepmatch (addP_rReg_imm movP);
12853 // peepconstraint (0.dst == 1.dst);
12854 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12855 // %}
12857 // // Change load of spilled value to only a spill
12858 // instruct storeI(memory mem, rRegI src)
12859 // %{
12860 // match(Set mem (StoreI mem src));
12861 // %}
12862 //
12863 // instruct loadI(rRegI dst, memory mem)
12864 // %{
12865 // match(Set dst (LoadI mem));
12866 // %}
12867 //
12869 peephole
12870 %{
12871 peepmatch (loadI storeI);
12872 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12873 peepreplace (storeI(1.mem 1.mem 1.src));
12874 %}
12876 peephole
12877 %{
12878 peepmatch (loadL storeL);
12879 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12880 peepreplace (storeL(1.mem 1.mem 1.src));
12881 %}
12883 //----------SMARTSPILL RULES---------------------------------------------------
12884 // These must follow all instruction definitions as they use the names
12885 // defined in the instructions definitions.
