jdk8-mips64-public/hotspot: src/cpu/x86/vm/c1_FrameMap

6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
Reviewed-by: never

     1 /*

     2  * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20  * or visit www.oracle.com if you need additional information or have any

    21  * questions.

    22  *

    23  */

    25 //  On i486 the frame looks as follows:

    26 //

    27 //  +-----------------------------+---------+----------------------------------------+----------------+-----------

    28 //  | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .

    29 //  +-----------------------------+---------+----------------------------------------+----------------+-----------

    30 //

    31 //  The FPU registers are mapped with their offset from TOS; therefore the

    32 //  status of FPU stack must be updated during code emission.

    34  public:

    35   static const int pd_c_runtime_reserved_arg_size;

    37   enum {

    38     nof_xmm_regs = pd_nof_xmm_regs_frame_map,

    39     nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,

    40     first_available_sp_in_frame = 0,

    41 #ifndef _LP64

    42     frame_pad_in_bytes = 8,

    43     nof_reg_args = 2

    44 #else

    45     frame_pad_in_bytes = 16,

    46     nof_reg_args = 6

    47 #endif // _LP64

    48   };

    50  private:

    51   static LIR_Opr      _caller_save_xmm_regs [nof_caller_save_xmm_regs];

    53   static XMMRegister _xmm_regs[nof_xmm_regs];

    55  public:

    56   static LIR_Opr receiver_opr;

    58   static LIR_Opr rsi_opr;

    59   static LIR_Opr rdi_opr;

    60   static LIR_Opr rbx_opr;

    61   static LIR_Opr rax_opr;

    62   static LIR_Opr rdx_opr;

    63   static LIR_Opr rcx_opr;

    64   static LIR_Opr rsp_opr;

    65   static LIR_Opr rbp_opr;

    67   static LIR_Opr rsi_oop_opr;

    68   static LIR_Opr rdi_oop_opr;

    69   static LIR_Opr rbx_oop_opr;

    70   static LIR_Opr rax_oop_opr;

    71   static LIR_Opr rdx_oop_opr;

    72   static LIR_Opr rcx_oop_opr;

    73 #ifdef _LP64

    75   static LIR_Opr  r8_opr;

    76   static LIR_Opr  r9_opr;

    77   static LIR_Opr r10_opr;

    78   static LIR_Opr r11_opr;

    79   static LIR_Opr r12_opr;

    80   static LIR_Opr r13_opr;

    81   static LIR_Opr r14_opr;

    82   static LIR_Opr r15_opr;

    84   static LIR_Opr  r8_oop_opr;

    85   static LIR_Opr  r9_oop_opr;

    87   static LIR_Opr r11_oop_opr;

    88   static LIR_Opr r12_oop_opr;

    89   static LIR_Opr r13_oop_opr;

    90   static LIR_Opr r14_oop_opr;

    92 #endif // _LP64

    94   static LIR_Opr long0_opr;

    95   static LIR_Opr long1_opr;

    96   static LIR_Opr fpu0_float_opr;

    97   static LIR_Opr fpu0_double_opr;

    98   static LIR_Opr xmm0_float_opr;

    99   static LIR_Opr xmm0_double_opr;

   101 #ifdef _LP64

   102   static LIR_Opr as_long_opr(Register r) {

   103     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));

   104   }

   105   static LIR_Opr as_pointer_opr(Register r) {

   106     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));

   107   }

   108 #else

   109   static LIR_Opr as_long_opr(Register r, Register r2) {

   110     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));

   111   }

   112   static LIR_Opr as_pointer_opr(Register r) {

   113     return LIR_OprFact::single_cpu(cpu_reg2rnr(r));

   114   }

   115 #endif // _LP64

   117   // VMReg name for spilled physical FPU stack slot n

   118   static VMReg fpu_regname (int n);

   120   static XMMRegister nr2xmmreg(int rnr);

   122   static bool is_caller_save_register (LIR_Opr opr) { return true; }

   123   static bool is_caller_save_register (Register r) { return true; }

   125   static LIR_Opr caller_save_xmm_reg_at(int i) {

   126     assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");

   127     return _caller_save_xmm_regs[i];

   128   }

src/cpu/x86/vm/c1_FrameMap_x86.hpp@d257356e35f0