Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/mips/vm/nativeInst_mips.cpp@cecfc245b19a
src/cpu/mips/vm/nativeInst_mips.cpp
Tue, 12 Jun 2018 13:58:17 +0800
- author
- zhaixiang
- date
- Tue, 12 Jun 2018 13:58:17 +0800
- changeset 9144
- cecfc245b19a
- parent 9128
- 1d748903b598
- child 9146
- 4c971a763d55
- permissions
- -rw-r--r--
#7157 Fix all forgot saying delayed() when filling delay slot issues
Summary: enable check_delay and guarantee delay_state is at_delay_slot when filling delay slot
Reviewed-by: aoqi
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "nativeInst_mips.hpp"
30 #include "oops/oop.inline.hpp"
31 #include "runtime/handles.hpp"
32 #include "runtime/sharedRuntime.hpp"
33 #include "runtime/stubRoutines.hpp"
34 #include "utilities/ostream.hpp"
35 #ifdef COMPILER1
36 #include "c1/c1_Runtime1.hpp"
37 #endif
39 #include <sys/mman.h>
41 void NativeInstruction::wrote(int offset) {
42 ICache::invalidate_word(addr_at(offset));
43 }
45 void NativeInstruction::set_long_at(int offset, long i) {
46 address addr = addr_at(offset);
47 *(long*)addr = i;
48 #ifdef _LP64
49 ICache::invalidate_range(addr, 8);
50 #else
51 ICache::invalidate_word(addr);
52 #endif
53 }
55 static int illegal_instruction_bits = 0;
57 int NativeInstruction::illegal_instruction() {
58 if (illegal_instruction_bits == 0) {
59 ResourceMark rm;
60 char buf[40];
61 CodeBuffer cbuf((address)&buf[0], 20);
62 MacroAssembler* a = new MacroAssembler(&cbuf);
63 address ia = a->pc();
64 a->brk(11);
65 int bits = *(int*)ia;
66 illegal_instruction_bits = bits;
67 }
68 return illegal_instruction_bits;
69 }
71 bool NativeInstruction::is_int_branch() {
72 switch(Assembler::opcode(insn_word())) {
73 case Assembler::beq_op:
74 case Assembler::beql_op:
75 case Assembler::bgtz_op:
76 case Assembler::bgtzl_op:
77 case Assembler::blez_op:
78 case Assembler::blezl_op:
79 case Assembler::bne_op:
80 case Assembler::bnel_op:
81 return true;
82 case Assembler::regimm_op:
83 switch(Assembler::rt(insn_word())) {
84 case Assembler::bgez_op:
85 case Assembler::bgezal_op:
86 case Assembler::bgezall_op:
87 case Assembler::bgezl_op:
88 case Assembler::bltz_op:
89 case Assembler::bltzal_op:
90 case Assembler::bltzall_op:
91 case Assembler::bltzl_op:
92 return true;
93 }
94 }
96 return false;
97 }
99 bool NativeInstruction::is_float_branch() {
100 if (!is_op(Assembler::cop1_op) ||
101 !is_rs((Register)Assembler::bc1f_op)) return false;
103 switch(Assembler::rt(insn_word())) {
104 case Assembler::bcf_op:
105 case Assembler::bcfl_op:
106 case Assembler::bct_op:
107 case Assembler::bctl_op:
108 return true;
109 }
111 return false;
112 }
115 void NativeCall::verify() {
116 // make sure code pattern is actually a call instruction
117 #ifndef _LP64
118 if ( !is_op(Assembler::lui_op) ||
119 !is_op(int_at(4), Assembler::addiu_op) ||
120 !is_special_op(int_at(8), Assembler::jalr_op) ) {
121 fatal("not a call");
122 }
123 #else
125 // nop
126 // nop
127 // nop
128 // nop
129 // jal targe
130 // nop
131 if ( is_nop() &&
132 nativeInstruction_at(addr_at(4))->is_nop() &&
133 nativeInstruction_at(addr_at(8))->is_nop() &&
134 nativeInstruction_at(addr_at(12))->is_nop() &&
135 is_op(int_at(16), Assembler::jal_op) &&
136 nativeInstruction_at(addr_at(20))->is_nop() ) {
137 return;
138 }
140 // jal targe
141 // nop
142 if ( is_op(int_at(0), Assembler::jal_op) &&
143 nativeInstruction_at(addr_at(4))->is_nop() ) {
144 return;
145 }
147 // li64
148 if ( is_op(Assembler::lui_op) &&
149 is_op(int_at(4), Assembler::ori_op) &&
150 is_special_op(int_at(8), Assembler::dsll_op) &&
151 is_op(int_at(12), Assembler::ori_op) &&
152 is_special_op(int_at(16), Assembler::dsll_op) &&
153 is_op(int_at(20), Assembler::ori_op) &&
154 is_special_op(int_at(24), Assembler::jalr_op) ) {
155 return;
156 }
158 //lui dst, imm16
159 //ori dst, dst, imm16
160 //dsll dst, dst, 16
161 //ori dst, dst, imm16
162 if ( is_op(Assembler::lui_op) &&
163 is_op (int_at(4), Assembler::ori_op) &&
164 is_special_op(int_at(8), Assembler::dsll_op) &&
165 is_op (int_at(12), Assembler::ori_op) &&
166 is_special_op(int_at(16), Assembler::jalr_op) ) {
167 return;
168 }
170 //ori dst, R0, imm16
171 //dsll dst, dst, 16
172 //ori dst, dst, imm16
173 //nop
174 if ( is_op(Assembler::ori_op) &&
175 is_special_op(int_at(4), Assembler::dsll_op) &&
176 is_op (int_at(8), Assembler::ori_op) &&
177 nativeInstruction_at(addr_at(12))->is_nop() &&
178 is_special_op(int_at(16), Assembler::jalr_op) ) {
179 return;
180 }
182 //ori dst, R0, imm16
183 //dsll dst, dst, 16
184 //nop
185 //nop
186 if ( is_op(Assembler::ori_op) &&
187 is_special_op(int_at(4), Assembler::dsll_op) &&
188 nativeInstruction_at(addr_at(8))->is_nop() &&
189 nativeInstruction_at(addr_at(12))->is_nop() &&
190 is_special_op(int_at(16), Assembler::jalr_op) ) {
191 return;
192 }
194 //daddiu dst, R0, imm16
195 //nop
196 //nop
197 //nop
198 if ( is_op(Assembler::daddiu_op) &&
199 nativeInstruction_at(addr_at(4))->is_nop() &&
200 nativeInstruction_at(addr_at(8))->is_nop() &&
201 nativeInstruction_at(addr_at(12))->is_nop() &&
202 is_special_op(int_at(16), Assembler::jalr_op) ) {
203 return;
204 }
206 // FIXME: why add jr_op here?
207 //daddiu dst, R0, imm16
208 //nop
209 //nop
210 //nop
211 if ( is_op(Assembler::daddiu_op) &&
212 nativeInstruction_at(addr_at(4))->is_nop() &&
213 nativeInstruction_at(addr_at(8))->is_nop() &&
214 nativeInstruction_at(addr_at(12))->is_nop() &&
215 is_special_op(int_at(16), Assembler::jr_op) ) {
216 return;
217 }
219 //lui dst, imm16
220 //ori dst, dst, imm16
221 //nop
222 //nop
223 if ( is_op(Assembler::lui_op) &&
224 is_op (int_at(4), Assembler::ori_op) &&
225 nativeInstruction_at(addr_at(8))->is_nop() &&
226 nativeInstruction_at(addr_at(12))->is_nop() &&
227 is_special_op(int_at(16), Assembler::jalr_op) ) {
228 return;
229 }
231 //lui dst, imm16
232 //nop
233 //nop
234 //nop
235 if ( is_op(Assembler::lui_op) &&
236 nativeInstruction_at(addr_at(4))->is_nop() &&
237 nativeInstruction_at(addr_at(8))->is_nop() &&
238 nativeInstruction_at(addr_at(12))->is_nop() &&
239 is_special_op(int_at(16), Assembler::jalr_op) ) {
240 return;
241 }
243 //daddiu dst, R0, imm16
244 //nop
245 if ( is_op(Assembler::daddiu_op) &&
246 nativeInstruction_at(addr_at(4))->is_nop() &&
247 is_special_op(int_at(8), Assembler::jalr_op) ) {
248 return;
249 }
251 //lui dst, imm16
252 //ori dst, dst, imm16
253 if ( is_op(Assembler::lui_op) &&
254 is_op (int_at(4), Assembler::ori_op) &&
255 is_special_op(int_at(8), Assembler::jalr_op) ) {
256 return;
257 }
259 //lui dst, imm16
260 //nop
261 if ( is_op(Assembler::lui_op) &&
262 nativeInstruction_at(addr_at(4))->is_nop() &&
263 is_special_op(int_at(8), Assembler::jalr_op) ) {
264 return;
265 }
267 fatal("not a call");
268 #endif
269 }
271 address NativeCall::destination() const {
272 #ifndef _LP64
273 return (address)Assembler::merge(int_at(4)&0xffff, long_at(0)&0xffff);
274 #else
275 // jal target
276 // nop
277 if ( is_op(int_at(0), Assembler::jal_op) &&
278 nativeInstruction_at(addr_at(4))->is_nop()) {
279 int instr_index = int_at(0) & 0x3ffffff;
280 intptr_t target_high = ((intptr_t)addr_at(4)) & 0xfffffffff0000000;
281 intptr_t target = target_high | (instr_index << 2);
282 return (address)target;
283 }
285 // nop
286 // nop
287 // nop
288 // nop
289 // jal target
290 // nop
291 if ( nativeInstruction_at(addr_at(0))->is_nop() &&
292 nativeInstruction_at(addr_at(4))->is_nop() &&
293 nativeInstruction_at(addr_at(8))->is_nop() &&
294 nativeInstruction_at(addr_at(12))->is_nop() &&
295 is_op(int_at(16), Assembler::jal_op) &&
296 nativeInstruction_at(addr_at(20))->is_nop()) {
297 int instr_index = int_at(16) & 0x3ffffff;
298 intptr_t target_high = ((intptr_t)addr_at(20)) & 0xfffffffff0000000;
299 intptr_t target = target_high | (instr_index << 2);
300 return (address)target;
301 }
303 // li64
304 if ( is_op(Assembler::lui_op) &&
305 is_op(int_at(4), Assembler::ori_op) &&
306 is_special_op(int_at(8), Assembler::dsll_op) &&
307 is_op(int_at(12), Assembler::ori_op) &&
308 is_special_op(int_at(16), Assembler::dsll_op) &&
309 is_op(int_at(20), Assembler::ori_op) ) {
311 return (address)Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
312 (intptr_t)(int_at(12) & 0xffff),
313 (intptr_t)(int_at(4) & 0xffff),
314 (intptr_t)(int_at(0) & 0xffff));
315 }
317 //lui dst, imm16
318 //ori dst, dst, imm16
319 //dsll dst, dst, 16
320 //ori dst, dst, imm16
321 if ( is_op(Assembler::lui_op) &&
322 is_op (int_at(4), Assembler::ori_op) &&
323 is_special_op(int_at(8), Assembler::dsll_op) &&
324 is_op (int_at(12), Assembler::ori_op) ) {
326 return (address)Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
327 (intptr_t)(int_at(4) & 0xffff),
328 (intptr_t)(int_at(0) & 0xffff),
329 (intptr_t)0);
330 }
332 //ori dst, R0, imm16
333 //dsll dst, dst, 16
334 //ori dst, dst, imm16
335 //nop
336 if ( is_op(Assembler::ori_op) &&
337 is_special_op(int_at(4), Assembler::dsll_op) &&
338 is_op (int_at(8), Assembler::ori_op) &&
339 nativeInstruction_at(addr_at(12))->is_nop()) {
341 return (address)Assembler::merge( (intptr_t)(int_at(8) & 0xffff),
342 (intptr_t)(int_at(0) & 0xffff),
343 (intptr_t)0,
344 (intptr_t)0);
345 }
347 //ori dst, R0, imm16
348 //dsll dst, dst, 16
349 //nop
350 //nop
351 if ( is_op(Assembler::ori_op) &&
352 is_special_op(int_at(4), Assembler::dsll_op) &&
353 nativeInstruction_at(addr_at(8))->is_nop() &&
354 nativeInstruction_at(addr_at(12))->is_nop()) {
356 return (address)Assembler::merge( (intptr_t)(0),
357 (intptr_t)(int_at(0) & 0xffff),
358 (intptr_t)0,
359 (intptr_t)0);
360 }
362 //daddiu dst, R0, imm16
363 //nop
364 //nop <-- optional
365 //nop <-- optional
366 if ( is_op(Assembler::daddiu_op) &&
367 nativeInstruction_at(addr_at(4))->is_nop() ) {
369 int sign = int_at(0) & 0x8000;
370 if (sign == 0) {
371 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
372 (intptr_t)0,
373 (intptr_t)0,
374 (intptr_t)0);
375 } else {
376 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
377 (intptr_t)(0xffff),
378 (intptr_t)(0xffff),
379 (intptr_t)(0xffff));
380 }
381 }
383 //lui dst, imm16
384 //ori dst, dst, imm16
385 //nop <-- optional
386 //nop <-- optional
387 if ( is_op(Assembler::lui_op) &&
388 is_op (int_at(4), Assembler::ori_op) ) {
390 int sign = int_at(0) & 0x8000;
391 if (sign == 0) {
392 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
393 (intptr_t)(int_at(0) & 0xffff),
394 (intptr_t)0,
395 (intptr_t)0);
396 } else {
397 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
398 (intptr_t)(int_at(0) & 0xffff),
399 (intptr_t)(0xffff),
400 (intptr_t)(0xffff));
401 }
402 }
404 //lui dst, imm16
405 //nop
406 //nop <-- optional
407 //nop <-- optional
408 if ( is_op(Assembler::lui_op) &&
409 nativeInstruction_at(addr_at(4))->is_nop() ) {
411 int sign = int_at(0) & 0x8000;
412 if (sign == 0) {
413 return (address)Assembler::merge( (intptr_t)0,
414 (intptr_t)(int_at(0) & 0xffff),
415 (intptr_t)0,
416 (intptr_t)0);
417 } else {
418 return (address)Assembler::merge( (intptr_t)0,
419 (intptr_t)(int_at(0) & 0xffff),
420 (intptr_t)(0xffff),
421 (intptr_t)(0xffff));
422 }
423 }
425 fatal("not a call");
426 #endif
427 }
429 /* 2013/6/14 Jin: manual implementation of GSSQ
430 *
431 * 00000001200009c0 <atomic_store128>:
432 * 1200009c0: 0085202d daddu a0, a0, a1
433 * 1200009c4: e8860027 gssq a2, a3, 0(a0)
434 * 1200009c8: 03e00008 jr ra
435 * 1200009cc: 00000000 nop
436 */
437 typedef void (* atomic_store128_ptr)(long *addr, int offset, long low64, long hi64);
439 static int *buf;
441 static atomic_store128_ptr get_atomic_store128_func() {
442 assert(UseLoongsonISA, "UseLoongsonISA must be true");
443 static atomic_store128_ptr p = NULL;
444 if (p != NULL)
445 return p;
447 buf = (int *)mmap(NULL, 1024, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS,
448 -1, 0);
449 buf[0] = 0x0085202d;
450 buf[1] = (0x3a << 26) | (4 << 21) | (6 << 16) | 0x27; /* gssq $a2, $a3, 0($a0) */
451 buf[2] = 0x03e00008;
452 buf[3] = 0;
454 asm("sync");
455 p = (atomic_store128_ptr)buf;
456 return p;
457 }
459 void NativeCall::patch_on_jal_only(address dst) {
460 #ifdef _LP64
461 long dest = ((long)dst - (((long)addr_at(4)) & 0xfffffffff0000000))>>2;
462 #else
463 long dest = ((long)dst - (((long)addr_at(4)) & 0xf0000000))>>2;
464 #endif
465 if ((dest >= 0) && (dest < (1<<26))) {
466 jint jal_inst = (Assembler::jal_op << 26) | dest;
467 set_int_at(0, jal_inst);
468 ICache::invalidate_range(addr_at(0), 4);
469 } else {
470 ShouldNotReachHere();
471 }
472 }
474 void NativeCall::patch_on_jal_gs(address dst) {
475 #ifdef _LP64
476 long dest = ((long)dst - (((long)addr_at(20)) & 0xfffffffff0000000))>>2;
477 #else
478 long dest = ((long)dst - (((long)addr_at(20)) & 0xf0000000))>>2;
479 #endif
480 if ((dest >= 0) && (dest < (1<<26))) {
481 jint jal_inst = (Assembler::jal_op << 26) | dest;
482 set_int_at(16, jal_inst);
483 ICache::invalidate_range(addr_at(16), 4);
484 } else {
485 ShouldNotReachHere();
486 }
487 }
489 void NativeCall::patch_on_jal(address dst) {
490 patch_on_jal_gs(dst);
491 }
493 void NativeCall::patch_on_jalr_gs(address dst) {
494 patch_set48_gs(dst);
495 }
497 void NativeCall::patch_on_jalr(address dst) {
498 patch_set48(dst);
499 }
501 void NativeCall::patch_set48_gs(address dest) {
502 jlong value = (jlong) dest;
503 int rt_reg = (int_at(0) & (0x1f << 16));
505 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
507 int rs_reg = rt_reg << 5;
508 int rd_reg = rt_reg >> 5;
510 int hi = (int)(value >> 32);
511 int lo = (int)(value & ~0);
512 int count = 0;
513 int insts[4] = {0, 0, 0, 0};
515 if (value == lo) { // 32-bit integer
516 if (Assembler::is_simm16(value)) {
517 insts[count] = (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value);
518 count += 1;
519 } else {
520 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16);
521 count += 1;
522 if (Assembler::split_low(value)) {
523 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
524 count += 1;
525 }
526 }
527 } else if (hi == 0) { // hardware zero-extends to upper 32
528 insts[count] = (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16);
529 count += 1;
530 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
531 count += 1;
532 if (Assembler::split_low(value)) {
533 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
534 count += 1;
535 }
536 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
537 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32);
538 count += 1;
539 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16);
540 count += 1;
541 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
542 count += 1;
543 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
544 count += 1;
545 } else {
546 tty->print_cr("dest = 0x%x", value);
547 guarantee(false, "Not supported yet !");
548 }
550 for (count; count < 4; count++) {
551 insts[count] = 0;
552 }
554 atomic_store128_ptr func = get_atomic_store128_func();
555 (*func)((long *)addr_at(0), 0, *(long *)&insts[0], *(long *)&insts[2]);
557 ICache::invalidate_range(addr_at(0), 16);
558 }
560 void NativeCall::patch_set32_gs(address dest) {
561 jlong value = (jlong) dest;
562 int rt_reg = (int_at(0) & (0x1f << 16));
564 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
566 int rs_reg = rt_reg << 5;
567 int rd_reg = rt_reg >> 5;
569 int hi = (int)(value >> 32);
570 int lo = (int)(value & ~0);
572 int count = 0;
574 int insts[2] = {0, 0};
576 if (value == lo) { // 32-bit integer
577 if (Assembler::is_simm16(value)) {
578 //daddiu(d, R0, value);
579 //set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
580 insts[count] = (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value);
581 count += 1;
582 } else {
583 //lui(d, split_low(value >> 16));
584 //set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
585 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16);
586 count += 1;
587 if (Assembler::split_low(value)) {
588 //ori(d, d, split_low(value));
589 //set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
590 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
591 count += 1;
592 }
593 }
594 } else {
595 tty->print_cr("dest = 0x%x", value);
596 guarantee(false, "Not supported yet !");
597 }
599 for (count; count < 2; count++) {
600 //nop();
601 //set_int_at(count << 2, 0);
602 insts[count] = 0;
603 }
605 long inst = insts[1];
606 inst = inst << 32;
607 inst = inst + insts[0];
609 set_long_at(0, inst);
610 }
612 void NativeCall::patch_set48(address dest) {
613 jlong value = (jlong) dest;
614 int rt_reg = (int_at(0) & (0x1f << 16));
616 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
618 int rs_reg = rt_reg << 5;
619 int rd_reg = rt_reg >> 5;
621 int hi = (int)(value >> 32);
622 int lo = (int)(value & ~0);
624 int count = 0;
626 if (value == lo) { // 32-bit integer
627 if (Assembler::is_simm16(value)) {
628 //daddiu(d, R0, value);
629 set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
630 count += 1;
631 } else {
632 //lui(d, split_low(value >> 16));
633 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
634 count += 1;
635 if (Assembler::split_low(value)) {
636 //ori(d, d, split_low(value));
637 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
638 count += 1;
639 }
640 }
641 } else if (hi == 0) { // hardware zero-extends to upper 32
642 //ori(d, R0, julong(value) >> 16);
643 set_int_at(count << 2, (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16));
644 count += 1;
645 //dsll(d, d, 16);
646 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
647 count += 1;
648 if (Assembler::split_low(value)) {
649 //ori(d, d, split_low(value));
650 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
651 count += 1;
652 }
653 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
654 //lui(d, value >> 32);
655 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32));
656 count += 1;
657 //ori(d, d, split_low(value >> 16));
658 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16));
659 count += 1;
660 //dsll(d, d, 16);
661 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
662 count += 1;
663 //ori(d, d, split_low(value));
664 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
665 count += 1;
666 } else {
667 tty->print_cr("dest = 0x%x", value);
668 guarantee(false, "Not supported yet !");
669 }
671 for (count; count < 4; count++) {
672 //nop();
673 set_int_at(count << 2, 0);
674 }
676 ICache::invalidate_range(addr_at(0), 16);
677 }
679 void NativeCall::patch_set32(address dest) {
680 patch_set32_gs(dest);
681 }
683 void NativeCall::set_destination(address dest) {
684 #ifndef _LP64
685 OrderAccess::fence();
686 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high((intptr_t)dest) & 0xffff));
687 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
688 ICache::invalidate_range(addr_at(0), 8);
689 #else
690 OrderAccess::fence();
692 // li64
693 if (is_special_op(int_at(16), Assembler::dsll_op)) {
694 int first_word = int_at(0);
695 set_int_at(0, 0x1000ffff); /* .1: b .1 */
696 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 32) & 0xffff));
697 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 16) & 0xffff));
698 set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
699 set_int_at(0, (first_word & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 48) & 0xffff));
700 ICache::invalidate_range(addr_at(0), 24);
701 } else if (is_op(int_at(16), Assembler::jal_op)) {
702 if (UseLoongsonISA) {
703 patch_on_jal_gs(dest);
704 } else {
705 patch_on_jal(dest);
706 }
707 } else if (is_op(int_at(0), Assembler::jal_op)) {
708 patch_on_jal_only(dest);
709 } else if (is_special_op(int_at(16), Assembler::jalr_op)) {
710 if (UseLoongsonISA) {
711 patch_on_jalr(dest);
712 } else {
713 patch_on_jalr(dest);
714 }
715 } else if (is_special_op(int_at(8), Assembler::jalr_op)) {
716 guarantee(!os::is_MP() || (((long)addr_at(0) % 8) == 0), "destination must be aligned by 8");
717 if (UseLoongsonISA) {
718 patch_set32_gs(dest);
719 } else {
720 patch_set32(dest);
721 }
722 ICache::invalidate_range(addr_at(0), 8);
723 } else {
724 fatal("not a call");
725 }
726 #endif
727 }
729 void NativeCall::print() {
730 tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
731 instruction_address(), destination());
732 }
734 // Inserts a native call instruction at a given pc
735 void NativeCall::insert(address code_pos, address entry) {
736 NativeCall *call = nativeCall_at(code_pos);
737 CodeBuffer cb(call->addr_at(0), instruction_size);
738 MacroAssembler masm(&cb);
739 #define __ masm.
740 #ifndef _LP64
741 __ lui(T9, Assembler::split_high((int)entry));
742 __ addiu(T9, T9, Assembler::split_low((int)entry));
743 #else
744 __ li48(T9, (long)entry);
745 #endif
746 __ jalr ();
747 __ delayed()->nop();
748 #undef __
750 ICache::invalidate_range(call->addr_at(0), instruction_size);
751 }
753 // MT-safe patching of a call instruction.
754 // First patches first word of instruction to two jmp's that jmps to them
755 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
756 // the jmp's with the first 4 byte of the new instruction.
757 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
758 Unimplemented();
759 }
761 //-------------------------------------------------------------------
763 void NativeMovConstReg::verify() {
764 #ifndef _LP64
765 if ( !is_op(Assembler::lui_op) ||
766 !is_op(int_at(4), Assembler::addiu_op) )
767 fatal("not a mov reg, imm32")
768 #else
769 // li64
770 if ( is_op(Assembler::lui_op) &&
771 is_op(int_at(4), Assembler::ori_op) &&
772 is_special_op(int_at(8), Assembler::dsll_op) &&
773 is_op(int_at(12), Assembler::ori_op) &&
774 is_special_op(int_at(16), Assembler::dsll_op) &&
775 is_op(int_at(20), Assembler::ori_op) ) {
776 return;
777 }
779 //lui dst, imm16
780 //ori dst, dst, imm16
781 //dsll dst, dst, 16
782 //ori dst, dst, imm16
783 if ( is_op(Assembler::lui_op) &&
784 is_op (int_at(4), Assembler::ori_op) &&
785 is_special_op(int_at(8), Assembler::dsll_op) &&
786 is_op (int_at(12), Assembler::ori_op) ) {
787 return;
788 }
790 //ori dst, R0, imm16
791 //dsll dst, dst, 16
792 //ori dst, dst, imm16
793 //nop
794 if ( is_op(Assembler::ori_op) &&
795 is_special_op(int_at(4), Assembler::dsll_op) &&
796 is_op (int_at(8), Assembler::ori_op) &&
797 nativeInstruction_at(addr_at(12))->is_nop()) {
798 return;
799 }
801 //ori dst, R0, imm16
802 //dsll dst, dst, 16
803 //nop
804 //nop
805 if ( is_op(Assembler::ori_op) &&
806 is_special_op(int_at(4), Assembler::dsll_op) &&
807 nativeInstruction_at(addr_at(8))->is_nop() &&
808 nativeInstruction_at(addr_at(12))->is_nop()) {
809 return;
810 }
812 //daddiu dst, R0, imm16
813 //nop
814 //nop
815 //nop
816 if ( is_op(Assembler::daddiu_op) &&
817 nativeInstruction_at(addr_at(4))->is_nop() &&
818 nativeInstruction_at(addr_at(8))->is_nop() &&
819 nativeInstruction_at(addr_at(12))->is_nop() ) {
820 return;
821 }
823 //lui dst, imm16
824 //ori dst, dst, imm16
825 //nop
826 //nop
827 if ( is_op(Assembler::lui_op) &&
828 is_op (int_at(4), Assembler::ori_op) &&
829 nativeInstruction_at(addr_at(8))->is_nop() &&
830 nativeInstruction_at(addr_at(12))->is_nop() ) {
831 return;
832 }
834 //lui dst, imm16
835 //nop
836 //nop
837 //nop
838 if ( is_op(Assembler::lui_op) &&
839 nativeInstruction_at(addr_at(4))->is_nop() &&
840 nativeInstruction_at(addr_at(8))->is_nop() &&
841 nativeInstruction_at(addr_at(12))->is_nop() ) {
842 return;
843 }
845 fatal("not a mov reg, imm64/imm48");
846 #endif
847 }
849 void NativeMovConstReg::print() {
850 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
851 instruction_address(), data());
852 }
854 intptr_t NativeMovConstReg::data() const {
855 #ifndef _LP64
856 return Assembler::merge(int_at(4)&0xffff, long_at(0)&0xffff);
857 #else
858 // li64
859 if ( is_op(Assembler::lui_op) &&
860 is_op(int_at(4), Assembler::ori_op) &&
861 is_special_op(int_at(8), Assembler::dsll_op) &&
862 is_op(int_at(12), Assembler::ori_op) &&
863 is_special_op(int_at(16), Assembler::dsll_op) &&
864 is_op(int_at(20), Assembler::ori_op) ) {
866 return Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
867 (intptr_t)(int_at(12) & 0xffff),
868 (intptr_t)(int_at(4) & 0xffff),
869 (intptr_t)(int_at(0) & 0xffff));
870 }
872 //lui dst, imm16
873 //ori dst, dst, imm16
874 //dsll dst, dst, 16
875 //ori dst, dst, imm16
876 if ( is_op(Assembler::lui_op) &&
877 is_op (int_at(4), Assembler::ori_op) &&
878 is_special_op(int_at(8), Assembler::dsll_op) &&
879 is_op (int_at(12), Assembler::ori_op) ) {
881 return Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
882 (intptr_t)(int_at(4) & 0xffff),
883 (intptr_t)(int_at(0) & 0xffff),
884 (intptr_t)0);
885 }
887 //ori dst, R0, imm16
888 //dsll dst, dst, 16
889 //ori dst, dst, imm16
890 //nop
891 if ( is_op(Assembler::ori_op) &&
892 is_special_op(int_at(4), Assembler::dsll_op) &&
893 is_op (int_at(8), Assembler::ori_op) &&
894 nativeInstruction_at(addr_at(12))->is_nop()) {
896 return Assembler::merge( (intptr_t)(int_at(8) & 0xffff),
897 (intptr_t)(int_at(0) & 0xffff),
898 (intptr_t)0,
899 (intptr_t)0);
900 }
902 //ori dst, R0, imm16
903 //dsll dst, dst, 16
904 //nop
905 //nop
906 if ( is_op(Assembler::ori_op) &&
907 is_special_op(int_at(4), Assembler::dsll_op) &&
908 nativeInstruction_at(addr_at(8))->is_nop() &&
909 nativeInstruction_at(addr_at(12))->is_nop()) {
911 return Assembler::merge( (intptr_t)(0),
912 (intptr_t)(int_at(0) & 0xffff),
913 (intptr_t)0,
914 (intptr_t)0);
915 }
917 //daddiu dst, R0, imm16
918 //nop
919 //nop
920 //nop
921 if ( is_op(Assembler::daddiu_op) &&
922 nativeInstruction_at(addr_at(4))->is_nop() &&
923 nativeInstruction_at(addr_at(8))->is_nop() &&
924 nativeInstruction_at(addr_at(12))->is_nop() ) {
926 int sign = int_at(0) & 0x8000;
927 if (sign == 0) {
928 return Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
929 (intptr_t)0,
930 (intptr_t)0,
931 (intptr_t)0);
932 } else {
933 return Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
934 (intptr_t)(0xffff),
935 (intptr_t)(0xffff),
936 (intptr_t)(0xffff));
937 }
938 }
940 //lui dst, imm16
941 //ori dst, dst, imm16
942 //nop
943 //nop
944 if ( is_op(Assembler::lui_op) &&
945 is_op (int_at(4), Assembler::ori_op) &&
946 nativeInstruction_at(addr_at(8))->is_nop() &&
947 nativeInstruction_at(addr_at(12))->is_nop() ) {
949 int sign = int_at(0) & 0x8000;
950 if (sign == 0) {
951 return Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
952 (intptr_t)(int_at(0) & 0xffff),
953 (intptr_t)0,
954 (intptr_t)0);
955 } else {
956 return Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
957 (intptr_t)(int_at(0) & 0xffff),
958 (intptr_t)(0xffff),
959 (intptr_t)(0xffff));
960 }
961 }
963 //lui dst, imm16
964 //nop
965 //nop
966 //nop
967 if ( is_op(Assembler::lui_op) &&
968 nativeInstruction_at(addr_at(4))->is_nop() &&
969 nativeInstruction_at(addr_at(8))->is_nop() &&
970 nativeInstruction_at(addr_at(12))->is_nop() ) {
972 int sign = int_at(0) & 0x8000;
973 if (sign == 0) {
974 return Assembler::merge( (intptr_t)0,
975 (intptr_t)(int_at(0) & 0xffff),
976 (intptr_t)0,
977 (intptr_t)0);
978 } else {
979 return Assembler::merge( (intptr_t)0,
980 (intptr_t)(int_at(0) & 0xffff),
981 (intptr_t)(0xffff),
982 (intptr_t)(0xffff));
983 }
984 }
986 fatal("not a mov reg, imm64/imm48");
988 #endif
989 }
991 void NativeMovConstReg::patch_set48(intptr_t x) {
992 jlong value = (jlong) x;
993 int rt_reg = (int_at(0) & (0x1f << 16));
994 int rs_reg = rt_reg << 5;
995 int rd_reg = rt_reg >> 5;
997 int hi = (int)(value >> 32);
998 int lo = (int)(value & ~0);
1000 int count = 0;
1002 if (value == lo) { // 32-bit integer
1003 if (Assembler::is_simm16(value)) {
1004 //daddiu(d, R0, value);
1005 set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
1006 count += 1;
1007 } else {
1008 //lui(d, split_low(value >> 16));
1009 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
1010 count += 1;
1011 if (Assembler::split_low(value)) {
1012 //ori(d, d, split_low(value));
1013 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1014 count += 1;
1015 }
1016 }
1017 } else if (hi == 0) { // hardware zero-extends to upper 32
1018 set_int_at(count << 2, (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16));
1019 count += 1;
1020 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1021 count += 1;
1022 if (Assembler::split_low(value)) {
1023 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1024 count += 1;
1025 }
1026 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
1027 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32));
1028 count += 1;
1029 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16));
1030 count += 1;
1031 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1032 count += 1;
1033 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1034 count += 1;
1035 } else {
1036 tty->print_cr("value = 0x%x", value);
1037 guarantee(false, "Not supported yet !");
1038 }
1040 for (count; count < 4; count++) {
1041 set_int_at(count << 2, 0);
1042 }
1043 }
1045 void NativeMovConstReg::set_data(intptr_t x) {
1046 #ifndef _LP64
1047 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high(x) & 0xffff));
1048 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low(x) & 0xffff));
1049 ICache::invalidate_range(addr_at(0), 8);
1050 #else
1051 /* li64 or li48 */
1052 if ((!nativeInstruction_at(addr_at(12))->is_nop()) && is_special_op(int_at(16), Assembler::dsll_op) && is_op(long_at(20), Assembler::ori_op)) {
1053 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 48) & 0xffff));
1054 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 32) & 0xffff));
1055 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 16) & 0xffff));
1056 set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)x) & 0xffff));
1057 } else {
1058 patch_set48(x);
1059 }
1061 ICache::invalidate_range(addr_at(0), 24);
1062 #endif
1063 }
1065 //-------------------------------------------------------------------
1067 int NativeMovRegMem::offset() const{
1068 if (is_immediate())
1069 return (short)(int_at(instruction_offset)&0xffff);
1070 else
1071 return Assembler::merge(int_at(hiword_offset)&0xffff, long_at(instruction_offset)&0xffff);
1072 }
1074 void NativeMovRegMem::set_offset(int x) {
1075 if (is_immediate()) {
1076 assert(Assembler::is_simm16(x), "just check");
1077 set_int_at(0, (int_at(0)&0xffff0000) | (x&0xffff) );
1078 if (is_64ldst()) {
1079 assert(Assembler::is_simm16(x+4), "just check");
1080 set_int_at(4, (int_at(4)&0xffff0000) | ((x+4)&0xffff) );
1081 }
1082 } else {
1083 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high(x) & 0xffff));
1084 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low(x) & 0xffff));
1085 }
1086 ICache::invalidate_range(addr_at(0), 8);
1087 }
1089 void NativeMovRegMem::verify() {
1090 int offset = 0;
1092 if ( Assembler::opcode(int_at(0)) == Assembler::lui_op ) {
1093 #ifndef _LP64
1094 if ( (Assembler::opcode(int_at(4)) != Assembler::addiu_op) ||
1095 (Assembler::opcode(int_at(8)) != Assembler::special_op) ||
1096 (Assembler::special(int_at(8)) != Assembler::add_op))
1097 #else
1098 /* Jin: fit MIPS64 */
1099 if ( (Assembler::opcode(int_at(4)) != Assembler::addiu_op &&
1100 Assembler::opcode(int_at(4)) != Assembler::daddiu_op ) ||
1101 (Assembler::opcode(int_at(8)) != Assembler::special_op) ||
1102 (Assembler::special(int_at(8)) != Assembler::add_op
1103 && Assembler::special(int_at(8)) != Assembler::dadd_op))
1104 #endif
1105 fatal ("not a mov [reg+offs], reg instruction");
1106 offset += 12;
1107 }
1109 switch(Assembler::opcode(int_at(offset))) {
1110 case Assembler::lb_op:
1111 case Assembler::lbu_op:
1112 case Assembler::lh_op:
1113 case Assembler::lhu_op:
1114 case Assembler::lw_op:
1115 case Assembler::lwu_op:
1116 LP64_ONLY(case Assembler::ld_op:)
1117 case Assembler::lwc1_op:
1118 LP64_ONLY(case Assembler::ldc1_op:)
1119 case Assembler::sb_op:
1120 case Assembler::sh_op:
1121 case Assembler::sw_op:
1122 LP64_ONLY(case Assembler::sd_op:)
1123 case Assembler::swc1_op:
1124 LP64_ONLY(case Assembler::sdc1_op:)
1125 break;
1126 default:
1127 fatal ("not a mov [reg+offs], reg instruction");
1128 }
1129 }
1132 void NativeMovRegMem::print() {
1133 tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
1134 }
1136 void NativeIllegalInstruction::insert(address code_pos) {
1137 CodeBuffer cb(code_pos, instruction_size);
1138 MacroAssembler masm(&cb);
1139 #define __ masm.
1140 __ brk(11);
1141 #undef __
1143 ICache::invalidate_range(code_pos, instruction_size);
1144 }
1146 void NativeGeneralJump::verify() {
1147 assert(((NativeInstruction *)this)->is_jump() ||
1148 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
1149 }
1151 void NativeGeneralJump::patch_set48_gs(address dest) {
1152 jlong value = (jlong) dest;
1153 int rt_reg = (int_at(0) & (0x1f << 16));
1155 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
1157 int rs_reg = rt_reg << 5;
1158 int rd_reg = rt_reg >> 5;
1160 int hi = (int)(value >> 32);
1161 int lo = (int)(value & ~0);
1163 int count = 0;
1165 int insts[4] = {0, 0, 0, 0};
1167 if (value == lo) { // 32-bit integer
1168 if (Assembler::is_simm16(value)) {
1169 insts[count] = (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value);
1170 count += 1;
1171 } else {
1172 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16);
1173 count += 1;
1174 if (Assembler::split_low(value)) {
1175 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
1176 count += 1;
1177 }
1178 }
1179 } else if (hi == 0) { // hardware zero-extends to upper 32
1180 insts[count] = (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16);
1181 count += 1;
1182 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
1183 count += 1;
1184 if (Assembler::split_low(value)) {
1185 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
1186 count += 1;
1187 }
1188 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
1189 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32);
1190 count += 1;
1191 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16);
1192 count += 1;
1193 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
1194 count += 1;
1195 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
1196 count += 1;
1197 } else {
1198 tty->print_cr("dest = 0x%x", value);
1199 guarantee(false, "Not supported yet !");
1200 }
1202 for (count; count < 4; count++) {
1203 insts[count] = 0;
1204 }
1206 atomic_store128_ptr func = get_atomic_store128_func();
1207 (*func)((long *)addr_at(0), 0, *(long *)&insts[0], *(long *)&insts[2]);
1209 ICache::invalidate_range(addr_at(0), 16);
1210 }
1212 void NativeGeneralJump::patch_set48(address dest) {
1213 jlong value = (jlong) dest;
1214 int rt_reg = (int_at(0) & (0x1f << 16));
1215 int rs_reg = rt_reg << 5;
1216 int rd_reg = rt_reg >> 5;
1218 int hi = (int)(value >> 32);
1219 int lo = (int)(value & ~0);
1221 int count = 0;
1223 if (value == lo) { // 32-bit integer
1224 if (Assembler::is_simm16(value)) {
1225 set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
1226 count += 1;
1227 } else {
1228 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
1229 count += 1;
1230 if (Assembler::split_low(value)) {
1231 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1232 count += 1;
1233 }
1234 }
1235 } else if (hi == 0) { // hardware zero-extends to upper 32
1236 set_int_at(count << 2, (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16));
1237 count += 1;
1238 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1239 count += 1;
1240 if (Assembler::split_low(value)) {
1241 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1242 count += 1;
1243 }
1244 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
1245 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32));
1246 count += 1;
1247 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16));
1248 count += 1;
1249 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1250 count += 1;
1251 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1252 count += 1;
1253 } else {
1254 tty->print_cr("dest = 0x%x", value);
1255 guarantee(false, "Not supported yet !");
1256 }
1258 for (count; count < 4; count++) {
1259 set_int_at(count << 2, 0);
1260 }
1262 ICache::invalidate_range(addr_at(0), 16);
1263 }
1265 void NativeGeneralJump::patch_on_j_only(address dst) {
1266 #ifdef _LP64
1267 long dest = ((long)dst - (((long)addr_at(4)) & 0xfffffffff0000000))>>2;
1268 #else
1269 long dest = ((long)dst - (((long)addr_at(4)) & 0xf0000000))>>2;
1270 #endif
1271 if ((dest >= 0) && (dest < (1<<26))) {
1272 jint j_inst = (Assembler::j_op << 26) | dest;
1273 set_int_at(0, j_inst);
1274 ICache::invalidate_range(addr_at(0), 4);
1275 } else {
1276 ShouldNotReachHere();
1277 }
1278 }
1281 void NativeGeneralJump::patch_on_j_gs(address dst) {
1282 #ifdef _LP64
1283 long dest = ((long)dst - (((long)addr_at(20)) & 0xfffffffff0000000))>>2;
1284 #else
1285 long dest = ((long)dst - (((long)addr_at(20)) & 0xf0000000))>>2;
1286 #endif
1287 if ((dest >= 0) && (dest < (1<<26))) {
1288 jint j_inst = (Assembler::j_op << 26) | dest;
1289 set_int_at(16, j_inst);
1290 ICache::invalidate_range(addr_at(16), 4);
1291 } else {
1292 ShouldNotReachHere();
1293 }
1294 }
1296 void NativeGeneralJump::patch_on_j(address dst) {
1297 patch_on_j_gs(dst);
1298 }
1300 void NativeGeneralJump::patch_on_jr_gs(address dst) {
1301 patch_set48_gs(dst);
1302 ICache::invalidate_range(addr_at(0), 16);
1303 }
1305 void NativeGeneralJump::patch_on_jr(address dst) {
1306 patch_set48(dst);
1307 ICache::invalidate_range(addr_at(0), 16);
1308 }
1311 void NativeGeneralJump::set_jump_destination(address dest) {
1312 OrderAccess::fence();
1314 if (is_short()) {
1315 assert(Assembler::is_simm16(dest-addr_at(4)), "change this code");
1316 set_int_at(0, (int_at(0) & 0xffff0000) | (dest - addr_at(4)) & 0xffff );
1317 ICache::invalidate_range(addr_at(0), 4);
1318 #ifdef _LP64
1319 } else if (is_b_far()) {
1320 int offset = dest - addr_at(12);
1321 set_int_at(12, (int_at(12) & 0xffff0000) | (offset >> 16));
1322 set_int_at(16, (int_at(16) & 0xffff0000) | (offset & 0xffff));
1323 #endif
1324 } else {
1325 #ifndef _LP64
1326 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high((intptr_t)dest) & 0xffff));
1327 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
1328 ICache::invalidate_range(addr_at(0), 8);
1329 #else
1330 if (is_op(int_at(16), Assembler::j_op)) {
1331 if (UseLoongsonISA) {
1332 patch_on_j_gs(dest);
1333 } else {
1334 patch_on_j(dest);
1335 }
1336 } else if (is_op(int_at(0), Assembler::j_op)) {
1337 patch_on_j_only(dest);
1338 } else if (is_special_op(int_at(16), Assembler::jr_op)) {
1339 if (UseLoongsonISA) {
1340 //guarantee(!os::is_MP() || (((long)addr_at(0) % 16) == 0), "destination must be aligned for GSSD");
1341 //patch_on_jr_gs(dest);
1342 patch_on_jr(dest);
1343 } else {
1344 patch_on_jr(dest);
1345 }
1346 } else {
1347 fatal("not a jump");
1348 }
1349 #endif
1350 }
1351 }
1353 // we now use b to do this. be careful when using this method
1354 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
1355 CodeBuffer cb(code_pos, instruction_size);
1356 MacroAssembler masm(&cb);
1357 #define __ masm.
1358 #ifdef _LP64
1359 if (Assembler::is_simm16((entry - code_pos - 4) / 4)) {
1360 __ b(entry);
1361 __ delayed()->nop();
1362 } else {
1363 /* a simplified b_far */
1364 int offset = entry - code_pos;
1366 // FIXME: need to preserve RA?
1367 __ emit_long(0x4110001); //__ emit_long(Assembler::insn_ORRI(Assembler::regimm_op, 0, Assembler::bgezal_op, 1));
1368 __ lui(T9, (offset - 8) >> 16); // delay slot
1369 __ ori(T9, T9, (offset - 8) & 0xffff);
1370 __ daddu(T9, T9, RA);
1371 __ jr(T9);
1372 __ delayed()->nop();
1373 }
1374 #else
1375 __ b(entry);
1376 __ delayed()->nop();
1377 #endif
1378 #undef __
1380 ICache::invalidate_range(code_pos, instruction_size);
1381 }
1383 #ifdef _LP64
1384 bool NativeGeneralJump::is_b_far() {
1385 /*
1386 0x000000556809f198: dadd at, ra, zero
1387 0x000000556809f19c: [4110001]bgezal zero, 0x000000556809f1a4
1389 0x000000556809f1a0: nop
1390 0x000000556809f1a4: lui t9, 0xfffffffd
1391 0x000000556809f1a8: ori t9, t9, 0x14dc
1392 0x000000556809f1ac: daddu t9, t9, ra
1393 0x000000556809f1b0: dadd ra, at, zero
1394 0x000000556809f1b4: jr t9
1395 0x000000556809f1b8: nop
1396 ;; ImplicitNullCheckStub slow case
1397 0x000000556809f1bc: lui t9, 0x55
1398 */
1399 return is_op(int_at(12), Assembler::lui_op);
1400 }
1401 #endif
1403 address NativeGeneralJump::jump_destination() {
1404 if ( is_short() ) {
1405 return addr_at(4) + Assembler::imm_off(int_at(instruction_offset)) * 4;
1406 }
1407 #ifndef _LP64
1408 return (address)Assembler::merge(int_at(4)&0xffff, long_at(instruction_offset)&0xffff);
1409 #else
1410 /* 2012/4/19 Jin: Assembler::merge() is not correct in MIPS_64!
1412 Example:
1413 hi16 = 0xfffd,
1414 lo16 = f7a4,
1416 offset=0xfffdf7a4 (Right)
1417 Assembler::merge = 0xfffcf7a4 (Wrong)
1418 */
1419 if ( is_b_far() ) {
1420 int hi16 = int_at(12)&0xffff;
1421 int low16 = int_at(16)&0xffff;
1422 address target = addr_at(12) + (hi16 << 16) + low16;
1423 return target;
1424 }
1426 // nop
1427 // nop
1428 // nop
1429 // nop
1430 // j target
1431 // nop
1432 if ( nativeInstruction_at(addr_at(0))->is_nop() &&
1433 nativeInstruction_at(addr_at(4))->is_nop() &&
1434 nativeInstruction_at(addr_at(8))->is_nop() &&
1435 nativeInstruction_at(addr_at(12))->is_nop() &&
1436 is_op(int_at(16), Assembler::j_op) &&
1437 nativeInstruction_at(addr_at(20))->is_nop()) {
1438 int instr_index = int_at(16) & 0x3ffffff;
1439 intptr_t target_high = ((intptr_t)addr_at(20)) & 0xfffffffff0000000;
1440 intptr_t target = target_high | (instr_index << 2);
1441 return (address)target;
1442 }
1444 // j target
1445 // nop
1446 if ( is_op(int_at(0), Assembler::j_op) &&
1447 nativeInstruction_at(addr_at(4))->is_nop()) {
1448 int instr_index = int_at(0) & 0x3ffffff;
1449 intptr_t target_high = ((intptr_t)addr_at(4)) & 0xfffffffff0000000;
1450 intptr_t target = target_high | (instr_index << 2);
1451 return (address)target;
1452 }
1454 // li64
1455 if ( is_op(Assembler::lui_op) &&
1456 is_op(int_at(4), Assembler::ori_op) &&
1457 is_special_op(int_at(8), Assembler::dsll_op) &&
1458 is_op(int_at(12), Assembler::ori_op) &&
1459 is_special_op(int_at(16), Assembler::dsll_op) &&
1460 is_op(int_at(20), Assembler::ori_op) ) {
1462 return (address)Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
1463 (intptr_t)(int_at(12) & 0xffff),
1464 (intptr_t)(int_at(4) & 0xffff),
1465 (intptr_t)(int_at(0) & 0xffff));
1466 }
1468 //lui dst, imm16
1469 //ori dst, dst, imm16
1470 //dsll dst, dst, 16
1471 //ori dst, dst, imm16
1472 if ( is_op(Assembler::lui_op) &&
1473 is_op (int_at(4), Assembler::ori_op) &&
1474 is_special_op(int_at(8), Assembler::dsll_op) &&
1475 is_op (int_at(12), Assembler::ori_op) ) {
1477 return (address)Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
1478 (intptr_t)(int_at(4) & 0xffff),
1479 (intptr_t)(int_at(0) & 0xffff),
1480 (intptr_t)0);
1481 }
1483 //ori dst, R0, imm16
1484 //dsll dst, dst, 16
1485 //ori dst, dst, imm16
1486 //nop
1487 if ( is_op(Assembler::ori_op) &&
1488 is_special_op(int_at(4), Assembler::dsll_op) &&
1489 is_op (int_at(8), Assembler::ori_op) &&
1490 nativeInstruction_at(addr_at(12))->is_nop()) {
1492 return (address)Assembler::merge( (intptr_t)(int_at(8) & 0xffff),
1493 (intptr_t)(int_at(0) & 0xffff),
1494 (intptr_t)0,
1495 (intptr_t)0);
1496 }
1498 //ori dst, R0, imm16
1499 //dsll dst, dst, 16
1500 //nop
1501 //nop
1502 if ( is_op(Assembler::ori_op) &&
1503 is_special_op(int_at(4), Assembler::dsll_op) &&
1504 nativeInstruction_at(addr_at(8))->is_nop() &&
1505 nativeInstruction_at(addr_at(12))->is_nop()) {
1507 return (address)Assembler::merge( (intptr_t)(0),
1508 (intptr_t)(int_at(0) & 0xffff),
1509 (intptr_t)0,
1510 (intptr_t)0);
1511 }
1513 //daddiu dst, R0, imm16
1514 //nop
1515 //nop
1516 //nop
1517 if ( is_op(Assembler::daddiu_op) &&
1518 nativeInstruction_at(addr_at(4))->is_nop() &&
1519 nativeInstruction_at(addr_at(8))->is_nop() &&
1520 nativeInstruction_at(addr_at(12))->is_nop() ) {
1522 int sign = int_at(0) & 0x8000;
1523 if (sign == 0) {
1524 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
1525 (intptr_t)0,
1526 (intptr_t)0,
1527 (intptr_t)0);
1528 } else {
1529 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
1530 (intptr_t)(0xffff),
1531 (intptr_t)(0xffff),
1532 (intptr_t)(0xffff));
1533 }
1534 }
1536 //lui dst, imm16
1537 //ori dst, dst, imm16
1538 //nop
1539 //nop
1540 if ( is_op(Assembler::lui_op) &&
1541 is_op (int_at(4), Assembler::ori_op) &&
1542 nativeInstruction_at(addr_at(8))->is_nop() &&
1543 nativeInstruction_at(addr_at(12))->is_nop() ) {
1545 int sign = int_at(0) & 0x8000;
1546 if (sign == 0) {
1547 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
1548 (intptr_t)(int_at(0) & 0xffff),
1549 (intptr_t)0,
1550 (intptr_t)0);
1551 } else {
1552 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
1553 (intptr_t)(int_at(0) & 0xffff),
1554 (intptr_t)(0xffff),
1555 (intptr_t)(0xffff));
1556 }
1557 }
1559 //lui dst, imm16
1560 //nop
1561 //nop
1562 //nop
1563 if ( is_op(Assembler::lui_op) &&
1564 nativeInstruction_at(addr_at(4))->is_nop() &&
1565 nativeInstruction_at(addr_at(8))->is_nop() &&
1566 nativeInstruction_at(addr_at(12))->is_nop() ) {
1568 int sign = int_at(0) & 0x8000;
1569 if (sign == 0) {
1570 return (address)Assembler::merge( (intptr_t)0,
1571 (intptr_t)(int_at(0) & 0xffff),
1572 (intptr_t)0,
1573 (intptr_t)0);
1574 } else {
1575 return (address)Assembler::merge( (intptr_t)0,
1576 (intptr_t)(int_at(0) & 0xffff),
1577 (intptr_t)(0xffff),
1578 (intptr_t)(0xffff));
1579 }
1580 }
1582 fatal("not a jump");
1583 #endif
1584 }
1586 // MT-safe patching of a long jump instruction.
1587 // First patches first word of instruction to two jmp's that jmps to them
1588 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
1589 // the jmp's with the first 4 byte of the new instruction.
1590 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
1591 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr);
1592 assert(NativeGeneralJump::instruction_size == NativeCall::instruction_size,
1593 "note::Runtime1::patch_code uses NativeCall::instruction_size");
1595 /* 2013/6/13 Jin: ensure 100% atomicity */
1596 guarantee(!os::is_MP() || (((long)instr_addr % BytesPerWord) == 0), "destination must be aligned for SD");
1598 int *p = (int *)instr_addr;
1599 int jr_word = p[4];
1601 p[4] = 0x1000fffb; /* .1: --; --; --; --; b .1; nop */
1602 memcpy(instr_addr, code_buffer, NativeCall::instruction_size - 8);
1603 *(long *)(instr_addr + 16) = *(long *)(code_buffer + 16);
1604 }
1606 /* Must ensure atomicity */
1607 void NativeGeneralJump::patch_verified_entry(address entry, address verified_entry, address dest) {
1608 /* 2013/11/5 Jin: ensure 100% atomicity.
1609 * The destination is fixed and can be cached in JavaThread.
1610 */
1611 guarantee(!os::is_MP() || (((long)verified_entry % BytesPerWord) == 0), "destination must be aligned for SD");
1613 int code_buffer[4];
1615 CodeBuffer cb((address)code_buffer, instruction_size);
1616 MacroAssembler masm(&cb);
1617 #define __ masm.
1618 __ ld(T9, TREG, in_bytes(JavaThread::handle_wrong_method_stub_offset()));
1619 __ jr(T9);
1620 __ delayed()->nop();
1621 __ nop();
1623 atomic_store128_ptr func = get_atomic_store128_func();
1624 (*func)((long *)verified_entry, 0, *(long *)&code_buffer[0], *(long *)&code_buffer[2]);
1626 ICache::invalidate_range(verified_entry, instruction_size);
1627 }
1629 bool NativeInstruction::is_jump()
1630 {
1631 #ifndef _LP64
1632 return ((int_at(0) & NativeGeneralJump::b_mask) == NativeGeneralJump::beq_opcode) ||
1633 (is_op(int_at(0), Assembler::lui_op) &&
1634 is_op(int_at(4), Assembler::addiu_op) &&
1635 is_special_op(int_at(8), Assembler::jr_op));
1636 #else
1637 // lui rd, imm(63...48);
1638 // ori rd, rd, imm(47...32);
1639 // dsll rd, rd, 16;
1640 // ori rd, rd, imm(31...16);
1641 // dsll rd, rd, 16;
1642 // ori rd, rd, imm(15...0);
1643 // jalr rd
1644 // nop
1645 //
1646 if ((int_at(0) & NativeGeneralJump::b_mask) == NativeGeneralJump::beq_opcode)
1647 return true;
1648 if (is_op(int_at(4), Assembler::lui_op)) /* simplified b_far */
1649 return true;
1650 if (is_op(int_at(12), Assembler::lui_op)) /* original b_far */
1651 return true;
1653 // nop
1654 // nop
1655 // nop
1656 // nop
1657 // j target
1658 // nop
1659 if ( is_nop() &&
1660 nativeInstruction_at(addr_at(4))->is_nop() &&
1661 nativeInstruction_at(addr_at(8))->is_nop() &&
1662 nativeInstruction_at(addr_at(12))->is_nop() &&
1663 nativeInstruction_at(addr_at(16))->is_op(Assembler::j_op) &&
1664 nativeInstruction_at(addr_at(20))->is_nop() ) {
1665 return true;
1666 }
1668 if ( nativeInstruction_at(addr_at(0))->is_op(Assembler::j_op) &&
1669 nativeInstruction_at(addr_at(4))->is_nop() ) {
1670 return true;
1671 }
1673 if (is_op(int_at(0), Assembler::lui_op) &&
1674 is_op(int_at(4), Assembler::ori_op) &&
1675 is_special_op(int_at(8), Assembler::dsll_op) &&
1676 is_op(int_at(12), Assembler::ori_op) &&
1677 is_special_op(int_at(16), Assembler::dsll_op) &&
1678 is_op(int_at(20), Assembler::ori_op))
1679 return true;
1680 if (is_op(int_at(0), Assembler::lui_op) &&
1681 is_op(int_at(4), Assembler::ori_op) &&
1682 is_special_op(int_at(8), Assembler::dsll_op) &&
1683 is_op(int_at(12), Assembler::ori_op))
1684 return true;
1686 //ori dst, R0, imm16
1687 //dsll dst, dst, 16
1688 //ori dst, dst, imm16
1689 //nop
1690 if ( is_op(Assembler::ori_op) &&
1691 is_special_op(int_at(4), Assembler::dsll_op) &&
1692 is_op (int_at(8), Assembler::ori_op) &&
1693 nativeInstruction_at(addr_at(12))->is_nop()) {
1694 return true;
1695 }
1697 //ori dst, R0, imm16
1698 //dsll dst, dst, 16
1699 //nop
1700 //nop
1701 if ( is_op(Assembler::ori_op) &&
1702 is_special_op(int_at(4), Assembler::dsll_op) &&
1703 nativeInstruction_at(addr_at(8))->is_nop() &&
1704 nativeInstruction_at(addr_at(12))->is_nop()) {
1705 return true;
1706 }
1708 //daddiu dst, R0, imm16
1709 //nop
1710 //nop
1711 //nop
1712 if ( is_op(Assembler::daddiu_op) &&
1713 nativeInstruction_at(addr_at(4))->is_nop() &&
1714 nativeInstruction_at(addr_at(8))->is_nop() &&
1715 nativeInstruction_at(addr_at(12))->is_nop() ) {
1716 return true;
1717 }
1719 //lui dst, imm16
1720 //ori dst, dst, imm16
1721 //nop
1722 //nop
1723 if ( is_op(Assembler::lui_op) &&
1724 is_op (int_at(4), Assembler::ori_op) &&
1725 nativeInstruction_at(addr_at(8))->is_nop() &&
1726 nativeInstruction_at(addr_at(12))->is_nop() ) {
1727 return true;
1728 }
1730 //lui dst, imm16
1731 //nop
1732 //nop
1733 //nop
1734 if ( is_op(Assembler::lui_op) &&
1735 nativeInstruction_at(addr_at(4))->is_nop() &&
1736 nativeInstruction_at(addr_at(8))->is_nop() &&
1737 nativeInstruction_at(addr_at(12))->is_nop() ) {
1738 return true;
1739 }
1741 return false;
1742 #endif
1743 }
1745 bool NativeInstruction::is_dtrace_trap() {
1746 //return (*(int32_t*)this & 0xff) == 0xcc;
1747 Unimplemented();
1748 return false;
1749 }
1751 bool NativeInstruction::is_safepoint_poll() {
1752 #ifdef _LP64
1753 /*
1754 390 li T2, 0x0000000000400000 #@loadConP
1755 394 sw [SP + #12], V1 # spill 9
1756 398 Safepoint @ [T2] : poll for GC @ safePoint_poll # spec.benchmarks.compress.Decompressor::decompress @ bci:224 L[0]=A6 L[1]=_ L[2]=sp + #28 L[3]=_ L[4]=V1
1758 0x000000ffe5815130: lui t2, 0x40
1759 0x000000ffe5815134: sw v1, 0xc(sp) ; OopMap{a6=Oop off=920}
1760 ;*goto
1761 ; - spec.benchmarks.compress.Decompressor::decompress@224 (line 584)
1763 0x000000ffe5815138: lw at, 0x0(t2) ;*goto <--- PC
1764 ; - spec.benchmarks.compress.Decompressor::decompress@224 (line 584)
1765 */
1767 // Since there may be some spill instructions between the safePoint_poll and loadConP,
1768 // we check the safepoint instruction like the this.
1769 return is_op(Assembler::lw_op) && is_rt(AT);
1770 #else
1771 return is_op(int_at(-4), Assembler::lui_op) &&
1772 is_op(Assembler::lw_op) &&
1773 is_rt(AT);
1774 #endif
1775 }
