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src/cpu/ppc/vm/vm_version_ppc.cpp@c4567d28f31f
src/cpu/ppc/vm/vm_version_ppc.cpp
Tue, 18 Jun 2019 09:33:34 -0400
- author
- ogatak
- date
- Tue, 18 Jun 2019 09:33:34 -0400
- changeset 9713
- c4567d28f31f
- parent 9684
- 69f33959c27f
- child 9730
- 42118db355f5
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8185979: PPC64: Implement SHA2 intrinsic
Reviewed-by: mdoerr, goetz
Contributed-by: Bruno Rosa <bruno.rosa@eldorado.org.br>, Gustavo Serra Scalet <gustavo.scalet@eldorado.org.br>, Igor Nunes <igor.nunes@eldorado.org.br>, Martin Doerr <martin.doerr@sap.com>
1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2018 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "utilities/defaultStream.hpp"
34 #include "vm_version_ppc.hpp"
35 #ifdef TARGET_OS_FAMILY_aix
36 # include "os_aix.inline.hpp"
37 #endif
38 #ifdef TARGET_OS_FAMILY_linux
39 # include "os_linux.inline.hpp"
40 #endif
42 # include <sys/sysinfo.h>
44 int VM_Version::_features = VM_Version::unknown_m;
45 int VM_Version::_measured_cache_line_size = 128; // default value
46 const char* VM_Version::_features_str = "";
47 bool VM_Version::_is_determine_features_test_running = false;
48 uint64_t VM_Version::_dscr_val = 0;
50 #define MSG(flag) \
51 if (flag && !FLAG_IS_DEFAULT(flag)) \
52 jio_fprintf(defaultStream::error_stream(), \
53 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
54 " -XX:+" #flag " will be disabled!\n");
56 void VM_Version::initialize() {
58 // Test which instructions are supported and measure cache line size.
59 determine_features();
61 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
62 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
63 if (VM_Version::has_lqarx()) {
64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
65 } else if (VM_Version::has_popcntw()) {
66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
67 } else if (VM_Version::has_cmpb()) {
68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
69 } else if (VM_Version::has_popcntb()) {
70 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
71 } else {
72 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
73 }
74 }
75 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
76 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 ||
77 PowerArchitecturePPC64 == 8,
78 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8");
80 // Power 8: Configure Data Stream Control Register.
81 if (PowerArchitecturePPC64 >= 8) {
82 config_dscr();
83 }
85 if (!UseSIGTRAP) {
86 MSG(TrapBasedICMissChecks);
87 MSG(TrapBasedNotEntrantChecks);
88 MSG(TrapBasedNullChecks);
89 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
90 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
91 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
92 }
94 #ifdef COMPILER2
95 if (!UseSIGTRAP) {
96 MSG(TrapBasedRangeChecks);
97 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
98 }
100 // On Power6 test for section size.
101 if (PowerArchitecturePPC64 == 6) {
102 determine_section_size();
103 // TODO: PPC port } else {
104 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
105 }
107 MaxVectorSize = 8;
108 #endif
110 // Create and print feature-string.
111 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
112 jio_snprintf(buf, sizeof(buf),
113 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
114 (has_fsqrt() ? " fsqrt" : ""),
115 (has_isel() ? " isel" : ""),
116 (has_lxarxeh() ? " lxarxeh" : ""),
117 (has_cmpb() ? " cmpb" : ""),
118 //(has_mftgpr()? " mftgpr" : ""),
119 (has_popcntb() ? " popcntb" : ""),
120 (has_popcntw() ? " popcntw" : ""),
121 (has_fcfids() ? " fcfids" : ""),
122 (has_vand() ? " vand" : ""),
123 (has_lqarx() ? " lqarx" : ""),
124 (has_vcipher() ? " aes" : ""),
125 (has_vpmsumb() ? " vpmsumb" : ""),
126 (has_mfdscr() ? " mfdscr" : ""),
127 (has_vsx() ? " vsx" : ""),
128 (has_vshasig() ? " sha" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_str = strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
141 UseSSE = 0; // Only on x86 and x64
143 intx cache_line_size = _measured_cache_line_size;
145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
147 if (AllocatePrefetchStyle == 4) {
148 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
149 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
150 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
151 } else {
152 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
153 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
154 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
155 }
157 assert(AllocatePrefetchLines > 0, "invalid value");
158 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
159 AllocatePrefetchLines = 1; // Conservative value.
160 }
162 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
163 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
164 }
166 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
168 // Implementation does not use any of the vector instructions
169 // available with Power8. Their exploitation is still pending.
170 if (!UseCRC32Intrinsics) {
171 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
172 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
173 }
174 }
176 // The AES intrinsic stubs require AES instruction support.
177 #if defined(VM_LITTLE_ENDIAN)
178 if (has_vcipher()) {
179 if (FLAG_IS_DEFAULT(UseAES)) {
180 UseAES = true;
181 }
182 } else if (UseAES) {
183 if (!FLAG_IS_DEFAULT(UseAES))
184 warning("AES instructions are not available on this CPU");
185 FLAG_SET_DEFAULT(UseAES, false);
186 }
188 if (UseAES && has_vcipher()) {
189 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
190 UseAESIntrinsics = true;
191 }
192 } else if (UseAESIntrinsics) {
193 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
194 warning("AES intrinsics are not available on this CPU");
195 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
196 }
198 #else
199 if (UseAES) {
200 warning("AES instructions are not available on this CPU");
201 FLAG_SET_DEFAULT(UseAES, false);
202 }
203 if (UseAESIntrinsics) {
204 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
205 warning("AES intrinsics are not available on this CPU");
206 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
207 }
208 #endif
210 if (has_vshasig()) {
211 if (FLAG_IS_DEFAULT(UseSHA)) {
212 UseSHA = true;
213 }
214 } else if (UseSHA) {
215 if (!FLAG_IS_DEFAULT(UseSHA))
216 warning("SHA instructions are not available on this CPU");
217 FLAG_SET_DEFAULT(UseSHA, false);
218 }
220 if (UseSHA1Intrinsics) {
221 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
222 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
223 }
225 if (UseSHA && has_vshasig()) {
226 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
227 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
228 }
229 } else if (UseSHA256Intrinsics) {
230 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
231 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
232 }
234 if (UseSHA && has_vshasig()) {
235 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
236 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
237 }
238 } else if (UseSHA512Intrinsics) {
239 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
240 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
241 }
243 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
244 FLAG_SET_DEFAULT(UseSHA, false);
245 }
247 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
248 UseMontgomeryMultiplyIntrinsic = true;
249 }
250 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
251 UseMontgomerySquareIntrinsic = true;
252 }
253 }
255 void VM_Version::print_features() {
256 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
257 }
259 #ifdef COMPILER2
260 // Determine section size on power6: If section size is 8 instructions,
261 // there should be a difference between the two testloops of ~15 %. If
262 // no difference is detected the section is assumed to be 32 instructions.
263 void VM_Version::determine_section_size() {
265 int unroll = 80;
267 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
269 // Allocate space for the code.
270 ResourceMark rm;
271 CodeBuffer cb("detect_section_size", code_size, 0);
272 MacroAssembler* a = new MacroAssembler(&cb);
274 uint32_t *code = (uint32_t *)a->pc();
275 // Emit code.
276 void (*test1)() = (void(*)())(void *)a->function_entry();
278 Label l1;
280 a->li(R4, 1);
281 a->sldi(R4, R4, 28);
282 a->b(l1);
283 a->align(CodeEntryAlignment);
285 a->bind(l1);
287 for (int i = 0; i < unroll; i++) {
288 // Schleife 1
289 // ------- sector 0 ------------
290 // ;; 0
291 a->nop(); // 1
292 a->fpnop0(); // 2
293 a->fpnop1(); // 3
294 a->addi(R4,R4, -1); // 4
296 // ;; 1
297 a->nop(); // 5
298 a->fmr(F6, F6); // 6
299 a->fmr(F7, F7); // 7
300 a->endgroup(); // 8
301 // ------- sector 8 ------------
303 // ;; 2
304 a->nop(); // 9
305 a->nop(); // 10
306 a->fmr(F8, F8); // 11
307 a->fmr(F9, F9); // 12
309 // ;; 3
310 a->nop(); // 13
311 a->fmr(F10, F10); // 14
312 a->fmr(F11, F11); // 15
313 a->endgroup(); // 16
314 // -------- sector 16 -------------
316 // ;; 4
317 a->nop(); // 17
318 a->nop(); // 18
319 a->fmr(F15, F15); // 19
320 a->fmr(F16, F16); // 20
322 // ;; 5
323 a->nop(); // 21
324 a->fmr(F17, F17); // 22
325 a->fmr(F18, F18); // 23
326 a->endgroup(); // 24
327 // ------- sector 24 ------------
329 // ;; 6
330 a->nop(); // 25
331 a->nop(); // 26
332 a->fmr(F19, F19); // 27
333 a->fmr(F20, F20); // 28
335 // ;; 7
336 a->nop(); // 29
337 a->fmr(F21, F21); // 30
338 a->fmr(F22, F22); // 31
339 a->brnop0(); // 32
341 // ------- sector 32 ------------
342 }
344 // ;; 8
345 a->cmpdi(CCR0, R4, unroll); // 33
346 a->bge(CCR0, l1); // 34
347 a->blr();
349 // Emit code.
350 void (*test2)() = (void(*)())(void *)a->function_entry();
351 // uint32_t *code = (uint32_t *)a->pc();
353 Label l2;
355 a->li(R4, 1);
356 a->sldi(R4, R4, 28);
357 a->b(l2);
358 a->align(CodeEntryAlignment);
360 a->bind(l2);
362 for (int i = 0; i < unroll; i++) {
363 // Schleife 2
364 // ------- sector 0 ------------
365 // ;; 0
366 a->brnop0(); // 1
367 a->nop(); // 2
368 //a->cmpdi(CCR0, R4, unroll);
369 a->fpnop0(); // 3
370 a->fpnop1(); // 4
371 a->addi(R4,R4, -1); // 5
373 // ;; 1
375 a->nop(); // 6
376 a->fmr(F6, F6); // 7
377 a->fmr(F7, F7); // 8
378 // ------- sector 8 ---------------
380 // ;; 2
381 a->endgroup(); // 9
383 // ;; 3
384 a->nop(); // 10
385 a->nop(); // 11
386 a->fmr(F8, F8); // 12
388 // ;; 4
389 a->fmr(F9, F9); // 13
390 a->nop(); // 14
391 a->fmr(F10, F10); // 15
393 // ;; 5
394 a->fmr(F11, F11); // 16
395 // -------- sector 16 -------------
397 // ;; 6
398 a->endgroup(); // 17
400 // ;; 7
401 a->nop(); // 18
402 a->nop(); // 19
403 a->fmr(F15, F15); // 20
405 // ;; 8
406 a->fmr(F16, F16); // 21
407 a->nop(); // 22
408 a->fmr(F17, F17); // 23
410 // ;; 9
411 a->fmr(F18, F18); // 24
412 // -------- sector 24 -------------
414 // ;; 10
415 a->endgroup(); // 25
417 // ;; 11
418 a->nop(); // 26
419 a->nop(); // 27
420 a->fmr(F19, F19); // 28
422 // ;; 12
423 a->fmr(F20, F20); // 29
424 a->nop(); // 30
425 a->fmr(F21, F21); // 31
427 // ;; 13
428 a->fmr(F22, F22); // 32
429 }
431 // -------- sector 32 -------------
432 // ;; 14
433 a->cmpdi(CCR0, R4, unroll); // 33
434 a->bge(CCR0, l2); // 34
436 a->blr();
437 uint32_t *code_end = (uint32_t *)a->pc();
438 a->flush();
440 double loop1_seconds,loop2_seconds, rel_diff;
441 uint64_t start1, stop1;
443 start1 = os::current_thread_cpu_time(false);
444 (*test1)();
445 stop1 = os::current_thread_cpu_time(false);
446 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
449 start1 = os::current_thread_cpu_time(false);
450 (*test2)();
451 stop1 = os::current_thread_cpu_time(false);
453 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
455 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
457 if (PrintAssembly) {
458 ttyLocker ttyl;
459 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
460 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
461 tty->print_cr("Time loop1 :%f", loop1_seconds);
462 tty->print_cr("Time loop2 :%f", loop2_seconds);
463 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
465 if (rel_diff > 12.0) {
466 tty->print_cr("Section Size 8 Instructions");
467 } else{
468 tty->print_cr("Section Size 32 Instructions or Power5");
469 }
470 }
472 #if 0 // TODO: PPC port
473 // Set sector size (if not set explicitly).
474 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
475 if (rel_diff > 12.0) {
476 PdScheduling::power6SectorSize = 0x20;
477 } else {
478 PdScheduling::power6SectorSize = 0x80;
479 }
480 } else if (Power6SectorSize128PPC64) {
481 PdScheduling::power6SectorSize = 0x80;
482 } else {
483 PdScheduling::power6SectorSize = 0x20;
484 }
485 #endif
486 if (UsePower6SchedulerPPC64) Unimplemented();
487 }
488 #endif // COMPILER2
490 void VM_Version::determine_features() {
491 #if defined(ABI_ELFv2)
492 const int code_size = (num_features+1+2*7)*BytesPerInstWord; // TODO(asmundak): calculation is incorrect.
493 #else
494 // 7 InstWords for each call (function descriptor + blr instruction).
495 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
496 #endif
497 int features = 0;
499 // create test area
500 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
501 char test_area[BUFFER_SIZE];
502 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
504 // Allocate space for the code.
505 ResourceMark rm;
506 CodeBuffer cb("detect_cpu_features", code_size, 0);
507 MacroAssembler* a = new MacroAssembler(&cb);
509 // Must be set to true so we can generate the test code.
510 _features = VM_Version::all_features_m;
512 // Emit code.
513 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
514 uint32_t *code = (uint32_t *)a->pc();
515 // Don't use R0 in ldarx.
516 // Keep R3_ARG1 unmodified, it contains &field (see below).
517 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
518 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
519 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
520 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
521 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
522 a->cmpb(R7, R5, R6); // code[4] -> bcmp
523 //a->mftgpr(R7, F3); // code[5] -> mftgpr
524 a->popcntb(R7, R5); // code[6] -> popcntb
525 a->popcntw(R7, R5); // code[7] -> popcntw
526 a->fcfids(F3, F4); // code[8] -> fcfids
527 a->vand(VR0, VR0, VR0); // code[9] -> vand
528 a->lqarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[10] -> lqarx_m
529 a->vcipher(VR0, VR1, VR2); // code[11] -> vcipher
530 a->vpmsumb(VR0, VR1, VR2); // code[12] -> vpmsumb
531 a->mfdscr(R0); // code[13] -> mfdscr
532 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
533 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[15] -> vshasig
534 a->blr();
536 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
537 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
538 a->dcbz(R3_ARG1); // R3_ARG1 = addr
539 a->blr();
541 uint32_t *code_end = (uint32_t *)a->pc();
542 a->flush();
543 _features = VM_Version::unknown_m;
545 // Print the detection code.
546 if (PrintAssembly) {
547 ttyLocker ttyl;
548 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
549 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
550 }
552 // Measure cache line size.
553 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
554 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
555 int count = 0; // count zeroed bytes
556 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
557 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
558 _measured_cache_line_size = count;
560 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
561 VM_Version::_is_determine_features_test_running = true;
562 (*test)((address)mid_of_test_area, (uint64_t)0);
563 VM_Version::_is_determine_features_test_running = false;
565 // determine which instructions are legal.
566 int feature_cntr = 0;
567 if (code[feature_cntr++]) features |= fsqrt_m;
568 if (code[feature_cntr++]) features |= fsqrts_m;
569 if (code[feature_cntr++]) features |= isel_m;
570 if (code[feature_cntr++]) features |= lxarxeh_m;
571 if (code[feature_cntr++]) features |= cmpb_m;
572 //if(code[feature_cntr++])features |= mftgpr_m;
573 if (code[feature_cntr++]) features |= popcntb_m;
574 if (code[feature_cntr++]) features |= popcntw_m;
575 if (code[feature_cntr++]) features |= fcfids_m;
576 if (code[feature_cntr++]) features |= vand_m;
577 if (code[feature_cntr++]) features |= lqarx_m;
578 if (code[feature_cntr++]) features |= vcipher_m;
579 if (code[feature_cntr++]) features |= vpmsumb_m;
580 if (code[feature_cntr++]) features |= mfdscr_m;
581 if (code[feature_cntr++]) features |= vsx_m;
582 if (code[feature_cntr++]) features |= vshasig_m;
584 // Print the detection code.
585 if (PrintAssembly) {
586 ttyLocker ttyl;
587 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
588 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
589 }
591 _features = features;
592 }
594 // Power 8: Configure Data Stream Control Register.
595 void VM_Version::config_dscr() {
596 assert(has_lqarx(), "Only execute on Power 8 or later!");
598 // 7 InstWords for each call (function descriptor + blr instruction).
599 const int code_size = (2+2*7)*BytesPerInstWord;
601 // Allocate space for the code.
602 ResourceMark rm;
603 CodeBuffer cb("config_dscr", code_size, 0);
604 MacroAssembler* a = new MacroAssembler(&cb);
606 // Emit code.
607 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
608 uint32_t *code = (uint32_t *)a->pc();
609 a->mfdscr(R3);
610 a->blr();
612 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
613 a->mtdscr(R3);
614 a->blr();
616 uint32_t *code_end = (uint32_t *)a->pc();
617 a->flush();
619 // Print the detection code.
620 if (PrintAssembly) {
621 ttyLocker ttyl;
622 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
623 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
624 }
626 // Apply the configuration if needed.
627 _dscr_val = (*get_dscr)();
628 if (Verbose) {
629 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
630 }
631 bool change_requested = false;
632 if (DSCR_PPC64 != (uintx)-1) {
633 _dscr_val = DSCR_PPC64;
634 change_requested = true;
635 }
636 if (DSCR_DPFD_PPC64 <= 7) {
637 uint64_t mask = 0x7;
638 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
639 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
640 change_requested = true;
641 }
642 }
643 if (DSCR_URG_PPC64 <= 7) {
644 uint64_t mask = 0x7 << 6;
645 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
646 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
647 change_requested = true;
648 }
649 }
650 if (change_requested) {
651 (*set_dscr)(_dscr_val);
652 if (Verbose) {
653 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
654 }
655 }
656 }
658 static int saved_features = 0;
660 void VM_Version::allow_all() {
661 saved_features = _features;
662 _features = all_features_m;
663 }
665 void VM_Version::revert() {
666 _features = saved_features;
667 }
