Wed, 29 Jan 2014 12:22:13 +0100
8033117: PPC64: Adapt to 8002074: Support for AES on SPARC
Summary: Implement missing function Matcher::pass_original_key_for_aes() in ppc64 ad file.
Reviewed-by: kvn
1 //
2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2013 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 //
27 // PPC64 Architecture Description File
28 //
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
79 // PPC64 has 32 64-bit integer registers.
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
233 // Condition Codes Flag Registers
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
248 // Special registers of PPC64
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
267 // It's worth about 1% on SPEC geomean to get this right.
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
335 // scratch register
336 F0, F0_H,
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
398 //-------Architecture Description Register Classes-----------------------
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
560 reg_class r19_bits64_reg(R19_H, R19);
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
861 %}
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Returns true if Node n is followed by a MemBar node that
895 // will do an acquire. If so, this node must not do the acquire
896 // operation.
897 bool followed_by_acquire(const Node *n);
898 %}
900 source %{
902 // Optimize load-acquire.
903 //
904 // Check if acquire is unnecessary due to following operation that does
905 // acquire anyways.
906 // Walk the pattern:
907 //
908 // n: Load.acq
909 // |
910 // MemBarAcquire
911 // | |
912 // Proj(ctrl) Proj(mem)
913 // | |
914 // MemBarRelease/Volatile
915 //
916 bool followed_by_acquire(const Node *load) {
917 assert(load->is_Load(), "So far implemented only for loads.");
919 // Find MemBarAcquire.
920 const Node *mba = NULL;
921 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
922 const Node *out = load->fast_out(i);
923 if (out->Opcode() == Op_MemBarAcquire) {
924 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
925 mba = out;
926 break;
927 }
928 }
929 if (!mba) return false;
931 // Find following MemBar node.
932 //
933 // The following node must be reachable by control AND memory
934 // edge to assure no other operations are in between the two nodes.
935 //
936 // So first get the Proj node, mem_proj, to use it to iterate forward.
937 Node *mem_proj = NULL;
938 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
939 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
940 assert(mem_proj->is_Proj(), "only projections here");
941 ProjNode *proj = mem_proj->as_Proj();
942 if (proj->_con == TypeFunc::Memory &&
943 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
944 break;
945 }
946 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
948 // Search MemBar behind Proj. If there are other memory operations
949 // behind the Proj we lost.
950 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
951 Node *x = mem_proj->fast_out(j);
952 // Proj might have an edge to a store or load node which precedes the membar.
953 if (x->is_Mem()) return false;
955 // On PPC64 release and volatile are implemented by an instruction
956 // that also has acquire semantics. I.e. there is no need for an
957 // acquire before these.
958 int xop = x->Opcode();
959 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
960 // Make sure we're not missing Call/Phi/MergeMem by checking
961 // control edges. The control edge must directly lead back
962 // to the MemBarAcquire
963 Node *ctrl_proj = x->in(0);
964 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
965 return true;
966 }
967 }
968 }
970 return false;
971 }
973 #define __ _masm.
975 // Tertiary op of a LoadP or StoreP encoding.
976 #define REGP_OP true
978 // ****************************************************************************
980 // REQUIRED FUNCTIONALITY
982 // !!!!! Special hack to get all type of calls to specify the byte offset
983 // from the start of the call to the point where the return address
984 // will point.
986 // PPC port: Removed use of lazy constant construct.
988 int MachCallStaticJavaNode::ret_addr_offset() {
989 // It's only a single branch-and-link instruction.
990 return 4;
991 }
993 int MachCallDynamicJavaNode::ret_addr_offset() {
994 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
995 // postalloc expanded calls if we use inline caches and do not update method data.
996 if (UseInlineCaches)
997 return 4;
999 int vtable_index = this->_vtable_index;
1000 if (vtable_index < 0) {
1001 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1002 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1003 return 12;
1004 } else {
1005 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1006 return 24;
1007 }
1008 }
1010 int MachCallRuntimeNode::ret_addr_offset() {
1011 return 40;
1012 }
1014 //=============================================================================
1016 // condition code conversions
1018 static int cc_to_boint(int cc) {
1019 return Assembler::bcondCRbiIs0 | (cc & 8);
1020 }
1022 static int cc_to_inverse_boint(int cc) {
1023 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1024 }
1026 static int cc_to_biint(int cc, int flags_reg) {
1027 return (flags_reg << 2) | (cc & 3);
1028 }
1030 //=============================================================================
1032 // Compute padding required for nodes which need alignment. The padding
1033 // is the number of bytes (not instructions) which will be inserted before
1034 // the instruction. The padding must match the size of a NOP instruction.
1036 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1037 return (3*4-current_offset)&31;
1038 }
1040 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1041 return (2*4-current_offset)&31;
1042 }
1044 int string_indexOf_immNode::compute_padding(int current_offset) const {
1045 return (3*4-current_offset)&31;
1046 }
1048 int string_indexOfNode::compute_padding(int current_offset) const {
1049 return (1*4-current_offset)&31;
1050 }
1052 int string_compareNode::compute_padding(int current_offset) const {
1053 return (4*4-current_offset)&31;
1054 }
1056 int string_equals_immNode::compute_padding(int current_offset) const {
1057 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1058 return (2*4-current_offset)&31;
1059 }
1061 int string_equalsNode::compute_padding(int current_offset) const {
1062 return (7*4-current_offset)&31;
1063 }
1065 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1066 return (2*4-current_offset)&31;
1067 }
1069 //=============================================================================
1071 // Indicate if the safepoint node needs the polling page as an input.
1072 bool SafePointNode::needs_polling_address_input() {
1073 // The address is loaded from thread by a seperate node.
1074 return true;
1075 }
1077 //=============================================================================
1079 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1080 void emit_break(CodeBuffer &cbuf) {
1081 MacroAssembler _masm(&cbuf);
1082 __ illtrap();
1083 }
1085 #ifndef PRODUCT
1086 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1087 st->print("BREAKPOINT");
1088 }
1089 #endif
1091 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1092 emit_break(cbuf);
1093 }
1095 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1096 return MachNode::size(ra_);
1097 }
1099 //=============================================================================
1101 void emit_nop(CodeBuffer &cbuf) {
1102 MacroAssembler _masm(&cbuf);
1103 __ nop();
1104 }
1106 static inline void emit_long(CodeBuffer &cbuf, int value) {
1107 *((int*)(cbuf.insts_end())) = value;
1108 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1109 }
1111 //=============================================================================
1113 // Emit a trampoline stub for a call to a target which is too far away.
1114 //
1115 // code sequences:
1116 //
1117 // call-site:
1118 // branch-and-link to <destination> or <trampoline stub>
1119 //
1120 // Related trampoline stub for this call-site in the stub section:
1121 // load the call target from the constant pool
1122 // branch via CTR (LR/link still points to the call-site above)
1124 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1126 void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1127 // Start the stub.
1128 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1129 if (stub == NULL) {
1130 Compile::current()->env()->record_out_of_memory_failure();
1131 return;
1132 }
1134 // For java_to_interp stubs we use R11_scratch1 as scratch register
1135 // and in call trampoline stubs we use R12_scratch2. This way we
1136 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1137 Register reg_scratch = R12_scratch2;
1139 // Create a trampoline stub relocation which relates this trampoline stub
1140 // with the call instruction at insts_call_instruction_offset in the
1141 // instructions code-section.
1142 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1143 const int stub_start_offset = __ offset();
1145 // Now, create the trampoline stub's code:
1146 // - load the TOC
1147 // - load the call target from the constant pool
1148 // - call
1149 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1150 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1151 __ mtctr(reg_scratch);
1152 __ bctr();
1154 const address stub_start_addr = __ addr_at(stub_start_offset);
1156 // FIXME: Assert that the trampoline stub can be identified and patched.
1158 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1159 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1160 "encoded offset into the constant pool must match");
1161 // Trampoline_stub_size should be good.
1162 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1163 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1165 // End the stub.
1166 __ end_a_stub();
1167 }
1169 // Size of trampoline stub, this doesn't need to be accurate but it must
1170 // be larger or equal to the real size of the stub.
1171 // Used for optimization in Compile::Shorten_branches.
1172 uint size_call_trampoline() {
1173 return trampoline_stub_size;
1174 }
1176 // Number of relocation entries needed by trampoline stub.
1177 // Used for optimization in Compile::Shorten_branches.
1178 uint reloc_call_trampoline() {
1179 return 5;
1180 }
1182 //=============================================================================
1184 // Emit an inline branch-and-link call and a related trampoline stub.
1185 //
1186 // code sequences:
1187 //
1188 // call-site:
1189 // branch-and-link to <destination> or <trampoline stub>
1190 //
1191 // Related trampoline stub for this call-site in the stub section:
1192 // load the call target from the constant pool
1193 // branch via CTR (LR/link still points to the call-site above)
1194 //
1196 typedef struct {
1197 int insts_call_instruction_offset;
1198 int ret_addr_offset;
1199 } EmitCallOffsets;
1201 // Emit a branch-and-link instruction that branches to a trampoline.
1202 // - Remember the offset of the branch-and-link instruction.
1203 // - Add a relocation at the branch-and-link instruction.
1204 // - Emit a branch-and-link.
1205 // - Remember the return pc offset.
1206 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1207 EmitCallOffsets offsets = { -1, -1 };
1208 const int start_offset = __ offset();
1209 offsets.insts_call_instruction_offset = __ offset();
1211 // No entry point given, use the current pc.
1212 if (entry_point == NULL) entry_point = __ pc();
1214 if (!Compile::current()->in_scratch_emit_size()) {
1215 // Put the entry point as a constant into the constant pool.
1216 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1217 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1219 // Emit the trampoline stub which will be related to the branch-and-link below.
1220 emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1221 __ relocate(rtype);
1222 }
1224 // Note: At this point we do not have the address of the trampoline
1225 // stub, and the entry point might be too far away for bl, so __ pc()
1226 // serves as dummy and the bl will be patched later.
1227 __ bl((address) __ pc());
1229 offsets.ret_addr_offset = __ offset() - start_offset;
1231 return offsets;
1232 }
1234 //=============================================================================
1236 // Factory for creating loadConL* nodes for large/small constant pool.
1238 static inline jlong replicate_immF(float con) {
1239 // Replicate float con 2 times and pack into vector.
1240 int val = *((int*)&con);
1241 jlong lval = val;
1242 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1243 return lval;
1244 }
1246 //=============================================================================
1248 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1249 int Compile::ConstantTable::calculate_table_base_offset() const {
1250 return 0; // absolute addressing, no offset
1251 }
1253 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1254 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1255 Compile *C = ra_->C;
1257 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1258 MachNode *m1 = new (C) loadToc_hiNode();
1259 MachNode *m2 = new (C) loadToc_loNode();
1261 m1->add_req(NULL);
1262 m2->add_req(NULL, m1);
1263 m1->_opnds[0] = op_dst;
1264 m2->_opnds[0] = op_dst;
1265 m2->_opnds[1] = op_dst;
1266 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1267 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1268 nodes->push(m1);
1269 nodes->push(m2);
1270 }
1272 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1273 // Is postalloc expanded.
1274 ShouldNotReachHere();
1275 }
1277 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1278 return 0;
1279 }
1281 #ifndef PRODUCT
1282 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1283 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1284 }
1285 #endif
1287 //=============================================================================
1289 #ifndef PRODUCT
1290 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1291 Compile* C = ra_->C;
1292 const long framesize = C->frame_slots() << LogBytesPerInt;
1294 st->print("PROLOG\n\t");
1295 if (C->need_stack_bang(framesize)) {
1296 st->print("stack_overflow_check\n\t");
1297 }
1299 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1300 st->print("save return pc\n\t");
1301 st->print("push frame %d\n\t", -framesize);
1302 }
1303 }
1304 #endif
1306 // Macro used instead of the common __ to emulate the pipes of PPC.
1307 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1308 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1309 // still no scheduling of this code is possible, the micro scheduler is aware of the
1310 // code and can update its internal data. The following mechanism is used to achieve this:
1311 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1312 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1313 #if 0 // TODO: PPC port
1314 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1315 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1316 _masm.
1317 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1318 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1319 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1320 C->hb_scheduling()->_pdScheduling->advance_offset
1321 #else
1322 #define ___(op) if (UsePower6SchedulerPPC64) \
1323 Unimplemented(); \
1324 _masm.
1325 #define ___stop if (UsePower6SchedulerPPC64) \
1326 Unimplemented()
1327 #define ___advance if (UsePower6SchedulerPPC64) \
1328 Unimplemented()
1329 #endif
1331 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1332 Compile* C = ra_->C;
1333 MacroAssembler _masm(&cbuf);
1335 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1336 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1338 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1340 const Register return_pc = R20; // Must match return_addr() in frame section.
1341 const Register callers_sp = R21;
1342 const Register push_frame_temp = R22;
1343 const Register toc_temp = R23;
1344 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1346 if (method_is_frameless) {
1347 // Add nop at beginning of all frameless methods to prevent any
1348 // oop instructions from getting overwritten by make_not_entrant
1349 // (patching attempt would fail).
1350 ___(nop) nop();
1351 } else {
1352 // Get return pc.
1353 ___(mflr) mflr(return_pc);
1354 }
1356 // Calls to C2R adapters often do not accept exceptional returns.
1357 // We require that their callers must bang for them. But be
1358 // careful, because some VM calls (such as call site linkage) can
1359 // use several kilobytes of stack. But the stack safety zone should
1360 // account for that. See bugs 4446381, 4468289, 4497237.
1361 if (C->need_stack_bang(framesize) && UseStackBanging) {
1362 // Unfortunately we cannot use the function provided in
1363 // assembler.cpp as we have to emulate the pipes. So I had to
1364 // insert the code of generate_stack_overflow_check(), see
1365 // assembler.cpp for some illuminative comments.
1366 const int page_size = os::vm_page_size();
1367 int bang_end = StackShadowPages*page_size;
1369 // This is how far the previous frame's stack banging extended.
1370 const int bang_end_safe = bang_end;
1372 if (framesize > page_size) {
1373 bang_end += framesize;
1374 }
1376 int bang_offset = bang_end_safe;
1378 while (bang_offset <= bang_end) {
1379 // Need at least one stack bang at end of shadow zone.
1381 // Again I had to copy code, this time from assembler_ppc64.cpp,
1382 // bang_stack_with_offset - see there for comments.
1384 // Stack grows down, caller passes positive offset.
1385 assert(bang_offset > 0, "must bang with positive offset");
1387 long stdoffset = -bang_offset;
1389 if (Assembler::is_simm(stdoffset, 16)) {
1390 // Signed 16 bit offset, a simple std is ok.
1391 if (UseLoadInstructionsForStackBangingPPC64) {
1392 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1393 } else {
1394 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1395 }
1396 } else if (Assembler::is_simm(stdoffset, 31)) {
1397 // Use largeoffset calculations for addis & ld/std.
1398 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1399 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1401 Register tmp = R11;
1402 ___(addis) addis(tmp, R1_SP, hi);
1403 if (UseLoadInstructionsForStackBangingPPC64) {
1404 ___(ld) ld(R0, lo, tmp);
1405 } else {
1406 ___(std) std(R0, lo, tmp);
1407 }
1408 } else {
1409 ShouldNotReachHere();
1410 }
1412 bang_offset += page_size;
1413 }
1414 // R11 trashed
1415 } // C->need_stack_bang(framesize) && UseStackBanging
1417 unsigned int bytes = (unsigned int)framesize;
1418 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1419 ciMethod *currMethod = C -> method();
1421 // Optimized version for most common case.
1422 if (UsePower6SchedulerPPC64 &&
1423 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1424 !(false /* ConstantsALot TODO: PPC port*/)) {
1425 ___(or) mr(callers_sp, R1_SP);
1426 ___(std) std(return_pc, _abi(lr), R1_SP);
1427 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1428 return;
1429 }
1431 if (!method_is_frameless) {
1432 // Get callers sp.
1433 ___(or) mr(callers_sp, R1_SP);
1435 // Push method's frame, modifies SP.
1436 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1437 // The ABI is already accounted for in 'framesize' via the
1438 // 'out_preserve' area.
1439 Register tmp = push_frame_temp;
1440 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1441 if (Assembler::is_simm(-offset, 16)) {
1442 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1443 } else {
1444 long x = -offset;
1445 // Had to insert load_const(tmp, -offset).
1446 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1447 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1448 ___(rldicr) sldi(tmp, tmp, 32);
1449 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1450 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1452 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1453 }
1454 }
1455 #if 0 // TODO: PPC port
1456 // For testing large constant pools, emit a lot of constants to constant pool.
1457 // "Randomize" const_size.
1458 if (ConstantsALot) {
1459 const int num_consts = const_size();
1460 for (int i = 0; i < num_consts; i++) {
1461 __ long_constant(0xB0B5B00BBABE);
1462 }
1463 }
1464 #endif
1465 if (!method_is_frameless) {
1466 // Save return pc.
1467 ___(std) std(return_pc, _abi(lr), callers_sp);
1468 }
1469 }
1470 #undef ___
1471 #undef ___stop
1472 #undef ___advance
1474 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1475 // Variable size. determine dynamically.
1476 return MachNode::size(ra_);
1477 }
1479 int MachPrologNode::reloc() const {
1480 // Return number of relocatable values contained in this instruction.
1481 return 1; // 1 reloc entry for load_const(toc).
1482 }
1484 //=============================================================================
1486 #ifndef PRODUCT
1487 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1488 Compile* C = ra_->C;
1490 st->print("EPILOG\n\t");
1491 st->print("restore return pc\n\t");
1492 st->print("pop frame\n\t");
1494 if (do_polling() && C->is_method_compilation()) {
1495 st->print("touch polling page\n\t");
1496 }
1497 }
1498 #endif
1500 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1501 Compile* C = ra_->C;
1502 MacroAssembler _masm(&cbuf);
1504 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1505 assert(framesize >= 0, "negative frame-size?");
1507 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1508 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1509 const Register return_pc = R11;
1510 const Register polling_page = R12;
1512 if (!method_is_frameless) {
1513 // Restore return pc relative to callers' sp.
1514 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1515 }
1517 if (method_needs_polling) {
1518 if (LoadPollAddressFromThread) {
1519 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1520 Unimplemented();
1521 } else {
1522 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1523 }
1524 }
1526 if (!method_is_frameless) {
1527 // Move return pc to LR.
1528 __ mtlr(return_pc);
1529 // Pop frame (fixed frame-size).
1530 __ addi(R1_SP, R1_SP, (int)framesize);
1531 }
1533 if (method_needs_polling) {
1534 // We need to mark the code position where the load from the safepoint
1535 // polling page was emitted as relocInfo::poll_return_type here.
1536 __ relocate(relocInfo::poll_return_type);
1537 __ load_from_polling_page(polling_page);
1538 }
1539 }
1541 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1542 // Variable size. Determine dynamically.
1543 return MachNode::size(ra_);
1544 }
1546 int MachEpilogNode::reloc() const {
1547 // Return number of relocatable values contained in this instruction.
1548 return 1; // 1 for load_from_polling_page.
1549 }
1551 const Pipeline * MachEpilogNode::pipeline() const {
1552 return MachNode::pipeline_class();
1553 }
1555 // This method seems to be obsolete. It is declared in machnode.hpp
1556 // and defined in all *.ad files, but it is never called. Should we
1557 // get rid of it?
1558 int MachEpilogNode::safepoint_offset() const {
1559 assert(do_polling(), "no return for this epilog node");
1560 return 0;
1561 }
1563 #if 0 // TODO: PPC port
1564 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1565 MacroAssembler _masm(&cbuf);
1566 if (LoadPollAddressFromThread) {
1567 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1568 } else {
1569 _masm.nop();
1570 }
1571 }
1573 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1574 if (LoadPollAddressFromThread) {
1575 return 4;
1576 } else {
1577 return 4;
1578 }
1579 }
1581 #ifndef PRODUCT
1582 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1583 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1584 }
1585 #endif
1587 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1588 return RSCRATCH1_BITS64_REG_mask();
1589 }
1590 #endif // PPC port
1592 // =============================================================================
1594 // Figure out which register class each belongs in: rc_int, rc_float or
1595 // rc_stack.
1596 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1598 static enum RC rc_class(OptoReg::Name reg) {
1599 // Return the register class for the given register. The given register
1600 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1601 // enumeration in adGlobals_ppc64.hpp.
1603 if (reg == OptoReg::Bad) return rc_bad;
1605 // We have 64 integer register halves, starting at index 0.
1606 if (reg < 64) return rc_int;
1608 // We have 64 floating-point register halves, starting at index 64.
1609 if (reg < 64+64) return rc_float;
1611 // Between float regs & stack are the flags regs.
1612 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1614 return rc_stack;
1615 }
1617 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1618 bool do_print, Compile* C, outputStream *st) {
1620 assert(opcode == Assembler::LD_OPCODE ||
1621 opcode == Assembler::STD_OPCODE ||
1622 opcode == Assembler::LWZ_OPCODE ||
1623 opcode == Assembler::STW_OPCODE ||
1624 opcode == Assembler::LFD_OPCODE ||
1625 opcode == Assembler::STFD_OPCODE ||
1626 opcode == Assembler::LFS_OPCODE ||
1627 opcode == Assembler::STFS_OPCODE,
1628 "opcode not supported");
1630 if (cbuf) {
1631 int d =
1632 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1633 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1634 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1635 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1636 }
1637 #ifndef PRODUCT
1638 else if (do_print) {
1639 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1640 op_str,
1641 Matcher::regName[reg],
1642 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1643 }
1644 #endif
1645 return 4; // size
1646 }
1648 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1649 Compile* C = ra_->C;
1651 // Get registers to move.
1652 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1653 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1654 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1655 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1657 enum RC src_hi_rc = rc_class(src_hi);
1658 enum RC src_lo_rc = rc_class(src_lo);
1659 enum RC dst_hi_rc = rc_class(dst_hi);
1660 enum RC dst_lo_rc = rc_class(dst_lo);
1662 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1663 if (src_hi != OptoReg::Bad)
1664 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1665 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1666 "expected aligned-adjacent pairs");
1667 // Generate spill code!
1668 int size = 0;
1670 if (src_lo == dst_lo && src_hi == dst_hi)
1671 return size; // Self copy, no move.
1673 // --------------------------------------
1674 // Memory->Memory Spill. Use R0 to hold the value.
1675 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1676 int src_offset = ra_->reg2offset(src_lo);
1677 int dst_offset = ra_->reg2offset(dst_lo);
1678 if (src_hi != OptoReg::Bad) {
1679 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1680 "expected same type of move for high parts");
1681 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1682 if (!cbuf && !do_size) st->print("\n\t");
1683 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1684 } else {
1685 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1686 if (!cbuf && !do_size) st->print("\n\t");
1687 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1688 }
1689 return size;
1690 }
1692 // --------------------------------------
1693 // Check for float->int copy; requires a trip through memory.
1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1695 Unimplemented();
1696 }
1698 // --------------------------------------
1699 // Check for integer reg-reg copy.
1700 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1701 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1702 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1703 size = (Rsrc != Rdst) ? 4 : 0;
1705 if (cbuf) {
1706 MacroAssembler _masm(cbuf);
1707 if (size) {
1708 __ mr(Rdst, Rsrc);
1709 }
1710 }
1711 #ifndef PRODUCT
1712 else if (!do_size) {
1713 if (size) {
1714 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1715 } else {
1716 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1717 }
1718 }
1719 #endif
1720 return size;
1721 }
1723 // Check for integer store.
1724 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1725 int dst_offset = ra_->reg2offset(dst_lo);
1726 if (src_hi != OptoReg::Bad) {
1727 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1728 "expected same type of move for high parts");
1729 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1730 } else {
1731 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1732 }
1733 return size;
1734 }
1736 // Check for integer load.
1737 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1738 int src_offset = ra_->reg2offset(src_lo);
1739 if (src_hi != OptoReg::Bad) {
1740 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1741 "expected same type of move for high parts");
1742 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1743 } else {
1744 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1745 }
1746 return size;
1747 }
1749 // Check for float reg-reg copy.
1750 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1751 if (cbuf) {
1752 MacroAssembler _masm(cbuf);
1753 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1754 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1755 __ fmr(Rdst, Rsrc);
1756 }
1757 #ifndef PRODUCT
1758 else if (!do_size) {
1759 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1760 }
1761 #endif
1762 return 4;
1763 }
1765 // Check for float store.
1766 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1767 int dst_offset = ra_->reg2offset(dst_lo);
1768 if (src_hi != OptoReg::Bad) {
1769 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1770 "expected same type of move for high parts");
1771 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1772 } else {
1773 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1774 }
1775 return size;
1776 }
1778 // Check for float load.
1779 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1780 int src_offset = ra_->reg2offset(src_lo);
1781 if (src_hi != OptoReg::Bad) {
1782 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1783 "expected same type of move for high parts");
1784 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1785 } else {
1786 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1787 }
1788 return size;
1789 }
1791 // --------------------------------------------------------------------
1792 // Check for hi bits still needing moving. Only happens for misaligned
1793 // arguments to native calls.
1794 if (src_hi == dst_hi)
1795 return size; // Self copy; no move.
1797 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1798 ShouldNotReachHere(); // Unimplemented
1799 return 0;
1800 }
1802 #ifndef PRODUCT
1803 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1804 if (!ra_)
1805 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1806 else
1807 implementation(NULL, ra_, false, st);
1808 }
1809 #endif
1811 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1812 implementation(&cbuf, ra_, false, NULL);
1813 }
1815 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1816 return implementation(NULL, ra_, true, NULL);
1817 }
1819 #if 0 // TODO: PPC port
1820 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1821 #ifndef PRODUCT
1822 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1823 #endif
1824 assert(ra_->node_regs_max_index() != 0, "");
1826 // Get registers to move.
1827 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1828 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1829 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1830 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1832 enum RC src_lo_rc = rc_class(src_lo);
1833 enum RC dst_lo_rc = rc_class(dst_lo);
1835 if (src_lo == dst_lo && src_hi == dst_hi)
1836 return ppc64Opcode_none; // Self copy, no move.
1838 // --------------------------------------
1839 // Memory->Memory Spill. Use R0 to hold the value.
1840 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1841 return ppc64Opcode_compound;
1842 }
1844 // --------------------------------------
1845 // Check for float->int copy; requires a trip through memory.
1846 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1847 Unimplemented();
1848 }
1850 // --------------------------------------
1851 // Check for integer reg-reg copy.
1852 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1853 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1854 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1855 if (Rsrc == Rdst) {
1856 return ppc64Opcode_none;
1857 } else {
1858 return ppc64Opcode_or;
1859 }
1860 }
1862 // Check for integer store.
1863 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1864 if (src_hi != OptoReg::Bad) {
1865 return ppc64Opcode_std;
1866 } else {
1867 return ppc64Opcode_stw;
1868 }
1869 }
1871 // Check for integer load.
1872 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1873 if (src_hi != OptoReg::Bad) {
1874 return ppc64Opcode_ld;
1875 } else {
1876 return ppc64Opcode_lwz;
1877 }
1878 }
1880 // Check for float reg-reg copy.
1881 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1882 return ppc64Opcode_fmr;
1883 }
1885 // Check for float store.
1886 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1887 if (src_hi != OptoReg::Bad) {
1888 return ppc64Opcode_stfd;
1889 } else {
1890 return ppc64Opcode_stfs;
1891 }
1892 }
1894 // Check for float load.
1895 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1896 if (src_hi != OptoReg::Bad) {
1897 return ppc64Opcode_lfd;
1898 } else {
1899 return ppc64Opcode_lfs;
1900 }
1901 }
1903 // --------------------------------------------------------------------
1904 // Check for hi bits still needing moving. Only happens for misaligned
1905 // arguments to native calls.
1906 if (src_hi == dst_hi)
1907 return ppc64Opcode_none; // Self copy; no move.
1909 ShouldNotReachHere();
1910 return ppc64Opcode_undefined;
1911 }
1912 #endif // PPC port
1914 #ifndef PRODUCT
1915 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1916 st->print("NOP \t// %d nops to pad for loops.", _count);
1917 }
1918 #endif
1920 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1921 MacroAssembler _masm(&cbuf);
1922 // _count contains the number of nops needed for padding.
1923 for (int i = 0; i < _count; i++) {
1924 __ nop();
1925 }
1926 }
1928 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1929 return _count * 4;
1930 }
1932 #ifndef PRODUCT
1933 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1934 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1935 int reg = ra_->get_reg_first(this);
1936 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1937 }
1938 #endif
1940 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1941 MacroAssembler _masm(&cbuf);
1943 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1944 int reg = ra_->get_encode(this);
1946 if (Assembler::is_simm(offset, 16)) {
1947 __ addi(as_Register(reg), R1, offset);
1948 } else {
1949 ShouldNotReachHere();
1950 }
1951 }
1953 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1954 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1955 return 4;
1956 }
1958 #ifndef PRODUCT
1959 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1960 st->print_cr("---- MachUEPNode ----");
1961 st->print_cr("...");
1962 }
1963 #endif
1965 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1966 // This is the unverified entry point.
1967 MacroAssembler _masm(&cbuf);
1969 // Inline_cache contains a klass.
1970 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1971 Register receiver_klass = R0; // tmp
1973 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1974 assert(R11_scratch1 == R11, "need prologue scratch register");
1976 // Check for NULL argument if we don't have implicit null checks.
1977 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1978 if (TrapBasedNullChecks) {
1979 __ trap_null_check(R3_ARG1);
1980 } else {
1981 Label valid;
1982 __ cmpdi(CCR0, R3_ARG1, 0);
1983 __ bne_predict_taken(CCR0, valid);
1984 // We have a null argument, branch to ic_miss_stub.
1985 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1986 relocInfo::runtime_call_type);
1987 __ bind(valid);
1988 }
1989 }
1990 // Assume argument is not NULL, load klass from receiver.
1991 __ load_klass(receiver_klass, R3_ARG1);
1993 if (TrapBasedICMissChecks) {
1994 __ trap_ic_miss_check(receiver_klass, ic_klass);
1995 } else {
1996 Label valid;
1997 __ cmpd(CCR0, receiver_klass, ic_klass);
1998 __ beq_predict_taken(CCR0, valid);
1999 // We have an unexpected klass, branch to ic_miss_stub.
2000 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2001 relocInfo::runtime_call_type);
2002 __ bind(valid);
2003 }
2005 // Argument is valid and klass is as expected, continue.
2006 }
2008 #if 0 // TODO: PPC port
2009 // Optimize UEP code on z (save a load_const() call in main path).
2010 int MachUEPNode::ep_offset() {
2011 return 0;
2012 }
2013 #endif
2015 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2016 // Variable size. Determine dynamically.
2017 return MachNode::size(ra_);
2018 }
2020 //=============================================================================
2022 uint size_exception_handler() {
2023 // The exception_handler is a b64_patchable.
2024 return MacroAssembler::b64_patchable_size;
2025 }
2027 uint size_deopt_handler() {
2028 // The deopt_handler is a bl64_patchable.
2029 return MacroAssembler::bl64_patchable_size;
2030 }
2032 int emit_exception_handler(CodeBuffer &cbuf) {
2033 MacroAssembler _masm(&cbuf);
2035 address base = __ start_a_stub(size_exception_handler());
2036 if (base == NULL) return 0; // CodeBuffer::expand failed
2038 int offset = __ offset();
2039 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2040 relocInfo::runtime_call_type);
2041 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2042 __ end_a_stub();
2044 return offset;
2045 }
2047 // The deopt_handler is like the exception handler, but it calls to
2048 // the deoptimization blob instead of jumping to the exception blob.
2049 int emit_deopt_handler(CodeBuffer& cbuf) {
2050 MacroAssembler _masm(&cbuf);
2052 address base = __ start_a_stub(size_deopt_handler());
2053 if (base == NULL) return 0; // CodeBuffer::expand failed
2055 int offset = __ offset();
2056 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2057 relocInfo::runtime_call_type);
2058 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2059 __ end_a_stub();
2061 return offset;
2062 }
2064 //=============================================================================
2066 // Use a frame slots bias for frameless methods if accessing the stack.
2067 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2068 if (as_Register(reg_enc) == R1_SP) {
2069 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2070 }
2071 return 0;
2072 }
2074 const bool Matcher::match_rule_supported(int opcode) {
2075 if (!has_match_rule(opcode))
2076 return false;
2078 switch (opcode) {
2079 case Op_CountLeadingZerosI:
2080 case Op_CountLeadingZerosL:
2081 case Op_CountTrailingZerosI:
2082 case Op_CountTrailingZerosL:
2083 if (!UseCountLeadingZerosInstructionsPPC64)
2084 return false;
2085 break;
2087 case Op_PopCountI:
2088 case Op_PopCountL:
2089 return (UsePopCountInstruction && VM_Version::has_popcntw());
2091 case Op_StrComp:
2092 return SpecialStringCompareTo;
2093 case Op_StrEquals:
2094 return SpecialStringEquals;
2095 case Op_StrIndexOf:
2096 return SpecialStringIndexOf;
2097 }
2099 return true; // Per default match rules are supported.
2100 }
2102 int Matcher::regnum_to_fpu_offset(int regnum) {
2103 // No user for this method?
2104 Unimplemented();
2105 return 999;
2106 }
2108 const bool Matcher::convL2FSupported(void) {
2109 // fcfids can do the conversion (>= Power7).
2110 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2111 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2112 }
2114 // Vector width in bytes.
2115 const int Matcher::vector_width_in_bytes(BasicType bt) {
2116 assert(MaxVectorSize == 8, "");
2117 return 8;
2118 }
2120 // Vector ideal reg.
2121 const int Matcher::vector_ideal_reg(int size) {
2122 assert(MaxVectorSize == 8 && size == 8, "");
2123 return Op_RegL;
2124 }
2126 const int Matcher::vector_shift_count_ideal_reg(int size) {
2127 fatal("vector shift is not supported");
2128 return Node::NotAMachineReg;
2129 }
2131 // Limits on vector size (number of elements) loaded into vector.
2132 const int Matcher::max_vector_size(const BasicType bt) {
2133 assert(is_java_primitive(bt), "only primitive type vectors");
2134 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2135 }
2137 const int Matcher::min_vector_size(const BasicType bt) {
2138 return max_vector_size(bt); // Same as max.
2139 }
2141 // PPC doesn't support misaligned vectors store/load.
2142 const bool Matcher::misaligned_vectors_ok() {
2143 return false;
2144 }
2146 // PPC AES support not yet implemented
2147 const bool Matcher::pass_original_key_for_aes() {
2148 return false;
2149 }
2151 // RETURNS: whether this branch offset is short enough that a short
2152 // branch can be used.
2153 //
2154 // If the platform does not provide any short branch variants, then
2155 // this method should return `false' for offset 0.
2156 //
2157 // `Compile::Fill_buffer' will decide on basis of this information
2158 // whether to do the pass `Compile::Shorten_branches' at all.
2159 //
2160 // And `Compile::Shorten_branches' will decide on basis of this
2161 // information whether to replace particular branch sites by short
2162 // ones.
2163 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2164 // Is the offset within the range of a ppc64 pc relative branch?
2165 bool b;
2167 const int safety_zone = 3 * BytesPerInstWord;
2168 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2169 29 - 16 + 1 + 2);
2170 return b;
2171 }
2173 const bool Matcher::isSimpleConstant64(jlong value) {
2174 // Probably always true, even if a temp register is required.
2175 return true;
2176 }
2177 /* TODO: PPC port
2178 // Make a new machine dependent decode node (with its operands).
2179 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2180 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2181 "This method is only implemented for unscaled cOops mode so far");
2182 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2183 decode->set_opnd_array(0, new (C) iRegPdstOper());
2184 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2185 return decode;
2186 }
2187 */
2188 // Threshold size for cleararray.
2189 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2191 // false => size gets scaled to BytesPerLong, ok.
2192 const bool Matcher::init_array_count_is_in_bytes = false;
2194 // Use conditional move (CMOVL) on Power7.
2195 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2197 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2198 // fsel doesn't accept a condition register as input, so this would be slightly different.
2199 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2201 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2202 const bool Matcher::require_postalloc_expand = true;
2204 // Should the Matcher clone shifts on addressing modes, expecting them to
2205 // be subsumed into complex addressing expressions or compute them into
2206 // registers? True for Intel but false for most RISCs.
2207 const bool Matcher::clone_shift_expressions = false;
2209 // Do we need to mask the count passed to shift instructions or does
2210 // the cpu only look at the lower 5/6 bits anyway?
2211 // Off, as masks are generated in expand rules where required.
2212 // Constant shift counts are handled in Ideal phase.
2213 const bool Matcher::need_masked_shift_count = false;
2215 // This affects two different things:
2216 // - how Decode nodes are matched
2217 // - how ImplicitNullCheck opportunities are recognized
2218 // If true, the matcher will try to remove all Decodes and match them
2219 // (as operands) into nodes. NullChecks are not prepared to deal with
2220 // Decodes by final_graph_reshaping().
2221 // If false, final_graph_reshaping() forces the decode behind the Cmp
2222 // for a NullCheck. The matcher matches the Decode node into a register.
2223 // Implicit_null_check optimization moves the Decode along with the
2224 // memory operation back up before the NullCheck.
2225 bool Matcher::narrow_oop_use_complex_address() {
2226 // TODO: PPC port if (MatchDecodeNodes) return true;
2227 return false;
2228 }
2230 bool Matcher::narrow_klass_use_complex_address() {
2231 NOT_LP64(ShouldNotCallThis());
2232 assert(UseCompressedClassPointers, "only for compressed klass code");
2233 // TODO: PPC port if (MatchDecodeNodes) return true;
2234 return false;
2235 }
2237 // Is it better to copy float constants, or load them directly from memory?
2238 // Intel can load a float constant from a direct address, requiring no
2239 // extra registers. Most RISCs will have to materialize an address into a
2240 // register first, so they would do better to copy the constant from stack.
2241 const bool Matcher::rematerialize_float_constants = false;
2243 // If CPU can load and store mis-aligned doubles directly then no fixup is
2244 // needed. Else we split the double into 2 integer pieces and move it
2245 // piece-by-piece. Only happens when passing doubles into C code as the
2246 // Java calling convention forces doubles to be aligned.
2247 const bool Matcher::misaligned_doubles_ok = true;
2249 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2250 Unimplemented();
2251 }
2253 // Advertise here if the CPU requires explicit rounding operations
2254 // to implement the UseStrictFP mode.
2255 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2257 // Do floats take an entire double register or just half?
2258 //
2259 // A float occupies a ppc64 double register. For the allocator, a
2260 // ppc64 double register appears as a pair of float registers.
2261 bool Matcher::float_in_double() { return true; }
2263 // Do ints take an entire long register or just half?
2264 // The relevant question is how the int is callee-saved:
2265 // the whole long is written but de-opt'ing will have to extract
2266 // the relevant 32 bits.
2267 const bool Matcher::int_in_long = true;
2269 // Constants for c2c and c calling conventions.
2271 const MachRegisterNumbers iarg_reg[8] = {
2272 R3_num, R4_num, R5_num, R6_num,
2273 R7_num, R8_num, R9_num, R10_num
2274 };
2276 const MachRegisterNumbers farg_reg[13] = {
2277 F1_num, F2_num, F3_num, F4_num,
2278 F5_num, F6_num, F7_num, F8_num,
2279 F9_num, F10_num, F11_num, F12_num,
2280 F13_num
2281 };
2283 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2285 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2287 // Return whether or not this register is ever used as an argument. This
2288 // function is used on startup to build the trampoline stubs in generateOptoStub.
2289 // Registers not mentioned will be killed by the VM call in the trampoline, and
2290 // arguments in those registers not be available to the callee.
2291 bool Matcher::can_be_java_arg(int reg) {
2292 // We return true for all registers contained in iarg_reg[] and
2293 // farg_reg[] and their virtual halves.
2294 // We must include the virtual halves in order to get STDs and LDs
2295 // instead of STWs and LWs in the trampoline stubs.
2297 if ( reg == R3_num || reg == R3_H_num
2298 || reg == R4_num || reg == R4_H_num
2299 || reg == R5_num || reg == R5_H_num
2300 || reg == R6_num || reg == R6_H_num
2301 || reg == R7_num || reg == R7_H_num
2302 || reg == R8_num || reg == R8_H_num
2303 || reg == R9_num || reg == R9_H_num
2304 || reg == R10_num || reg == R10_H_num)
2305 return true;
2307 if ( reg == F1_num || reg == F1_H_num
2308 || reg == F2_num || reg == F2_H_num
2309 || reg == F3_num || reg == F3_H_num
2310 || reg == F4_num || reg == F4_H_num
2311 || reg == F5_num || reg == F5_H_num
2312 || reg == F6_num || reg == F6_H_num
2313 || reg == F7_num || reg == F7_H_num
2314 || reg == F8_num || reg == F8_H_num
2315 || reg == F9_num || reg == F9_H_num
2316 || reg == F10_num || reg == F10_H_num
2317 || reg == F11_num || reg == F11_H_num
2318 || reg == F12_num || reg == F12_H_num
2319 || reg == F13_num || reg == F13_H_num)
2320 return true;
2322 return false;
2323 }
2325 bool Matcher::is_spillable_arg(int reg) {
2326 return can_be_java_arg(reg);
2327 }
2329 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2330 return false;
2331 }
2333 // Register for DIVI projection of divmodI.
2334 RegMask Matcher::divI_proj_mask() {
2335 ShouldNotReachHere();
2336 return RegMask();
2337 }
2339 // Register for MODI projection of divmodI.
2340 RegMask Matcher::modI_proj_mask() {
2341 ShouldNotReachHere();
2342 return RegMask();
2343 }
2345 // Register for DIVL projection of divmodL.
2346 RegMask Matcher::divL_proj_mask() {
2347 ShouldNotReachHere();
2348 return RegMask();
2349 }
2351 // Register for MODL projection of divmodL.
2352 RegMask Matcher::modL_proj_mask() {
2353 ShouldNotReachHere();
2354 return RegMask();
2355 }
2357 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2358 return RegMask();
2359 }
2361 const RegMask Matcher::mathExactI_result_proj_mask() {
2362 return RARG4_BITS64_REG_mask();
2363 }
2365 const RegMask Matcher::mathExactL_result_proj_mask() {
2366 return RARG4_BITS64_REG_mask();
2367 }
2369 const RegMask Matcher::mathExactI_flags_proj_mask() {
2370 return INT_FLAGS_mask();
2371 }
2373 %}
2375 //----------ENCODING BLOCK-----------------------------------------------------
2376 // This block specifies the encoding classes used by the compiler to output
2377 // byte streams. Encoding classes are parameterized macros used by
2378 // Machine Instruction Nodes in order to generate the bit encoding of the
2379 // instruction. Operands specify their base encoding interface with the
2380 // interface keyword. There are currently supported four interfaces,
2381 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2382 // operand to generate a function which returns its register number when
2383 // queried. CONST_INTER causes an operand to generate a function which
2384 // returns the value of the constant when queried. MEMORY_INTER causes an
2385 // operand to generate four functions which return the Base Register, the
2386 // Index Register, the Scale Value, and the Offset Value of the operand when
2387 // queried. COND_INTER causes an operand to generate six functions which
2388 // return the encoding code (ie - encoding bits for the instruction)
2389 // associated with each basic boolean condition for a conditional instruction.
2390 //
2391 // Instructions specify two basic values for encoding. Again, a function
2392 // is available to check if the constant displacement is an oop. They use the
2393 // ins_encode keyword to specify their encoding classes (which must be
2394 // a sequence of enc_class names, and their parameters, specified in
2395 // the encoding block), and they use the
2396 // opcode keyword to specify, in order, their primary, secondary, and
2397 // tertiary opcode. Only the opcode sections which a particular instruction
2398 // needs for encoding need to be specified.
2399 encode %{
2400 enc_class enc_unimplemented %{
2401 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2402 MacroAssembler _masm(&cbuf);
2403 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2404 %}
2406 enc_class enc_untested %{
2407 #ifdef ASSERT
2408 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2409 MacroAssembler _masm(&cbuf);
2410 __ untested("Untested mach node encoding in AD file.");
2411 #else
2412 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2413 #endif
2414 %}
2416 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2417 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2418 MacroAssembler _masm(&cbuf);
2419 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2420 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2421 %}
2423 // Load acquire.
2424 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2425 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2426 MacroAssembler _masm(&cbuf);
2427 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2428 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2429 __ twi_0($dst$$Register);
2430 __ isync();
2431 %}
2433 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2434 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2436 MacroAssembler _masm(&cbuf);
2437 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2438 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2439 %}
2441 // Load acquire.
2442 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2443 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2445 MacroAssembler _masm(&cbuf);
2446 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2447 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2448 __ twi_0($dst$$Register);
2449 __ isync();
2450 %}
2452 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2453 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2455 MacroAssembler _masm(&cbuf);
2456 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2457 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2458 %}
2460 // Load acquire.
2461 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2462 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2464 MacroAssembler _masm(&cbuf);
2465 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2466 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2467 __ twi_0($dst$$Register);
2468 __ isync();
2469 %}
2471 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2472 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2473 MacroAssembler _masm(&cbuf);
2474 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2475 // Operand 'ds' requires 4-alignment.
2476 assert((Idisp & 0x3) == 0, "unaligned offset");
2477 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2478 %}
2480 // Load acquire.
2481 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2482 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2483 MacroAssembler _masm(&cbuf);
2484 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2485 // Operand 'ds' requires 4-alignment.
2486 assert((Idisp & 0x3) == 0, "unaligned offset");
2487 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2488 __ twi_0($dst$$Register);
2489 __ isync();
2490 %}
2492 enc_class enc_lfd(RegF dst, memory mem) %{
2493 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2494 MacroAssembler _masm(&cbuf);
2495 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2496 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2497 %}
2499 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2500 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2502 MacroAssembler _masm(&cbuf);
2503 int toc_offset = 0;
2505 if (!ra_->C->in_scratch_emit_size()) {
2506 address const_toc_addr;
2507 // Create a non-oop constant, no relocation needed.
2508 // If it is an IC, it has a virtual_call_Relocation.
2509 const_toc_addr = __ long_constant((jlong)$src$$constant);
2511 // Get the constant's TOC offset.
2512 toc_offset = __ offset_to_method_toc(const_toc_addr);
2514 // Keep the current instruction offset in mind.
2515 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2516 }
2518 __ ld($dst$$Register, toc_offset, $toc$$Register);
2519 %}
2521 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2522 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2524 MacroAssembler _masm(&cbuf);
2526 if (!ra_->C->in_scratch_emit_size()) {
2527 address const_toc_addr;
2528 // Create a non-oop constant, no relocation needed.
2529 // If it is an IC, it has a virtual_call_Relocation.
2530 const_toc_addr = __ long_constant((jlong)$src$$constant);
2532 // Get the constant's TOC offset.
2533 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2534 // Store the toc offset of the constant.
2535 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2537 // Also keep the current instruction offset in mind.
2538 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2539 }
2541 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2542 %}
2544 %} // encode
2546 source %{
2548 typedef struct {
2549 loadConL_hiNode *_large_hi;
2550 loadConL_loNode *_large_lo;
2551 loadConLNode *_small;
2552 MachNode *_last;
2553 } loadConLNodesTuple;
2555 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2556 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2557 loadConLNodesTuple nodes;
2559 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2560 if (large_constant_pool) {
2561 // Create new nodes.
2562 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2563 loadConL_loNode *m2 = new (C) loadConL_loNode();
2565 // inputs for new nodes
2566 m1->add_req(NULL, toc);
2567 m2->add_req(NULL, m1);
2569 // operands for new nodes
2570 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2571 m1->_opnds[1] = immSrc; // src
2572 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2573 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2574 m2->_opnds[1] = immSrc; // src
2575 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2577 // Initialize ins_attrib TOC fields.
2578 m1->_const_toc_offset = -1;
2579 m2->_const_toc_offset_hi_node = m1;
2581 // Initialize ins_attrib instruction offset.
2582 m1->_cbuf_insts_offset = -1;
2584 // register allocation for new nodes
2585 ra_->set_pair(m1->_idx, reg_second, reg_first);
2586 ra_->set_pair(m2->_idx, reg_second, reg_first);
2588 // Create result.
2589 nodes._large_hi = m1;
2590 nodes._large_lo = m2;
2591 nodes._small = NULL;
2592 nodes._last = nodes._large_lo;
2593 assert(m2->bottom_type()->isa_long(), "must be long");
2594 } else {
2595 loadConLNode *m2 = new (C) loadConLNode();
2597 // inputs for new nodes
2598 m2->add_req(NULL, toc);
2600 // operands for new nodes
2601 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2602 m2->_opnds[1] = immSrc; // src
2603 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2605 // Initialize ins_attrib instruction offset.
2606 m2->_cbuf_insts_offset = -1;
2608 // register allocation for new nodes
2609 ra_->set_pair(m2->_idx, reg_second, reg_first);
2611 // Create result.
2612 nodes._large_hi = NULL;
2613 nodes._large_lo = NULL;
2614 nodes._small = m2;
2615 nodes._last = nodes._small;
2616 assert(m2->bottom_type()->isa_long(), "must be long");
2617 }
2619 return nodes;
2620 }
2622 %} // source
2624 encode %{
2625 // Postalloc expand emitter for loading a long constant from the method's TOC.
2626 // Enc_class needed as consttanttablebase is not supported by postalloc
2627 // expand.
2628 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2629 // Create new nodes.
2630 loadConLNodesTuple loadConLNodes =
2631 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2632 ra_->get_reg_second(this), ra_->get_reg_first(this));
2634 // Push new nodes.
2635 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2636 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2638 // some asserts
2639 assert(nodes->length() >= 1, "must have created at least 1 node");
2640 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2641 %}
2643 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2644 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2646 MacroAssembler _masm(&cbuf);
2647 int toc_offset = 0;
2649 if (!ra_->C->in_scratch_emit_size()) {
2650 intptr_t val = $src$$constant;
2651 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2652 address const_toc_addr;
2653 if (constant_reloc == relocInfo::oop_type) {
2654 // Create an oop constant and a corresponding relocation.
2655 AddressLiteral a = __ allocate_oop_address((jobject)val);
2656 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2657 __ relocate(a.rspec());
2658 } else if (constant_reloc == relocInfo::metadata_type) {
2659 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2660 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2661 __ relocate(a.rspec());
2662 } else {
2663 // Create a non-oop constant, no relocation needed.
2664 const_toc_addr = __ long_constant((jlong)$src$$constant);
2665 }
2667 // Get the constant's TOC offset.
2668 toc_offset = __ offset_to_method_toc(const_toc_addr);
2669 }
2671 __ ld($dst$$Register, toc_offset, $toc$$Register);
2672 %}
2674 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2675 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2677 MacroAssembler _masm(&cbuf);
2678 if (!ra_->C->in_scratch_emit_size()) {
2679 intptr_t val = $src$$constant;
2680 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2681 address const_toc_addr;
2682 if (constant_reloc == relocInfo::oop_type) {
2683 // Create an oop constant and a corresponding relocation.
2684 AddressLiteral a = __ allocate_oop_address((jobject)val);
2685 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2686 __ relocate(a.rspec());
2687 } else if (constant_reloc == relocInfo::metadata_type) {
2688 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2689 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2690 __ relocate(a.rspec());
2691 } else { // non-oop pointers, e.g. card mark base, heap top
2692 // Create a non-oop constant, no relocation needed.
2693 const_toc_addr = __ long_constant((jlong)$src$$constant);
2694 }
2696 // Get the constant's TOC offset.
2697 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2698 // Store the toc offset of the constant.
2699 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2700 }
2702 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2703 %}
2705 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2706 // Enc_class needed as consttanttablebase is not supported by postalloc
2707 // expand.
2708 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2709 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2710 if (large_constant_pool) {
2711 // Create new nodes.
2712 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2713 loadConP_loNode *m2 = new (C) loadConP_loNode();
2715 // inputs for new nodes
2716 m1->add_req(NULL, n_toc);
2717 m2->add_req(NULL, m1);
2719 // operands for new nodes
2720 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2721 m1->_opnds[1] = op_src; // src
2722 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2723 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2724 m2->_opnds[1] = op_src; // src
2725 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2727 // Initialize ins_attrib TOC fields.
2728 m1->_const_toc_offset = -1;
2729 m2->_const_toc_offset_hi_node = m1;
2731 // Register allocation for new nodes.
2732 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2733 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2735 nodes->push(m1);
2736 nodes->push(m2);
2737 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2738 } else {
2739 loadConPNode *m2 = new (C) loadConPNode();
2741 // inputs for new nodes
2742 m2->add_req(NULL, n_toc);
2744 // operands for new nodes
2745 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2746 m2->_opnds[1] = op_src; // src
2747 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2749 // Register allocation for new nodes.
2750 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2752 nodes->push(m2);
2753 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2754 }
2755 %}
2757 // Enc_class needed as consttanttablebase is not supported by postalloc
2758 // expand.
2759 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2760 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2762 MachNode *m2;
2763 if (large_constant_pool) {
2764 m2 = new (C) loadConFCompNode();
2765 } else {
2766 m2 = new (C) loadConFNode();
2767 }
2768 // inputs for new nodes
2769 m2->add_req(NULL, n_toc);
2771 // operands for new nodes
2772 m2->_opnds[0] = op_dst;
2773 m2->_opnds[1] = op_src;
2774 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2776 // register allocation for new nodes
2777 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2778 nodes->push(m2);
2779 %}
2781 // Enc_class needed as consttanttablebase is not supported by postalloc
2782 // expand.
2783 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2784 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2786 MachNode *m2;
2787 if (large_constant_pool) {
2788 m2 = new (C) loadConDCompNode();
2789 } else {
2790 m2 = new (C) loadConDNode();
2791 }
2792 // inputs for new nodes
2793 m2->add_req(NULL, n_toc);
2795 // operands for new nodes
2796 m2->_opnds[0] = op_dst;
2797 m2->_opnds[1] = op_src;
2798 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2800 // register allocation for new nodes
2801 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2802 nodes->push(m2);
2803 %}
2805 enc_class enc_stw(iRegIsrc src, memory mem) %{
2806 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2807 MacroAssembler _masm(&cbuf);
2808 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2809 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2810 %}
2812 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2813 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2814 MacroAssembler _masm(&cbuf);
2815 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2816 // Operand 'ds' requires 4-alignment.
2817 assert((Idisp & 0x3) == 0, "unaligned offset");
2818 __ std($src$$Register, Idisp, $mem$$base$$Register);
2819 %}
2821 enc_class enc_stfs(RegF src, memory mem) %{
2822 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2823 MacroAssembler _masm(&cbuf);
2824 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2825 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2826 %}
2828 enc_class enc_stfd(RegF src, memory mem) %{
2829 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2830 MacroAssembler _masm(&cbuf);
2831 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2832 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2833 %}
2835 // Use release_store for card-marking to ensure that previous
2836 // oop-stores are visible before the card-mark change.
2837 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2838 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2839 // FIXME: Implement this as a cmove and use a fixed condition code
2840 // register which is written on every transition to compiled code,
2841 // e.g. in call-stub and when returning from runtime stubs.
2842 //
2843 // Proposed code sequence for the cmove implementation:
2844 //
2845 // Label skip_release;
2846 // __ beq(CCRfixed, skip_release);
2847 // __ release();
2848 // __ bind(skip_release);
2849 // __ stb(card mark);
2851 MacroAssembler _masm(&cbuf);
2852 Label skip_storestore;
2854 #if 0 // TODO: PPC port
2855 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2856 // StoreStore barrier conditionally.
2857 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2858 __ cmpwi(CCR0, R0, 0);
2859 __ beq_predict_taken(CCR0, skip_storestore);
2860 #endif
2861 __ li(R0, 0);
2862 __ membar(Assembler::StoreStore);
2863 #if 0 // TODO: PPC port
2864 __ bind(skip_storestore);
2865 #endif
2867 // Do the store.
2868 if ($mem$$index == 0) {
2869 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2870 } else {
2871 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2872 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2873 }
2874 %}
2876 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2878 if (VM_Version::has_isel()) {
2879 // use isel instruction with Power 7
2880 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2881 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2882 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2883 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2885 n_compare->add_req(n_region, n_src);
2886 n_compare->_opnds[0] = op_crx;
2887 n_compare->_opnds[1] = op_src;
2888 n_compare->_opnds[2] = new (C) immL16Oper(0);
2890 n_sub_base->add_req(n_region, n_src);
2891 n_sub_base->_opnds[0] = op_dst;
2892 n_sub_base->_opnds[1] = op_src;
2893 n_sub_base->_bottom_type = _bottom_type;
2895 n_shift->add_req(n_region, n_sub_base);
2896 n_shift->_opnds[0] = op_dst;
2897 n_shift->_opnds[1] = op_dst;
2898 n_shift->_bottom_type = _bottom_type;
2900 n_cond_set->add_req(n_region, n_compare, n_shift);
2901 n_cond_set->_opnds[0] = op_dst;
2902 n_cond_set->_opnds[1] = op_crx;
2903 n_cond_set->_opnds[2] = op_dst;
2904 n_cond_set->_bottom_type = _bottom_type;
2906 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2907 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2908 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2909 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2911 nodes->push(n_compare);
2912 nodes->push(n_sub_base);
2913 nodes->push(n_shift);
2914 nodes->push(n_cond_set);
2916 } else {
2917 // before Power 7
2918 moveRegNode *n_move = new (C) moveRegNode();
2919 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2920 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2921 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2923 n_move->add_req(n_region, n_src);
2924 n_move->_opnds[0] = op_dst;
2925 n_move->_opnds[1] = op_src;
2926 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2928 n_compare->add_req(n_region, n_src);
2929 n_compare->add_prec(n_move);
2931 n_compare->_opnds[0] = op_crx;
2932 n_compare->_opnds[1] = op_src;
2933 n_compare->_opnds[2] = new (C) immL16Oper(0);
2935 n_sub_base->add_req(n_region, n_compare, n_src);
2936 n_sub_base->_opnds[0] = op_dst;
2937 n_sub_base->_opnds[1] = op_crx;
2938 n_sub_base->_opnds[2] = op_src;
2939 n_sub_base->_bottom_type = _bottom_type;
2941 n_shift->add_req(n_region, n_sub_base);
2942 n_shift->_opnds[0] = op_dst;
2943 n_shift->_opnds[1] = op_dst;
2944 n_shift->_bottom_type = _bottom_type;
2946 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2947 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2948 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2949 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2951 nodes->push(n_move);
2952 nodes->push(n_compare);
2953 nodes->push(n_sub_base);
2954 nodes->push(n_shift);
2955 }
2957 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2958 %}
2960 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2962 encodeP_subNode *n1 = new (C) encodeP_subNode();
2963 n1->add_req(n_region, n_src);
2964 n1->_opnds[0] = op_dst;
2965 n1->_opnds[1] = op_src;
2966 n1->_bottom_type = _bottom_type;
2968 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
2969 n2->add_req(n_region, n1);
2970 n2->_opnds[0] = op_dst;
2971 n2->_opnds[1] = op_dst;
2972 n2->_bottom_type = _bottom_type;
2973 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2974 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2976 nodes->push(n1);
2977 nodes->push(n2);
2978 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2979 %}
2981 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2982 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
2983 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
2985 n_compare->add_req(n_region, n_src);
2986 n_compare->_opnds[0] = op_crx;
2987 n_compare->_opnds[1] = op_src;
2988 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
2990 n_shift->add_req(n_region, n_src);
2991 n_shift->_opnds[0] = op_dst;
2992 n_shift->_opnds[1] = op_src;
2993 n_shift->_bottom_type = _bottom_type;
2995 if (VM_Version::has_isel()) {
2996 // use isel instruction with Power 7
2998 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
2999 n_add_base->add_req(n_region, n_shift);
3000 n_add_base->_opnds[0] = op_dst;
3001 n_add_base->_opnds[1] = op_dst;
3002 n_add_base->_bottom_type = _bottom_type;
3004 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3005 n_cond_set->add_req(n_region, n_compare, n_add_base);
3006 n_cond_set->_opnds[0] = op_dst;
3007 n_cond_set->_opnds[1] = op_crx;
3008 n_cond_set->_opnds[2] = op_dst;
3009 n_cond_set->_bottom_type = _bottom_type;
3011 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3012 ra_->set_oop(n_cond_set, true);
3014 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3015 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3016 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3019 nodes->push(n_compare);
3020 nodes->push(n_shift);
3021 nodes->push(n_add_base);
3022 nodes->push(n_cond_set);
3024 } else {
3025 // before Power 7
3026 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3028 n_add_base->add_req(n_region, n_compare, n_shift);
3029 n_add_base->_opnds[0] = op_dst;
3030 n_add_base->_opnds[1] = op_crx;
3031 n_add_base->_opnds[2] = op_dst;
3032 n_add_base->_bottom_type = _bottom_type;
3034 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3035 ra_->set_oop(n_add_base, true);
3037 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3038 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3039 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3041 nodes->push(n_compare);
3042 nodes->push(n_shift);
3043 nodes->push(n_add_base);
3044 }
3045 %}
3047 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3048 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3049 n1->add_req(n_region, n_src);
3050 n1->_opnds[0] = op_dst;
3051 n1->_opnds[1] = op_src;
3052 n1->_bottom_type = _bottom_type;
3054 decodeN_addNode *n2 = new (C) decodeN_addNode();
3055 n2->add_req(n_region, n1);
3056 n2->_opnds[0] = op_dst;
3057 n2->_opnds[1] = op_dst;
3058 n2->_bottom_type = _bottom_type;
3059 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3060 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3062 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3063 ra_->set_oop(n2, true);
3065 nodes->push(n1);
3066 nodes->push(n2);
3067 %}
3069 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3070 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3072 MacroAssembler _masm(&cbuf);
3073 int cc = $cmp$$cmpcode;
3074 int flags_reg = $crx$$reg;
3075 Label done;
3076 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3077 // Branch if not (cmp crx).
3078 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3079 __ mr($dst$$Register, $src$$Register);
3080 // TODO PPC port __ endgroup_if_needed(_size == 12);
3081 __ bind(done);
3082 %}
3084 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3085 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3087 MacroAssembler _masm(&cbuf);
3088 Label done;
3089 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3090 // Branch if not (cmp crx).
3091 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3092 __ li($dst$$Register, $src$$constant);
3093 // TODO PPC port __ endgroup_if_needed(_size == 12);
3094 __ bind(done);
3095 %}
3097 // New atomics.
3098 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3099 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3101 MacroAssembler _masm(&cbuf);
3102 Register Rtmp = R0;
3103 Register Rres = $res$$Register;
3104 Register Rsrc = $src$$Register;
3105 Register Rptr = $mem_ptr$$Register;
3106 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3107 Register Rold = RegCollision ? Rtmp : Rres;
3109 Label Lretry;
3110 __ bind(Lretry);
3111 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3112 __ add(Rtmp, Rsrc, Rold);
3113 __ stwcx_(Rtmp, Rptr);
3114 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3115 __ bne_predict_not_taken(CCR0, Lretry);
3116 } else {
3117 __ bne( CCR0, Lretry);
3118 }
3119 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3120 __ fence();
3121 %}
3123 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3124 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3126 MacroAssembler _masm(&cbuf);
3127 Register Rtmp = R0;
3128 Register Rres = $res$$Register;
3129 Register Rsrc = $src$$Register;
3130 Register Rptr = $mem_ptr$$Register;
3131 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3132 Register Rold = RegCollision ? Rtmp : Rres;
3134 Label Lretry;
3135 __ bind(Lretry);
3136 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3137 __ add(Rtmp, Rsrc, Rold);
3138 __ stdcx_(Rtmp, Rptr);
3139 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3140 __ bne_predict_not_taken(CCR0, Lretry);
3141 } else {
3142 __ bne( CCR0, Lretry);
3143 }
3144 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3145 __ fence();
3146 %}
3148 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3149 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3151 MacroAssembler _masm(&cbuf);
3152 Register Rtmp = R0;
3153 Register Rres = $res$$Register;
3154 Register Rsrc = $src$$Register;
3155 Register Rptr = $mem_ptr$$Register;
3156 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3157 Register Rold = RegCollision ? Rtmp : Rres;
3159 Label Lretry;
3160 __ bind(Lretry);
3161 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3162 __ stwcx_(Rsrc, Rptr);
3163 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3164 __ bne_predict_not_taken(CCR0, Lretry);
3165 } else {
3166 __ bne( CCR0, Lretry);
3167 }
3168 if (RegCollision) __ mr(Rres, Rtmp);
3169 __ fence();
3170 %}
3172 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3173 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3175 MacroAssembler _masm(&cbuf);
3176 Register Rtmp = R0;
3177 Register Rres = $res$$Register;
3178 Register Rsrc = $src$$Register;
3179 Register Rptr = $mem_ptr$$Register;
3180 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3181 Register Rold = RegCollision ? Rtmp : Rres;
3183 Label Lretry;
3184 __ bind(Lretry);
3185 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3186 __ stdcx_(Rsrc, Rptr);
3187 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3188 __ bne_predict_not_taken(CCR0, Lretry);
3189 } else {
3190 __ bne( CCR0, Lretry);
3191 }
3192 if (RegCollision) __ mr(Rres, Rtmp);
3193 __ fence();
3194 %}
3196 // This enc_class is needed so that scheduler gets proper
3197 // input mapping for latency computation.
3198 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3199 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3200 MacroAssembler _masm(&cbuf);
3201 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3202 %}
3204 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3205 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3207 MacroAssembler _masm(&cbuf);
3209 Label done;
3210 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3211 __ li($dst$$Register, $zero$$constant);
3212 __ beq($crx$$CondRegister, done);
3213 __ li($dst$$Register, $notzero$$constant);
3214 __ bind(done);
3215 %}
3217 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3218 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3220 MacroAssembler _masm(&cbuf);
3222 Label done;
3223 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3224 __ li($dst$$Register, $zero$$constant);
3225 __ beq($crx$$CondRegister, done);
3226 __ li($dst$$Register, $notzero$$constant);
3227 __ bind(done);
3228 %}
3230 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3231 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3233 MacroAssembler _masm(&cbuf);
3234 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3235 Label done;
3236 __ bso($crx$$CondRegister, done);
3237 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3238 // TODO PPC port __ endgroup_if_needed(_size == 12);
3239 __ bind(done);
3240 %}
3242 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3243 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3245 MacroAssembler _masm(&cbuf);
3246 Label d; // dummy
3247 __ bind(d);
3248 Label* p = ($lbl$$label);
3249 // `p' is `NULL' when this encoding class is used only to
3250 // determine the size of the encoded instruction.
3251 Label& l = (NULL == p)? d : *(p);
3252 int cc = $cmp$$cmpcode;
3253 int flags_reg = $crx$$reg;
3254 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3255 int bhint = Assembler::bhintNoHint;
3257 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3258 if (_prob <= PROB_NEVER) {
3259 bhint = Assembler::bhintIsNotTaken;
3260 } else if (_prob >= PROB_ALWAYS) {
3261 bhint = Assembler::bhintIsTaken;
3262 }
3263 }
3265 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3266 cc_to_biint(cc, flags_reg),
3267 l);
3268 %}
3270 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3271 // The scheduler doesn't know about branch shortening, so we set the opcode
3272 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3273 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3275 MacroAssembler _masm(&cbuf);
3276 Label d; // dummy
3277 __ bind(d);
3278 Label* p = ($lbl$$label);
3279 // `p' is `NULL' when this encoding class is used only to
3280 // determine the size of the encoded instruction.
3281 Label& l = (NULL == p)? d : *(p);
3282 int cc = $cmp$$cmpcode;
3283 int flags_reg = $crx$$reg;
3284 int bhint = Assembler::bhintNoHint;
3286 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3287 if (_prob <= PROB_NEVER) {
3288 bhint = Assembler::bhintIsNotTaken;
3289 } else if (_prob >= PROB_ALWAYS) {
3290 bhint = Assembler::bhintIsTaken;
3291 }
3292 }
3294 // Tell the conditional far branch to optimize itself when being relocated.
3295 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3296 cc_to_biint(cc, flags_reg),
3297 l,
3298 MacroAssembler::bc_far_optimize_on_relocate);
3299 %}
3301 // Branch used with Power6 scheduling (can be shortened without changing the node).
3302 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3303 // The scheduler doesn't know about branch shortening, so we set the opcode
3304 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3305 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3307 MacroAssembler _masm(&cbuf);
3308 Label d; // dummy
3309 __ bind(d);
3310 Label* p = ($lbl$$label);
3311 // `p' is `NULL' when this encoding class is used only to
3312 // determine the size of the encoded instruction.
3313 Label& l = (NULL == p)? d : *(p);
3314 int cc = $cmp$$cmpcode;
3315 int flags_reg = $crx$$reg;
3316 int bhint = Assembler::bhintNoHint;
3318 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3319 if (_prob <= PROB_NEVER) {
3320 bhint = Assembler::bhintIsNotTaken;
3321 } else if (_prob >= PROB_ALWAYS) {
3322 bhint = Assembler::bhintIsTaken;
3323 }
3324 }
3326 #if 0 // TODO: PPC port
3327 if (_size == 8) {
3328 // Tell the conditional far branch to optimize itself when being relocated.
3329 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3330 cc_to_biint(cc, flags_reg),
3331 l,
3332 MacroAssembler::bc_far_optimize_on_relocate);
3333 } else {
3334 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3335 cc_to_biint(cc, flags_reg),
3336 l);
3337 }
3338 #endif
3339 Unimplemented();
3340 %}
3342 // Postalloc expand emitter for loading a replicatef float constant from
3343 // the method's TOC.
3344 // Enc_class needed as consttanttablebase is not supported by postalloc
3345 // expand.
3346 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3347 // Create new nodes.
3349 // Make an operand with the bit pattern to load as float.
3350 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3352 loadConLNodesTuple loadConLNodes =
3353 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3354 ra_->get_reg_second(this), ra_->get_reg_first(this));
3356 // Push new nodes.
3357 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3358 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3360 assert(nodes->length() >= 1, "must have created at least 1 node");
3361 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3362 %}
3364 // This enc_class is needed so that scheduler gets proper
3365 // input mapping for latency computation.
3366 enc_class enc_poll(immI dst, iRegLdst poll) %{
3367 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3368 // Fake operand dst needed for PPC scheduler.
3369 assert($dst$$constant == 0x0, "dst must be 0x0");
3371 MacroAssembler _masm(&cbuf);
3372 // Mark the code position where the load from the safepoint
3373 // polling page was emitted as relocInfo::poll_type.
3374 __ relocate(relocInfo::poll_type);
3375 __ load_from_polling_page($poll$$Register);
3376 %}
3378 // A Java static call or a runtime call.
3379 //
3380 // Branch-and-link relative to a trampoline.
3381 // The trampoline loads the target address and does a long branch to there.
3382 // In case we call java, the trampoline branches to a interpreter_stub
3383 // which loads the inline cache and the real call target from the constant pool.
3384 //
3385 // This basically looks like this:
3386 //
3387 // >>>> consts -+ -+
3388 // | |- offset1
3389 // [call target1] | <-+
3390 // [IC cache] |- offset2
3391 // [call target2] <--+
3392 //
3393 // <<<< consts
3394 // >>>> insts
3395 //
3396 // bl offset16 -+ -+ ??? // How many bits available?
3397 // | |
3398 // <<<< insts | |
3399 // >>>> stubs | |
3400 // | |- trampoline_stub_Reloc
3401 // trampoline stub: | <-+
3402 // r2 = toc |
3403 // r2 = [r2 + offset1] | // Load call target1 from const section
3404 // mtctr r2 |
3405 // bctr |- static_stub_Reloc
3406 // comp_to_interp_stub: <---+
3407 // r1 = toc
3408 // ICreg = [r1 + IC_offset] // Load IC from const section
3409 // r1 = [r1 + offset2] // Load call target2 from const section
3410 // mtctr r1
3411 // bctr
3412 //
3413 // <<<< stubs
3414 //
3415 // The call instruction in the code either
3416 // - Branches directly to a compiled method if the offset is encodable in instruction.
3417 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3418 // - Branches to the compiled_to_interp stub if the target is interpreted.
3419 //
3420 // Further there are three relocations from the loads to the constants in
3421 // the constant section.
3422 //
3423 // Usage of r1 and r2 in the stubs allows to distinguish them.
3424 enc_class enc_java_static_call(method meth) %{
3425 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3427 MacroAssembler _masm(&cbuf);
3428 address entry_point = (address)$meth$$method;
3430 if (!_method) {
3431 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3432 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3433 } else {
3434 // Remember the offset not the address.
3435 const int start_offset = __ offset();
3436 // The trampoline stub.
3437 if (!Compile::current()->in_scratch_emit_size()) {
3438 // No entry point given, use the current pc.
3439 // Make sure branch fits into
3440 if (entry_point == 0) entry_point = __ pc();
3442 // Put the entry point as a constant into the constant pool.
3443 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3444 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3446 // Emit the trampoline stub which will be related to the branch-and-link below.
3447 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3448 __ relocate(_optimized_virtual ?
3449 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3450 }
3452 // The real call.
3453 // Note: At this point we do not have the address of the trampoline
3454 // stub, and the entry point might be too far away for bl, so __ pc()
3455 // serves as dummy and the bl will be patched later.
3456 cbuf.set_insts_mark();
3457 __ bl(__ pc()); // Emits a relocation.
3459 // The stub for call to interpreter.
3460 CompiledStaticCall::emit_to_interp_stub(cbuf);
3461 }
3462 %}
3464 // Emit a method handle call.
3465 //
3466 // Method handle calls from compiled to compiled are going thru a
3467 // c2i -> i2c adapter, extending the frame for their arguments. The
3468 // caller however, returns directly to the compiled callee, that has
3469 // to cope with the extended frame. We restore the original frame by
3470 // loading the callers sp and adding the calculated framesize.
3471 enc_class enc_java_handle_call(method meth) %{
3472 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3474 MacroAssembler _masm(&cbuf);
3475 address entry_point = (address)$meth$$method;
3477 // Remember the offset not the address.
3478 const int start_offset = __ offset();
3479 // The trampoline stub.
3480 if (!ra_->C->in_scratch_emit_size()) {
3481 // No entry point given, use the current pc.
3482 // Make sure branch fits into
3483 if (entry_point == 0) entry_point = __ pc();
3485 // Put the entry point as a constant into the constant pool.
3486 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3487 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3489 // Emit the trampoline stub which will be related to the branch-and-link below.
3490 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3491 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3492 __ relocate(relocInfo::opt_virtual_call_type);
3493 }
3495 // The real call.
3496 // Note: At this point we do not have the address of the trampoline
3497 // stub, and the entry point might be too far away for bl, so __ pc()
3498 // serves as dummy and the bl will be patched later.
3499 cbuf.set_insts_mark();
3500 __ bl(__ pc()); // Emits a relocation.
3502 assert(_method, "execute next statement conditionally");
3503 // The stub for call to interpreter.
3504 CompiledStaticCall::emit_to_interp_stub(cbuf);
3506 // Restore original sp.
3507 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3508 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3509 unsigned int bytes = (unsigned int)framesize;
3510 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3511 if (Assembler::is_simm(-offset, 16)) {
3512 __ addi(R1_SP, R11_scratch1, -offset);
3513 } else {
3514 __ load_const_optimized(R12_scratch2, -offset);
3515 __ add(R1_SP, R11_scratch1, R12_scratch2);
3516 }
3517 #ifdef ASSERT
3518 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3519 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3520 __ asm_assert_eq("backlink changed", 0x8000);
3521 #endif
3522 // If fails should store backlink before unextending.
3524 if (ra_->C->env()->failing()) {
3525 return;
3526 }
3527 %}
3529 // Second node of expanded dynamic call - the call.
3530 enc_class enc_java_dynamic_call_sched(method meth) %{
3531 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3533 MacroAssembler _masm(&cbuf);
3535 if (!ra_->C->in_scratch_emit_size()) {
3536 // Create a call trampoline stub for the given method.
3537 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3538 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3539 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3540 emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3542 if (ra_->C->env()->failing())
3543 return;
3545 // Build relocation at call site with ic position as data.
3546 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3547 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3548 "must have one, but can't have both");
3549 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3550 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3551 "must contain instruction offset");
3552 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3553 ? _load_ic_hi_node->_cbuf_insts_offset
3554 : _load_ic_node->_cbuf_insts_offset;
3555 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3556 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3557 "should be load from TOC");
3559 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3560 }
3562 // At this point I do not have the address of the trampoline stub,
3563 // and the entry point might be too far away for bl. Pc() serves
3564 // as dummy and bl will be patched later.
3565 __ bl((address) __ pc());
3566 %}
3568 // postalloc expand emitter for virtual calls.
3569 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3571 // Create the nodes for loading the IC from the TOC.
3572 loadConLNodesTuple loadConLNodes_IC =
3573 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3574 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3576 // Create the call node.
3577 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3578 call->_method_handle_invoke = _method_handle_invoke;
3579 call->_vtable_index = _vtable_index;
3580 call->_method = _method;
3581 call->_bci = _bci;
3582 call->_optimized_virtual = _optimized_virtual;
3583 call->_tf = _tf;
3584 call->_entry_point = _entry_point;
3585 call->_cnt = _cnt;
3586 call->_argsize = _argsize;
3587 call->_oop_map = _oop_map;
3588 call->_jvms = _jvms;
3589 call->_jvmadj = _jvmadj;
3590 call->_in_rms = _in_rms;
3591 call->_nesting = _nesting;
3593 // New call needs all inputs of old call.
3594 // Req...
3595 for (uint i = 0; i < req(); ++i) {
3596 // The expanded node does not need toc any more.
3597 // Add the inline cache constant here instead. This expresses the
3598 // register of the inline cache must be live at the call.
3599 // Else we would have to adapt JVMState by -1.
3600 if (i == mach_constant_base_node_input()) {
3601 call->add_req(loadConLNodes_IC._last);
3602 } else {
3603 call->add_req(in(i));
3604 }
3605 }
3606 // ...as well as prec
3607 for (uint i = req(); i < len(); ++i) {
3608 call->add_prec(in(i));
3609 }
3611 // Remember nodes loading the inline cache into r19.
3612 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3613 call->_load_ic_node = loadConLNodes_IC._small;
3615 // Operands for new nodes.
3616 call->_opnds[0] = _opnds[0];
3617 call->_opnds[1] = _opnds[1];
3619 // Only the inline cache is associated with a register.
3620 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3622 // Push new nodes.
3623 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3624 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3625 nodes->push(call);
3626 %}
3628 // Compound version of call dynamic
3629 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3630 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3631 MacroAssembler _masm(&cbuf);
3632 int start_offset = __ offset();
3634 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3635 #if 0
3636 if (_vtable_index < 0) {
3637 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3638 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3639 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3640 AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word());
3642 address virtual_call_meta_addr = __ pc();
3643 __ load_const_from_method_toc(ic_reg, meta, Rtoc);
3644 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3645 // to determine who we intended to call.
3646 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3647 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3648 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3649 "Fix constant in ret_addr_offset()");
3650 } else {
3651 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3652 // Go thru the vtable. Get receiver klass. Receiver already
3653 // checked for non-null. If we'll go thru a C2I adapter, the
3654 // interpreter expects method in R19_method.
3656 __ load_klass(R11_scratch1, R3);
3658 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3659 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3660 __ li(R19_method, v_off);
3661 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3662 // NOTE: for vtable dispatches, the vtable entry will never be
3663 // null. However it may very well end up in handle_wrong_method
3664 // if the method is abstract for the particular class.
3665 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3666 // Call target. Either compiled code or C2I adapter.
3667 __ mtctr(R11_scratch1);
3668 __ bctrl();
3669 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3670 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3671 }
3672 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3673 "Fix constant in ret_addr_offset()");
3674 }
3675 #endif
3676 guarantee(0, "Fix handling of toc edge: messes up derived/base pairs.");
3677 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3678 %}
3680 // a runtime call
3681 enc_class enc_java_to_runtime_call (method meth) %{
3682 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3684 MacroAssembler _masm(&cbuf);
3685 const address start_pc = __ pc();
3687 // The function we're going to call.
3688 FunctionDescriptor fdtemp;
3689 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3691 Register Rtoc = R12_scratch2;
3692 // Calculate the method's TOC.
3693 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3694 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3695 // pool entries; call_c_using_toc will optimize the call.
3696 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3698 // Check the ret_addr_offset.
3699 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3700 "Fix constant in ret_addr_offset()");
3701 %}
3703 // Move to ctr for leaf call.
3704 // This enc_class is needed so that scheduler gets proper
3705 // input mapping for latency computation.
3706 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3707 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3708 MacroAssembler _masm(&cbuf);
3709 __ mtctr($src$$Register);
3710 %}
3712 // postalloc expand emitter for runtime leaf calls.
3713 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3714 // Get the struct that describes the function we are about to call.
3715 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3716 assert(fd, "need fd here");
3717 // new nodes
3718 loadConLNodesTuple loadConLNodes_Entry;
3719 loadConLNodesTuple loadConLNodes_Env;
3720 loadConLNodesTuple loadConLNodes_Toc;
3721 MachNode *mtctr = NULL;
3722 MachCallLeafNode *call = NULL;
3724 // Create nodes and operands for loading the entry point.
3725 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->entry()),
3726 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3729 // Create nodes and operands for loading the env pointer.
3730 if (fd->env() != NULL) {
3731 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3732 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3733 } else {
3734 loadConLNodes_Env._large_hi = NULL;
3735 loadConLNodes_Env._large_lo = NULL;
3736 loadConLNodes_Env._small = NULL;
3737 loadConLNodes_Env._last = new (C) loadConL16Node();
3738 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3739 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3740 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3741 }
3743 // Create nodes and operands for loading the Toc point.
3744 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3745 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3746 // mtctr node
3747 mtctr = new (C) CallLeafDirect_mtctrNode();
3749 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3750 mtctr->add_req(0, loadConLNodes_Entry._last);
3752 mtctr->_opnds[0] = new (C) iRegLdstOper();
3753 mtctr->_opnds[1] = new (C) iRegLdstOper();
3755 // call node
3756 call = new (C) CallLeafDirectNode();
3758 call->_opnds[0] = _opnds[0];
3759 call->_opnds[1] = new (C) methodOper((intptr_t) fd->entry()); // may get set later
3761 // Make the new call node look like the old one.
3762 call->_name = _name;
3763 call->_tf = _tf;
3764 call->_entry_point = _entry_point;
3765 call->_cnt = _cnt;
3766 call->_argsize = _argsize;
3767 call->_oop_map = _oop_map;
3768 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3769 call->_jvms = NULL;
3770 call->_jvmadj = _jvmadj;
3771 call->_in_rms = _in_rms;
3772 call->_nesting = _nesting;
3775 // New call needs all inputs of old call.
3776 // Req...
3777 for (uint i = 0; i < req(); ++i) {
3778 if (i != mach_constant_base_node_input()) {
3779 call->add_req(in(i));
3780 }
3781 }
3783 // These must be reqired edges, as the registers are live up to
3784 // the call. Else the constants are handled as kills.
3785 call->add_req(mtctr);
3786 call->add_req(loadConLNodes_Env._last);
3787 call->add_req(loadConLNodes_Toc._last);
3789 // ...as well as prec
3790 for (uint i = req(); i < len(); ++i) {
3791 call->add_prec(in(i));
3792 }
3794 // registers
3795 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3797 // Insert the new nodes.
3798 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3799 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3800 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3801 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3802 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3803 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3804 nodes->push(mtctr);
3805 nodes->push(call);
3806 %}
3807 %}
3809 //----------FRAME--------------------------------------------------------------
3810 // Definition of frame structure and management information.
3812 frame %{
3813 // What direction does stack grow in (assumed to be same for native & Java).
3814 stack_direction(TOWARDS_LOW);
3816 // These two registers define part of the calling convention between
3817 // compiled code and the interpreter.
3819 // Inline Cache Register or method for I2C.
3820 inline_cache_reg(R19); // R19_method
3822 // Method Oop Register when calling interpreter.
3823 interpreter_method_oop_reg(R19); // R19_method
3825 // Optional: name the operand used by cisc-spilling to access
3826 // [stack_pointer + offset].
3827 cisc_spilling_operand_name(indOffset);
3829 // Number of stack slots consumed by a Monitor enter.
3830 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3832 // Compiled code's Frame Pointer.
3833 frame_pointer(R1); // R1_SP
3835 // Interpreter stores its frame pointer in a register which is
3836 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3837 // interpreted java to compiled java.
3838 //
3839 // R14_state holds pointer to caller's cInterpreter.
3840 interpreter_frame_pointer(R14); // R14_state
3842 stack_alignment(frame::alignment_in_bytes);
3844 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3846 // Number of outgoing stack slots killed above the
3847 // out_preserve_stack_slots for calls to C. Supports the var-args
3848 // backing area for register parms.
3849 //
3850 varargs_C_out_slots_killed(((frame::abi_112_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3852 // The after-PROLOG location of the return address. Location of
3853 // return address specifies a type (REG or STACK) and a number
3854 // representing the register number (i.e. - use a register name) or
3855 // stack slot.
3856 //
3857 // A: Link register is stored in stack slot ...
3858 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3859 // J: Therefore, we make sure that the link register is also in R11_scratch1
3860 // at the end of the prolog.
3861 // B: We use R20, now.
3862 //return_addr(REG R20);
3864 // G: After reading the comments made by all the luminaries on their
3865 // failure to tell the compiler where the return address really is,
3866 // I hardly dare to try myself. However, I'm convinced it's in slot
3867 // 4 what apparently works and saves us some spills.
3868 return_addr(STACK 4);
3870 // This is the body of the function
3871 //
3872 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3873 // uint length, // length of array
3874 // bool is_outgoing)
3875 //
3876 // The `sig' array is to be updated. sig[j] represents the location
3877 // of the j-th argument, either a register or a stack slot.
3879 // Comment taken from i486.ad:
3880 // Body of function which returns an integer array locating
3881 // arguments either in registers or in stack slots. Passed an array
3882 // of ideal registers called "sig" and a "length" count. Stack-slot
3883 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3884 // arguments for a CALLEE. Incoming stack arguments are
3885 // automatically biased by the preserve_stack_slots field above.
3886 calling_convention %{
3887 // No difference between ingoing/outgoing. Just pass false.
3888 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3889 %}
3891 // Comment taken from i486.ad:
3892 // Body of function which returns an integer array locating
3893 // arguments either in registers or in stack slots. Passed an array
3894 // of ideal registers called "sig" and a "length" count. Stack-slot
3895 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3896 // arguments for a CALLEE. Incoming stack arguments are
3897 // automatically biased by the preserve_stack_slots field above.
3898 c_calling_convention %{
3899 // This is obviously always outgoing.
3900 // C argument in register AND stack slot.
3901 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3902 %}
3904 // Location of native (C/C++) and interpreter return values. This
3905 // is specified to be the same as Java. In the 32-bit VM, long
3906 // values are actually returned from native calls in O0:O1 and
3907 // returned to the interpreter in I0:I1. The copying to and from
3908 // the register pairs is done by the appropriate call and epilog
3909 // opcodes. This simplifies the register allocator.
3910 c_return_value %{
3911 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3912 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3913 "only return normal values");
3914 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3915 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3916 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3917 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3918 %}
3920 // Location of compiled Java return values. Same as C
3921 return_value %{
3922 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3923 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3924 "only return normal values");
3925 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3926 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3927 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3928 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3929 %}
3930 %}
3933 //----------ATTRIBUTES---------------------------------------------------------
3935 //----------Operand Attributes-------------------------------------------------
3936 op_attrib op_cost(1); // Required cost attribute.
3938 //----------Instruction Attributes---------------------------------------------
3940 // Cost attribute. required.
3941 ins_attrib ins_cost(DEFAULT_COST);
3943 // Is this instruction a non-matching short branch variant of some
3944 // long branch? Not required.
3945 ins_attrib ins_short_branch(0);
3947 ins_attrib ins_is_TrapBasedCheckNode(true);
3949 // Number of constants.
3950 // This instruction uses the given number of constants
3951 // (optional attribute).
3952 // This is needed to determine in time whether the constant pool will
3953 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3954 // is determined. It's also used to compute the constant pool size
3955 // in Output().
3956 ins_attrib ins_num_consts(0);
3958 // Required alignment attribute (must be a power of 2) specifies the
3959 // alignment that some part of the instruction (not necessarily the
3960 // start) requires. If > 1, a compute_padding() function must be
3961 // provided for the instruction.
3962 ins_attrib ins_alignment(1);
3964 // Enforce/prohibit rematerializations.
3965 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3966 // then rematerialization of that instruction is prohibited and the
3967 // instruction's value will be spilled if necessary.
3968 // Causes that MachNode::rematerialize() returns false.
3969 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3970 // then rematerialization should be enforced and a copy of the instruction
3971 // should be inserted if possible; rematerialization is not guaranteed.
3972 // Note: this may result in rematerializations in front of every use.
3973 // Causes that MachNode::rematerialize() can return true.
3974 // (optional attribute)
3975 ins_attrib ins_cannot_rematerialize(false);
3976 ins_attrib ins_should_rematerialize(false);
3978 // Instruction has variable size depending on alignment.
3979 ins_attrib ins_variable_size_depending_on_alignment(false);
3981 // Instruction is a nop.
3982 ins_attrib ins_is_nop(false);
3984 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3985 ins_attrib ins_use_mach_if_fast_lock_node(false);
3987 // Field for the toc offset of a constant.
3988 //
3989 // This is needed if the toc offset is not encodable as an immediate in
3990 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3991 // added to the toc, and from this a load with immediate is performed.
3992 // With postalloc expand, we get two nodes that require the same offset
3993 // but which don't know about each other. The offset is only known
3994 // when the constant is added to the constant pool during emitting.
3995 // It is generated in the 'hi'-node adding the upper bits, and saved
3996 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3997 // the offset from there when it gets encoded.
3998 ins_attrib ins_field_const_toc_offset(0);
3999 ins_attrib ins_field_const_toc_offset_hi_node(0);
4001 // A field that can hold the instructions offset in the code buffer.
4002 // Set in the nodes emitter.
4003 ins_attrib ins_field_cbuf_insts_offset(-1);
4005 // Fields for referencing a call's load-IC-node.
4006 // If the toc offset can not be encoded as an immediate in a load, we
4007 // use two nodes.
4008 ins_attrib ins_field_load_ic_hi_node(0);
4009 ins_attrib ins_field_load_ic_node(0);
4011 //----------OPERANDS-----------------------------------------------------------
4012 // Operand definitions must precede instruction definitions for correct
4013 // parsing in the ADLC because operands constitute user defined types
4014 // which are used in instruction definitions.
4015 //
4016 // Formats are generated automatically for constants and base registers.
4018 //----------Simple Operands----------------------------------------------------
4019 // Immediate Operands
4021 // Integer Immediate: 32-bit
4022 operand immI() %{
4023 match(ConI);
4024 op_cost(40);
4025 format %{ %}
4026 interface(CONST_INTER);
4027 %}
4029 operand immI8() %{
4030 predicate(Assembler::is_simm(n->get_int(), 8));
4031 op_cost(0);
4032 match(ConI);
4033 format %{ %}
4034 interface(CONST_INTER);
4035 %}
4037 // Integer Immediate: 16-bit
4038 operand immI16() %{
4039 predicate(Assembler::is_simm(n->get_int(), 16));
4040 op_cost(0);
4041 match(ConI);
4042 format %{ %}
4043 interface(CONST_INTER);
4044 %}
4046 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4047 operand immIhi16() %{
4048 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4049 match(ConI);
4050 op_cost(0);
4051 format %{ %}
4052 interface(CONST_INTER);
4053 %}
4055 operand immInegpow2() %{
4056 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4057 match(ConI);
4058 op_cost(0);
4059 format %{ %}
4060 interface(CONST_INTER);
4061 %}
4063 operand immIpow2minus1() %{
4064 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4065 match(ConI);
4066 op_cost(0);
4067 format %{ %}
4068 interface(CONST_INTER);
4069 %}
4071 operand immIpowerOf2() %{
4072 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4073 match(ConI);
4074 op_cost(0);
4075 format %{ %}
4076 interface(CONST_INTER);
4077 %}
4079 // Unsigned Integer Immediate: the values 0-31
4080 operand uimmI5() %{
4081 predicate(Assembler::is_uimm(n->get_int(), 5));
4082 match(ConI);
4083 op_cost(0);
4084 format %{ %}
4085 interface(CONST_INTER);
4086 %}
4088 // Unsigned Integer Immediate: 6-bit
4089 operand uimmI6() %{
4090 predicate(Assembler::is_uimm(n->get_int(), 6));
4091 match(ConI);
4092 op_cost(0);
4093 format %{ %}
4094 interface(CONST_INTER);
4095 %}
4097 // Unsigned Integer Immediate: 6-bit int, greater than 32
4098 operand uimmI6_ge32() %{
4099 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4100 match(ConI);
4101 op_cost(0);
4102 format %{ %}
4103 interface(CONST_INTER);
4104 %}
4106 // Unsigned Integer Immediate: 15-bit
4107 operand uimmI15() %{
4108 predicate(Assembler::is_uimm(n->get_int(), 15));
4109 match(ConI);
4110 op_cost(0);
4111 format %{ %}
4112 interface(CONST_INTER);
4113 %}
4115 // Unsigned Integer Immediate: 16-bit
4116 operand uimmI16() %{
4117 predicate(Assembler::is_uimm(n->get_int(), 16));
4118 match(ConI);
4119 op_cost(0);
4120 format %{ %}
4121 interface(CONST_INTER);
4122 %}
4124 // constant 'int 0'.
4125 operand immI_0() %{
4126 predicate(n->get_int() == 0);
4127 match(ConI);
4128 op_cost(0);
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4133 // constant 'int 1'.
4134 operand immI_1() %{
4135 predicate(n->get_int() == 1);
4136 match(ConI);
4137 op_cost(0);
4138 format %{ %}
4139 interface(CONST_INTER);
4140 %}
4142 // constant 'int -1'.
4143 operand immI_minus1() %{
4144 predicate(n->get_int() == -1);
4145 match(ConI);
4146 op_cost(0);
4147 format %{ %}
4148 interface(CONST_INTER);
4149 %}
4151 // int value 16.
4152 operand immI_16() %{
4153 predicate(n->get_int() == 16);
4154 match(ConI);
4155 op_cost(0);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4160 // int value 24.
4161 operand immI_24() %{
4162 predicate(n->get_int() == 24);
4163 match(ConI);
4164 op_cost(0);
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4169 // Compressed oops constants
4170 // Pointer Immediate
4171 operand immN() %{
4172 match(ConN);
4174 op_cost(10);
4175 format %{ %}
4176 interface(CONST_INTER);
4177 %}
4179 // NULL Pointer Immediate
4180 operand immN_0() %{
4181 predicate(n->get_narrowcon() == 0);
4182 match(ConN);
4184 op_cost(0);
4185 format %{ %}
4186 interface(CONST_INTER);
4187 %}
4189 // Compressed klass constants
4190 operand immNKlass() %{
4191 match(ConNKlass);
4193 op_cost(0);
4194 format %{ %}
4195 interface(CONST_INTER);
4196 %}
4198 // This operand can be used to avoid matching of an instruct
4199 // with chain rule.
4200 operand immNKlass_NM() %{
4201 match(ConNKlass);
4202 predicate(false);
4203 op_cost(0);
4204 format %{ %}
4205 interface(CONST_INTER);
4206 %}
4208 // Pointer Immediate: 64-bit
4209 operand immP() %{
4210 match(ConP);
4211 op_cost(0);
4212 format %{ %}
4213 interface(CONST_INTER);
4214 %}
4216 // Operand to avoid match of loadConP.
4217 // This operand can be used to avoid matching of an instruct
4218 // with chain rule.
4219 operand immP_NM() %{
4220 match(ConP);
4221 predicate(false);
4222 op_cost(0);
4223 format %{ %}
4224 interface(CONST_INTER);
4225 %}
4227 // costant 'pointer 0'.
4228 operand immP_0() %{
4229 predicate(n->get_ptr() == 0);
4230 match(ConP);
4231 op_cost(0);
4232 format %{ %}
4233 interface(CONST_INTER);
4234 %}
4236 // pointer 0x0 or 0x1
4237 operand immP_0or1() %{
4238 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4239 match(ConP);
4240 op_cost(0);
4241 format %{ %}
4242 interface(CONST_INTER);
4243 %}
4245 operand immL() %{
4246 match(ConL);
4247 op_cost(40);
4248 format %{ %}
4249 interface(CONST_INTER);
4250 %}
4252 // Long Immediate: 16-bit
4253 operand immL16() %{
4254 predicate(Assembler::is_simm(n->get_long(), 16));
4255 match(ConL);
4256 op_cost(0);
4257 format %{ %}
4258 interface(CONST_INTER);
4259 %}
4261 // Long Immediate: 16-bit, 4-aligned
4262 operand immL16Alg4() %{
4263 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4264 match(ConL);
4265 op_cost(0);
4266 format %{ %}
4267 interface(CONST_INTER);
4268 %}
4270 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4271 operand immL32hi16() %{
4272 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4273 match(ConL);
4274 op_cost(0);
4275 format %{ %}
4276 interface(CONST_INTER);
4277 %}
4279 // Long Immediate: 32-bit
4280 operand immL32() %{
4281 predicate(Assembler::is_simm(n->get_long(), 32));
4282 match(ConL);
4283 op_cost(0);
4284 format %{ %}
4285 interface(CONST_INTER);
4286 %}
4288 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4289 operand immLhighest16() %{
4290 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4291 match(ConL);
4292 op_cost(0);
4293 format %{ %}
4294 interface(CONST_INTER);
4295 %}
4297 operand immLnegpow2() %{
4298 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4299 match(ConL);
4300 op_cost(0);
4301 format %{ %}
4302 interface(CONST_INTER);
4303 %}
4305 operand immLpow2minus1() %{
4306 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4307 (n->get_long() != (jlong)0xffffffffffffffffL));
4308 match(ConL);
4309 op_cost(0);
4310 format %{ %}
4311 interface(CONST_INTER);
4312 %}
4314 // constant 'long 0'.
4315 operand immL_0() %{
4316 predicate(n->get_long() == 0L);
4317 match(ConL);
4318 op_cost(0);
4319 format %{ %}
4320 interface(CONST_INTER);
4321 %}
4323 // constat ' long -1'.
4324 operand immL_minus1() %{
4325 predicate(n->get_long() == -1L);
4326 match(ConL);
4327 op_cost(0);
4328 format %{ %}
4329 interface(CONST_INTER);
4330 %}
4332 // Long Immediate: low 32-bit mask
4333 operand immL_32bits() %{
4334 predicate(n->get_long() == 0xFFFFFFFFL);
4335 match(ConL);
4336 op_cost(0);
4337 format %{ %}
4338 interface(CONST_INTER);
4339 %}
4341 // Unsigned Long Immediate: 16-bit
4342 operand uimmL16() %{
4343 predicate(Assembler::is_uimm(n->get_long(), 16));
4344 match(ConL);
4345 op_cost(0);
4346 format %{ %}
4347 interface(CONST_INTER);
4348 %}
4350 // Float Immediate
4351 operand immF() %{
4352 match(ConF);
4353 op_cost(40);
4354 format %{ %}
4355 interface(CONST_INTER);
4356 %}
4358 // constant 'float +0.0'.
4359 operand immF_0() %{
4360 predicate((n->getf() == 0) &&
4361 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4362 match(ConF);
4363 op_cost(0);
4364 format %{ %}
4365 interface(CONST_INTER);
4366 %}
4368 // Double Immediate
4369 operand immD() %{
4370 match(ConD);
4371 op_cost(40);
4372 format %{ %}
4373 interface(CONST_INTER);
4374 %}
4376 // Integer Register Operands
4377 // Integer Destination Register
4378 // See definition of reg_class bits32_reg_rw.
4379 operand iRegIdst() %{
4380 constraint(ALLOC_IN_RC(bits32_reg_rw));
4381 match(RegI);
4382 match(rscratch1RegI);
4383 match(rscratch2RegI);
4384 match(rarg1RegI);
4385 match(rarg2RegI);
4386 match(rarg3RegI);
4387 match(rarg4RegI);
4388 format %{ %}
4389 interface(REG_INTER);
4390 %}
4392 // Integer Source Register
4393 // See definition of reg_class bits32_reg_ro.
4394 operand iRegIsrc() %{
4395 constraint(ALLOC_IN_RC(bits32_reg_ro));
4396 match(RegI);
4397 match(rscratch1RegI);
4398 match(rscratch2RegI);
4399 match(rarg1RegI);
4400 match(rarg2RegI);
4401 match(rarg3RegI);
4402 match(rarg4RegI);
4403 format %{ %}
4404 interface(REG_INTER);
4405 %}
4407 operand rscratch1RegI() %{
4408 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4409 match(iRegIdst);
4410 format %{ %}
4411 interface(REG_INTER);
4412 %}
4414 operand rscratch2RegI() %{
4415 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4416 match(iRegIdst);
4417 format %{ %}
4418 interface(REG_INTER);
4419 %}
4421 operand rarg1RegI() %{
4422 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4423 match(iRegIdst);
4424 format %{ %}
4425 interface(REG_INTER);
4426 %}
4428 operand rarg2RegI() %{
4429 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4430 match(iRegIdst);
4431 format %{ %}
4432 interface(REG_INTER);
4433 %}
4435 operand rarg3RegI() %{
4436 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4437 match(iRegIdst);
4438 format %{ %}
4439 interface(REG_INTER);
4440 %}
4442 operand rarg4RegI() %{
4443 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4444 match(iRegIdst);
4445 format %{ %}
4446 interface(REG_INTER);
4447 %}
4449 operand rarg1RegL() %{
4450 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4451 match(iRegLdst);
4452 format %{ %}
4453 interface(REG_INTER);
4454 %}
4456 operand rarg2RegL() %{
4457 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4458 match(iRegLdst);
4459 format %{ %}
4460 interface(REG_INTER);
4461 %}
4463 operand rarg3RegL() %{
4464 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4465 match(iRegLdst);
4466 format %{ %}
4467 interface(REG_INTER);
4468 %}
4470 operand rarg4RegL() %{
4471 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4472 match(iRegLdst);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4477 // Pointer Destination Register
4478 // See definition of reg_class bits64_reg_rw.
4479 operand iRegPdst() %{
4480 constraint(ALLOC_IN_RC(bits64_reg_rw));
4481 match(RegP);
4482 match(rscratch1RegP);
4483 match(rscratch2RegP);
4484 match(rarg1RegP);
4485 match(rarg2RegP);
4486 match(rarg3RegP);
4487 match(rarg4RegP);
4488 format %{ %}
4489 interface(REG_INTER);
4490 %}
4492 // Pointer Destination Register
4493 // Operand not using r11 and r12 (killed in epilog).
4494 operand iRegPdstNoScratch() %{
4495 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4496 match(RegP);
4497 match(rarg1RegP);
4498 match(rarg2RegP);
4499 match(rarg3RegP);
4500 match(rarg4RegP);
4501 format %{ %}
4502 interface(REG_INTER);
4503 %}
4505 // Pointer Source Register
4506 // See definition of reg_class bits64_reg_ro.
4507 operand iRegPsrc() %{
4508 constraint(ALLOC_IN_RC(bits64_reg_ro));
4509 match(RegP);
4510 match(iRegPdst);
4511 match(rscratch1RegP);
4512 match(rscratch2RegP);
4513 match(rarg1RegP);
4514 match(rarg2RegP);
4515 match(rarg3RegP);
4516 match(rarg4RegP);
4517 match(threadRegP);
4518 format %{ %}
4519 interface(REG_INTER);
4520 %}
4522 // Thread operand.
4523 operand threadRegP() %{
4524 constraint(ALLOC_IN_RC(thread_bits64_reg));
4525 match(iRegPdst);
4526 format %{ "R16" %}
4527 interface(REG_INTER);
4528 %}
4530 operand rscratch1RegP() %{
4531 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4532 match(iRegPdst);
4533 format %{ "R11" %}
4534 interface(REG_INTER);
4535 %}
4537 operand rscratch2RegP() %{
4538 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4539 match(iRegPdst);
4540 format %{ %}
4541 interface(REG_INTER);
4542 %}
4544 operand rarg1RegP() %{
4545 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4546 match(iRegPdst);
4547 format %{ %}
4548 interface(REG_INTER);
4549 %}
4551 operand rarg2RegP() %{
4552 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4553 match(iRegPdst);
4554 format %{ %}
4555 interface(REG_INTER);
4556 %}
4558 operand rarg3RegP() %{
4559 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4560 match(iRegPdst);
4561 format %{ %}
4562 interface(REG_INTER);
4563 %}
4565 operand rarg4RegP() %{
4566 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4567 match(iRegPdst);
4568 format %{ %}
4569 interface(REG_INTER);
4570 %}
4572 operand iRegNsrc() %{
4573 constraint(ALLOC_IN_RC(bits32_reg_ro));
4574 match(RegN);
4575 match(iRegNdst);
4577 format %{ %}
4578 interface(REG_INTER);
4579 %}
4581 operand iRegNdst() %{
4582 constraint(ALLOC_IN_RC(bits32_reg_rw));
4583 match(RegN);
4585 format %{ %}
4586 interface(REG_INTER);
4587 %}
4589 // Long Destination Register
4590 // See definition of reg_class bits64_reg_rw.
4591 operand iRegLdst() %{
4592 constraint(ALLOC_IN_RC(bits64_reg_rw));
4593 match(RegL);
4594 match(rscratch1RegL);
4595 match(rscratch2RegL);
4596 format %{ %}
4597 interface(REG_INTER);
4598 %}
4600 // Long Source Register
4601 // See definition of reg_class bits64_reg_ro.
4602 operand iRegLsrc() %{
4603 constraint(ALLOC_IN_RC(bits64_reg_ro));
4604 match(RegL);
4605 match(iRegLdst);
4606 match(rscratch1RegL);
4607 match(rscratch2RegL);
4608 format %{ %}
4609 interface(REG_INTER);
4610 %}
4612 // Special operand for ConvL2I.
4613 operand iRegL2Isrc(iRegLsrc reg) %{
4614 constraint(ALLOC_IN_RC(bits64_reg_ro));
4615 match(ConvL2I reg);
4616 format %{ "ConvL2I($reg)" %}
4617 interface(REG_INTER)
4618 %}
4620 operand rscratch1RegL() %{
4621 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4622 match(RegL);
4623 format %{ %}
4624 interface(REG_INTER);
4625 %}
4627 operand rscratch2RegL() %{
4628 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4629 match(RegL);
4630 format %{ %}
4631 interface(REG_INTER);
4632 %}
4634 // Condition Code Flag Registers
4635 operand flagsReg() %{
4636 constraint(ALLOC_IN_RC(int_flags));
4637 match(RegFlags);
4638 format %{ %}
4639 interface(REG_INTER);
4640 %}
4642 // Condition Code Flag Register CR0
4643 operand flagsRegCR0() %{
4644 constraint(ALLOC_IN_RC(int_flags_CR0));
4645 match(RegFlags);
4646 format %{ "CR0" %}
4647 interface(REG_INTER);
4648 %}
4650 operand flagsRegCR1() %{
4651 constraint(ALLOC_IN_RC(int_flags_CR1));
4652 match(RegFlags);
4653 format %{ "CR1" %}
4654 interface(REG_INTER);
4655 %}
4657 operand flagsRegCR6() %{
4658 constraint(ALLOC_IN_RC(int_flags_CR6));
4659 match(RegFlags);
4660 format %{ "CR6" %}
4661 interface(REG_INTER);
4662 %}
4664 operand regCTR() %{
4665 constraint(ALLOC_IN_RC(ctr_reg));
4666 // RegFlags should work. Introducing a RegSpecial type would cause a
4667 // lot of changes.
4668 match(RegFlags);
4669 format %{"SR_CTR" %}
4670 interface(REG_INTER);
4671 %}
4673 operand regD() %{
4674 constraint(ALLOC_IN_RC(dbl_reg));
4675 match(RegD);
4676 format %{ %}
4677 interface(REG_INTER);
4678 %}
4680 operand regF() %{
4681 constraint(ALLOC_IN_RC(flt_reg));
4682 match(RegF);
4683 format %{ %}
4684 interface(REG_INTER);
4685 %}
4687 // Special Registers
4689 // Method Register
4690 operand inline_cache_regP(iRegPdst reg) %{
4691 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4692 match(reg);
4693 format %{ %}
4694 interface(REG_INTER);
4695 %}
4697 operand compiler_method_oop_regP(iRegPdst reg) %{
4698 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4699 match(reg);
4700 format %{ %}
4701 interface(REG_INTER);
4702 %}
4704 operand interpreter_method_oop_regP(iRegPdst reg) %{
4705 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4706 match(reg);
4707 format %{ %}
4708 interface(REG_INTER);
4709 %}
4711 // Operands to remove register moves in unscaled mode.
4712 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4713 operand iRegP2N(iRegPsrc reg) %{
4714 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4715 constraint(ALLOC_IN_RC(bits64_reg_ro));
4716 match(EncodeP reg);
4717 format %{ "$reg" %}
4718 interface(REG_INTER)
4719 %}
4721 operand iRegN2P(iRegNsrc reg) %{
4722 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4723 constraint(ALLOC_IN_RC(bits32_reg_ro));
4724 match(DecodeN reg);
4725 match(DecodeNKlass reg);
4726 format %{ "$reg" %}
4727 interface(REG_INTER)
4728 %}
4730 //----------Complex Operands---------------------------------------------------
4731 // Indirect Memory Reference
4732 operand indirect(iRegPsrc reg) %{
4733 constraint(ALLOC_IN_RC(bits64_reg_ro));
4734 match(reg);
4735 op_cost(100);
4736 format %{ "[$reg]" %}
4737 interface(MEMORY_INTER) %{
4738 base($reg);
4739 index(0x0);
4740 scale(0x0);
4741 disp(0x0);
4742 %}
4743 %}
4745 // Indirect with Offset
4746 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4747 constraint(ALLOC_IN_RC(bits64_reg_ro));
4748 match(AddP reg offset);
4749 op_cost(100);
4750 format %{ "[$reg + $offset]" %}
4751 interface(MEMORY_INTER) %{
4752 base($reg);
4753 index(0x0);
4754 scale(0x0);
4755 disp($offset);
4756 %}
4757 %}
4759 // Indirect with 4-aligned Offset
4760 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4761 constraint(ALLOC_IN_RC(bits64_reg_ro));
4762 match(AddP reg offset);
4763 op_cost(100);
4764 format %{ "[$reg + $offset]" %}
4765 interface(MEMORY_INTER) %{
4766 base($reg);
4767 index(0x0);
4768 scale(0x0);
4769 disp($offset);
4770 %}
4771 %}
4773 //----------Complex Operands for Compressed OOPs-------------------------------
4774 // Compressed OOPs with narrow_oop_shift == 0.
4776 // Indirect Memory Reference, compressed OOP
4777 operand indirectNarrow(iRegNsrc reg) %{
4778 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4779 constraint(ALLOC_IN_RC(bits64_reg_ro));
4780 match(DecodeN reg);
4781 match(DecodeNKlass reg);
4782 op_cost(100);
4783 format %{ "[$reg]" %}
4784 interface(MEMORY_INTER) %{
4785 base($reg);
4786 index(0x0);
4787 scale(0x0);
4788 disp(0x0);
4789 %}
4790 %}
4792 // Indirect with Offset, compressed OOP
4793 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4794 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4795 constraint(ALLOC_IN_RC(bits64_reg_ro));
4796 match(AddP (DecodeN reg) offset);
4797 match(AddP (DecodeNKlass reg) offset);
4798 op_cost(100);
4799 format %{ "[$reg + $offset]" %}
4800 interface(MEMORY_INTER) %{
4801 base($reg);
4802 index(0x0);
4803 scale(0x0);
4804 disp($offset);
4805 %}
4806 %}
4808 // Indirect with 4-aligned Offset, compressed OOP
4809 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4810 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4811 constraint(ALLOC_IN_RC(bits64_reg_ro));
4812 match(AddP (DecodeN reg) offset);
4813 match(AddP (DecodeNKlass reg) offset);
4814 op_cost(100);
4815 format %{ "[$reg + $offset]" %}
4816 interface(MEMORY_INTER) %{
4817 base($reg);
4818 index(0x0);
4819 scale(0x0);
4820 disp($offset);
4821 %}
4822 %}
4824 //----------Special Memory Operands--------------------------------------------
4825 // Stack Slot Operand
4826 //
4827 // This operand is used for loading and storing temporary values on
4828 // the stack where a match requires a value to flow through memory.
4829 operand stackSlotI(sRegI reg) %{
4830 constraint(ALLOC_IN_RC(stack_slots));
4831 op_cost(100);
4832 //match(RegI);
4833 format %{ "[sp+$reg]" %}
4834 interface(MEMORY_INTER) %{
4835 base(0x1); // R1_SP
4836 index(0x0);
4837 scale(0x0);
4838 disp($reg); // Stack Offset
4839 %}
4840 %}
4842 operand stackSlotL(sRegL reg) %{
4843 constraint(ALLOC_IN_RC(stack_slots));
4844 op_cost(100);
4845 //match(RegL);
4846 format %{ "[sp+$reg]" %}
4847 interface(MEMORY_INTER) %{
4848 base(0x1); // R1_SP
4849 index(0x0);
4850 scale(0x0);
4851 disp($reg); // Stack Offset
4852 %}
4853 %}
4855 operand stackSlotP(sRegP reg) %{
4856 constraint(ALLOC_IN_RC(stack_slots));
4857 op_cost(100);
4858 //match(RegP);
4859 format %{ "[sp+$reg]" %}
4860 interface(MEMORY_INTER) %{
4861 base(0x1); // R1_SP
4862 index(0x0);
4863 scale(0x0);
4864 disp($reg); // Stack Offset
4865 %}
4866 %}
4868 operand stackSlotF(sRegF reg) %{
4869 constraint(ALLOC_IN_RC(stack_slots));
4870 op_cost(100);
4871 //match(RegF);
4872 format %{ "[sp+$reg]" %}
4873 interface(MEMORY_INTER) %{
4874 base(0x1); // R1_SP
4875 index(0x0);
4876 scale(0x0);
4877 disp($reg); // Stack Offset
4878 %}
4879 %}
4881 operand stackSlotD(sRegD reg) %{
4882 constraint(ALLOC_IN_RC(stack_slots));
4883 op_cost(100);
4884 //match(RegD);
4885 format %{ "[sp+$reg]" %}
4886 interface(MEMORY_INTER) %{
4887 base(0x1); // R1_SP
4888 index(0x0);
4889 scale(0x0);
4890 disp($reg); // Stack Offset
4891 %}
4892 %}
4894 // Operands for expressing Control Flow
4895 // NOTE: Label is a predefined operand which should not be redefined in
4896 // the AD file. It is generically handled within the ADLC.
4898 //----------Conditional Branch Operands----------------------------------------
4899 // Comparison Op
4900 //
4901 // This is the operation of the comparison, and is limited to the
4902 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4903 // (!=).
4904 //
4905 // Other attributes of the comparison, such as unsignedness, are specified
4906 // by the comparison instruction that sets a condition code flags register.
4907 // That result is represented by a flags operand whose subtype is appropriate
4908 // to the unsignedness (etc.) of the comparison.
4909 //
4910 // Later, the instruction which matches both the Comparison Op (a Bool) and
4911 // the flags (produced by the Cmp) specifies the coding of the comparison op
4912 // by matching a specific subtype of Bool operand below.
4914 // When used for floating point comparisons: unordered same as less.
4915 operand cmpOp() %{
4916 match(Bool);
4917 format %{ "" %}
4918 interface(COND_INTER) %{
4919 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4920 // BO & BI
4921 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4922 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4923 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4924 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4925 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4926 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4927 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4928 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4929 %}
4930 %}
4932 //----------OPERAND CLASSES----------------------------------------------------
4933 // Operand Classes are groups of operands that are used to simplify
4934 // instruction definitions by not requiring the AD writer to specify
4935 // seperate instructions for every form of operand when the
4936 // instruction accepts multiple operand types with the same basic
4937 // encoding and format. The classic case of this is memory operands.
4938 // Indirect is not included since its use is limited to Compare & Swap.
4940 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4941 // Memory operand where offsets are 4-aligned. Required for ld, std.
4942 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
4943 opclass indirectMemory(indirect, indirectNarrow);
4945 // Special opclass for I and ConvL2I.
4946 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4948 // Operand classes to match encode and decode. iRegN_P2N is only used
4949 // for storeN. I have never seen an encode node elsewhere.
4950 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4951 opclass iRegP_N2P(iRegPsrc, iRegN2P);
4953 //----------PIPELINE-----------------------------------------------------------
4955 pipeline %{
4957 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4958 // J. Res. & Dev., No. 1, Jan. 2002.
4960 //----------ATTRIBUTES---------------------------------------------------------
4961 attributes %{
4963 // Power4 instructions are of fixed length.
4964 fixed_size_instructions;
4966 // TODO: if `bundle' means number of instructions fetched
4967 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4968 // max instructions issued per cycle, this is 5.
4969 max_instructions_per_bundle = 8;
4971 // A Power4 instruction is 4 bytes long.
4972 instruction_unit_size = 4;
4974 // The Power4 processor fetches 64 bytes...
4975 instruction_fetch_unit_size = 64;
4977 // ...in one line
4978 instruction_fetch_units = 1
4980 // Unused, list one so that array generated by adlc is not empty.
4981 // Aix compiler chokes if _nop_count = 0.
4982 nops(fxNop);
4983 %}
4985 //----------RESOURCES----------------------------------------------------------
4986 // Resources are the functional units available to the machine
4987 resources(
4988 PPC_BR, // branch unit
4989 PPC_CR, // condition unit
4990 PPC_FX1, // integer arithmetic unit 1
4991 PPC_FX2, // integer arithmetic unit 2
4992 PPC_LDST1, // load/store unit 1
4993 PPC_LDST2, // load/store unit 2
4994 PPC_FP1, // float arithmetic unit 1
4995 PPC_FP2, // float arithmetic unit 2
4996 PPC_LDST = PPC_LDST1 | PPC_LDST2,
4997 PPC_FX = PPC_FX1 | PPC_FX2,
4998 PPC_FP = PPC_FP1 | PPC_FP2
4999 );
5001 //----------PIPELINE DESCRIPTION-----------------------------------------------
5002 // Pipeline Description specifies the stages in the machine's pipeline
5003 pipe_desc(
5004 // Power4 longest pipeline path
5005 PPC_IF, // instruction fetch
5006 PPC_IC,
5007 //PPC_BP, // branch prediction
5008 PPC_D0, // decode
5009 PPC_D1, // decode
5010 PPC_D2, // decode
5011 PPC_D3, // decode
5012 PPC_Xfer1,
5013 PPC_GD, // group definition
5014 PPC_MP, // map
5015 PPC_ISS, // issue
5016 PPC_RF, // resource fetch
5017 PPC_EX1, // execute (all units)
5018 PPC_EX2, // execute (FP, LDST)
5019 PPC_EX3, // execute (FP, LDST)
5020 PPC_EX4, // execute (FP)
5021 PPC_EX5, // execute (FP)
5022 PPC_EX6, // execute (FP)
5023 PPC_WB, // write back
5024 PPC_Xfer2,
5025 PPC_CP
5026 );
5028 //----------PIPELINE CLASSES---------------------------------------------------
5029 // Pipeline Classes describe the stages in which input and output are
5030 // referenced by the hardware pipeline.
5032 // Simple pipeline classes.
5034 // Default pipeline class.
5035 pipe_class pipe_class_default() %{
5036 single_instruction;
5037 fixed_latency(2);
5038 %}
5040 // Pipeline class for empty instructions.
5041 pipe_class pipe_class_empty() %{
5042 single_instruction;
5043 fixed_latency(0);
5044 %}
5046 // Pipeline class for compares.
5047 pipe_class pipe_class_compare() %{
5048 single_instruction;
5049 fixed_latency(16);
5050 %}
5052 // Pipeline class for traps.
5053 pipe_class pipe_class_trap() %{
5054 single_instruction;
5055 fixed_latency(100);
5056 %}
5058 // Pipeline class for memory operations.
5059 pipe_class pipe_class_memory() %{
5060 single_instruction;
5061 fixed_latency(16);
5062 %}
5064 // Pipeline class for call.
5065 pipe_class pipe_class_call() %{
5066 single_instruction;
5067 fixed_latency(100);
5068 %}
5070 // Define the class for the Nop node.
5071 define %{
5072 MachNop = pipe_class_default;
5073 %}
5075 %}
5077 //----------INSTRUCTIONS-------------------------------------------------------
5079 // Naming of instructions:
5080 // opA_operB / opA_operB_operC:
5081 // Operation 'op' with one or two source operands 'oper'. Result
5082 // type is A, source operand types are B and C.
5083 // Iff A == B == C, B and C are left out.
5084 //
5085 // The instructions are ordered according to the following scheme:
5086 // - loads
5087 // - load constants
5088 // - prefetch
5089 // - store
5090 // - encode/decode
5091 // - membar
5092 // - conditional moves
5093 // - compare & swap
5094 // - arithmetic and logic operations
5095 // * int: Add, Sub, Mul, Div, Mod
5096 // * int: lShift, arShift, urShift, rot
5097 // * float: Add, Sub, Mul, Div
5098 // * and, or, xor ...
5099 // - register moves: float <-> int, reg <-> stack, repl
5100 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5101 // - conv (low level type cast requiring bit changes (sign extend etc)
5102 // - compares, range & zero checks.
5103 // - branches
5104 // - complex operations, intrinsics, min, max, replicate
5105 // - lock
5106 // - Calls
5107 //
5108 // If there are similar instructions with different types they are sorted:
5109 // int before float
5110 // small before big
5111 // signed before unsigned
5112 // e.g., loadS before loadUS before loadI before loadF.
5115 //----------Load/Store Instructions--------------------------------------------
5117 //----------Load Instructions--------------------------------------------------
5119 // Converts byte to int.
5120 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5121 // reuses the 'amount' operand, but adlc expects that operand specification
5122 // and operands in match rule are equivalent.
5123 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5124 effect(DEF dst, USE src);
5125 format %{ "EXTSB $dst, $src \t// byte->int" %}
5126 size(4);
5127 ins_encode %{
5128 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5129 __ extsb($dst$$Register, $src$$Register);
5130 %}
5131 ins_pipe(pipe_class_default);
5132 %}
5134 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5135 // match-rule, false predicate
5136 match(Set dst (LoadB mem));
5137 predicate(false);
5139 format %{ "LBZ $dst, $mem" %}
5140 size(4);
5141 ins_encode( enc_lbz(dst, mem) );
5142 ins_pipe(pipe_class_memory);
5143 %}
5145 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5146 // match-rule, false predicate
5147 match(Set dst (LoadB mem));
5148 predicate(false);
5150 format %{ "LBZ $dst, $mem\n\t"
5151 "TWI $dst\n\t"
5152 "ISYNC" %}
5153 size(12);
5154 ins_encode( enc_lbz_ac(dst, mem) );
5155 ins_pipe(pipe_class_memory);
5156 %}
5158 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5159 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5160 match(Set dst (LoadB mem));
5161 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5162 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5163 expand %{
5164 iRegIdst tmp;
5165 loadUB_indirect(tmp, mem);
5166 convB2I_reg_2(dst, tmp);
5167 %}
5168 %}
5170 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5171 match(Set dst (LoadB mem));
5172 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5173 expand %{
5174 iRegIdst tmp;
5175 loadUB_indirect_ac(tmp, mem);
5176 convB2I_reg_2(dst, tmp);
5177 %}
5178 %}
5180 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5181 // match-rule, false predicate
5182 match(Set dst (LoadB mem));
5183 predicate(false);
5185 format %{ "LBZ $dst, $mem" %}
5186 size(4);
5187 ins_encode( enc_lbz(dst, mem) );
5188 ins_pipe(pipe_class_memory);
5189 %}
5191 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5192 // match-rule, false predicate
5193 match(Set dst (LoadB mem));
5194 predicate(false);
5196 format %{ "LBZ $dst, $mem\n\t"
5197 "TWI $dst\n\t"
5198 "ISYNC" %}
5199 size(12);
5200 ins_encode( enc_lbz_ac(dst, mem) );
5201 ins_pipe(pipe_class_memory);
5202 %}
5204 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5205 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5206 match(Set dst (LoadB mem));
5207 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5208 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5210 expand %{
5211 iRegIdst tmp;
5212 loadUB_indOffset16(tmp, mem);
5213 convB2I_reg_2(dst, tmp);
5214 %}
5215 %}
5217 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5218 match(Set dst (LoadB mem));
5219 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5221 expand %{
5222 iRegIdst tmp;
5223 loadUB_indOffset16_ac(tmp, mem);
5224 convB2I_reg_2(dst, tmp);
5225 %}
5226 %}
5228 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5229 instruct loadUB(iRegIdst dst, memory mem) %{
5230 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5231 match(Set dst (LoadUB mem));
5232 ins_cost(MEMORY_REF_COST);
5234 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5235 size(4);
5236 ins_encode( enc_lbz(dst, mem) );
5237 ins_pipe(pipe_class_memory);
5238 %}
5240 // Load Unsigned Byte (8bit UNsigned) acquire.
5241 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5242 match(Set dst (LoadUB mem));
5243 ins_cost(3*MEMORY_REF_COST);
5245 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5246 "TWI $dst\n\t"
5247 "ISYNC" %}
5248 size(12);
5249 ins_encode( enc_lbz_ac(dst, mem) );
5250 ins_pipe(pipe_class_memory);
5251 %}
5253 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5254 instruct loadUB2L(iRegLdst dst, memory mem) %{
5255 match(Set dst (ConvI2L (LoadUB mem)));
5256 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5257 ins_cost(MEMORY_REF_COST);
5259 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5260 size(4);
5261 ins_encode( enc_lbz(dst, mem) );
5262 ins_pipe(pipe_class_memory);
5263 %}
5265 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5266 match(Set dst (ConvI2L (LoadUB mem)));
5267 ins_cost(3*MEMORY_REF_COST);
5269 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5270 "TWI $dst\n\t"
5271 "ISYNC" %}
5272 size(12);
5273 ins_encode( enc_lbz_ac(dst, mem) );
5274 ins_pipe(pipe_class_memory);
5275 %}
5277 // Load Short (16bit signed)
5278 instruct loadS(iRegIdst dst, memory mem) %{
5279 match(Set dst (LoadS mem));
5280 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5281 ins_cost(MEMORY_REF_COST);
5283 format %{ "LHA $dst, $mem" %}
5284 size(4);
5285 ins_encode %{
5286 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5287 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5288 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5289 %}
5290 ins_pipe(pipe_class_memory);
5291 %}
5293 // Load Short (16bit signed) acquire.
5294 instruct loadS_ac(iRegIdst dst, memory mem) %{
5295 match(Set dst (LoadS mem));
5296 ins_cost(3*MEMORY_REF_COST);
5298 format %{ "LHA $dst, $mem\t acquire\n\t"
5299 "TWI $dst\n\t"
5300 "ISYNC" %}
5301 size(12);
5302 ins_encode %{
5303 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5304 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5305 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5306 __ twi_0($dst$$Register);
5307 __ isync();
5308 %}
5309 ins_pipe(pipe_class_memory);
5310 %}
5312 // Load Char (16bit unsigned)
5313 instruct loadUS(iRegIdst dst, memory mem) %{
5314 match(Set dst (LoadUS mem));
5315 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5316 ins_cost(MEMORY_REF_COST);
5318 format %{ "LHZ $dst, $mem" %}
5319 size(4);
5320 ins_encode( enc_lhz(dst, mem) );
5321 ins_pipe(pipe_class_memory);
5322 %}
5324 // Load Char (16bit unsigned) acquire.
5325 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5326 match(Set dst (LoadUS mem));
5327 ins_cost(3*MEMORY_REF_COST);
5329 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5330 "TWI $dst\n\t"
5331 "ISYNC" %}
5332 size(12);
5333 ins_encode( enc_lhz_ac(dst, mem) );
5334 ins_pipe(pipe_class_memory);
5335 %}
5337 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5338 instruct loadUS2L(iRegLdst dst, memory mem) %{
5339 match(Set dst (ConvI2L (LoadUS mem)));
5340 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5341 ins_cost(MEMORY_REF_COST);
5343 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5344 size(4);
5345 ins_encode( enc_lhz(dst, mem) );
5346 ins_pipe(pipe_class_memory);
5347 %}
5349 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5350 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5351 match(Set dst (ConvI2L (LoadUS mem)));
5352 ins_cost(3*MEMORY_REF_COST);
5354 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5355 "TWI $dst\n\t"
5356 "ISYNC" %}
5357 size(12);
5358 ins_encode( enc_lhz_ac(dst, mem) );
5359 ins_pipe(pipe_class_memory);
5360 %}
5362 // Load Integer.
5363 instruct loadI(iRegIdst dst, memory mem) %{
5364 match(Set dst (LoadI mem));
5365 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5366 ins_cost(MEMORY_REF_COST);
5368 format %{ "LWZ $dst, $mem" %}
5369 size(4);
5370 ins_encode( enc_lwz(dst, mem) );
5371 ins_pipe(pipe_class_memory);
5372 %}
5374 // Load Integer acquire.
5375 instruct loadI_ac(iRegIdst dst, memory mem) %{
5376 match(Set dst (LoadI mem));
5377 ins_cost(3*MEMORY_REF_COST);
5379 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5380 "TWI $dst\n\t"
5381 "ISYNC" %}
5382 size(12);
5383 ins_encode( enc_lwz_ac(dst, mem) );
5384 ins_pipe(pipe_class_memory);
5385 %}
5387 // Match loading integer and casting it to unsigned int in
5388 // long register.
5389 // LoadI + ConvI2L + AndL 0xffffffff.
5390 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5391 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5392 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5393 ins_cost(MEMORY_REF_COST);
5395 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5396 size(4);
5397 ins_encode( enc_lwz(dst, mem) );
5398 ins_pipe(pipe_class_memory);
5399 %}
5401 // Match loading integer and casting it to long.
5402 instruct loadI2L(iRegLdst dst, memory mem) %{
5403 match(Set dst (ConvI2L (LoadI mem)));
5404 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5405 ins_cost(MEMORY_REF_COST);
5407 format %{ "LWA $dst, $mem \t// loadI2L" %}
5408 size(4);
5409 ins_encode %{
5410 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5411 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5412 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5413 %}
5414 ins_pipe(pipe_class_memory);
5415 %}
5417 // Match loading integer and casting it to long - acquire.
5418 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5419 match(Set dst (ConvI2L (LoadI mem)));
5420 ins_cost(3*MEMORY_REF_COST);
5422 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5423 "TWI $dst\n\t"
5424 "ISYNC" %}
5425 size(12);
5426 ins_encode %{
5427 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5428 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5429 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5430 __ twi_0($dst$$Register);
5431 __ isync();
5432 %}
5433 ins_pipe(pipe_class_memory);
5434 %}
5436 // Load Long - aligned
5437 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5438 match(Set dst (LoadL mem));
5439 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5440 ins_cost(MEMORY_REF_COST);
5442 format %{ "LD $dst, $mem \t// long" %}
5443 size(4);
5444 ins_encode( enc_ld(dst, mem) );
5445 ins_pipe(pipe_class_memory);
5446 %}
5448 // Load Long - aligned acquire.
5449 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5450 match(Set dst (LoadL mem));
5451 ins_cost(3*MEMORY_REF_COST);
5453 format %{ "LD $dst, $mem \t// long acquire\n\t"
5454 "TWI $dst\n\t"
5455 "ISYNC" %}
5456 size(12);
5457 ins_encode( enc_ld_ac(dst, mem) );
5458 ins_pipe(pipe_class_memory);
5459 %}
5461 // Load Long - UNaligned
5462 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5463 match(Set dst (LoadL_unaligned mem));
5464 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5465 ins_cost(MEMORY_REF_COST);
5467 format %{ "LD $dst, $mem \t// unaligned long" %}
5468 size(4);
5469 ins_encode( enc_ld(dst, mem) );
5470 ins_pipe(pipe_class_memory);
5471 %}
5473 // Load nodes for superwords
5475 // Load Aligned Packed Byte
5476 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5477 predicate(n->as_LoadVector()->memory_size() == 8);
5478 match(Set dst (LoadVector mem));
5479 ins_cost(MEMORY_REF_COST);
5481 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5482 size(4);
5483 ins_encode( enc_ld(dst, mem) );
5484 ins_pipe(pipe_class_memory);
5485 %}
5487 // Load Range, range = array length (=jint)
5488 instruct loadRange(iRegIdst dst, memory mem) %{
5489 match(Set dst (LoadRange mem));
5490 ins_cost(MEMORY_REF_COST);
5492 format %{ "LWZ $dst, $mem \t// range" %}
5493 size(4);
5494 ins_encode( enc_lwz(dst, mem) );
5495 ins_pipe(pipe_class_memory);
5496 %}
5498 // Load Compressed Pointer
5499 instruct loadN(iRegNdst dst, memory mem) %{
5500 match(Set dst (LoadN mem));
5501 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5502 ins_cost(MEMORY_REF_COST);
5504 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5505 size(4);
5506 ins_encode( enc_lwz(dst, mem) );
5507 ins_pipe(pipe_class_memory);
5508 %}
5510 // Load Compressed Pointer acquire.
5511 instruct loadN_ac(iRegNdst dst, memory mem) %{
5512 match(Set dst (LoadN mem));
5513 ins_cost(3*MEMORY_REF_COST);
5515 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5516 "TWI $dst\n\t"
5517 "ISYNC" %}
5518 size(12);
5519 ins_encode( enc_lwz_ac(dst, mem) );
5520 ins_pipe(pipe_class_memory);
5521 %}
5523 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5524 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5525 match(Set dst (DecodeN (LoadN mem)));
5526 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5527 ins_cost(MEMORY_REF_COST);
5529 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5530 size(4);
5531 ins_encode( enc_lwz(dst, mem) );
5532 ins_pipe(pipe_class_memory);
5533 %}
5535 // Load Pointer
5536 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5537 match(Set dst (LoadP mem));
5538 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5539 ins_cost(MEMORY_REF_COST);
5541 format %{ "LD $dst, $mem \t// ptr" %}
5542 size(4);
5543 ins_encode( enc_ld(dst, mem) );
5544 ins_pipe(pipe_class_memory);
5545 %}
5547 // Load Pointer acquire.
5548 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5549 match(Set dst (LoadP mem));
5550 ins_cost(3*MEMORY_REF_COST);
5552 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5553 "TWI $dst\n\t"
5554 "ISYNC" %}
5555 size(12);
5556 ins_encode( enc_ld_ac(dst, mem) );
5557 ins_pipe(pipe_class_memory);
5558 %}
5560 // LoadP + CastP2L
5561 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5562 match(Set dst (CastP2X (LoadP mem)));
5563 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5564 ins_cost(MEMORY_REF_COST);
5566 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5567 size(4);
5568 ins_encode( enc_ld(dst, mem) );
5569 ins_pipe(pipe_class_memory);
5570 %}
5572 // Load compressed klass pointer.
5573 instruct loadNKlass(iRegNdst dst, memory mem) %{
5574 match(Set dst (LoadNKlass mem));
5575 ins_cost(MEMORY_REF_COST);
5577 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5578 size(4);
5579 ins_encode( enc_lwz(dst, mem) );
5580 ins_pipe(pipe_class_memory);
5581 %}
5583 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5584 //// TODO: will narrow_klass_shift ever be 0?
5585 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5586 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5587 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5588 // ins_cost(MEMORY_REF_COST);
5589 //
5590 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5591 // size(4);
5592 // ins_encode( enc_lwz(dst, mem) );
5593 // ins_pipe(pipe_class_memory);
5594 //%}
5596 // Load Klass Pointer
5597 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5598 match(Set dst (LoadKlass mem));
5599 ins_cost(MEMORY_REF_COST);
5601 format %{ "LD $dst, $mem \t// klass ptr" %}
5602 size(4);
5603 ins_encode( enc_ld(dst, mem) );
5604 ins_pipe(pipe_class_memory);
5605 %}
5607 // Load Float
5608 instruct loadF(regF dst, memory mem) %{
5609 match(Set dst (LoadF mem));
5610 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5611 ins_cost(MEMORY_REF_COST);
5613 format %{ "LFS $dst, $mem" %}
5614 size(4);
5615 ins_encode %{
5616 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5617 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5618 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5619 %}
5620 ins_pipe(pipe_class_memory);
5621 %}
5623 // Load Float acquire.
5624 instruct loadF_ac(regF dst, memory mem) %{
5625 match(Set dst (LoadF mem));
5626 ins_cost(3*MEMORY_REF_COST);
5628 format %{ "LFS $dst, $mem \t// acquire\n\t"
5629 "FCMPU cr0, $dst, $dst\n\t"
5630 "BNE cr0, next\n"
5631 "next:\n\t"
5632 "ISYNC" %}
5633 size(16);
5634 ins_encode %{
5635 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5636 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5637 Label next;
5638 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5639 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5640 __ bne(CCR0, next);
5641 __ bind(next);
5642 __ isync();
5643 %}
5644 ins_pipe(pipe_class_memory);
5645 %}
5647 // Load Double - aligned
5648 instruct loadD(regD dst, memory mem) %{
5649 match(Set dst (LoadD mem));
5650 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5651 ins_cost(MEMORY_REF_COST);
5653 format %{ "LFD $dst, $mem" %}
5654 size(4);
5655 ins_encode( enc_lfd(dst, mem) );
5656 ins_pipe(pipe_class_memory);
5657 %}
5659 // Load Double - aligned acquire.
5660 instruct loadD_ac(regD dst, memory mem) %{
5661 match(Set dst (LoadD mem));
5662 ins_cost(3*MEMORY_REF_COST);
5664 format %{ "LFD $dst, $mem \t// acquire\n\t"
5665 "FCMPU cr0, $dst, $dst\n\t"
5666 "BNE cr0, next\n"
5667 "next:\n\t"
5668 "ISYNC" %}
5669 size(16);
5670 ins_encode %{
5671 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5672 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5673 Label next;
5674 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5675 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5676 __ bne(CCR0, next);
5677 __ bind(next);
5678 __ isync();
5679 %}
5680 ins_pipe(pipe_class_memory);
5681 %}
5683 // Load Double - UNaligned
5684 instruct loadD_unaligned(regD dst, memory mem) %{
5685 match(Set dst (LoadD_unaligned mem));
5686 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5687 ins_cost(MEMORY_REF_COST);
5689 format %{ "LFD $dst, $mem" %}
5690 size(4);
5691 ins_encode( enc_lfd(dst, mem) );
5692 ins_pipe(pipe_class_memory);
5693 %}
5695 //----------Constants--------------------------------------------------------
5697 // Load MachConstantTableBase: add hi offset to global toc.
5698 // TODO: Handle hidden register r29 in bundler!
5699 instruct loadToc_hi(iRegLdst dst) %{
5700 effect(DEF dst);
5701 ins_cost(DEFAULT_COST);
5703 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5704 size(4);
5705 ins_encode %{
5706 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5707 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5708 %}
5709 ins_pipe(pipe_class_default);
5710 %}
5712 // Load MachConstantTableBase: add lo offset to global toc.
5713 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5714 effect(DEF dst, USE src);
5715 ins_cost(DEFAULT_COST);
5717 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5718 size(4);
5719 ins_encode %{
5720 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5721 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5722 %}
5723 ins_pipe(pipe_class_default);
5724 %}
5726 // Load 16-bit integer constant 0xssss????
5727 instruct loadConI16(iRegIdst dst, immI16 src) %{
5728 match(Set dst src);
5730 format %{ "LI $dst, $src" %}
5731 size(4);
5732 ins_encode %{
5733 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5734 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5735 %}
5736 ins_pipe(pipe_class_default);
5737 %}
5739 // Load integer constant 0x????0000
5740 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5741 match(Set dst src);
5742 ins_cost(DEFAULT_COST);
5744 format %{ "LIS $dst, $src.hi" %}
5745 size(4);
5746 ins_encode %{
5747 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5748 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5749 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5750 %}
5751 ins_pipe(pipe_class_default);
5752 %}
5754 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5755 // and sign extended), this adds the low 16 bits.
5756 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5757 // no match-rule, false predicate
5758 effect(DEF dst, USE src1, USE src2);
5759 predicate(false);
5761 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5762 size(4);
5763 ins_encode %{
5764 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5765 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5766 %}
5767 ins_pipe(pipe_class_default);
5768 %}
5770 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5771 match(Set dst src);
5772 ins_cost(DEFAULT_COST*2);
5774 expand %{
5775 // Would like to use $src$$constant.
5776 immI16 srcLo %{ _opnds[1]->constant() %}
5777 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5778 immIhi16 srcHi %{ _opnds[1]->constant() %}
5779 iRegIdst tmpI;
5780 loadConIhi16(tmpI, srcHi);
5781 loadConI32_lo16(dst, tmpI, srcLo);
5782 %}
5783 %}
5785 // No constant pool entries required.
5786 instruct loadConL16(iRegLdst dst, immL16 src) %{
5787 match(Set dst src);
5789 format %{ "LI $dst, $src \t// long" %}
5790 size(4);
5791 ins_encode %{
5792 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5793 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5794 %}
5795 ins_pipe(pipe_class_default);
5796 %}
5798 // Load long constant 0xssssssss????0000
5799 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5800 match(Set dst src);
5801 ins_cost(DEFAULT_COST);
5803 format %{ "LIS $dst, $src.hi \t// long" %}
5804 size(4);
5805 ins_encode %{
5806 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5807 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5808 %}
5809 ins_pipe(pipe_class_default);
5810 %}
5812 // To load a 32 bit constant: merge lower 16 bits into already loaded
5813 // high 16 bits.
5814 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5815 // no match-rule, false predicate
5816 effect(DEF dst, USE src1, USE src2);
5817 predicate(false);
5819 format %{ "ORI $dst, $src1, $src2.lo" %}
5820 size(4);
5821 ins_encode %{
5822 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5823 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5824 %}
5825 ins_pipe(pipe_class_default);
5826 %}
5828 // Load 32-bit long constant
5829 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5830 match(Set dst src);
5831 ins_cost(DEFAULT_COST*2);
5833 expand %{
5834 // Would like to use $src$$constant.
5835 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5836 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5837 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5838 iRegLdst tmpL;
5839 loadConL32hi16(tmpL, srcHi);
5840 loadConL32_lo16(dst, tmpL, srcLo);
5841 %}
5842 %}
5844 // Load long constant 0x????000000000000.
5845 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5846 match(Set dst src);
5847 ins_cost(DEFAULT_COST);
5849 expand %{
5850 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5851 immI shift32 %{ 32 %}
5852 iRegLdst tmpL;
5853 loadConL32hi16(tmpL, srcHi);
5854 lshiftL_regL_immI(dst, tmpL, shift32);
5855 %}
5856 %}
5858 // Expand node for constant pool load: small offset.
5859 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5860 effect(DEF dst, USE src, USE toc);
5861 ins_cost(MEMORY_REF_COST);
5863 ins_num_consts(1);
5864 // Needed so that CallDynamicJavaDirect can compute the address of this
5865 // instruction for relocation.
5866 ins_field_cbuf_insts_offset(int);
5868 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5869 size(4);
5870 ins_encode( enc_load_long_constL(dst, src, toc) );
5871 ins_pipe(pipe_class_memory);
5872 %}
5874 // Expand node for constant pool load: large offset.
5875 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5876 effect(DEF dst, USE src, USE toc);
5877 predicate(false);
5879 ins_num_consts(1);
5880 ins_field_const_toc_offset(int);
5881 // Needed so that CallDynamicJavaDirect can compute the address of this
5882 // instruction for relocation.
5883 ins_field_cbuf_insts_offset(int);
5885 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5886 size(4);
5887 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5888 ins_pipe(pipe_class_default);
5889 %}
5891 // Expand node for constant pool load: large offset.
5892 // No constant pool entries required.
5893 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5894 effect(DEF dst, USE src, USE base);
5895 predicate(false);
5897 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5899 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5900 size(4);
5901 ins_encode %{
5902 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5903 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5904 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5905 %}
5906 ins_pipe(pipe_class_memory);
5907 %}
5909 // Load long constant from constant table. Expand in case of
5910 // offset > 16 bit is needed.
5911 // Adlc adds toc node MachConstantTableBase.
5912 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5913 match(Set dst src);
5914 ins_cost(MEMORY_REF_COST);
5916 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5917 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5918 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5919 %}
5921 // Load NULL as compressed oop.
5922 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5923 match(Set dst src);
5924 ins_cost(DEFAULT_COST);
5926 format %{ "LI $dst, $src \t// compressed ptr" %}
5927 size(4);
5928 ins_encode %{
5929 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5930 __ li($dst$$Register, 0);
5931 %}
5932 ins_pipe(pipe_class_default);
5933 %}
5935 // Load hi part of compressed oop constant.
5936 instruct loadConN_hi(iRegNdst dst, immN src) %{
5937 effect(DEF dst, USE src);
5938 ins_cost(DEFAULT_COST);
5940 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5941 size(4);
5942 ins_encode %{
5943 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5944 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5945 %}
5946 ins_pipe(pipe_class_default);
5947 %}
5949 // Add lo part of compressed oop constant to already loaded hi part.
5950 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5951 effect(DEF dst, USE src1, USE src2);
5952 ins_cost(DEFAULT_COST);
5954 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5955 size(4);
5956 ins_encode %{
5957 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5958 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5959 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5960 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5961 __ relocate(rspec, 1);
5962 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5963 %}
5964 ins_pipe(pipe_class_default);
5965 %}
5967 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5968 // leaving the upper 32 bits with sign-extension bits.
5969 // This clears these bits: dst = src & 0xFFFFFFFF.
5970 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5971 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5972 effect(DEF dst, USE src);
5973 predicate(false);
5975 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
5976 size(4);
5977 ins_encode %{
5978 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5979 __ clrldi($dst$$Register, $src$$Register, 0x20);
5980 %}
5981 ins_pipe(pipe_class_default);
5982 %}
5984 // Loading ConN must be postalloc expanded so that edges between
5985 // the nodes are safe. They may not interfere with a safepoint.
5986 // GL TODO: This needs three instructions: better put this into the constant pool.
5987 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5988 match(Set dst src);
5989 ins_cost(DEFAULT_COST*2);
5991 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
5992 postalloc_expand %{
5993 MachNode *m1 = new (C) loadConN_hiNode();
5994 MachNode *m2 = new (C) loadConN_loNode();
5995 MachNode *m3 = new (C) clearMs32bNode();
5996 m1->add_req(NULL);
5997 m2->add_req(NULL, m1);
5998 m3->add_req(NULL, m2);
5999 m1->_opnds[0] = op_dst;
6000 m1->_opnds[1] = op_src;
6001 m2->_opnds[0] = op_dst;
6002 m2->_opnds[1] = op_dst;
6003 m2->_opnds[2] = op_src;
6004 m3->_opnds[0] = op_dst;
6005 m3->_opnds[1] = op_dst;
6006 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6007 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6008 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6009 nodes->push(m1);
6010 nodes->push(m2);
6011 nodes->push(m3);
6012 %}
6013 %}
6015 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6016 effect(DEF dst, USE src);
6017 ins_cost(DEFAULT_COST);
6019 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6020 size(4);
6021 ins_encode %{
6022 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6023 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6024 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6025 %}
6026 ins_pipe(pipe_class_default);
6027 %}
6029 // This needs a match rule so that build_oop_map knows this is
6030 // not a narrow oop.
6031 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6032 match(Set dst src1);
6033 effect(TEMP src2);
6034 ins_cost(DEFAULT_COST);
6036 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6037 size(4);
6038 ins_encode %{
6039 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6040 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6041 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6042 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6043 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6045 __ relocate(rspec, 1);
6046 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6047 %}
6048 ins_pipe(pipe_class_default);
6049 %}
6051 // Loading ConNKlass must be postalloc expanded so that edges between
6052 // the nodes are safe. They may not interfere with a safepoint.
6053 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6054 match(Set dst src);
6055 ins_cost(DEFAULT_COST*2);
6057 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6058 postalloc_expand %{
6059 // Load high bits into register. Sign extended.
6060 MachNode *m1 = new (C) loadConNKlass_hiNode();
6061 m1->add_req(NULL);
6062 m1->_opnds[0] = op_dst;
6063 m1->_opnds[1] = op_src;
6064 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6065 nodes->push(m1);
6067 MachNode *m2 = m1;
6068 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6069 // Value might be 1-extended. Mask out these bits.
6070 m2 = new (C) clearMs32bNode();
6071 m2->add_req(NULL, m1);
6072 m2->_opnds[0] = op_dst;
6073 m2->_opnds[1] = op_dst;
6074 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6075 nodes->push(m2);
6076 }
6078 MachNode *m3 = new (C) loadConNKlass_loNode();
6079 m3->add_req(NULL, m2);
6080 m3->_opnds[0] = op_dst;
6081 m3->_opnds[1] = op_src;
6082 m3->_opnds[2] = op_dst;
6083 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6084 nodes->push(m3);
6085 %}
6086 %}
6088 // 0x1 is used in object initialization (initial object header).
6089 // No constant pool entries required.
6090 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6091 match(Set dst src);
6093 format %{ "LI $dst, $src \t// ptr" %}
6094 size(4);
6095 ins_encode %{
6096 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6097 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6098 %}
6099 ins_pipe(pipe_class_default);
6100 %}
6102 // Expand node for constant pool load: small offset.
6103 // The match rule is needed to generate the correct bottom_type(),
6104 // however this node should never match. The use of predicate is not
6105 // possible since ADLC forbids predicates for chain rules. The higher
6106 // costs do not prevent matching in this case. For that reason the
6107 // operand immP_NM with predicate(false) is used.
6108 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6109 match(Set dst src);
6110 effect(TEMP toc);
6112 ins_num_consts(1);
6114 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6115 size(4);
6116 ins_encode( enc_load_long_constP(dst, src, toc) );
6117 ins_pipe(pipe_class_memory);
6118 %}
6120 // Expand node for constant pool load: large offset.
6121 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6122 effect(DEF dst, USE src, USE toc);
6123 predicate(false);
6125 ins_num_consts(1);
6126 ins_field_const_toc_offset(int);
6128 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6129 size(4);
6130 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6131 ins_pipe(pipe_class_default);
6132 %}
6134 // Expand node for constant pool load: large offset.
6135 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6136 match(Set dst src);
6137 effect(TEMP base);
6139 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6141 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6142 size(4);
6143 ins_encode %{
6144 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6145 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6146 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6147 %}
6148 ins_pipe(pipe_class_memory);
6149 %}
6151 // Load pointer constant from constant table. Expand in case an
6152 // offset > 16 bit is needed.
6153 // Adlc adds toc node MachConstantTableBase.
6154 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6155 match(Set dst src);
6156 ins_cost(MEMORY_REF_COST);
6158 // This rule does not use "expand" because then
6159 // the result type is not known to be an Oop. An ADLC
6160 // enhancement will be needed to make that work - not worth it!
6162 // If this instruction rematerializes, it prolongs the live range
6163 // of the toc node, causing illegal graphs.
6164 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6165 ins_cannot_rematerialize(true);
6167 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6168 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6169 %}
6171 // Expand node for constant pool load: small offset.
6172 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6173 effect(DEF dst, USE src, USE toc);
6174 ins_cost(MEMORY_REF_COST);
6176 ins_num_consts(1);
6178 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6179 size(4);
6180 ins_encode %{
6181 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6182 address float_address = __ float_constant($src$$constant);
6183 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6184 %}
6185 ins_pipe(pipe_class_memory);
6186 %}
6188 // Expand node for constant pool load: large offset.
6189 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6190 effect(DEF dst, USE src, USE toc);
6191 ins_cost(MEMORY_REF_COST);
6193 ins_num_consts(1);
6195 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6196 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6197 "ADDIS $toc, $toc, -offset_hi"%}
6198 size(12);
6199 ins_encode %{
6200 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6201 FloatRegister Rdst = $dst$$FloatRegister;
6202 Register Rtoc = $toc$$Register;
6203 address float_address = __ float_constant($src$$constant);
6204 int offset = __ offset_to_method_toc(float_address);
6205 int hi = (offset + (1<<15))>>16;
6206 int lo = offset - hi * (1<<16);
6208 __ addis(Rtoc, Rtoc, hi);
6209 __ lfs(Rdst, lo, Rtoc);
6210 __ addis(Rtoc, Rtoc, -hi);
6211 %}
6212 ins_pipe(pipe_class_memory);
6213 %}
6215 // Adlc adds toc node MachConstantTableBase.
6216 instruct loadConF_Ex(regF dst, immF src) %{
6217 match(Set dst src);
6218 ins_cost(MEMORY_REF_COST);
6220 // See loadConP.
6221 ins_cannot_rematerialize(true);
6223 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6224 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6225 %}
6227 // Expand node for constant pool load: small offset.
6228 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6229 effect(DEF dst, USE src, USE toc);
6230 ins_cost(MEMORY_REF_COST);
6232 ins_num_consts(1);
6234 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6235 size(4);
6236 ins_encode %{
6237 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6238 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6239 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6240 %}
6241 ins_pipe(pipe_class_memory);
6242 %}
6244 // Expand node for constant pool load: large offset.
6245 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6246 effect(DEF dst, USE src, USE toc);
6247 ins_cost(MEMORY_REF_COST);
6249 ins_num_consts(1);
6251 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6252 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6253 "ADDIS $toc, $toc, -offset_hi" %}
6254 size(12);
6255 ins_encode %{
6256 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6257 FloatRegister Rdst = $dst$$FloatRegister;
6258 Register Rtoc = $toc$$Register;
6259 address float_address = __ double_constant($src$$constant);
6260 int offset = __ offset_to_method_toc(float_address);
6261 int hi = (offset + (1<<15))>>16;
6262 int lo = offset - hi * (1<<16);
6264 __ addis(Rtoc, Rtoc, hi);
6265 __ lfd(Rdst, lo, Rtoc);
6266 __ addis(Rtoc, Rtoc, -hi);
6267 %}
6268 ins_pipe(pipe_class_memory);
6269 %}
6271 // Adlc adds toc node MachConstantTableBase.
6272 instruct loadConD_Ex(regD dst, immD src) %{
6273 match(Set dst src);
6274 ins_cost(MEMORY_REF_COST);
6276 // See loadConP.
6277 ins_cannot_rematerialize(true);
6279 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6280 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6281 %}
6283 // Prefetch instructions.
6284 // Must be safe to execute with invalid address (cannot fault).
6286 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6287 match(PrefetchRead (AddP mem src));
6288 ins_cost(MEMORY_REF_COST);
6290 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6291 size(4);
6292 ins_encode %{
6293 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6294 __ dcbt($src$$Register, $mem$$base$$Register);
6295 %}
6296 ins_pipe(pipe_class_memory);
6297 %}
6299 instruct prefetchr_no_offset(indirectMemory mem) %{
6300 match(PrefetchRead mem);
6301 ins_cost(MEMORY_REF_COST);
6303 format %{ "PREFETCH $mem" %}
6304 size(4);
6305 ins_encode %{
6306 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6307 __ dcbt($mem$$base$$Register);
6308 %}
6309 ins_pipe(pipe_class_memory);
6310 %}
6312 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6313 match(PrefetchWrite (AddP mem src));
6314 ins_cost(MEMORY_REF_COST);
6316 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6317 size(4);
6318 ins_encode %{
6319 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6320 __ dcbtst($src$$Register, $mem$$base$$Register);
6321 %}
6322 ins_pipe(pipe_class_memory);
6323 %}
6325 instruct prefetchw_no_offset(indirectMemory mem) %{
6326 match(PrefetchWrite mem);
6327 ins_cost(MEMORY_REF_COST);
6329 format %{ "PREFETCH $mem" %}
6330 size(4);
6331 ins_encode %{
6332 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6333 __ dcbtst($mem$$base$$Register);
6334 %}
6335 ins_pipe(pipe_class_memory);
6336 %}
6338 // Special prefetch versions which use the dcbz instruction.
6339 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6340 match(PrefetchAllocation (AddP mem src));
6341 predicate(AllocatePrefetchStyle == 3);
6342 ins_cost(MEMORY_REF_COST);
6344 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6345 size(4);
6346 ins_encode %{
6347 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6348 __ dcbz($src$$Register, $mem$$base$$Register);
6349 %}
6350 ins_pipe(pipe_class_memory);
6351 %}
6353 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6354 match(PrefetchAllocation mem);
6355 predicate(AllocatePrefetchStyle == 3);
6356 ins_cost(MEMORY_REF_COST);
6358 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6359 size(4);
6360 ins_encode %{
6361 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6362 __ dcbz($mem$$base$$Register);
6363 %}
6364 ins_pipe(pipe_class_memory);
6365 %}
6367 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6368 match(PrefetchAllocation (AddP mem src));
6369 predicate(AllocatePrefetchStyle != 3);
6370 ins_cost(MEMORY_REF_COST);
6372 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6373 size(4);
6374 ins_encode %{
6375 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6376 __ dcbtst($src$$Register, $mem$$base$$Register);
6377 %}
6378 ins_pipe(pipe_class_memory);
6379 %}
6381 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6382 match(PrefetchAllocation mem);
6383 predicate(AllocatePrefetchStyle != 3);
6384 ins_cost(MEMORY_REF_COST);
6386 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6387 size(4);
6388 ins_encode %{
6389 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6390 __ dcbtst($mem$$base$$Register);
6391 %}
6392 ins_pipe(pipe_class_memory);
6393 %}
6395 //----------Store Instructions-------------------------------------------------
6397 // Store Byte
6398 instruct storeB(memory mem, iRegIsrc src) %{
6399 match(Set mem (StoreB mem src));
6400 ins_cost(MEMORY_REF_COST);
6402 format %{ "STB $src, $mem \t// byte" %}
6403 size(4);
6404 ins_encode %{
6405 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6406 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6407 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6408 %}
6409 ins_pipe(pipe_class_memory);
6410 %}
6412 // Store Char/Short
6413 instruct storeC(memory mem, iRegIsrc src) %{
6414 match(Set mem (StoreC mem src));
6415 ins_cost(MEMORY_REF_COST);
6417 format %{ "STH $src, $mem \t// short" %}
6418 size(4);
6419 ins_encode %{
6420 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6421 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6422 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6423 %}
6424 ins_pipe(pipe_class_memory);
6425 %}
6427 // Store Integer
6428 instruct storeI(memory mem, iRegIsrc src) %{
6429 match(Set mem (StoreI mem src));
6430 ins_cost(MEMORY_REF_COST);
6432 format %{ "STW $src, $mem" %}
6433 size(4);
6434 ins_encode( enc_stw(src, mem) );
6435 ins_pipe(pipe_class_memory);
6436 %}
6438 // ConvL2I + StoreI.
6439 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6440 match(Set mem (StoreI mem (ConvL2I src)));
6441 ins_cost(MEMORY_REF_COST);
6443 format %{ "STW l2i($src), $mem" %}
6444 size(4);
6445 ins_encode( enc_stw(src, mem) );
6446 ins_pipe(pipe_class_memory);
6447 %}
6449 // Store Long
6450 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6451 match(Set mem (StoreL mem src));
6452 ins_cost(MEMORY_REF_COST);
6454 format %{ "STD $src, $mem \t// long" %}
6455 size(4);
6456 ins_encode( enc_std(src, mem) );
6457 ins_pipe(pipe_class_memory);
6458 %}
6460 // Store super word nodes.
6462 // Store Aligned Packed Byte long register to memory
6463 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6464 predicate(n->as_StoreVector()->memory_size() == 8);
6465 match(Set mem (StoreVector mem src));
6466 ins_cost(MEMORY_REF_COST);
6468 format %{ "STD $mem, $src \t// packed8B" %}
6469 size(4);
6470 ins_encode( enc_std(src, mem) );
6471 ins_pipe(pipe_class_memory);
6472 %}
6474 // Store Compressed Oop
6475 instruct storeN(memory dst, iRegN_P2N src) %{
6476 match(Set dst (StoreN dst src));
6477 ins_cost(MEMORY_REF_COST);
6479 format %{ "STW $src, $dst \t// compressed oop" %}
6480 size(4);
6481 ins_encode( enc_stw(src, dst) );
6482 ins_pipe(pipe_class_memory);
6483 %}
6485 // Store Compressed KLass
6486 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6487 match(Set dst (StoreNKlass dst src));
6488 ins_cost(MEMORY_REF_COST);
6490 format %{ "STW $src, $dst \t// compressed klass" %}
6491 size(4);
6492 ins_encode( enc_stw(src, dst) );
6493 ins_pipe(pipe_class_memory);
6494 %}
6496 // Store Pointer
6497 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6498 match(Set dst (StoreP dst src));
6499 ins_cost(MEMORY_REF_COST);
6501 format %{ "STD $src, $dst \t// ptr" %}
6502 size(4);
6503 ins_encode( enc_std(src, dst) );
6504 ins_pipe(pipe_class_memory);
6505 %}
6507 // Store Float
6508 instruct storeF(memory mem, regF src) %{
6509 match(Set mem (StoreF mem src));
6510 ins_cost(MEMORY_REF_COST);
6512 format %{ "STFS $src, $mem" %}
6513 size(4);
6514 ins_encode( enc_stfs(src, mem) );
6515 ins_pipe(pipe_class_memory);
6516 %}
6518 // Store Double
6519 instruct storeD(memory mem, regD src) %{
6520 match(Set mem (StoreD mem src));
6521 ins_cost(MEMORY_REF_COST);
6523 format %{ "STFD $src, $mem" %}
6524 size(4);
6525 ins_encode( enc_stfd(src, mem) );
6526 ins_pipe(pipe_class_memory);
6527 %}
6529 //----------Store Instructions With Zeros--------------------------------------
6531 // Card-mark for CMS garbage collection.
6532 // This cardmark does an optimization so that it must not always
6533 // do a releasing store. For this, it gets the address of
6534 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6535 // (Using releaseFieldAddr in the match rule is a hack.)
6536 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6537 match(Set mem (StoreCM mem releaseFieldAddr));
6538 predicate(false);
6539 ins_cost(MEMORY_REF_COST);
6541 // See loadConP.
6542 ins_cannot_rematerialize(true);
6544 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6545 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6546 ins_pipe(pipe_class_memory);
6547 %}
6549 // Card-mark for CMS garbage collection.
6550 // This cardmark does an optimization so that it must not always
6551 // do a releasing store. For this, it needs the constant address of
6552 // CMSCollectorCardTableModRefBSExt::_requires_release.
6553 // This constant address is split off here by expand so we can use
6554 // adlc / matcher functionality to load it from the constant section.
6555 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6556 match(Set mem (StoreCM mem zero));
6557 predicate(UseConcMarkSweepGC);
6559 expand %{
6560 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6561 iRegLdst releaseFieldAddress;
6562 loadConL_Ex(releaseFieldAddress, baseImm);
6563 storeCM_CMS(mem, releaseFieldAddress);
6564 %}
6565 %}
6567 instruct storeCM_G1(memory mem, immI_0 zero) %{
6568 match(Set mem (StoreCM mem zero));
6569 predicate(UseG1GC);
6570 ins_cost(MEMORY_REF_COST);
6572 ins_cannot_rematerialize(true);
6574 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6575 size(8);
6576 ins_encode %{
6577 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6578 __ li(R0, 0);
6579 //__ release(); // G1: oops are allowed to get visible after dirty marking
6580 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6581 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6582 %}
6583 ins_pipe(pipe_class_memory);
6584 %}
6586 // Convert oop pointer into compressed form.
6588 // Nodes for postalloc expand.
6590 // Shift node for expand.
6591 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6592 // The match rule is needed to make it a 'MachTypeNode'!
6593 match(Set dst (EncodeP src));
6594 predicate(false);
6596 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6597 size(4);
6598 ins_encode %{
6599 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6600 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6601 %}
6602 ins_pipe(pipe_class_default);
6603 %}
6605 // Add node for expand.
6606 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6607 // The match rule is needed to make it a 'MachTypeNode'!
6608 match(Set dst (EncodeP src));
6609 predicate(false);
6611 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6612 size(4);
6613 ins_encode %{
6614 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6615 __ subf($dst$$Register, R30, $src$$Register);
6616 %}
6617 ins_pipe(pipe_class_default);
6618 %}
6620 // Conditional sub base.
6621 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6622 // The match rule is needed to make it a 'MachTypeNode'!
6623 match(Set dst (EncodeP (Binary crx src1)));
6624 predicate(false);
6626 ins_variable_size_depending_on_alignment(true);
6628 format %{ "BEQ $crx, done\n\t"
6629 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6630 "done:" %}
6631 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6632 ins_encode %{
6633 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6634 Label done;
6635 __ beq($crx$$CondRegister, done);
6636 __ subf($dst$$Register, R30, $src1$$Register);
6637 // TODO PPC port __ endgroup_if_needed(_size == 12);
6638 __ bind(done);
6639 %}
6640 ins_pipe(pipe_class_default);
6641 %}
6643 // Power 7 can use isel instruction
6644 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6645 // The match rule is needed to make it a 'MachTypeNode'!
6646 match(Set dst (EncodeP (Binary crx src1)));
6647 predicate(false);
6649 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6650 size(4);
6651 ins_encode %{
6652 // This is a Power7 instruction for which no machine description exists.
6653 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6654 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6655 %}
6656 ins_pipe(pipe_class_default);
6657 %}
6659 // base != 0
6660 // 32G aligned narrow oop base.
6661 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6662 match(Set dst (EncodeP src));
6663 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6665 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6666 size(4);
6667 ins_encode %{
6668 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6669 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6670 %}
6671 ins_pipe(pipe_class_default);
6672 %}
6674 // shift != 0, base != 0
6675 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6676 match(Set dst (EncodeP src));
6677 effect(TEMP crx);
6678 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6679 Universe::narrow_oop_shift() != 0 &&
6680 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6682 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6683 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6684 %}
6686 // shift != 0, base != 0
6687 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6688 match(Set dst (EncodeP src));
6689 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6690 Universe::narrow_oop_shift() != 0 &&
6691 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6693 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6694 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6695 %}
6697 // shift != 0, base == 0
6698 // TODO: This is the same as encodeP_shift. Merge!
6699 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6700 match(Set dst (EncodeP src));
6701 predicate(Universe::narrow_oop_shift() != 0 &&
6702 Universe::narrow_oop_base() ==0);
6704 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6705 size(4);
6706 ins_encode %{
6707 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6708 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6709 %}
6710 ins_pipe(pipe_class_default);
6711 %}
6713 // Compressed OOPs with narrow_oop_shift == 0.
6714 // shift == 0, base == 0
6715 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6716 match(Set dst (EncodeP src));
6717 predicate(Universe::narrow_oop_shift() == 0);
6719 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6720 // variable size, 0 or 4.
6721 ins_encode %{
6722 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6723 __ mr_if_needed($dst$$Register, $src$$Register);
6724 %}
6725 ins_pipe(pipe_class_default);
6726 %}
6728 // Decode nodes.
6730 // Shift node for expand.
6731 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6732 // The match rule is needed to make it a 'MachTypeNode'!
6733 match(Set dst (DecodeN src));
6734 predicate(false);
6736 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6737 size(4);
6738 ins_encode %{
6739 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6740 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6741 %}
6742 ins_pipe(pipe_class_default);
6743 %}
6745 // Add node for expand.
6746 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6747 // The match rule is needed to make it a 'MachTypeNode'!
6748 match(Set dst (DecodeN src));
6749 predicate(false);
6751 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6752 size(4);
6753 ins_encode %{
6754 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6755 __ add($dst$$Register, $src$$Register, R30);
6756 %}
6757 ins_pipe(pipe_class_default);
6758 %}
6760 // conditianal add base for expand
6761 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6762 // The match rule is needed to make it a 'MachTypeNode'!
6763 // NOTICE that the rule is nonsense - we just have to make sure that:
6764 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6765 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6766 match(Set dst (DecodeN (Binary crx src1)));
6767 predicate(false);
6769 ins_variable_size_depending_on_alignment(true);
6771 format %{ "BEQ $crx, done\n\t"
6772 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6773 "done:" %}
6774 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6775 ins_encode %{
6776 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6777 Label done;
6778 __ beq($crx$$CondRegister, done);
6779 __ add($dst$$Register, $src1$$Register, R30);
6780 // TODO PPC port __ endgroup_if_needed(_size == 12);
6781 __ bind(done);
6782 %}
6783 ins_pipe(pipe_class_default);
6784 %}
6786 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6787 // The match rule is needed to make it a 'MachTypeNode'!
6788 // NOTICE that the rule is nonsense - we just have to make sure that:
6789 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6790 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6791 match(Set dst (DecodeN (Binary crx src1)));
6792 predicate(false);
6794 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6795 size(4);
6796 ins_encode %{
6797 // This is a Power7 instruction for which no machine description exists.
6798 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6799 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6800 %}
6801 ins_pipe(pipe_class_default);
6802 %}
6804 // shift != 0, base != 0
6805 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6806 match(Set dst (DecodeN src));
6807 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6808 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6809 Universe::narrow_oop_shift() != 0 &&
6810 Universe::narrow_oop_base() != 0);
6811 effect(TEMP crx);
6813 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6814 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6815 %}
6817 // shift != 0, base == 0
6818 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6819 match(Set dst (DecodeN src));
6820 predicate(Universe::narrow_oop_shift() != 0 &&
6821 Universe::narrow_oop_base() == 0);
6823 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6824 size(4);
6825 ins_encode %{
6826 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6827 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6828 %}
6829 ins_pipe(pipe_class_default);
6830 %}
6832 // src != 0, shift != 0, base != 0
6833 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6834 match(Set dst (DecodeN src));
6835 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6836 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6837 Universe::narrow_oop_shift() != 0 &&
6838 Universe::narrow_oop_base() != 0);
6840 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6841 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6842 %}
6844 // Compressed OOPs with narrow_oop_shift == 0.
6845 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6846 match(Set dst (DecodeN src));
6847 predicate(Universe::narrow_oop_shift() == 0);
6848 ins_cost(DEFAULT_COST);
6850 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6851 // variable size, 0 or 4.
6852 ins_encode %{
6853 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6854 __ mr_if_needed($dst$$Register, $src$$Register);
6855 %}
6856 ins_pipe(pipe_class_default);
6857 %}
6859 // Convert compressed oop into int for vectors alignment masking.
6860 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6861 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6862 predicate(Universe::narrow_oop_shift() == 0);
6863 ins_cost(DEFAULT_COST);
6865 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6866 // variable size, 0 or 4.
6867 ins_encode %{
6868 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6869 __ mr_if_needed($dst$$Register, $src$$Register);
6870 %}
6871 ins_pipe(pipe_class_default);
6872 %}
6874 // Convert klass pointer into compressed form.
6876 // Nodes for postalloc expand.
6878 // Shift node for expand.
6879 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6880 // The match rule is needed to make it a 'MachTypeNode'!
6881 match(Set dst (EncodePKlass src));
6882 predicate(false);
6884 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6885 size(4);
6886 ins_encode %{
6887 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6888 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6889 %}
6890 ins_pipe(pipe_class_default);
6891 %}
6893 // Add node for expand.
6894 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6895 // The match rule is needed to make it a 'MachTypeNode'!
6896 match(Set dst (EncodePKlass (Binary base src)));
6897 predicate(false);
6899 format %{ "SUB $dst, $base, $src \t// encode" %}
6900 size(4);
6901 ins_encode %{
6902 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6903 __ subf($dst$$Register, $base$$Register, $src$$Register);
6904 %}
6905 ins_pipe(pipe_class_default);
6906 %}
6908 // base != 0
6909 // 32G aligned narrow oop base.
6910 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6911 match(Set dst (EncodePKlass src));
6912 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6914 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6915 size(4);
6916 ins_encode %{
6917 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6918 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6919 %}
6920 ins_pipe(pipe_class_default);
6921 %}
6923 // shift != 0, base != 0
6924 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6925 match(Set dst (EncodePKlass (Binary base src)));
6926 predicate(false);
6928 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6929 postalloc_expand %{
6930 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
6931 n1->add_req(n_region, n_base, n_src);
6932 n1->_opnds[0] = op_dst;
6933 n1->_opnds[1] = op_base;
6934 n1->_opnds[2] = op_src;
6935 n1->_bottom_type = _bottom_type;
6937 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
6938 n2->add_req(n_region, n1);
6939 n2->_opnds[0] = op_dst;
6940 n2->_opnds[1] = op_dst;
6941 n2->_bottom_type = _bottom_type;
6942 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6943 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6945 nodes->push(n1);
6946 nodes->push(n2);
6947 %}
6948 %}
6950 // shift != 0, base != 0
6951 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
6952 match(Set dst (EncodePKlass src));
6953 //predicate(Universe::narrow_klass_shift() != 0 &&
6954 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
6956 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6957 ins_cost(DEFAULT_COST*2); // Don't count constant.
6958 expand %{
6959 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
6960 iRegLdst base;
6961 loadConL_Ex(base, baseImm);
6962 encodePKlass_not_null_Ex(dst, base, src);
6963 %}
6964 %}
6966 // Decode nodes.
6968 // Shift node for expand.
6969 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
6970 // The match rule is needed to make it a 'MachTypeNode'!
6971 match(Set dst (DecodeNKlass src));
6972 predicate(false);
6974 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
6975 size(4);
6976 ins_encode %{
6977 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6978 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6979 %}
6980 ins_pipe(pipe_class_default);
6981 %}
6983 // Add node for expand.
6985 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6986 // The match rule is needed to make it a 'MachTypeNode'!
6987 match(Set dst (DecodeNKlass (Binary base src)));
6988 predicate(false);
6990 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
6991 size(4);
6992 ins_encode %{
6993 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6994 __ add($dst$$Register, $base$$Register, $src$$Register);
6995 %}
6996 ins_pipe(pipe_class_default);
6997 %}
6999 // src != 0, shift != 0, base != 0
7000 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7001 match(Set dst (DecodeNKlass (Binary base src)));
7002 //effect(kill src); // We need a register for the immediate result after shifting.
7003 predicate(false);
7005 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7006 postalloc_expand %{
7007 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7008 n1->add_req(n_region, n_base, n_src);
7009 n1->_opnds[0] = op_dst;
7010 n1->_opnds[1] = op_base;
7011 n1->_opnds[2] = op_src;
7012 n1->_bottom_type = _bottom_type;
7014 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7015 n2->add_req(n_region, n2);
7016 n2->_opnds[0] = op_dst;
7017 n2->_opnds[1] = op_dst;
7018 n2->_bottom_type = _bottom_type;
7020 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7021 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7023 nodes->push(n1);
7024 nodes->push(n2);
7025 %}
7026 %}
7028 // src != 0, shift != 0, base != 0
7029 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7030 match(Set dst (DecodeNKlass src));
7031 // predicate(Universe::narrow_klass_shift() != 0 &&
7032 // Universe::narrow_klass_base() != 0);
7034 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7036 ins_cost(DEFAULT_COST*2); // Don't count constant.
7037 expand %{
7038 // We add first, then we shift. Like this, we can get along with one register less.
7039 // But we have to load the base pre-shifted.
7040 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7041 iRegLdst base;
7042 loadConL_Ex(base, baseImm);
7043 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7044 %}
7045 %}
7047 //----------MemBar Instructions-----------------------------------------------
7048 // Memory barrier flavors
7050 instruct membar_acquire() %{
7051 match(LoadFence);
7052 ins_cost(4*MEMORY_REF_COST);
7054 format %{ "MEMBAR-acquire" %}
7055 size(4);
7056 ins_encode %{
7057 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7058 __ acquire();
7059 %}
7060 ins_pipe(pipe_class_default);
7061 %}
7063 instruct unnecessary_membar_acquire() %{
7064 match(MemBarAcquire);
7065 ins_cost(0);
7067 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7068 size(0);
7069 ins_encode( /*empty*/ );
7070 ins_pipe(pipe_class_default);
7071 %}
7073 instruct membar_acquire_lock() %{
7074 match(MemBarAcquireLock);
7075 ins_cost(0);
7077 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7078 size(0);
7079 ins_encode( /*empty*/ );
7080 ins_pipe(pipe_class_default);
7081 %}
7083 instruct membar_release() %{
7084 match(MemBarRelease);
7085 match(StoreFence);
7086 ins_cost(4*MEMORY_REF_COST);
7088 format %{ "MEMBAR-release" %}
7089 size(4);
7090 ins_encode %{
7091 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7092 __ release();
7093 %}
7094 ins_pipe(pipe_class_default);
7095 %}
7097 instruct membar_storestore() %{
7098 match(MemBarStoreStore);
7099 ins_cost(4*MEMORY_REF_COST);
7101 format %{ "MEMBAR-store-store" %}
7102 size(4);
7103 ins_encode %{
7104 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7105 __ membar(Assembler::StoreStore);
7106 %}
7107 ins_pipe(pipe_class_default);
7108 %}
7110 instruct membar_release_lock() %{
7111 match(MemBarReleaseLock);
7112 ins_cost(0);
7114 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7115 size(0);
7116 ins_encode( /*empty*/ );
7117 ins_pipe(pipe_class_default);
7118 %}
7120 instruct membar_volatile() %{
7121 match(MemBarVolatile);
7122 ins_cost(4*MEMORY_REF_COST);
7124 format %{ "MEMBAR-volatile" %}
7125 size(4);
7126 ins_encode %{
7127 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7128 __ fence();
7129 %}
7130 ins_pipe(pipe_class_default);
7131 %}
7133 // This optimization is wrong on PPC. The following pattern is not supported:
7134 // MemBarVolatile
7135 // ^ ^
7136 // | |
7137 // CtrlProj MemProj
7138 // ^ ^
7139 // | |
7140 // | Load
7141 // |
7142 // MemBarVolatile
7143 //
7144 // The first MemBarVolatile could get optimized out! According to
7145 // Vladimir, this pattern can not occur on Oracle platforms.
7146 // However, it does occur on PPC64 (because of membars in
7147 // inline_unsafe_load_store).
7148 //
7149 // Add this node again if we found a good solution for inline_unsafe_load_store().
7150 // Don't forget to look at the implementation of post_store_load_barrier again,
7151 // we did other fixes in that method.
7152 //instruct unnecessary_membar_volatile() %{
7153 // match(MemBarVolatile);
7154 // predicate(Matcher::post_store_load_barrier(n));
7155 // ins_cost(0);
7156 //
7157 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7158 // size(0);
7159 // ins_encode( /*empty*/ );
7160 // ins_pipe(pipe_class_default);
7161 //%}
7163 instruct membar_CPUOrder() %{
7164 match(MemBarCPUOrder);
7165 ins_cost(0);
7167 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7168 size(0);
7169 ins_encode( /*empty*/ );
7170 ins_pipe(pipe_class_default);
7171 %}
7173 //----------Conditional Move---------------------------------------------------
7175 // Cmove using isel.
7176 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7177 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7178 predicate(VM_Version::has_isel());
7179 ins_cost(DEFAULT_COST);
7181 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7182 size(4);
7183 ins_encode %{
7184 // This is a Power7 instruction for which no machine description
7185 // exists. Anyways, the scheduler should be off on Power7.
7186 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7187 int cc = $cmp$$cmpcode;
7188 __ isel($dst$$Register, $crx$$CondRegister,
7189 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7190 %}
7191 ins_pipe(pipe_class_default);
7192 %}
7194 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7195 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7196 predicate(!VM_Version::has_isel());
7197 ins_cost(DEFAULT_COST+BRANCH_COST);
7199 ins_variable_size_depending_on_alignment(true);
7201 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7202 // Worst case is branch + move + stop, no stop without scheduler
7203 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7204 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7205 ins_pipe(pipe_class_default);
7206 %}
7208 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7209 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7210 ins_cost(DEFAULT_COST+BRANCH_COST);
7212 ins_variable_size_depending_on_alignment(true);
7214 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7215 // Worst case is branch + move + stop, no stop without scheduler
7216 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7217 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7218 ins_pipe(pipe_class_default);
7219 %}
7221 // Cmove using isel.
7222 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7223 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7224 predicate(VM_Version::has_isel());
7225 ins_cost(DEFAULT_COST);
7227 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7228 size(4);
7229 ins_encode %{
7230 // This is a Power7 instruction for which no machine description
7231 // exists. Anyways, the scheduler should be off on Power7.
7232 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7233 int cc = $cmp$$cmpcode;
7234 __ isel($dst$$Register, $crx$$CondRegister,
7235 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7236 %}
7237 ins_pipe(pipe_class_default);
7238 %}
7240 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7241 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7242 predicate(!VM_Version::has_isel());
7243 ins_cost(DEFAULT_COST+BRANCH_COST);
7245 ins_variable_size_depending_on_alignment(true);
7247 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7248 // Worst case is branch + move + stop, no stop without scheduler.
7249 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7250 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7251 ins_pipe(pipe_class_default);
7252 %}
7254 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7255 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7256 ins_cost(DEFAULT_COST+BRANCH_COST);
7258 ins_variable_size_depending_on_alignment(true);
7260 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7261 // Worst case is branch + move + stop, no stop without scheduler.
7262 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7263 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7264 ins_pipe(pipe_class_default);
7265 %}
7267 // Cmove using isel.
7268 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7269 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7270 predicate(VM_Version::has_isel());
7271 ins_cost(DEFAULT_COST);
7273 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7274 size(4);
7275 ins_encode %{
7276 // This is a Power7 instruction for which no machine description
7277 // exists. Anyways, the scheduler should be off on Power7.
7278 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7279 int cc = $cmp$$cmpcode;
7280 __ isel($dst$$Register, $crx$$CondRegister,
7281 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7282 %}
7283 ins_pipe(pipe_class_default);
7284 %}
7286 // Conditional move for RegN. Only cmov(reg, reg).
7287 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7288 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7289 predicate(!VM_Version::has_isel());
7290 ins_cost(DEFAULT_COST+BRANCH_COST);
7292 ins_variable_size_depending_on_alignment(true);
7294 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7295 // Worst case is branch + move + stop, no stop without scheduler.
7296 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7297 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7298 ins_pipe(pipe_class_default);
7299 %}
7301 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7302 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7303 ins_cost(DEFAULT_COST+BRANCH_COST);
7305 ins_variable_size_depending_on_alignment(true);
7307 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7308 // Worst case is branch + move + stop, no stop without scheduler.
7309 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7310 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7311 ins_pipe(pipe_class_default);
7312 %}
7314 // Cmove using isel.
7315 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7316 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7317 predicate(VM_Version::has_isel());
7318 ins_cost(DEFAULT_COST);
7320 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7321 size(4);
7322 ins_encode %{
7323 // This is a Power7 instruction for which no machine description
7324 // exists. Anyways, the scheduler should be off on Power7.
7325 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7326 int cc = $cmp$$cmpcode;
7327 __ isel($dst$$Register, $crx$$CondRegister,
7328 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7329 %}
7330 ins_pipe(pipe_class_default);
7331 %}
7333 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7334 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7335 predicate(!VM_Version::has_isel());
7336 ins_cost(DEFAULT_COST+BRANCH_COST);
7338 ins_variable_size_depending_on_alignment(true);
7340 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7341 // Worst case is branch + move + stop, no stop without scheduler.
7342 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7343 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7344 ins_pipe(pipe_class_default);
7345 %}
7347 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7348 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7349 ins_cost(DEFAULT_COST+BRANCH_COST);
7351 ins_variable_size_depending_on_alignment(true);
7353 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7354 // Worst case is branch + move + stop, no stop without scheduler.
7355 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7356 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7357 ins_pipe(pipe_class_default);
7358 %}
7360 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7361 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7362 ins_cost(DEFAULT_COST+BRANCH_COST);
7364 ins_variable_size_depending_on_alignment(true);
7366 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7367 // Worst case is branch + move + stop, no stop without scheduler.
7368 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7369 ins_encode %{
7370 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7371 Label done;
7372 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7373 // Branch if not (cmp crx).
7374 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7375 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7376 // TODO PPC port __ endgroup_if_needed(_size == 12);
7377 __ bind(done);
7378 %}
7379 ins_pipe(pipe_class_default);
7380 %}
7382 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7383 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7384 ins_cost(DEFAULT_COST+BRANCH_COST);
7386 ins_variable_size_depending_on_alignment(true);
7388 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7389 // Worst case is branch + move + stop, no stop without scheduler.
7390 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7391 ins_encode %{
7392 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7393 Label done;
7394 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7395 // Branch if not (cmp crx).
7396 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7397 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7398 // TODO PPC port __ endgroup_if_needed(_size == 12);
7399 __ bind(done);
7400 %}
7401 ins_pipe(pipe_class_default);
7402 %}
7404 //----------Conditional_store--------------------------------------------------
7405 // Conditional-store of the updated heap-top.
7406 // Used during allocation of the shared heap.
7407 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7409 // As compareAndSwapL, but return flag register instead of boolean value in
7410 // int register.
7411 // Used by sun/misc/AtomicLongCSImpl.java.
7412 // Mem_ptr must be a memory operand, else this node does not get
7413 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7414 // can be rematerialized which leads to errors.
7415 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7416 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7417 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7418 ins_encode %{
7419 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7420 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7421 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7422 noreg, NULL, true);
7423 %}
7424 ins_pipe(pipe_class_default);
7425 %}
7427 // As compareAndSwapP, but return flag register instead of boolean value in
7428 // int register.
7429 // This instruction is matched if UseTLAB is off.
7430 // Mem_ptr must be a memory operand, else this node does not get
7431 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7432 // can be rematerialized which leads to errors.
7433 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7434 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7435 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7436 ins_encode %{
7437 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7438 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7439 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7440 noreg, NULL, true);
7441 %}
7442 ins_pipe(pipe_class_default);
7443 %}
7445 // Implement LoadPLocked. Must be ordered against changes of the memory location
7446 // by storePConditional.
7447 // Don't know whether this is ever used.
7448 instruct loadPLocked(iRegPdst dst, memory mem) %{
7449 match(Set dst (LoadPLocked mem));
7450 ins_cost(MEMORY_REF_COST);
7452 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7453 "TWI $dst\n\t"
7454 "ISYNC" %}
7455 size(12);
7456 ins_encode( enc_ld_ac(dst, mem) );
7457 ins_pipe(pipe_class_memory);
7458 %}
7460 //----------Compare-And-Swap---------------------------------------------------
7462 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7463 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7464 // matched.
7466 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7467 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7468 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7469 // Variable size: instruction count smaller if regs are disjoint.
7470 ins_encode %{
7471 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7472 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7473 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7474 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7475 $res$$Register, true);
7476 %}
7477 ins_pipe(pipe_class_default);
7478 %}
7480 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7481 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7482 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7483 // Variable size: instruction count smaller if regs are disjoint.
7484 ins_encode %{
7485 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7486 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7487 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7488 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7489 $res$$Register, true);
7490 %}
7491 ins_pipe(pipe_class_default);
7492 %}
7494 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7495 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7496 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7497 // Variable size: instruction count smaller if regs are disjoint.
7498 ins_encode %{
7499 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7500 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7501 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7502 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7503 $res$$Register, NULL, true);
7504 %}
7505 ins_pipe(pipe_class_default);
7506 %}
7508 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7509 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7510 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7511 // Variable size: instruction count smaller if regs are disjoint.
7512 ins_encode %{
7513 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7514 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7515 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7516 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7517 $res$$Register, NULL, true);
7518 %}
7519 ins_pipe(pipe_class_default);
7520 %}
7522 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7523 match(Set res (GetAndAddI mem_ptr src));
7524 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7525 // Variable size: instruction count smaller if regs are disjoint.
7526 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7527 ins_pipe(pipe_class_default);
7528 %}
7530 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7531 match(Set res (GetAndAddL mem_ptr src));
7532 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7533 // Variable size: instruction count smaller if regs are disjoint.
7534 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7535 ins_pipe(pipe_class_default);
7536 %}
7538 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7539 match(Set res (GetAndSetI mem_ptr src));
7540 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7541 // Variable size: instruction count smaller if regs are disjoint.
7542 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7543 ins_pipe(pipe_class_default);
7544 %}
7546 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7547 match(Set res (GetAndSetL mem_ptr src));
7548 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7549 // Variable size: instruction count smaller if regs are disjoint.
7550 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7551 ins_pipe(pipe_class_default);
7552 %}
7554 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7555 match(Set res (GetAndSetP mem_ptr src));
7556 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7557 // Variable size: instruction count smaller if regs are disjoint.
7558 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7559 ins_pipe(pipe_class_default);
7560 %}
7562 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7563 match(Set res (GetAndSetN mem_ptr src));
7564 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7565 // Variable size: instruction count smaller if regs are disjoint.
7566 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7567 ins_pipe(pipe_class_default);
7568 %}
7570 //----------Arithmetic Instructions--------------------------------------------
7571 // Addition Instructions
7573 // PPC has no instruction setting overflow of 32-bit integer.
7574 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{
7575 // match(AddExactI dst src);
7576 // effect(DEF cr);
7577 //
7578 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %}
7579 // ins_encode( enc_add(dst, dst, src) );
7580 // ins_pipe(pipe_class_default);
7581 //%}
7583 // Register Addition
7584 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7585 match(Set dst (AddI src1 src2));
7586 format %{ "ADD $dst, $src1, $src2" %}
7587 size(4);
7588 ins_encode %{
7589 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7590 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7591 %}
7592 ins_pipe(pipe_class_default);
7593 %}
7595 // Expand does not work with above instruct. (??)
7596 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7597 // no match-rule
7598 effect(DEF dst, USE src1, USE src2);
7599 format %{ "ADD $dst, $src1, $src2" %}
7600 size(4);
7601 ins_encode %{
7602 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7603 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7604 %}
7605 ins_pipe(pipe_class_default);
7606 %}
7608 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7609 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7610 ins_cost(DEFAULT_COST*3);
7612 expand %{
7613 // FIXME: we should do this in the ideal world.
7614 iRegIdst tmp1;
7615 iRegIdst tmp2;
7616 addI_reg_reg(tmp1, src1, src2);
7617 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7618 addI_reg_reg(dst, tmp1, tmp2);
7619 %}
7620 %}
7622 // Immediate Addition
7623 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7624 match(Set dst (AddI src1 src2));
7625 format %{ "ADDI $dst, $src1, $src2" %}
7626 size(4);
7627 ins_encode %{
7628 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7629 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7630 %}
7631 ins_pipe(pipe_class_default);
7632 %}
7634 // Immediate Addition with 16-bit shifted operand
7635 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7636 match(Set dst (AddI src1 src2));
7637 format %{ "ADDIS $dst, $src1, $src2" %}
7638 size(4);
7639 ins_encode %{
7640 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7641 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7642 %}
7643 ins_pipe(pipe_class_default);
7644 %}
7646 // Long Addition
7647 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7648 match(Set dst (AddL src1 src2));
7649 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7650 size(4);
7651 ins_encode %{
7652 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7653 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7654 %}
7655 ins_pipe(pipe_class_default);
7656 %}
7658 // Expand does not work with above instruct. (??)
7659 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7660 // no match-rule
7661 effect(DEF dst, USE src1, USE src2);
7662 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7663 size(4);
7664 ins_encode %{
7665 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7666 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7667 %}
7668 ins_pipe(pipe_class_default);
7669 %}
7671 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7672 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7673 ins_cost(DEFAULT_COST*3);
7675 expand %{
7676 // FIXME: we should do this in the ideal world.
7677 iRegLdst tmp1;
7678 iRegLdst tmp2;
7679 addL_reg_reg(tmp1, src1, src2);
7680 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7681 addL_reg_reg(dst, tmp1, tmp2);
7682 %}
7683 %}
7685 // AddL + ConvL2I.
7686 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7687 match(Set dst (ConvL2I (AddL src1 src2)));
7689 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7690 size(4);
7691 ins_encode %{
7692 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7693 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7694 %}
7695 ins_pipe(pipe_class_default);
7696 %}
7698 // No constant pool entries required.
7699 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7700 match(Set dst (AddL src1 src2));
7702 format %{ "ADDI $dst, $src1, $src2" %}
7703 size(4);
7704 ins_encode %{
7705 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7706 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7707 %}
7708 ins_pipe(pipe_class_default);
7709 %}
7711 // Long Immediate Addition with 16-bit shifted operand.
7712 // No constant pool entries required.
7713 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7714 match(Set dst (AddL src1 src2));
7716 format %{ "ADDIS $dst, $src1, $src2" %}
7717 size(4);
7718 ins_encode %{
7719 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7720 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7721 %}
7722 ins_pipe(pipe_class_default);
7723 %}
7725 // Pointer Register Addition
7726 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7727 match(Set dst (AddP src1 src2));
7728 format %{ "ADD $dst, $src1, $src2" %}
7729 size(4);
7730 ins_encode %{
7731 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7732 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7733 %}
7734 ins_pipe(pipe_class_default);
7735 %}
7737 // Pointer Immediate Addition
7738 // No constant pool entries required.
7739 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7740 match(Set dst (AddP src1 src2));
7742 format %{ "ADDI $dst, $src1, $src2" %}
7743 size(4);
7744 ins_encode %{
7745 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7746 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7747 %}
7748 ins_pipe(pipe_class_default);
7749 %}
7751 // Pointer Immediate Addition with 16-bit shifted operand.
7752 // No constant pool entries required.
7753 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7754 match(Set dst (AddP src1 src2));
7756 format %{ "ADDIS $dst, $src1, $src2" %}
7757 size(4);
7758 ins_encode %{
7759 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7760 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7761 %}
7762 ins_pipe(pipe_class_default);
7763 %}
7765 //---------------------
7766 // Subtraction Instructions
7768 // Register Subtraction
7769 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7770 match(Set dst (SubI src1 src2));
7771 format %{ "SUBF $dst, $src2, $src1" %}
7772 size(4);
7773 ins_encode %{
7774 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7775 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7776 %}
7777 ins_pipe(pipe_class_default);
7778 %}
7780 // Immediate Subtraction
7781 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7782 // so this rule seems to be unused.
7783 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7784 match(Set dst (SubI src1 src2));
7785 format %{ "SUBI $dst, $src1, $src2" %}
7786 size(4);
7787 ins_encode %{
7788 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7789 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7790 %}
7791 ins_pipe(pipe_class_default);
7792 %}
7794 // SubI from constant (using subfic).
7795 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7796 match(Set dst (SubI src1 src2));
7797 format %{ "SUBI $dst, $src1, $src2" %}
7799 size(4);
7800 ins_encode %{
7801 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7802 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7803 %}
7804 ins_pipe(pipe_class_default);
7805 %}
7807 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7808 // positive integers and 0xF...F for negative ones.
7809 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7810 // no match-rule, false predicate
7811 effect(DEF dst, USE src);
7812 predicate(false);
7814 format %{ "SRAWI $dst, $src, #31" %}
7815 size(4);
7816 ins_encode %{
7817 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7818 __ srawi($dst$$Register, $src$$Register, 0x1f);
7819 %}
7820 ins_pipe(pipe_class_default);
7821 %}
7823 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7824 match(Set dst (AbsI src));
7825 ins_cost(DEFAULT_COST*3);
7827 expand %{
7828 iRegIdst tmp1;
7829 iRegIdst tmp2;
7830 signmask32I_regI(tmp1, src);
7831 xorI_reg_reg(tmp2, tmp1, src);
7832 subI_reg_reg(dst, tmp2, tmp1);
7833 %}
7834 %}
7836 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7837 match(Set dst (SubI zero src2));
7838 format %{ "NEG $dst, $src2" %}
7839 size(4);
7840 ins_encode %{
7841 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7842 __ neg($dst$$Register, $src2$$Register);
7843 %}
7844 ins_pipe(pipe_class_default);
7845 %}
7847 // Long subtraction
7848 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7849 match(Set dst (SubL src1 src2));
7850 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7851 size(4);
7852 ins_encode %{
7853 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7854 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7855 %}
7856 ins_pipe(pipe_class_default);
7857 %}
7859 // SubL + convL2I.
7860 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7861 match(Set dst (ConvL2I (SubL src1 src2)));
7863 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7864 size(4);
7865 ins_encode %{
7866 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7867 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7868 %}
7869 ins_pipe(pipe_class_default);
7870 %}
7872 // Immediate Subtraction
7873 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7874 // so this rule seems to be unused.
7875 // No constant pool entries required.
7876 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7877 match(Set dst (SubL src1 src2));
7879 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7880 size(4);
7881 ins_encode %{
7882 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7883 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7884 %}
7885 ins_pipe(pipe_class_default);
7886 %}
7888 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7889 // positive longs and 0xF...F for negative ones.
7890 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
7891 // no match-rule, false predicate
7892 effect(DEF dst, USE src);
7893 predicate(false);
7895 format %{ "SRADI $dst, $src, #63" %}
7896 size(4);
7897 ins_encode %{
7898 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7899 __ sradi($dst$$Register, $src$$Register, 0x3f);
7900 %}
7901 ins_pipe(pipe_class_default);
7902 %}
7904 // Long negation
7905 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7906 match(Set dst (SubL zero src2));
7907 format %{ "NEG $dst, $src2 \t// long" %}
7908 size(4);
7909 ins_encode %{
7910 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7911 __ neg($dst$$Register, $src2$$Register);
7912 %}
7913 ins_pipe(pipe_class_default);
7914 %}
7916 // NegL + ConvL2I.
7917 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7918 match(Set dst (ConvL2I (SubL zero src2)));
7920 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7921 size(4);
7922 ins_encode %{
7923 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7924 __ neg($dst$$Register, $src2$$Register);
7925 %}
7926 ins_pipe(pipe_class_default);
7927 %}
7929 // Multiplication Instructions
7930 // Integer Multiplication
7932 // Register Multiplication
7933 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7934 match(Set dst (MulI src1 src2));
7935 ins_cost(DEFAULT_COST);
7937 format %{ "MULLW $dst, $src1, $src2" %}
7938 size(4);
7939 ins_encode %{
7940 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
7941 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
7942 %}
7943 ins_pipe(pipe_class_default);
7944 %}
7946 // Immediate Multiplication
7947 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7948 match(Set dst (MulI src1 src2));
7949 ins_cost(DEFAULT_COST);
7951 format %{ "MULLI $dst, $src1, $src2" %}
7952 size(4);
7953 ins_encode %{
7954 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7955 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7956 %}
7957 ins_pipe(pipe_class_default);
7958 %}
7960 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7961 match(Set dst (MulL src1 src2));
7962 ins_cost(DEFAULT_COST);
7964 format %{ "MULLD $dst $src1, $src2 \t// long" %}
7965 size(4);
7966 ins_encode %{
7967 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
7968 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
7969 %}
7970 ins_pipe(pipe_class_default);
7971 %}
7973 // Multiply high for optimized long division by constant.
7974 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7975 match(Set dst (MulHiL src1 src2));
7976 ins_cost(DEFAULT_COST);
7978 format %{ "MULHD $dst $src1, $src2 \t// long" %}
7979 size(4);
7980 ins_encode %{
7981 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
7982 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
7983 %}
7984 ins_pipe(pipe_class_default);
7985 %}
7987 // Immediate Multiplication
7988 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7989 match(Set dst (MulL src1 src2));
7990 ins_cost(DEFAULT_COST);
7992 format %{ "MULLI $dst, $src1, $src2" %}
7993 size(4);
7994 ins_encode %{
7995 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7996 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7997 %}
7998 ins_pipe(pipe_class_default);
7999 %}
8001 // Integer Division with Immediate -1: Negate.
8002 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8003 match(Set dst (DivI src1 src2));
8004 ins_cost(DEFAULT_COST);
8006 format %{ "NEG $dst, $src1 \t// /-1" %}
8007 size(4);
8008 ins_encode %{
8009 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8010 __ neg($dst$$Register, $src1$$Register);
8011 %}
8012 ins_pipe(pipe_class_default);
8013 %}
8015 // Integer Division with constant, but not -1.
8016 // We should be able to improve this by checking the type of src2.
8017 // It might well be that src2 is known to be positive.
8018 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8019 match(Set dst (DivI src1 src2));
8020 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8021 ins_cost(2*DEFAULT_COST);
8023 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8024 size(4);
8025 ins_encode %{
8026 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8027 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8028 %}
8029 ins_pipe(pipe_class_default);
8030 %}
8032 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8033 effect(USE_DEF dst, USE src1, USE crx);
8034 predicate(false);
8036 ins_variable_size_depending_on_alignment(true);
8038 format %{ "CMOVE $dst, neg($src1), $crx" %}
8039 // Worst case is branch + move + stop, no stop without scheduler.
8040 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8041 ins_encode %{
8042 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8043 Label done;
8044 __ bne($crx$$CondRegister, done);
8045 __ neg($dst$$Register, $src1$$Register);
8046 // TODO PPC port __ endgroup_if_needed(_size == 12);
8047 __ bind(done);
8048 %}
8049 ins_pipe(pipe_class_default);
8050 %}
8052 // Integer Division with Registers not containing constants.
8053 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8054 match(Set dst (DivI src1 src2));
8055 ins_cost(10*DEFAULT_COST);
8057 expand %{
8058 immI16 imm %{ (int)-1 %}
8059 flagsReg tmp1;
8060 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8061 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8062 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8063 %}
8064 %}
8066 // Long Division with Immediate -1: Negate.
8067 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8068 match(Set dst (DivL src1 src2));
8069 ins_cost(DEFAULT_COST);
8071 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8072 size(4);
8073 ins_encode %{
8074 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8075 __ neg($dst$$Register, $src1$$Register);
8076 %}
8077 ins_pipe(pipe_class_default);
8078 %}
8080 // Long Division with constant, but not -1.
8081 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8082 match(Set dst (DivL src1 src2));
8083 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8084 ins_cost(2*DEFAULT_COST);
8086 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8087 size(4);
8088 ins_encode %{
8089 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8090 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8091 %}
8092 ins_pipe(pipe_class_default);
8093 %}
8095 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8096 effect(USE_DEF dst, USE src1, USE crx);
8097 predicate(false);
8099 ins_variable_size_depending_on_alignment(true);
8101 format %{ "CMOVE $dst, neg($src1), $crx" %}
8102 // Worst case is branch + move + stop, no stop without scheduler.
8103 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8104 ins_encode %{
8105 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8106 Label done;
8107 __ bne($crx$$CondRegister, done);
8108 __ neg($dst$$Register, $src1$$Register);
8109 // TODO PPC port __ endgroup_if_needed(_size == 12);
8110 __ bind(done);
8111 %}
8112 ins_pipe(pipe_class_default);
8113 %}
8115 // Long Division with Registers not containing constants.
8116 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8117 match(Set dst (DivL src1 src2));
8118 ins_cost(10*DEFAULT_COST);
8120 expand %{
8121 immL16 imm %{ (int)-1 %}
8122 flagsReg tmp1;
8123 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8124 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8125 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8126 %}
8127 %}
8129 // Integer Remainder with registers.
8130 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8131 match(Set dst (ModI src1 src2));
8132 ins_cost(10*DEFAULT_COST);
8134 expand %{
8135 immI16 imm %{ (int)-1 %}
8136 flagsReg tmp1;
8137 iRegIdst tmp2;
8138 iRegIdst tmp3;
8139 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8140 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8141 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8142 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8143 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8144 %}
8145 %}
8147 // Long Remainder with registers
8148 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8149 match(Set dst (ModL src1 src2));
8150 ins_cost(10*DEFAULT_COST);
8152 expand %{
8153 immL16 imm %{ (int)-1 %}
8154 flagsReg tmp1;
8155 iRegLdst tmp2;
8156 iRegLdst tmp3;
8157 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8158 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8159 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8160 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8161 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8162 %}
8163 %}
8165 // Integer Shift Instructions
8167 // Register Shift Left
8169 // Clear all but the lowest #mask bits.
8170 // Used to normalize shift amounts in registers.
8171 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8172 // no match-rule, false predicate
8173 effect(DEF dst, USE src, USE mask);
8174 predicate(false);
8176 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8177 size(4);
8178 ins_encode %{
8179 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8180 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8181 %}
8182 ins_pipe(pipe_class_default);
8183 %}
8185 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8186 // no match-rule, false predicate
8187 effect(DEF dst, USE src1, USE src2);
8188 predicate(false);
8190 format %{ "SLW $dst, $src1, $src2" %}
8191 size(4);
8192 ins_encode %{
8193 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8194 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8195 %}
8196 ins_pipe(pipe_class_default);
8197 %}
8199 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8200 match(Set dst (LShiftI src1 src2));
8201 ins_cost(DEFAULT_COST*2);
8202 expand %{
8203 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8204 iRegIdst tmpI;
8205 maskI_reg_imm(tmpI, src2, mask);
8206 lShiftI_reg_reg(dst, src1, tmpI);
8207 %}
8208 %}
8210 // Register Shift Left Immediate
8211 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8212 match(Set dst (LShiftI src1 src2));
8214 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8215 size(4);
8216 ins_encode %{
8217 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8218 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8219 %}
8220 ins_pipe(pipe_class_default);
8221 %}
8223 // AndI with negpow2-constant + LShiftI
8224 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8225 match(Set dst (LShiftI (AndI src1 src2) src3));
8226 predicate(UseRotateAndMaskInstructionsPPC64);
8228 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8229 size(4);
8230 ins_encode %{
8231 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8232 long src2 = $src2$$constant;
8233 long src3 = $src3$$constant;
8234 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8235 if (maskbits >= 32) {
8236 __ li($dst$$Register, 0); // addi
8237 } else {
8238 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8239 }
8240 %}
8241 ins_pipe(pipe_class_default);
8242 %}
8244 // RShiftI + AndI with negpow2-constant + LShiftI
8245 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8246 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8247 predicate(UseRotateAndMaskInstructionsPPC64);
8249 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8250 size(4);
8251 ins_encode %{
8252 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8253 long src2 = $src2$$constant;
8254 long src3 = $src3$$constant;
8255 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8256 if (maskbits >= 32) {
8257 __ li($dst$$Register, 0); // addi
8258 } else {
8259 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8260 }
8261 %}
8262 ins_pipe(pipe_class_default);
8263 %}
8265 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8266 // no match-rule, false predicate
8267 effect(DEF dst, USE src1, USE src2);
8268 predicate(false);
8270 format %{ "SLD $dst, $src1, $src2" %}
8271 size(4);
8272 ins_encode %{
8273 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8274 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8275 %}
8276 ins_pipe(pipe_class_default);
8277 %}
8279 // Register Shift Left
8280 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8281 match(Set dst (LShiftL src1 src2));
8282 ins_cost(DEFAULT_COST*2);
8283 expand %{
8284 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8285 iRegIdst tmpI;
8286 maskI_reg_imm(tmpI, src2, mask);
8287 lShiftL_regL_regI(dst, src1, tmpI);
8288 %}
8289 %}
8291 // Register Shift Left Immediate
8292 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8293 match(Set dst (LShiftL src1 src2));
8294 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8295 size(4);
8296 ins_encode %{
8297 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8298 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8299 %}
8300 ins_pipe(pipe_class_default);
8301 %}
8303 // If we shift more than 32 bits, we need not convert I2L.
8304 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8305 match(Set dst (LShiftL (ConvI2L src1) src2));
8306 ins_cost(DEFAULT_COST);
8308 size(4);
8309 format %{ "SLDI $dst, i2l($src1), $src2" %}
8310 ins_encode %{
8311 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8312 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8313 %}
8314 ins_pipe(pipe_class_default);
8315 %}
8317 // Shift a postivie int to the left.
8318 // Clrlsldi clears the upper 32 bits and shifts.
8319 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8320 match(Set dst (LShiftL (ConvI2L src1) src2));
8321 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8323 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8324 size(4);
8325 ins_encode %{
8326 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8327 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8328 %}
8329 ins_pipe(pipe_class_default);
8330 %}
8332 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8333 // no match-rule, false predicate
8334 effect(DEF dst, USE src1, USE src2);
8335 predicate(false);
8337 format %{ "SRAW $dst, $src1, $src2" %}
8338 size(4);
8339 ins_encode %{
8340 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8341 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8342 %}
8343 ins_pipe(pipe_class_default);
8344 %}
8346 // Register Arithmetic Shift Right
8347 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8348 match(Set dst (RShiftI src1 src2));
8349 ins_cost(DEFAULT_COST*2);
8350 expand %{
8351 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8352 iRegIdst tmpI;
8353 maskI_reg_imm(tmpI, src2, mask);
8354 arShiftI_reg_reg(dst, src1, tmpI);
8355 %}
8356 %}
8358 // Register Arithmetic Shift Right Immediate
8359 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8360 match(Set dst (RShiftI src1 src2));
8362 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8363 size(4);
8364 ins_encode %{
8365 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8366 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8367 %}
8368 ins_pipe(pipe_class_default);
8369 %}
8371 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8372 // no match-rule, false predicate
8373 effect(DEF dst, USE src1, USE src2);
8374 predicate(false);
8376 format %{ "SRAD $dst, $src1, $src2" %}
8377 size(4);
8378 ins_encode %{
8379 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8380 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8381 %}
8382 ins_pipe(pipe_class_default);
8383 %}
8385 // Register Shift Right Arithmetic Long
8386 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8387 match(Set dst (RShiftL src1 src2));
8388 ins_cost(DEFAULT_COST*2);
8390 expand %{
8391 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8392 iRegIdst tmpI;
8393 maskI_reg_imm(tmpI, src2, mask);
8394 arShiftL_regL_regI(dst, src1, tmpI);
8395 %}
8396 %}
8398 // Register Shift Right Immediate
8399 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8400 match(Set dst (RShiftL src1 src2));
8402 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8403 size(4);
8404 ins_encode %{
8405 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8406 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8407 %}
8408 ins_pipe(pipe_class_default);
8409 %}
8411 // RShiftL + ConvL2I
8412 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8413 match(Set dst (ConvL2I (RShiftL src1 src2)));
8415 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8416 size(4);
8417 ins_encode %{
8418 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8419 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8420 %}
8421 ins_pipe(pipe_class_default);
8422 %}
8424 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8425 // no match-rule, false predicate
8426 effect(DEF dst, USE src1, USE src2);
8427 predicate(false);
8429 format %{ "SRW $dst, $src1, $src2" %}
8430 size(4);
8431 ins_encode %{
8432 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8433 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8434 %}
8435 ins_pipe(pipe_class_default);
8436 %}
8438 // Register Shift Right
8439 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8440 match(Set dst (URShiftI src1 src2));
8441 ins_cost(DEFAULT_COST*2);
8443 expand %{
8444 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8445 iRegIdst tmpI;
8446 maskI_reg_imm(tmpI, src2, mask);
8447 urShiftI_reg_reg(dst, src1, tmpI);
8448 %}
8449 %}
8451 // Register Shift Right Immediate
8452 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8453 match(Set dst (URShiftI src1 src2));
8455 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8456 size(4);
8457 ins_encode %{
8458 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8459 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8460 %}
8461 ins_pipe(pipe_class_default);
8462 %}
8464 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8465 // no match-rule, false predicate
8466 effect(DEF dst, USE src1, USE src2);
8467 predicate(false);
8469 format %{ "SRD $dst, $src1, $src2" %}
8470 size(4);
8471 ins_encode %{
8472 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8473 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8474 %}
8475 ins_pipe(pipe_class_default);
8476 %}
8478 // Register Shift Right
8479 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8480 match(Set dst (URShiftL src1 src2));
8481 ins_cost(DEFAULT_COST*2);
8483 expand %{
8484 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8485 iRegIdst tmpI;
8486 maskI_reg_imm(tmpI, src2, mask);
8487 urShiftL_regL_regI(dst, src1, tmpI);
8488 %}
8489 %}
8491 // Register Shift Right Immediate
8492 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8493 match(Set dst (URShiftL src1 src2));
8495 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8496 size(4);
8497 ins_encode %{
8498 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8499 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8500 %}
8501 ins_pipe(pipe_class_default);
8502 %}
8504 // URShiftL + ConvL2I.
8505 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8506 match(Set dst (ConvL2I (URShiftL src1 src2)));
8508 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8509 size(4);
8510 ins_encode %{
8511 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8512 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8513 %}
8514 ins_pipe(pipe_class_default);
8515 %}
8517 // Register Shift Right Immediate with a CastP2X
8518 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8519 match(Set dst (URShiftL (CastP2X src1) src2));
8521 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8522 size(4);
8523 ins_encode %{
8524 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8525 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8526 %}
8527 ins_pipe(pipe_class_default);
8528 %}
8530 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8531 match(Set dst (ConvL2I (ConvI2L src)));
8533 format %{ "EXTSW $dst, $src \t// int->int" %}
8534 size(4);
8535 ins_encode %{
8536 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8537 __ extsw($dst$$Register, $src$$Register);
8538 %}
8539 ins_pipe(pipe_class_default);
8540 %}
8542 //----------Rotate Instructions------------------------------------------------
8544 // Rotate Left by 8-bit immediate
8545 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8546 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8547 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8549 format %{ "ROTLWI $dst, $src, $lshift" %}
8550 size(4);
8551 ins_encode %{
8552 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8553 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8554 %}
8555 ins_pipe(pipe_class_default);
8556 %}
8558 // Rotate Right by 8-bit immediate
8559 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8560 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8561 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8563 format %{ "ROTRWI $dst, $rshift" %}
8564 size(4);
8565 ins_encode %{
8566 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8567 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8568 %}
8569 ins_pipe(pipe_class_default);
8570 %}
8572 //----------Floating Point Arithmetic Instructions-----------------------------
8574 // Add float single precision
8575 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8576 match(Set dst (AddF src1 src2));
8578 format %{ "FADDS $dst, $src1, $src2" %}
8579 size(4);
8580 ins_encode %{
8581 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8582 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8583 %}
8584 ins_pipe(pipe_class_default);
8585 %}
8587 // Add float double precision
8588 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8589 match(Set dst (AddD src1 src2));
8591 format %{ "FADD $dst, $src1, $src2" %}
8592 size(4);
8593 ins_encode %{
8594 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8595 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8596 %}
8597 ins_pipe(pipe_class_default);
8598 %}
8600 // Sub float single precision
8601 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8602 match(Set dst (SubF src1 src2));
8604 format %{ "FSUBS $dst, $src1, $src2" %}
8605 size(4);
8606 ins_encode %{
8607 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8608 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8609 %}
8610 ins_pipe(pipe_class_default);
8611 %}
8613 // Sub float double precision
8614 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8615 match(Set dst (SubD src1 src2));
8616 format %{ "FSUB $dst, $src1, $src2" %}
8617 size(4);
8618 ins_encode %{
8619 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8620 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8621 %}
8622 ins_pipe(pipe_class_default);
8623 %}
8625 // Mul float single precision
8626 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8627 match(Set dst (MulF src1 src2));
8628 format %{ "FMULS $dst, $src1, $src2" %}
8629 size(4);
8630 ins_encode %{
8631 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8632 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8633 %}
8634 ins_pipe(pipe_class_default);
8635 %}
8637 // Mul float double precision
8638 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8639 match(Set dst (MulD src1 src2));
8640 format %{ "FMUL $dst, $src1, $src2" %}
8641 size(4);
8642 ins_encode %{
8643 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8644 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8645 %}
8646 ins_pipe(pipe_class_default);
8647 %}
8649 // Div float single precision
8650 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8651 match(Set dst (DivF src1 src2));
8652 format %{ "FDIVS $dst, $src1, $src2" %}
8653 size(4);
8654 ins_encode %{
8655 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8656 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8657 %}
8658 ins_pipe(pipe_class_default);
8659 %}
8661 // Div float double precision
8662 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8663 match(Set dst (DivD src1 src2));
8664 format %{ "FDIV $dst, $src1, $src2" %}
8665 size(4);
8666 ins_encode %{
8667 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8668 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8669 %}
8670 ins_pipe(pipe_class_default);
8671 %}
8673 // Absolute float single precision
8674 instruct absF_reg(regF dst, regF src) %{
8675 match(Set dst (AbsF src));
8676 format %{ "FABS $dst, $src \t// float" %}
8677 size(4);
8678 ins_encode %{
8679 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8680 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8681 %}
8682 ins_pipe(pipe_class_default);
8683 %}
8685 // Absolute float double precision
8686 instruct absD_reg(regD dst, regD src) %{
8687 match(Set dst (AbsD src));
8688 format %{ "FABS $dst, $src \t// double" %}
8689 size(4);
8690 ins_encode %{
8691 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8692 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8693 %}
8694 ins_pipe(pipe_class_default);
8695 %}
8697 instruct negF_reg(regF dst, regF src) %{
8698 match(Set dst (NegF src));
8699 format %{ "FNEG $dst, $src \t// float" %}
8700 size(4);
8701 ins_encode %{
8702 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8703 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8704 %}
8705 ins_pipe(pipe_class_default);
8706 %}
8708 instruct negD_reg(regD dst, regD src) %{
8709 match(Set dst (NegD src));
8710 format %{ "FNEG $dst, $src \t// double" %}
8711 size(4);
8712 ins_encode %{
8713 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8714 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8715 %}
8716 ins_pipe(pipe_class_default);
8717 %}
8719 // AbsF + NegF.
8720 instruct negF_absF_reg(regF dst, regF src) %{
8721 match(Set dst (NegF (AbsF src)));
8722 format %{ "FNABS $dst, $src \t// float" %}
8723 size(4);
8724 ins_encode %{
8725 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8726 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8727 %}
8728 ins_pipe(pipe_class_default);
8729 %}
8731 // AbsD + NegD.
8732 instruct negD_absD_reg(regD dst, regD src) %{
8733 match(Set dst (NegD (AbsD src)));
8734 format %{ "FNABS $dst, $src \t// double" %}
8735 size(4);
8736 ins_encode %{
8737 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8738 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8739 %}
8740 ins_pipe(pipe_class_default);
8741 %}
8743 // VM_Version::has_sqrt() decides if this node will be used.
8744 // Sqrt float double precision
8745 instruct sqrtD_reg(regD dst, regD src) %{
8746 match(Set dst (SqrtD src));
8747 format %{ "FSQRT $dst, $src" %}
8748 size(4);
8749 ins_encode %{
8750 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8751 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8752 %}
8753 ins_pipe(pipe_class_default);
8754 %}
8756 // Single-precision sqrt.
8757 instruct sqrtF_reg(regF dst, regF src) %{
8758 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8759 ins_cost(DEFAULT_COST);
8761 format %{ "FSQRTS $dst, $src" %}
8762 size(4);
8763 ins_encode %{
8764 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8765 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8766 %}
8767 ins_pipe(pipe_class_default);
8768 %}
8770 instruct roundDouble_nop(regD dst) %{
8771 match(Set dst (RoundDouble dst));
8772 ins_cost(0);
8774 format %{ " -- \t// RoundDouble not needed - empty" %}
8775 size(0);
8776 // PPC results are already "rounded" (i.e., normal-format IEEE).
8777 ins_encode( /*empty*/ );
8778 ins_pipe(pipe_class_default);
8779 %}
8781 instruct roundFloat_nop(regF dst) %{
8782 match(Set dst (RoundFloat dst));
8783 ins_cost(0);
8785 format %{ " -- \t// RoundFloat not needed - empty" %}
8786 size(0);
8787 // PPC results are already "rounded" (i.e., normal-format IEEE).
8788 ins_encode( /*empty*/ );
8789 ins_pipe(pipe_class_default);
8790 %}
8792 //----------Logical Instructions-----------------------------------------------
8794 // And Instructions
8796 // Register And
8797 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8798 match(Set dst (AndI src1 src2));
8799 format %{ "AND $dst, $src1, $src2" %}
8800 size(4);
8801 ins_encode %{
8802 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8803 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8804 %}
8805 ins_pipe(pipe_class_default);
8806 %}
8808 // Immediate And
8809 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8810 match(Set dst (AndI src1 src2));
8811 effect(KILL cr0);
8813 format %{ "ANDI $dst, $src1, $src2" %}
8814 size(4);
8815 ins_encode %{
8816 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8817 // FIXME: avoid andi_ ?
8818 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8819 %}
8820 ins_pipe(pipe_class_default);
8821 %}
8823 // Immediate And where the immediate is a negative power of 2.
8824 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8825 match(Set dst (AndI src1 src2));
8826 format %{ "ANDWI $dst, $src1, $src2" %}
8827 size(4);
8828 ins_encode %{
8829 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8830 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8831 %}
8832 ins_pipe(pipe_class_default);
8833 %}
8835 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8836 match(Set dst (AndI src1 src2));
8837 format %{ "ANDWI $dst, $src1, $src2" %}
8838 size(4);
8839 ins_encode %{
8840 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8841 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8842 %}
8843 ins_pipe(pipe_class_default);
8844 %}
8846 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8847 match(Set dst (AndI src1 src2));
8848 predicate(UseRotateAndMaskInstructionsPPC64);
8849 format %{ "ANDWI $dst, $src1, $src2" %}
8850 size(4);
8851 ins_encode %{
8852 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8853 __ rlwinm($dst$$Register, $src1$$Register, 0,
8854 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8855 %}
8856 ins_pipe(pipe_class_default);
8857 %}
8859 // Register And Long
8860 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8861 match(Set dst (AndL src1 src2));
8862 ins_cost(DEFAULT_COST);
8864 format %{ "AND $dst, $src1, $src2 \t// long" %}
8865 size(4);
8866 ins_encode %{
8867 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8868 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8869 %}
8870 ins_pipe(pipe_class_default);
8871 %}
8873 // Immediate And long
8874 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8875 match(Set dst (AndL src1 src2));
8876 effect(KILL cr0);
8877 ins_cost(DEFAULT_COST);
8879 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8880 size(4);
8881 ins_encode %{
8882 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8883 // FIXME: avoid andi_ ?
8884 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8885 %}
8886 ins_pipe(pipe_class_default);
8887 %}
8889 // Immediate And Long where the immediate is a negative power of 2.
8890 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8891 match(Set dst (AndL src1 src2));
8892 format %{ "ANDDI $dst, $src1, $src2" %}
8893 size(4);
8894 ins_encode %{
8895 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8896 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8897 %}
8898 ins_pipe(pipe_class_default);
8899 %}
8901 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8902 match(Set dst (AndL src1 src2));
8903 format %{ "ANDDI $dst, $src1, $src2" %}
8904 size(4);
8905 ins_encode %{
8906 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8907 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8908 %}
8909 ins_pipe(pipe_class_default);
8910 %}
8912 // AndL + ConvL2I.
8913 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8914 match(Set dst (ConvL2I (AndL src1 src2)));
8915 ins_cost(DEFAULT_COST);
8917 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8918 size(4);
8919 ins_encode %{
8920 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8921 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8922 %}
8923 ins_pipe(pipe_class_default);
8924 %}
8926 // Or Instructions
8928 // Register Or
8929 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8930 match(Set dst (OrI src1 src2));
8931 format %{ "OR $dst, $src1, $src2" %}
8932 size(4);
8933 ins_encode %{
8934 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8935 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8936 %}
8937 ins_pipe(pipe_class_default);
8938 %}
8940 // Expand does not work with above instruct. (??)
8941 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8942 // no match-rule
8943 effect(DEF dst, USE src1, USE src2);
8944 format %{ "OR $dst, $src1, $src2" %}
8945 size(4);
8946 ins_encode %{
8947 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8948 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8949 %}
8950 ins_pipe(pipe_class_default);
8951 %}
8953 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8954 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
8955 ins_cost(DEFAULT_COST*3);
8957 expand %{
8958 // FIXME: we should do this in the ideal world.
8959 iRegIdst tmp1;
8960 iRegIdst tmp2;
8961 orI_reg_reg(tmp1, src1, src2);
8962 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8963 orI_reg_reg(dst, tmp1, tmp2);
8964 %}
8965 %}
8967 // Immediate Or
8968 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
8969 match(Set dst (OrI src1 src2));
8970 format %{ "ORI $dst, $src1, $src2" %}
8971 size(4);
8972 ins_encode %{
8973 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
8974 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
8975 %}
8976 ins_pipe(pipe_class_default);
8977 %}
8979 // Register Or Long
8980 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8981 match(Set dst (OrL src1 src2));
8982 ins_cost(DEFAULT_COST);
8984 size(4);
8985 format %{ "OR $dst, $src1, $src2 \t// long" %}
8986 ins_encode %{
8987 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8988 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8989 %}
8990 ins_pipe(pipe_class_default);
8991 %}
8993 // OrL + ConvL2I.
8994 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8995 match(Set dst (ConvL2I (OrL src1 src2)));
8996 ins_cost(DEFAULT_COST);
8998 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
8999 size(4);
9000 ins_encode %{
9001 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9002 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9003 %}
9004 ins_pipe(pipe_class_default);
9005 %}
9007 // Immediate Or long
9008 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9009 match(Set dst (OrL src1 con));
9010 ins_cost(DEFAULT_COST);
9012 format %{ "ORI $dst, $src1, $con \t// long" %}
9013 size(4);
9014 ins_encode %{
9015 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9016 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9017 %}
9018 ins_pipe(pipe_class_default);
9019 %}
9021 // Xor Instructions
9023 // Register Xor
9024 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9025 match(Set dst (XorI src1 src2));
9026 format %{ "XOR $dst, $src1, $src2" %}
9027 size(4);
9028 ins_encode %{
9029 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9030 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9031 %}
9032 ins_pipe(pipe_class_default);
9033 %}
9035 // Expand does not work with above instruct. (??)
9036 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9037 // no match-rule
9038 effect(DEF dst, USE src1, USE src2);
9039 format %{ "XOR $dst, $src1, $src2" %}
9040 size(4);
9041 ins_encode %{
9042 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9043 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9044 %}
9045 ins_pipe(pipe_class_default);
9046 %}
9048 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9049 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9050 ins_cost(DEFAULT_COST*3);
9052 expand %{
9053 // FIXME: we should do this in the ideal world.
9054 iRegIdst tmp1;
9055 iRegIdst tmp2;
9056 xorI_reg_reg(tmp1, src1, src2);
9057 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9058 xorI_reg_reg(dst, tmp1, tmp2);
9059 %}
9060 %}
9062 // Immediate Xor
9063 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9064 match(Set dst (XorI src1 src2));
9065 format %{ "XORI $dst, $src1, $src2" %}
9066 size(4);
9067 ins_encode %{
9068 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9069 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9070 %}
9071 ins_pipe(pipe_class_default);
9072 %}
9074 // Register Xor Long
9075 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9076 match(Set dst (XorL src1 src2));
9077 ins_cost(DEFAULT_COST);
9079 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9080 size(4);
9081 ins_encode %{
9082 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9083 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9084 %}
9085 ins_pipe(pipe_class_default);
9086 %}
9088 // XorL + ConvL2I.
9089 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9090 match(Set dst (ConvL2I (XorL src1 src2)));
9091 ins_cost(DEFAULT_COST);
9093 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9094 size(4);
9095 ins_encode %{
9096 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9097 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9098 %}
9099 ins_pipe(pipe_class_default);
9100 %}
9102 // Immediate Xor Long
9103 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9104 match(Set dst (XorL src1 src2));
9105 ins_cost(DEFAULT_COST);
9107 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9108 size(4);
9109 ins_encode %{
9110 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9111 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9112 %}
9113 ins_pipe(pipe_class_default);
9114 %}
9116 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9117 match(Set dst (XorI src1 src2));
9118 ins_cost(DEFAULT_COST);
9120 format %{ "NOT $dst, $src1 ($src2)" %}
9121 size(4);
9122 ins_encode %{
9123 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9124 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9125 %}
9126 ins_pipe(pipe_class_default);
9127 %}
9129 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9130 match(Set dst (XorL src1 src2));
9131 ins_cost(DEFAULT_COST);
9133 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9134 size(4);
9135 ins_encode %{
9136 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9137 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9138 %}
9139 ins_pipe(pipe_class_default);
9140 %}
9142 // And-complement
9143 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9144 match(Set dst (AndI (XorI src1 src2) src3));
9145 ins_cost(DEFAULT_COST);
9147 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9148 size(4);
9149 ins_encode( enc_andc(dst, src3, src1) );
9150 ins_pipe(pipe_class_default);
9151 %}
9153 // And-complement
9154 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9155 // no match-rule, false predicate
9156 effect(DEF dst, USE src1, USE src2);
9157 predicate(false);
9159 format %{ "ANDC $dst, $src1, $src2" %}
9160 size(4);
9161 ins_encode %{
9162 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9163 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9164 %}
9165 ins_pipe(pipe_class_default);
9166 %}
9168 //----------Moves between int/long and float/double----------------------------
9169 //
9170 // The following rules move values from int/long registers/stack-locations
9171 // to float/double registers/stack-locations and vice versa, without doing any
9172 // conversions. These rules are used to implement the bit-conversion methods
9173 // of java.lang.Float etc., e.g.
9174 // int floatToIntBits(float value)
9175 // float intBitsToFloat(int bits)
9176 //
9177 // Notes on the implementation on ppc64:
9178 // We only provide rules which move between a register and a stack-location,
9179 // because we always have to go through memory when moving between a float
9180 // register and an integer register.
9182 //---------- Chain stack slots between similar types --------
9184 // These are needed so that the rules below can match.
9186 // Load integer from stack slot
9187 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9188 match(Set dst src);
9189 ins_cost(MEMORY_REF_COST);
9191 format %{ "LWZ $dst, $src" %}
9192 size(4);
9193 ins_encode( enc_lwz(dst, src) );
9194 ins_pipe(pipe_class_memory);
9195 %}
9197 // Store integer to stack slot
9198 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9199 match(Set dst src);
9200 ins_cost(MEMORY_REF_COST);
9202 format %{ "STW $src, $dst \t// stk" %}
9203 size(4);
9204 ins_encode( enc_stw(src, dst) ); // rs=rt
9205 ins_pipe(pipe_class_memory);
9206 %}
9208 // Load long from stack slot
9209 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9210 match(Set dst src);
9211 ins_cost(MEMORY_REF_COST);
9213 format %{ "LD $dst, $src \t// long" %}
9214 size(4);
9215 ins_encode( enc_ld(dst, src) );
9216 ins_pipe(pipe_class_memory);
9217 %}
9219 // Store long to stack slot
9220 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9221 match(Set dst src);
9222 ins_cost(MEMORY_REF_COST);
9224 format %{ "STD $src, $dst \t// long" %}
9225 size(4);
9226 ins_encode( enc_std(src, dst) ); // rs=rt
9227 ins_pipe(pipe_class_memory);
9228 %}
9230 //----------Moves between int and float
9232 // Move float value from float stack-location to integer register.
9233 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9234 match(Set dst (MoveF2I src));
9235 ins_cost(MEMORY_REF_COST);
9237 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9238 size(4);
9239 ins_encode( enc_lwz(dst, src) );
9240 ins_pipe(pipe_class_memory);
9241 %}
9243 // Move float value from float register to integer stack-location.
9244 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9245 match(Set dst (MoveF2I src));
9246 ins_cost(MEMORY_REF_COST);
9248 format %{ "STFS $src, $dst \t// MoveF2I" %}
9249 size(4);
9250 ins_encode( enc_stfs(src, dst) );
9251 ins_pipe(pipe_class_memory);
9252 %}
9254 // Move integer value from integer stack-location to float register.
9255 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9256 match(Set dst (MoveI2F src));
9257 ins_cost(MEMORY_REF_COST);
9259 format %{ "LFS $dst, $src \t// MoveI2F" %}
9260 size(4);
9261 ins_encode %{
9262 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9263 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9264 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9265 %}
9266 ins_pipe(pipe_class_memory);
9267 %}
9269 // Move integer value from integer register to float stack-location.
9270 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9271 match(Set dst (MoveI2F src));
9272 ins_cost(MEMORY_REF_COST);
9274 format %{ "STW $src, $dst \t// MoveI2F" %}
9275 size(4);
9276 ins_encode( enc_stw(src, dst) );
9277 ins_pipe(pipe_class_memory);
9278 %}
9280 //----------Moves between long and float
9282 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9283 // no match-rule, false predicate
9284 effect(DEF dst, USE src);
9285 predicate(false);
9287 format %{ "storeD $src, $dst \t// STACK" %}
9288 size(4);
9289 ins_encode( enc_stfd(src, dst) );
9290 ins_pipe(pipe_class_default);
9291 %}
9293 //----------Moves between long and double
9295 // Move double value from double stack-location to long register.
9296 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9297 match(Set dst (MoveD2L src));
9298 ins_cost(MEMORY_REF_COST);
9299 size(4);
9300 format %{ "LD $dst, $src \t// MoveD2L" %}
9301 ins_encode( enc_ld(dst, src) );
9302 ins_pipe(pipe_class_memory);
9303 %}
9305 // Move double value from double register to long stack-location.
9306 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9307 match(Set dst (MoveD2L src));
9308 effect(DEF dst, USE src);
9309 ins_cost(MEMORY_REF_COST);
9311 format %{ "STFD $src, $dst \t// MoveD2L" %}
9312 size(4);
9313 ins_encode( enc_stfd(src, dst) );
9314 ins_pipe(pipe_class_memory);
9315 %}
9317 // Move long value from long stack-location to double register.
9318 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9319 match(Set dst (MoveL2D src));
9320 ins_cost(MEMORY_REF_COST);
9322 format %{ "LFD $dst, $src \t// MoveL2D" %}
9323 size(4);
9324 ins_encode( enc_lfd(dst, src) );
9325 ins_pipe(pipe_class_memory);
9326 %}
9328 // Move long value from long register to double stack-location.
9329 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9330 match(Set dst (MoveL2D src));
9331 ins_cost(MEMORY_REF_COST);
9333 format %{ "STD $src, $dst \t// MoveL2D" %}
9334 size(4);
9335 ins_encode( enc_std(src, dst) );
9336 ins_pipe(pipe_class_memory);
9337 %}
9339 //----------Register Move Instructions-----------------------------------------
9341 // Replicate for Superword
9343 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9344 predicate(false);
9345 effect(DEF dst, USE src);
9347 format %{ "MR $dst, $src \t// replicate " %}
9348 // variable size, 0 or 4.
9349 ins_encode %{
9350 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9351 __ mr_if_needed($dst$$Register, $src$$Register);
9352 %}
9353 ins_pipe(pipe_class_default);
9354 %}
9356 //----------Cast instructions (Java-level type cast)---------------------------
9358 // Cast Long to Pointer for unsafe natives.
9359 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9360 match(Set dst (CastX2P src));
9362 format %{ "MR $dst, $src \t// Long->Ptr" %}
9363 // variable size, 0 or 4.
9364 ins_encode %{
9365 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9366 __ mr_if_needed($dst$$Register, $src$$Register);
9367 %}
9368 ins_pipe(pipe_class_default);
9369 %}
9371 // Cast Pointer to Long for unsafe natives.
9372 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9373 match(Set dst (CastP2X src));
9375 format %{ "MR $dst, $src \t// Ptr->Long" %}
9376 // variable size, 0 or 4.
9377 ins_encode %{
9378 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9379 __ mr_if_needed($dst$$Register, $src$$Register);
9380 %}
9381 ins_pipe(pipe_class_default);
9382 %}
9384 instruct castPP(iRegPdst dst) %{
9385 match(Set dst (CastPP dst));
9386 format %{ " -- \t// castPP of $dst" %}
9387 size(0);
9388 ins_encode( /*empty*/ );
9389 ins_pipe(pipe_class_default);
9390 %}
9392 instruct castII(iRegIdst dst) %{
9393 match(Set dst (CastII dst));
9394 format %{ " -- \t// castII of $dst" %}
9395 size(0);
9396 ins_encode( /*empty*/ );
9397 ins_pipe(pipe_class_default);
9398 %}
9400 instruct checkCastPP(iRegPdst dst) %{
9401 match(Set dst (CheckCastPP dst));
9402 format %{ " -- \t// checkcastPP of $dst" %}
9403 size(0);
9404 ins_encode( /*empty*/ );
9405 ins_pipe(pipe_class_default);
9406 %}
9408 //----------Convert instructions-----------------------------------------------
9410 // Convert to boolean.
9412 // int_to_bool(src) : { 1 if src != 0
9413 // { 0 else
9414 //
9415 // strategy:
9416 // 1) Count leading zeros of 32 bit-value src,
9417 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9418 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9419 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9421 // convI2Bool
9422 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9423 match(Set dst (Conv2B src));
9424 predicate(UseCountLeadingZerosInstructionsPPC64);
9425 ins_cost(DEFAULT_COST);
9427 expand %{
9428 immI shiftAmount %{ 0x5 %}
9429 uimmI16 mask %{ 0x1 %}
9430 iRegIdst tmp1;
9431 iRegIdst tmp2;
9432 countLeadingZerosI(tmp1, src);
9433 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9434 xorI_reg_uimm16(dst, tmp2, mask);
9435 %}
9436 %}
9438 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9439 match(Set dst (Conv2B src));
9440 effect(TEMP crx);
9441 predicate(!UseCountLeadingZerosInstructionsPPC64);
9442 ins_cost(DEFAULT_COST);
9444 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9445 "LI $dst, #0\n\t"
9446 "BEQ $crx, done\n\t"
9447 "LI $dst, #1\n"
9448 "done:" %}
9449 size(16);
9450 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9451 ins_pipe(pipe_class_compare);
9452 %}
9454 // ConvI2B + XorI
9455 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9456 match(Set dst (XorI (Conv2B src) mask));
9457 predicate(UseCountLeadingZerosInstructionsPPC64);
9458 ins_cost(DEFAULT_COST);
9460 expand %{
9461 immI shiftAmount %{ 0x5 %}
9462 iRegIdst tmp1;
9463 countLeadingZerosI(tmp1, src);
9464 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9465 %}
9466 %}
9468 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9469 match(Set dst (XorI (Conv2B src) mask));
9470 effect(TEMP crx);
9471 predicate(!UseCountLeadingZerosInstructionsPPC64);
9472 ins_cost(DEFAULT_COST);
9474 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9475 "LI $dst, #1\n\t"
9476 "BEQ $crx, done\n\t"
9477 "LI $dst, #0\n"
9478 "done:" %}
9479 size(16);
9480 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9481 ins_pipe(pipe_class_compare);
9482 %}
9484 // AndI 0b0..010..0 + ConvI2B
9485 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9486 match(Set dst (Conv2B (AndI src mask)));
9487 predicate(UseRotateAndMaskInstructionsPPC64);
9488 ins_cost(DEFAULT_COST);
9490 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9491 size(4);
9492 ins_encode %{
9493 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9494 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9495 %}
9496 ins_pipe(pipe_class_default);
9497 %}
9499 // Convert pointer to boolean.
9500 //
9501 // ptr_to_bool(src) : { 1 if src != 0
9502 // { 0 else
9503 //
9504 // strategy:
9505 // 1) Count leading zeros of 64 bit-value src,
9506 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9507 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9508 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9510 // ConvP2B
9511 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9512 match(Set dst (Conv2B src));
9513 predicate(UseCountLeadingZerosInstructionsPPC64);
9514 ins_cost(DEFAULT_COST);
9516 expand %{
9517 immI shiftAmount %{ 0x6 %}
9518 uimmI16 mask %{ 0x1 %}
9519 iRegIdst tmp1;
9520 iRegIdst tmp2;
9521 countLeadingZerosP(tmp1, src);
9522 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9523 xorI_reg_uimm16(dst, tmp2, mask);
9524 %}
9525 %}
9527 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9528 match(Set dst (Conv2B src));
9529 effect(TEMP crx);
9530 predicate(!UseCountLeadingZerosInstructionsPPC64);
9531 ins_cost(DEFAULT_COST);
9533 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9534 "LI $dst, #0\n\t"
9535 "BEQ $crx, done\n\t"
9536 "LI $dst, #1\n"
9537 "done:" %}
9538 size(16);
9539 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9540 ins_pipe(pipe_class_compare);
9541 %}
9543 // ConvP2B + XorI
9544 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9545 match(Set dst (XorI (Conv2B src) mask));
9546 predicate(UseCountLeadingZerosInstructionsPPC64);
9547 ins_cost(DEFAULT_COST);
9549 expand %{
9550 immI shiftAmount %{ 0x6 %}
9551 iRegIdst tmp1;
9552 countLeadingZerosP(tmp1, src);
9553 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9554 %}
9555 %}
9557 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9558 match(Set dst (XorI (Conv2B src) mask));
9559 effect(TEMP crx);
9560 predicate(!UseCountLeadingZerosInstructionsPPC64);
9561 ins_cost(DEFAULT_COST);
9563 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9564 "LI $dst, #1\n\t"
9565 "BEQ $crx, done\n\t"
9566 "LI $dst, #0\n"
9567 "done:" %}
9568 size(16);
9569 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9570 ins_pipe(pipe_class_compare);
9571 %}
9573 // if src1 < src2, return -1 else return 0
9574 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9575 match(Set dst (CmpLTMask src1 src2));
9576 ins_cost(DEFAULT_COST*4);
9578 expand %{
9579 iRegIdst src1s;
9580 iRegIdst src2s;
9581 iRegIdst diff;
9582 sxtI_reg(src1s, src1); // ensure proper sign extention
9583 sxtI_reg(src2s, src2); // ensure proper sign extention
9584 subI_reg_reg(diff, src1s, src2s);
9585 // Need to consider >=33 bit result, therefore we need signmaskL.
9586 signmask64I_regI(dst, diff);
9587 %}
9588 %}
9590 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9591 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9592 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9593 size(4);
9594 ins_encode %{
9595 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9596 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9597 %}
9598 ins_pipe(pipe_class_default);
9599 %}
9601 //----------Arithmetic Conversion Instructions---------------------------------
9603 // Convert to Byte -- nop
9604 // Convert to Short -- nop
9606 // Convert to Int
9608 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9609 match(Set dst (RShiftI (LShiftI src amount) amount));
9610 format %{ "EXTSB $dst, $src \t// byte->int" %}
9611 size(4);
9612 ins_encode %{
9613 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9614 __ extsb($dst$$Register, $src$$Register);
9615 %}
9616 ins_pipe(pipe_class_default);
9617 %}
9619 // LShiftI 16 + RShiftI 16 converts short to int.
9620 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9621 match(Set dst (RShiftI (LShiftI src amount) amount));
9622 format %{ "EXTSH $dst, $src \t// short->int" %}
9623 size(4);
9624 ins_encode %{
9625 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9626 __ extsh($dst$$Register, $src$$Register);
9627 %}
9628 ins_pipe(pipe_class_default);
9629 %}
9631 // ConvL2I + ConvI2L: Sign extend int in long register.
9632 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9633 match(Set dst (ConvI2L (ConvL2I src)));
9635 format %{ "EXTSW $dst, $src \t// long->long" %}
9636 size(4);
9637 ins_encode %{
9638 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9639 __ extsw($dst$$Register, $src$$Register);
9640 %}
9641 ins_pipe(pipe_class_default);
9642 %}
9644 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9645 match(Set dst (ConvL2I src));
9646 format %{ "MR $dst, $src \t// long->int" %}
9647 // variable size, 0 or 4
9648 ins_encode %{
9649 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9650 __ mr_if_needed($dst$$Register, $src$$Register);
9651 %}
9652 ins_pipe(pipe_class_default);
9653 %}
9655 instruct convD2IRaw_regD(regD dst, regD src) %{
9656 // no match-rule, false predicate
9657 effect(DEF dst, USE src);
9658 predicate(false);
9660 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9661 size(4);
9662 ins_encode %{
9663 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9664 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9665 %}
9666 ins_pipe(pipe_class_default);
9667 %}
9669 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9670 // no match-rule, false predicate
9671 effect(DEF dst, USE crx, USE src);
9672 predicate(false);
9674 ins_variable_size_depending_on_alignment(true);
9676 format %{ "cmovI $crx, $dst, $src" %}
9677 // Worst case is branch + move + stop, no stop without scheduler.
9678 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9679 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9680 ins_pipe(pipe_class_default);
9681 %}
9683 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9684 // no match-rule, false predicate
9685 effect(DEF dst, USE crx, USE mem);
9686 predicate(false);
9688 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9689 postalloc_expand %{
9690 //
9691 // replaces
9692 //
9693 // region dst crx mem
9694 // \ | | /
9695 // dst=cmovI_bso_stackSlotL_conLvalue0
9696 //
9697 // with
9698 //
9699 // region dst
9700 // \ /
9701 // dst=loadConI16(0)
9702 // |
9703 // ^ region dst crx mem
9704 // | \ | | /
9705 // dst=cmovI_bso_stackSlotL
9706 //
9708 // Create new nodes.
9709 MachNode *m1 = new (C) loadConI16Node();
9710 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9712 // inputs for new nodes
9713 m1->add_req(n_region);
9714 m2->add_req(n_region, n_crx, n_mem);
9716 // precedences for new nodes
9717 m2->add_prec(m1);
9719 // operands for new nodes
9720 m1->_opnds[0] = op_dst;
9721 m1->_opnds[1] = new (C) immI16Oper(0);
9723 m2->_opnds[0] = op_dst;
9724 m2->_opnds[1] = op_crx;
9725 m2->_opnds[2] = op_mem;
9727 // registers for new nodes
9728 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9729 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9731 // Insert new nodes.
9732 nodes->push(m1);
9733 nodes->push(m2);
9734 %}
9735 %}
9737 // Double to Int conversion, NaN is mapped to 0.
9738 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9739 match(Set dst (ConvD2I src));
9740 ins_cost(DEFAULT_COST);
9742 expand %{
9743 regD tmpD;
9744 stackSlotL tmpS;
9745 flagsReg crx;
9746 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9747 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9748 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9749 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9750 %}
9751 %}
9753 instruct convF2IRaw_regF(regF dst, regF src) %{
9754 // no match-rule, false predicate
9755 effect(DEF dst, USE src);
9756 predicate(false);
9758 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9759 size(4);
9760 ins_encode %{
9761 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9762 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9763 %}
9764 ins_pipe(pipe_class_default);
9765 %}
9767 // Float to Int conversion, NaN is mapped to 0.
9768 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9769 match(Set dst (ConvF2I src));
9770 ins_cost(DEFAULT_COST);
9772 expand %{
9773 regF tmpF;
9774 stackSlotL tmpS;
9775 flagsReg crx;
9776 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9777 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9778 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9779 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9780 %}
9781 %}
9783 // Convert to Long
9785 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9786 match(Set dst (ConvI2L src));
9787 format %{ "EXTSW $dst, $src \t// int->long" %}
9788 size(4);
9789 ins_encode %{
9790 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9791 __ extsw($dst$$Register, $src$$Register);
9792 %}
9793 ins_pipe(pipe_class_default);
9794 %}
9796 // Zero-extend: convert unsigned int to long (convUI2L).
9797 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9798 match(Set dst (AndL (ConvI2L src) mask));
9799 ins_cost(DEFAULT_COST);
9801 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9802 size(4);
9803 ins_encode %{
9804 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9805 __ clrldi($dst$$Register, $src$$Register, 32);
9806 %}
9807 ins_pipe(pipe_class_default);
9808 %}
9810 // Zero-extend: convert unsigned int to long in long register.
9811 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9812 match(Set dst (AndL src mask));
9813 ins_cost(DEFAULT_COST);
9815 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9816 size(4);
9817 ins_encode %{
9818 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9819 __ clrldi($dst$$Register, $src$$Register, 32);
9820 %}
9821 ins_pipe(pipe_class_default);
9822 %}
9824 instruct convF2LRaw_regF(regF dst, regF src) %{
9825 // no match-rule, false predicate
9826 effect(DEF dst, USE src);
9827 predicate(false);
9829 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9830 size(4);
9831 ins_encode %{
9832 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9833 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9834 %}
9835 ins_pipe(pipe_class_default);
9836 %}
9838 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9839 // no match-rule, false predicate
9840 effect(DEF dst, USE crx, USE src);
9841 predicate(false);
9843 ins_variable_size_depending_on_alignment(true);
9845 format %{ "cmovL $crx, $dst, $src" %}
9846 // Worst case is branch + move + stop, no stop without scheduler.
9847 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9848 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9849 ins_pipe(pipe_class_default);
9850 %}
9852 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9853 // no match-rule, false predicate
9854 effect(DEF dst, USE crx, USE mem);
9855 predicate(false);
9857 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9858 postalloc_expand %{
9859 //
9860 // replaces
9861 //
9862 // region dst crx mem
9863 // \ | | /
9864 // dst=cmovL_bso_stackSlotL_conLvalue0
9865 //
9866 // with
9867 //
9868 // region dst
9869 // \ /
9870 // dst=loadConL16(0)
9871 // |
9872 // ^ region dst crx mem
9873 // | \ | | /
9874 // dst=cmovL_bso_stackSlotL
9875 //
9877 // Create new nodes.
9878 MachNode *m1 = new (C) loadConL16Node();
9879 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9881 // inputs for new nodes
9882 m1->add_req(n_region);
9883 m2->add_req(n_region, n_crx, n_mem);
9884 m2->add_prec(m1);
9886 // operands for new nodes
9887 m1->_opnds[0] = op_dst;
9888 m1->_opnds[1] = new (C) immL16Oper(0);
9889 m2->_opnds[0] = op_dst;
9890 m2->_opnds[1] = op_crx;
9891 m2->_opnds[2] = op_mem;
9893 // registers for new nodes
9894 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9895 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9897 // Insert new nodes.
9898 nodes->push(m1);
9899 nodes->push(m2);
9900 %}
9901 %}
9903 // Float to Long conversion, NaN is mapped to 0.
9904 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9905 match(Set dst (ConvF2L src));
9906 ins_cost(DEFAULT_COST);
9908 expand %{
9909 regF tmpF;
9910 stackSlotL tmpS;
9911 flagsReg crx;
9912 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9913 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9914 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9915 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9916 %}
9917 %}
9919 instruct convD2LRaw_regD(regD dst, regD src) %{
9920 // no match-rule, false predicate
9921 effect(DEF dst, USE src);
9922 predicate(false);
9924 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9925 size(4);
9926 ins_encode %{
9927 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9928 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9929 %}
9930 ins_pipe(pipe_class_default);
9931 %}
9933 // Double to Long conversion, NaN is mapped to 0.
9934 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
9935 match(Set dst (ConvD2L src));
9936 ins_cost(DEFAULT_COST);
9938 expand %{
9939 regD tmpD;
9940 stackSlotL tmpS;
9941 flagsReg crx;
9942 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9943 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
9944 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9945 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9946 %}
9947 %}
9949 // Convert to Float
9951 // Placed here as needed in expand.
9952 instruct convL2DRaw_regD(regD dst, regD src) %{
9953 // no match-rule, false predicate
9954 effect(DEF dst, USE src);
9955 predicate(false);
9957 format %{ "FCFID $dst, $src \t// convL2D" %}
9958 size(4);
9959 ins_encode %{
9960 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
9961 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
9962 %}
9963 ins_pipe(pipe_class_default);
9964 %}
9966 // Placed here as needed in expand.
9967 instruct convD2F_reg(regF dst, regD src) %{
9968 match(Set dst (ConvD2F src));
9969 format %{ "FRSP $dst, $src \t// convD2F" %}
9970 size(4);
9971 ins_encode %{
9972 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
9973 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
9974 %}
9975 ins_pipe(pipe_class_default);
9976 %}
9978 // Integer to Float conversion.
9979 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
9980 match(Set dst (ConvI2F src));
9981 predicate(!VM_Version::has_fcfids());
9982 ins_cost(DEFAULT_COST);
9984 expand %{
9985 iRegLdst tmpL;
9986 stackSlotL tmpS;
9987 regD tmpD;
9988 regD tmpD2;
9989 convI2L_reg(tmpL, src); // Sign-extension int to long.
9990 regL_to_stkL(tmpS, tmpL); // Store long to stack.
9991 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
9992 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
9993 convD2F_reg(dst, tmpD2); // Convert double to float.
9994 %}
9995 %}
9997 instruct convL2FRaw_regF(regF dst, regD src) %{
9998 // no match-rule, false predicate
9999 effect(DEF dst, USE src);
10000 predicate(false);
10002 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10003 size(4);
10004 ins_encode %{
10005 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10006 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10007 %}
10008 ins_pipe(pipe_class_default);
10009 %}
10011 // Integer to Float conversion. Special version for Power7.
10012 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10013 match(Set dst (ConvI2F src));
10014 predicate(VM_Version::has_fcfids());
10015 ins_cost(DEFAULT_COST);
10017 expand %{
10018 iRegLdst tmpL;
10019 stackSlotL tmpS;
10020 regD tmpD;
10021 convI2L_reg(tmpL, src); // Sign-extension int to long.
10022 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10023 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10024 convL2FRaw_regF(dst, tmpD); // Convert to float.
10025 %}
10026 %}
10028 // L2F to avoid runtime call.
10029 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10030 match(Set dst (ConvL2F src));
10031 predicate(VM_Version::has_fcfids());
10032 ins_cost(DEFAULT_COST);
10034 expand %{
10035 stackSlotL tmpS;
10036 regD tmpD;
10037 regL_to_stkL(tmpS, src); // Store long to stack.
10038 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10039 convL2FRaw_regF(dst, tmpD); // Convert to float.
10040 %}
10041 %}
10043 // Moved up as used in expand.
10044 //instruct convD2F_reg(regF dst, regD src) %{%}
10046 // Convert to Double
10048 // Integer to Double conversion.
10049 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10050 match(Set dst (ConvI2D src));
10051 ins_cost(DEFAULT_COST);
10053 expand %{
10054 iRegLdst tmpL;
10055 stackSlotL tmpS;
10056 regD tmpD;
10057 convI2L_reg(tmpL, src); // Sign-extension int to long.
10058 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10059 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10060 convL2DRaw_regD(dst, tmpD); // Convert to double.
10061 %}
10062 %}
10064 // Long to Double conversion
10065 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10066 match(Set dst (ConvL2D src));
10067 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10069 expand %{
10070 regD tmpD;
10071 moveL2D_stack_reg(tmpD, src);
10072 convL2DRaw_regD(dst, tmpD);
10073 %}
10074 %}
10076 instruct convF2D_reg(regD dst, regF src) %{
10077 match(Set dst (ConvF2D src));
10078 format %{ "FMR $dst, $src \t// float->double" %}
10079 // variable size, 0 or 4
10080 ins_encode %{
10081 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10082 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10083 %}
10084 ins_pipe(pipe_class_default);
10085 %}
10087 //----------Control Flow Instructions------------------------------------------
10088 // Compare Instructions
10090 // Compare Integers
10091 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10092 match(Set crx (CmpI src1 src2));
10093 size(4);
10094 format %{ "CMPW $crx, $src1, $src2" %}
10095 ins_encode %{
10096 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10097 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10098 %}
10099 ins_pipe(pipe_class_compare);
10100 %}
10102 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10103 match(Set crx (CmpI src1 src2));
10104 format %{ "CMPWI $crx, $src1, $src2" %}
10105 size(4);
10106 ins_encode %{
10107 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10108 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10109 %}
10110 ins_pipe(pipe_class_compare);
10111 %}
10113 // (src1 & src2) == 0?
10114 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10115 match(Set cr0 (CmpI (AndI src1 src2) zero));
10116 // r0 is killed
10117 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10118 size(4);
10119 ins_encode %{
10120 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10121 // FIXME: avoid andi_ ?
10122 __ andi_(R0, $src1$$Register, $src2$$constant);
10123 %}
10124 ins_pipe(pipe_class_compare);
10125 %}
10127 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10128 match(Set crx (CmpL src1 src2));
10129 format %{ "CMPD $crx, $src1, $src2" %}
10130 size(4);
10131 ins_encode %{
10132 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10133 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10134 %}
10135 ins_pipe(pipe_class_compare);
10136 %}
10138 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10139 match(Set crx (CmpL src1 src2));
10140 format %{ "CMPDI $crx, $src1, $src2" %}
10141 size(4);
10142 ins_encode %{
10143 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10144 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10145 %}
10146 ins_pipe(pipe_class_compare);
10147 %}
10149 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10150 match(Set cr0 (CmpL (AndL src1 src2) zero));
10151 // r0 is killed
10152 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10153 size(4);
10154 ins_encode %{
10155 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10156 __ and_(R0, $src1$$Register, $src2$$Register);
10157 %}
10158 ins_pipe(pipe_class_compare);
10159 %}
10161 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10162 match(Set cr0 (CmpL (AndL src1 src2) zero));
10163 // r0 is killed
10164 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10165 size(4);
10166 ins_encode %{
10167 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10168 // FIXME: avoid andi_ ?
10169 __ andi_(R0, $src1$$Register, $src2$$constant);
10170 %}
10171 ins_pipe(pipe_class_compare);
10172 %}
10174 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10175 // no match-rule, false predicate
10176 effect(DEF dst, USE crx);
10177 predicate(false);
10179 ins_variable_size_depending_on_alignment(true);
10181 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10182 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10183 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10184 ins_encode %{
10185 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10186 Label done;
10187 // li(Rdst, 0); // equal -> 0
10188 __ beq($crx$$CondRegister, done);
10189 __ li($dst$$Register, 1); // greater -> +1
10190 __ bgt($crx$$CondRegister, done);
10191 __ li($dst$$Register, -1); // unordered or less -> -1
10192 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10193 __ bind(done);
10194 %}
10195 ins_pipe(pipe_class_compare);
10196 %}
10198 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10199 // no match-rule, false predicate
10200 effect(DEF dst, USE crx);
10201 predicate(false);
10203 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10204 postalloc_expand %{
10205 //
10206 // replaces
10207 //
10208 // region crx
10209 // \ |
10210 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10211 //
10212 // with
10213 //
10214 // region
10215 // \
10216 // dst=loadConI16(0)
10217 // |
10218 // ^ region crx
10219 // | \ |
10220 // dst=cmovI_conIvalueMinus1_conIvalue1
10221 //
10223 // Create new nodes.
10224 MachNode *m1 = new (C) loadConI16Node();
10225 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10227 // inputs for new nodes
10228 m1->add_req(n_region);
10229 m2->add_req(n_region, n_crx);
10230 m2->add_prec(m1);
10232 // operands for new nodes
10233 m1->_opnds[0] = op_dst;
10234 m1->_opnds[1] = new (C) immI16Oper(0);
10235 m2->_opnds[0] = op_dst;
10236 m2->_opnds[1] = op_crx;
10238 // registers for new nodes
10239 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10240 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10242 // Insert new nodes.
10243 nodes->push(m1);
10244 nodes->push(m2);
10245 %}
10246 %}
10248 // Manifest a CmpL3 result in an integer register. Very painful.
10249 // This is the test to avoid.
10250 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10251 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10252 match(Set dst (CmpL3 src1 src2));
10253 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10255 expand %{
10256 flagsReg tmp1;
10257 cmpL_reg_reg(tmp1, src1, src2);
10258 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10259 %}
10260 %}
10262 // Implicit range checks.
10263 // A range check in the ideal world has one of the following shapes:
10264 // - (If le (CmpU length index)), (IfTrue throw exception)
10265 // - (If lt (CmpU index length)), (IfFalse throw exception)
10266 //
10267 // Match range check 'If le (CmpU length index)'.
10268 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10269 match(If cmp (CmpU src_length index));
10270 effect(USE labl);
10271 predicate(TrapBasedRangeChecks &&
10272 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10273 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10274 (Matcher::branches_to_uncommon_trap(_leaf)));
10276 ins_is_TrapBasedCheckNode(true);
10278 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10279 size(4);
10280 ins_encode %{
10281 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10282 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10283 __ trap_range_check_le($src_length$$Register, $index$$constant);
10284 } else {
10285 // Both successors are uncommon traps, probability is 0.
10286 // Node got flipped during fixup flow.
10287 assert($cmp$$cmpcode == 0x9, "must be greater");
10288 __ trap_range_check_g($src_length$$Register, $index$$constant);
10289 }
10290 %}
10291 ins_pipe(pipe_class_trap);
10292 %}
10294 // Match range check 'If lt (CmpU index length)'.
10295 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10296 match(If cmp (CmpU src_index src_length));
10297 effect(USE labl);
10298 predicate(TrapBasedRangeChecks &&
10299 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10300 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10301 (Matcher::branches_to_uncommon_trap(_leaf)));
10303 ins_is_TrapBasedCheckNode(true);
10305 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10306 size(4);
10307 ins_encode %{
10308 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10309 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10310 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10311 } else {
10312 // Both successors are uncommon traps, probability is 0.
10313 // Node got flipped during fixup flow.
10314 assert($cmp$$cmpcode == 0x8, "must be less");
10315 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10316 }
10317 %}
10318 ins_pipe(pipe_class_trap);
10319 %}
10321 // Match range check 'If lt (CmpU index length)'.
10322 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10323 match(If cmp (CmpU src_index length));
10324 effect(USE labl);
10325 predicate(TrapBasedRangeChecks &&
10326 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10327 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10328 (Matcher::branches_to_uncommon_trap(_leaf)));
10330 ins_is_TrapBasedCheckNode(true);
10332 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10333 size(4);
10334 ins_encode %{
10335 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10336 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10337 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10338 } else {
10339 // Both successors are uncommon traps, probability is 0.
10340 // Node got flipped during fixup flow.
10341 assert($cmp$$cmpcode == 0x8, "must be less");
10342 __ trap_range_check_l($src_index$$Register, $length$$constant);
10343 }
10344 %}
10345 ins_pipe(pipe_class_trap);
10346 %}
10348 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10349 match(Set crx (CmpU src1 src2));
10350 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10351 size(4);
10352 ins_encode %{
10353 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10354 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10355 %}
10356 ins_pipe(pipe_class_compare);
10357 %}
10359 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10360 match(Set crx (CmpU src1 src2));
10361 size(4);
10362 format %{ "CMPLWI $crx, $src1, $src2" %}
10363 ins_encode %{
10364 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10365 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10366 %}
10367 ins_pipe(pipe_class_compare);
10368 %}
10370 // Implicit zero checks (more implicit null checks).
10371 // No constant pool entries required.
10372 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10373 match(If cmp (CmpN value zero));
10374 effect(USE labl);
10375 predicate(TrapBasedNullChecks &&
10376 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10377 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10378 Matcher::branches_to_uncommon_trap(_leaf));
10379 ins_cost(1);
10381 ins_is_TrapBasedCheckNode(true);
10383 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10384 size(4);
10385 ins_encode %{
10386 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10387 if ($cmp$$cmpcode == 0xA) {
10388 __ trap_null_check($value$$Register);
10389 } else {
10390 // Both successors are uncommon traps, probability is 0.
10391 // Node got flipped during fixup flow.
10392 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10393 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10394 }
10395 %}
10396 ins_pipe(pipe_class_trap);
10397 %}
10399 // Compare narrow oops.
10400 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10401 match(Set crx (CmpN src1 src2));
10403 size(4);
10404 ins_cost(DEFAULT_COST);
10405 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10406 ins_encode %{
10407 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10408 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10409 %}
10410 ins_pipe(pipe_class_compare);
10411 %}
10413 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10414 match(Set crx (CmpN src1 src2));
10415 // Make this more expensive than zeroCheckN_iReg_imm0.
10416 ins_cost(DEFAULT_COST);
10418 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10419 size(4);
10420 ins_encode %{
10421 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10422 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10423 %}
10424 ins_pipe(pipe_class_compare);
10425 %}
10427 // Implicit zero checks (more implicit null checks).
10428 // No constant pool entries required.
10429 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10430 match(If cmp (CmpP value zero));
10431 effect(USE labl);
10432 predicate(TrapBasedNullChecks &&
10433 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10434 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10435 Matcher::branches_to_uncommon_trap(_leaf));
10437 ins_is_TrapBasedCheckNode(true);
10439 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10440 size(4);
10441 ins_encode %{
10442 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10443 if ($cmp$$cmpcode == 0xA) {
10444 __ trap_null_check($value$$Register);
10445 } else {
10446 // Both successors are uncommon traps, probability is 0.
10447 // Node got flipped during fixup flow.
10448 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10449 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10450 }
10451 %}
10452 ins_pipe(pipe_class_trap);
10453 %}
10455 // Compare Pointers
10456 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10457 match(Set crx (CmpP src1 src2));
10458 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10459 size(4);
10460 ins_encode %{
10461 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10462 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10463 %}
10464 ins_pipe(pipe_class_compare);
10465 %}
10467 // Used in postalloc expand.
10468 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10469 // This match rule prevents reordering of node before a safepoint.
10470 // This only makes sense if this instructions is used exclusively
10471 // for the expansion of EncodeP!
10472 match(Set crx (CmpP src1 src2));
10473 predicate(false);
10475 format %{ "CMPDI $crx, $src1, $src2" %}
10476 size(4);
10477 ins_encode %{
10478 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10479 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10480 %}
10481 ins_pipe(pipe_class_compare);
10482 %}
10484 //----------Float Compares----------------------------------------------------
10486 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10487 // no match-rule, false predicate
10488 effect(DEF crx, USE src1, USE src2);
10489 predicate(false);
10491 format %{ "cmpFUrd $crx, $src1, $src2" %}
10492 size(4);
10493 ins_encode %{
10494 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10495 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10496 %}
10497 ins_pipe(pipe_class_default);
10498 %}
10500 instruct cmov_bns_less(flagsReg crx) %{
10501 // no match-rule, false predicate
10502 effect(DEF crx);
10503 predicate(false);
10505 ins_variable_size_depending_on_alignment(true);
10507 format %{ "cmov $crx" %}
10508 // Worst case is branch + move + stop, no stop without scheduler.
10509 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10510 ins_encode %{
10511 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10512 Label done;
10513 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10514 __ li(R0, 0);
10515 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10516 // TODO PPC port __ endgroup_if_needed(_size == 16);
10517 __ bind(done);
10518 %}
10519 ins_pipe(pipe_class_default);
10520 %}
10522 // Compare floating, generate condition code.
10523 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10524 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10525 //
10526 // The following code sequence occurs a lot in mpegaudio:
10527 //
10528 // block BXX:
10529 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10530 // cmpFUrd CCR6, F11, F9
10531 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10532 // cmov CCR6
10533 // 8: instruct branchConSched:
10534 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10535 match(Set crx (CmpF src1 src2));
10536 ins_cost(DEFAULT_COST+BRANCH_COST);
10538 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10539 postalloc_expand %{
10540 //
10541 // replaces
10542 //
10543 // region src1 src2
10544 // \ | |
10545 // crx=cmpF_reg_reg
10546 //
10547 // with
10548 //
10549 // region src1 src2
10550 // \ | |
10551 // crx=cmpFUnordered_reg_reg
10552 // |
10553 // ^ region
10554 // | \
10555 // crx=cmov_bns_less
10556 //
10558 // Create new nodes.
10559 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10560 MachNode *m2 = new (C) cmov_bns_lessNode();
10562 // inputs for new nodes
10563 m1->add_req(n_region, n_src1, n_src2);
10564 m2->add_req(n_region);
10565 m2->add_prec(m1);
10567 // operands for new nodes
10568 m1->_opnds[0] = op_crx;
10569 m1->_opnds[1] = op_src1;
10570 m1->_opnds[2] = op_src2;
10571 m2->_opnds[0] = op_crx;
10573 // registers for new nodes
10574 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10575 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10577 // Insert new nodes.
10578 nodes->push(m1);
10579 nodes->push(m2);
10580 %}
10581 %}
10583 // Compare float, generate -1,0,1
10584 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10585 match(Set dst (CmpF3 src1 src2));
10586 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10588 expand %{
10589 flagsReg tmp1;
10590 cmpFUnordered_reg_reg(tmp1, src1, src2);
10591 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10592 %}
10593 %}
10595 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10596 // no match-rule, false predicate
10597 effect(DEF crx, USE src1, USE src2);
10598 predicate(false);
10600 format %{ "cmpFUrd $crx, $src1, $src2" %}
10601 size(4);
10602 ins_encode %{
10603 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10604 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10605 %}
10606 ins_pipe(pipe_class_default);
10607 %}
10609 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10610 match(Set crx (CmpD src1 src2));
10611 ins_cost(DEFAULT_COST+BRANCH_COST);
10613 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10614 postalloc_expand %{
10615 //
10616 // replaces
10617 //
10618 // region src1 src2
10619 // \ | |
10620 // crx=cmpD_reg_reg
10621 //
10622 // with
10623 //
10624 // region src1 src2
10625 // \ | |
10626 // crx=cmpDUnordered_reg_reg
10627 // |
10628 // ^ region
10629 // | \
10630 // crx=cmov_bns_less
10631 //
10633 // create new nodes
10634 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10635 MachNode *m2 = new (C) cmov_bns_lessNode();
10637 // inputs for new nodes
10638 m1->add_req(n_region, n_src1, n_src2);
10639 m2->add_req(n_region);
10640 m2->add_prec(m1);
10642 // operands for new nodes
10643 m1->_opnds[0] = op_crx;
10644 m1->_opnds[1] = op_src1;
10645 m1->_opnds[2] = op_src2;
10646 m2->_opnds[0] = op_crx;
10648 // registers for new nodes
10649 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10650 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10652 // Insert new nodes.
10653 nodes->push(m1);
10654 nodes->push(m2);
10655 %}
10656 %}
10658 // Compare double, generate -1,0,1
10659 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10660 match(Set dst (CmpD3 src1 src2));
10661 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10663 expand %{
10664 flagsReg tmp1;
10665 cmpDUnordered_reg_reg(tmp1, src1, src2);
10666 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10667 %}
10668 %}
10670 //----------Branches---------------------------------------------------------
10671 // Jump
10673 // Direct Branch.
10674 instruct branch(label labl) %{
10675 match(Goto);
10676 effect(USE labl);
10677 ins_cost(BRANCH_COST);
10679 format %{ "B $labl" %}
10680 size(4);
10681 ins_encode %{
10682 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10683 Label d; // dummy
10684 __ bind(d);
10685 Label* p = $labl$$label;
10686 // `p' is `NULL' when this encoding class is used only to
10687 // determine the size of the encoded instruction.
10688 Label& l = (NULL == p)? d : *(p);
10689 __ b(l);
10690 %}
10691 ins_pipe(pipe_class_default);
10692 %}
10694 // Conditional Near Branch
10695 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10696 // Same match rule as `branchConFar'.
10697 match(If cmp crx);
10698 effect(USE lbl);
10699 ins_cost(BRANCH_COST);
10701 // If set to 1 this indicates that the current instruction is a
10702 // short variant of a long branch. This avoids using this
10703 // instruction in first-pass matching. It will then only be used in
10704 // the `Shorten_branches' pass.
10705 ins_short_branch(1);
10707 format %{ "B$cmp $crx, $lbl" %}
10708 size(4);
10709 ins_encode( enc_bc(crx, cmp, lbl) );
10710 ins_pipe(pipe_class_default);
10711 %}
10713 // This is for cases when the ppc64 `bc' instruction does not
10714 // reach far enough. So we emit a far branch here, which is more
10715 // expensive.
10716 //
10717 // Conditional Far Branch
10718 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10719 // Same match rule as `branchCon'.
10720 match(If cmp crx);
10721 effect(USE crx, USE lbl);
10722 predicate(!false /* TODO: PPC port HB_Schedule*/);
10723 // Higher cost than `branchCon'.
10724 ins_cost(5*BRANCH_COST);
10726 // This is not a short variant of a branch, but the long variant.
10727 ins_short_branch(0);
10729 format %{ "B_FAR$cmp $crx, $lbl" %}
10730 size(8);
10731 ins_encode( enc_bc_far(crx, cmp, lbl) );
10732 ins_pipe(pipe_class_default);
10733 %}
10735 // Conditional Branch used with Power6 scheduler (can be far or short).
10736 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10737 // Same match rule as `branchCon'.
10738 match(If cmp crx);
10739 effect(USE crx, USE lbl);
10740 predicate(false /* TODO: PPC port HB_Schedule*/);
10741 // Higher cost than `branchCon'.
10742 ins_cost(5*BRANCH_COST);
10744 // Actually size doesn't depend on alignment but on shortening.
10745 ins_variable_size_depending_on_alignment(true);
10746 // long variant.
10747 ins_short_branch(0);
10749 format %{ "B_FAR$cmp $crx, $lbl" %}
10750 size(8); // worst case
10751 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10752 ins_pipe(pipe_class_default);
10753 %}
10755 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10756 match(CountedLoopEnd cmp crx);
10757 effect(USE labl);
10758 ins_cost(BRANCH_COST);
10760 // short variant.
10761 ins_short_branch(1);
10763 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10764 size(4);
10765 ins_encode( enc_bc(crx, cmp, labl) );
10766 ins_pipe(pipe_class_default);
10767 %}
10769 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10770 match(CountedLoopEnd cmp crx);
10771 effect(USE labl);
10772 predicate(!false /* TODO: PPC port HB_Schedule */);
10773 ins_cost(BRANCH_COST);
10775 // Long variant.
10776 ins_short_branch(0);
10778 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10779 size(8);
10780 ins_encode( enc_bc_far(crx, cmp, labl) );
10781 ins_pipe(pipe_class_default);
10782 %}
10784 // Conditional Branch used with Power6 scheduler (can be far or short).
10785 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10786 match(CountedLoopEnd cmp crx);
10787 effect(USE labl);
10788 predicate(false /* TODO: PPC port HB_Schedule */);
10789 // Higher cost than `branchCon'.
10790 ins_cost(5*BRANCH_COST);
10792 // Actually size doesn't depend on alignment but on shortening.
10793 ins_variable_size_depending_on_alignment(true);
10794 // Long variant.
10795 ins_short_branch(0);
10797 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10798 size(8); // worst case
10799 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10800 ins_pipe(pipe_class_default);
10801 %}
10803 // ============================================================================
10804 // Java runtime operations, intrinsics and other complex operations.
10806 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10807 // array for an instance of the superklass. Set a hidden internal cache on a
10808 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10809 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10810 //
10811 // GL TODO: Improve this.
10812 // - result should not be a TEMP
10813 // - Add match rule as on sparc avoiding additional Cmp.
10814 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10815 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10816 match(Set result (PartialSubtypeCheck subklass superklass));
10817 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10818 ins_cost(DEFAULT_COST*10);
10820 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10821 ins_encode %{
10822 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10823 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10824 $tmp_klass$$Register, NULL, $result$$Register);
10825 %}
10826 ins_pipe(pipe_class_default);
10827 %}
10829 // inlined locking and unlocking
10831 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10832 match(Set crx (FastLock oop box));
10833 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10834 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10836 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10837 ins_encode %{
10838 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10839 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10840 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10841 // If locking was successfull, crx should indicate 'EQ'.
10842 // The compiler generates a branch to the runtime call to
10843 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10844 %}
10845 ins_pipe(pipe_class_compare);
10846 %}
10848 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10849 match(Set crx (FastUnlock oop box));
10850 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10852 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10853 ins_encode %{
10854 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10855 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10856 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10857 // If unlocking was successfull, crx should indicate 'EQ'.
10858 // The compiler generates a branch to the runtime call to
10859 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10860 %}
10861 ins_pipe(pipe_class_compare);
10862 %}
10864 // Align address.
10865 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10866 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10868 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10869 size(4);
10870 ins_encode %{
10871 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10872 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10873 %}
10874 ins_pipe(pipe_class_default);
10875 %}
10877 // Array size computation.
10878 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10879 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10881 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10882 size(4);
10883 ins_encode %{
10884 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10885 __ subf($dst$$Register, $start$$Register, $end$$Register);
10886 %}
10887 ins_pipe(pipe_class_default);
10888 %}
10890 // Clear-array with dynamic array-size.
10891 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10892 match(Set dummy (ClearArray cnt base));
10893 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10894 ins_cost(MEMORY_REF_COST);
10896 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10898 format %{ "ClearArray $cnt, $base" %}
10899 ins_encode %{
10900 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10901 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10902 %}
10903 ins_pipe(pipe_class_default);
10904 %}
10906 // String_IndexOf for needle of length 1.
10907 //
10908 // Match needle into immediate operands: no loadConP node needed. Saves one
10909 // register and two instructions over string_indexOf_imm1Node.
10910 //
10911 // Assumes register result differs from all input registers.
10912 //
10913 // Preserves registers haystack, haycnt
10914 // Kills registers tmp1, tmp2
10915 // Defines registers result
10916 //
10917 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10918 //
10919 // Unfortunately this does not match too often. In many situations the AddP is used
10920 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10921 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10922 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10923 iRegIdst tmp1, iRegIdst tmp2,
10924 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10925 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10926 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10928 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10930 ins_cost(150);
10931 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10932 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10934 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
10935 ins_encode %{
10936 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10937 immPOper *needleOper = (immPOper *)$needleImm;
10938 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10939 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10941 __ string_indexof_1($result$$Register,
10942 $haystack$$Register, $haycnt$$Register,
10943 R0, needle_values->char_at(0),
10944 $tmp1$$Register, $tmp2$$Register);
10945 %}
10946 ins_pipe(pipe_class_compare);
10947 %}
10949 // String_IndexOf for needle of length 1.
10950 //
10951 // Special case requires less registers and emits less instructions.
10952 //
10953 // Assumes register result differs from all input registers.
10954 //
10955 // Preserves registers haystack, haycnt
10956 // Kills registers tmp1, tmp2, needle
10957 // Defines registers result
10958 //
10959 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10960 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10961 rscratch2RegP needle, immI_1 needlecntImm,
10962 iRegIdst tmp1, iRegIdst tmp2,
10963 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10964 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10965 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
10966 TEMP tmp1, TEMP tmp2);
10967 // Required for EA: check if it is still a type_array.
10968 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
10969 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
10970 ins_cost(180);
10972 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10974 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
10975 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
10976 ins_encode %{
10977 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10978 Node *ndl = in(operand_index($needle)); // The node that defines needle.
10979 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
10980 guarantee(needle_values, "sanity");
10981 if (needle_values != NULL) {
10982 __ string_indexof_1($result$$Register,
10983 $haystack$$Register, $haycnt$$Register,
10984 R0, needle_values->char_at(0),
10985 $tmp1$$Register, $tmp2$$Register);
10986 } else {
10987 __ string_indexof_1($result$$Register,
10988 $haystack$$Register, $haycnt$$Register,
10989 $needle$$Register, 0,
10990 $tmp1$$Register, $tmp2$$Register);
10991 }
10992 %}
10993 ins_pipe(pipe_class_compare);
10994 %}
10996 // String_IndexOf.
10997 //
10998 // Length of needle as immediate. This saves instruction loading constant needle
10999 // length.
11000 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11001 // completely or do it in vector instruction. This should save registers for
11002 // needlecnt and needle.
11003 //
11004 // Assumes register result differs from all input registers.
11005 // Overwrites haycnt, needlecnt.
11006 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11007 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11008 iRegPsrc needle, uimmI15 needlecntImm,
11009 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11010 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11011 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11012 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11013 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11014 // Required for EA: check if it is still a type_array.
11015 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11016 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11017 ins_cost(250);
11019 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11021 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11022 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11023 ins_encode %{
11024 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11025 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11026 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11028 __ string_indexof($result$$Register,
11029 $haystack$$Register, $haycnt$$Register,
11030 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11031 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11032 %}
11033 ins_pipe(pipe_class_compare);
11034 %}
11036 // StrIndexOf node.
11037 //
11038 // Assumes register result differs from all input registers.
11039 // Overwrites haycnt, needlecnt.
11040 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11041 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11042 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11043 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11044 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11045 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11046 TEMP result,
11047 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11048 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11049 ins_cost(300);
11051 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11053 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11054 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11055 ins_encode %{
11056 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11057 __ string_indexof($result$$Register,
11058 $haystack$$Register, $haycnt$$Register,
11059 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11060 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11061 %}
11062 ins_pipe(pipe_class_compare);
11063 %}
11065 // String equals with immediate.
11066 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11067 iRegPdst tmp1, iRegPdst tmp2,
11068 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11069 match(Set result (StrEquals (Binary str1 str2) cntImm));
11070 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11071 KILL cr0, KILL cr6, KILL ctr);
11072 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11073 ins_cost(250);
11075 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11077 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11078 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11079 ins_encode %{
11080 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11081 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11082 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11083 %}
11084 ins_pipe(pipe_class_compare);
11085 %}
11087 // String equals.
11088 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11089 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11090 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11091 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11092 match(Set result (StrEquals (Binary str1 str2) cnt));
11093 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11094 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11095 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11096 ins_cost(300);
11098 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11100 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11101 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11102 ins_encode %{
11103 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11104 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11105 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11106 %}
11107 ins_pipe(pipe_class_compare);
11108 %}
11110 // String compare.
11111 // Char[] pointers are passed in.
11112 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11113 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11114 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11115 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11116 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11117 ins_cost(300);
11119 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11121 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11122 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11123 ins_encode %{
11124 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11125 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11126 $result$$Register, $tmp$$Register);
11127 %}
11128 ins_pipe(pipe_class_compare);
11129 %}
11131 //---------- Min/Max Instructions ---------------------------------------------
11133 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11134 match(Set dst (MinI src1 src2));
11135 ins_cost(DEFAULT_COST*6);
11137 expand %{
11138 iRegIdst src1s;
11139 iRegIdst src2s;
11140 iRegIdst diff;
11141 iRegIdst sm;
11142 iRegIdst doz; // difference or zero
11143 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11144 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11145 subI_reg_reg(diff, src2s, src1s);
11146 // Need to consider >=33 bit result, therefore we need signmaskL.
11147 signmask64I_regI(sm, diff);
11148 andI_reg_reg(doz, diff, sm); // <=0
11149 addI_reg_reg(dst, doz, src1s);
11150 %}
11151 %}
11153 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11154 match(Set dst (MaxI src1 src2));
11155 ins_cost(DEFAULT_COST*6);
11157 expand %{
11158 immI_minus1 m1 %{ -1 %}
11159 iRegIdst src1s;
11160 iRegIdst src2s;
11161 iRegIdst diff;
11162 iRegIdst sm;
11163 iRegIdst doz; // difference or zero
11164 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11165 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11166 subI_reg_reg(diff, src2s, src1s);
11167 // Need to consider >=33 bit result, therefore we need signmaskL.
11168 signmask64I_regI(sm, diff);
11169 andcI_reg_reg(doz, sm, m1, diff); // >=0
11170 addI_reg_reg(dst, doz, src1s);
11171 %}
11172 %}
11174 //---------- Population Count Instructions ------------------------------------
11176 // Popcnt for Power7.
11177 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11178 match(Set dst (PopCountI src));
11179 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11180 ins_cost(DEFAULT_COST);
11182 format %{ "POPCNTW $dst, $src" %}
11183 size(4);
11184 ins_encode %{
11185 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11186 __ popcntw($dst$$Register, $src$$Register);
11187 %}
11188 ins_pipe(pipe_class_default);
11189 %}
11191 // Popcnt for Power7.
11192 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11193 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11194 match(Set dst (PopCountL src));
11195 ins_cost(DEFAULT_COST);
11197 format %{ "POPCNTD $dst, $src" %}
11198 size(4);
11199 ins_encode %{
11200 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11201 __ popcntd($dst$$Register, $src$$Register);
11202 %}
11203 ins_pipe(pipe_class_default);
11204 %}
11206 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11207 match(Set dst (CountLeadingZerosI src));
11208 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11209 ins_cost(DEFAULT_COST);
11211 format %{ "CNTLZW $dst, $src" %}
11212 size(4);
11213 ins_encode %{
11214 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11215 __ cntlzw($dst$$Register, $src$$Register);
11216 %}
11217 ins_pipe(pipe_class_default);
11218 %}
11220 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11221 match(Set dst (CountLeadingZerosL src));
11222 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11223 ins_cost(DEFAULT_COST);
11225 format %{ "CNTLZD $dst, $src" %}
11226 size(4);
11227 ins_encode %{
11228 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11229 __ cntlzd($dst$$Register, $src$$Register);
11230 %}
11231 ins_pipe(pipe_class_default);
11232 %}
11234 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11235 // no match-rule, false predicate
11236 effect(DEF dst, USE src);
11237 predicate(false);
11239 format %{ "CNTLZD $dst, $src" %}
11240 size(4);
11241 ins_encode %{
11242 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11243 __ cntlzd($dst$$Register, $src$$Register);
11244 %}
11245 ins_pipe(pipe_class_default);
11246 %}
11248 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11249 match(Set dst (CountTrailingZerosI src));
11250 predicate(UseCountLeadingZerosInstructionsPPC64);
11251 ins_cost(DEFAULT_COST);
11253 expand %{
11254 immI16 imm1 %{ (int)-1 %}
11255 immI16 imm2 %{ (int)32 %}
11256 immI_minus1 m1 %{ -1 %}
11257 iRegIdst tmpI1;
11258 iRegIdst tmpI2;
11259 iRegIdst tmpI3;
11260 addI_reg_imm16(tmpI1, src, imm1);
11261 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11262 countLeadingZerosI(tmpI3, tmpI2);
11263 subI_imm16_reg(dst, imm2, tmpI3);
11264 %}
11265 %}
11267 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11268 match(Set dst (CountTrailingZerosL src));
11269 predicate(UseCountLeadingZerosInstructionsPPC64);
11270 ins_cost(DEFAULT_COST);
11272 expand %{
11273 immL16 imm1 %{ (long)-1 %}
11274 immI16 imm2 %{ (int)64 %}
11275 iRegLdst tmpL1;
11276 iRegLdst tmpL2;
11277 iRegIdst tmpL3;
11278 addL_reg_imm16(tmpL1, src, imm1);
11279 andcL_reg_reg(tmpL2, tmpL1, src);
11280 countLeadingZerosL(tmpL3, tmpL2);
11281 subI_imm16_reg(dst, imm2, tmpL3);
11282 %}
11283 %}
11285 // Expand nodes for byte_reverse_int.
11286 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11287 effect(DEF dst, USE src, USE pos, USE shift);
11288 predicate(false);
11290 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11291 size(4);
11292 ins_encode %{
11293 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11294 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11295 %}
11296 ins_pipe(pipe_class_default);
11297 %}
11299 // As insrwi_a, but with USE_DEF.
11300 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11301 effect(USE_DEF dst, USE src, USE pos, USE shift);
11302 predicate(false);
11304 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11305 size(4);
11306 ins_encode %{
11307 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11308 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11309 %}
11310 ins_pipe(pipe_class_default);
11311 %}
11313 // Just slightly faster than java implementation.
11314 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11315 match(Set dst (ReverseBytesI src));
11316 predicate(UseCountLeadingZerosInstructionsPPC64);
11317 ins_cost(DEFAULT_COST);
11319 expand %{
11320 immI16 imm24 %{ (int) 24 %}
11321 immI16 imm16 %{ (int) 16 %}
11322 immI16 imm8 %{ (int) 8 %}
11323 immI16 imm4 %{ (int) 4 %}
11324 immI16 imm0 %{ (int) 0 %}
11325 iRegLdst tmpI1;
11326 iRegLdst tmpI2;
11327 iRegLdst tmpI3;
11329 urShiftI_reg_imm(tmpI1, src, imm24);
11330 insrwi_a(dst, tmpI1, imm24, imm8);
11331 urShiftI_reg_imm(tmpI2, src, imm16);
11332 insrwi(dst, tmpI2, imm8, imm16);
11333 urShiftI_reg_imm(tmpI3, src, imm8);
11334 insrwi(dst, tmpI3, imm8, imm8);
11335 insrwi(dst, src, imm0, imm8);
11336 %}
11337 %}
11339 //---------- Replicate Vector Instructions ------------------------------------
11341 // Insrdi does replicate if src == dst.
11342 instruct repl32(iRegLdst dst) %{
11343 predicate(false);
11344 effect(USE_DEF dst);
11346 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11347 size(4);
11348 ins_encode %{
11349 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11350 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11351 %}
11352 ins_pipe(pipe_class_default);
11353 %}
11355 // Insrdi does replicate if src == dst.
11356 instruct repl48(iRegLdst dst) %{
11357 predicate(false);
11358 effect(USE_DEF dst);
11360 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11361 size(4);
11362 ins_encode %{
11363 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11364 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11365 %}
11366 ins_pipe(pipe_class_default);
11367 %}
11369 // Insrdi does replicate if src == dst.
11370 instruct repl56(iRegLdst dst) %{
11371 predicate(false);
11372 effect(USE_DEF dst);
11374 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11375 size(4);
11376 ins_encode %{
11377 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11378 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11379 %}
11380 ins_pipe(pipe_class_default);
11381 %}
11383 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11384 match(Set dst (ReplicateB src));
11385 predicate(n->as_Vector()->length() == 8);
11386 expand %{
11387 moveReg(dst, src);
11388 repl56(dst);
11389 repl48(dst);
11390 repl32(dst);
11391 %}
11392 %}
11394 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11395 match(Set dst (ReplicateB zero));
11396 predicate(n->as_Vector()->length() == 8);
11397 format %{ "LI $dst, #0 \t// replicate8B" %}
11398 size(4);
11399 ins_encode %{
11400 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11401 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11402 %}
11403 ins_pipe(pipe_class_default);
11404 %}
11406 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11407 match(Set dst (ReplicateB src));
11408 predicate(n->as_Vector()->length() == 8);
11409 format %{ "LI $dst, #-1 \t// replicate8B" %}
11410 size(4);
11411 ins_encode %{
11412 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11413 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11414 %}
11415 ins_pipe(pipe_class_default);
11416 %}
11418 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11419 match(Set dst (ReplicateS src));
11420 predicate(n->as_Vector()->length() == 4);
11421 expand %{
11422 moveReg(dst, src);
11423 repl48(dst);
11424 repl32(dst);
11425 %}
11426 %}
11428 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11429 match(Set dst (ReplicateS zero));
11430 predicate(n->as_Vector()->length() == 4);
11431 format %{ "LI $dst, #0 \t// replicate4C" %}
11432 size(4);
11433 ins_encode %{
11434 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11435 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11436 %}
11437 ins_pipe(pipe_class_default);
11438 %}
11440 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11441 match(Set dst (ReplicateS src));
11442 predicate(n->as_Vector()->length() == 4);
11443 format %{ "LI $dst, -1 \t// replicate4C" %}
11444 size(4);
11445 ins_encode %{
11446 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11447 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11448 %}
11449 ins_pipe(pipe_class_default);
11450 %}
11452 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11453 match(Set dst (ReplicateI src));
11454 predicate(n->as_Vector()->length() == 2);
11455 ins_cost(2 * DEFAULT_COST);
11456 expand %{
11457 moveReg(dst, src);
11458 repl32(dst);
11459 %}
11460 %}
11462 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11463 match(Set dst (ReplicateI zero));
11464 predicate(n->as_Vector()->length() == 2);
11465 format %{ "LI $dst, #0 \t// replicate4C" %}
11466 size(4);
11467 ins_encode %{
11468 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11469 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11470 %}
11471 ins_pipe(pipe_class_default);
11472 %}
11474 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11475 match(Set dst (ReplicateI src));
11476 predicate(n->as_Vector()->length() == 2);
11477 format %{ "LI $dst, -1 \t// replicate4C" %}
11478 size(4);
11479 ins_encode %{
11480 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11481 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11482 %}
11483 ins_pipe(pipe_class_default);
11484 %}
11486 // Move float to int register via stack, replicate.
11487 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11488 match(Set dst (ReplicateF src));
11489 predicate(n->as_Vector()->length() == 2);
11490 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11491 expand %{
11492 stackSlotL tmpS;
11493 iRegIdst tmpI;
11494 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11495 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11496 moveReg(dst, tmpI); // Move int to long reg.
11497 repl32(dst); // Replicate bitpattern.
11498 %}
11499 %}
11501 // Replicate scalar constant to packed float values in Double register
11502 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11503 match(Set dst (ReplicateF src));
11504 predicate(n->as_Vector()->length() == 2);
11505 ins_cost(5 * DEFAULT_COST);
11507 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11508 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11509 %}
11511 // Replicate scalar zero constant to packed float values in Double register
11512 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11513 match(Set dst (ReplicateF zero));
11514 predicate(n->as_Vector()->length() == 2);
11516 format %{ "LI $dst, #0 \t// replicate2F" %}
11517 ins_encode %{
11518 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11519 __ li($dst$$Register, 0x0);
11520 %}
11521 ins_pipe(pipe_class_default);
11522 %}
11524 // ============================================================================
11525 // Safepoint Instruction
11527 instruct safePoint_poll(iRegPdst poll) %{
11528 match(SafePoint poll);
11529 predicate(LoadPollAddressFromThread);
11531 // It caused problems to add the effect that r0 is killed, but this
11532 // effect no longer needs to be mentioned, since r0 is not contained
11533 // in a reg_class.
11535 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11536 size(4);
11537 ins_encode( enc_poll(0x0, poll) );
11538 ins_pipe(pipe_class_default);
11539 %}
11541 // Safepoint without per-thread support. Load address of page to poll
11542 // as constant.
11543 // Rscratch2RegP is R12.
11544 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11545 // a seperate node so that the oop map is at the right location.
11546 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11547 match(SafePoint poll);
11548 predicate(!LoadPollAddressFromThread);
11550 // It caused problems to add the effect that r0 is killed, but this
11551 // effect no longer needs to be mentioned, since r0 is not contained
11552 // in a reg_class.
11554 format %{ "LD R12, addr of polling page\n\t"
11555 "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11556 ins_encode( enc_poll(0x0, poll) );
11557 ins_pipe(pipe_class_default);
11558 %}
11560 // ============================================================================
11561 // Call Instructions
11563 // Call Java Static Instruction
11565 // Schedulable version of call static node.
11566 instruct CallStaticJavaDirect(method meth) %{
11567 match(CallStaticJava);
11568 effect(USE meth);
11569 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11570 ins_cost(CALL_COST);
11572 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11574 format %{ "CALL,static $meth \t// ==> " %}
11575 size(4);
11576 ins_encode( enc_java_static_call(meth) );
11577 ins_pipe(pipe_class_call);
11578 %}
11580 // Schedulable version of call static node.
11581 instruct CallStaticJavaDirectHandle(method meth) %{
11582 match(CallStaticJava);
11583 effect(USE meth);
11584 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11585 ins_cost(CALL_COST);
11587 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11589 format %{ "CALL,static $meth \t// ==> " %}
11590 ins_encode( enc_java_handle_call(meth) );
11591 ins_pipe(pipe_class_call);
11592 %}
11594 // Call Java Dynamic Instruction
11596 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11597 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11598 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11599 // The call destination must still be placed in the constant pool.
11600 instruct CallDynamicJavaDirectSched(method meth) %{
11601 match(CallDynamicJava); // To get all the data fields we need ...
11602 effect(USE meth);
11603 predicate(false); // ... but never match.
11605 ins_field_load_ic_hi_node(loadConL_hiNode*);
11606 ins_field_load_ic_node(loadConLNode*);
11607 ins_num_consts(1 /* 1 patchable constant: call destination */);
11609 format %{ "BL \t// dynamic $meth ==> " %}
11610 size(4);
11611 ins_encode( enc_java_dynamic_call_sched(meth) );
11612 ins_pipe(pipe_class_call);
11613 %}
11615 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11616 // We use postalloc expanded calls if we use inline caches
11617 // and do not update method data.
11618 //
11619 // This instruction has two constants: inline cache (IC) and call destination.
11620 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11621 // one constant.
11622 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11623 match(CallDynamicJava);
11624 effect(USE meth);
11625 predicate(UseInlineCaches);
11626 ins_cost(CALL_COST);
11628 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11630 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11631 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11632 %}
11634 // Compound version of call dynamic java
11635 // We use postalloc expanded calls if we use inline caches
11636 // and do not update method data.
11637 instruct CallDynamicJavaDirect(method meth) %{
11638 match(CallDynamicJava);
11639 effect(USE meth);
11640 predicate(!UseInlineCaches);
11641 ins_cost(CALL_COST);
11643 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11644 ins_num_consts(4);
11646 format %{ "CALL,dynamic $meth \t// ==> " %}
11647 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11648 ins_pipe(pipe_class_call);
11649 %}
11651 // Call Runtime Instruction
11653 instruct CallRuntimeDirect(method meth) %{
11654 match(CallRuntime);
11655 effect(USE meth);
11656 ins_cost(CALL_COST);
11658 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11659 // env for callee, C-toc.
11660 ins_num_consts(3);
11662 format %{ "CALL,runtime" %}
11663 ins_encode( enc_java_to_runtime_call(meth) );
11664 ins_pipe(pipe_class_call);
11665 %}
11667 // Call Leaf
11669 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11670 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11671 effect(DEF dst, USE src);
11673 ins_num_consts(1);
11675 format %{ "MTCTR $src" %}
11676 size(4);
11677 ins_encode( enc_leaf_call_mtctr(src) );
11678 ins_pipe(pipe_class_default);
11679 %}
11681 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11682 instruct CallLeafDirect(method meth) %{
11683 match(CallLeaf); // To get the data all the data fields we need ...
11684 effect(USE meth);
11685 predicate(false); // but never match.
11687 format %{ "BCTRL \t// leaf call $meth ==> " %}
11688 size(4);
11689 ins_encode %{
11690 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11691 __ bctrl();
11692 %}
11693 ins_pipe(pipe_class_call);
11694 %}
11696 // postalloc expand of CallLeafDirect.
11697 // Load adress to call from TOC, then bl to it.
11698 instruct CallLeafDirect_Ex(method meth) %{
11699 match(CallLeaf);
11700 effect(USE meth);
11701 ins_cost(CALL_COST);
11703 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11704 // env for callee, C-toc.
11705 ins_num_consts(3);
11707 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11708 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11709 %}
11711 // Call runtime without safepoint - same as CallLeaf.
11712 // postalloc expand of CallLeafNoFPDirect.
11713 // Load adress to call from TOC, then bl to it.
11714 instruct CallLeafNoFPDirect_Ex(method meth) %{
11715 match(CallLeafNoFP);
11716 effect(USE meth);
11717 ins_cost(CALL_COST);
11719 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11720 // env for callee, C-toc.
11721 ins_num_consts(3);
11723 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11724 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11725 %}
11727 // Tail Call; Jump from runtime stub to Java code.
11728 // Also known as an 'interprocedural jump'.
11729 // Target of jump will eventually return to caller.
11730 // TailJump below removes the return address.
11731 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11732 match(TailCall jump_target method_oop);
11733 ins_cost(CALL_COST);
11735 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11736 "BCTR \t// tail call" %}
11737 size(8);
11738 ins_encode %{
11739 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11740 __ mtctr($jump_target$$Register);
11741 __ bctr();
11742 %}
11743 ins_pipe(pipe_class_call);
11744 %}
11746 // Return Instruction
11747 instruct Ret() %{
11748 match(Return);
11749 format %{ "BLR \t// branch to link register" %}
11750 size(4);
11751 ins_encode %{
11752 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11753 // LR is restored in MachEpilogNode. Just do the RET here.
11754 __ blr();
11755 %}
11756 ins_pipe(pipe_class_default);
11757 %}
11759 // Tail Jump; remove the return address; jump to target.
11760 // TailCall above leaves the return address around.
11761 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11762 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11763 // "restore" before this instruction (in Epilogue), we need to materialize it
11764 // in %i0.
11765 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11766 match(TailJump jump_target ex_oop);
11767 ins_cost(CALL_COST);
11769 format %{ "LD R4_ARG2 = LR\n\t"
11770 "MTCTR $jump_target\n\t"
11771 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11772 size(12);
11773 ins_encode %{
11774 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11775 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11776 __ mtctr($jump_target$$Register);
11777 __ bctr();
11778 %}
11779 ins_pipe(pipe_class_call);
11780 %}
11782 // Create exception oop: created by stack-crawling runtime code.
11783 // Created exception is now available to this handler, and is setup
11784 // just prior to jumping to this handler. No code emitted.
11785 instruct CreateException(rarg1RegP ex_oop) %{
11786 match(Set ex_oop (CreateEx));
11787 ins_cost(0);
11789 format %{ " -- \t// exception oop; no code emitted" %}
11790 size(0);
11791 ins_encode( /*empty*/ );
11792 ins_pipe(pipe_class_default);
11793 %}
11795 // Rethrow exception: The exception oop will come in the first
11796 // argument position. Then JUMP (not call) to the rethrow stub code.
11797 instruct RethrowException() %{
11798 match(Rethrow);
11799 ins_cost(CALL_COST);
11801 format %{ "Jmp rethrow_stub" %}
11802 ins_encode %{
11803 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11804 cbuf.set_insts_mark();
11805 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11806 %}
11807 ins_pipe(pipe_class_call);
11808 %}
11810 // Die now.
11811 instruct ShouldNotReachHere() %{
11812 match(Halt);
11813 ins_cost(CALL_COST);
11815 format %{ "ShouldNotReachHere" %}
11816 size(4);
11817 ins_encode %{
11818 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11819 __ trap_should_not_reach_here();
11820 %}
11821 ins_pipe(pipe_class_default);
11822 %}
11824 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11825 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11826 // Get a DEF on threadRegP, no costs, no encoding, use
11827 // 'ins_should_rematerialize(true)' to avoid spilling.
11828 instruct tlsLoadP(threadRegP dst) %{
11829 match(Set dst (ThreadLocal));
11830 ins_cost(0);
11832 ins_should_rematerialize(true);
11834 format %{ " -- \t// $dst=Thread::current(), empty" %}
11835 size(0);
11836 ins_encode( /*empty*/ );
11837 ins_pipe(pipe_class_empty);
11838 %}
11840 //---Some PPC specific nodes---------------------------------------------------
11842 // Stop a group.
11843 instruct endGroup() %{
11844 ins_cost(0);
11846 ins_is_nop(true);
11848 format %{ "End Bundle (ori r1, r1, 0)" %}
11849 size(4);
11850 ins_encode %{
11851 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11852 __ endgroup();
11853 %}
11854 ins_pipe(pipe_class_default);
11855 %}
11857 // Nop instructions
11859 instruct fxNop() %{
11860 ins_cost(0);
11862 ins_is_nop(true);
11864 format %{ "fxNop" %}
11865 size(4);
11866 ins_encode %{
11867 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11868 __ nop();
11869 %}
11870 ins_pipe(pipe_class_default);
11871 %}
11873 instruct fpNop0() %{
11874 ins_cost(0);
11876 ins_is_nop(true);
11878 format %{ "fpNop0" %}
11879 size(4);
11880 ins_encode %{
11881 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11882 __ fpnop0();
11883 %}
11884 ins_pipe(pipe_class_default);
11885 %}
11887 instruct fpNop1() %{
11888 ins_cost(0);
11890 ins_is_nop(true);
11892 format %{ "fpNop1" %}
11893 size(4);
11894 ins_encode %{
11895 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11896 __ fpnop1();
11897 %}
11898 ins_pipe(pipe_class_default);
11899 %}
11901 instruct brNop0() %{
11902 ins_cost(0);
11903 size(4);
11904 format %{ "brNop0" %}
11905 ins_encode %{
11906 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11907 __ brnop0();
11908 %}
11909 ins_is_nop(true);
11910 ins_pipe(pipe_class_default);
11911 %}
11913 instruct brNop1() %{
11914 ins_cost(0);
11916 ins_is_nop(true);
11918 format %{ "brNop1" %}
11919 size(4);
11920 ins_encode %{
11921 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11922 __ brnop1();
11923 %}
11924 ins_pipe(pipe_class_default);
11925 %}
11927 instruct brNop2() %{
11928 ins_cost(0);
11930 ins_is_nop(true);
11932 format %{ "brNop2" %}
11933 size(4);
11934 ins_encode %{
11935 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11936 __ brnop2();
11937 %}
11938 ins_pipe(pipe_class_default);
11939 %}
11941 //----------PEEPHOLE RULES-----------------------------------------------------
11942 // These must follow all instruction definitions as they use the names
11943 // defined in the instructions definitions.
11944 //
11945 // peepmatch ( root_instr_name [preceeding_instruction]* );
11946 //
11947 // peepconstraint %{
11948 // (instruction_number.operand_name relational_op instruction_number.operand_name
11949 // [, ...] );
11950 // // instruction numbers are zero-based using left to right order in peepmatch
11951 //
11952 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11953 // // provide an instruction_number.operand_name for each operand that appears
11954 // // in the replacement instruction's match rule
11955 //
11956 // ---------VM FLAGS---------------------------------------------------------
11957 //
11958 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11959 //
11960 // Each peephole rule is given an identifying number starting with zero and
11961 // increasing by one in the order seen by the parser. An individual peephole
11962 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11963 // on the command-line.
11964 //
11965 // ---------CURRENT LIMITATIONS----------------------------------------------
11966 //
11967 // Only match adjacent instructions in same basic block
11968 // Only equality constraints
11969 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11970 // Only one replacement instruction
11971 //
11972 // ---------EXAMPLE----------------------------------------------------------
11973 //
11974 // // pertinent parts of existing instructions in architecture description
11975 // instruct movI(eRegI dst, eRegI src) %{
11976 // match(Set dst (CopyI src));
11977 // %}
11978 //
11979 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
11980 // match(Set dst (AddI dst src));
11981 // effect(KILL cr);
11982 // %}
11983 //
11984 // // Change (inc mov) to lea
11985 // peephole %{
11986 // // increment preceeded by register-register move
11987 // peepmatch ( incI_eReg movI );
11988 // // require that the destination register of the increment
11989 // // match the destination register of the move
11990 // peepconstraint ( 0.dst == 1.dst );
11991 // // construct a replacement instruction that sets
11992 // // the destination to ( move's source register + one )
11993 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
11994 // %}
11995 //
11996 // Implementation no longer uses movX instructions since
11997 // machine-independent system no longer uses CopyX nodes.
11998 //
11999 // peephole %{
12000 // peepmatch ( incI_eReg movI );
12001 // peepconstraint ( 0.dst == 1.dst );
12002 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12003 // %}
12004 //
12005 // peephole %{
12006 // peepmatch ( decI_eReg movI );
12007 // peepconstraint ( 0.dst == 1.dst );
12008 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12009 // %}
12010 //
12011 // peephole %{
12012 // peepmatch ( addI_eReg_imm movI );
12013 // peepconstraint ( 0.dst == 1.dst );
12014 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12015 // %}
12016 //
12017 // peephole %{
12018 // peepmatch ( addP_eReg_imm movP );
12019 // peepconstraint ( 0.dst == 1.dst );
12020 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12021 // %}
12023 // // Change load of spilled value to only a spill
12024 // instruct storeI(memory mem, eRegI src) %{
12025 // match(Set mem (StoreI mem src));
12026 // %}
12027 //
12028 // instruct loadI(eRegI dst, memory mem) %{
12029 // match(Set dst (LoadI mem));
12030 // %}
12031 //
12032 peephole %{
12033 peepmatch ( loadI storeI );
12034 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12035 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12036 %}
12038 peephole %{
12039 peepmatch ( loadL storeL );
12040 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12041 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12042 %}
12044 peephole %{
12045 peepmatch ( loadP storeP );
12046 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12047 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12048 %}
12050 //----------SMARTSPILL RULES---------------------------------------------------
12051 // These must follow all instruction definitions as they use the names
12052 // defined in the instructions definitions.