Mon, 24 Mar 2014 23:13:46 -0700
8038222: Assembler::bsrl fails on assert when -UseCountLeadingZerosInstruction is used on CPU with LZCNT support
Summary: Remove the overly strict assert
Reviewed-by: kvn, twisti
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
58 _is_lval = false;
59 _target = target;
60 switch (rtype) {
61 case relocInfo::oop_type:
62 case relocInfo::metadata_type:
63 // Oops are a special case. Normally they would be their own section
64 // but in cases like icBuffer they are literals in the code stream that
65 // we don't have a section for. We use none so that we get a literal address
66 // which is always patchable.
67 break;
68 case relocInfo::external_word_type:
69 _rspec = external_word_Relocation::spec(target);
70 break;
71 case relocInfo::internal_word_type:
72 _rspec = internal_word_Relocation::spec(target);
73 break;
74 case relocInfo::opt_virtual_call_type:
75 _rspec = opt_virtual_call_Relocation::spec();
76 break;
77 case relocInfo::static_call_type:
78 _rspec = static_call_Relocation::spec();
79 break;
80 case relocInfo::runtime_call_type:
81 _rspec = runtime_call_Relocation::spec();
82 break;
83 case relocInfo::poll_type:
84 case relocInfo::poll_return_type:
85 _rspec = Relocation::spec_simple(rtype);
86 break;
87 case relocInfo::none:
88 break;
89 default:
90 ShouldNotReachHere();
91 break;
92 }
93 }
95 // Implementation of Address
97 #ifdef _LP64
99 Address Address::make_array(ArrayAddress adr) {
100 // Not implementable on 64bit machines
101 // Should have been handled higher up the call chain.
102 ShouldNotReachHere();
103 return Address();
104 }
106 // exceedingly dangerous constructor
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
108 _base = noreg;
109 _index = noreg;
110 _scale = no_scale;
111 _disp = disp;
112 switch (rtype) {
113 case relocInfo::external_word_type:
114 _rspec = external_word_Relocation::spec(loc);
115 break;
116 case relocInfo::internal_word_type:
117 _rspec = internal_word_Relocation::spec(loc);
118 break;
119 case relocInfo::runtime_call_type:
120 // HMM
121 _rspec = runtime_call_Relocation::spec();
122 break;
123 case relocInfo::poll_type:
124 case relocInfo::poll_return_type:
125 _rspec = Relocation::spec_simple(rtype);
126 break;
127 case relocInfo::none:
128 break;
129 default:
130 ShouldNotReachHere();
131 }
132 }
133 #else // LP64
135 Address Address::make_array(ArrayAddress adr) {
136 AddressLiteral base = adr.base();
137 Address index = adr.index();
138 assert(index._disp == 0, "must not have disp"); // maybe it can?
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
140 array._rspec = base._rspec;
141 return array;
142 }
144 // exceedingly dangerous constructor
145 Address::Address(address loc, RelocationHolder spec) {
146 _base = noreg;
147 _index = noreg;
148 _scale = no_scale;
149 _disp = (intptr_t) loc;
150 _rspec = spec;
151 }
153 #endif // _LP64
157 // Convert the raw encoding form into the form expected by the constructor for
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert
159 // that to noreg for the Address constructor.
160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
161 RelocationHolder rspec;
162 if (disp_reloc != relocInfo::none) {
163 rspec = Relocation::spec_simple(disp_reloc);
164 }
165 bool valid_index = index != rsp->encoding();
166 if (valid_index) {
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
168 madr._rspec = rspec;
169 return madr;
170 } else {
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
172 madr._rspec = rspec;
173 return madr;
174 }
175 }
177 // Implementation of Assembler
179 int AbstractAssembler::code_fill_byte() {
180 return (u_char)'\xF4'; // hlt
181 }
183 // make this go away someday
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
185 if (rtype == relocInfo::none)
186 emit_int32(data);
187 else emit_data(data, Relocation::spec_simple(rtype), format);
188 }
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
191 assert(imm_operand == 0, "default format must be immediate in this file");
192 assert(inst_mark() != NULL, "must be inside InstructionMark");
193 if (rspec.type() != relocInfo::none) {
194 #ifdef ASSERT
195 check_relocation(rspec, format);
196 #endif
197 // Do not use AbstractAssembler::relocate, which is not intended for
198 // embedded words. Instead, relocate to the enclosing instruction.
200 // hack. call32 is too wide for mask so use disp32
201 if (format == call32_operand)
202 code_section()->relocate(inst_mark(), rspec, disp32_operand);
203 else
204 code_section()->relocate(inst_mark(), rspec, format);
205 }
206 emit_int32(data);
207 }
209 static int encode(Register r) {
210 int enc = r->encoding();
211 if (enc >= 8) {
212 enc -= 8;
213 }
214 return enc;
215 }
217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
218 assert(dst->has_byte_register(), "must have byte register");
219 assert(isByte(op1) && isByte(op2), "wrong opcode");
220 assert(isByte(imm8), "not a byte");
221 assert((op1 & 0x01) == 0, "should be 8bit operation");
222 emit_int8(op1);
223 emit_int8(op2 | encode(dst));
224 emit_int8(imm8);
225 }
228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
229 assert(isByte(op1) && isByte(op2), "wrong opcode");
230 assert((op1 & 0x01) == 1, "should be 32bit operation");
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
232 if (is8bit(imm32)) {
233 emit_int8(op1 | 0x02); // set sign bit
234 emit_int8(op2 | encode(dst));
235 emit_int8(imm32 & 0xFF);
236 } else {
237 emit_int8(op1);
238 emit_int8(op2 | encode(dst));
239 emit_int32(imm32);
240 }
241 }
243 // Force generation of a 4 byte immediate value even if it fits into 8bit
244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
245 assert(isByte(op1) && isByte(op2), "wrong opcode");
246 assert((op1 & 0x01) == 1, "should be 32bit operation");
247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
248 emit_int8(op1);
249 emit_int8(op2 | encode(dst));
250 emit_int32(imm32);
251 }
253 // immediate-to-memory forms
254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_operand(rm, adr, 1);
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_operand(rm, adr, 4);
264 emit_int32(imm32);
265 }
266 }
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 emit_int8(op1);
272 emit_int8(op2 | encode(dst) << 3 | encode(src));
273 }
276 void Assembler::emit_operand(Register reg, Register base, Register index,
277 Address::ScaleFactor scale, int disp,
278 RelocationHolder const& rspec,
279 int rip_relative_correction) {
280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
282 // Encode the registers as needed in the fields they are used in
284 int regenc = encode(reg) << 3;
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
286 int baseenc = base->is_valid() ? encode(base) : 0;
288 if (base->is_valid()) {
289 if (index->is_valid()) {
290 assert(scale != Address::no_scale, "inconsistent address");
291 // [base + index*scale + disp]
292 if (disp == 0 && rtype == relocInfo::none &&
293 base != rbp LP64_ONLY(&& base != r13)) {
294 // [base + index*scale]
295 // [00 reg 100][ss index base]
296 assert(index != rsp, "illegal addressing mode");
297 emit_int8(0x04 | regenc);
298 emit_int8(scale << 6 | indexenc | baseenc);
299 } else if (is8bit(disp) && rtype == relocInfo::none) {
300 // [base + index*scale + imm8]
301 // [01 reg 100][ss index base] imm8
302 assert(index != rsp, "illegal addressing mode");
303 emit_int8(0x44 | regenc);
304 emit_int8(scale << 6 | indexenc | baseenc);
305 emit_int8(disp & 0xFF);
306 } else {
307 // [base + index*scale + disp32]
308 // [10 reg 100][ss index base] disp32
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x84 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_data(disp, rspec, disp32_operand);
313 }
314 } else if (base == rsp LP64_ONLY(|| base == r12)) {
315 // [rsp + disp]
316 if (disp == 0 && rtype == relocInfo::none) {
317 // [rsp]
318 // [00 reg 100][00 100 100]
319 emit_int8(0x04 | regenc);
320 emit_int8(0x24);
321 } else if (is8bit(disp) && rtype == relocInfo::none) {
322 // [rsp + imm8]
323 // [01 reg 100][00 100 100] disp8
324 emit_int8(0x44 | regenc);
325 emit_int8(0x24);
326 emit_int8(disp & 0xFF);
327 } else {
328 // [rsp + imm32]
329 // [10 reg 100][00 100 100] disp32
330 emit_int8(0x84 | regenc);
331 emit_int8(0x24);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 } else {
335 // [base + disp]
336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
337 if (disp == 0 && rtype == relocInfo::none &&
338 base != rbp LP64_ONLY(&& base != r13)) {
339 // [base]
340 // [00 reg base]
341 emit_int8(0x00 | regenc | baseenc);
342 } else if (is8bit(disp) && rtype == relocInfo::none) {
343 // [base + disp8]
344 // [01 reg base] disp8
345 emit_int8(0x40 | regenc | baseenc);
346 emit_int8(disp & 0xFF);
347 } else {
348 // [base + disp32]
349 // [10 reg base] disp32
350 emit_int8(0x80 | regenc | baseenc);
351 emit_data(disp, rspec, disp32_operand);
352 }
353 }
354 } else {
355 if (index->is_valid()) {
356 assert(scale != Address::no_scale, "inconsistent address");
357 // [index*scale + disp]
358 // [00 reg 100][ss index 101] disp32
359 assert(index != rsp, "illegal addressing mode");
360 emit_int8(0x04 | regenc);
361 emit_int8(scale << 6 | indexenc | 0x05);
362 emit_data(disp, rspec, disp32_operand);
363 } else if (rtype != relocInfo::none ) {
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs
365 // [00 000 101] disp32
367 emit_int8(0x05 | regenc);
368 // Note that the RIP-rel. correction applies to the generated
369 // disp field, but _not_ to the target address in the rspec.
371 // disp was created by converting the target address minus the pc
372 // at the start of the instruction. That needs more correction here.
373 // intptr_t disp = target - next_ip;
374 assert(inst_mark() != NULL, "must be inside InstructionMark");
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
376 int64_t adjusted = disp;
377 // Do rip-rel adjustment for 64bit
378 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
379 assert(is_simm32(adjusted),
380 "must be 32bit offset (RIP relative address)");
381 emit_data((int32_t) adjusted, rspec, disp32_operand);
383 } else {
384 // 32bit never did this, did everything as the rip-rel/disp code above
385 // [disp] ABSOLUTE
386 // [00 reg 100][00 100 101] disp32
387 emit_int8(0x04 | regenc);
388 emit_int8(0x25);
389 emit_data(disp, rspec, disp32_operand);
390 }
391 }
392 }
394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
395 Address::ScaleFactor scale, int disp,
396 RelocationHolder const& rspec) {
397 emit_operand((Register)reg, base, index, scale, disp, rspec);
398 }
400 // Secret local extension to Assembler::WhichOperand:
401 #define end_pc_operand (_WhichOperand_limit)
403 address Assembler::locate_operand(address inst, WhichOperand which) {
404 // Decode the given instruction, and return the address of
405 // an embedded 32-bit operand word.
407 // If "which" is disp32_operand, selects the displacement portion
408 // of an effective address specifier.
409 // If "which" is imm64_operand, selects the trailing immediate constant.
410 // If "which" is call32_operand, selects the displacement of a call or jump.
411 // Caller is responsible for ensuring that there is such an operand,
412 // and that it is 32/64 bits wide.
414 // If "which" is end_pc_operand, find the end of the instruction.
416 address ip = inst;
417 bool is_64bit = false;
419 debug_only(bool has_disp32 = false);
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
422 again_after_prefix:
423 switch (0xFF & *ip++) {
425 // These convenience macros generate groups of "case" labels for the switch.
426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
428 case (x)+4: case (x)+5: case (x)+6: case (x)+7
429 #define REP16(x) REP8((x)+0): \
430 case REP8((x)+8)
432 case CS_segment:
433 case SS_segment:
434 case DS_segment:
435 case ES_segment:
436 case FS_segment:
437 case GS_segment:
438 // Seems dubious
439 LP64_ONLY(assert(false, "shouldn't have that prefix"));
440 assert(ip == inst+1, "only one prefix allowed");
441 goto again_after_prefix;
443 case 0x67:
444 case REX:
445 case REX_B:
446 case REX_X:
447 case REX_XB:
448 case REX_R:
449 case REX_RB:
450 case REX_RX:
451 case REX_RXB:
452 NOT_LP64(assert(false, "64bit prefixes"));
453 goto again_after_prefix;
455 case REX_W:
456 case REX_WB:
457 case REX_WX:
458 case REX_WXB:
459 case REX_WR:
460 case REX_WRB:
461 case REX_WRX:
462 case REX_WRXB:
463 NOT_LP64(assert(false, "64bit prefixes"));
464 is_64bit = true;
465 goto again_after_prefix;
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
468 case 0x88: // movb a, r
469 case 0x89: // movl a, r
470 case 0x8A: // movb r, a
471 case 0x8B: // movl r, a
472 case 0x8F: // popl a
473 debug_only(has_disp32 = true);
474 break;
476 case 0x68: // pushq #32
477 if (which == end_pc_operand) {
478 return ip + 4;
479 }
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
481 return ip; // not produced by emit_operand
483 case 0x66: // movw ... (size prefix)
484 again_after_size_prefix2:
485 switch (0xFF & *ip++) {
486 case REX:
487 case REX_B:
488 case REX_X:
489 case REX_XB:
490 case REX_R:
491 case REX_RB:
492 case REX_RX:
493 case REX_RXB:
494 case REX_W:
495 case REX_WB:
496 case REX_WX:
497 case REX_WXB:
498 case REX_WR:
499 case REX_WRB:
500 case REX_WRX:
501 case REX_WRXB:
502 NOT_LP64(assert(false, "64bit prefix found"));
503 goto again_after_size_prefix2;
504 case 0x8B: // movw r, a
505 case 0x89: // movw a, r
506 debug_only(has_disp32 = true);
507 break;
508 case 0xC7: // movw a, #16
509 debug_only(has_disp32 = true);
510 tail_size = 2; // the imm16
511 break;
512 case 0x0F: // several SSE/SSE2 variants
513 ip--; // reparse the 0x0F
514 goto again_after_prefix;
515 default:
516 ShouldNotReachHere();
517 }
518 break;
520 case REP8(0xB8): // movl/q r, #32/#64(oop?)
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
522 // these asserts are somewhat nonsensical
523 #ifndef _LP64
524 assert(which == imm_operand || which == disp32_operand,
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
526 #else
527 assert((which == call32_operand || which == imm_operand) && is_64bit ||
528 which == narrow_oop_operand && !is_64bit,
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
530 #endif // _LP64
531 return ip;
533 case 0x69: // imul r, a, #32
534 case 0xC7: // movl a, #32(oop?)
535 tail_size = 4;
536 debug_only(has_disp32 = true); // has both kinds of operands!
537 break;
539 case 0x0F: // movx..., etc.
540 switch (0xFF & *ip++) {
541 case 0x3A: // pcmpestri
542 tail_size = 1;
543 case 0x38: // ptest, pmovzxbw
544 ip++; // skip opcode
545 debug_only(has_disp32 = true); // has both kinds of operands!
546 break;
548 case 0x70: // pshufd r, r/a, #8
549 debug_only(has_disp32 = true); // has both kinds of operands!
550 case 0x73: // psrldq r, #8
551 tail_size = 1;
552 break;
554 case 0x12: // movlps
555 case 0x28: // movaps
556 case 0x2E: // ucomiss
557 case 0x2F: // comiss
558 case 0x54: // andps
559 case 0x55: // andnps
560 case 0x56: // orps
561 case 0x57: // xorps
562 case 0x6E: // movd
563 case 0x7E: // movd
564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
565 debug_only(has_disp32 = true);
566 break;
568 case 0xAD: // shrd r, a, %cl
569 case 0xAF: // imul r, a
570 case 0xBE: // movsbl r, a (movsxb)
571 case 0xBF: // movswl r, a (movsxw)
572 case 0xB6: // movzbl r, a (movzxb)
573 case 0xB7: // movzwl r, a (movzxw)
574 case REP16(0x40): // cmovl cc, r, a
575 case 0xB0: // cmpxchgb
576 case 0xB1: // cmpxchg
577 case 0xC1: // xaddl
578 case 0xC7: // cmpxchg8
579 case REP16(0x90): // setcc a
580 debug_only(has_disp32 = true);
581 // fall out of the switch to decode the address
582 break;
584 case 0xC4: // pinsrw r, a, #8
585 debug_only(has_disp32 = true);
586 case 0xC5: // pextrw r, r, #8
587 tail_size = 1; // the imm8
588 break;
590 case 0xAC: // shrd r, a, #8
591 debug_only(has_disp32 = true);
592 tail_size = 1; // the imm8
593 break;
595 case REP16(0x80): // jcc rdisp32
596 if (which == end_pc_operand) return ip + 4;
597 assert(which == call32_operand, "jcc has no disp32 or imm");
598 return ip;
599 default:
600 ShouldNotReachHere();
601 }
602 break;
604 case 0x81: // addl a, #32; addl r, #32
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
606 // on 32bit in the case of cmpl, the imm might be an oop
607 tail_size = 4;
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 break;
611 case 0x83: // addl a, #8; addl r, #8
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 tail_size = 1;
615 break;
617 case 0x9B:
618 switch (0xFF & *ip++) {
619 case 0xD9: // fnstcw a
620 debug_only(has_disp32 = true);
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 break;
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
628 case REP4(0x10): // adc...
629 case REP4(0x20): // and...
630 case REP4(0x30): // xor...
631 case REP4(0x08): // or...
632 case REP4(0x18): // sbb...
633 case REP4(0x28): // sub...
634 case 0xF7: // mull a
635 case 0x8D: // lea r, a
636 case 0x87: // xchg r, a
637 case REP4(0x38): // cmp...
638 case 0x85: // test r, a
639 debug_only(has_disp32 = true); // has both kinds of operands!
640 break;
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
643 case 0xC6: // movb a, #8
644 case 0x80: // cmpb a, #8
645 case 0x6B: // imul r, a, #8
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 tail_size = 1; // the imm8
648 break;
650 case 0xC4: // VEX_3bytes
651 case 0xC5: // VEX_2bytes
652 assert((UseAVX > 0), "shouldn't have VEX prefix");
653 assert(ip == inst+1, "no prefixes allowed");
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
655 // but they have prefix 0x0F and processed when 0x0F processed above.
656 //
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
658 // instructions (these instructions are not supported in 64-bit mode).
659 // To distinguish them bits [7:6] are set in the VEX second byte since
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
661 // those VEX bits REX and vvvv bits are inverted.
662 //
663 // Fortunately C2 doesn't generate these instructions so we don't need
664 // to check for them in product version.
666 // Check second byte
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
669 // First byte
670 if ((0xFF & *inst) == VEX_3bytes) {
671 ip++; // third byte
672 is_64bit = ((VEX_W & *ip) == VEX_W);
673 }
674 ip++; // opcode
675 // To find the end of instruction (which == end_pc_operand).
676 switch (0xFF & *ip) {
677 case 0x61: // pcmpestri r, r/a, #8
678 case 0x70: // pshufd r, r/a, #8
679 case 0x73: // psrldq r, #8
680 tail_size = 1; // the imm8
681 break;
682 default:
683 break;
684 }
685 ip++; // skip opcode
686 debug_only(has_disp32 = true); // has both kinds of operands!
687 break;
689 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
690 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
691 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
692 case 0xDD: // fld_d a; fst_d a; fstp_d a
693 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
694 case 0xDF: // fild_d a; fistp_d a
695 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
696 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
697 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
698 debug_only(has_disp32 = true);
699 break;
701 case 0xE8: // call rdisp32
702 case 0xE9: // jmp rdisp32
703 if (which == end_pc_operand) return ip + 4;
704 assert(which == call32_operand, "call has no disp32 or imm");
705 return ip;
707 case 0xF0: // Lock
708 assert(os::is_MP(), "only on MP");
709 goto again_after_prefix;
711 case 0xF3: // For SSE
712 case 0xF2: // For SSE2
713 switch (0xFF & *ip++) {
714 case REX:
715 case REX_B:
716 case REX_X:
717 case REX_XB:
718 case REX_R:
719 case REX_RB:
720 case REX_RX:
721 case REX_RXB:
722 case REX_W:
723 case REX_WB:
724 case REX_WX:
725 case REX_WXB:
726 case REX_WR:
727 case REX_WRB:
728 case REX_WRX:
729 case REX_WRXB:
730 NOT_LP64(assert(false, "found 64bit prefix"));
731 ip++;
732 default:
733 ip++;
734 }
735 debug_only(has_disp32 = true); // has both kinds of operands!
736 break;
738 default:
739 ShouldNotReachHere();
741 #undef REP8
742 #undef REP16
743 }
745 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
746 #ifdef _LP64
747 assert(which != imm_operand, "instruction is not a movq reg, imm64");
748 #else
749 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
750 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
751 #endif // LP64
752 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
754 // parse the output of emit_operand
755 int op2 = 0xFF & *ip++;
756 int base = op2 & 0x07;
757 int op3 = -1;
758 const int b100 = 4;
759 const int b101 = 5;
760 if (base == b100 && (op2 >> 6) != 3) {
761 op3 = 0xFF & *ip++;
762 base = op3 & 0x07; // refetch the base
763 }
764 // now ip points at the disp (if any)
766 switch (op2 >> 6) {
767 case 0:
768 // [00 reg 100][ss index base]
769 // [00 reg 100][00 100 esp]
770 // [00 reg base]
771 // [00 reg 100][ss index 101][disp32]
772 // [00 reg 101] [disp32]
774 if (base == b101) {
775 if (which == disp32_operand)
776 return ip; // caller wants the disp32
777 ip += 4; // skip the disp32
778 }
779 break;
781 case 1:
782 // [01 reg 100][ss index base][disp8]
783 // [01 reg 100][00 100 esp][disp8]
784 // [01 reg base] [disp8]
785 ip += 1; // skip the disp8
786 break;
788 case 2:
789 // [10 reg 100][ss index base][disp32]
790 // [10 reg 100][00 100 esp][disp32]
791 // [10 reg base] [disp32]
792 if (which == disp32_operand)
793 return ip; // caller wants the disp32
794 ip += 4; // skip the disp32
795 break;
797 case 3:
798 // [11 reg base] (not a memory addressing mode)
799 break;
800 }
802 if (which == end_pc_operand) {
803 return ip + tail_size;
804 }
806 #ifdef _LP64
807 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
808 #else
809 assert(which == imm_operand, "instruction has only an imm field");
810 #endif // LP64
811 return ip;
812 }
814 address Assembler::locate_next_instruction(address inst) {
815 // Secretly share code with locate_operand:
816 return locate_operand(inst, end_pc_operand);
817 }
820 #ifdef ASSERT
821 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
822 address inst = inst_mark();
823 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
824 address opnd;
826 Relocation* r = rspec.reloc();
827 if (r->type() == relocInfo::none) {
828 return;
829 } else if (r->is_call() || format == call32_operand) {
830 // assert(format == imm32_operand, "cannot specify a nonzero format");
831 opnd = locate_operand(inst, call32_operand);
832 } else if (r->is_data()) {
833 assert(format == imm_operand || format == disp32_operand
834 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
835 opnd = locate_operand(inst, (WhichOperand)format);
836 } else {
837 assert(format == imm_operand, "cannot specify a format");
838 return;
839 }
840 assert(opnd == pc(), "must put operand where relocs can find it");
841 }
842 #endif // ASSERT
844 void Assembler::emit_operand32(Register reg, Address adr) {
845 assert(reg->encoding() < 8, "no extended registers");
846 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
847 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
848 adr._rspec);
849 }
851 void Assembler::emit_operand(Register reg, Address adr,
852 int rip_relative_correction) {
853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
854 adr._rspec,
855 rip_relative_correction);
856 }
858 void Assembler::emit_operand(XMMRegister reg, Address adr) {
859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
860 adr._rspec);
861 }
863 // MMX operations
864 void Assembler::emit_operand(MMXRegister reg, Address adr) {
865 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
866 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
867 }
869 // work around gcc (3.2.1-7a) bug
870 void Assembler::emit_operand(Address adr, MMXRegister reg) {
871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
873 }
876 void Assembler::emit_farith(int b1, int b2, int i) {
877 assert(isByte(b1) && isByte(b2), "wrong opcode");
878 assert(0 <= i && i < 8, "illegal stack offset");
879 emit_int8(b1);
880 emit_int8(b2 + i);
881 }
884 // Now the Assembler instructions (identical for 32/64 bits)
886 void Assembler::adcl(Address dst, int32_t imm32) {
887 InstructionMark im(this);
888 prefix(dst);
889 emit_arith_operand(0x81, rdx, dst, imm32);
890 }
892 void Assembler::adcl(Address dst, Register src) {
893 InstructionMark im(this);
894 prefix(dst, src);
895 emit_int8(0x11);
896 emit_operand(src, dst);
897 }
899 void Assembler::adcl(Register dst, int32_t imm32) {
900 prefix(dst);
901 emit_arith(0x81, 0xD0, dst, imm32);
902 }
904 void Assembler::adcl(Register dst, Address src) {
905 InstructionMark im(this);
906 prefix(src, dst);
907 emit_int8(0x13);
908 emit_operand(dst, src);
909 }
911 void Assembler::adcl(Register dst, Register src) {
912 (void) prefix_and_encode(dst->encoding(), src->encoding());
913 emit_arith(0x13, 0xC0, dst, src);
914 }
916 void Assembler::addl(Address dst, int32_t imm32) {
917 InstructionMark im(this);
918 prefix(dst);
919 emit_arith_operand(0x81, rax, dst, imm32);
920 }
922 void Assembler::addl(Address dst, Register src) {
923 InstructionMark im(this);
924 prefix(dst, src);
925 emit_int8(0x01);
926 emit_operand(src, dst);
927 }
929 void Assembler::addl(Register dst, int32_t imm32) {
930 prefix(dst);
931 emit_arith(0x81, 0xC0, dst, imm32);
932 }
934 void Assembler::addl(Register dst, Address src) {
935 InstructionMark im(this);
936 prefix(src, dst);
937 emit_int8(0x03);
938 emit_operand(dst, src);
939 }
941 void Assembler::addl(Register dst, Register src) {
942 (void) prefix_and_encode(dst->encoding(), src->encoding());
943 emit_arith(0x03, 0xC0, dst, src);
944 }
946 void Assembler::addr_nop_4() {
947 assert(UseAddressNop, "no CPU support");
948 // 4 bytes: NOP DWORD PTR [EAX+0]
949 emit_int8(0x0F);
950 emit_int8(0x1F);
951 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
952 emit_int8(0); // 8-bits offset (1 byte)
953 }
955 void Assembler::addr_nop_5() {
956 assert(UseAddressNop, "no CPU support");
957 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
958 emit_int8(0x0F);
959 emit_int8(0x1F);
960 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
961 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
962 emit_int8(0); // 8-bits offset (1 byte)
963 }
965 void Assembler::addr_nop_7() {
966 assert(UseAddressNop, "no CPU support");
967 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
968 emit_int8(0x0F);
969 emit_int8(0x1F);
970 emit_int8((unsigned char)0x80);
971 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
972 emit_int32(0); // 32-bits offset (4 bytes)
973 }
975 void Assembler::addr_nop_8() {
976 assert(UseAddressNop, "no CPU support");
977 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
978 emit_int8(0x0F);
979 emit_int8(0x1F);
980 emit_int8((unsigned char)0x84);
981 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
982 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
983 emit_int32(0); // 32-bits offset (4 bytes)
984 }
986 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
988 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
989 }
991 void Assembler::addsd(XMMRegister dst, Address src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
996 void Assembler::addss(XMMRegister dst, XMMRegister src) {
997 NOT_LP64(assert(VM_Version::supports_sse(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
999 }
1001 void Assembler::addss(XMMRegister dst, Address src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1006 void Assembler::aesdec(XMMRegister dst, Address src) {
1007 assert(VM_Version::supports_aes(), "");
1008 InstructionMark im(this);
1009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1010 emit_int8((unsigned char)0xDE);
1011 emit_operand(dst, src);
1012 }
1014 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1015 assert(VM_Version::supports_aes(), "");
1016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_int8(0xC0 | encode);
1019 }
1021 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1022 assert(VM_Version::supports_aes(), "");
1023 InstructionMark im(this);
1024 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1025 emit_int8((unsigned char)0xDF);
1026 emit_operand(dst, src);
1027 }
1029 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1030 assert(VM_Version::supports_aes(), "");
1031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_int8((unsigned char)(0xC0 | encode));
1034 }
1036 void Assembler::aesenc(XMMRegister dst, Address src) {
1037 assert(VM_Version::supports_aes(), "");
1038 InstructionMark im(this);
1039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1040 emit_int8((unsigned char)0xDC);
1041 emit_operand(dst, src);
1042 }
1044 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1045 assert(VM_Version::supports_aes(), "");
1046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_int8(0xC0 | encode);
1049 }
1051 void Assembler::aesenclast(XMMRegister dst, Address src) {
1052 assert(VM_Version::supports_aes(), "");
1053 InstructionMark im(this);
1054 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1055 emit_int8((unsigned char)0xDD);
1056 emit_operand(dst, src);
1057 }
1059 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1060 assert(VM_Version::supports_aes(), "");
1061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_int8((unsigned char)(0xC0 | encode));
1064 }
1067 void Assembler::andl(Address dst, int32_t imm32) {
1068 InstructionMark im(this);
1069 prefix(dst);
1070 emit_int8((unsigned char)0x81);
1071 emit_operand(rsp, dst, 4);
1072 emit_int32(imm32);
1073 }
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1114 void Assembler::bsrl(Register dst, Register src) {
1115 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1116 emit_int8(0x0F);
1117 emit_int8((unsigned char)0xBD);
1118 emit_int8((unsigned char)(0xC0 | encode));
1119 }
1121 void Assembler::bswapl(Register reg) { // bswap
1122 int encode = prefix_and_encode(reg->encoding());
1123 emit_int8(0x0F);
1124 emit_int8((unsigned char)(0xC8 | encode));
1125 }
1127 void Assembler::blsil(Register dst, Register src) {
1128 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1129 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1130 emit_int8((unsigned char)0xF3);
1131 emit_int8((unsigned char)(0xC0 | encode));
1132 }
1134 void Assembler::blsil(Register dst, Address src) {
1135 InstructionMark im(this);
1136 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1137 vex_prefix_0F38(rbx, dst, src);
1138 emit_int8((unsigned char)0xF3);
1139 emit_operand(rbx, src);
1140 }
1142 void Assembler::blsmskl(Register dst, Register src) {
1143 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1144 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1145 emit_int8((unsigned char)0xF3);
1146 emit_int8((unsigned char)(0xC0 | encode));
1147 }
1149 void Assembler::blsmskl(Register dst, Address src) {
1150 InstructionMark im(this);
1151 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1152 vex_prefix_0F38(rdx, dst, src);
1153 emit_int8((unsigned char)0xF3);
1154 emit_operand(rdx, src);
1155 }
1157 void Assembler::blsrl(Register dst, Register src) {
1158 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1159 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1160 emit_int8((unsigned char)0xF3);
1161 emit_int8((unsigned char)(0xC0 | encode));
1162 }
1164 void Assembler::blsrl(Register dst, Address src) {
1165 InstructionMark im(this);
1166 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1167 vex_prefix_0F38(rcx, dst, src);
1168 emit_int8((unsigned char)0xF3);
1169 emit_operand(rcx, src);
1170 }
1172 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1173 // suspect disp32 is always good
1174 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1176 if (L.is_bound()) {
1177 const int long_size = 5;
1178 int offs = (int)( target(L) - pc() );
1179 assert(offs <= 0, "assembler error");
1180 InstructionMark im(this);
1181 // 1110 1000 #32-bit disp
1182 emit_int8((unsigned char)0xE8);
1183 emit_data(offs - long_size, rtype, operand);
1184 } else {
1185 InstructionMark im(this);
1186 // 1110 1000 #32-bit disp
1187 L.add_patch_at(code(), locator());
1189 emit_int8((unsigned char)0xE8);
1190 emit_data(int(0), rtype, operand);
1191 }
1192 }
1194 void Assembler::call(Register dst) {
1195 int encode = prefix_and_encode(dst->encoding());
1196 emit_int8((unsigned char)0xFF);
1197 emit_int8((unsigned char)(0xD0 | encode));
1198 }
1201 void Assembler::call(Address adr) {
1202 InstructionMark im(this);
1203 prefix(adr);
1204 emit_int8((unsigned char)0xFF);
1205 emit_operand(rdx, adr);
1206 }
1208 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1209 assert(entry != NULL, "call most probably wrong");
1210 InstructionMark im(this);
1211 emit_int8((unsigned char)0xE8);
1212 intptr_t disp = entry - (pc() + sizeof(int32_t));
1213 assert(is_simm32(disp), "must be 32bit offset (call2)");
1214 // Technically, should use call32_operand, but this format is
1215 // implied by the fact that we're emitting a call instruction.
1217 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1218 emit_data((int) disp, rspec, operand);
1219 }
1221 void Assembler::cdql() {
1222 emit_int8((unsigned char)0x99);
1223 }
1225 void Assembler::cld() {
1226 emit_int8((unsigned char)0xFC);
1227 }
1229 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1230 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1231 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1232 emit_int8(0x0F);
1233 emit_int8(0x40 | cc);
1234 emit_int8((unsigned char)(0xC0 | encode));
1235 }
1238 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1239 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1240 prefix(src, dst);
1241 emit_int8(0x0F);
1242 emit_int8(0x40 | cc);
1243 emit_operand(dst, src);
1244 }
1246 void Assembler::cmpb(Address dst, int imm8) {
1247 InstructionMark im(this);
1248 prefix(dst);
1249 emit_int8((unsigned char)0x80);
1250 emit_operand(rdi, dst, 1);
1251 emit_int8(imm8);
1252 }
1254 void Assembler::cmpl(Address dst, int32_t imm32) {
1255 InstructionMark im(this);
1256 prefix(dst);
1257 emit_int8((unsigned char)0x81);
1258 emit_operand(rdi, dst, 4);
1259 emit_int32(imm32);
1260 }
1262 void Assembler::cmpl(Register dst, int32_t imm32) {
1263 prefix(dst);
1264 emit_arith(0x81, 0xF8, dst, imm32);
1265 }
1267 void Assembler::cmpl(Register dst, Register src) {
1268 (void) prefix_and_encode(dst->encoding(), src->encoding());
1269 emit_arith(0x3B, 0xC0, dst, src);
1270 }
1273 void Assembler::cmpl(Register dst, Address src) {
1274 InstructionMark im(this);
1275 prefix(src, dst);
1276 emit_int8((unsigned char)0x3B);
1277 emit_operand(dst, src);
1278 }
1280 void Assembler::cmpw(Address dst, int imm16) {
1281 InstructionMark im(this);
1282 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1283 emit_int8(0x66);
1284 emit_int8((unsigned char)0x81);
1285 emit_operand(rdi, dst, 2);
1286 emit_int16(imm16);
1287 }
1289 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1290 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1291 // The ZF is set if the compared values were equal, and cleared otherwise.
1292 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1293 InstructionMark im(this);
1294 prefix(adr, reg);
1295 emit_int8(0x0F);
1296 emit_int8((unsigned char)0xB1);
1297 emit_operand(reg, adr);
1298 }
1300 void Assembler::comisd(XMMRegister dst, Address src) {
1301 // NOTE: dbx seems to decode this as comiss even though the
1302 // 0x66 is there. Strangly ucomisd comes out correct
1303 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1304 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1305 }
1307 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1309 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1310 }
1312 void Assembler::comiss(XMMRegister dst, Address src) {
1313 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1314 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1315 }
1317 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1318 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1319 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1320 }
1322 void Assembler::cpuid() {
1323 emit_int8(0x0F);
1324 emit_int8((unsigned char)0xA2);
1325 }
1327 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1329 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1330 }
1332 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1334 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1335 }
1337 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1338 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1339 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1340 }
1342 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1344 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1345 }
1347 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1350 emit_int8(0x2A);
1351 emit_int8((unsigned char)(0xC0 | encode));
1352 }
1354 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1356 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1357 }
1359 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1360 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1361 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1362 emit_int8(0x2A);
1363 emit_int8((unsigned char)(0xC0 | encode));
1364 }
1366 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1367 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1368 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1369 }
1371 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1373 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1374 }
1376 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1378 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1379 }
1382 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1384 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1385 emit_int8(0x2C);
1386 emit_int8((unsigned char)(0xC0 | encode));
1387 }
1389 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1390 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1391 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1392 emit_int8(0x2C);
1393 emit_int8((unsigned char)(0xC0 | encode));
1394 }
1396 void Assembler::decl(Address dst) {
1397 // Don't use it directly. Use MacroAssembler::decrement() instead.
1398 InstructionMark im(this);
1399 prefix(dst);
1400 emit_int8((unsigned char)0xFF);
1401 emit_operand(rcx, dst);
1402 }
1404 void Assembler::divsd(XMMRegister dst, Address src) {
1405 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1406 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1407 }
1409 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1411 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1412 }
1414 void Assembler::divss(XMMRegister dst, Address src) {
1415 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1416 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1417 }
1419 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1420 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1421 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1422 }
1424 void Assembler::emms() {
1425 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1426 emit_int8(0x0F);
1427 emit_int8(0x77);
1428 }
1430 void Assembler::hlt() {
1431 emit_int8((unsigned char)0xF4);
1432 }
1434 void Assembler::idivl(Register src) {
1435 int encode = prefix_and_encode(src->encoding());
1436 emit_int8((unsigned char)0xF7);
1437 emit_int8((unsigned char)(0xF8 | encode));
1438 }
1440 void Assembler::divl(Register src) { // Unsigned
1441 int encode = prefix_and_encode(src->encoding());
1442 emit_int8((unsigned char)0xF7);
1443 emit_int8((unsigned char)(0xF0 | encode));
1444 }
1446 void Assembler::imull(Register dst, Register src) {
1447 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1448 emit_int8(0x0F);
1449 emit_int8((unsigned char)0xAF);
1450 emit_int8((unsigned char)(0xC0 | encode));
1451 }
1454 void Assembler::imull(Register dst, Register src, int value) {
1455 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1456 if (is8bit(value)) {
1457 emit_int8(0x6B);
1458 emit_int8((unsigned char)(0xC0 | encode));
1459 emit_int8(value & 0xFF);
1460 } else {
1461 emit_int8(0x69);
1462 emit_int8((unsigned char)(0xC0 | encode));
1463 emit_int32(value);
1464 }
1465 }
1467 void Assembler::imull(Register dst, Address src) {
1468 InstructionMark im(this);
1469 prefix(src, dst);
1470 emit_int8(0x0F);
1471 emit_int8((unsigned char) 0xAF);
1472 emit_operand(dst, src);
1473 }
1476 void Assembler::incl(Address dst) {
1477 // Don't use it directly. Use MacroAssembler::increment() instead.
1478 InstructionMark im(this);
1479 prefix(dst);
1480 emit_int8((unsigned char)0xFF);
1481 emit_operand(rax, dst);
1482 }
1484 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1485 InstructionMark im(this);
1486 assert((0 <= cc) && (cc < 16), "illegal cc");
1487 if (L.is_bound()) {
1488 address dst = target(L);
1489 assert(dst != NULL, "jcc most probably wrong");
1491 const int short_size = 2;
1492 const int long_size = 6;
1493 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1494 if (maybe_short && is8bit(offs - short_size)) {
1495 // 0111 tttn #8-bit disp
1496 emit_int8(0x70 | cc);
1497 emit_int8((offs - short_size) & 0xFF);
1498 } else {
1499 // 0000 1111 1000 tttn #32-bit disp
1500 assert(is_simm32(offs - long_size),
1501 "must be 32bit offset (call4)");
1502 emit_int8(0x0F);
1503 emit_int8((unsigned char)(0x80 | cc));
1504 emit_int32(offs - long_size);
1505 }
1506 } else {
1507 // Note: could eliminate cond. jumps to this jump if condition
1508 // is the same however, seems to be rather unlikely case.
1509 // Note: use jccb() if label to be bound is very close to get
1510 // an 8-bit displacement
1511 L.add_patch_at(code(), locator());
1512 emit_int8(0x0F);
1513 emit_int8((unsigned char)(0x80 | cc));
1514 emit_int32(0);
1515 }
1516 }
1518 void Assembler::jccb(Condition cc, Label& L) {
1519 if (L.is_bound()) {
1520 const int short_size = 2;
1521 address entry = target(L);
1522 #ifdef ASSERT
1523 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1524 intptr_t delta = short_branch_delta();
1525 if (delta != 0) {
1526 dist += (dist < 0 ? (-delta) :delta);
1527 }
1528 assert(is8bit(dist), "Dispacement too large for a short jmp");
1529 #endif
1530 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1531 // 0111 tttn #8-bit disp
1532 emit_int8(0x70 | cc);
1533 emit_int8((offs - short_size) & 0xFF);
1534 } else {
1535 InstructionMark im(this);
1536 L.add_patch_at(code(), locator());
1537 emit_int8(0x70 | cc);
1538 emit_int8(0);
1539 }
1540 }
1542 void Assembler::jmp(Address adr) {
1543 InstructionMark im(this);
1544 prefix(adr);
1545 emit_int8((unsigned char)0xFF);
1546 emit_operand(rsp, adr);
1547 }
1549 void Assembler::jmp(Label& L, bool maybe_short) {
1550 if (L.is_bound()) {
1551 address entry = target(L);
1552 assert(entry != NULL, "jmp most probably wrong");
1553 InstructionMark im(this);
1554 const int short_size = 2;
1555 const int long_size = 5;
1556 intptr_t offs = entry - pc();
1557 if (maybe_short && is8bit(offs - short_size)) {
1558 emit_int8((unsigned char)0xEB);
1559 emit_int8((offs - short_size) & 0xFF);
1560 } else {
1561 emit_int8((unsigned char)0xE9);
1562 emit_int32(offs - long_size);
1563 }
1564 } else {
1565 // By default, forward jumps are always 32-bit displacements, since
1566 // we can't yet know where the label will be bound. If you're sure that
1567 // the forward jump will not run beyond 256 bytes, use jmpb to
1568 // force an 8-bit displacement.
1569 InstructionMark im(this);
1570 L.add_patch_at(code(), locator());
1571 emit_int8((unsigned char)0xE9);
1572 emit_int32(0);
1573 }
1574 }
1576 void Assembler::jmp(Register entry) {
1577 int encode = prefix_and_encode(entry->encoding());
1578 emit_int8((unsigned char)0xFF);
1579 emit_int8((unsigned char)(0xE0 | encode));
1580 }
1582 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1583 InstructionMark im(this);
1584 emit_int8((unsigned char)0xE9);
1585 assert(dest != NULL, "must have a target");
1586 intptr_t disp = dest - (pc() + sizeof(int32_t));
1587 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1588 emit_data(disp, rspec.reloc(), call32_operand);
1589 }
1591 void Assembler::jmpb(Label& L) {
1592 if (L.is_bound()) {
1593 const int short_size = 2;
1594 address entry = target(L);
1595 assert(entry != NULL, "jmp most probably wrong");
1596 #ifdef ASSERT
1597 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1598 intptr_t delta = short_branch_delta();
1599 if (delta != 0) {
1600 dist += (dist < 0 ? (-delta) :delta);
1601 }
1602 assert(is8bit(dist), "Dispacement too large for a short jmp");
1603 #endif
1604 intptr_t offs = entry - pc();
1605 emit_int8((unsigned char)0xEB);
1606 emit_int8((offs - short_size) & 0xFF);
1607 } else {
1608 InstructionMark im(this);
1609 L.add_patch_at(code(), locator());
1610 emit_int8((unsigned char)0xEB);
1611 emit_int8(0);
1612 }
1613 }
1615 void Assembler::ldmxcsr( Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617 InstructionMark im(this);
1618 prefix(src);
1619 emit_int8(0x0F);
1620 emit_int8((unsigned char)0xAE);
1621 emit_operand(as_Register(2), src);
1622 }
1624 void Assembler::leal(Register dst, Address src) {
1625 InstructionMark im(this);
1626 #ifdef _LP64
1627 emit_int8(0x67); // addr32
1628 prefix(src, dst);
1629 #endif // LP64
1630 emit_int8((unsigned char)0x8D);
1631 emit_operand(dst, src);
1632 }
1634 void Assembler::lfence() {
1635 emit_int8(0x0F);
1636 emit_int8((unsigned char)0xAE);
1637 emit_int8((unsigned char)0xE8);
1638 }
1640 void Assembler::lock() {
1641 emit_int8((unsigned char)0xF0);
1642 }
1644 void Assembler::lzcntl(Register dst, Register src) {
1645 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1646 emit_int8((unsigned char)0xF3);
1647 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1648 emit_int8(0x0F);
1649 emit_int8((unsigned char)0xBD);
1650 emit_int8((unsigned char)(0xC0 | encode));
1651 }
1653 // Emit mfence instruction
1654 void Assembler::mfence() {
1655 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1656 emit_int8(0x0F);
1657 emit_int8((unsigned char)0xAE);
1658 emit_int8((unsigned char)0xF0);
1659 }
1661 void Assembler::mov(Register dst, Register src) {
1662 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1663 }
1665 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1666 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1667 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1668 }
1670 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1671 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1672 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1673 }
1675 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1676 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1677 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1678 emit_int8(0x16);
1679 emit_int8((unsigned char)(0xC0 | encode));
1680 }
1682 void Assembler::movb(Register dst, Address src) {
1683 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1684 InstructionMark im(this);
1685 prefix(src, dst, true);
1686 emit_int8((unsigned char)0x8A);
1687 emit_operand(dst, src);
1688 }
1691 void Assembler::movb(Address dst, int imm8) {
1692 InstructionMark im(this);
1693 prefix(dst);
1694 emit_int8((unsigned char)0xC6);
1695 emit_operand(rax, dst, 1);
1696 emit_int8(imm8);
1697 }
1700 void Assembler::movb(Address dst, Register src) {
1701 assert(src->has_byte_register(), "must have byte register");
1702 InstructionMark im(this);
1703 prefix(dst, src, true);
1704 emit_int8((unsigned char)0x88);
1705 emit_operand(src, dst);
1706 }
1708 void Assembler::movdl(XMMRegister dst, Register src) {
1709 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1710 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1711 emit_int8(0x6E);
1712 emit_int8((unsigned char)(0xC0 | encode));
1713 }
1715 void Assembler::movdl(Register dst, XMMRegister src) {
1716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1717 // swap src/dst to get correct prefix
1718 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1719 emit_int8(0x7E);
1720 emit_int8((unsigned char)(0xC0 | encode));
1721 }
1723 void Assembler::movdl(XMMRegister dst, Address src) {
1724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1725 InstructionMark im(this);
1726 simd_prefix(dst, src, VEX_SIMD_66);
1727 emit_int8(0x6E);
1728 emit_operand(dst, src);
1729 }
1731 void Assembler::movdl(Address dst, XMMRegister src) {
1732 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1733 InstructionMark im(this);
1734 simd_prefix(dst, src, VEX_SIMD_66);
1735 emit_int8(0x7E);
1736 emit_operand(src, dst);
1737 }
1739 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1740 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1741 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1742 }
1744 void Assembler::movdqa(XMMRegister dst, Address src) {
1745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1746 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1747 }
1749 void Assembler::movdqu(XMMRegister dst, Address src) {
1750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1751 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1752 }
1754 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1756 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1757 }
1759 void Assembler::movdqu(Address dst, XMMRegister src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 InstructionMark im(this);
1762 simd_prefix(dst, src, VEX_SIMD_F3);
1763 emit_int8(0x7F);
1764 emit_operand(src, dst);
1765 }
1767 // Move Unaligned 256bit Vector
1768 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1769 assert(UseAVX, "");
1770 bool vector256 = true;
1771 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1772 emit_int8(0x6F);
1773 emit_int8((unsigned char)(0xC0 | encode));
1774 }
1776 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1777 assert(UseAVX, "");
1778 InstructionMark im(this);
1779 bool vector256 = true;
1780 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1781 emit_int8(0x6F);
1782 emit_operand(dst, src);
1783 }
1785 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1786 assert(UseAVX, "");
1787 InstructionMark im(this);
1788 bool vector256 = true;
1789 // swap src<->dst for encoding
1790 assert(src != xnoreg, "sanity");
1791 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1792 emit_int8(0x7F);
1793 emit_operand(src, dst);
1794 }
1796 // Uses zero extension on 64bit
1798 void Assembler::movl(Register dst, int32_t imm32) {
1799 int encode = prefix_and_encode(dst->encoding());
1800 emit_int8((unsigned char)(0xB8 | encode));
1801 emit_int32(imm32);
1802 }
1804 void Assembler::movl(Register dst, Register src) {
1805 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1806 emit_int8((unsigned char)0x8B);
1807 emit_int8((unsigned char)(0xC0 | encode));
1808 }
1810 void Assembler::movl(Register dst, Address src) {
1811 InstructionMark im(this);
1812 prefix(src, dst);
1813 emit_int8((unsigned char)0x8B);
1814 emit_operand(dst, src);
1815 }
1817 void Assembler::movl(Address dst, int32_t imm32) {
1818 InstructionMark im(this);
1819 prefix(dst);
1820 emit_int8((unsigned char)0xC7);
1821 emit_operand(rax, dst, 4);
1822 emit_int32(imm32);
1823 }
1825 void Assembler::movl(Address dst, Register src) {
1826 InstructionMark im(this);
1827 prefix(dst, src);
1828 emit_int8((unsigned char)0x89);
1829 emit_operand(src, dst);
1830 }
1832 // New cpus require to use movsd and movss to avoid partial register stall
1833 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1834 // The selection is done in MacroAssembler::movdbl() and movflt().
1835 void Assembler::movlpd(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1837 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1838 }
1840 void Assembler::movq( MMXRegister dst, Address src ) {
1841 assert( VM_Version::supports_mmx(), "" );
1842 emit_int8(0x0F);
1843 emit_int8(0x6F);
1844 emit_operand(dst, src);
1845 }
1847 void Assembler::movq( Address dst, MMXRegister src ) {
1848 assert( VM_Version::supports_mmx(), "" );
1849 emit_int8(0x0F);
1850 emit_int8(0x7F);
1851 // workaround gcc (3.2.1-7a) bug
1852 // In that version of gcc with only an emit_operand(MMX, Address)
1853 // gcc will tail jump and try and reverse the parameters completely
1854 // obliterating dst in the process. By having a version available
1855 // that doesn't need to swap the args at the tail jump the bug is
1856 // avoided.
1857 emit_operand(dst, src);
1858 }
1860 void Assembler::movq(XMMRegister dst, Address src) {
1861 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1862 InstructionMark im(this);
1863 simd_prefix(dst, src, VEX_SIMD_F3);
1864 emit_int8(0x7E);
1865 emit_operand(dst, src);
1866 }
1868 void Assembler::movq(Address dst, XMMRegister src) {
1869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1870 InstructionMark im(this);
1871 simd_prefix(dst, src, VEX_SIMD_66);
1872 emit_int8((unsigned char)0xD6);
1873 emit_operand(src, dst);
1874 }
1876 void Assembler::movsbl(Register dst, Address src) { // movsxb
1877 InstructionMark im(this);
1878 prefix(src, dst);
1879 emit_int8(0x0F);
1880 emit_int8((unsigned char)0xBE);
1881 emit_operand(dst, src);
1882 }
1884 void Assembler::movsbl(Register dst, Register src) { // movsxb
1885 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1886 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1887 emit_int8(0x0F);
1888 emit_int8((unsigned char)0xBE);
1889 emit_int8((unsigned char)(0xC0 | encode));
1890 }
1892 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1894 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1895 }
1897 void Assembler::movsd(XMMRegister dst, Address src) {
1898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1899 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1900 }
1902 void Assembler::movsd(Address dst, XMMRegister src) {
1903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1904 InstructionMark im(this);
1905 simd_prefix(dst, src, VEX_SIMD_F2);
1906 emit_int8(0x11);
1907 emit_operand(src, dst);
1908 }
1910 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1911 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1912 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1913 }
1915 void Assembler::movss(XMMRegister dst, Address src) {
1916 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1917 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1918 }
1920 void Assembler::movss(Address dst, XMMRegister src) {
1921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1922 InstructionMark im(this);
1923 simd_prefix(dst, src, VEX_SIMD_F3);
1924 emit_int8(0x11);
1925 emit_operand(src, dst);
1926 }
1928 void Assembler::movswl(Register dst, Address src) { // movsxw
1929 InstructionMark im(this);
1930 prefix(src, dst);
1931 emit_int8(0x0F);
1932 emit_int8((unsigned char)0xBF);
1933 emit_operand(dst, src);
1934 }
1936 void Assembler::movswl(Register dst, Register src) { // movsxw
1937 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1938 emit_int8(0x0F);
1939 emit_int8((unsigned char)0xBF);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1943 void Assembler::movw(Address dst, int imm16) {
1944 InstructionMark im(this);
1946 emit_int8(0x66); // switch to 16-bit mode
1947 prefix(dst);
1948 emit_int8((unsigned char)0xC7);
1949 emit_operand(rax, dst, 2);
1950 emit_int16(imm16);
1951 }
1953 void Assembler::movw(Register dst, Address src) {
1954 InstructionMark im(this);
1955 emit_int8(0x66);
1956 prefix(src, dst);
1957 emit_int8((unsigned char)0x8B);
1958 emit_operand(dst, src);
1959 }
1961 void Assembler::movw(Address dst, Register src) {
1962 InstructionMark im(this);
1963 emit_int8(0x66);
1964 prefix(dst, src);
1965 emit_int8((unsigned char)0x89);
1966 emit_operand(src, dst);
1967 }
1969 void Assembler::movzbl(Register dst, Address src) { // movzxb
1970 InstructionMark im(this);
1971 prefix(src, dst);
1972 emit_int8(0x0F);
1973 emit_int8((unsigned char)0xB6);
1974 emit_operand(dst, src);
1975 }
1977 void Assembler::movzbl(Register dst, Register src) { // movzxb
1978 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1979 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1980 emit_int8(0x0F);
1981 emit_int8((unsigned char)0xB6);
1982 emit_int8(0xC0 | encode);
1983 }
1985 void Assembler::movzwl(Register dst, Address src) { // movzxw
1986 InstructionMark im(this);
1987 prefix(src, dst);
1988 emit_int8(0x0F);
1989 emit_int8((unsigned char)0xB7);
1990 emit_operand(dst, src);
1991 }
1993 void Assembler::movzwl(Register dst, Register src) { // movzxw
1994 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1995 emit_int8(0x0F);
1996 emit_int8((unsigned char)0xB7);
1997 emit_int8(0xC0 | encode);
1998 }
2000 void Assembler::mull(Address src) {
2001 InstructionMark im(this);
2002 prefix(src);
2003 emit_int8((unsigned char)0xF7);
2004 emit_operand(rsp, src);
2005 }
2007 void Assembler::mull(Register src) {
2008 int encode = prefix_and_encode(src->encoding());
2009 emit_int8((unsigned char)0xF7);
2010 emit_int8((unsigned char)(0xE0 | encode));
2011 }
2013 void Assembler::mulsd(XMMRegister dst, Address src) {
2014 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2015 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2016 }
2018 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2019 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2020 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2021 }
2023 void Assembler::mulss(XMMRegister dst, Address src) {
2024 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2025 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2026 }
2028 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2029 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2030 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2031 }
2033 void Assembler::negl(Register dst) {
2034 int encode = prefix_and_encode(dst->encoding());
2035 emit_int8((unsigned char)0xF7);
2036 emit_int8((unsigned char)(0xD8 | encode));
2037 }
2039 void Assembler::nop(int i) {
2040 #ifdef ASSERT
2041 assert(i > 0, " ");
2042 // The fancy nops aren't currently recognized by debuggers making it a
2043 // pain to disassemble code while debugging. If asserts are on clearly
2044 // speed is not an issue so simply use the single byte traditional nop
2045 // to do alignment.
2047 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2048 return;
2050 #endif // ASSERT
2052 if (UseAddressNop && VM_Version::is_intel()) {
2053 //
2054 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2055 // 1: 0x90
2056 // 2: 0x66 0x90
2057 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2058 // 4: 0x0F 0x1F 0x40 0x00
2059 // 5: 0x0F 0x1F 0x44 0x00 0x00
2060 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2061 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2062 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2063 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2064 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2065 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2067 // The rest coding is Intel specific - don't use consecutive address nops
2069 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2070 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2071 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2072 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2074 while(i >= 15) {
2075 // For Intel don't generate consecutive addess nops (mix with regular nops)
2076 i -= 15;
2077 emit_int8(0x66); // size prefix
2078 emit_int8(0x66); // size prefix
2079 emit_int8(0x66); // size prefix
2080 addr_nop_8();
2081 emit_int8(0x66); // size prefix
2082 emit_int8(0x66); // size prefix
2083 emit_int8(0x66); // size prefix
2084 emit_int8((unsigned char)0x90);
2085 // nop
2086 }
2087 switch (i) {
2088 case 14:
2089 emit_int8(0x66); // size prefix
2090 case 13:
2091 emit_int8(0x66); // size prefix
2092 case 12:
2093 addr_nop_8();
2094 emit_int8(0x66); // size prefix
2095 emit_int8(0x66); // size prefix
2096 emit_int8(0x66); // size prefix
2097 emit_int8((unsigned char)0x90);
2098 // nop
2099 break;
2100 case 11:
2101 emit_int8(0x66); // size prefix
2102 case 10:
2103 emit_int8(0x66); // size prefix
2104 case 9:
2105 emit_int8(0x66); // size prefix
2106 case 8:
2107 addr_nop_8();
2108 break;
2109 case 7:
2110 addr_nop_7();
2111 break;
2112 case 6:
2113 emit_int8(0x66); // size prefix
2114 case 5:
2115 addr_nop_5();
2116 break;
2117 case 4:
2118 addr_nop_4();
2119 break;
2120 case 3:
2121 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2122 emit_int8(0x66); // size prefix
2123 case 2:
2124 emit_int8(0x66); // size prefix
2125 case 1:
2126 emit_int8((unsigned char)0x90);
2127 // nop
2128 break;
2129 default:
2130 assert(i == 0, " ");
2131 }
2132 return;
2133 }
2134 if (UseAddressNop && VM_Version::is_amd()) {
2135 //
2136 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2137 // 1: 0x90
2138 // 2: 0x66 0x90
2139 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2140 // 4: 0x0F 0x1F 0x40 0x00
2141 // 5: 0x0F 0x1F 0x44 0x00 0x00
2142 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2143 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2144 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2145 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2146 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2147 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2149 // The rest coding is AMD specific - use consecutive address nops
2151 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2152 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2153 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2154 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2155 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2156 // Size prefixes (0x66) are added for larger sizes
2158 while(i >= 22) {
2159 i -= 11;
2160 emit_int8(0x66); // size prefix
2161 emit_int8(0x66); // size prefix
2162 emit_int8(0x66); // size prefix
2163 addr_nop_8();
2164 }
2165 // Generate first nop for size between 21-12
2166 switch (i) {
2167 case 21:
2168 i -= 1;
2169 emit_int8(0x66); // size prefix
2170 case 20:
2171 case 19:
2172 i -= 1;
2173 emit_int8(0x66); // size prefix
2174 case 18:
2175 case 17:
2176 i -= 1;
2177 emit_int8(0x66); // size prefix
2178 case 16:
2179 case 15:
2180 i -= 8;
2181 addr_nop_8();
2182 break;
2183 case 14:
2184 case 13:
2185 i -= 7;
2186 addr_nop_7();
2187 break;
2188 case 12:
2189 i -= 6;
2190 emit_int8(0x66); // size prefix
2191 addr_nop_5();
2192 break;
2193 default:
2194 assert(i < 12, " ");
2195 }
2197 // Generate second nop for size between 11-1
2198 switch (i) {
2199 case 11:
2200 emit_int8(0x66); // size prefix
2201 case 10:
2202 emit_int8(0x66); // size prefix
2203 case 9:
2204 emit_int8(0x66); // size prefix
2205 case 8:
2206 addr_nop_8();
2207 break;
2208 case 7:
2209 addr_nop_7();
2210 break;
2211 case 6:
2212 emit_int8(0x66); // size prefix
2213 case 5:
2214 addr_nop_5();
2215 break;
2216 case 4:
2217 addr_nop_4();
2218 break;
2219 case 3:
2220 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2221 emit_int8(0x66); // size prefix
2222 case 2:
2223 emit_int8(0x66); // size prefix
2224 case 1:
2225 emit_int8((unsigned char)0x90);
2226 // nop
2227 break;
2228 default:
2229 assert(i == 0, " ");
2230 }
2231 return;
2232 }
2234 // Using nops with size prefixes "0x66 0x90".
2235 // From AMD Optimization Guide:
2236 // 1: 0x90
2237 // 2: 0x66 0x90
2238 // 3: 0x66 0x66 0x90
2239 // 4: 0x66 0x66 0x66 0x90
2240 // 5: 0x66 0x66 0x90 0x66 0x90
2241 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2242 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2243 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2244 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2245 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2246 //
2247 while(i > 12) {
2248 i -= 4;
2249 emit_int8(0x66); // size prefix
2250 emit_int8(0x66);
2251 emit_int8(0x66);
2252 emit_int8((unsigned char)0x90);
2253 // nop
2254 }
2255 // 1 - 12 nops
2256 if(i > 8) {
2257 if(i > 9) {
2258 i -= 1;
2259 emit_int8(0x66);
2260 }
2261 i -= 3;
2262 emit_int8(0x66);
2263 emit_int8(0x66);
2264 emit_int8((unsigned char)0x90);
2265 }
2266 // 1 - 8 nops
2267 if(i > 4) {
2268 if(i > 6) {
2269 i -= 1;
2270 emit_int8(0x66);
2271 }
2272 i -= 3;
2273 emit_int8(0x66);
2274 emit_int8(0x66);
2275 emit_int8((unsigned char)0x90);
2276 }
2277 switch (i) {
2278 case 4:
2279 emit_int8(0x66);
2280 case 3:
2281 emit_int8(0x66);
2282 case 2:
2283 emit_int8(0x66);
2284 case 1:
2285 emit_int8((unsigned char)0x90);
2286 break;
2287 default:
2288 assert(i == 0, " ");
2289 }
2290 }
2292 void Assembler::notl(Register dst) {
2293 int encode = prefix_and_encode(dst->encoding());
2294 emit_int8((unsigned char)0xF7);
2295 emit_int8((unsigned char)(0xD0 | encode));
2296 }
2298 void Assembler::orl(Address dst, int32_t imm32) {
2299 InstructionMark im(this);
2300 prefix(dst);
2301 emit_arith_operand(0x81, rcx, dst, imm32);
2302 }
2304 void Assembler::orl(Register dst, int32_t imm32) {
2305 prefix(dst);
2306 emit_arith(0x81, 0xC8, dst, imm32);
2307 }
2309 void Assembler::orl(Register dst, Address src) {
2310 InstructionMark im(this);
2311 prefix(src, dst);
2312 emit_int8(0x0B);
2313 emit_operand(dst, src);
2314 }
2316 void Assembler::orl(Register dst, Register src) {
2317 (void) prefix_and_encode(dst->encoding(), src->encoding());
2318 emit_arith(0x0B, 0xC0, dst, src);
2319 }
2321 void Assembler::packuswb(XMMRegister dst, Address src) {
2322 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2323 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2324 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2325 }
2327 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2329 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2330 }
2332 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2333 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2334 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2335 }
2337 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2338 assert(VM_Version::supports_avx2(), "");
2339 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2340 emit_int8(0x00);
2341 emit_int8(0xC0 | encode);
2342 emit_int8(imm8);
2343 }
2345 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2346 assert(VM_Version::supports_sse4_2(), "");
2347 InstructionMark im(this);
2348 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2349 emit_int8(0x61);
2350 emit_operand(dst, src);
2351 emit_int8(imm8);
2352 }
2354 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2355 assert(VM_Version::supports_sse4_2(), "");
2356 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2357 emit_int8(0x61);
2358 emit_int8((unsigned char)(0xC0 | encode));
2359 emit_int8(imm8);
2360 }
2362 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2363 assert(VM_Version::supports_sse4_1(), "");
2364 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2365 emit_int8(0x16);
2366 emit_int8((unsigned char)(0xC0 | encode));
2367 emit_int8(imm8);
2368 }
2370 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2371 assert(VM_Version::supports_sse4_1(), "");
2372 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2373 emit_int8(0x16);
2374 emit_int8((unsigned char)(0xC0 | encode));
2375 emit_int8(imm8);
2376 }
2378 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2379 assert(VM_Version::supports_sse4_1(), "");
2380 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2381 emit_int8(0x22);
2382 emit_int8((unsigned char)(0xC0 | encode));
2383 emit_int8(imm8);
2384 }
2386 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2387 assert(VM_Version::supports_sse4_1(), "");
2388 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2389 emit_int8(0x22);
2390 emit_int8((unsigned char)(0xC0 | encode));
2391 emit_int8(imm8);
2392 }
2394 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2395 assert(VM_Version::supports_sse4_1(), "");
2396 InstructionMark im(this);
2397 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2398 emit_int8(0x30);
2399 emit_operand(dst, src);
2400 }
2402 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2403 assert(VM_Version::supports_sse4_1(), "");
2404 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2405 emit_int8(0x30);
2406 emit_int8((unsigned char)(0xC0 | encode));
2407 }
2409 // generic
2410 void Assembler::pop(Register dst) {
2411 int encode = prefix_and_encode(dst->encoding());
2412 emit_int8(0x58 | encode);
2413 }
2415 void Assembler::popcntl(Register dst, Address src) {
2416 assert(VM_Version::supports_popcnt(), "must support");
2417 InstructionMark im(this);
2418 emit_int8((unsigned char)0xF3);
2419 prefix(src, dst);
2420 emit_int8(0x0F);
2421 emit_int8((unsigned char)0xB8);
2422 emit_operand(dst, src);
2423 }
2425 void Assembler::popcntl(Register dst, Register src) {
2426 assert(VM_Version::supports_popcnt(), "must support");
2427 emit_int8((unsigned char)0xF3);
2428 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2429 emit_int8(0x0F);
2430 emit_int8((unsigned char)0xB8);
2431 emit_int8((unsigned char)(0xC0 | encode));
2432 }
2434 void Assembler::popf() {
2435 emit_int8((unsigned char)0x9D);
2436 }
2438 #ifndef _LP64 // no 32bit push/pop on amd64
2439 void Assembler::popl(Address dst) {
2440 // NOTE: this will adjust stack by 8byte on 64bits
2441 InstructionMark im(this);
2442 prefix(dst);
2443 emit_int8((unsigned char)0x8F);
2444 emit_operand(rax, dst);
2445 }
2446 #endif
2448 void Assembler::prefetch_prefix(Address src) {
2449 prefix(src);
2450 emit_int8(0x0F);
2451 }
2453 void Assembler::prefetchnta(Address src) {
2454 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2455 InstructionMark im(this);
2456 prefetch_prefix(src);
2457 emit_int8(0x18);
2458 emit_operand(rax, src); // 0, src
2459 }
2461 void Assembler::prefetchr(Address src) {
2462 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2463 InstructionMark im(this);
2464 prefetch_prefix(src);
2465 emit_int8(0x0D);
2466 emit_operand(rax, src); // 0, src
2467 }
2469 void Assembler::prefetcht0(Address src) {
2470 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2471 InstructionMark im(this);
2472 prefetch_prefix(src);
2473 emit_int8(0x18);
2474 emit_operand(rcx, src); // 1, src
2475 }
2477 void Assembler::prefetcht1(Address src) {
2478 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2479 InstructionMark im(this);
2480 prefetch_prefix(src);
2481 emit_int8(0x18);
2482 emit_operand(rdx, src); // 2, src
2483 }
2485 void Assembler::prefetcht2(Address src) {
2486 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2487 InstructionMark im(this);
2488 prefetch_prefix(src);
2489 emit_int8(0x18);
2490 emit_operand(rbx, src); // 3, src
2491 }
2493 void Assembler::prefetchw(Address src) {
2494 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2495 InstructionMark im(this);
2496 prefetch_prefix(src);
2497 emit_int8(0x0D);
2498 emit_operand(rcx, src); // 1, src
2499 }
2501 void Assembler::prefix(Prefix p) {
2502 emit_int8(p);
2503 }
2505 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2506 assert(VM_Version::supports_ssse3(), "");
2507 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2508 emit_int8(0x00);
2509 emit_int8((unsigned char)(0xC0 | encode));
2510 }
2512 void Assembler::pshufb(XMMRegister dst, Address src) {
2513 assert(VM_Version::supports_ssse3(), "");
2514 InstructionMark im(this);
2515 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2516 emit_int8(0x00);
2517 emit_operand(dst, src);
2518 }
2520 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2521 assert(isByte(mode), "invalid value");
2522 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2523 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2524 emit_int8(mode & 0xFF);
2526 }
2528 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2529 assert(isByte(mode), "invalid value");
2530 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2531 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2532 InstructionMark im(this);
2533 simd_prefix(dst, src, VEX_SIMD_66);
2534 emit_int8(0x70);
2535 emit_operand(dst, src);
2536 emit_int8(mode & 0xFF);
2537 }
2539 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2540 assert(isByte(mode), "invalid value");
2541 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2542 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2543 emit_int8(mode & 0xFF);
2544 }
2546 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2547 assert(isByte(mode), "invalid value");
2548 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2549 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2550 InstructionMark im(this);
2551 simd_prefix(dst, src, VEX_SIMD_F2);
2552 emit_int8(0x70);
2553 emit_operand(dst, src);
2554 emit_int8(mode & 0xFF);
2555 }
2557 void Assembler::psrldq(XMMRegister dst, int shift) {
2558 // Shift 128 bit value in xmm register by number of bytes.
2559 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2560 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2561 emit_int8(0x73);
2562 emit_int8((unsigned char)(0xC0 | encode));
2563 emit_int8(shift);
2564 }
2566 void Assembler::ptest(XMMRegister dst, Address src) {
2567 assert(VM_Version::supports_sse4_1(), "");
2568 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2569 InstructionMark im(this);
2570 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2571 emit_int8(0x17);
2572 emit_operand(dst, src);
2573 }
2575 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2576 assert(VM_Version::supports_sse4_1(), "");
2577 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2578 emit_int8(0x17);
2579 emit_int8((unsigned char)(0xC0 | encode));
2580 }
2582 void Assembler::vptest(XMMRegister dst, Address src) {
2583 assert(VM_Version::supports_avx(), "");
2584 InstructionMark im(this);
2585 bool vector256 = true;
2586 assert(dst != xnoreg, "sanity");
2587 int dst_enc = dst->encoding();
2588 // swap src<->dst for encoding
2589 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2590 emit_int8(0x17);
2591 emit_operand(dst, src);
2592 }
2594 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2595 assert(VM_Version::supports_avx(), "");
2596 bool vector256 = true;
2597 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2598 emit_int8(0x17);
2599 emit_int8((unsigned char)(0xC0 | encode));
2600 }
2602 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2603 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2604 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2605 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2606 }
2608 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2610 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2611 }
2613 void Assembler::punpckldq(XMMRegister dst, Address src) {
2614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2615 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2616 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2617 }
2619 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2621 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2622 }
2624 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2625 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2626 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2627 }
2629 void Assembler::push(int32_t imm32) {
2630 // in 64bits we push 64bits onto the stack but only
2631 // take a 32bit immediate
2632 emit_int8(0x68);
2633 emit_int32(imm32);
2634 }
2636 void Assembler::push(Register src) {
2637 int encode = prefix_and_encode(src->encoding());
2639 emit_int8(0x50 | encode);
2640 }
2642 void Assembler::pushf() {
2643 emit_int8((unsigned char)0x9C);
2644 }
2646 #ifndef _LP64 // no 32bit push/pop on amd64
2647 void Assembler::pushl(Address src) {
2648 // Note this will push 64bit on 64bit
2649 InstructionMark im(this);
2650 prefix(src);
2651 emit_int8((unsigned char)0xFF);
2652 emit_operand(rsi, src);
2653 }
2654 #endif
2656 void Assembler::rcll(Register dst, int imm8) {
2657 assert(isShiftCount(imm8), "illegal shift count");
2658 int encode = prefix_and_encode(dst->encoding());
2659 if (imm8 == 1) {
2660 emit_int8((unsigned char)0xD1);
2661 emit_int8((unsigned char)(0xD0 | encode));
2662 } else {
2663 emit_int8((unsigned char)0xC1);
2664 emit_int8((unsigned char)0xD0 | encode);
2665 emit_int8(imm8);
2666 }
2667 }
2669 // copies data from [esi] to [edi] using rcx pointer sized words
2670 // generic
2671 void Assembler::rep_mov() {
2672 emit_int8((unsigned char)0xF3);
2673 // MOVSQ
2674 LP64_ONLY(prefix(REX_W));
2675 emit_int8((unsigned char)0xA5);
2676 }
2678 // sets rcx bytes with rax, value at [edi]
2679 void Assembler::rep_stosb() {
2680 emit_int8((unsigned char)0xF3); // REP
2681 LP64_ONLY(prefix(REX_W));
2682 emit_int8((unsigned char)0xAA); // STOSB
2683 }
2685 // sets rcx pointer sized words with rax, value at [edi]
2686 // generic
2687 void Assembler::rep_stos() {
2688 emit_int8((unsigned char)0xF3); // REP
2689 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2690 emit_int8((unsigned char)0xAB);
2691 }
2693 // scans rcx pointer sized words at [edi] for occurance of rax,
2694 // generic
2695 void Assembler::repne_scan() { // repne_scan
2696 emit_int8((unsigned char)0xF2);
2697 // SCASQ
2698 LP64_ONLY(prefix(REX_W));
2699 emit_int8((unsigned char)0xAF);
2700 }
2702 #ifdef _LP64
2703 // scans rcx 4 byte words at [edi] for occurance of rax,
2704 // generic
2705 void Assembler::repne_scanl() { // repne_scan
2706 emit_int8((unsigned char)0xF2);
2707 // SCASL
2708 emit_int8((unsigned char)0xAF);
2709 }
2710 #endif
2712 void Assembler::ret(int imm16) {
2713 if (imm16 == 0) {
2714 emit_int8((unsigned char)0xC3);
2715 } else {
2716 emit_int8((unsigned char)0xC2);
2717 emit_int16(imm16);
2718 }
2719 }
2721 void Assembler::sahf() {
2722 #ifdef _LP64
2723 // Not supported in 64bit mode
2724 ShouldNotReachHere();
2725 #endif
2726 emit_int8((unsigned char)0x9E);
2727 }
2729 void Assembler::sarl(Register dst, int imm8) {
2730 int encode = prefix_and_encode(dst->encoding());
2731 assert(isShiftCount(imm8), "illegal shift count");
2732 if (imm8 == 1) {
2733 emit_int8((unsigned char)0xD1);
2734 emit_int8((unsigned char)(0xF8 | encode));
2735 } else {
2736 emit_int8((unsigned char)0xC1);
2737 emit_int8((unsigned char)(0xF8 | encode));
2738 emit_int8(imm8);
2739 }
2740 }
2742 void Assembler::sarl(Register dst) {
2743 int encode = prefix_and_encode(dst->encoding());
2744 emit_int8((unsigned char)0xD3);
2745 emit_int8((unsigned char)(0xF8 | encode));
2746 }
2748 void Assembler::sbbl(Address dst, int32_t imm32) {
2749 InstructionMark im(this);
2750 prefix(dst);
2751 emit_arith_operand(0x81, rbx, dst, imm32);
2752 }
2754 void Assembler::sbbl(Register dst, int32_t imm32) {
2755 prefix(dst);
2756 emit_arith(0x81, 0xD8, dst, imm32);
2757 }
2760 void Assembler::sbbl(Register dst, Address src) {
2761 InstructionMark im(this);
2762 prefix(src, dst);
2763 emit_int8(0x1B);
2764 emit_operand(dst, src);
2765 }
2767 void Assembler::sbbl(Register dst, Register src) {
2768 (void) prefix_and_encode(dst->encoding(), src->encoding());
2769 emit_arith(0x1B, 0xC0, dst, src);
2770 }
2772 void Assembler::setb(Condition cc, Register dst) {
2773 assert(0 <= cc && cc < 16, "illegal cc");
2774 int encode = prefix_and_encode(dst->encoding(), true);
2775 emit_int8(0x0F);
2776 emit_int8((unsigned char)0x90 | cc);
2777 emit_int8((unsigned char)(0xC0 | encode));
2778 }
2780 void Assembler::shll(Register dst, int imm8) {
2781 assert(isShiftCount(imm8), "illegal shift count");
2782 int encode = prefix_and_encode(dst->encoding());
2783 if (imm8 == 1 ) {
2784 emit_int8((unsigned char)0xD1);
2785 emit_int8((unsigned char)(0xE0 | encode));
2786 } else {
2787 emit_int8((unsigned char)0xC1);
2788 emit_int8((unsigned char)(0xE0 | encode));
2789 emit_int8(imm8);
2790 }
2791 }
2793 void Assembler::shll(Register dst) {
2794 int encode = prefix_and_encode(dst->encoding());
2795 emit_int8((unsigned char)0xD3);
2796 emit_int8((unsigned char)(0xE0 | encode));
2797 }
2799 void Assembler::shrl(Register dst, int imm8) {
2800 assert(isShiftCount(imm8), "illegal shift count");
2801 int encode = prefix_and_encode(dst->encoding());
2802 emit_int8((unsigned char)0xC1);
2803 emit_int8((unsigned char)(0xE8 | encode));
2804 emit_int8(imm8);
2805 }
2807 void Assembler::shrl(Register dst) {
2808 int encode = prefix_and_encode(dst->encoding());
2809 emit_int8((unsigned char)0xD3);
2810 emit_int8((unsigned char)(0xE8 | encode));
2811 }
2813 // copies a single word from [esi] to [edi]
2814 void Assembler::smovl() {
2815 emit_int8((unsigned char)0xA5);
2816 }
2818 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2820 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2821 }
2823 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2825 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2826 }
2828 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2830 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2831 }
2833 void Assembler::std() {
2834 emit_int8((unsigned char)0xFD);
2835 }
2837 void Assembler::sqrtss(XMMRegister dst, Address src) {
2838 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2839 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2840 }
2842 void Assembler::stmxcsr( Address dst) {
2843 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2844 InstructionMark im(this);
2845 prefix(dst);
2846 emit_int8(0x0F);
2847 emit_int8((unsigned char)0xAE);
2848 emit_operand(as_Register(3), dst);
2849 }
2851 void Assembler::subl(Address dst, int32_t imm32) {
2852 InstructionMark im(this);
2853 prefix(dst);
2854 emit_arith_operand(0x81, rbp, dst, imm32);
2855 }
2857 void Assembler::subl(Address dst, Register src) {
2858 InstructionMark im(this);
2859 prefix(dst, src);
2860 emit_int8(0x29);
2861 emit_operand(src, dst);
2862 }
2864 void Assembler::subl(Register dst, int32_t imm32) {
2865 prefix(dst);
2866 emit_arith(0x81, 0xE8, dst, imm32);
2867 }
2869 // Force generation of a 4 byte immediate value even if it fits into 8bit
2870 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2871 prefix(dst);
2872 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2873 }
2875 void Assembler::subl(Register dst, Address src) {
2876 InstructionMark im(this);
2877 prefix(src, dst);
2878 emit_int8(0x2B);
2879 emit_operand(dst, src);
2880 }
2882 void Assembler::subl(Register dst, Register src) {
2883 (void) prefix_and_encode(dst->encoding(), src->encoding());
2884 emit_arith(0x2B, 0xC0, dst, src);
2885 }
2887 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2888 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2889 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2890 }
2892 void Assembler::subsd(XMMRegister dst, Address src) {
2893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2894 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2895 }
2897 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2898 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2899 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2900 }
2902 void Assembler::subss(XMMRegister dst, Address src) {
2903 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2904 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2905 }
2907 void Assembler::testb(Register dst, int imm8) {
2908 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2909 (void) prefix_and_encode(dst->encoding(), true);
2910 emit_arith_b(0xF6, 0xC0, dst, imm8);
2911 }
2913 void Assembler::testl(Register dst, int32_t imm32) {
2914 // not using emit_arith because test
2915 // doesn't support sign-extension of
2916 // 8bit operands
2917 int encode = dst->encoding();
2918 if (encode == 0) {
2919 emit_int8((unsigned char)0xA9);
2920 } else {
2921 encode = prefix_and_encode(encode);
2922 emit_int8((unsigned char)0xF7);
2923 emit_int8((unsigned char)(0xC0 | encode));
2924 }
2925 emit_int32(imm32);
2926 }
2928 void Assembler::testl(Register dst, Register src) {
2929 (void) prefix_and_encode(dst->encoding(), src->encoding());
2930 emit_arith(0x85, 0xC0, dst, src);
2931 }
2933 void Assembler::testl(Register dst, Address src) {
2934 InstructionMark im(this);
2935 prefix(src, dst);
2936 emit_int8((unsigned char)0x85);
2937 emit_operand(dst, src);
2938 }
2940 void Assembler::tzcntl(Register dst, Register src) {
2941 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2942 emit_int8((unsigned char)0xF3);
2943 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2944 emit_int8(0x0F);
2945 emit_int8((unsigned char)0xBC);
2946 emit_int8((unsigned char)0xC0 | encode);
2947 }
2949 void Assembler::tzcntq(Register dst, Register src) {
2950 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2951 emit_int8((unsigned char)0xF3);
2952 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2953 emit_int8(0x0F);
2954 emit_int8((unsigned char)0xBC);
2955 emit_int8((unsigned char)(0xC0 | encode));
2956 }
2958 void Assembler::ucomisd(XMMRegister dst, Address src) {
2959 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2960 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2961 }
2963 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2964 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2965 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2966 }
2968 void Assembler::ucomiss(XMMRegister dst, Address src) {
2969 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2970 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2971 }
2973 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2974 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2975 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2976 }
2979 void Assembler::xaddl(Address dst, Register src) {
2980 InstructionMark im(this);
2981 prefix(dst, src);
2982 emit_int8(0x0F);
2983 emit_int8((unsigned char)0xC1);
2984 emit_operand(src, dst);
2985 }
2987 void Assembler::xchgl(Register dst, Address src) { // xchg
2988 InstructionMark im(this);
2989 prefix(src, dst);
2990 emit_int8((unsigned char)0x87);
2991 emit_operand(dst, src);
2992 }
2994 void Assembler::xchgl(Register dst, Register src) {
2995 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2996 emit_int8((unsigned char)0x87);
2997 emit_int8((unsigned char)(0xC0 | encode));
2998 }
3000 void Assembler::xgetbv() {
3001 emit_int8(0x0F);
3002 emit_int8(0x01);
3003 emit_int8((unsigned char)0xD0);
3004 }
3006 void Assembler::xorl(Register dst, int32_t imm32) {
3007 prefix(dst);
3008 emit_arith(0x81, 0xF0, dst, imm32);
3009 }
3011 void Assembler::xorl(Register dst, Address src) {
3012 InstructionMark im(this);
3013 prefix(src, dst);
3014 emit_int8(0x33);
3015 emit_operand(dst, src);
3016 }
3018 void Assembler::xorl(Register dst, Register src) {
3019 (void) prefix_and_encode(dst->encoding(), src->encoding());
3020 emit_arith(0x33, 0xC0, dst, src);
3021 }
3024 // AVX 3-operands scalar float-point arithmetic instructions
3026 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3027 assert(VM_Version::supports_avx(), "");
3028 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3029 }
3031 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3032 assert(VM_Version::supports_avx(), "");
3033 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3034 }
3036 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3037 assert(VM_Version::supports_avx(), "");
3038 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3039 }
3041 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3042 assert(VM_Version::supports_avx(), "");
3043 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3044 }
3046 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3047 assert(VM_Version::supports_avx(), "");
3048 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3049 }
3051 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3052 assert(VM_Version::supports_avx(), "");
3053 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3054 }
3056 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3057 assert(VM_Version::supports_avx(), "");
3058 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3059 }
3061 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3062 assert(VM_Version::supports_avx(), "");
3063 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3064 }
3066 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3067 assert(VM_Version::supports_avx(), "");
3068 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3069 }
3071 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3072 assert(VM_Version::supports_avx(), "");
3073 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3074 }
3076 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3077 assert(VM_Version::supports_avx(), "");
3078 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3079 }
3081 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3082 assert(VM_Version::supports_avx(), "");
3083 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3084 }
3086 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3087 assert(VM_Version::supports_avx(), "");
3088 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3089 }
3091 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3092 assert(VM_Version::supports_avx(), "");
3093 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3094 }
3096 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3097 assert(VM_Version::supports_avx(), "");
3098 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3099 }
3101 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3102 assert(VM_Version::supports_avx(), "");
3103 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3104 }
3106 //====================VECTOR ARITHMETIC=====================================
3108 // Float-point vector arithmetic
3110 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3111 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3112 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3113 }
3115 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3116 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3117 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3118 }
3120 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3121 assert(VM_Version::supports_avx(), "");
3122 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3123 }
3125 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3126 assert(VM_Version::supports_avx(), "");
3127 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3128 }
3130 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3131 assert(VM_Version::supports_avx(), "");
3132 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3133 }
3135 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3136 assert(VM_Version::supports_avx(), "");
3137 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3138 }
3140 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3141 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3142 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3143 }
3145 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3146 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3147 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3148 }
3150 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3151 assert(VM_Version::supports_avx(), "");
3152 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3153 }
3155 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3156 assert(VM_Version::supports_avx(), "");
3157 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3158 }
3160 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3161 assert(VM_Version::supports_avx(), "");
3162 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3163 }
3165 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3166 assert(VM_Version::supports_avx(), "");
3167 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3168 }
3170 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3171 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3172 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3173 }
3175 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3176 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3177 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3178 }
3180 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3181 assert(VM_Version::supports_avx(), "");
3182 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3183 }
3185 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3186 assert(VM_Version::supports_avx(), "");
3187 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3188 }
3190 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3191 assert(VM_Version::supports_avx(), "");
3192 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3193 }
3195 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3196 assert(VM_Version::supports_avx(), "");
3197 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3198 }
3200 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3202 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3203 }
3205 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3206 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3207 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3208 }
3210 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3211 assert(VM_Version::supports_avx(), "");
3212 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3213 }
3215 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3216 assert(VM_Version::supports_avx(), "");
3217 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3218 }
3220 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3221 assert(VM_Version::supports_avx(), "");
3222 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3223 }
3225 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3226 assert(VM_Version::supports_avx(), "");
3227 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3228 }
3230 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3231 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3232 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3233 }
3235 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3236 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3237 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3238 }
3240 void Assembler::andps(XMMRegister dst, Address src) {
3241 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3242 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3243 }
3245 void Assembler::andpd(XMMRegister dst, Address src) {
3246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3247 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3248 }
3250 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3251 assert(VM_Version::supports_avx(), "");
3252 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3253 }
3255 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3256 assert(VM_Version::supports_avx(), "");
3257 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3258 }
3260 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3261 assert(VM_Version::supports_avx(), "");
3262 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3263 }
3265 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3266 assert(VM_Version::supports_avx(), "");
3267 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3268 }
3270 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3272 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3273 }
3275 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3276 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3277 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3278 }
3280 void Assembler::xorpd(XMMRegister dst, Address src) {
3281 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3282 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3283 }
3285 void Assembler::xorps(XMMRegister dst, Address src) {
3286 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3287 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3288 }
3290 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3291 assert(VM_Version::supports_avx(), "");
3292 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3293 }
3295 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3296 assert(VM_Version::supports_avx(), "");
3297 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3298 }
3300 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3301 assert(VM_Version::supports_avx(), "");
3302 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3303 }
3305 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3306 assert(VM_Version::supports_avx(), "");
3307 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3308 }
3311 // Integer vector arithmetic
3312 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3313 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3314 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3315 }
3317 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3318 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3319 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3320 }
3322 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3323 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3324 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3325 }
3327 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3329 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3330 }
3332 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3333 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3334 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3335 }
3337 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3338 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3339 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3340 }
3342 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3343 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3344 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3345 }
3347 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3348 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3349 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3350 }
3352 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3353 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3354 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3355 }
3357 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3358 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3359 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3360 }
3362 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3363 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3364 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3365 }
3367 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3368 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3369 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3370 }
3372 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3374 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3375 }
3377 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3379 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3380 }
3382 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3384 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3385 }
3387 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3389 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3390 }
3392 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3393 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3394 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3395 }
3397 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3398 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3399 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3400 }
3402 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3403 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3404 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3405 }
3407 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3408 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3409 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3410 }
3412 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3413 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3414 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3415 }
3417 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3418 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3419 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3420 }
3422 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3423 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3424 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3425 }
3427 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3428 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3429 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3430 }
3432 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3433 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3434 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3435 }
3437 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3438 assert(VM_Version::supports_sse4_1(), "");
3439 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3440 emit_int8(0x40);
3441 emit_int8((unsigned char)(0xC0 | encode));
3442 }
3444 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3445 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3446 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3447 }
3449 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3450 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3451 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3452 emit_int8(0x40);
3453 emit_int8((unsigned char)(0xC0 | encode));
3454 }
3456 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3457 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3458 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3459 }
3461 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3462 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3463 InstructionMark im(this);
3464 int dst_enc = dst->encoding();
3465 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3466 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3467 emit_int8(0x40);
3468 emit_operand(dst, src);
3469 }
3471 // Shift packed integers left by specified number of bits.
3472 void Assembler::psllw(XMMRegister dst, int shift) {
3473 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3474 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3475 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3476 emit_int8(0x71);
3477 emit_int8((unsigned char)(0xC0 | encode));
3478 emit_int8(shift & 0xFF);
3479 }
3481 void Assembler::pslld(XMMRegister dst, int shift) {
3482 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3483 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3484 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3485 emit_int8(0x72);
3486 emit_int8((unsigned char)(0xC0 | encode));
3487 emit_int8(shift & 0xFF);
3488 }
3490 void Assembler::psllq(XMMRegister dst, int shift) {
3491 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3492 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3493 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3494 emit_int8(0x73);
3495 emit_int8((unsigned char)(0xC0 | encode));
3496 emit_int8(shift & 0xFF);
3497 }
3499 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3500 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3501 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3502 }
3504 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3505 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3506 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3507 }
3509 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3510 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3511 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3512 }
3514 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3515 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3516 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3517 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3518 emit_int8(shift & 0xFF);
3519 }
3521 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3522 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3523 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3524 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3525 emit_int8(shift & 0xFF);
3526 }
3528 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3529 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3530 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3531 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3532 emit_int8(shift & 0xFF);
3533 }
3535 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3536 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3537 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3538 }
3540 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3541 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3542 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3543 }
3545 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3546 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3547 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3548 }
3550 // Shift packed integers logically right by specified number of bits.
3551 void Assembler::psrlw(XMMRegister dst, int shift) {
3552 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3553 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3554 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3555 emit_int8(0x71);
3556 emit_int8((unsigned char)(0xC0 | encode));
3557 emit_int8(shift & 0xFF);
3558 }
3560 void Assembler::psrld(XMMRegister dst, int shift) {
3561 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3562 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3563 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3564 emit_int8(0x72);
3565 emit_int8((unsigned char)(0xC0 | encode));
3566 emit_int8(shift & 0xFF);
3567 }
3569 void Assembler::psrlq(XMMRegister dst, int shift) {
3570 // Do not confuse it with psrldq SSE2 instruction which
3571 // shifts 128 bit value in xmm register by number of bytes.
3572 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3573 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3574 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3575 emit_int8(0x73);
3576 emit_int8((unsigned char)(0xC0 | encode));
3577 emit_int8(shift & 0xFF);
3578 }
3580 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3581 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3582 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3583 }
3585 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3587 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3588 }
3590 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3591 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3592 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3593 }
3595 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3596 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3597 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3598 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3599 emit_int8(shift & 0xFF);
3600 }
3602 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3603 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3604 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3605 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3606 emit_int8(shift & 0xFF);
3607 }
3609 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3610 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3611 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3612 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3613 emit_int8(shift & 0xFF);
3614 }
3616 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3617 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3618 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3619 }
3621 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3622 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3623 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3624 }
3626 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3627 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3628 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3629 }
3631 // Shift packed integers arithmetically right by specified number of bits.
3632 void Assembler::psraw(XMMRegister dst, int shift) {
3633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3634 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3635 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3636 emit_int8(0x71);
3637 emit_int8((unsigned char)(0xC0 | encode));
3638 emit_int8(shift & 0xFF);
3639 }
3641 void Assembler::psrad(XMMRegister dst, int shift) {
3642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3643 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3644 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3645 emit_int8(0x72);
3646 emit_int8((unsigned char)(0xC0 | encode));
3647 emit_int8(shift & 0xFF);
3648 }
3650 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3651 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3652 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3653 }
3655 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3656 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3657 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3658 }
3660 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3661 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3662 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3663 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3664 emit_int8(shift & 0xFF);
3665 }
3667 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3668 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3669 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3670 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3671 emit_int8(shift & 0xFF);
3672 }
3674 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3675 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3676 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3677 }
3679 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3680 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3681 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3682 }
3685 // AND packed integers
3686 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3688 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3689 }
3691 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3692 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3693 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3694 }
3696 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3697 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3698 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3699 }
3701 void Assembler::por(XMMRegister dst, XMMRegister src) {
3702 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3703 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3704 }
3706 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3707 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3708 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3709 }
3711 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3712 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3713 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3714 }
3716 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3717 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3718 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3719 }
3721 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3722 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3723 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3724 }
3726 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3727 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3728 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3729 }
3732 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3733 assert(VM_Version::supports_avx(), "");
3734 bool vector256 = true;
3735 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3736 emit_int8(0x18);
3737 emit_int8((unsigned char)(0xC0 | encode));
3738 // 0x00 - insert into lower 128 bits
3739 // 0x01 - insert into upper 128 bits
3740 emit_int8(0x01);
3741 }
3743 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3744 assert(VM_Version::supports_avx(), "");
3745 InstructionMark im(this);
3746 bool vector256 = true;
3747 assert(dst != xnoreg, "sanity");
3748 int dst_enc = dst->encoding();
3749 // swap src<->dst for encoding
3750 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3751 emit_int8(0x18);
3752 emit_operand(dst, src);
3753 // 0x01 - insert into upper 128 bits
3754 emit_int8(0x01);
3755 }
3757 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3758 assert(VM_Version::supports_avx(), "");
3759 InstructionMark im(this);
3760 bool vector256 = true;
3761 assert(src != xnoreg, "sanity");
3762 int src_enc = src->encoding();
3763 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3764 emit_int8(0x19);
3765 emit_operand(src, dst);
3766 // 0x01 - extract from upper 128 bits
3767 emit_int8(0x01);
3768 }
3770 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3771 assert(VM_Version::supports_avx2(), "");
3772 bool vector256 = true;
3773 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3774 emit_int8(0x38);
3775 emit_int8((unsigned char)(0xC0 | encode));
3776 // 0x00 - insert into lower 128 bits
3777 // 0x01 - insert into upper 128 bits
3778 emit_int8(0x01);
3779 }
3781 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3782 assert(VM_Version::supports_avx2(), "");
3783 InstructionMark im(this);
3784 bool vector256 = true;
3785 assert(dst != xnoreg, "sanity");
3786 int dst_enc = dst->encoding();
3787 // swap src<->dst for encoding
3788 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3789 emit_int8(0x38);
3790 emit_operand(dst, src);
3791 // 0x01 - insert into upper 128 bits
3792 emit_int8(0x01);
3793 }
3795 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3796 assert(VM_Version::supports_avx2(), "");
3797 InstructionMark im(this);
3798 bool vector256 = true;
3799 assert(src != xnoreg, "sanity");
3800 int src_enc = src->encoding();
3801 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3802 emit_int8(0x39);
3803 emit_operand(src, dst);
3804 // 0x01 - extract from upper 128 bits
3805 emit_int8(0x01);
3806 }
3808 // duplicate 4-bytes integer data from src into 8 locations in dest
3809 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3810 assert(VM_Version::supports_avx2(), "");
3811 bool vector256 = true;
3812 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3813 emit_int8(0x58);
3814 emit_int8((unsigned char)(0xC0 | encode));
3815 }
3817 // Carry-Less Multiplication Quadword
3818 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3819 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3820 bool vector256 = false;
3821 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3822 emit_int8(0x44);
3823 emit_int8((unsigned char)(0xC0 | encode));
3824 emit_int8((unsigned char)mask);
3825 }
3827 void Assembler::vzeroupper() {
3828 assert(VM_Version::supports_avx(), "");
3829 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3830 emit_int8(0x77);
3831 }
3834 #ifndef _LP64
3835 // 32bit only pieces of the assembler
3837 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3838 // NO PREFIX AS NEVER 64BIT
3839 InstructionMark im(this);
3840 emit_int8((unsigned char)0x81);
3841 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3842 emit_data(imm32, rspec, 0);
3843 }
3845 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3846 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3847 InstructionMark im(this);
3848 emit_int8((unsigned char)0x81);
3849 emit_operand(rdi, src1);
3850 emit_data(imm32, rspec, 0);
3851 }
3853 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3854 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3855 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3856 void Assembler::cmpxchg8(Address adr) {
3857 InstructionMark im(this);
3858 emit_int8(0x0F);
3859 emit_int8((unsigned char)0xC7);
3860 emit_operand(rcx, adr);
3861 }
3863 void Assembler::decl(Register dst) {
3864 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3865 emit_int8(0x48 | dst->encoding());
3866 }
3868 #endif // _LP64
3870 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3872 void Assembler::fabs() {
3873 emit_int8((unsigned char)0xD9);
3874 emit_int8((unsigned char)0xE1);
3875 }
3877 void Assembler::fadd(int i) {
3878 emit_farith(0xD8, 0xC0, i);
3879 }
3881 void Assembler::fadd_d(Address src) {
3882 InstructionMark im(this);
3883 emit_int8((unsigned char)0xDC);
3884 emit_operand32(rax, src);
3885 }
3887 void Assembler::fadd_s(Address src) {
3888 InstructionMark im(this);
3889 emit_int8((unsigned char)0xD8);
3890 emit_operand32(rax, src);
3891 }
3893 void Assembler::fadda(int i) {
3894 emit_farith(0xDC, 0xC0, i);
3895 }
3897 void Assembler::faddp(int i) {
3898 emit_farith(0xDE, 0xC0, i);
3899 }
3901 void Assembler::fchs() {
3902 emit_int8((unsigned char)0xD9);
3903 emit_int8((unsigned char)0xE0);
3904 }
3906 void Assembler::fcom(int i) {
3907 emit_farith(0xD8, 0xD0, i);
3908 }
3910 void Assembler::fcomp(int i) {
3911 emit_farith(0xD8, 0xD8, i);
3912 }
3914 void Assembler::fcomp_d(Address src) {
3915 InstructionMark im(this);
3916 emit_int8((unsigned char)0xDC);
3917 emit_operand32(rbx, src);
3918 }
3920 void Assembler::fcomp_s(Address src) {
3921 InstructionMark im(this);
3922 emit_int8((unsigned char)0xD8);
3923 emit_operand32(rbx, src);
3924 }
3926 void Assembler::fcompp() {
3927 emit_int8((unsigned char)0xDE);
3928 emit_int8((unsigned char)0xD9);
3929 }
3931 void Assembler::fcos() {
3932 emit_int8((unsigned char)0xD9);
3933 emit_int8((unsigned char)0xFF);
3934 }
3936 void Assembler::fdecstp() {
3937 emit_int8((unsigned char)0xD9);
3938 emit_int8((unsigned char)0xF6);
3939 }
3941 void Assembler::fdiv(int i) {
3942 emit_farith(0xD8, 0xF0, i);
3943 }
3945 void Assembler::fdiv_d(Address src) {
3946 InstructionMark im(this);
3947 emit_int8((unsigned char)0xDC);
3948 emit_operand32(rsi, src);
3949 }
3951 void Assembler::fdiv_s(Address src) {
3952 InstructionMark im(this);
3953 emit_int8((unsigned char)0xD8);
3954 emit_operand32(rsi, src);
3955 }
3957 void Assembler::fdiva(int i) {
3958 emit_farith(0xDC, 0xF8, i);
3959 }
3961 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3962 // is erroneous for some of the floating-point instructions below.
3964 void Assembler::fdivp(int i) {
3965 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3966 }
3968 void Assembler::fdivr(int i) {
3969 emit_farith(0xD8, 0xF8, i);
3970 }
3972 void Assembler::fdivr_d(Address src) {
3973 InstructionMark im(this);
3974 emit_int8((unsigned char)0xDC);
3975 emit_operand32(rdi, src);
3976 }
3978 void Assembler::fdivr_s(Address src) {
3979 InstructionMark im(this);
3980 emit_int8((unsigned char)0xD8);
3981 emit_operand32(rdi, src);
3982 }
3984 void Assembler::fdivra(int i) {
3985 emit_farith(0xDC, 0xF0, i);
3986 }
3988 void Assembler::fdivrp(int i) {
3989 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3990 }
3992 void Assembler::ffree(int i) {
3993 emit_farith(0xDD, 0xC0, i);
3994 }
3996 void Assembler::fild_d(Address adr) {
3997 InstructionMark im(this);
3998 emit_int8((unsigned char)0xDF);
3999 emit_operand32(rbp, adr);
4000 }
4002 void Assembler::fild_s(Address adr) {
4003 InstructionMark im(this);
4004 emit_int8((unsigned char)0xDB);
4005 emit_operand32(rax, adr);
4006 }
4008 void Assembler::fincstp() {
4009 emit_int8((unsigned char)0xD9);
4010 emit_int8((unsigned char)0xF7);
4011 }
4013 void Assembler::finit() {
4014 emit_int8((unsigned char)0x9B);
4015 emit_int8((unsigned char)0xDB);
4016 emit_int8((unsigned char)0xE3);
4017 }
4019 void Assembler::fist_s(Address adr) {
4020 InstructionMark im(this);
4021 emit_int8((unsigned char)0xDB);
4022 emit_operand32(rdx, adr);
4023 }
4025 void Assembler::fistp_d(Address adr) {
4026 InstructionMark im(this);
4027 emit_int8((unsigned char)0xDF);
4028 emit_operand32(rdi, adr);
4029 }
4031 void Assembler::fistp_s(Address adr) {
4032 InstructionMark im(this);
4033 emit_int8((unsigned char)0xDB);
4034 emit_operand32(rbx, adr);
4035 }
4037 void Assembler::fld1() {
4038 emit_int8((unsigned char)0xD9);
4039 emit_int8((unsigned char)0xE8);
4040 }
4042 void Assembler::fld_d(Address adr) {
4043 InstructionMark im(this);
4044 emit_int8((unsigned char)0xDD);
4045 emit_operand32(rax, adr);
4046 }
4048 void Assembler::fld_s(Address adr) {
4049 InstructionMark im(this);
4050 emit_int8((unsigned char)0xD9);
4051 emit_operand32(rax, adr);
4052 }
4055 void Assembler::fld_s(int index) {
4056 emit_farith(0xD9, 0xC0, index);
4057 }
4059 void Assembler::fld_x(Address adr) {
4060 InstructionMark im(this);
4061 emit_int8((unsigned char)0xDB);
4062 emit_operand32(rbp, adr);
4063 }
4065 void Assembler::fldcw(Address src) {
4066 InstructionMark im(this);
4067 emit_int8((unsigned char)0xD9);
4068 emit_operand32(rbp, src);
4069 }
4071 void Assembler::fldenv(Address src) {
4072 InstructionMark im(this);
4073 emit_int8((unsigned char)0xD9);
4074 emit_operand32(rsp, src);
4075 }
4077 void Assembler::fldlg2() {
4078 emit_int8((unsigned char)0xD9);
4079 emit_int8((unsigned char)0xEC);
4080 }
4082 void Assembler::fldln2() {
4083 emit_int8((unsigned char)0xD9);
4084 emit_int8((unsigned char)0xED);
4085 }
4087 void Assembler::fldz() {
4088 emit_int8((unsigned char)0xD9);
4089 emit_int8((unsigned char)0xEE);
4090 }
4092 void Assembler::flog() {
4093 fldln2();
4094 fxch();
4095 fyl2x();
4096 }
4098 void Assembler::flog10() {
4099 fldlg2();
4100 fxch();
4101 fyl2x();
4102 }
4104 void Assembler::fmul(int i) {
4105 emit_farith(0xD8, 0xC8, i);
4106 }
4108 void Assembler::fmul_d(Address src) {
4109 InstructionMark im(this);
4110 emit_int8((unsigned char)0xDC);
4111 emit_operand32(rcx, src);
4112 }
4114 void Assembler::fmul_s(Address src) {
4115 InstructionMark im(this);
4116 emit_int8((unsigned char)0xD8);
4117 emit_operand32(rcx, src);
4118 }
4120 void Assembler::fmula(int i) {
4121 emit_farith(0xDC, 0xC8, i);
4122 }
4124 void Assembler::fmulp(int i) {
4125 emit_farith(0xDE, 0xC8, i);
4126 }
4128 void Assembler::fnsave(Address dst) {
4129 InstructionMark im(this);
4130 emit_int8((unsigned char)0xDD);
4131 emit_operand32(rsi, dst);
4132 }
4134 void Assembler::fnstcw(Address src) {
4135 InstructionMark im(this);
4136 emit_int8((unsigned char)0x9B);
4137 emit_int8((unsigned char)0xD9);
4138 emit_operand32(rdi, src);
4139 }
4141 void Assembler::fnstsw_ax() {
4142 emit_int8((unsigned char)0xDF);
4143 emit_int8((unsigned char)0xE0);
4144 }
4146 void Assembler::fprem() {
4147 emit_int8((unsigned char)0xD9);
4148 emit_int8((unsigned char)0xF8);
4149 }
4151 void Assembler::fprem1() {
4152 emit_int8((unsigned char)0xD9);
4153 emit_int8((unsigned char)0xF5);
4154 }
4156 void Assembler::frstor(Address src) {
4157 InstructionMark im(this);
4158 emit_int8((unsigned char)0xDD);
4159 emit_operand32(rsp, src);
4160 }
4162 void Assembler::fsin() {
4163 emit_int8((unsigned char)0xD9);
4164 emit_int8((unsigned char)0xFE);
4165 }
4167 void Assembler::fsqrt() {
4168 emit_int8((unsigned char)0xD9);
4169 emit_int8((unsigned char)0xFA);
4170 }
4172 void Assembler::fst_d(Address adr) {
4173 InstructionMark im(this);
4174 emit_int8((unsigned char)0xDD);
4175 emit_operand32(rdx, adr);
4176 }
4178 void Assembler::fst_s(Address adr) {
4179 InstructionMark im(this);
4180 emit_int8((unsigned char)0xD9);
4181 emit_operand32(rdx, adr);
4182 }
4184 void Assembler::fstp_d(Address adr) {
4185 InstructionMark im(this);
4186 emit_int8((unsigned char)0xDD);
4187 emit_operand32(rbx, adr);
4188 }
4190 void Assembler::fstp_d(int index) {
4191 emit_farith(0xDD, 0xD8, index);
4192 }
4194 void Assembler::fstp_s(Address adr) {
4195 InstructionMark im(this);
4196 emit_int8((unsigned char)0xD9);
4197 emit_operand32(rbx, adr);
4198 }
4200 void Assembler::fstp_x(Address adr) {
4201 InstructionMark im(this);
4202 emit_int8((unsigned char)0xDB);
4203 emit_operand32(rdi, adr);
4204 }
4206 void Assembler::fsub(int i) {
4207 emit_farith(0xD8, 0xE0, i);
4208 }
4210 void Assembler::fsub_d(Address src) {
4211 InstructionMark im(this);
4212 emit_int8((unsigned char)0xDC);
4213 emit_operand32(rsp, src);
4214 }
4216 void Assembler::fsub_s(Address src) {
4217 InstructionMark im(this);
4218 emit_int8((unsigned char)0xD8);
4219 emit_operand32(rsp, src);
4220 }
4222 void Assembler::fsuba(int i) {
4223 emit_farith(0xDC, 0xE8, i);
4224 }
4226 void Assembler::fsubp(int i) {
4227 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4228 }
4230 void Assembler::fsubr(int i) {
4231 emit_farith(0xD8, 0xE8, i);
4232 }
4234 void Assembler::fsubr_d(Address src) {
4235 InstructionMark im(this);
4236 emit_int8((unsigned char)0xDC);
4237 emit_operand32(rbp, src);
4238 }
4240 void Assembler::fsubr_s(Address src) {
4241 InstructionMark im(this);
4242 emit_int8((unsigned char)0xD8);
4243 emit_operand32(rbp, src);
4244 }
4246 void Assembler::fsubra(int i) {
4247 emit_farith(0xDC, 0xE0, i);
4248 }
4250 void Assembler::fsubrp(int i) {
4251 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4252 }
4254 void Assembler::ftan() {
4255 emit_int8((unsigned char)0xD9);
4256 emit_int8((unsigned char)0xF2);
4257 emit_int8((unsigned char)0xDD);
4258 emit_int8((unsigned char)0xD8);
4259 }
4261 void Assembler::ftst() {
4262 emit_int8((unsigned char)0xD9);
4263 emit_int8((unsigned char)0xE4);
4264 }
4266 void Assembler::fucomi(int i) {
4267 // make sure the instruction is supported (introduced for P6, together with cmov)
4268 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4269 emit_farith(0xDB, 0xE8, i);
4270 }
4272 void Assembler::fucomip(int i) {
4273 // make sure the instruction is supported (introduced for P6, together with cmov)
4274 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4275 emit_farith(0xDF, 0xE8, i);
4276 }
4278 void Assembler::fwait() {
4279 emit_int8((unsigned char)0x9B);
4280 }
4282 void Assembler::fxch(int i) {
4283 emit_farith(0xD9, 0xC8, i);
4284 }
4286 void Assembler::fyl2x() {
4287 emit_int8((unsigned char)0xD9);
4288 emit_int8((unsigned char)0xF1);
4289 }
4291 void Assembler::frndint() {
4292 emit_int8((unsigned char)0xD9);
4293 emit_int8((unsigned char)0xFC);
4294 }
4296 void Assembler::f2xm1() {
4297 emit_int8((unsigned char)0xD9);
4298 emit_int8((unsigned char)0xF0);
4299 }
4301 void Assembler::fldl2e() {
4302 emit_int8((unsigned char)0xD9);
4303 emit_int8((unsigned char)0xEA);
4304 }
4306 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4307 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4308 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4309 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4311 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4312 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4313 if (pre > 0) {
4314 emit_int8(simd_pre[pre]);
4315 }
4316 if (rex_w) {
4317 prefixq(adr, xreg);
4318 } else {
4319 prefix(adr, xreg);
4320 }
4321 if (opc > 0) {
4322 emit_int8(0x0F);
4323 int opc2 = simd_opc[opc];
4324 if (opc2 > 0) {
4325 emit_int8(opc2);
4326 }
4327 }
4328 }
4330 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4331 if (pre > 0) {
4332 emit_int8(simd_pre[pre]);
4333 }
4334 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4335 prefix_and_encode(dst_enc, src_enc);
4336 if (opc > 0) {
4337 emit_int8(0x0F);
4338 int opc2 = simd_opc[opc];
4339 if (opc2 > 0) {
4340 emit_int8(opc2);
4341 }
4342 }
4343 return encode;
4344 }
4347 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4348 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4349 prefix(VEX_3bytes);
4351 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4352 byte1 = (~byte1) & 0xE0;
4353 byte1 |= opc;
4354 emit_int8(byte1);
4356 int byte2 = ((~nds_enc) & 0xf) << 3;
4357 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4358 emit_int8(byte2);
4359 } else {
4360 prefix(VEX_2bytes);
4362 int byte1 = vex_r ? VEX_R : 0;
4363 byte1 = (~byte1) & 0x80;
4364 byte1 |= ((~nds_enc) & 0xf) << 3;
4365 byte1 |= (vector256 ? 4 : 0) | pre;
4366 emit_int8(byte1);
4367 }
4368 }
4370 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4371 bool vex_r = (xreg_enc >= 8);
4372 bool vex_b = adr.base_needs_rex();
4373 bool vex_x = adr.index_needs_rex();
4374 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4375 }
4377 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4378 bool vex_r = (dst_enc >= 8);
4379 bool vex_b = (src_enc >= 8);
4380 bool vex_x = false;
4381 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4382 return (((dst_enc & 7) << 3) | (src_enc & 7));
4383 }
4386 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4387 if (UseAVX > 0) {
4388 int xreg_enc = xreg->encoding();
4389 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4390 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4391 } else {
4392 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4393 rex_prefix(adr, xreg, pre, opc, rex_w);
4394 }
4395 }
4397 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4398 int dst_enc = dst->encoding();
4399 int src_enc = src->encoding();
4400 if (UseAVX > 0) {
4401 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4402 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4403 } else {
4404 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4405 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4406 }
4407 }
4409 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4410 InstructionMark im(this);
4411 simd_prefix(dst, dst, src, pre);
4412 emit_int8(opcode);
4413 emit_operand(dst, src);
4414 }
4416 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4417 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4418 emit_int8(opcode);
4419 emit_int8((unsigned char)(0xC0 | encode));
4420 }
4422 // Versions with no second source register (non-destructive source).
4423 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4424 InstructionMark im(this);
4425 simd_prefix(dst, xnoreg, src, pre);
4426 emit_int8(opcode);
4427 emit_operand(dst, src);
4428 }
4430 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4431 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4432 emit_int8(opcode);
4433 emit_int8((unsigned char)(0xC0 | encode));
4434 }
4436 // 3-operands AVX instructions
4437 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4438 Address src, VexSimdPrefix pre, bool vector256) {
4439 InstructionMark im(this);
4440 vex_prefix(dst, nds, src, pre, vector256);
4441 emit_int8(opcode);
4442 emit_operand(dst, src);
4443 }
4445 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4446 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4447 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4448 emit_int8(opcode);
4449 emit_int8((unsigned char)(0xC0 | encode));
4450 }
4452 #ifndef _LP64
4454 void Assembler::incl(Register dst) {
4455 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4456 emit_int8(0x40 | dst->encoding());
4457 }
4459 void Assembler::lea(Register dst, Address src) {
4460 leal(dst, src);
4461 }
4463 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4464 InstructionMark im(this);
4465 emit_int8((unsigned char)0xC7);
4466 emit_operand(rax, dst);
4467 emit_data((int)imm32, rspec, 0);
4468 }
4470 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4471 InstructionMark im(this);
4472 int encode = prefix_and_encode(dst->encoding());
4473 emit_int8((unsigned char)(0xB8 | encode));
4474 emit_data((int)imm32, rspec, 0);
4475 }
4477 void Assembler::popa() { // 32bit
4478 emit_int8(0x61);
4479 }
4481 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4482 InstructionMark im(this);
4483 emit_int8(0x68);
4484 emit_data(imm32, rspec, 0);
4485 }
4487 void Assembler::pusha() { // 32bit
4488 emit_int8(0x60);
4489 }
4491 void Assembler::set_byte_if_not_zero(Register dst) {
4492 emit_int8(0x0F);
4493 emit_int8((unsigned char)0x95);
4494 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4495 }
4497 void Assembler::shldl(Register dst, Register src) {
4498 emit_int8(0x0F);
4499 emit_int8((unsigned char)0xA5);
4500 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4501 }
4503 void Assembler::shrdl(Register dst, Register src) {
4504 emit_int8(0x0F);
4505 emit_int8((unsigned char)0xAD);
4506 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4507 }
4509 #else // LP64
4511 void Assembler::set_byte_if_not_zero(Register dst) {
4512 int enc = prefix_and_encode(dst->encoding(), true);
4513 emit_int8(0x0F);
4514 emit_int8((unsigned char)0x95);
4515 emit_int8((unsigned char)(0xE0 | enc));
4516 }
4518 // 64bit only pieces of the assembler
4519 // This should only be used by 64bit instructions that can use rip-relative
4520 // it cannot be used by instructions that want an immediate value.
4522 bool Assembler::reachable(AddressLiteral adr) {
4523 int64_t disp;
4524 // None will force a 64bit literal to the code stream. Likely a placeholder
4525 // for something that will be patched later and we need to certain it will
4526 // always be reachable.
4527 if (adr.reloc() == relocInfo::none) {
4528 return false;
4529 }
4530 if (adr.reloc() == relocInfo::internal_word_type) {
4531 // This should be rip relative and easily reachable.
4532 return true;
4533 }
4534 if (adr.reloc() == relocInfo::virtual_call_type ||
4535 adr.reloc() == relocInfo::opt_virtual_call_type ||
4536 adr.reloc() == relocInfo::static_call_type ||
4537 adr.reloc() == relocInfo::static_stub_type ) {
4538 // This should be rip relative within the code cache and easily
4539 // reachable until we get huge code caches. (At which point
4540 // ic code is going to have issues).
4541 return true;
4542 }
4543 if (adr.reloc() != relocInfo::external_word_type &&
4544 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4545 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4546 adr.reloc() != relocInfo::runtime_call_type ) {
4547 return false;
4548 }
4550 // Stress the correction code
4551 if (ForceUnreachable) {
4552 // Must be runtimecall reloc, see if it is in the codecache
4553 // Flipping stuff in the codecache to be unreachable causes issues
4554 // with things like inline caches where the additional instructions
4555 // are not handled.
4556 if (CodeCache::find_blob(adr._target) == NULL) {
4557 return false;
4558 }
4559 }
4560 // For external_word_type/runtime_call_type if it is reachable from where we
4561 // are now (possibly a temp buffer) and where we might end up
4562 // anywhere in the codeCache then we are always reachable.
4563 // This would have to change if we ever save/restore shared code
4564 // to be more pessimistic.
4565 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4566 if (!is_simm32(disp)) return false;
4567 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4568 if (!is_simm32(disp)) return false;
4570 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4572 // Because rip relative is a disp + address_of_next_instruction and we
4573 // don't know the value of address_of_next_instruction we apply a fudge factor
4574 // to make sure we will be ok no matter the size of the instruction we get placed into.
4575 // We don't have to fudge the checks above here because they are already worst case.
4577 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4578 // + 4 because better safe than sorry.
4579 const int fudge = 12 + 4;
4580 if (disp < 0) {
4581 disp -= fudge;
4582 } else {
4583 disp += fudge;
4584 }
4585 return is_simm32(disp);
4586 }
4588 // Check if the polling page is not reachable from the code cache using rip-relative
4589 // addressing.
4590 bool Assembler::is_polling_page_far() {
4591 intptr_t addr = (intptr_t)os::get_polling_page();
4592 return ForceUnreachable ||
4593 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4594 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4595 }
4597 void Assembler::emit_data64(jlong data,
4598 relocInfo::relocType rtype,
4599 int format) {
4600 if (rtype == relocInfo::none) {
4601 emit_int64(data);
4602 } else {
4603 emit_data64(data, Relocation::spec_simple(rtype), format);
4604 }
4605 }
4607 void Assembler::emit_data64(jlong data,
4608 RelocationHolder const& rspec,
4609 int format) {
4610 assert(imm_operand == 0, "default format must be immediate in this file");
4611 assert(imm_operand == format, "must be immediate");
4612 assert(inst_mark() != NULL, "must be inside InstructionMark");
4613 // Do not use AbstractAssembler::relocate, which is not intended for
4614 // embedded words. Instead, relocate to the enclosing instruction.
4615 code_section()->relocate(inst_mark(), rspec, format);
4616 #ifdef ASSERT
4617 check_relocation(rspec, format);
4618 #endif
4619 emit_int64(data);
4620 }
4622 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4623 if (reg_enc >= 8) {
4624 prefix(REX_B);
4625 reg_enc -= 8;
4626 } else if (byteinst && reg_enc >= 4) {
4627 prefix(REX);
4628 }
4629 return reg_enc;
4630 }
4632 int Assembler::prefixq_and_encode(int reg_enc) {
4633 if (reg_enc < 8) {
4634 prefix(REX_W);
4635 } else {
4636 prefix(REX_WB);
4637 reg_enc -= 8;
4638 }
4639 return reg_enc;
4640 }
4642 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4643 if (dst_enc < 8) {
4644 if (src_enc >= 8) {
4645 prefix(REX_B);
4646 src_enc -= 8;
4647 } else if (byteinst && src_enc >= 4) {
4648 prefix(REX);
4649 }
4650 } else {
4651 if (src_enc < 8) {
4652 prefix(REX_R);
4653 } else {
4654 prefix(REX_RB);
4655 src_enc -= 8;
4656 }
4657 dst_enc -= 8;
4658 }
4659 return dst_enc << 3 | src_enc;
4660 }
4662 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4663 if (dst_enc < 8) {
4664 if (src_enc < 8) {
4665 prefix(REX_W);
4666 } else {
4667 prefix(REX_WB);
4668 src_enc -= 8;
4669 }
4670 } else {
4671 if (src_enc < 8) {
4672 prefix(REX_WR);
4673 } else {
4674 prefix(REX_WRB);
4675 src_enc -= 8;
4676 }
4677 dst_enc -= 8;
4678 }
4679 return dst_enc << 3 | src_enc;
4680 }
4682 void Assembler::prefix(Register reg) {
4683 if (reg->encoding() >= 8) {
4684 prefix(REX_B);
4685 }
4686 }
4688 void Assembler::prefix(Address adr) {
4689 if (adr.base_needs_rex()) {
4690 if (adr.index_needs_rex()) {
4691 prefix(REX_XB);
4692 } else {
4693 prefix(REX_B);
4694 }
4695 } else {
4696 if (adr.index_needs_rex()) {
4697 prefix(REX_X);
4698 }
4699 }
4700 }
4702 void Assembler::prefixq(Address adr) {
4703 if (adr.base_needs_rex()) {
4704 if (adr.index_needs_rex()) {
4705 prefix(REX_WXB);
4706 } else {
4707 prefix(REX_WB);
4708 }
4709 } else {
4710 if (adr.index_needs_rex()) {
4711 prefix(REX_WX);
4712 } else {
4713 prefix(REX_W);
4714 }
4715 }
4716 }
4719 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4720 if (reg->encoding() < 8) {
4721 if (adr.base_needs_rex()) {
4722 if (adr.index_needs_rex()) {
4723 prefix(REX_XB);
4724 } else {
4725 prefix(REX_B);
4726 }
4727 } else {
4728 if (adr.index_needs_rex()) {
4729 prefix(REX_X);
4730 } else if (byteinst && reg->encoding() >= 4 ) {
4731 prefix(REX);
4732 }
4733 }
4734 } else {
4735 if (adr.base_needs_rex()) {
4736 if (adr.index_needs_rex()) {
4737 prefix(REX_RXB);
4738 } else {
4739 prefix(REX_RB);
4740 }
4741 } else {
4742 if (adr.index_needs_rex()) {
4743 prefix(REX_RX);
4744 } else {
4745 prefix(REX_R);
4746 }
4747 }
4748 }
4749 }
4751 void Assembler::prefixq(Address adr, Register src) {
4752 if (src->encoding() < 8) {
4753 if (adr.base_needs_rex()) {
4754 if (adr.index_needs_rex()) {
4755 prefix(REX_WXB);
4756 } else {
4757 prefix(REX_WB);
4758 }
4759 } else {
4760 if (adr.index_needs_rex()) {
4761 prefix(REX_WX);
4762 } else {
4763 prefix(REX_W);
4764 }
4765 }
4766 } else {
4767 if (adr.base_needs_rex()) {
4768 if (adr.index_needs_rex()) {
4769 prefix(REX_WRXB);
4770 } else {
4771 prefix(REX_WRB);
4772 }
4773 } else {
4774 if (adr.index_needs_rex()) {
4775 prefix(REX_WRX);
4776 } else {
4777 prefix(REX_WR);
4778 }
4779 }
4780 }
4781 }
4783 void Assembler::prefix(Address adr, XMMRegister reg) {
4784 if (reg->encoding() < 8) {
4785 if (adr.base_needs_rex()) {
4786 if (adr.index_needs_rex()) {
4787 prefix(REX_XB);
4788 } else {
4789 prefix(REX_B);
4790 }
4791 } else {
4792 if (adr.index_needs_rex()) {
4793 prefix(REX_X);
4794 }
4795 }
4796 } else {
4797 if (adr.base_needs_rex()) {
4798 if (adr.index_needs_rex()) {
4799 prefix(REX_RXB);
4800 } else {
4801 prefix(REX_RB);
4802 }
4803 } else {
4804 if (adr.index_needs_rex()) {
4805 prefix(REX_RX);
4806 } else {
4807 prefix(REX_R);
4808 }
4809 }
4810 }
4811 }
4813 void Assembler::prefixq(Address adr, XMMRegister src) {
4814 if (src->encoding() < 8) {
4815 if (adr.base_needs_rex()) {
4816 if (adr.index_needs_rex()) {
4817 prefix(REX_WXB);
4818 } else {
4819 prefix(REX_WB);
4820 }
4821 } else {
4822 if (adr.index_needs_rex()) {
4823 prefix(REX_WX);
4824 } else {
4825 prefix(REX_W);
4826 }
4827 }
4828 } else {
4829 if (adr.base_needs_rex()) {
4830 if (adr.index_needs_rex()) {
4831 prefix(REX_WRXB);
4832 } else {
4833 prefix(REX_WRB);
4834 }
4835 } else {
4836 if (adr.index_needs_rex()) {
4837 prefix(REX_WRX);
4838 } else {
4839 prefix(REX_WR);
4840 }
4841 }
4842 }
4843 }
4845 void Assembler::adcq(Register dst, int32_t imm32) {
4846 (void) prefixq_and_encode(dst->encoding());
4847 emit_arith(0x81, 0xD0, dst, imm32);
4848 }
4850 void Assembler::adcq(Register dst, Address src) {
4851 InstructionMark im(this);
4852 prefixq(src, dst);
4853 emit_int8(0x13);
4854 emit_operand(dst, src);
4855 }
4857 void Assembler::adcq(Register dst, Register src) {
4858 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4859 emit_arith(0x13, 0xC0, dst, src);
4860 }
4862 void Assembler::addq(Address dst, int32_t imm32) {
4863 InstructionMark im(this);
4864 prefixq(dst);
4865 emit_arith_operand(0x81, rax, dst,imm32);
4866 }
4868 void Assembler::addq(Address dst, Register src) {
4869 InstructionMark im(this);
4870 prefixq(dst, src);
4871 emit_int8(0x01);
4872 emit_operand(src, dst);
4873 }
4875 void Assembler::addq(Register dst, int32_t imm32) {
4876 (void) prefixq_and_encode(dst->encoding());
4877 emit_arith(0x81, 0xC0, dst, imm32);
4878 }
4880 void Assembler::addq(Register dst, Address src) {
4881 InstructionMark im(this);
4882 prefixq(src, dst);
4883 emit_int8(0x03);
4884 emit_operand(dst, src);
4885 }
4887 void Assembler::addq(Register dst, Register src) {
4888 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4889 emit_arith(0x03, 0xC0, dst, src);
4890 }
4892 void Assembler::andq(Address dst, int32_t imm32) {
4893 InstructionMark im(this);
4894 prefixq(dst);
4895 emit_int8((unsigned char)0x81);
4896 emit_operand(rsp, dst, 4);
4897 emit_int32(imm32);
4898 }
4900 void Assembler::andq(Register dst, int32_t imm32) {
4901 (void) prefixq_and_encode(dst->encoding());
4902 emit_arith(0x81, 0xE0, dst, imm32);
4903 }
4905 void Assembler::andq(Register dst, Address src) {
4906 InstructionMark im(this);
4907 prefixq(src, dst);
4908 emit_int8(0x23);
4909 emit_operand(dst, src);
4910 }
4912 void Assembler::andq(Register dst, Register src) {
4913 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4914 emit_arith(0x23, 0xC0, dst, src);
4915 }
4917 void Assembler::andnq(Register dst, Register src1, Register src2) {
4918 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4919 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
4920 emit_int8((unsigned char)0xF2);
4921 emit_int8((unsigned char)(0xC0 | encode));
4922 }
4924 void Assembler::andnq(Register dst, Register src1, Address src2) {
4925 InstructionMark im(this);
4926 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4927 vex_prefix_0F38_q(dst, src1, src2);
4928 emit_int8((unsigned char)0xF2);
4929 emit_operand(dst, src2);
4930 }
4932 void Assembler::bsfq(Register dst, Register src) {
4933 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4934 emit_int8(0x0F);
4935 emit_int8((unsigned char)0xBC);
4936 emit_int8((unsigned char)(0xC0 | encode));
4937 }
4939 void Assembler::bsrq(Register dst, Register src) {
4940 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4941 emit_int8(0x0F);
4942 emit_int8((unsigned char)0xBD);
4943 emit_int8((unsigned char)(0xC0 | encode));
4944 }
4946 void Assembler::bswapq(Register reg) {
4947 int encode = prefixq_and_encode(reg->encoding());
4948 emit_int8(0x0F);
4949 emit_int8((unsigned char)(0xC8 | encode));
4950 }
4952 void Assembler::blsiq(Register dst, Register src) {
4953 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4954 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
4955 emit_int8((unsigned char)0xF3);
4956 emit_int8((unsigned char)(0xC0 | encode));
4957 }
4959 void Assembler::blsiq(Register dst, Address src) {
4960 InstructionMark im(this);
4961 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4962 vex_prefix_0F38_q(rbx, dst, src);
4963 emit_int8((unsigned char)0xF3);
4964 emit_operand(rbx, src);
4965 }
4967 void Assembler::blsmskq(Register dst, Register src) {
4968 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4969 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
4970 emit_int8((unsigned char)0xF3);
4971 emit_int8((unsigned char)(0xC0 | encode));
4972 }
4974 void Assembler::blsmskq(Register dst, Address src) {
4975 InstructionMark im(this);
4976 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4977 vex_prefix_0F38_q(rdx, dst, src);
4978 emit_int8((unsigned char)0xF3);
4979 emit_operand(rdx, src);
4980 }
4982 void Assembler::blsrq(Register dst, Register src) {
4983 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4984 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
4985 emit_int8((unsigned char)0xF3);
4986 emit_int8((unsigned char)(0xC0 | encode));
4987 }
4989 void Assembler::blsrq(Register dst, Address src) {
4990 InstructionMark im(this);
4991 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4992 vex_prefix_0F38_q(rcx, dst, src);
4993 emit_int8((unsigned char)0xF3);
4994 emit_operand(rcx, src);
4995 }
4997 void Assembler::cdqq() {
4998 prefix(REX_W);
4999 emit_int8((unsigned char)0x99);
5000 }
5002 void Assembler::clflush(Address adr) {
5003 prefix(adr);
5004 emit_int8(0x0F);
5005 emit_int8((unsigned char)0xAE);
5006 emit_operand(rdi, adr);
5007 }
5009 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5010 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5011 emit_int8(0x0F);
5012 emit_int8(0x40 | cc);
5013 emit_int8((unsigned char)(0xC0 | encode));
5014 }
5016 void Assembler::cmovq(Condition cc, Register dst, Address src) {
5017 InstructionMark im(this);
5018 prefixq(src, dst);
5019 emit_int8(0x0F);
5020 emit_int8(0x40 | cc);
5021 emit_operand(dst, src);
5022 }
5024 void Assembler::cmpq(Address dst, int32_t imm32) {
5025 InstructionMark im(this);
5026 prefixq(dst);
5027 emit_int8((unsigned char)0x81);
5028 emit_operand(rdi, dst, 4);
5029 emit_int32(imm32);
5030 }
5032 void Assembler::cmpq(Register dst, int32_t imm32) {
5033 (void) prefixq_and_encode(dst->encoding());
5034 emit_arith(0x81, 0xF8, dst, imm32);
5035 }
5037 void Assembler::cmpq(Address dst, Register src) {
5038 InstructionMark im(this);
5039 prefixq(dst, src);
5040 emit_int8(0x3B);
5041 emit_operand(src, dst);
5042 }
5044 void Assembler::cmpq(Register dst, Register src) {
5045 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5046 emit_arith(0x3B, 0xC0, dst, src);
5047 }
5049 void Assembler::cmpq(Register dst, Address src) {
5050 InstructionMark im(this);
5051 prefixq(src, dst);
5052 emit_int8(0x3B);
5053 emit_operand(dst, src);
5054 }
5056 void Assembler::cmpxchgq(Register reg, Address adr) {
5057 InstructionMark im(this);
5058 prefixq(adr, reg);
5059 emit_int8(0x0F);
5060 emit_int8((unsigned char)0xB1);
5061 emit_operand(reg, adr);
5062 }
5064 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
5065 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5066 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
5067 emit_int8(0x2A);
5068 emit_int8((unsigned char)(0xC0 | encode));
5069 }
5071 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
5072 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5073 InstructionMark im(this);
5074 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
5075 emit_int8(0x2A);
5076 emit_operand(dst, src);
5077 }
5079 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
5080 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5081 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
5082 emit_int8(0x2A);
5083 emit_int8((unsigned char)(0xC0 | encode));
5084 }
5086 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
5087 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5088 InstructionMark im(this);
5089 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
5090 emit_int8(0x2A);
5091 emit_operand(dst, src);
5092 }
5094 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
5095 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5096 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
5097 emit_int8(0x2C);
5098 emit_int8((unsigned char)(0xC0 | encode));
5099 }
5101 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
5102 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5103 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
5104 emit_int8(0x2C);
5105 emit_int8((unsigned char)(0xC0 | encode));
5106 }
5108 void Assembler::decl(Register dst) {
5109 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5110 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
5111 int encode = prefix_and_encode(dst->encoding());
5112 emit_int8((unsigned char)0xFF);
5113 emit_int8((unsigned char)(0xC8 | encode));
5114 }
5116 void Assembler::decq(Register dst) {
5117 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5118 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5119 int encode = prefixq_and_encode(dst->encoding());
5120 emit_int8((unsigned char)0xFF);
5121 emit_int8(0xC8 | encode);
5122 }
5124 void Assembler::decq(Address dst) {
5125 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5126 InstructionMark im(this);
5127 prefixq(dst);
5128 emit_int8((unsigned char)0xFF);
5129 emit_operand(rcx, dst);
5130 }
5132 void Assembler::fxrstor(Address src) {
5133 prefixq(src);
5134 emit_int8(0x0F);
5135 emit_int8((unsigned char)0xAE);
5136 emit_operand(as_Register(1), src);
5137 }
5139 void Assembler::fxsave(Address dst) {
5140 prefixq(dst);
5141 emit_int8(0x0F);
5142 emit_int8((unsigned char)0xAE);
5143 emit_operand(as_Register(0), dst);
5144 }
5146 void Assembler::idivq(Register src) {
5147 int encode = prefixq_and_encode(src->encoding());
5148 emit_int8((unsigned char)0xF7);
5149 emit_int8((unsigned char)(0xF8 | encode));
5150 }
5152 void Assembler::imulq(Register dst, Register src) {
5153 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5154 emit_int8(0x0F);
5155 emit_int8((unsigned char)0xAF);
5156 emit_int8((unsigned char)(0xC0 | encode));
5157 }
5159 void Assembler::imulq(Register dst, Register src, int value) {
5160 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5161 if (is8bit(value)) {
5162 emit_int8(0x6B);
5163 emit_int8((unsigned char)(0xC0 | encode));
5164 emit_int8(value & 0xFF);
5165 } else {
5166 emit_int8(0x69);
5167 emit_int8((unsigned char)(0xC0 | encode));
5168 emit_int32(value);
5169 }
5170 }
5172 void Assembler::imulq(Register dst, Address src) {
5173 InstructionMark im(this);
5174 prefixq(src, dst);
5175 emit_int8(0x0F);
5176 emit_int8((unsigned char) 0xAF);
5177 emit_operand(dst, src);
5178 }
5180 void Assembler::incl(Register dst) {
5181 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5182 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5183 int encode = prefix_and_encode(dst->encoding());
5184 emit_int8((unsigned char)0xFF);
5185 emit_int8((unsigned char)(0xC0 | encode));
5186 }
5188 void Assembler::incq(Register dst) {
5189 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5190 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5191 int encode = prefixq_and_encode(dst->encoding());
5192 emit_int8((unsigned char)0xFF);
5193 emit_int8((unsigned char)(0xC0 | encode));
5194 }
5196 void Assembler::incq(Address dst) {
5197 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5198 InstructionMark im(this);
5199 prefixq(dst);
5200 emit_int8((unsigned char)0xFF);
5201 emit_operand(rax, dst);
5202 }
5204 void Assembler::lea(Register dst, Address src) {
5205 leaq(dst, src);
5206 }
5208 void Assembler::leaq(Register dst, Address src) {
5209 InstructionMark im(this);
5210 prefixq(src, dst);
5211 emit_int8((unsigned char)0x8D);
5212 emit_operand(dst, src);
5213 }
5215 void Assembler::mov64(Register dst, int64_t imm64) {
5216 InstructionMark im(this);
5217 int encode = prefixq_and_encode(dst->encoding());
5218 emit_int8((unsigned char)(0xB8 | encode));
5219 emit_int64(imm64);
5220 }
5222 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5223 InstructionMark im(this);
5224 int encode = prefixq_and_encode(dst->encoding());
5225 emit_int8(0xB8 | encode);
5226 emit_data64(imm64, rspec);
5227 }
5229 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5230 InstructionMark im(this);
5231 int encode = prefix_and_encode(dst->encoding());
5232 emit_int8((unsigned char)(0xB8 | encode));
5233 emit_data((int)imm32, rspec, narrow_oop_operand);
5234 }
5236 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5237 InstructionMark im(this);
5238 prefix(dst);
5239 emit_int8((unsigned char)0xC7);
5240 emit_operand(rax, dst, 4);
5241 emit_data((int)imm32, rspec, narrow_oop_operand);
5242 }
5244 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5245 InstructionMark im(this);
5246 int encode = prefix_and_encode(src1->encoding());
5247 emit_int8((unsigned char)0x81);
5248 emit_int8((unsigned char)(0xF8 | encode));
5249 emit_data((int)imm32, rspec, narrow_oop_operand);
5250 }
5252 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5253 InstructionMark im(this);
5254 prefix(src1);
5255 emit_int8((unsigned char)0x81);
5256 emit_operand(rax, src1, 4);
5257 emit_data((int)imm32, rspec, narrow_oop_operand);
5258 }
5260 void Assembler::lzcntq(Register dst, Register src) {
5261 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5262 emit_int8((unsigned char)0xF3);
5263 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5264 emit_int8(0x0F);
5265 emit_int8((unsigned char)0xBD);
5266 emit_int8((unsigned char)(0xC0 | encode));
5267 }
5269 void Assembler::movdq(XMMRegister dst, Register src) {
5270 // table D-1 says MMX/SSE2
5271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5272 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5273 emit_int8(0x6E);
5274 emit_int8((unsigned char)(0xC0 | encode));
5275 }
5277 void Assembler::movdq(Register dst, XMMRegister src) {
5278 // table D-1 says MMX/SSE2
5279 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5280 // swap src/dst to get correct prefix
5281 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5282 emit_int8(0x7E);
5283 emit_int8((unsigned char)(0xC0 | encode));
5284 }
5286 void Assembler::movq(Register dst, Register src) {
5287 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5288 emit_int8((unsigned char)0x8B);
5289 emit_int8((unsigned char)(0xC0 | encode));
5290 }
5292 void Assembler::movq(Register dst, Address src) {
5293 InstructionMark im(this);
5294 prefixq(src, dst);
5295 emit_int8((unsigned char)0x8B);
5296 emit_operand(dst, src);
5297 }
5299 void Assembler::movq(Address dst, Register src) {
5300 InstructionMark im(this);
5301 prefixq(dst, src);
5302 emit_int8((unsigned char)0x89);
5303 emit_operand(src, dst);
5304 }
5306 void Assembler::movsbq(Register dst, Address src) {
5307 InstructionMark im(this);
5308 prefixq(src, dst);
5309 emit_int8(0x0F);
5310 emit_int8((unsigned char)0xBE);
5311 emit_operand(dst, src);
5312 }
5314 void Assembler::movsbq(Register dst, Register src) {
5315 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5316 emit_int8(0x0F);
5317 emit_int8((unsigned char)0xBE);
5318 emit_int8((unsigned char)(0xC0 | encode));
5319 }
5321 void Assembler::movslq(Register dst, int32_t imm32) {
5322 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5323 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5324 // as a result we shouldn't use until tested at runtime...
5325 ShouldNotReachHere();
5326 InstructionMark im(this);
5327 int encode = prefixq_and_encode(dst->encoding());
5328 emit_int8((unsigned char)(0xC7 | encode));
5329 emit_int32(imm32);
5330 }
5332 void Assembler::movslq(Address dst, int32_t imm32) {
5333 assert(is_simm32(imm32), "lost bits");
5334 InstructionMark im(this);
5335 prefixq(dst);
5336 emit_int8((unsigned char)0xC7);
5337 emit_operand(rax, dst, 4);
5338 emit_int32(imm32);
5339 }
5341 void Assembler::movslq(Register dst, Address src) {
5342 InstructionMark im(this);
5343 prefixq(src, dst);
5344 emit_int8(0x63);
5345 emit_operand(dst, src);
5346 }
5348 void Assembler::movslq(Register dst, Register src) {
5349 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5350 emit_int8(0x63);
5351 emit_int8((unsigned char)(0xC0 | encode));
5352 }
5354 void Assembler::movswq(Register dst, Address src) {
5355 InstructionMark im(this);
5356 prefixq(src, dst);
5357 emit_int8(0x0F);
5358 emit_int8((unsigned char)0xBF);
5359 emit_operand(dst, src);
5360 }
5362 void Assembler::movswq(Register dst, Register src) {
5363 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5364 emit_int8((unsigned char)0x0F);
5365 emit_int8((unsigned char)0xBF);
5366 emit_int8((unsigned char)(0xC0 | encode));
5367 }
5369 void Assembler::movzbq(Register dst, Address src) {
5370 InstructionMark im(this);
5371 prefixq(src, dst);
5372 emit_int8((unsigned char)0x0F);
5373 emit_int8((unsigned char)0xB6);
5374 emit_operand(dst, src);
5375 }
5377 void Assembler::movzbq(Register dst, Register src) {
5378 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5379 emit_int8(0x0F);
5380 emit_int8((unsigned char)0xB6);
5381 emit_int8(0xC0 | encode);
5382 }
5384 void Assembler::movzwq(Register dst, Address src) {
5385 InstructionMark im(this);
5386 prefixq(src, dst);
5387 emit_int8((unsigned char)0x0F);
5388 emit_int8((unsigned char)0xB7);
5389 emit_operand(dst, src);
5390 }
5392 void Assembler::movzwq(Register dst, Register src) {
5393 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5394 emit_int8((unsigned char)0x0F);
5395 emit_int8((unsigned char)0xB7);
5396 emit_int8((unsigned char)(0xC0 | encode));
5397 }
5399 void Assembler::negq(Register dst) {
5400 int encode = prefixq_and_encode(dst->encoding());
5401 emit_int8((unsigned char)0xF7);
5402 emit_int8((unsigned char)(0xD8 | encode));
5403 }
5405 void Assembler::notq(Register dst) {
5406 int encode = prefixq_and_encode(dst->encoding());
5407 emit_int8((unsigned char)0xF7);
5408 emit_int8((unsigned char)(0xD0 | encode));
5409 }
5411 void Assembler::orq(Address dst, int32_t imm32) {
5412 InstructionMark im(this);
5413 prefixq(dst);
5414 emit_int8((unsigned char)0x81);
5415 emit_operand(rcx, dst, 4);
5416 emit_int32(imm32);
5417 }
5419 void Assembler::orq(Register dst, int32_t imm32) {
5420 (void) prefixq_and_encode(dst->encoding());
5421 emit_arith(0x81, 0xC8, dst, imm32);
5422 }
5424 void Assembler::orq(Register dst, Address src) {
5425 InstructionMark im(this);
5426 prefixq(src, dst);
5427 emit_int8(0x0B);
5428 emit_operand(dst, src);
5429 }
5431 void Assembler::orq(Register dst, Register src) {
5432 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5433 emit_arith(0x0B, 0xC0, dst, src);
5434 }
5436 void Assembler::popa() { // 64bit
5437 movq(r15, Address(rsp, 0));
5438 movq(r14, Address(rsp, wordSize));
5439 movq(r13, Address(rsp, 2 * wordSize));
5440 movq(r12, Address(rsp, 3 * wordSize));
5441 movq(r11, Address(rsp, 4 * wordSize));
5442 movq(r10, Address(rsp, 5 * wordSize));
5443 movq(r9, Address(rsp, 6 * wordSize));
5444 movq(r8, Address(rsp, 7 * wordSize));
5445 movq(rdi, Address(rsp, 8 * wordSize));
5446 movq(rsi, Address(rsp, 9 * wordSize));
5447 movq(rbp, Address(rsp, 10 * wordSize));
5448 // skip rsp
5449 movq(rbx, Address(rsp, 12 * wordSize));
5450 movq(rdx, Address(rsp, 13 * wordSize));
5451 movq(rcx, Address(rsp, 14 * wordSize));
5452 movq(rax, Address(rsp, 15 * wordSize));
5454 addq(rsp, 16 * wordSize);
5455 }
5457 void Assembler::popcntq(Register dst, Address src) {
5458 assert(VM_Version::supports_popcnt(), "must support");
5459 InstructionMark im(this);
5460 emit_int8((unsigned char)0xF3);
5461 prefixq(src, dst);
5462 emit_int8((unsigned char)0x0F);
5463 emit_int8((unsigned char)0xB8);
5464 emit_operand(dst, src);
5465 }
5467 void Assembler::popcntq(Register dst, Register src) {
5468 assert(VM_Version::supports_popcnt(), "must support");
5469 emit_int8((unsigned char)0xF3);
5470 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5471 emit_int8((unsigned char)0x0F);
5472 emit_int8((unsigned char)0xB8);
5473 emit_int8((unsigned char)(0xC0 | encode));
5474 }
5476 void Assembler::popq(Address dst) {
5477 InstructionMark im(this);
5478 prefixq(dst);
5479 emit_int8((unsigned char)0x8F);
5480 emit_operand(rax, dst);
5481 }
5483 void Assembler::pusha() { // 64bit
5484 // we have to store original rsp. ABI says that 128 bytes
5485 // below rsp are local scratch.
5486 movq(Address(rsp, -5 * wordSize), rsp);
5488 subq(rsp, 16 * wordSize);
5490 movq(Address(rsp, 15 * wordSize), rax);
5491 movq(Address(rsp, 14 * wordSize), rcx);
5492 movq(Address(rsp, 13 * wordSize), rdx);
5493 movq(Address(rsp, 12 * wordSize), rbx);
5494 // skip rsp
5495 movq(Address(rsp, 10 * wordSize), rbp);
5496 movq(Address(rsp, 9 * wordSize), rsi);
5497 movq(Address(rsp, 8 * wordSize), rdi);
5498 movq(Address(rsp, 7 * wordSize), r8);
5499 movq(Address(rsp, 6 * wordSize), r9);
5500 movq(Address(rsp, 5 * wordSize), r10);
5501 movq(Address(rsp, 4 * wordSize), r11);
5502 movq(Address(rsp, 3 * wordSize), r12);
5503 movq(Address(rsp, 2 * wordSize), r13);
5504 movq(Address(rsp, wordSize), r14);
5505 movq(Address(rsp, 0), r15);
5506 }
5508 void Assembler::pushq(Address src) {
5509 InstructionMark im(this);
5510 prefixq(src);
5511 emit_int8((unsigned char)0xFF);
5512 emit_operand(rsi, src);
5513 }
5515 void Assembler::rclq(Register dst, int imm8) {
5516 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5517 int encode = prefixq_and_encode(dst->encoding());
5518 if (imm8 == 1) {
5519 emit_int8((unsigned char)0xD1);
5520 emit_int8((unsigned char)(0xD0 | encode));
5521 } else {
5522 emit_int8((unsigned char)0xC1);
5523 emit_int8((unsigned char)(0xD0 | encode));
5524 emit_int8(imm8);
5525 }
5526 }
5527 void Assembler::sarq(Register dst, int imm8) {
5528 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5529 int encode = prefixq_and_encode(dst->encoding());
5530 if (imm8 == 1) {
5531 emit_int8((unsigned char)0xD1);
5532 emit_int8((unsigned char)(0xF8 | encode));
5533 } else {
5534 emit_int8((unsigned char)0xC1);
5535 emit_int8((unsigned char)(0xF8 | encode));
5536 emit_int8(imm8);
5537 }
5538 }
5540 void Assembler::sarq(Register dst) {
5541 int encode = prefixq_and_encode(dst->encoding());
5542 emit_int8((unsigned char)0xD3);
5543 emit_int8((unsigned char)(0xF8 | encode));
5544 }
5546 void Assembler::sbbq(Address dst, int32_t imm32) {
5547 InstructionMark im(this);
5548 prefixq(dst);
5549 emit_arith_operand(0x81, rbx, dst, imm32);
5550 }
5552 void Assembler::sbbq(Register dst, int32_t imm32) {
5553 (void) prefixq_and_encode(dst->encoding());
5554 emit_arith(0x81, 0xD8, dst, imm32);
5555 }
5557 void Assembler::sbbq(Register dst, Address src) {
5558 InstructionMark im(this);
5559 prefixq(src, dst);
5560 emit_int8(0x1B);
5561 emit_operand(dst, src);
5562 }
5564 void Assembler::sbbq(Register dst, Register src) {
5565 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5566 emit_arith(0x1B, 0xC0, dst, src);
5567 }
5569 void Assembler::shlq(Register dst, int imm8) {
5570 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5571 int encode = prefixq_and_encode(dst->encoding());
5572 if (imm8 == 1) {
5573 emit_int8((unsigned char)0xD1);
5574 emit_int8((unsigned char)(0xE0 | encode));
5575 } else {
5576 emit_int8((unsigned char)0xC1);
5577 emit_int8((unsigned char)(0xE0 | encode));
5578 emit_int8(imm8);
5579 }
5580 }
5582 void Assembler::shlq(Register dst) {
5583 int encode = prefixq_and_encode(dst->encoding());
5584 emit_int8((unsigned char)0xD3);
5585 emit_int8((unsigned char)(0xE0 | encode));
5586 }
5588 void Assembler::shrq(Register dst, int imm8) {
5589 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5590 int encode = prefixq_and_encode(dst->encoding());
5591 emit_int8((unsigned char)0xC1);
5592 emit_int8((unsigned char)(0xE8 | encode));
5593 emit_int8(imm8);
5594 }
5596 void Assembler::shrq(Register dst) {
5597 int encode = prefixq_and_encode(dst->encoding());
5598 emit_int8((unsigned char)0xD3);
5599 emit_int8(0xE8 | encode);
5600 }
5602 void Assembler::subq(Address dst, int32_t imm32) {
5603 InstructionMark im(this);
5604 prefixq(dst);
5605 emit_arith_operand(0x81, rbp, dst, imm32);
5606 }
5608 void Assembler::subq(Address dst, Register src) {
5609 InstructionMark im(this);
5610 prefixq(dst, src);
5611 emit_int8(0x29);
5612 emit_operand(src, dst);
5613 }
5615 void Assembler::subq(Register dst, int32_t imm32) {
5616 (void) prefixq_and_encode(dst->encoding());
5617 emit_arith(0x81, 0xE8, dst, imm32);
5618 }
5620 // Force generation of a 4 byte immediate value even if it fits into 8bit
5621 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5622 (void) prefixq_and_encode(dst->encoding());
5623 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5624 }
5626 void Assembler::subq(Register dst, Address src) {
5627 InstructionMark im(this);
5628 prefixq(src, dst);
5629 emit_int8(0x2B);
5630 emit_operand(dst, src);
5631 }
5633 void Assembler::subq(Register dst, Register src) {
5634 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5635 emit_arith(0x2B, 0xC0, dst, src);
5636 }
5638 void Assembler::testq(Register dst, int32_t imm32) {
5639 // not using emit_arith because test
5640 // doesn't support sign-extension of
5641 // 8bit operands
5642 int encode = dst->encoding();
5643 if (encode == 0) {
5644 prefix(REX_W);
5645 emit_int8((unsigned char)0xA9);
5646 } else {
5647 encode = prefixq_and_encode(encode);
5648 emit_int8((unsigned char)0xF7);
5649 emit_int8((unsigned char)(0xC0 | encode));
5650 }
5651 emit_int32(imm32);
5652 }
5654 void Assembler::testq(Register dst, Register src) {
5655 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5656 emit_arith(0x85, 0xC0, dst, src);
5657 }
5659 void Assembler::xaddq(Address dst, Register src) {
5660 InstructionMark im(this);
5661 prefixq(dst, src);
5662 emit_int8(0x0F);
5663 emit_int8((unsigned char)0xC1);
5664 emit_operand(src, dst);
5665 }
5667 void Assembler::xchgq(Register dst, Address src) {
5668 InstructionMark im(this);
5669 prefixq(src, dst);
5670 emit_int8((unsigned char)0x87);
5671 emit_operand(dst, src);
5672 }
5674 void Assembler::xchgq(Register dst, Register src) {
5675 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5676 emit_int8((unsigned char)0x87);
5677 emit_int8((unsigned char)(0xc0 | encode));
5678 }
5680 void Assembler::xorq(Register dst, Register src) {
5681 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5682 emit_arith(0x33, 0xC0, dst, src);
5683 }
5685 void Assembler::xorq(Register dst, Address src) {
5686 InstructionMark im(this);
5687 prefixq(src, dst);
5688 emit_int8(0x33);
5689 emit_operand(dst, src);
5690 }
5692 #endif // !LP64