Mon, 03 May 2010 16:31:07 -0400
Merge
1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 class BiasedLockingCounters;
27 // <sys/trap.h> promises that the system will not use traps 16-31
28 #define ST_RESERVED_FOR_USER_0 0x10
30 /* Written: David Ungar 4/19/97 */
32 // Contains all the definitions needed for sparc assembly code generation.
34 // Register aliases for parts of the system:
36 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
37 // across context switches in V8+ ABI. Of course, there are no 64 bit regs
38 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
40 // g2-g4 are scratch registers called "application globals". Their
41 // meaning is reserved to the "compilation system"--which means us!
42 // They are are not supposed to be touched by ordinary C code, although
43 // highly-optimized C code might steal them for temps. They are safe
44 // across thread switches, and the ABI requires that they be safe
45 // across function calls.
46 //
47 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
48 // across func calls, and V8+ also allows g5 to be clobbered across
49 // func calls. Also, g1 and g5 can get touched while doing shared
50 // library loading.
51 //
52 // We must not touch g7 (it is the thread-self register) and g6 is
53 // reserved for certain tools. g0, of course, is always zero.
54 //
55 // (Sources: SunSoft Compilers Group, thread library engineers.)
57 // %%%% The interpreter should be revisited to reduce global scratch regs.
59 // This global always holds the current JavaThread pointer:
61 REGISTER_DECLARATION(Register, G2_thread , G2);
62 REGISTER_DECLARATION(Register, G6_heapbase , G6);
64 // The following globals are part of the Java calling convention:
66 REGISTER_DECLARATION(Register, G5_method , G5);
67 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
68 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
70 // The following globals are used for the new C1 & interpreter calling convention:
71 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
73 // This local is used to preserve G2_thread in the interpreter and in stubs:
74 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
76 // These globals are used as scratch registers in the interpreter:
78 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
79 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
80 REGISTER_DECLARATION(Register, G3_scratch , G3);
81 REGISTER_DECLARATION(Register, G4_scratch , G4);
83 // These globals are used as short-lived scratch registers in the compiler:
85 REGISTER_DECLARATION(Register, Gtemp , G5);
87 // JSR 292 fixed register usages:
88 REGISTER_DECLARATION(Register, G5_method_type , G5);
89 REGISTER_DECLARATION(Register, G3_method_handle , G3);
91 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
92 // because a single patchable "set" instruction (NativeMovConstReg,
93 // or NativeMovConstPatching for compiler1) instruction
94 // serves to set up either quantity, depending on whether the compiled
95 // call site is an inline cache or is megamorphic. See the function
96 // CompiledIC::set_to_megamorphic.
97 //
98 // If a inline cache targets an interpreted method, then the
99 // G5 register will be used twice during the call. First,
100 // the call site will be patched to load a compiledICHolder
101 // into G5. (This is an ordered pair of ic_klass, method.)
102 // The c2i adapter will first check the ic_klass, then load
103 // G5_method with the method part of the pair just before
104 // jumping into the interpreter.
105 //
106 // Note that G5_method is only the method-self for the interpreter,
107 // and is logically unrelated to G5_megamorphic_method.
108 //
109 // Invariants on G2_thread (the JavaThread pointer):
110 // - it should not be used for any other purpose anywhere
111 // - it must be re-initialized by StubRoutines::call_stub()
112 // - it must be preserved around every use of call_VM
114 // We can consider using g2/g3/g4 to cache more values than the
115 // JavaThread, such as the card-marking base or perhaps pointers into
116 // Eden. It's something of a waste to use them as scratch temporaries,
117 // since they are not supposed to be volatile. (Of course, if we find
118 // that Java doesn't benefit from application globals, then we can just
119 // use them as ordinary temporaries.)
120 //
121 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
122 // it makes sense to use them routinely for procedure linkage,
123 // whenever the On registers are not applicable. Examples: G5_method,
124 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
125 // stubs. This means that compiler stubs, etc., should be kept to a
126 // maximum of two or three G-register arguments.
129 // stub frames
131 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
133 // Interpreter frames
135 #ifdef CC_INTERP
136 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
137 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
138 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
139 REGISTER_DECLARATION(Register, L2_scratch , L2);
140 REGISTER_DECLARATION(Register, L3_scratch , L3);
141 REGISTER_DECLARATION(Register, L4_scratch , L4);
142 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
143 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
144 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
145 REGISTER_DECLARATION(Register, O5_savedSP , O5);
146 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
147 // a copy SP, so in 64-bit it's a biased value. The bias
148 // is added and removed as needed in the frame code.
149 // Interface to signature handler
150 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
151 REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler
153 #else
154 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
155 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
156 REGISTER_DECLARATION(Register, Lmethod , L2);
157 REGISTER_DECLARATION(Register, Llocals , L3);
158 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
159 // must match Llocals in asm interpreter
160 REGISTER_DECLARATION(Register, Lmonitors , L4);
161 REGISTER_DECLARATION(Register, Lbyte_code , L5);
162 // When calling out from the interpreter we record SP so that we can remove any extra stack
163 // space allocated during adapter transitions. This register is only live from the point
164 // of the call until we return.
165 REGISTER_DECLARATION(Register, Llast_SP , L5);
166 REGISTER_DECLARATION(Register, Lscratch , L5);
167 REGISTER_DECLARATION(Register, Lscratch2 , L6);
168 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
170 REGISTER_DECLARATION(Register, O5_savedSP , O5);
171 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
172 // a copy SP, so in 64-bit it's a biased value. The bias
173 // is added and removed as needed in the frame code.
174 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
175 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
176 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
177 #endif /* CC_INTERP */
179 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
180 // the interpreter code. If Lscratch2 needs to be used for some
181 // purpose than LcpoolCache should be restore after that for
182 // the interpreter to work right
183 // (These assignments must be compatible with L7_thread_cache; see above.)
185 // Since Lbcp points into the middle of the method object,
186 // it is temporarily converted into a "bcx" during GC.
188 // Exception processing
189 // These registers are passed into exception handlers.
190 // All exception handlers require the exception object being thrown.
191 // In addition, an nmethod's exception handler must be passed
192 // the address of the call site within the nmethod, to allow
193 // proper selection of the applicable catch block.
194 // (Interpreter frames use their own bcp() for this purpose.)
195 //
196 // The Oissuing_pc value is not always needed. When jumping to a
197 // handler that is known to be interpreted, the Oissuing_pc value can be
198 // omitted. An actual catch block in compiled code receives (from its
199 // nmethod's exception handler) the thrown exception in the Oexception,
200 // but it doesn't need the Oissuing_pc.
201 //
202 // If an exception handler (either interpreted or compiled)
203 // discovers there is no applicable catch block, it updates
204 // the Oissuing_pc to the continuation PC of its own caller,
205 // pops back to that caller's stack frame, and executes that
206 // caller's exception handler. Obviously, this process will
207 // iterate until the control stack is popped back to a method
208 // containing an applicable catch block. A key invariant is
209 // that the Oissuing_pc value is always a value local to
210 // the method whose exception handler is currently executing.
211 //
212 // Note: The issuing PC value is __not__ a raw return address (I7 value).
213 // It is a "return pc", the address __following__ the call.
214 // Raw return addresses are converted to issuing PCs by frame::pc(),
215 // or by stubs. Issuing PCs can be used directly with PC range tables.
216 //
217 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
218 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
221 // These must occur after the declarations above
222 #ifndef DONT_USE_REGISTER_DEFINES
224 #define Gthread AS_REGISTER(Register, Gthread)
225 #define Gmethod AS_REGISTER(Register, Gmethod)
226 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
227 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
228 #define Gargs AS_REGISTER(Register, Gargs)
229 #define Lthread_cache AS_REGISTER(Register, Lthread_cache)
230 #define Gframe_size AS_REGISTER(Register, Gframe_size)
231 #define Gtemp AS_REGISTER(Register, Gtemp)
233 #ifdef CC_INTERP
234 #define Lstate AS_REGISTER(Register, Lstate)
235 #define Lesp AS_REGISTER(Register, Lesp)
236 #define L1_scratch AS_REGISTER(Register, L1_scratch)
237 #define Lmirror AS_REGISTER(Register, Lmirror)
238 #define L2_scratch AS_REGISTER(Register, L2_scratch)
239 #define L3_scratch AS_REGISTER(Register, L3_scratch)
240 #define L4_scratch AS_REGISTER(Register, L4_scratch)
241 #define Lscratch AS_REGISTER(Register, Lscratch)
242 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
243 #define L7_scratch AS_REGISTER(Register, L7_scratch)
244 #define Ostate AS_REGISTER(Register, Ostate)
245 #else
246 #define Lesp AS_REGISTER(Register, Lesp)
247 #define Lbcp AS_REGISTER(Register, Lbcp)
248 #define Lmethod AS_REGISTER(Register, Lmethod)
249 #define Llocals AS_REGISTER(Register, Llocals)
250 #define Lmonitors AS_REGISTER(Register, Lmonitors)
251 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
252 #define Lscratch AS_REGISTER(Register, Lscratch)
253 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
254 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
255 #endif /* ! CC_INTERP */
257 #define Lentry_args AS_REGISTER(Register, Lentry_args)
258 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
259 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
260 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
261 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
262 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
264 #define Oexception AS_REGISTER(Register, Oexception)
265 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
268 #endif
270 // Address is an abstraction used to represent a memory location.
271 //
272 // Note: A register location is represented via a Register, not
273 // via an address for efficiency & simplicity reasons.
275 class Address VALUE_OBJ_CLASS_SPEC {
276 private:
277 Register _base; // Base register.
278 RegisterOrConstant _index_or_disp; // Index register or constant displacement.
279 RelocationHolder _rspec;
281 public:
282 Address() : _base(noreg), _index_or_disp(noreg) {}
284 Address(Register base, RegisterOrConstant index_or_disp)
285 : _base(base),
286 _index_or_disp(index_or_disp) {
287 }
289 Address(Register base, Register index)
290 : _base(base),
291 _index_or_disp(index) {
292 }
294 Address(Register base, int disp)
295 : _base(base),
296 _index_or_disp(disp) {
297 }
299 #ifdef ASSERT
300 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
301 Address(Register base, ByteSize disp)
302 : _base(base),
303 _index_or_disp(in_bytes(disp)) {
304 }
305 #endif
307 // accessors
308 Register base() const { return _base; }
309 Register index() const { return _index_or_disp.as_register(); }
310 int disp() const { return _index_or_disp.as_constant(); }
312 bool has_index() const { return _index_or_disp.is_register(); }
313 bool has_disp() const { return _index_or_disp.is_constant(); }
315 const relocInfo::relocType rtype() { return _rspec.type(); }
316 const RelocationHolder& rspec() { return _rspec; }
318 RelocationHolder rspec(int offset) const {
319 return offset == 0 ? _rspec : _rspec.plus(offset);
320 }
322 inline bool is_simm13(int offset = 0); // check disp+offset for overflow
324 Address plus_disp(int plusdisp) const { // bump disp by a small amount
325 assert(_index_or_disp.is_constant(), "must have a displacement");
326 Address a(base(), disp() + plusdisp);
327 return a;
328 }
330 Address after_save() const {
331 Address a = (*this);
332 a._base = a._base->after_save();
333 return a;
334 }
336 Address after_restore() const {
337 Address a = (*this);
338 a._base = a._base->after_restore();
339 return a;
340 }
342 // Convert the raw encoding form into the form expected by the
343 // constructor for Address.
344 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
346 friend class Assembler;
347 };
350 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
351 private:
352 address _address;
353 RelocationHolder _rspec;
355 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
356 switch (rtype) {
357 case relocInfo::external_word_type:
358 return external_word_Relocation::spec(addr);
359 case relocInfo::internal_word_type:
360 return internal_word_Relocation::spec(addr);
361 #ifdef _LP64
362 case relocInfo::opt_virtual_call_type:
363 return opt_virtual_call_Relocation::spec();
364 case relocInfo::static_call_type:
365 return static_call_Relocation::spec();
366 case relocInfo::runtime_call_type:
367 return runtime_call_Relocation::spec();
368 #endif
369 case relocInfo::none:
370 return RelocationHolder();
371 default:
372 ShouldNotReachHere();
373 return RelocationHolder();
374 }
375 }
377 protected:
378 // creation
379 AddressLiteral() : _address(NULL), _rspec(NULL) {}
381 public:
382 AddressLiteral(address addr, RelocationHolder const& rspec)
383 : _address(addr),
384 _rspec(rspec) {}
386 // Some constructors to avoid casting at the call site.
387 AddressLiteral(jobject obj, RelocationHolder const& rspec)
388 : _address((address) obj),
389 _rspec(rspec) {}
391 AddressLiteral(intptr_t value, RelocationHolder const& rspec)
392 : _address((address) value),
393 _rspec(rspec) {}
395 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
396 : _address((address) addr),
397 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
399 // Some constructors to avoid casting at the call site.
400 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
401 : _address((address) addr),
402 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
404 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
405 : _address((address) addr),
406 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
408 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
409 : _address((address) addr),
410 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
412 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
413 : _address((address) addr),
414 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
416 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
417 : _address((address) addr),
418 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
420 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
421 : _address((address) addr),
422 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
424 #ifdef _LP64
425 // 32-bit complains about a multiple declaration for int*.
426 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
427 : _address((address) addr),
428 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
429 #endif
431 AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none)
432 : _address((address) addr),
433 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
435 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
436 : _address((address) addr),
437 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
439 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
440 : _address((address) addr),
441 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
443 intptr_t value() const { return (intptr_t) _address; }
444 int low10() const;
446 const relocInfo::relocType rtype() const { return _rspec.type(); }
447 const RelocationHolder& rspec() const { return _rspec; }
449 RelocationHolder rspec(int offset) const {
450 return offset == 0 ? _rspec : _rspec.plus(offset);
451 }
452 };
455 inline Address RegisterImpl::address_in_saved_window() const {
456 return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
457 }
461 // Argument is an abstraction used to represent an outgoing
462 // actual argument or an incoming formal parameter, whether
463 // it resides in memory or in a register, in a manner consistent
464 // with the SPARC Application Binary Interface, or ABI. This is
465 // often referred to as the native or C calling convention.
467 class Argument VALUE_OBJ_CLASS_SPEC {
468 private:
469 int _number;
470 bool _is_in;
472 public:
473 #ifdef _LP64
474 enum {
475 n_register_parameters = 6, // only 6 registers may contain integer parameters
476 n_float_register_parameters = 16 // Can have up to 16 floating registers
477 };
478 #else
479 enum {
480 n_register_parameters = 6 // only 6 registers may contain integer parameters
481 };
482 #endif
484 // creation
485 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
487 int number() const { return _number; }
488 bool is_in() const { return _is_in; }
489 bool is_out() const { return !is_in(); }
491 Argument successor() const { return Argument(number() + 1, is_in()); }
492 Argument as_in() const { return Argument(number(), true ); }
493 Argument as_out() const { return Argument(number(), false); }
495 // locating register-based arguments:
496 bool is_register() const { return _number < n_register_parameters; }
498 #ifdef _LP64
499 // locating Floating Point register-based arguments:
500 bool is_float_register() const { return _number < n_float_register_parameters; }
502 FloatRegister as_float_register() const {
503 assert(is_float_register(), "must be a register argument");
504 return as_FloatRegister(( number() *2 ) + 1);
505 }
506 FloatRegister as_double_register() const {
507 assert(is_float_register(), "must be a register argument");
508 return as_FloatRegister(( number() *2 ));
509 }
510 #endif
512 Register as_register() const {
513 assert(is_register(), "must be a register argument");
514 return is_in() ? as_iRegister(number()) : as_oRegister(number());
515 }
517 // locating memory-based arguments
518 Address as_address() const {
519 assert(!is_register(), "must be a memory argument");
520 return address_in_frame();
521 }
523 // When applied to a register-based argument, give the corresponding address
524 // into the 6-word area "into which callee may store register arguments"
525 // (This is a different place than the corresponding register-save area location.)
526 Address address_in_frame() const;
528 // debugging
529 const char* name() const;
531 friend class Assembler;
532 };
535 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
536 // level; i.e., what you write
537 // is what you get. The Assembler is generating code into a CodeBuffer.
539 class Assembler : public AbstractAssembler {
540 protected:
542 static void print_instruction(int inst);
543 static int patched_branch(int dest_pos, int inst, int inst_pos);
544 static int branch_destination(int inst, int pos);
547 friend class AbstractAssembler;
548 friend class AddressLiteral;
550 // code patchers need various routines like inv_wdisp()
551 friend class NativeInstruction;
552 friend class NativeGeneralJump;
553 friend class Relocation;
554 friend class Label;
556 public:
557 // op carries format info; see page 62 & 267
559 enum ops {
560 call_op = 1, // fmt 1
561 branch_op = 0, // also sethi (fmt2)
562 arith_op = 2, // fmt 3, arith & misc
563 ldst_op = 3 // fmt 3, load/store
564 };
566 enum op2s {
567 bpr_op2 = 3,
568 fb_op2 = 6,
569 fbp_op2 = 5,
570 br_op2 = 2,
571 bp_op2 = 1,
572 cb_op2 = 7, // V8
573 sethi_op2 = 4
574 };
576 enum op3s {
577 // selected op3s
578 add_op3 = 0x00,
579 and_op3 = 0x01,
580 or_op3 = 0x02,
581 xor_op3 = 0x03,
582 sub_op3 = 0x04,
583 andn_op3 = 0x05,
584 orn_op3 = 0x06,
585 xnor_op3 = 0x07,
586 addc_op3 = 0x08,
587 mulx_op3 = 0x09,
588 umul_op3 = 0x0a,
589 smul_op3 = 0x0b,
590 subc_op3 = 0x0c,
591 udivx_op3 = 0x0d,
592 udiv_op3 = 0x0e,
593 sdiv_op3 = 0x0f,
595 addcc_op3 = 0x10,
596 andcc_op3 = 0x11,
597 orcc_op3 = 0x12,
598 xorcc_op3 = 0x13,
599 subcc_op3 = 0x14,
600 andncc_op3 = 0x15,
601 orncc_op3 = 0x16,
602 xnorcc_op3 = 0x17,
603 addccc_op3 = 0x18,
604 umulcc_op3 = 0x1a,
605 smulcc_op3 = 0x1b,
606 subccc_op3 = 0x1c,
607 udivcc_op3 = 0x1e,
608 sdivcc_op3 = 0x1f,
610 taddcc_op3 = 0x20,
611 tsubcc_op3 = 0x21,
612 taddcctv_op3 = 0x22,
613 tsubcctv_op3 = 0x23,
614 mulscc_op3 = 0x24,
615 sll_op3 = 0x25,
616 sllx_op3 = 0x25,
617 srl_op3 = 0x26,
618 srlx_op3 = 0x26,
619 sra_op3 = 0x27,
620 srax_op3 = 0x27,
621 rdreg_op3 = 0x28,
622 membar_op3 = 0x28,
624 flushw_op3 = 0x2b,
625 movcc_op3 = 0x2c,
626 sdivx_op3 = 0x2d,
627 popc_op3 = 0x2e,
628 movr_op3 = 0x2f,
630 sir_op3 = 0x30,
631 wrreg_op3 = 0x30,
632 saved_op3 = 0x31,
634 fpop1_op3 = 0x34,
635 fpop2_op3 = 0x35,
636 impdep1_op3 = 0x36,
637 impdep2_op3 = 0x37,
638 jmpl_op3 = 0x38,
639 rett_op3 = 0x39,
640 trap_op3 = 0x3a,
641 flush_op3 = 0x3b,
642 save_op3 = 0x3c,
643 restore_op3 = 0x3d,
644 done_op3 = 0x3e,
645 retry_op3 = 0x3e,
647 lduw_op3 = 0x00,
648 ldub_op3 = 0x01,
649 lduh_op3 = 0x02,
650 ldd_op3 = 0x03,
651 stw_op3 = 0x04,
652 stb_op3 = 0x05,
653 sth_op3 = 0x06,
654 std_op3 = 0x07,
655 ldsw_op3 = 0x08,
656 ldsb_op3 = 0x09,
657 ldsh_op3 = 0x0a,
658 ldx_op3 = 0x0b,
660 ldstub_op3 = 0x0d,
661 stx_op3 = 0x0e,
662 swap_op3 = 0x0f,
664 stwa_op3 = 0x14,
665 stxa_op3 = 0x1e,
667 ldf_op3 = 0x20,
668 ldfsr_op3 = 0x21,
669 ldqf_op3 = 0x22,
670 lddf_op3 = 0x23,
671 stf_op3 = 0x24,
672 stfsr_op3 = 0x25,
673 stqf_op3 = 0x26,
674 stdf_op3 = 0x27,
676 prefetch_op3 = 0x2d,
679 ldc_op3 = 0x30,
680 ldcsr_op3 = 0x31,
681 lddc_op3 = 0x33,
682 stc_op3 = 0x34,
683 stcsr_op3 = 0x35,
684 stdcq_op3 = 0x36,
685 stdc_op3 = 0x37,
687 casa_op3 = 0x3c,
688 casxa_op3 = 0x3e,
690 alt_bit_op3 = 0x10,
691 cc_bit_op3 = 0x10
692 };
694 enum opfs {
695 // selected opfs
696 fmovs_opf = 0x01,
697 fmovd_opf = 0x02,
699 fnegs_opf = 0x05,
700 fnegd_opf = 0x06,
702 fadds_opf = 0x41,
703 faddd_opf = 0x42,
704 fsubs_opf = 0x45,
705 fsubd_opf = 0x46,
707 fmuls_opf = 0x49,
708 fmuld_opf = 0x4a,
709 fdivs_opf = 0x4d,
710 fdivd_opf = 0x4e,
712 fcmps_opf = 0x51,
713 fcmpd_opf = 0x52,
715 fstox_opf = 0x81,
716 fdtox_opf = 0x82,
717 fxtos_opf = 0x84,
718 fxtod_opf = 0x88,
719 fitos_opf = 0xc4,
720 fdtos_opf = 0xc6,
721 fitod_opf = 0xc8,
722 fstod_opf = 0xc9,
723 fstoi_opf = 0xd1,
724 fdtoi_opf = 0xd2
725 };
727 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
729 enum Condition {
730 // for FBfcc & FBPfcc instruction
731 f_never = 0,
732 f_notEqual = 1,
733 f_notZero = 1,
734 f_lessOrGreater = 2,
735 f_unorderedOrLess = 3,
736 f_less = 4,
737 f_unorderedOrGreater = 5,
738 f_greater = 6,
739 f_unordered = 7,
740 f_always = 8,
741 f_equal = 9,
742 f_zero = 9,
743 f_unorderedOrEqual = 10,
744 f_greaterOrEqual = 11,
745 f_unorderedOrGreaterOrEqual = 12,
746 f_lessOrEqual = 13,
747 f_unorderedOrLessOrEqual = 14,
748 f_ordered = 15,
750 // V8 coproc, pp 123 v8 manual
752 cp_always = 8,
753 cp_never = 0,
754 cp_3 = 7,
755 cp_2 = 6,
756 cp_2or3 = 5,
757 cp_1 = 4,
758 cp_1or3 = 3,
759 cp_1or2 = 2,
760 cp_1or2or3 = 1,
761 cp_0 = 9,
762 cp_0or3 = 10,
763 cp_0or2 = 11,
764 cp_0or2or3 = 12,
765 cp_0or1 = 13,
766 cp_0or1or3 = 14,
767 cp_0or1or2 = 15,
770 // for integers
772 never = 0,
773 equal = 1,
774 zero = 1,
775 lessEqual = 2,
776 less = 3,
777 lessEqualUnsigned = 4,
778 lessUnsigned = 5,
779 carrySet = 5,
780 negative = 6,
781 overflowSet = 7,
782 always = 8,
783 notEqual = 9,
784 notZero = 9,
785 greater = 10,
786 greaterEqual = 11,
787 greaterUnsigned = 12,
788 greaterEqualUnsigned = 13,
789 carryClear = 13,
790 positive = 14,
791 overflowClear = 15
792 };
794 enum CC {
795 icc = 0, xcc = 2,
796 // ptr_cc is the correct condition code for a pointer or intptr_t:
797 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
798 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
799 };
801 enum PrefetchFcn {
802 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
803 };
805 public:
806 // Helper functions for groups of instructions
808 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
810 enum Membar_mask_bits { // page 184, v9
811 StoreStore = 1 << 3,
812 LoadStore = 1 << 2,
813 StoreLoad = 1 << 1,
814 LoadLoad = 1 << 0,
816 Sync = 1 << 6,
817 MemIssue = 1 << 5,
818 Lookaside = 1 << 4
819 };
821 // test if x is within signed immediate range for nbits
822 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); }
824 // test if -4096 <= x <= 4095
825 static bool is_simm13(int x) { return is_simm(x, 13); }
827 enum ASIs { // page 72, v9
828 ASI_PRIMARY = 0x80,
829 ASI_PRIMARY_LITTLE = 0x88
830 // add more from book as needed
831 };
833 protected:
834 // helpers
836 // x is supposed to fit in a field "nbits" wide
837 // and be sign-extended. Check the range.
839 static void assert_signed_range(intptr_t x, int nbits) {
840 assert( nbits == 32
841 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
842 "value out of range");
843 }
845 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
846 assert( (x & 3) == 0, "not word aligned");
847 assert_signed_range(x, nbits + 2);
848 }
850 static void assert_unsigned_const(int x, int nbits) {
851 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
852 }
854 // fields: note bits numbered from LSB = 0,
855 // fields known by inclusive bit range
857 static int fmask(juint hi_bit, juint lo_bit) {
858 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
859 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
860 }
862 // inverse of u_field
864 static int inv_u_field(int x, int hi_bit, int lo_bit) {
865 juint r = juint(x) >> lo_bit;
866 r &= fmask( hi_bit, lo_bit);
867 return int(r);
868 }
871 // signed version: extract from field and sign-extend
873 static int inv_s_field(int x, int hi_bit, int lo_bit) {
874 int sign_shift = 31 - hi_bit;
875 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
876 }
878 // given a field that ranges from hi_bit to lo_bit (inclusive,
879 // LSB = 0), and an unsigned value for the field,
880 // shift it into the field
882 #ifdef ASSERT
883 static int u_field(int x, int hi_bit, int lo_bit) {
884 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
885 "value out of range");
886 int r = x << lo_bit;
887 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
888 return r;
889 }
890 #else
891 // make sure this is inlined as it will reduce code size significantly
892 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
893 #endif
895 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
896 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
897 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
898 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
900 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
902 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
903 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
904 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
906 static int op( int x) { return u_field(x, 31, 30); }
907 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
908 static int fcn( int x) { return u_field(x, 29, 25); }
909 static int op3( int x) { return u_field(x, 24, 19); }
910 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
911 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
912 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
913 static int cond( int x) { return u_field(x, 28, 25); }
914 static int cond_mov( int x) { return u_field(x, 17, 14); }
915 static int rcond( RCondition x) { return u_field(x, 12, 10); }
916 static int op2( int x) { return u_field(x, 24, 22); }
917 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
918 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
919 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
920 static int imm_asi( int x) { return u_field(x, 12, 5); }
921 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
922 static int opf_low6( int w) { return u_field(w, 10, 5); }
923 static int opf_low5( int w) { return u_field(w, 9, 5); }
924 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
925 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
926 static int opf( int x) { return u_field(x, 13, 5); }
928 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
929 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
931 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
932 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
933 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
935 // some float instructions use this encoding on the op3 field
936 static int alt_op3(int op, FloatRegisterImpl::Width w) {
937 int r;
938 switch(w) {
939 case FloatRegisterImpl::S: r = op + 0; break;
940 case FloatRegisterImpl::D: r = op + 3; break;
941 case FloatRegisterImpl::Q: r = op + 2; break;
942 default: ShouldNotReachHere(); break;
943 }
944 return op3(r);
945 }
948 // compute inverse of simm
949 static int inv_simm(int x, int nbits) {
950 return (int)(x << (32 - nbits)) >> (32 - nbits);
951 }
953 static int inv_simm13( int x ) { return inv_simm(x, 13); }
955 // signed immediate, in low bits, nbits long
956 static int simm(int x, int nbits) {
957 assert_signed_range(x, nbits);
958 return x & (( 1 << nbits ) - 1);
959 }
961 // compute inverse of wdisp16
962 static intptr_t inv_wdisp16(int x, intptr_t pos) {
963 int lo = x & (( 1 << 14 ) - 1);
964 int hi = (x >> 20) & 3;
965 if (hi >= 2) hi |= ~1;
966 return (((hi << 14) | lo) << 2) + pos;
967 }
969 // word offset, 14 bits at LSend, 2 bits at B21, B20
970 static int wdisp16(intptr_t x, intptr_t off) {
971 intptr_t xx = x - off;
972 assert_signed_word_disp_range(xx, 16);
973 int r = (xx >> 2) & ((1 << 14) - 1)
974 | ( ( (xx>>(2+14)) & 3 ) << 20 );
975 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
976 return r;
977 }
980 // word displacement in low-order nbits bits
982 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
983 int pre_sign_extend = x & (( 1 << nbits ) - 1);
984 int r = pre_sign_extend >= ( 1 << (nbits-1) )
985 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
986 : pre_sign_extend;
987 return (r << 2) + pos;
988 }
990 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
991 intptr_t xx = x - off;
992 assert_signed_word_disp_range(xx, nbits);
993 int r = (xx >> 2) & (( 1 << nbits ) - 1);
994 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
995 return r;
996 }
999 // Extract the top 32 bits in a 64 bit word
1000 static int32_t hi32( int64_t x ) {
1001 int32_t r = int32_t( (uint64_t)x >> 32 );
1002 return r;
1003 }
1005 // given a sethi instruction, extract the constant, left-justified
1006 static int inv_hi22( int x ) {
1007 return x << 10;
1008 }
1010 // create an imm22 field, given a 32-bit left-justified constant
1011 static int hi22( int x ) {
1012 int r = int( juint(x) >> 10 );
1013 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
1014 return r;
1015 }
1017 // create a low10 __value__ (not a field) for a given a 32-bit constant
1018 static int low10( int x ) {
1019 return x & ((1 << 10) - 1);
1020 }
1022 // instruction only in v9
1023 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
1025 // instruction only in v8
1026 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
1028 // instruction deprecated in v9
1029 static void v9_dep() { } // do nothing for now
1031 // some float instructions only exist for single prec. on v8
1032 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); }
1034 // v8 has no CC field
1035 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
1037 protected:
1038 // Simple delay-slot scheme:
1039 // In order to check the programmer, the assembler keeps track of deley slots.
1040 // It forbids CTIs in delay slots (conservative, but should be OK).
1041 // Also, when putting an instruction into a delay slot, you must say
1042 // asm->delayed()->add(...), in order to check that you don't omit
1043 // delay-slot instructions.
1044 // To implement this, we use a simple FSA
1046 #ifdef ASSERT
1047 #define CHECK_DELAY
1048 #endif
1049 #ifdef CHECK_DELAY
1050 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
1051 #endif
1053 public:
1054 // Tells assembler next instruction must NOT be in delay slot.
1055 // Use at start of multinstruction macros.
1056 void assert_not_delayed() {
1057 // This is a separate overloading to avoid creation of string constants
1058 // in non-asserted code--with some compilers this pollutes the object code.
1059 #ifdef CHECK_DELAY
1060 assert_not_delayed("next instruction should not be a delay slot");
1061 #endif
1062 }
1063 void assert_not_delayed(const char* msg) {
1064 #ifdef CHECK_DELAY
1065 assert(delay_state == no_delay, msg);
1066 #endif
1067 }
1069 protected:
1070 // Delay slot helpers
1071 // cti is called when emitting control-transfer instruction,
1072 // BEFORE doing the emitting.
1073 // Only effective when assertion-checking is enabled.
1074 void cti() {
1075 #ifdef CHECK_DELAY
1076 assert_not_delayed("cti should not be in delay slot");
1077 #endif
1078 }
1080 // called when emitting cti with a delay slot, AFTER emitting
1081 void has_delay_slot() {
1082 #ifdef CHECK_DELAY
1083 assert_not_delayed("just checking");
1084 delay_state = at_delay_slot;
1085 #endif
1086 }
1088 public:
1089 // Tells assembler you know that next instruction is delayed
1090 Assembler* delayed() {
1091 #ifdef CHECK_DELAY
1092 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
1093 delay_state = filling_delay_slot;
1094 #endif
1095 return this;
1096 }
1098 void flush() {
1099 #ifdef CHECK_DELAY
1100 assert ( delay_state == no_delay, "ending code with a delay slot");
1101 #endif
1102 AbstractAssembler::flush();
1103 }
1105 inline void emit_long(int); // shadows AbstractAssembler::emit_long
1106 inline void emit_data(int x) { emit_long(x); }
1107 inline void emit_data(int, RelocationHolder const&);
1108 inline void emit_data(int, relocInfo::relocType rtype);
1109 // helper for above fcns
1110 inline void check_delay();
1113 public:
1114 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1116 // pp 135 (addc was addx in v8)
1118 inline void add(Register s1, Register s2, Register d );
1119 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1120 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1121 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1122 inline void add(const Address& a, Register d, int offset = 0) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
1124 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1125 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1126 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
1127 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1128 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1129 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1131 // pp 136
1133 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1134 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
1136 protected: // use MacroAssembler::br instead
1138 // pp 138
1140 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1141 inline void fb( Condition c, bool a, Label& L );
1143 // pp 141
1145 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1146 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1148 public:
1150 // pp 144
1152 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1153 inline void br( Condition c, bool a, Label& L );
1155 // pp 146
1157 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1158 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1160 // pp 121 (V8)
1162 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1163 inline void cb( Condition c, bool a, Label& L );
1165 // pp 149
1167 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1168 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
1170 // pp 150
1172 // These instructions compare the contents of s2 with the contents of
1173 // memory at address in s1. If the values are equal, the contents of memory
1174 // at address s1 is swapped with the data in d. If the values are not equal,
1175 // the the contents of memory at s1 is loaded into d, without the swap.
1177 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1178 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1180 // pp 152
1182 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
1183 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1184 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
1185 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1186 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1187 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1188 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1189 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1191 // pp 155
1193 void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
1194 void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
1196 // pp 156
1198 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
1199 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
1201 // pp 157
1203 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
1204 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
1206 // pp 159
1208 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
1209 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
1211 // pp 160
1213 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
1215 // pp 161
1217 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
1218 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
1220 // pp 162
1222 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
1224 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
1226 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
1227 // on v8 to do negation of single, double and quad precision floats.
1229 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); }
1231 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
1233 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
1234 // on v8 to do abs operation on single/double/quad precision floats.
1236 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
1238 // pp 163
1240 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
1241 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
1242 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
1244 // pp 164
1246 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
1248 // pp 165
1250 inline void flush( Register s1, Register s2 );
1251 inline void flush( Register s1, int simm13a);
1253 // pp 167
1255 void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); }
1257 // pp 168
1259 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
1260 // v8 unimp == illtrap(0)
1262 // pp 169
1264 void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
1265 void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
1267 // pp 149 (v8)
1269 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1270 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1272 // pp 170
1274 void jmpl( Register s1, Register s2, Register d );
1275 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1277 // 171
1279 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
1280 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
1281 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
1283 inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
1286 inline void ldfsr( Register s1, Register s2 );
1287 inline void ldfsr( Register s1, int simm13a);
1288 inline void ldxfsr( Register s1, Register s2 );
1289 inline void ldxfsr( Register s1, int simm13a);
1291 // pp 94 (v8)
1293 inline void ldc( Register s1, Register s2, int crd );
1294 inline void ldc( Register s1, int simm13a, int crd);
1295 inline void lddc( Register s1, Register s2, int crd );
1296 inline void lddc( Register s1, int simm13a, int crd);
1297 inline void ldcsr( Register s1, Register s2, int crd );
1298 inline void ldcsr( Register s1, int simm13a, int crd);
1301 // 173
1303 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1304 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1306 // pp 175, lduw is ld on v8
1308 inline void ldsb( Register s1, Register s2, Register d );
1309 inline void ldsb( Register s1, int simm13a, Register d);
1310 inline void ldsh( Register s1, Register s2, Register d );
1311 inline void ldsh( Register s1, int simm13a, Register d);
1312 inline void ldsw( Register s1, Register s2, Register d );
1313 inline void ldsw( Register s1, int simm13a, Register d);
1314 inline void ldub( Register s1, Register s2, Register d );
1315 inline void ldub( Register s1, int simm13a, Register d);
1316 inline void lduh( Register s1, Register s2, Register d );
1317 inline void lduh( Register s1, int simm13a, Register d);
1318 inline void lduw( Register s1, Register s2, Register d );
1319 inline void lduw( Register s1, int simm13a, Register d);
1320 inline void ldx( Register s1, Register s2, Register d );
1321 inline void ldx( Register s1, int simm13a, Register d);
1322 inline void ld( Register s1, Register s2, Register d );
1323 inline void ld( Register s1, int simm13a, Register d);
1324 inline void ldd( Register s1, Register s2, Register d );
1325 inline void ldd( Register s1, int simm13a, Register d);
1327 #ifdef ASSERT
1328 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1329 inline void ld( Register s1, ByteSize simm13a, Register d);
1330 #endif
1332 inline void ldsb(const Address& a, Register d, int offset = 0);
1333 inline void ldsh(const Address& a, Register d, int offset = 0);
1334 inline void ldsw(const Address& a, Register d, int offset = 0);
1335 inline void ldub(const Address& a, Register d, int offset = 0);
1336 inline void lduh(const Address& a, Register d, int offset = 0);
1337 inline void lduw(const Address& a, Register d, int offset = 0);
1338 inline void ldx( const Address& a, Register d, int offset = 0);
1339 inline void ld( const Address& a, Register d, int offset = 0);
1340 inline void ldd( const Address& a, Register d, int offset = 0);
1342 inline void ldub( Register s1, RegisterOrConstant s2, Register d );
1343 inline void ldsb( Register s1, RegisterOrConstant s2, Register d );
1344 inline void lduh( Register s1, RegisterOrConstant s2, Register d );
1345 inline void ldsh( Register s1, RegisterOrConstant s2, Register d );
1346 inline void lduw( Register s1, RegisterOrConstant s2, Register d );
1347 inline void ldsw( Register s1, RegisterOrConstant s2, Register d );
1348 inline void ldx( Register s1, RegisterOrConstant s2, Register d );
1349 inline void ld( Register s1, RegisterOrConstant s2, Register d );
1350 inline void ldd( Register s1, RegisterOrConstant s2, Register d );
1352 // pp 177
1354 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1355 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1356 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1357 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1358 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1359 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1360 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1361 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1362 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1363 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1364 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1365 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1366 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1367 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1368 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1369 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1371 // pp 179
1373 inline void ldstub( Register s1, Register s2, Register d );
1374 inline void ldstub( Register s1, int simm13a, Register d);
1376 // pp 180
1378 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1379 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1381 // pp 181
1383 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1384 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1385 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1386 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1387 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1388 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1389 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1390 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1391 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1392 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1393 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1394 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1395 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1396 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1397 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1398 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1399 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1400 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1401 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1402 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1403 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1404 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1405 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1406 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1408 // pp 183
1410 void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
1412 // pp 185
1414 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
1416 // pp 189
1418 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
1420 // pp 191
1422 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
1423 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
1425 // pp 195
1427 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
1428 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
1430 // pp 196
1432 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1433 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1434 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1435 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1436 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1437 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1439 // pp 197
1441 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1442 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1443 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1444 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1445 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1446 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1447 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1448 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1450 // pp 199
1452 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
1453 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1455 // pp 201
1457 void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
1460 // pp 202
1462 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1463 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1465 // pp 203
1467 void prefetch( Register s1, Register s2, PrefetchFcn f);
1468 void prefetch( Register s1, int simm13a, PrefetchFcn f);
1469 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1470 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1472 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
1474 // pp 208
1476 // not implementing read privileged register
1478 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1479 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1480 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1481 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1482 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1483 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1485 // pp 213
1487 inline void rett( Register s1, Register s2);
1488 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1490 // pp 214
1492 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1493 void save( Register s1, int simm13a, Register d ) {
1494 // make sure frame is at least large enough for the register save area
1495 assert(-simm13a >= 16 * wordSize, "frame too small");
1496 emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1497 }
1499 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1500 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1502 // pp 216
1504 void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
1505 void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
1507 // pp 217
1509 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1510 // pp 218
1512 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1513 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1514 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1515 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1516 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1517 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1519 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1520 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1521 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1522 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1523 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1524 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1526 // pp 220
1528 void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1530 // pp 221
1532 void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1534 // pp 222
1536 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
1537 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1538 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1539 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
1541 inline void stfsr( Register s1, Register s2 );
1542 inline void stfsr( Register s1, int simm13a);
1543 inline void stxfsr( Register s1, Register s2 );
1544 inline void stxfsr( Register s1, int simm13a);
1546 // pp 224
1548 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1549 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1551 // p 226
1553 inline void stb( Register d, Register s1, Register s2 );
1554 inline void stb( Register d, Register s1, int simm13a);
1555 inline void sth( Register d, Register s1, Register s2 );
1556 inline void sth( Register d, Register s1, int simm13a);
1557 inline void stw( Register d, Register s1, Register s2 );
1558 inline void stw( Register d, Register s1, int simm13a);
1559 inline void st( Register d, Register s1, Register s2 );
1560 inline void st( Register d, Register s1, int simm13a);
1561 inline void stx( Register d, Register s1, Register s2 );
1562 inline void stx( Register d, Register s1, int simm13a);
1563 inline void std( Register d, Register s1, Register s2 );
1564 inline void std( Register d, Register s1, int simm13a);
1566 #ifdef ASSERT
1567 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1568 inline void st( Register d, Register s1, ByteSize simm13a);
1569 #endif
1571 inline void stb( Register d, const Address& a, int offset = 0 );
1572 inline void sth( Register d, const Address& a, int offset = 0 );
1573 inline void stw( Register d, const Address& a, int offset = 0 );
1574 inline void stx( Register d, const Address& a, int offset = 0 );
1575 inline void st( Register d, const Address& a, int offset = 0 );
1576 inline void std( Register d, const Address& a, int offset = 0 );
1578 inline void stb( Register d, Register s1, RegisterOrConstant s2 );
1579 inline void sth( Register d, Register s1, RegisterOrConstant s2 );
1580 inline void stw( Register d, Register s1, RegisterOrConstant s2 );
1581 inline void stx( Register d, Register s1, RegisterOrConstant s2 );
1582 inline void std( Register d, Register s1, RegisterOrConstant s2 );
1583 inline void st( Register d, Register s1, RegisterOrConstant s2 );
1585 // pp 177
1587 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1588 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1589 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1590 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1591 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1592 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1593 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1594 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1595 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1596 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1598 // pp 97 (v8)
1600 inline void stc( int crd, Register s1, Register s2 );
1601 inline void stc( int crd, Register s1, int simm13a);
1602 inline void stdc( int crd, Register s1, Register s2 );
1603 inline void stdc( int crd, Register s1, int simm13a);
1604 inline void stcsr( int crd, Register s1, Register s2 );
1605 inline void stcsr( int crd, Register s1, int simm13a);
1606 inline void stdcq( int crd, Register s1, Register s2 );
1607 inline void stdcq( int crd, Register s1, int simm13a);
1609 // pp 230
1611 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1612 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1613 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1614 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1615 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1616 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1617 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1618 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1620 // pp 231
1622 inline void swap( Register s1, Register s2, Register d );
1623 inline void swap( Register s1, int simm13a, Register d);
1624 inline void swap( Address& a, Register d, int offset = 0 );
1626 // pp 232
1628 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1629 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1631 // pp 234, note op in book is wrong, see pp 268
1633 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1634 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1635 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1636 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1638 // pp 235
1640 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1641 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1642 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1643 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1645 // pp 237
1647 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1648 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1649 // simple uncond. trap
1650 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1652 // pp 239 omit write priv register for now
1654 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1655 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1656 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
1657 rs1(s) |
1658 op3(wrreg_op3) |
1659 u_field(2, 29, 25) |
1660 u_field(1, 13, 13) |
1661 simm(simm13a, 13)); }
1662 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1663 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1665 // For a given register condition, return the appropriate condition code
1666 // Condition (the one you would use to get the same effect after "tst" on
1667 // the target register.)
1668 Assembler::Condition reg_cond_to_cc_cond(RCondition in);
1671 // Creation
1672 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1673 #ifdef CHECK_DELAY
1674 delay_state = no_delay;
1675 #endif
1676 }
1678 // Testing
1679 #ifndef PRODUCT
1680 void test_v9();
1681 void test_v8_onlys();
1682 #endif
1683 };
1686 class RegistersForDebugging : public StackObj {
1687 public:
1688 intptr_t i[8], l[8], o[8], g[8];
1689 float f[32];
1690 double d[32];
1692 void print(outputStream* s);
1694 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
1695 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
1696 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
1697 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
1698 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
1699 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
1701 // gen asm code to save regs
1702 static void save_registers(MacroAssembler* a);
1704 // restore global registers in case C code disturbed them
1705 static void restore_registers(MacroAssembler* a, Register r);
1708 };
1711 // MacroAssembler extends Assembler by a few frequently used macros.
1712 //
1713 // Most of the standard SPARC synthetic ops are defined here.
1714 // Instructions for which a 'better' code sequence exists depending
1715 // on arguments should also go in here.
1717 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
1718 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
1719 #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__)
1720 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
1723 class MacroAssembler: public Assembler {
1724 protected:
1725 // Support for VM calls
1726 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1727 // may customize this version by overriding it for its purposes (e.g., to save/restore
1728 // additional registers when doing a VM call).
1729 #ifdef CC_INTERP
1730 #define VIRTUAL
1731 #else
1732 #define VIRTUAL virtual
1733 #endif
1735 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
1737 //
1738 // It is imperative that all calls into the VM are handled via the call_VM macros.
1739 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1740 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1741 //
1742 // This is the base routine called by the different versions of call_VM. The interpreter
1743 // may customize this version by overriding it for its purposes (e.g., to save/restore
1744 // additional registers when doing a VM call).
1745 //
1746 // A non-volatile java_thread_cache register should be specified so
1747 // that the G2_thread value can be preserved across the call.
1748 // (If java_thread_cache is noreg, then a slow get_thread call
1749 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
1750 // thread.
1751 //
1752 // If no last_java_sp is specified (noreg) than SP will be used instead.
1754 virtual void call_VM_base(
1755 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1756 Register java_thread_cache, // the thread if computed before ; use noreg otherwise
1757 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1758 address entry_point, // the entry point
1759 int number_of_arguments, // the number of arguments (w/o thread) to pop after call
1760 bool check_exception=true // flag which indicates if exception should be checked
1761 );
1763 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1764 // The implementation is only non-empty for the InterpreterMacroAssembler,
1765 // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
1766 virtual void check_and_handle_popframe(Register scratch_reg);
1767 virtual void check_and_handle_earlyret(Register scratch_reg);
1769 public:
1770 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1772 // Support for NULL-checks
1773 //
1774 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1775 // If the accessed location is M[reg + offset] and the offset is known, provide the
1776 // offset. No explicit code generation is needed if the offset is within a certain
1777 // range (0 <= offset <= page_size).
1778 //
1779 // %%%%%% Currently not done for SPARC
1781 void null_check(Register reg, int offset = -1);
1782 static bool needs_explicit_null_check(intptr_t offset);
1784 // support for delayed instructions
1785 MacroAssembler* delayed() { Assembler::delayed(); return this; }
1787 // branches that use right instruction for v8 vs. v9
1788 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1789 inline void br( Condition c, bool a, Predict p, Label& L );
1790 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1791 inline void fb( Condition c, bool a, Predict p, Label& L );
1793 // compares register with zero and branches (V9 and V8 instructions)
1794 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1795 // Compares a pointer register with zero and branches on (not)null.
1796 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1797 void br_null ( Register s1, bool a, Predict p, Label& L );
1798 void br_notnull( Register s1, bool a, Predict p, Label& L );
1800 // These versions will do the most efficient thing on v8 and v9. Perhaps
1801 // this is what the routine above was meant to do, but it didn't (and
1802 // didn't cover both target address kinds.)
1803 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1804 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1806 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1807 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1809 // Branch that tests xcc in LP64 and icc in !LP64
1810 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1811 inline void brx( Condition c, bool a, Predict p, Label& L );
1813 // unconditional short branch
1814 inline void ba( bool a, Label& L );
1816 // Branch that tests fp condition codes
1817 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1818 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1820 // get PC the best way
1821 inline int get_pc( Register d );
1823 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1824 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1825 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1827 inline void jmp( Register s1, Register s2 );
1828 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1830 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1831 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
1832 inline void callr( Register s1, Register s2 );
1833 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1835 // Emits nothing on V8
1836 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
1837 inline void iprefetch( Label& L);
1839 inline void tst( Register s ) { orcc( G0, s, G0 ); }
1841 #ifdef PRODUCT
1842 inline void ret( bool trace = TraceJumps ) { if (trace) {
1843 mov(I7, O7); // traceable register
1844 JMP(O7, 2 * BytesPerInstWord);
1845 } else {
1846 jmpl( I7, 2 * BytesPerInstWord, G0 );
1847 }
1848 }
1850 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
1851 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
1852 #else
1853 void ret( bool trace = TraceJumps );
1854 void retl( bool trace = TraceJumps );
1855 #endif /* PRODUCT */
1857 // Required platform-specific helpers for Label::patch_instructions.
1858 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1859 void pd_patch_instruction(address branch, address target);
1860 #ifndef PRODUCT
1861 static void pd_print_patched_instruction(address branch);
1862 #endif
1864 // sethi Macro handles optimizations and relocations
1865 private:
1866 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
1867 public:
1868 void sethi(const AddressLiteral& addrlit, Register d);
1869 void patchable_sethi(const AddressLiteral& addrlit, Register d);
1871 // compute the size of a sethi/set
1872 static int size_of_sethi( address a, bool worst_case = false );
1873 static int worst_case_size_of_set();
1875 // set may be either setsw or setuw (high 32 bits may be zero or sign)
1876 private:
1877 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
1878 public:
1879 void set(const AddressLiteral& addrlit, Register d);
1880 void set(intptr_t value, Register d);
1881 void set(address addr, Register d, RelocationHolder const& rspec);
1882 void patchable_set(const AddressLiteral& addrlit, Register d);
1883 void patchable_set(intptr_t value, Register d);
1884 void set64(jlong value, Register d, Register tmp);
1886 // sign-extend 32 to 64
1887 inline void signx( Register s, Register d ) { sra( s, G0, d); }
1888 inline void signx( Register d ) { sra( d, G0, d); }
1890 inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
1891 inline void not1( Register d ) { xnor( d, G0, d ); }
1893 inline void neg( Register s, Register d ) { sub( G0, s, d ); }
1894 inline void neg( Register d ) { sub( G0, d, d ); }
1896 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
1897 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
1898 // Functions for isolating 64 bit atomic swaps for LP64
1899 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
1900 inline void cas_ptr( Register s1, Register s2, Register d) {
1901 #ifdef _LP64
1902 casx( s1, s2, d );
1903 #else
1904 cas( s1, s2, d );
1905 #endif
1906 }
1908 // Functions for isolating 64 bit shifts for LP64
1909 inline void sll_ptr( Register s1, Register s2, Register d );
1910 inline void sll_ptr( Register s1, int imm6a, Register d );
1911 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
1912 inline void srl_ptr( Register s1, Register s2, Register d );
1913 inline void srl_ptr( Register s1, int imm6a, Register d );
1915 // little-endian
1916 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
1917 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
1919 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
1920 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
1922 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
1923 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
1925 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
1926 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
1928 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
1929 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
1931 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
1932 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
1934 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
1935 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
1937 inline void clr( Register d ) { or3( G0, G0, d ); }
1939 inline void clrb( Register s1, Register s2);
1940 inline void clrh( Register s1, Register s2);
1941 inline void clr( Register s1, Register s2);
1942 inline void clrx( Register s1, Register s2);
1944 inline void clrb( Register s1, int simm13a);
1945 inline void clrh( Register s1, int simm13a);
1946 inline void clr( Register s1, int simm13a);
1947 inline void clrx( Register s1, int simm13a);
1949 // copy & clear upper word
1950 inline void clruw( Register s, Register d ) { srl( s, G0, d); }
1951 // clear upper word
1952 inline void clruwu( Register d ) { srl( d, G0, d); }
1954 // membar psuedo instruction. takes into account target memory model.
1955 inline void membar( Assembler::Membar_mask_bits const7a );
1957 // returns if membar generates anything.
1958 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
1960 // mov pseudo instructions
1961 inline void mov( Register s, Register d) {
1962 if ( s != d ) or3( G0, s, d);
1963 else assert_not_delayed(); // Put something useful in the delay slot!
1964 }
1966 inline void mov_or_nop( Register s, Register d) {
1967 if ( s != d ) or3( G0, s, d);
1968 else nop();
1969 }
1971 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
1973 // address pseudos: make these names unlike instruction names to avoid confusion
1974 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
1975 inline void load_contents(AddressLiteral& addrlit, Register d, int offset = 0);
1976 inline void load_ptr_contents(AddressLiteral& addrlit, Register d, int offset = 0);
1977 inline void store_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0);
1978 inline void store_ptr_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0);
1979 inline void jumpl_to(AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
1980 inline void jump_to(AddressLiteral& addrlit, Register temp, int offset = 0);
1981 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
1983 // ring buffer traceable jumps
1985 void jmp2( Register r1, Register r2, const char* file, int line );
1986 void jmp ( Register r1, int offset, const char* file, int line );
1988 void jumpl(AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
1989 void jump (AddressLiteral& addrlit, Register temp, int offset, const char* file, int line);
1992 // argument pseudos:
1994 inline void load_argument( Argument& a, Register d );
1995 inline void store_argument( Register s, Argument& a );
1996 inline void store_ptr_argument( Register s, Argument& a );
1997 inline void store_float_argument( FloatRegister s, Argument& a );
1998 inline void store_double_argument( FloatRegister s, Argument& a );
1999 inline void store_long_argument( Register s, Argument& a );
2001 // handy macros:
2003 inline void round_to( Register r, int modulus ) {
2004 assert_not_delayed();
2005 inc( r, modulus - 1 );
2006 and3( r, -modulus, r );
2007 }
2009 // --------------------------------------------------
2011 // Functions for isolating 64 bit loads for LP64
2012 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
2013 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
2014 inline void ld_ptr(Register s1, Register s2, Register d);
2015 inline void ld_ptr(Register s1, int simm13a, Register d);
2016 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
2017 inline void ld_ptr(const Address& a, Register d, int offset = 0);
2018 inline void st_ptr(Register d, Register s1, Register s2);
2019 inline void st_ptr(Register d, Register s1, int simm13a);
2020 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
2021 inline void st_ptr(Register d, const Address& a, int offset = 0);
2023 #ifdef ASSERT
2024 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
2025 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
2026 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
2027 #endif
2029 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
2030 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
2031 inline void ld_long(Register s1, Register s2, Register d);
2032 inline void ld_long(Register s1, int simm13a, Register d);
2033 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
2034 inline void ld_long(const Address& a, Register d, int offset = 0);
2035 inline void st_long(Register d, Register s1, Register s2);
2036 inline void st_long(Register d, Register s1, int simm13a);
2037 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
2038 inline void st_long(Register d, const Address& a, int offset = 0);
2040 // Helpers for address formation.
2041 // They update the dest in place, whether it is a register or constant.
2042 // They emit no code at all if src is a constant zero.
2043 // If dest is a constant and src is a register, the temp argument
2044 // is required, and becomes the result.
2045 // If dest is a register and src is a non-simm13 constant,
2046 // the temp argument is required, and is used to materialize the constant.
2047 void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
2048 Register temp = noreg );
2049 void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
2050 Register temp = noreg );
2052 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) {
2053 guarantee(Rtemp != noreg, "constant offset overflow");
2054 if (is_simm13(roc.constant_or_zero()))
2055 return roc; // register or short constant
2056 set(roc.as_constant(), Rtemp);
2057 return RegisterOrConstant(Rtemp);
2058 }
2060 // --------------------------------------------------
2062 public:
2063 // traps as per trap.h (SPARC ABI?)
2065 void breakpoint_trap();
2066 void breakpoint_trap(Condition c, CC cc = icc);
2067 void flush_windows_trap();
2068 void clean_windows_trap();
2069 void get_psr_trap();
2070 void set_psr_trap();
2072 // V8/V9 flush_windows
2073 void flush_windows();
2075 // Support for serializing memory accesses between threads
2076 void serialize_memory(Register thread, Register tmp1, Register tmp2);
2078 // Stack frame creation/removal
2079 void enter();
2080 void leave();
2082 // V8/V9 integer multiply
2083 void mult(Register s1, Register s2, Register d);
2084 void mult(Register s1, int simm13a, Register d);
2086 // V8/V9 read and write of condition codes.
2087 void read_ccr(Register d);
2088 void write_ccr(Register s);
2090 // Manipulation of C++ bools
2091 // These are idioms to flag the need for care with accessing bools but on
2092 // this platform we assume byte size
2094 inline void stbool(Register d, const Address& a) { stb(d, a); }
2095 inline void ldbool(const Address& a, Register d) { ldsb(a, d); }
2096 inline void tstbool( Register s ) { tst(s); }
2097 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
2099 // klass oop manipulations if compressed
2100 void load_klass(Register src_oop, Register klass);
2101 void store_klass(Register klass, Register dst_oop);
2102 void store_klass_gap(Register s, Register dst_oop);
2104 // oop manipulations
2105 void load_heap_oop(const Address& s, Register d);
2106 void load_heap_oop(Register s1, Register s2, Register d);
2107 void load_heap_oop(Register s1, int simm13a, Register d);
2108 void store_heap_oop(Register d, Register s1, Register s2);
2109 void store_heap_oop(Register d, Register s1, int simm13a);
2110 void store_heap_oop(Register d, const Address& a, int offset = 0);
2112 void encode_heap_oop(Register src, Register dst);
2113 void encode_heap_oop(Register r) {
2114 encode_heap_oop(r, r);
2115 }
2116 void decode_heap_oop(Register src, Register dst);
2117 void decode_heap_oop(Register r) {
2118 decode_heap_oop(r, r);
2119 }
2120 void encode_heap_oop_not_null(Register r);
2121 void decode_heap_oop_not_null(Register r);
2122 void encode_heap_oop_not_null(Register src, Register dst);
2123 void decode_heap_oop_not_null(Register src, Register dst);
2125 // Support for managing the JavaThread pointer (i.e.; the reference to
2126 // thread-local information).
2127 void get_thread(); // load G2_thread
2128 void verify_thread(); // verify G2_thread contents
2129 void save_thread (const Register threache); // save to cache
2130 void restore_thread(const Register thread_cache); // restore from cache
2132 // Support for last Java frame (but use call_VM instead where possible)
2133 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
2134 void reset_last_Java_frame(void);
2136 // Call into the VM.
2137 // Passes the thread pointer (in O0) as a prepended argument.
2138 // Makes sure oop return values are visible to the GC.
2139 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2140 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
2141 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2142 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2144 // these overloadings are not presently used on SPARC:
2145 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2146 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
2147 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2148 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2150 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
2151 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
2152 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
2153 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
2155 void get_vm_result (Register oop_result);
2156 void get_vm_result_2(Register oop_result);
2158 // vm result is currently getting hijacked to for oop preservation
2159 void set_vm_result(Register oop_result);
2161 // if call_VM_base was called with check_exceptions=false, then call
2162 // check_and_forward_exception to handle exceptions when it is safe
2163 void check_and_forward_exception(Register scratch_reg);
2165 private:
2166 // For V8
2167 void read_ccr_trap(Register ccr_save);
2168 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2170 #ifdef ASSERT
2171 // For V8 debugging. Uses V8 instruction sequence and checks
2172 // result with V9 insturctions rdccr and wrccr.
2173 // Uses Gscatch and Gscatch2
2174 void read_ccr_v8_assert(Register ccr_save);
2175 void write_ccr_v8_assert(Register ccr_save);
2176 #endif // ASSERT
2178 public:
2180 // Write to card table for - register is destroyed afterwards.
2181 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2183 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2185 #ifndef SERIALGC
2186 // Array store and offset
2187 void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs);
2189 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2191 // May do filtering, depending on the boolean arguments.
2192 void g1_card_table_write(jbyte* byte_map_base,
2193 Register tmp, Register obj, Register new_val,
2194 bool region_filter, bool null_filter);
2195 #endif // SERIALGC
2197 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2198 void push_fTOS();
2200 // pops double TOS element from CPU stack and pushes on FPU stack
2201 void pop_fTOS();
2203 void empty_FPU_stack();
2205 void push_IU_state();
2206 void pop_IU_state();
2208 void push_FPU_state();
2209 void pop_FPU_state();
2211 void push_CPU_state();
2212 void pop_CPU_state();
2214 // if heap base register is used - reinit it with the correct value
2215 void reinit_heapbase();
2217 // Debugging
2218 void _verify_oop(Register reg, const char * msg, const char * file, int line);
2219 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
2221 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
2222 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
2224 // only if +VerifyOops
2225 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2226 // only if +VerifyFPU
2227 void stop(const char* msg); // prints msg, dumps registers and stops execution
2228 void warn(const char* msg); // prints msg, but don't stop
2229 void untested(const char* what = "");
2230 void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); }
2231 void should_not_reach_here() { stop("should not reach here"); }
2232 void print_CPU_state();
2234 // oops in code
2235 AddressLiteral allocate_oop_address(jobject obj); // allocate_index
2236 AddressLiteral constant_oop_address(jobject obj); // find_index
2237 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address
2238 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address
2239 inline void set_oop (AddressLiteral& obj_addr, Register d); // same as load_address
2241 void set_narrow_oop( jobject obj, Register d );
2243 // nop padding
2244 void align(int modulus);
2246 // declare a safepoint
2247 void safepoint();
2249 // factor out part of stop into subroutine to save space
2250 void stop_subroutine();
2251 // factor out part of verify_oop into subroutine to save space
2252 void verify_oop_subroutine();
2254 // side-door communication with signalHandler in os_solaris.cpp
2255 static address _verify_oop_implicit_branch[3];
2257 #ifndef PRODUCT
2258 static void test();
2259 #endif
2261 // convert an incoming arglist to varargs format; put the pointer in d
2262 void set_varargs( Argument a, Register d );
2264 int total_frame_size_in_bytes(int extraWords);
2266 // used when extraWords known statically
2267 void save_frame(int extraWords);
2268 void save_frame_c1(int size_in_bytes);
2269 // make a frame, and simultaneously pass up one or two register value
2270 // into the new register window
2271 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
2273 // give no. (outgoing) params, calc # of words will need on frame
2274 void calc_mem_param_words(Register Rparam_words, Register Rresult);
2276 // used to calculate frame size dynamically
2277 // result is in bytes and must be negated for save inst
2278 void calc_frame_size(Register extraWords, Register resultReg);
2280 // calc and also save
2281 void calc_frame_size_and_save(Register extraWords, Register resultReg);
2283 static void debug(char* msg, RegistersForDebugging* outWindow);
2285 // implementations of bytecodes used by both interpreter and compiler
2287 void lcmp( Register Ra_hi, Register Ra_low,
2288 Register Rb_hi, Register Rb_low,
2289 Register Rresult);
2291 void lneg( Register Rhi, Register Rlow );
2293 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
2294 Register Rout_high, Register Rout_low, Register Rtemp );
2296 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
2297 Register Rout_high, Register Rout_low, Register Rtemp );
2299 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
2300 Register Rout_high, Register Rout_low, Register Rtemp );
2302 #ifdef _LP64
2303 void lcmp( Register Ra, Register Rb, Register Rresult);
2304 #endif
2306 void float_cmp( bool is_float, int unordered_result,
2307 FloatRegister Fa, FloatRegister Fb,
2308 Register Rresult);
2310 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2311 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
2312 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2313 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2315 void save_all_globals_into_locals();
2316 void restore_globals_from_locals();
2318 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2319 address lock_addr=0, bool use_call_vm=false);
2320 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2321 address lock_addr=0, bool use_call_vm=false);
2322 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2324 // These set the icc condition code to equal if the lock succeeded
2325 // and notEqual if it failed and requires a slow case
2326 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
2327 Register Rscratch,
2328 BiasedLockingCounters* counters = NULL,
2329 bool try_bias = UseBiasedLocking);
2330 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
2331 Register Rscratch,
2332 bool try_bias = UseBiasedLocking);
2334 // Biased locking support
2335 // Upon entry, lock_reg must point to the lock record on the stack,
2336 // obj_reg must contain the target object, and mark_reg must contain
2337 // the target object's header.
2338 // Destroys mark_reg if an attempt is made to bias an anonymously
2339 // biased lock. In this case a failure will go either to the slow
2340 // case or fall through with the notEqual condition code set with
2341 // the expectation that the slow case in the runtime will be called.
2342 // In the fall-through case where the CAS-based lock is done,
2343 // mark_reg is not destroyed.
2344 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
2345 Label& done, Label* slow_case = NULL,
2346 BiasedLockingCounters* counters = NULL);
2347 // Upon entry, the base register of mark_addr must contain the oop.
2348 // Destroys temp_reg.
2350 // If allow_delay_slot_filling is set to true, the next instruction
2351 // emitted after this one will go in an annulled delay slot if the
2352 // biased locking exit case failed.
2353 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2355 // allocation
2356 void eden_allocate(
2357 Register obj, // result: pointer to object after successful allocation
2358 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2359 int con_size_in_bytes, // object size in bytes if known at compile time
2360 Register t1, // temp register
2361 Register t2, // temp register
2362 Label& slow_case // continuation point if fast allocation fails
2363 );
2364 void tlab_allocate(
2365 Register obj, // result: pointer to object after successful allocation
2366 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2367 int con_size_in_bytes, // object size in bytes if known at compile time
2368 Register t1, // temp register
2369 Label& slow_case // continuation point if fast allocation fails
2370 );
2371 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2373 // interface method calling
2374 void lookup_interface_method(Register recv_klass,
2375 Register intf_klass,
2376 RegisterOrConstant itable_index,
2377 Register method_result,
2378 Register temp_reg, Register temp2_reg,
2379 Label& no_such_interface);
2381 // Test sub_klass against super_klass, with fast and slow paths.
2383 // The fast path produces a tri-state answer: yes / no / maybe-slow.
2384 // One of the three labels can be NULL, meaning take the fall-through.
2385 // If super_check_offset is -1, the value is loaded up from super_klass.
2386 // No registers are killed, except temp_reg and temp2_reg.
2387 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
2388 void check_klass_subtype_fast_path(Register sub_klass,
2389 Register super_klass,
2390 Register temp_reg,
2391 Register temp2_reg,
2392 Label* L_success,
2393 Label* L_failure,
2394 Label* L_slow_path,
2395 RegisterOrConstant super_check_offset = RegisterOrConstant(-1),
2396 Register instanceof_hack = noreg);
2398 // The rest of the type check; must be wired to a corresponding fast path.
2399 // It does not repeat the fast path logic, so don't use it standalone.
2400 // The temp_reg can be noreg, if no temps are available.
2401 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
2402 // Updates the sub's secondary super cache as necessary.
2403 void check_klass_subtype_slow_path(Register sub_klass,
2404 Register super_klass,
2405 Register temp_reg,
2406 Register temp2_reg,
2407 Register temp3_reg,
2408 Register temp4_reg,
2409 Label* L_success,
2410 Label* L_failure);
2412 // Simplified, combined version, good for typical uses.
2413 // Falls through on failure.
2414 void check_klass_subtype(Register sub_klass,
2415 Register super_klass,
2416 Register temp_reg,
2417 Register temp2_reg,
2418 Label& L_success);
2420 // method handles (JSR 292)
2421 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2422 Register temp_reg,
2423 Label& wrong_method_type);
2424 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
2425 // offset relative to Gargs of argument at tos[arg_slot].
2426 // (arg_slot == 0 means the last argument, not the first).
2427 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
2428 int extra_slot_offset = 0);
2431 // Stack overflow checking
2433 // Note: this clobbers G3_scratch
2434 void bang_stack_with_offset(int offset) {
2435 // stack grows down, caller passes positive offset
2436 assert(offset > 0, "must bang with negative offset");
2437 set((-offset)+STACK_BIAS, G3_scratch);
2438 st(G0, SP, G3_scratch);
2439 }
2441 // Writes to stack successive pages until offset reached to check for
2442 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
2443 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2445 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
2447 void verify_tlab();
2449 Condition negate_condition(Condition cond);
2451 // Helper functions for statistics gathering.
2452 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
2453 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
2454 // Unconditional increment.
2455 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
2456 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2);
2458 // Compare char[] arrays aligned to 4 bytes.
2459 void char_arrays_equals(Register ary1, Register ary2,
2460 Register limit, Register result,
2461 Register chr1, Register chr2, Label& Ldone);
2463 #undef VIRTUAL
2465 };
2467 /**
2468 * class SkipIfEqual:
2469 *
2470 * Instantiating this class will result in assembly code being output that will
2471 * jump around any code emitted between the creation of the instance and it's
2472 * automatic destruction at the end of a scope block, depending on the value of
2473 * the flag passed to the constructor, which will be checked at run-time.
2474 */
2475 class SkipIfEqual : public StackObj {
2476 private:
2477 MacroAssembler* _masm;
2478 Label _label;
2480 public:
2481 // 'temp' is a temp register that this object can use (and trash)
2482 SkipIfEqual(MacroAssembler*, Register temp,
2483 const bool* flag_addr, Assembler::Condition condition);
2484 ~SkipIfEqual();
2485 };
2487 #ifdef ASSERT
2488 // On RISC, there's no benefit to verifying instruction boundaries.
2489 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
2490 #endif