Thu, 19 Mar 2009 09:13:24 -0700
Merge
1 //
2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
469 %}
471 source %{
472 #define __ _masm.
474 // tertiary op of a LoadP or StoreP encoding
475 #define REGP_OP true
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
479 static Register reg_to_register_object(int register_encoding);
481 // Used by the DFA in dfa_sparc.cpp.
482 // Check for being able to use a V9 branch-on-register. Requires a
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
484 // extended. Doesn't work following an integer ADD, for example, because of
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
487 // replace them with zero, which could become sign-extension in a different OS
488 // release. There's no obvious reason why an interrupt will ever fill these
489 // bits with non-zero junk (the registers are reloaded with standard LD
490 // instructions which either zero-fill or sign-fill).
491 bool can_branch_register( Node *bol, Node *cmp ) {
492 if( !BranchOnRegister ) return false;
493 #ifdef _LP64
494 if( cmp->Opcode() == Op_CmpP )
495 return true; // No problems with pointer compares
496 #endif
497 if( cmp->Opcode() == Op_CmpL )
498 return true; // No problems with long compares
500 if( !SparcV9RegsHiBitsZero ) return false;
501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
502 bol->as_Bool()->_test._test != BoolTest::eq )
503 return false;
505 // Check for comparing against a 'safe' value. Any operation which
506 // clears out the high word is safe. Thus, loads and certain shifts
507 // are safe, as are non-negative constants. Any operation which
508 // preserves zero bits in the high word is safe as long as each of its
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
510 // inputs are safe. At present, the only important case to recognize
511 // seems to be loads. Constants should fold away, and shifts &
512 // logicals can use the 'cc' forms.
513 Node *x = cmp->in(1);
514 if( x->is_Load() ) return true;
515 if( x->is_Phi() ) {
516 for( uint i = 1; i < x->req(); i++ )
517 if( !x->in(i)->is_Load() )
518 return false;
519 return true;
520 }
521 return false;
522 }
524 // ****************************************************************************
526 // REQUIRED FUNCTIONALITY
528 // !!!!! Special hack to get all type of calls to specify the byte offset
529 // from the start of the call to the point where the return address
530 // will point.
531 // The "return address" is the address of the call instruction, plus 8.
533 int MachCallStaticJavaNode::ret_addr_offset() {
534 return NativeCall::instruction_size; // call; delay slot
535 }
537 int MachCallDynamicJavaNode::ret_addr_offset() {
538 int vtable_index = this->_vtable_index;
539 if (vtable_index < 0) {
540 // must be invalid_vtable_index, not nonvirtual_vtable_index
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
542 return (NativeMovConstReg::instruction_size +
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
544 } else {
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
548 int klass_load_size;
549 if (UseCompressedOops) {
550 assert(Universe::heap() != NULL, "java heap should be initialized");
551 if (Universe::narrow_oop_base() == NULL)
552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
553 else
554 klass_load_size = 3*BytesPerInstWord;
555 } else {
556 klass_load_size = 1*BytesPerInstWord;
557 }
558 if( Assembler::is_simm13(v_off) ) {
559 return klass_load_size +
560 (2*BytesPerInstWord + // ld_ptr, ld_ptr
561 NativeCall::instruction_size); // call; delay slot
562 } else {
563 return klass_load_size +
564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
565 NativeCall::instruction_size); // call; delay slot
566 }
567 }
568 }
570 int MachCallRuntimeNode::ret_addr_offset() {
571 #ifdef _LP64
572 return NativeFarCall::instruction_size; // farcall; delay slot
573 #else
574 return NativeCall::instruction_size; // call; delay slot
575 #endif
576 }
578 // Indicate if the safepoint node needs the polling page as an input.
579 // Since Sparc does not have absolute addressing, it does.
580 bool SafePointNode::needs_polling_address_input() {
581 return true;
582 }
584 // emit an interrupt that is caught by the debugger (for debugging compiler)
585 void emit_break(CodeBuffer &cbuf) {
586 MacroAssembler _masm(&cbuf);
587 __ breakpoint_trap();
588 }
590 #ifndef PRODUCT
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
592 st->print("TA");
593 }
594 #endif
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
597 emit_break(cbuf);
598 }
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
601 return MachNode::size(ra_);
602 }
604 // Traceable jump
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
606 MacroAssembler _masm(&cbuf);
607 Register rdest = reg_to_register_object(jump_target);
608 __ JMP(rdest, 0);
609 __ delayed()->nop();
610 }
612 // Traceable jump and set exception pc
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
614 MacroAssembler _masm(&cbuf);
615 Register rdest = reg_to_register_object(jump_target);
616 __ JMP(rdest, 0);
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
618 }
620 void emit_nop(CodeBuffer &cbuf) {
621 MacroAssembler _masm(&cbuf);
622 __ nop();
623 }
625 void emit_illtrap(CodeBuffer &cbuf) {
626 MacroAssembler _masm(&cbuf);
627 __ illtrap(0);
628 }
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
632 assert(n->rule() != loadUB_rule, "");
634 intptr_t offset = 0;
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
636 const Node* addr = n->get_base_and_disp(offset, adr_type);
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
639 assert(addr->bottom_type()->isa_oopptr() == atype, "");
640 atype = atype->add_offset(offset);
641 assert(disp32 == offset, "wrong disp32");
642 return atype->_offset;
643 }
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
649 intptr_t offset = 0;
650 Node* addr = n->in(2);
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
653 Node* a = addr->in(2/*AddPNode::Address*/);
654 Node* o = addr->in(3/*AddPNode::Offset*/);
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
656 atype = a->bottom_type()->is_ptr()->add_offset(offset);
657 assert(atype->isa_oop_ptr(), "still an oop");
658 }
659 offset = atype->is_ptr()->_offset;
660 if (offset != Type::OffsetBot) offset += disp32;
661 return offset;
662 }
664 // Standard Sparc opcode form2 field breakdown
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits
667 int op = (f30 << 30) |
668 (f29 << 29) |
669 (f25 << 25) |
670 (f22 << 22) |
671 (f20 << 20) |
672 (f19 << 19) |
673 (f0 << 0);
674 *((int*)(cbuf.code_end())) = op;
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
676 }
678 // Standard Sparc opcode form2 field breakdown
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
680 f0 >>= 10; // Drop 10 bits
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits
682 int op = (f30 << 30) |
683 (f25 << 25) |
684 (f22 << 22) |
685 (f0 << 0);
686 *((int*)(cbuf.code_end())) = op;
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
688 }
690 // Standard Sparc opcode form3 field breakdown
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
692 int op = (f30 << 30) |
693 (f25 << 25) |
694 (f19 << 19) |
695 (f14 << 14) |
696 (f5 << 5) |
697 (f0 << 0);
698 *((int*)(cbuf.code_end())) = op;
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
700 }
702 // Standard Sparc opcode form3 field breakdown
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
704 simm13 &= (1<<13)-1; // Mask to 13 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f19 << 19) |
708 (f14 << 14) |
709 (1 << 13) | // bit to indicate immediate-mode
710 (simm13<<0);
711 *((int*)(cbuf.code_end())) = op;
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
713 }
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
716 simm10 &= (1<<10)-1; // Mask to 10 bits
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
718 }
720 #ifdef ASSERT
721 // Helper function for VerifyOops in emit_form3_mem_reg
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
723 warning("VerifyOops encountered unexpected instruction:");
724 n->dump(2);
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
726 }
727 #endif
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
731 int src1_enc, int disp32, int src2_enc, int dst_enc) {
733 #ifdef ASSERT
734 // The following code implements the +VerifyOops feature.
735 // It verifies oop values which are loaded into or stored out of
736 // the current method activation. +VerifyOops complements techniques
737 // like ScavengeALot, because it eagerly inspects oops in transit,
738 // as they enter or leave the stack, as opposed to ScavengeALot,
739 // which inspects oops "at rest", in the stack or heap, at safepoints.
740 // For this reason, +VerifyOops can sometimes detect bugs very close
741 // to their point of creation. It can also serve as a cross-check
742 // on the validity of oop maps, when used toegether with ScavengeALot.
744 // It would be good to verify oops at other points, especially
745 // when an oop is used as a base pointer for a load or store.
746 // This is presently difficult, because it is hard to know when
747 // a base address is biased or not. (If we had such information,
748 // it would be easy and useful to make a two-argument version of
749 // verify_oop which unbiases the base, and performs verification.)
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
752 bool is_verified_oop_base = false;
753 bool is_verified_oop_load = false;
754 bool is_verified_oop_store = false;
755 int tmp_enc = -1;
756 if (VerifyOops && src1_enc != R_SP_enc) {
757 // classify the op, mainly for an assert check
758 int st_op = 0, ld_op = 0;
759 switch (primary) {
760 case Assembler::stb_op3: st_op = Op_StoreB; break;
761 case Assembler::sth_op3: st_op = Op_StoreC; break;
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
763 case Assembler::stw_op3: st_op = Op_StoreI; break;
764 case Assembler::std_op3: st_op = Op_StoreL; break;
765 case Assembler::stf_op3: st_op = Op_StoreF; break;
766 case Assembler::stdf_op3: st_op = Op_StoreD; break;
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
780 default: ShouldNotReachHere();
781 }
782 if (tertiary == REGP_OP) {
783 if (st_op == Op_StoreI) st_op = Op_StoreP;
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
785 else ShouldNotReachHere();
786 if (st_op) {
787 // a store
788 // inputs are (0:control, 1:memory, 2:address, 3:value)
789 Node* n2 = n->in(3);
790 if (n2 != NULL) {
791 const Type* t = n2->bottom_type();
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
793 }
794 } else {
795 // a load
796 const Type* t = n->bottom_type();
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
798 }
799 }
801 if (ld_op) {
802 // a Load
803 // inputs are (0:control, 1:memory, 2:address)
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
818 !(n->rule() == loadUB_rule)) {
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
820 }
821 } else if (st_op) {
822 // a Store
823 // inputs are (0:control, 1:memory, 2:address, 3:value)
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
830 verify_oops_warning(n, n->ideal_Opcode(), st_op);
831 }
832 }
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
835 Node* addr = n->in(2);
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
838 if (atype != NULL) {
839 intptr_t offset = get_offset_from_base(n, atype, disp32);
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
841 if (offset != offset_2) {
842 get_offset_from_base(n, atype, disp32);
843 get_offset_from_base_2(n, atype, disp32);
844 }
845 assert(offset == offset_2, "different offsets");
846 if (offset == disp32) {
847 // we now know that src1 is a true oop pointer
848 is_verified_oop_base = true;
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
850 if( primary == Assembler::ldd_op3 ) {
851 is_verified_oop_base = false; // Cannot 'ldd' into O7
852 } else {
853 tmp_enc = dst_enc;
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop
855 assert(src1_enc != dst_enc, "");
856 }
857 }
858 }
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
860 || offset == oopDesc::mark_offset_in_bytes())) {
861 // loading the mark should not be allowed either, but
862 // we don't check this since it conflicts with InlineObjectHash
863 // usage of LoadINode to get the mark. We could keep the
864 // check if we create a new LoadMarkNode
865 // but do not verify the object before its header is initialized
866 ShouldNotReachHere();
867 }
868 }
869 }
870 }
871 }
872 #endif
874 uint instr;
875 instr = (Assembler::ldst_op << 30)
876 | (dst_enc << 25)
877 | (primary << 19)
878 | (src1_enc << 14);
880 uint index = src2_enc;
881 int disp = disp32;
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
884 disp += STACK_BIAS;
886 // We should have a compiler bailout here rather than a guarantee.
887 // Better yet would be some mechanism to handle variable-size matches correctly.
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
890 if( disp == 0 ) {
891 // use reg-reg form
892 // bit 13 is already zero
893 instr |= index;
894 } else {
895 // use reg-imm form
896 instr |= 0x00002000; // set bit 13 to one
897 instr |= disp & 0x1FFF;
898 }
900 uint *code = (uint*)cbuf.code_end();
901 *code = instr;
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
904 #ifdef ASSERT
905 {
906 MacroAssembler _masm(&cbuf);
907 if (is_verified_oop_base) {
908 __ verify_oop(reg_to_register_object(src1_enc));
909 }
910 if (is_verified_oop_store) {
911 __ verify_oop(reg_to_register_object(dst_enc));
912 }
913 if (tmp_enc != -1) {
914 __ mov(O7, reg_to_register_object(tmp_enc));
915 }
916 if (is_verified_oop_load) {
917 __ verify_oop(reg_to_register_object(dst_enc));
918 }
919 }
920 #endif
921 }
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
926 uint instr;
927 instr = (Assembler::ldst_op << 30)
928 | (dst_enc << 25)
929 | (primary << 19)
930 | (src1_enc << 14);
932 int disp = disp32;
933 int index = src2_enc;
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
936 disp += STACK_BIAS;
938 // We should have a compiler bailout here rather than a guarantee.
939 // Better yet would be some mechanism to handle variable-size matches correctly.
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
942 if( disp != 0 ) {
943 // use reg-reg form
944 // set src2=R_O7 contains offset
945 index = R_O7_enc;
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
947 }
948 instr |= (asi << 5);
949 instr |= index;
950 uint *code = (uint*)cbuf.code_end();
951 *code = instr;
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
953 }
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
956 // The method which records debug information at every safepoint
957 // expects the call to be the first instruction in the snippet as
958 // it creates a PcDesc structure which tracks the offset of a call
959 // from the start of the codeBlob. This offset is computed as
960 // code_end() - code_begin() of the code which has been emitted
961 // so far.
962 // In this particular case we have skirted around the problem by
963 // putting the "mov" instruction in the delay slot but the problem
964 // may bite us again at some other point and a cleaner/generic
965 // solution using relocations would be needed.
966 MacroAssembler _masm(&cbuf);
967 __ set_inst_mark();
969 // We flush the current window just so that there is a valid stack copy
970 // the fact that the current window becomes active again instantly is
971 // not a problem there is nothing live in it.
973 #ifdef ASSERT
974 int startpos = __ offset();
975 #endif /* ASSERT */
977 #ifdef _LP64
978 // Calls to the runtime or native may not be reachable from compiled code,
979 // so we generate the far call sequence on 64 bit sparc.
980 // This code sequence is relocatable to any address, even on LP64.
981 if ( force_far_call ) {
982 __ relocate(rtype);
983 Address dest(O7, (address)entry_point);
984 __ jumpl_to(dest, O7);
985 }
986 else
987 #endif
988 {
989 __ call((address)entry_point, rtype);
990 }
992 if (preserve_g2) __ delayed()->mov(G2, L7);
993 else __ delayed()->nop();
995 if (preserve_g2) __ mov(L7, G2);
997 #ifdef ASSERT
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
999 #ifdef _LP64
1000 // Trash argument dump slots.
1001 __ set(0xb0b8ac0db0b8ac0d, G1);
1002 __ mov(G1, G5);
1003 __ stx(G1, SP, STACK_BIAS + 0x80);
1004 __ stx(G1, SP, STACK_BIAS + 0x88);
1005 __ stx(G1, SP, STACK_BIAS + 0x90);
1006 __ stx(G1, SP, STACK_BIAS + 0x98);
1007 __ stx(G1, SP, STACK_BIAS + 0xA0);
1008 __ stx(G1, SP, STACK_BIAS + 0xA8);
1009 #else // _LP64
1010 // this is also a native call, so smash the first 7 stack locations,
1011 // and the various registers
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1014 // while [SP+0x44..0x58] are the argument dump slots.
1015 __ set((intptr_t)0xbaadf00d, G1);
1016 __ mov(G1, G5);
1017 __ sllx(G1, 32, G1);
1018 __ or3(G1, G5, G1);
1019 __ mov(G1, G5);
1020 __ stx(G1, SP, 0x40);
1021 __ stx(G1, SP, 0x48);
1022 __ stx(G1, SP, 0x50);
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1024 #endif // _LP64
1025 }
1026 #endif /*ASSERT*/
1027 }
1029 //=============================================================================
1030 // REQUIRED FUNCTIONALITY for encoding
1031 void emit_lo(CodeBuffer &cbuf, int val) { }
1032 void emit_hi(CodeBuffer &cbuf, int val) { }
1034 void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) {
1035 MacroAssembler _masm(&cbuf);
1036 if (ForceRelocatable) {
1037 Address addr(reg, (address)val);
1038 __ sethi(addr, ForceRelocatable);
1039 __ add(addr, reg);
1040 } else {
1041 __ set(val, reg);
1042 }
1043 }
1046 //=============================================================================
1048 #ifndef PRODUCT
1049 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1050 Compile* C = ra_->C;
1052 for (int i = 0; i < OptoPrologueNops; i++) {
1053 st->print_cr("NOP"); st->print("\t");
1054 }
1056 if( VerifyThread ) {
1057 st->print_cr("Verify_Thread"); st->print("\t");
1058 }
1060 size_t framesize = C->frame_slots() << LogBytesPerInt;
1062 // Calls to C2R adapters often do not accept exceptional returns.
1063 // We require that their callers must bang for them. But be careful, because
1064 // some VM calls (such as call site linkage) can use several kilobytes of
1065 // stack. But the stack safety zone should account for that.
1066 // See bugs 4446381, 4468289, 4497237.
1067 if (C->need_stack_bang(framesize)) {
1068 st->print_cr("! stack bang"); st->print("\t");
1069 }
1071 if (Assembler::is_simm13(-framesize)) {
1072 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1073 } else {
1074 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1075 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1076 st->print ("SAVE R_SP,R_G3,R_SP");
1077 }
1079 }
1080 #endif
1082 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1083 Compile* C = ra_->C;
1084 MacroAssembler _masm(&cbuf);
1086 for (int i = 0; i < OptoPrologueNops; i++) {
1087 __ nop();
1088 }
1090 __ verify_thread();
1092 size_t framesize = C->frame_slots() << LogBytesPerInt;
1093 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1094 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1096 // Calls to C2R adapters often do not accept exceptional returns.
1097 // We require that their callers must bang for them. But be careful, because
1098 // some VM calls (such as call site linkage) can use several kilobytes of
1099 // stack. But the stack safety zone should account for that.
1100 // See bugs 4446381, 4468289, 4497237.
1101 if (C->need_stack_bang(framesize)) {
1102 __ generate_stack_overflow_check(framesize);
1103 }
1105 if (Assembler::is_simm13(-framesize)) {
1106 __ save(SP, -framesize, SP);
1107 } else {
1108 __ sethi(-framesize & ~0x3ff, G3);
1109 __ add(G3, -framesize & 0x3ff, G3);
1110 __ save(SP, G3, SP);
1111 }
1112 C->set_frame_complete( __ offset() );
1113 }
1115 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1116 return MachNode::size(ra_);
1117 }
1119 int MachPrologNode::reloc() const {
1120 return 10; // a large enough number
1121 }
1123 //=============================================================================
1124 #ifndef PRODUCT
1125 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1126 Compile* C = ra_->C;
1128 if( do_polling() && ra_->C->is_method_compilation() ) {
1129 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1130 #ifdef _LP64
1131 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1132 #else
1133 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1134 #endif
1135 }
1137 if( do_polling() )
1138 st->print("RET\n\t");
1140 st->print("RESTORE");
1141 }
1142 #endif
1144 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1145 MacroAssembler _masm(&cbuf);
1146 Compile* C = ra_->C;
1148 __ verify_thread();
1150 // If this does safepoint polling, then do it here
1151 if( do_polling() && ra_->C->is_method_compilation() ) {
1152 Address polling_page(L0, (address)os::get_polling_page());
1153 __ sethi(polling_page, false);
1154 __ relocate(relocInfo::poll_return_type);
1155 __ ld_ptr( L0, 0, G0 );
1156 }
1158 // If this is a return, then stuff the restore in the delay slot
1159 if( do_polling() ) {
1160 __ ret();
1161 __ delayed()->restore();
1162 } else {
1163 __ restore();
1164 }
1165 }
1167 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1168 return MachNode::size(ra_);
1169 }
1171 int MachEpilogNode::reloc() const {
1172 return 16; // a large enough number
1173 }
1175 const Pipeline * MachEpilogNode::pipeline() const {
1176 return MachNode::pipeline_class();
1177 }
1179 int MachEpilogNode::safepoint_offset() const {
1180 assert( do_polling(), "no return for this epilog node");
1181 return MacroAssembler::size_of_sethi(os::get_polling_page());
1182 }
1184 //=============================================================================
1186 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1187 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1188 static enum RC rc_class( OptoReg::Name reg ) {
1189 if( !OptoReg::is_valid(reg) ) return rc_bad;
1190 if (OptoReg::is_stack(reg)) return rc_stack;
1191 VMReg r = OptoReg::as_VMReg(reg);
1192 if (r->is_Register()) return rc_int;
1193 assert(r->is_FloatRegister(), "must be");
1194 return rc_float;
1195 }
1197 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1198 if( cbuf ) {
1199 // Better yet would be some mechanism to handle variable-size matches correctly
1200 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1201 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1202 } else {
1203 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1204 }
1205 }
1206 #ifndef PRODUCT
1207 else if( !do_size ) {
1208 if( size != 0 ) st->print("\n\t");
1209 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1210 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1211 }
1212 #endif
1213 return size+4;
1214 }
1216 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1217 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1218 #ifndef PRODUCT
1219 else if( !do_size ) {
1220 if( size != 0 ) st->print("\n\t");
1221 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1222 }
1223 #endif
1224 return size+4;
1225 }
1227 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1228 PhaseRegAlloc *ra_,
1229 bool do_size,
1230 outputStream* st ) const {
1231 // Get registers to move
1232 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1233 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1234 OptoReg::Name dst_second = ra_->get_reg_second(this );
1235 OptoReg::Name dst_first = ra_->get_reg_first(this );
1237 enum RC src_second_rc = rc_class(src_second);
1238 enum RC src_first_rc = rc_class(src_first);
1239 enum RC dst_second_rc = rc_class(dst_second);
1240 enum RC dst_first_rc = rc_class(dst_first);
1242 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1244 // Generate spill code!
1245 int size = 0;
1247 if( src_first == dst_first && src_second == dst_second )
1248 return size; // Self copy, no move
1250 // --------------------------------------
1251 // Check for mem-mem move. Load into unused float registers and fall into
1252 // the float-store case.
1253 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1254 int offset = ra_->reg2offset(src_first);
1255 // Further check for aligned-adjacent pair, so we can use a double load
1256 if( (src_first&1)==0 && src_first+1 == src_second ) {
1257 src_second = OptoReg::Name(R_F31_num);
1258 src_second_rc = rc_float;
1259 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1260 } else {
1261 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1262 }
1263 src_first = OptoReg::Name(R_F30_num);
1264 src_first_rc = rc_float;
1265 }
1267 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1268 int offset = ra_->reg2offset(src_second);
1269 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1270 src_second = OptoReg::Name(R_F31_num);
1271 src_second_rc = rc_float;
1272 }
1274 // --------------------------------------
1275 // Check for float->int copy; requires a trip through memory
1276 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1277 int offset = frame::register_save_words*wordSize;
1278 if( cbuf ) {
1279 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1280 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1281 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1282 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1283 }
1284 #ifndef PRODUCT
1285 else if( !do_size ) {
1286 if( size != 0 ) st->print("\n\t");
1287 st->print( "SUB R_SP,16,R_SP\n");
1288 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1289 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1290 st->print("\tADD R_SP,16,R_SP\n");
1291 }
1292 #endif
1293 size += 16;
1294 }
1296 // --------------------------------------
1297 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1298 // In such cases, I have to do the big-endian swap. For aligned targets, the
1299 // hardware does the flop for me. Doubles are always aligned, so no problem
1300 // there. Misaligned sources only come from native-long-returns (handled
1301 // special below).
1302 #ifndef _LP64
1303 if( src_first_rc == rc_int && // source is already big-endian
1304 src_second_rc != rc_bad && // 64-bit move
1305 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1306 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1307 // Do the big-endian flop.
1308 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1309 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1310 }
1311 #endif
1313 // --------------------------------------
1314 // Check for integer reg-reg copy
1315 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1316 #ifndef _LP64
1317 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1318 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1319 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1320 // operand contains the least significant word of the 64-bit value and vice versa.
1321 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1322 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1323 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1324 if( cbuf ) {
1325 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1326 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1327 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1328 #ifndef PRODUCT
1329 } else if( !do_size ) {
1330 if( size != 0 ) st->print("\n\t");
1331 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1332 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1333 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1334 #endif
1335 }
1336 return size+12;
1337 }
1338 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1339 // returning a long value in I0/I1
1340 // a SpillCopy must be able to target a return instruction's reg_class
1341 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1342 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1343 // operand contains the least significant word of the 64-bit value and vice versa.
1344 OptoReg::Name tdest = dst_first;
1346 if (src_first == dst_first) {
1347 tdest = OptoReg::Name(R_O7_num);
1348 size += 4;
1349 }
1351 if( cbuf ) {
1352 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1353 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1354 // ShrL_reg_imm6
1355 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1356 // ShrR_reg_imm6 src, 0, dst
1357 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1358 if (tdest != dst_first) {
1359 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1360 }
1361 }
1362 #ifndef PRODUCT
1363 else if( !do_size ) {
1364 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1365 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1366 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1367 if (tdest != dst_first) {
1368 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1369 }
1370 }
1371 #endif // PRODUCT
1372 return size+8;
1373 }
1374 #endif // !_LP64
1375 // Else normal reg-reg copy
1376 assert( src_second != dst_first, "smashed second before evacuating it" );
1377 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1378 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1379 // This moves an aligned adjacent pair.
1380 // See if we are done.
1381 if( src_first+1 == src_second && dst_first+1 == dst_second )
1382 return size;
1383 }
1385 // Check for integer store
1386 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1387 int offset = ra_->reg2offset(dst_first);
1388 // Further check for aligned-adjacent pair, so we can use a double store
1389 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1390 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1391 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1392 }
1394 // Check for integer load
1395 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1396 int offset = ra_->reg2offset(src_first);
1397 // Further check for aligned-adjacent pair, so we can use a double load
1398 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1399 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1400 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1401 }
1403 // Check for float reg-reg copy
1404 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1405 // Further check for aligned-adjacent pair, so we can use a double move
1406 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1407 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1408 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1409 }
1411 // Check for float store
1412 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1413 int offset = ra_->reg2offset(dst_first);
1414 // Further check for aligned-adjacent pair, so we can use a double store
1415 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1416 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1417 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1418 }
1420 // Check for float load
1421 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1422 int offset = ra_->reg2offset(src_first);
1423 // Further check for aligned-adjacent pair, so we can use a double load
1424 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1425 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1426 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1427 }
1429 // --------------------------------------------------------------------
1430 // Check for hi bits still needing moving. Only happens for misaligned
1431 // arguments to native calls.
1432 if( src_second == dst_second )
1433 return size; // Self copy; no move
1434 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1436 #ifndef _LP64
1437 // In the LP64 build, all registers can be moved as aligned/adjacent
1438 // pairs, so there's never any need to move the high bits separately.
1439 // The 32-bit builds have to deal with the 32-bit ABI which can force
1440 // all sorts of silly alignment problems.
1442 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1443 // 32-bits of a 64-bit register, but are needed in low bits of another
1444 // register (else it's a hi-bits-to-hi-bits copy which should have
1445 // happened already as part of a 64-bit move)
1446 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1447 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1448 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1449 // Shift src_second down to dst_second's low bits.
1450 if( cbuf ) {
1451 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1452 #ifndef PRODUCT
1453 } else if( !do_size ) {
1454 if( size != 0 ) st->print("\n\t");
1455 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1456 #endif
1457 }
1458 return size+4;
1459 }
1461 // Check for high word integer store. Must down-shift the hi bits
1462 // into a temp register, then fall into the case of storing int bits.
1463 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1464 // Shift src_second down to dst_second's low bits.
1465 if( cbuf ) {
1466 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1467 #ifndef PRODUCT
1468 } else if( !do_size ) {
1469 if( size != 0 ) st->print("\n\t");
1470 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1471 #endif
1472 }
1473 size+=4;
1474 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1475 }
1477 // Check for high word integer load
1478 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1479 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1481 // Check for high word integer store
1482 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1483 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1485 // Check for high word float store
1486 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1487 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1489 #endif // !_LP64
1491 Unimplemented();
1492 }
1494 #ifndef PRODUCT
1495 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1496 implementation( NULL, ra_, false, st );
1497 }
1498 #endif
1500 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1501 implementation( &cbuf, ra_, false, NULL );
1502 }
1504 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1505 return implementation( NULL, ra_, true, NULL );
1506 }
1508 //=============================================================================
1509 #ifndef PRODUCT
1510 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1511 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1512 }
1513 #endif
1515 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1516 MacroAssembler _masm(&cbuf);
1517 for(int i = 0; i < _count; i += 1) {
1518 __ nop();
1519 }
1520 }
1522 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1523 return 4 * _count;
1524 }
1527 //=============================================================================
1528 #ifndef PRODUCT
1529 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1530 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1531 int reg = ra_->get_reg_first(this);
1532 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1533 }
1534 #endif
1536 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1537 MacroAssembler _masm(&cbuf);
1538 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1539 int reg = ra_->get_encode(this);
1541 if (Assembler::is_simm13(offset)) {
1542 __ add(SP, offset, reg_to_register_object(reg));
1543 } else {
1544 __ set(offset, O7);
1545 __ add(SP, O7, reg_to_register_object(reg));
1546 }
1547 }
1549 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1550 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1551 assert(ra_ == ra_->C->regalloc(), "sanity");
1552 return ra_->C->scratch_emit_size(this);
1553 }
1555 //=============================================================================
1557 // emit call stub, compiled java to interpretor
1558 void emit_java_to_interp(CodeBuffer &cbuf ) {
1560 // Stub is fixed up when the corresponding call is converted from calling
1561 // compiled code to calling interpreted code.
1562 // set (empty), G5
1563 // jmp -1
1565 address mark = cbuf.inst_mark(); // get mark within main instrs section
1567 MacroAssembler _masm(&cbuf);
1569 address base =
1570 __ start_a_stub(Compile::MAX_stubs_size);
1571 if (base == NULL) return; // CodeBuffer::expand failed
1573 // static stub relocation stores the instruction address of the call
1574 __ relocate(static_stub_Relocation::spec(mark));
1576 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1578 __ set_inst_mark();
1579 Address a(G3, (address)-1);
1580 __ JUMP(a, 0);
1582 __ delayed()->nop();
1584 // Update current stubs pointer and restore code_end.
1585 __ end_a_stub();
1586 }
1588 // size of call stub, compiled java to interpretor
1589 uint size_java_to_interp() {
1590 // This doesn't need to be accurate but it must be larger or equal to
1591 // the real size of the stub.
1592 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1593 NativeJump::instruction_size + // sethi; jmp; nop
1594 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1595 }
1596 // relocation entries for call stub, compiled java to interpretor
1597 uint reloc_java_to_interp() {
1598 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1599 }
1602 //=============================================================================
1603 #ifndef PRODUCT
1604 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1605 st->print_cr("\nUEP:");
1606 #ifdef _LP64
1607 if (UseCompressedOops) {
1608 assert(Universe::heap() != NULL, "java heap should be initialized");
1609 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1610 st->print_cr("\tSLL R_G5,3,R_G5");
1611 if (Universe::narrow_oop_base() != NULL)
1612 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1613 } else {
1614 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1615 }
1616 st->print_cr("\tCMP R_G5,R_G3" );
1617 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1618 #else // _LP64
1619 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1620 st->print_cr("\tCMP R_G5,R_G3" );
1621 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1622 #endif // _LP64
1623 }
1624 #endif
1626 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1627 MacroAssembler _masm(&cbuf);
1628 Label L;
1629 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1630 Register temp_reg = G3;
1631 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1633 // Load klass from receiver
1634 __ load_klass(O0, temp_reg);
1635 // Compare against expected klass
1636 __ cmp(temp_reg, G5_ic_reg);
1637 // Branch to miss code, checks xcc or icc depending
1638 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1639 }
1641 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1642 return MachNode::size(ra_);
1643 }
1646 //=============================================================================
1648 uint size_exception_handler() {
1649 if (TraceJumps) {
1650 return (400); // just a guess
1651 }
1652 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1653 }
1655 uint size_deopt_handler() {
1656 if (TraceJumps) {
1657 return (400); // just a guess
1658 }
1659 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1660 }
1662 // Emit exception handler code.
1663 int emit_exception_handler(CodeBuffer& cbuf) {
1664 Register temp_reg = G3;
1665 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin());
1666 MacroAssembler _masm(&cbuf);
1668 address base =
1669 __ start_a_stub(size_exception_handler());
1670 if (base == NULL) return 0; // CodeBuffer::expand failed
1672 int offset = __ offset();
1674 __ JUMP(exception_blob, 0); // sethi;jmp
1675 __ delayed()->nop();
1677 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1679 __ end_a_stub();
1681 return offset;
1682 }
1684 int emit_deopt_handler(CodeBuffer& cbuf) {
1685 // Can't use any of the current frame's registers as we may have deopted
1686 // at a poll and everything (including G3) can be live.
1687 Register temp_reg = L0;
1688 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack());
1689 MacroAssembler _masm(&cbuf);
1691 address base =
1692 __ start_a_stub(size_deopt_handler());
1693 if (base == NULL) return 0; // CodeBuffer::expand failed
1695 int offset = __ offset();
1696 __ save_frame(0);
1697 __ JUMP(deopt_blob, 0); // sethi;jmp
1698 __ delayed()->restore();
1700 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1702 __ end_a_stub();
1703 return offset;
1705 }
1707 // Given a register encoding, produce a Integer Register object
1708 static Register reg_to_register_object(int register_encoding) {
1709 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1710 return as_Register(register_encoding);
1711 }
1713 // Given a register encoding, produce a single-precision Float Register object
1714 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1715 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1716 return as_SingleFloatRegister(register_encoding);
1717 }
1719 // Given a register encoding, produce a double-precision Float Register object
1720 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1721 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1722 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1723 return as_DoubleFloatRegister(register_encoding);
1724 }
1726 int Matcher::regnum_to_fpu_offset(int regnum) {
1727 return regnum - 32; // The FP registers are in the second chunk
1728 }
1730 #ifdef ASSERT
1731 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1732 #endif
1734 // Vector width in bytes
1735 const uint Matcher::vector_width_in_bytes(void) {
1736 return 8;
1737 }
1739 // Vector ideal reg
1740 const uint Matcher::vector_ideal_reg(void) {
1741 return Op_RegD;
1742 }
1744 // USII supports fxtof through the whole range of number, USIII doesn't
1745 const bool Matcher::convL2FSupported(void) {
1746 return VM_Version::has_fast_fxtof();
1747 }
1749 // Is this branch offset short enough that a short branch can be used?
1750 //
1751 // NOTE: If the platform does not provide any short branch variants, then
1752 // this method should return false for offset 0.
1753 bool Matcher::is_short_branch_offset(int rule, int offset) {
1754 return false;
1755 }
1757 const bool Matcher::isSimpleConstant64(jlong value) {
1758 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1759 // Depends on optimizations in MacroAssembler::setx.
1760 int hi = (int)(value >> 32);
1761 int lo = (int)(value & ~0);
1762 return (hi == 0) || (hi == -1) || (lo == 0);
1763 }
1765 // No scaling for the parameter the ClearArray node.
1766 const bool Matcher::init_array_count_is_in_bytes = true;
1768 // Threshold size for cleararray.
1769 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1771 // Should the Matcher clone shifts on addressing modes, expecting them to
1772 // be subsumed into complex addressing expressions or compute them into
1773 // registers? True for Intel but false for most RISCs
1774 const bool Matcher::clone_shift_expressions = false;
1776 // Is it better to copy float constants, or load them directly from memory?
1777 // Intel can load a float constant from a direct address, requiring no
1778 // extra registers. Most RISCs will have to materialize an address into a
1779 // register first, so they would do better to copy the constant from stack.
1780 const bool Matcher::rematerialize_float_constants = false;
1782 // If CPU can load and store mis-aligned doubles directly then no fixup is
1783 // needed. Else we split the double into 2 integer pieces and move it
1784 // piece-by-piece. Only happens when passing doubles into C code as the
1785 // Java calling convention forces doubles to be aligned.
1786 #ifdef _LP64
1787 const bool Matcher::misaligned_doubles_ok = true;
1788 #else
1789 const bool Matcher::misaligned_doubles_ok = false;
1790 #endif
1792 // No-op on SPARC.
1793 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1794 }
1796 // Advertise here if the CPU requires explicit rounding operations
1797 // to implement the UseStrictFP mode.
1798 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1800 // Do floats take an entire double register or just half?
1801 const bool Matcher::float_in_double = false;
1803 // Do ints take an entire long register or just half?
1804 // Note that we if-def off of _LP64.
1805 // The relevant question is how the int is callee-saved. In _LP64
1806 // the whole long is written but de-opt'ing will have to extract
1807 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1808 #ifdef _LP64
1809 const bool Matcher::int_in_long = true;
1810 #else
1811 const bool Matcher::int_in_long = false;
1812 #endif
1814 // Return whether or not this register is ever used as an argument. This
1815 // function is used on startup to build the trampoline stubs in generateOptoStub.
1816 // Registers not mentioned will be killed by the VM call in the trampoline, and
1817 // arguments in those registers not be available to the callee.
1818 bool Matcher::can_be_java_arg( int reg ) {
1819 // Standard sparc 6 args in registers
1820 if( reg == R_I0_num ||
1821 reg == R_I1_num ||
1822 reg == R_I2_num ||
1823 reg == R_I3_num ||
1824 reg == R_I4_num ||
1825 reg == R_I5_num ) return true;
1826 #ifdef _LP64
1827 // 64-bit builds can pass 64-bit pointers and longs in
1828 // the high I registers
1829 if( reg == R_I0H_num ||
1830 reg == R_I1H_num ||
1831 reg == R_I2H_num ||
1832 reg == R_I3H_num ||
1833 reg == R_I4H_num ||
1834 reg == R_I5H_num ) return true;
1836 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1837 return true;
1838 }
1840 #else
1841 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1842 // Longs cannot be passed in O regs, because O regs become I regs
1843 // after a 'save' and I regs get their high bits chopped off on
1844 // interrupt.
1845 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1846 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1847 #endif
1848 // A few float args in registers
1849 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1851 return false;
1852 }
1854 bool Matcher::is_spillable_arg( int reg ) {
1855 return can_be_java_arg(reg);
1856 }
1858 // Register for DIVI projection of divmodI
1859 RegMask Matcher::divI_proj_mask() {
1860 ShouldNotReachHere();
1861 return RegMask();
1862 }
1864 // Register for MODI projection of divmodI
1865 RegMask Matcher::modI_proj_mask() {
1866 ShouldNotReachHere();
1867 return RegMask();
1868 }
1870 // Register for DIVL projection of divmodL
1871 RegMask Matcher::divL_proj_mask() {
1872 ShouldNotReachHere();
1873 return RegMask();
1874 }
1876 // Register for MODL projection of divmodL
1877 RegMask Matcher::modL_proj_mask() {
1878 ShouldNotReachHere();
1879 return RegMask();
1880 }
1882 %}
1885 // The intptr_t operand types, defined by textual substitution.
1886 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1887 #ifdef _LP64
1888 #define immX immL
1889 #define immX13 immL13
1890 #define iRegX iRegL
1891 #define g1RegX g1RegL
1892 #else
1893 #define immX immI
1894 #define immX13 immI13
1895 #define iRegX iRegI
1896 #define g1RegX g1RegI
1897 #endif
1899 //----------ENCODING BLOCK-----------------------------------------------------
1900 // This block specifies the encoding classes used by the compiler to output
1901 // byte streams. Encoding classes are parameterized macros used by
1902 // Machine Instruction Nodes in order to generate the bit encoding of the
1903 // instruction. Operands specify their base encoding interface with the
1904 // interface keyword. There are currently supported four interfaces,
1905 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1906 // operand to generate a function which returns its register number when
1907 // queried. CONST_INTER causes an operand to generate a function which
1908 // returns the value of the constant when queried. MEMORY_INTER causes an
1909 // operand to generate four functions which return the Base Register, the
1910 // Index Register, the Scale Value, and the Offset Value of the operand when
1911 // queried. COND_INTER causes an operand to generate six functions which
1912 // return the encoding code (ie - encoding bits for the instruction)
1913 // associated with each basic boolean condition for a conditional instruction.
1914 //
1915 // Instructions specify two basic values for encoding. Again, a function
1916 // is available to check if the constant displacement is an oop. They use the
1917 // ins_encode keyword to specify their encoding classes (which must be
1918 // a sequence of enc_class names, and their parameters, specified in
1919 // the encoding block), and they use the
1920 // opcode keyword to specify, in order, their primary, secondary, and
1921 // tertiary opcode. Only the opcode sections which a particular instruction
1922 // needs for encoding need to be specified.
1923 encode %{
1924 enc_class enc_untested %{
1925 #ifdef ASSERT
1926 MacroAssembler _masm(&cbuf);
1927 __ untested("encoding");
1928 #endif
1929 %}
1931 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1932 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1933 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1934 %}
1936 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1937 emit_form3_mem_reg(cbuf, this, $primary, -1,
1938 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1939 %}
1941 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1942 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1943 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1944 %}
1946 enc_class form3_mem_prefetch_read( memory mem ) %{
1947 emit_form3_mem_reg(cbuf, this, $primary, -1,
1948 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1949 %}
1951 enc_class form3_mem_prefetch_write( memory mem ) %{
1952 emit_form3_mem_reg(cbuf, this, $primary, -1,
1953 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1954 %}
1956 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1957 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1958 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1959 guarantee($mem$$index == R_G0_enc, "double index?");
1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1961 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1962 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1963 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1964 %}
1966 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1967 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1968 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1969 guarantee($mem$$index == R_G0_enc, "double index?");
1970 // Load long with 2 instructions
1971 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1972 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1973 %}
1975 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1976 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1977 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1978 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1979 %}
1981 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1982 // Encode a reg-reg copy. If it is useless, then empty encoding.
1983 if( $rs2$$reg != $rd$$reg )
1984 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1985 %}
1987 // Target lo half of long
1988 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1989 // Encode a reg-reg copy. If it is useless, then empty encoding.
1990 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1991 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1992 %}
1994 // Source lo half of long
1995 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
1996 // Encode a reg-reg copy. If it is useless, then empty encoding.
1997 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
1998 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
1999 %}
2001 // Target hi half of long
2002 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2003 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2004 %}
2006 // Source lo half of long, and leave it sign extended.
2007 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2008 // Sign extend low half
2009 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2010 %}
2012 // Source hi half of long, and leave it sign extended.
2013 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2014 // Shift high half to low half
2015 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2016 %}
2018 // Source hi half of long
2019 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2020 // Encode a reg-reg copy. If it is useless, then empty encoding.
2021 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2022 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2023 %}
2025 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2026 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2027 %}
2029 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2030 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2031 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2032 %}
2034 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2035 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2036 // clear if nothing else is happening
2037 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2038 // blt,a,pn done
2039 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2040 // mov dst,-1 in delay slot
2041 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2042 %}
2044 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2045 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2046 %}
2048 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2049 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2050 %}
2052 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2053 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2054 %}
2056 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2057 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2058 %}
2060 enc_class move_return_pc_to_o1() %{
2061 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2062 %}
2064 #ifdef _LP64
2065 /* %%% merge with enc_to_bool */
2066 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2067 MacroAssembler _masm(&cbuf);
2069 Register src_reg = reg_to_register_object($src$$reg);
2070 Register dst_reg = reg_to_register_object($dst$$reg);
2071 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2072 %}
2073 #endif
2075 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2076 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2077 MacroAssembler _masm(&cbuf);
2079 Register p_reg = reg_to_register_object($p$$reg);
2080 Register q_reg = reg_to_register_object($q$$reg);
2081 Register y_reg = reg_to_register_object($y$$reg);
2082 Register tmp_reg = reg_to_register_object($tmp$$reg);
2084 __ subcc( p_reg, q_reg, p_reg );
2085 __ add ( p_reg, y_reg, tmp_reg );
2086 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2087 %}
2089 enc_class form_d2i_helper(regD src, regF dst) %{
2090 // fcmp %fcc0,$src,$src
2091 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2092 // branch %fcc0 not-nan, predict taken
2093 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2094 // fdtoi $src,$dst
2095 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2096 // fitos $dst,$dst (if nan)
2097 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2098 // clear $dst (if nan)
2099 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2100 // carry on here...
2101 %}
2103 enc_class form_d2l_helper(regD src, regD dst) %{
2104 // fcmp %fcc0,$src,$src check for NAN
2105 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2106 // branch %fcc0 not-nan, predict taken
2107 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2108 // fdtox $src,$dst convert in delay slot
2109 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2110 // fxtod $dst,$dst (if nan)
2111 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2112 // clear $dst (if nan)
2113 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2114 // carry on here...
2115 %}
2117 enc_class form_f2i_helper(regF src, regF dst) %{
2118 // fcmps %fcc0,$src,$src
2119 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2120 // branch %fcc0 not-nan, predict taken
2121 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2122 // fstoi $src,$dst
2123 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2124 // fitos $dst,$dst (if nan)
2125 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2126 // clear $dst (if nan)
2127 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2128 // carry on here...
2129 %}
2131 enc_class form_f2l_helper(regF src, regD dst) %{
2132 // fcmps %fcc0,$src,$src
2133 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2134 // branch %fcc0 not-nan, predict taken
2135 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2136 // fstox $src,$dst
2137 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2138 // fxtod $dst,$dst (if nan)
2139 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2140 // clear $dst (if nan)
2141 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2142 // carry on here...
2143 %}
2145 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2146 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2147 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2148 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2150 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2152 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2153 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2155 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2156 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2157 %}
2159 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2160 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2161 %}
2163 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2164 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2165 %}
2167 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2168 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2169 %}
2171 enc_class form3_convI2F(regF rs2, regF rd) %{
2172 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2173 %}
2175 // Encloding class for traceable jumps
2176 enc_class form_jmpl(g3RegP dest) %{
2177 emit_jmpl(cbuf, $dest$$reg);
2178 %}
2180 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2181 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2182 %}
2184 enc_class form2_nop() %{
2185 emit_nop(cbuf);
2186 %}
2188 enc_class form2_illtrap() %{
2189 emit_illtrap(cbuf);
2190 %}
2193 // Compare longs and convert into -1, 0, 1.
2194 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2195 // CMP $src1,$src2
2196 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2197 // blt,a,pn done
2198 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2199 // mov dst,-1 in delay slot
2200 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2201 // bgt,a,pn done
2202 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2203 // mov dst,1 in delay slot
2204 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2205 // CLR $dst
2206 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2207 %}
2209 enc_class enc_PartialSubtypeCheck() %{
2210 MacroAssembler _masm(&cbuf);
2211 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2212 __ delayed()->nop();
2213 %}
2215 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2216 MacroAssembler _masm(&cbuf);
2217 Label &L = *($labl$$label);
2218 Assembler::Predict predict_taken =
2219 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2221 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2222 __ delayed()->nop();
2223 %}
2225 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2226 MacroAssembler _masm(&cbuf);
2227 Label &L = *($labl$$label);
2228 Assembler::Predict predict_taken =
2229 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2231 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2232 __ delayed()->nop();
2233 %}
2235 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2236 MacroAssembler _masm(&cbuf);
2237 Label &L = *($labl$$label);
2238 Assembler::Predict predict_taken =
2239 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2241 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2242 __ delayed()->nop();
2243 %}
2245 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2246 MacroAssembler _masm(&cbuf);
2247 Label &L = *($labl$$label);
2248 Assembler::Predict predict_taken =
2249 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2251 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2252 __ delayed()->nop();
2253 %}
2255 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2256 MacroAssembler _masm(&cbuf);
2258 Register switch_reg = as_Register($switch_val$$reg);
2259 Register table_reg = O7;
2261 address table_base = __ address_table_constant(_index2label);
2262 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2264 // Load table address
2265 Address the_pc(table_reg, table_base, rspec);
2266 __ load_address(the_pc);
2268 // Jump to base address + switch value
2269 __ ld_ptr(table_reg, switch_reg, table_reg);
2270 __ jmp(table_reg, G0);
2271 __ delayed()->nop();
2273 %}
2275 enc_class enc_ba( Label labl ) %{
2276 MacroAssembler _masm(&cbuf);
2277 Label &L = *($labl$$label);
2278 __ ba(false, L);
2279 __ delayed()->nop();
2280 %}
2282 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2283 MacroAssembler _masm(&cbuf);
2284 Label &L = *$labl$$label;
2285 Assembler::Predict predict_taken =
2286 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2288 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2289 __ delayed()->nop();
2290 %}
2292 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2293 int op = (Assembler::arith_op << 30) |
2294 ($dst$$reg << 25) |
2295 (Assembler::movcc_op3 << 19) |
2296 (1 << 18) | // cc2 bit for 'icc'
2297 ($cmp$$cmpcode << 14) |
2298 (0 << 13) | // select register move
2299 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2300 ($src$$reg << 0);
2301 *((int*)(cbuf.code_end())) = op;
2302 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2303 %}
2305 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2306 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2307 int op = (Assembler::arith_op << 30) |
2308 ($dst$$reg << 25) |
2309 (Assembler::movcc_op3 << 19) |
2310 (1 << 18) | // cc2 bit for 'icc'
2311 ($cmp$$cmpcode << 14) |
2312 (1 << 13) | // select immediate move
2313 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2314 (simm11 << 0);
2315 *((int*)(cbuf.code_end())) = op;
2316 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2317 %}
2319 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2320 int op = (Assembler::arith_op << 30) |
2321 ($dst$$reg << 25) |
2322 (Assembler::movcc_op3 << 19) |
2323 (0 << 18) | // cc2 bit for 'fccX'
2324 ($cmp$$cmpcode << 14) |
2325 (0 << 13) | // select register move
2326 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2327 ($src$$reg << 0);
2328 *((int*)(cbuf.code_end())) = op;
2329 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2330 %}
2332 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2333 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2334 int op = (Assembler::arith_op << 30) |
2335 ($dst$$reg << 25) |
2336 (Assembler::movcc_op3 << 19) |
2337 (0 << 18) | // cc2 bit for 'fccX'
2338 ($cmp$$cmpcode << 14) |
2339 (1 << 13) | // select immediate move
2340 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2341 (simm11 << 0);
2342 *((int*)(cbuf.code_end())) = op;
2343 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2344 %}
2346 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2347 int op = (Assembler::arith_op << 30) |
2348 ($dst$$reg << 25) |
2349 (Assembler::fpop2_op3 << 19) |
2350 (0 << 18) |
2351 ($cmp$$cmpcode << 14) |
2352 (1 << 13) | // select register move
2353 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2354 ($primary << 5) | // select single, double or quad
2355 ($src$$reg << 0);
2356 *((int*)(cbuf.code_end())) = op;
2357 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2358 %}
2360 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2361 int op = (Assembler::arith_op << 30) |
2362 ($dst$$reg << 25) |
2363 (Assembler::fpop2_op3 << 19) |
2364 (0 << 18) |
2365 ($cmp$$cmpcode << 14) |
2366 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2367 ($primary << 5) | // select single, double or quad
2368 ($src$$reg << 0);
2369 *((int*)(cbuf.code_end())) = op;
2370 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2371 %}
2373 // Used by the MIN/MAX encodings. Same as a CMOV, but
2374 // the condition comes from opcode-field instead of an argument.
2375 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2376 int op = (Assembler::arith_op << 30) |
2377 ($dst$$reg << 25) |
2378 (Assembler::movcc_op3 << 19) |
2379 (1 << 18) | // cc2 bit for 'icc'
2380 ($primary << 14) |
2381 (0 << 13) | // select register move
2382 (0 << 11) | // cc1, cc0 bits for 'icc'
2383 ($src$$reg << 0);
2384 *((int*)(cbuf.code_end())) = op;
2385 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2386 %}
2388 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2389 int op = (Assembler::arith_op << 30) |
2390 ($dst$$reg << 25) |
2391 (Assembler::movcc_op3 << 19) |
2392 (6 << 16) | // cc2 bit for 'xcc'
2393 ($primary << 14) |
2394 (0 << 13) | // select register move
2395 (0 << 11) | // cc1, cc0 bits for 'icc'
2396 ($src$$reg << 0);
2397 *((int*)(cbuf.code_end())) = op;
2398 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2399 %}
2401 // Utility encoding for loading a 64 bit Pointer into a register
2402 // The 64 bit pointer is stored in the generated code stream
2403 enc_class SetPtr( immP src, iRegP rd ) %{
2404 Register dest = reg_to_register_object($rd$$reg);
2405 // [RGV] This next line should be generated from ADLC
2406 if ( _opnds[1]->constant_is_oop() ) {
2407 intptr_t val = $src$$constant;
2408 MacroAssembler _masm(&cbuf);
2409 __ set_oop_constant((jobject)val, dest);
2410 } else { // non-oop pointers, e.g. card mark base, heap top
2411 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false);
2412 }
2413 %}
2415 enc_class Set13( immI13 src, iRegI rd ) %{
2416 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2417 %}
2419 enc_class SetHi22( immI src, iRegI rd ) %{
2420 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2421 %}
2423 enc_class Set32( immI src, iRegI rd ) %{
2424 MacroAssembler _masm(&cbuf);
2425 __ set($src$$constant, reg_to_register_object($rd$$reg));
2426 %}
2428 enc_class SetNull( iRegI rd ) %{
2429 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2430 %}
2432 enc_class call_epilog %{
2433 if( VerifyStackAtCalls ) {
2434 MacroAssembler _masm(&cbuf);
2435 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2436 Register temp_reg = G3;
2437 __ add(SP, framesize, temp_reg);
2438 __ cmp(temp_reg, FP);
2439 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2440 }
2441 %}
2443 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2444 // to G1 so the register allocator will not have to deal with the misaligned register
2445 // pair.
2446 enc_class adjust_long_from_native_call %{
2447 #ifndef _LP64
2448 if (returns_long()) {
2449 // sllx O0,32,O0
2450 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2451 // srl O1,0,O1
2452 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2453 // or O0,O1,G1
2454 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2455 }
2456 #endif
2457 %}
2459 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2460 // CALL directly to the runtime
2461 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2463 /*preserve_g2=*/true, /*force far call*/true);
2464 %}
2466 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2467 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2468 // who we intended to call.
2469 if ( !_method ) {
2470 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2471 } else if (_optimized_virtual) {
2472 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2473 } else {
2474 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2475 }
2476 if( _method ) { // Emit stub for static call
2477 emit_java_to_interp(cbuf);
2478 }
2479 %}
2481 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2482 MacroAssembler _masm(&cbuf);
2483 __ set_inst_mark();
2484 int vtable_index = this->_vtable_index;
2485 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2486 if (vtable_index < 0) {
2487 // must be invalid_vtable_index, not nonvirtual_vtable_index
2488 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2489 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2490 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2491 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2492 // !!!!!
2493 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2494 // emit_call_dynamic_prologue( cbuf );
2495 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2497 address virtual_call_oop_addr = __ inst_mark();
2498 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2499 // who we intended to call.
2500 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2501 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2502 } else {
2503 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2504 // Just go thru the vtable
2505 // get receiver klass (receiver already checked for non-null)
2506 // If we end up going thru a c2i adapter interpreter expects method in G5
2507 int off = __ offset();
2508 __ load_klass(O0, G3_scratch);
2509 int klass_load_size;
2510 if (UseCompressedOops) {
2511 assert(Universe::heap() != NULL, "java heap should be initialized");
2512 if (Universe::narrow_oop_base() == NULL)
2513 klass_load_size = 2*BytesPerInstWord;
2514 else
2515 klass_load_size = 3*BytesPerInstWord;
2516 } else {
2517 klass_load_size = 1*BytesPerInstWord;
2518 }
2519 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2520 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2521 if( __ is_simm13(v_off) ) {
2522 __ ld_ptr(G3, v_off, G5_method);
2523 } else {
2524 // Generate 2 instructions
2525 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2526 __ or3(G5_method, v_off & 0x3ff, G5_method);
2527 // ld_ptr, set_hi, set
2528 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2529 "Unexpected instruction size(s)");
2530 __ ld_ptr(G3, G5_method, G5_method);
2531 }
2532 // NOTE: for vtable dispatches, the vtable entry will never be null.
2533 // However it may very well end up in handle_wrong_method if the
2534 // method is abstract for the particular class.
2535 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2536 // jump to target (either compiled code or c2iadapter)
2537 __ jmpl(G3_scratch, G0, O7);
2538 __ delayed()->nop();
2539 }
2540 %}
2542 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2543 MacroAssembler _masm(&cbuf);
2545 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2546 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2547 // we might be calling a C2I adapter which needs it.
2549 assert(temp_reg != G5_ic_reg, "conflicting registers");
2550 // Load nmethod
2551 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2553 // CALL to compiled java, indirect the contents of G3
2554 __ set_inst_mark();
2555 __ callr(temp_reg, G0);
2556 __ delayed()->nop();
2557 %}
2559 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2560 MacroAssembler _masm(&cbuf);
2561 Register Rdividend = reg_to_register_object($src1$$reg);
2562 Register Rdivisor = reg_to_register_object($src2$$reg);
2563 Register Rresult = reg_to_register_object($dst$$reg);
2565 __ sra(Rdivisor, 0, Rdivisor);
2566 __ sra(Rdividend, 0, Rdividend);
2567 __ sdivx(Rdividend, Rdivisor, Rresult);
2568 %}
2570 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2571 MacroAssembler _masm(&cbuf);
2573 Register Rdividend = reg_to_register_object($src1$$reg);
2574 int divisor = $imm$$constant;
2575 Register Rresult = reg_to_register_object($dst$$reg);
2577 __ sra(Rdividend, 0, Rdividend);
2578 __ sdivx(Rdividend, divisor, Rresult);
2579 %}
2581 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2582 MacroAssembler _masm(&cbuf);
2583 Register Rsrc1 = reg_to_register_object($src1$$reg);
2584 Register Rsrc2 = reg_to_register_object($src2$$reg);
2585 Register Rdst = reg_to_register_object($dst$$reg);
2587 __ sra( Rsrc1, 0, Rsrc1 );
2588 __ sra( Rsrc2, 0, Rsrc2 );
2589 __ mulx( Rsrc1, Rsrc2, Rdst );
2590 __ srlx( Rdst, 32, Rdst );
2591 %}
2593 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2594 MacroAssembler _masm(&cbuf);
2595 Register Rdividend = reg_to_register_object($src1$$reg);
2596 Register Rdivisor = reg_to_register_object($src2$$reg);
2597 Register Rresult = reg_to_register_object($dst$$reg);
2598 Register Rscratch = reg_to_register_object($scratch$$reg);
2600 assert(Rdividend != Rscratch, "");
2601 assert(Rdivisor != Rscratch, "");
2603 __ sra(Rdividend, 0, Rdividend);
2604 __ sra(Rdivisor, 0, Rdivisor);
2605 __ sdivx(Rdividend, Rdivisor, Rscratch);
2606 __ mulx(Rscratch, Rdivisor, Rscratch);
2607 __ sub(Rdividend, Rscratch, Rresult);
2608 %}
2610 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2611 MacroAssembler _masm(&cbuf);
2613 Register Rdividend = reg_to_register_object($src1$$reg);
2614 int divisor = $imm$$constant;
2615 Register Rresult = reg_to_register_object($dst$$reg);
2616 Register Rscratch = reg_to_register_object($scratch$$reg);
2618 assert(Rdividend != Rscratch, "");
2620 __ sra(Rdividend, 0, Rdividend);
2621 __ sdivx(Rdividend, divisor, Rscratch);
2622 __ mulx(Rscratch, divisor, Rscratch);
2623 __ sub(Rdividend, Rscratch, Rresult);
2624 %}
2626 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2627 MacroAssembler _masm(&cbuf);
2629 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2630 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2632 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2633 %}
2635 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2636 MacroAssembler _masm(&cbuf);
2638 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2639 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2641 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2642 %}
2644 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2645 MacroAssembler _masm(&cbuf);
2647 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2648 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2650 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2651 %}
2653 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2654 MacroAssembler _masm(&cbuf);
2656 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2657 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2659 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2660 %}
2662 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2663 MacroAssembler _masm(&cbuf);
2665 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2666 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2668 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2669 %}
2671 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2672 MacroAssembler _masm(&cbuf);
2674 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2675 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2677 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2678 %}
2680 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2681 MacroAssembler _masm(&cbuf);
2683 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2684 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2686 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2687 %}
2689 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2690 MacroAssembler _masm(&cbuf);
2692 Register Roop = reg_to_register_object($oop$$reg);
2693 Register Rbox = reg_to_register_object($box$$reg);
2694 Register Rscratch = reg_to_register_object($scratch$$reg);
2695 Register Rmark = reg_to_register_object($scratch2$$reg);
2697 assert(Roop != Rscratch, "");
2698 assert(Roop != Rmark, "");
2699 assert(Rbox != Rscratch, "");
2700 assert(Rbox != Rmark, "");
2702 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2703 %}
2705 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2706 MacroAssembler _masm(&cbuf);
2708 Register Roop = reg_to_register_object($oop$$reg);
2709 Register Rbox = reg_to_register_object($box$$reg);
2710 Register Rscratch = reg_to_register_object($scratch$$reg);
2711 Register Rmark = reg_to_register_object($scratch2$$reg);
2713 assert(Roop != Rscratch, "");
2714 assert(Roop != Rmark, "");
2715 assert(Rbox != Rscratch, "");
2716 assert(Rbox != Rmark, "");
2718 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2719 %}
2721 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2722 MacroAssembler _masm(&cbuf);
2723 Register Rmem = reg_to_register_object($mem$$reg);
2724 Register Rold = reg_to_register_object($old$$reg);
2725 Register Rnew = reg_to_register_object($new$$reg);
2727 // casx_under_lock picks 1 of 3 encodings:
2728 // For 32-bit pointers you get a 32-bit CAS
2729 // For 64-bit pointers you get a 64-bit CASX
2730 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2731 __ cmp( Rold, Rnew );
2732 %}
2734 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2735 Register Rmem = reg_to_register_object($mem$$reg);
2736 Register Rold = reg_to_register_object($old$$reg);
2737 Register Rnew = reg_to_register_object($new$$reg);
2739 MacroAssembler _masm(&cbuf);
2740 __ mov(Rnew, O7);
2741 __ casx(Rmem, Rold, O7);
2742 __ cmp( Rold, O7 );
2743 %}
2745 // raw int cas, used for compareAndSwap
2746 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2747 Register Rmem = reg_to_register_object($mem$$reg);
2748 Register Rold = reg_to_register_object($old$$reg);
2749 Register Rnew = reg_to_register_object($new$$reg);
2751 MacroAssembler _masm(&cbuf);
2752 __ mov(Rnew, O7);
2753 __ cas(Rmem, Rold, O7);
2754 __ cmp( Rold, O7 );
2755 %}
2757 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2758 Register Rres = reg_to_register_object($res$$reg);
2760 MacroAssembler _masm(&cbuf);
2761 __ mov(1, Rres);
2762 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2763 %}
2765 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2766 Register Rres = reg_to_register_object($res$$reg);
2768 MacroAssembler _masm(&cbuf);
2769 __ mov(1, Rres);
2770 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2771 %}
2773 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2774 MacroAssembler _masm(&cbuf);
2775 Register Rdst = reg_to_register_object($dst$$reg);
2776 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2777 : reg_to_DoubleFloatRegister_object($src1$$reg);
2778 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2779 : reg_to_DoubleFloatRegister_object($src2$$reg);
2781 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2782 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2783 %}
2785 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2786 MacroAssembler _masm(&cbuf);
2787 Register dest = reg_to_register_object($dst$$reg);
2788 Register temp = reg_to_register_object($tmp$$reg);
2789 __ set64( $src$$constant, dest, temp );
2790 %}
2792 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate
2793 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant);
2794 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
2795 #ifdef _LP64
2796 Register tmp_reg = reg_to_register_object($tmp$$reg);
2797 cbuf.relocate(cbuf.code_end(), rspec, 0);
2798 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true);
2799 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 );
2800 #else // _LP64
2801 uint *code;
2802 int tmp_reg = $tmp$$reg;
2804 cbuf.relocate(cbuf.code_end(), rspec, 0);
2805 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address );
2807 cbuf.relocate(cbuf.code_end(), rspec, 0);
2808 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address );
2809 #endif // _LP64
2810 %}
2812 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate
2813 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant);
2814 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2815 #ifdef _LP64
2816 Register tmp_reg = reg_to_register_object($tmp$$reg);
2817 cbuf.relocate(cbuf.code_end(), rspec, 0);
2818 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
2819 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2820 #else // _LP64
2821 uint *code;
2822 int tmp_reg = $tmp$$reg;
2824 cbuf.relocate(cbuf.code_end(), rspec, 0);
2825 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2827 cbuf.relocate(cbuf.code_end(), rspec, 0);
2828 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2829 #endif // _LP64
2830 %}
2832 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2833 // Load a constant replicated "count" times with width "width"
2834 int bit_width = $width$$constant * 8;
2835 jlong elt_val = $src$$constant;
2836 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2837 jlong val = elt_val;
2838 for (int i = 0; i < $count$$constant - 1; i++) {
2839 val <<= bit_width;
2840 val |= elt_val;
2841 }
2842 jdouble dval = *(jdouble*)&val; // coerce to double type
2843 address double_address = MacroAssembler(&cbuf).double_constant(dval);
2844 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2845 #ifdef _LP64
2846 Register tmp_reg = reg_to_register_object($tmp$$reg);
2847 cbuf.relocate(cbuf.code_end(), rspec, 0);
2848 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
2849 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2850 #else // _LP64
2851 uint *code;
2852 int tmp_reg = $tmp$$reg;
2854 cbuf.relocate(cbuf.code_end(), rspec, 0);
2855 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2857 cbuf.relocate(cbuf.code_end(), rspec, 0);
2858 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2859 #endif // _LP64
2860 %}
2863 enc_class ShouldNotEncodeThis ( ) %{
2864 ShouldNotCallThis();
2865 %}
2867 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2868 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2869 MacroAssembler _masm(&cbuf);
2870 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2871 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2872 Register base_pointer_arg = reg_to_register_object($base$$reg);
2874 Label loop;
2875 __ mov(nof_bytes_arg, nof_bytes_tmp);
2877 // Loop and clear, walking backwards through the array.
2878 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2879 __ bind(loop);
2880 __ deccc(nof_bytes_tmp, 8);
2881 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2882 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2883 // %%%% this mini-loop must not cross a cache boundary!
2884 %}
2887 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2888 Label Ldone, Lloop;
2889 MacroAssembler _masm(&cbuf);
2891 Register str1_reg = reg_to_register_object($str1$$reg);
2892 Register str2_reg = reg_to_register_object($str2$$reg);
2893 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2894 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2895 Register result_reg = reg_to_register_object($result$$reg);
2897 // Get the first character position in both strings
2898 // [8] char array, [12] offset, [16] count
2899 int value_offset = java_lang_String:: value_offset_in_bytes();
2900 int offset_offset = java_lang_String::offset_offset_in_bytes();
2901 int count_offset = java_lang_String:: count_offset_in_bytes();
2903 // load str1 (jchar*) base address into tmp1_reg
2904 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg);
2905 __ ld(Address(str1_reg, 0, offset_offset), result_reg);
2906 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2907 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
2908 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2909 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
2910 __ add(result_reg, tmp1_reg, tmp1_reg);
2912 // load str2 (jchar*) base address into tmp2_reg
2913 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
2914 __ ld(Address(str2_reg, 0, offset_offset), result_reg);
2915 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2916 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
2917 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2918 __ subcc(str1_reg, str2_reg, O7); // hoisted
2919 __ add(result_reg, tmp2_reg, tmp2_reg);
2921 // Compute the minimum of the string lengths(str1_reg) and the
2922 // difference of the string lengths (stack)
2924 // discard string base pointers, after loading up the lengths
2925 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
2926 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
2928 // See if the lengths are different, and calculate min in str1_reg.
2929 // Stash diff in O7 in case we need it for a tie-breaker.
2930 Label Lskip;
2931 // __ subcc(str1_reg, str2_reg, O7); // hoisted
2932 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2933 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2934 // str2 is shorter, so use its count:
2935 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2936 __ bind(Lskip);
2938 // reallocate str1_reg, str2_reg, result_reg
2939 // Note: limit_reg holds the string length pre-scaled by 2
2940 Register limit_reg = str1_reg;
2941 Register chr2_reg = str2_reg;
2942 Register chr1_reg = result_reg;
2943 // tmp{12} are the base pointers
2945 // Is the minimum length zero?
2946 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2947 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2948 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2950 // Load first characters
2951 __ lduh(tmp1_reg, 0, chr1_reg);
2952 __ lduh(tmp2_reg, 0, chr2_reg);
2954 // Compare first characters
2955 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2956 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2957 assert(chr1_reg == result_reg, "result must be pre-placed");
2958 __ delayed()->nop();
2960 {
2961 // Check after comparing first character to see if strings are equivalent
2962 Label LSkip2;
2963 // Check if the strings start at same location
2964 __ cmp(tmp1_reg, tmp2_reg);
2965 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2966 __ delayed()->nop();
2968 // Check if the length difference is zero (in O7)
2969 __ cmp(G0, O7);
2970 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2971 __ delayed()->mov(G0, result_reg); // result is zero
2973 // Strings might not be equal
2974 __ bind(LSkip2);
2975 }
2977 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2978 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2979 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2981 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
2982 __ add(tmp1_reg, limit_reg, tmp1_reg);
2983 __ add(tmp2_reg, limit_reg, tmp2_reg);
2984 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2986 // Compare the rest of the characters
2987 __ lduh(tmp1_reg, limit_reg, chr1_reg);
2988 __ bind(Lloop);
2989 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2990 __ lduh(tmp2_reg, limit_reg, chr2_reg);
2991 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2992 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2993 assert(chr1_reg == result_reg, "result must be pre-placed");
2994 __ delayed()->inccc(limit_reg, sizeof(jchar));
2995 // annul LDUH if branch is not taken to prevent access past end of string
2996 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2997 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2999 // If strings are equal up to min length, return the length difference.
3000 __ mov(O7, result_reg);
3002 // Otherwise, return the difference between the first mismatched chars.
3003 __ bind(Ldone);
3004 %}
3006 enc_class enc_rethrow() %{
3007 cbuf.set_inst_mark();
3008 Register temp_reg = G3;
3009 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub());
3010 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3011 MacroAssembler _masm(&cbuf);
3012 #ifdef ASSERT
3013 __ save_frame(0);
3014 Address last_rethrow_addr(L1, (address)&last_rethrow);
3015 __ sethi(last_rethrow_addr);
3016 __ get_pc(L2);
3017 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3018 __ st_ptr(L2, last_rethrow_addr);
3019 __ restore();
3020 #endif
3021 __ JUMP(rethrow_stub, 0); // sethi;jmp
3022 __ delayed()->nop();
3023 %}
3025 enc_class emit_mem_nop() %{
3026 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3027 unsigned int *code = (unsigned int*)cbuf.code_end();
3028 *code = (unsigned int)0xc0839040;
3029 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3030 %}
3032 enc_class emit_fadd_nop() %{
3033 // Generates the instruction FMOVS f31,f31
3034 unsigned int *code = (unsigned int*)cbuf.code_end();
3035 *code = (unsigned int)0xbfa0003f;
3036 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3037 %}
3039 enc_class emit_br_nop() %{
3040 // Generates the instruction BPN,PN .
3041 unsigned int *code = (unsigned int*)cbuf.code_end();
3042 *code = (unsigned int)0x00400000;
3043 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3044 %}
3046 enc_class enc_membar_acquire %{
3047 MacroAssembler _masm(&cbuf);
3048 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3049 %}
3051 enc_class enc_membar_release %{
3052 MacroAssembler _masm(&cbuf);
3053 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3054 %}
3056 enc_class enc_membar_volatile %{
3057 MacroAssembler _masm(&cbuf);
3058 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3059 %}
3061 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3062 MacroAssembler _masm(&cbuf);
3063 Register src_reg = reg_to_register_object($src$$reg);
3064 Register dst_reg = reg_to_register_object($dst$$reg);
3065 __ sllx(src_reg, 56, dst_reg);
3066 __ srlx(dst_reg, 8, O7);
3067 __ or3 (dst_reg, O7, dst_reg);
3068 __ srlx(dst_reg, 16, O7);
3069 __ or3 (dst_reg, O7, dst_reg);
3070 __ srlx(dst_reg, 32, O7);
3071 __ or3 (dst_reg, O7, dst_reg);
3072 %}
3074 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3075 MacroAssembler _masm(&cbuf);
3076 Register src_reg = reg_to_register_object($src$$reg);
3077 Register dst_reg = reg_to_register_object($dst$$reg);
3078 __ sll(src_reg, 24, dst_reg);
3079 __ srl(dst_reg, 8, O7);
3080 __ or3(dst_reg, O7, dst_reg);
3081 __ srl(dst_reg, 16, O7);
3082 __ or3(dst_reg, O7, dst_reg);
3083 %}
3085 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3086 MacroAssembler _masm(&cbuf);
3087 Register src_reg = reg_to_register_object($src$$reg);
3088 Register dst_reg = reg_to_register_object($dst$$reg);
3089 __ sllx(src_reg, 48, dst_reg);
3090 __ srlx(dst_reg, 16, O7);
3091 __ or3 (dst_reg, O7, dst_reg);
3092 __ srlx(dst_reg, 32, O7);
3093 __ or3 (dst_reg, O7, dst_reg);
3094 %}
3096 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3097 MacroAssembler _masm(&cbuf);
3098 Register src_reg = reg_to_register_object($src$$reg);
3099 Register dst_reg = reg_to_register_object($dst$$reg);
3100 __ sllx(src_reg, 32, dst_reg);
3101 __ srlx(dst_reg, 32, O7);
3102 __ or3 (dst_reg, O7, dst_reg);
3103 %}
3105 %}
3107 //----------FRAME--------------------------------------------------------------
3108 // Definition of frame structure and management information.
3109 //
3110 // S T A C K L A Y O U T Allocators stack-slot number
3111 // | (to get allocators register number
3112 // G Owned by | | v add VMRegImpl::stack0)
3113 // r CALLER | |
3114 // o | +--------+ pad to even-align allocators stack-slot
3115 // w V | pad0 | numbers; owned by CALLER
3116 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3117 // h ^ | in | 5
3118 // | | args | 4 Holes in incoming args owned by SELF
3119 // | | | | 3
3120 // | | +--------+
3121 // V | | old out| Empty on Intel, window on Sparc
3122 // | old |preserve| Must be even aligned.
3123 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3124 // | | in | 3 area for Intel ret address
3125 // Owned by |preserve| Empty on Sparc.
3126 // SELF +--------+
3127 // | | pad2 | 2 pad to align old SP
3128 // | +--------+ 1
3129 // | | locks | 0
3130 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3131 // | | pad1 | 11 pad to align new SP
3132 // | +--------+
3133 // | | | 10
3134 // | | spills | 9 spills
3135 // V | | 8 (pad0 slot for callee)
3136 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3137 // ^ | out | 7
3138 // | | args | 6 Holes in outgoing args owned by CALLEE
3139 // Owned by +--------+
3140 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3141 // | new |preserve| Must be even-aligned.
3142 // | SP-+--------+----> Matcher::_new_SP, even aligned
3143 // | | |
3144 //
3145 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3146 // known from SELF's arguments and the Java calling convention.
3147 // Region 6-7 is determined per call site.
3148 // Note 2: If the calling convention leaves holes in the incoming argument
3149 // area, those holes are owned by SELF. Holes in the outgoing area
3150 // are owned by the CALLEE. Holes should not be nessecary in the
3151 // incoming area, as the Java calling convention is completely under
3152 // the control of the AD file. Doubles can be sorted and packed to
3153 // avoid holes. Holes in the outgoing arguments may be nessecary for
3154 // varargs C calling conventions.
3155 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3156 // even aligned with pad0 as needed.
3157 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3158 // region 6-11 is even aligned; it may be padded out more so that
3159 // the region from SP to FP meets the minimum stack alignment.
3161 frame %{
3162 // What direction does stack grow in (assumed to be same for native & Java)
3163 stack_direction(TOWARDS_LOW);
3165 // These two registers define part of the calling convention
3166 // between compiled code and the interpreter.
3167 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3168 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3170 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3171 cisc_spilling_operand_name(indOffset);
3173 // Number of stack slots consumed by a Monitor enter
3174 #ifdef _LP64
3175 sync_stack_slots(2);
3176 #else
3177 sync_stack_slots(1);
3178 #endif
3180 // Compiled code's Frame Pointer
3181 frame_pointer(R_SP);
3183 // Stack alignment requirement
3184 stack_alignment(StackAlignmentInBytes);
3185 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3186 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3188 // Number of stack slots between incoming argument block and the start of
3189 // a new frame. The PROLOG must add this many slots to the stack. The
3190 // EPILOG must remove this many slots.
3191 in_preserve_stack_slots(0);
3193 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3194 // for calls to C. Supports the var-args backing area for register parms.
3195 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3196 #ifdef _LP64
3197 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3198 varargs_C_out_slots_killed(12);
3199 #else
3200 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3201 varargs_C_out_slots_killed( 7);
3202 #endif
3204 // The after-PROLOG location of the return address. Location of
3205 // return address specifies a type (REG or STACK) and a number
3206 // representing the register number (i.e. - use a register name) or
3207 // stack slot.
3208 return_addr(REG R_I7); // Ret Addr is in register I7
3210 // Body of function which returns an OptoRegs array locating
3211 // arguments either in registers or in stack slots for calling
3212 // java
3213 calling_convention %{
3214 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3216 %}
3218 // Body of function which returns an OptoRegs array locating
3219 // arguments either in registers or in stack slots for callin
3220 // C.
3221 c_calling_convention %{
3222 // This is obviously always outgoing
3223 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3224 %}
3226 // Location of native (C/C++) and interpreter return values. This is specified to
3227 // be the same as Java. In the 32-bit VM, long values are actually returned from
3228 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3229 // to and from the register pairs is done by the appropriate call and epilog
3230 // opcodes. This simplifies the register allocator.
3231 c_return_value %{
3232 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3233 #ifdef _LP64
3234 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3235 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3236 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3237 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3238 #else // !_LP64
3239 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3240 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3241 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3242 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3243 #endif
3244 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3245 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3246 %}
3248 // Location of compiled Java return values. Same as C
3249 return_value %{
3250 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3251 #ifdef _LP64
3252 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3253 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3254 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3255 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3256 #else // !_LP64
3257 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3258 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3259 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3260 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3261 #endif
3262 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3263 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3264 %}
3266 %}
3269 //----------ATTRIBUTES---------------------------------------------------------
3270 //----------Operand Attributes-------------------------------------------------
3271 op_attrib op_cost(1); // Required cost attribute
3273 //----------Instruction Attributes---------------------------------------------
3274 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3275 ins_attrib ins_size(32); // Required size attribute (in bits)
3276 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3277 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3278 // non-matching short branch variant of some
3279 // long branch?
3281 //----------OPERANDS-----------------------------------------------------------
3282 // Operand definitions must precede instruction definitions for correct parsing
3283 // in the ADLC because operands constitute user defined types which are used in
3284 // instruction definitions.
3286 //----------Simple Operands----------------------------------------------------
3287 // Immediate Operands
3288 // Integer Immediate: 32-bit
3289 operand immI() %{
3290 match(ConI);
3292 op_cost(0);
3293 // formats are generated automatically for constants and base registers
3294 format %{ %}
3295 interface(CONST_INTER);
3296 %}
3298 // Integer Immediate: 13-bit
3299 operand immI13() %{
3300 predicate(Assembler::is_simm13(n->get_int()));
3301 match(ConI);
3302 op_cost(0);
3304 format %{ %}
3305 interface(CONST_INTER);
3306 %}
3308 // Unsigned (positive) Integer Immediate: 13-bit
3309 operand immU13() %{
3310 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3311 match(ConI);
3312 op_cost(0);
3314 format %{ %}
3315 interface(CONST_INTER);
3316 %}
3318 // Integer Immediate: 6-bit
3319 operand immU6() %{
3320 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3321 match(ConI);
3322 op_cost(0);
3323 format %{ %}
3324 interface(CONST_INTER);
3325 %}
3327 // Integer Immediate: 11-bit
3328 operand immI11() %{
3329 predicate(Assembler::is_simm(n->get_int(),11));
3330 match(ConI);
3331 op_cost(0);
3332 format %{ %}
3333 interface(CONST_INTER);
3334 %}
3336 // Integer Immediate: 0-bit
3337 operand immI0() %{
3338 predicate(n->get_int() == 0);
3339 match(ConI);
3340 op_cost(0);
3342 format %{ %}
3343 interface(CONST_INTER);
3344 %}
3346 // Integer Immediate: the value 10
3347 operand immI10() %{
3348 predicate(n->get_int() == 10);
3349 match(ConI);
3350 op_cost(0);
3352 format %{ %}
3353 interface(CONST_INTER);
3354 %}
3356 // Integer Immediate: the values 0-31
3357 operand immU5() %{
3358 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3359 match(ConI);
3360 op_cost(0);
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3366 // Integer Immediate: the values 1-31
3367 operand immI_1_31() %{
3368 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3369 match(ConI);
3370 op_cost(0);
3372 format %{ %}
3373 interface(CONST_INTER);
3374 %}
3376 // Integer Immediate: the values 32-63
3377 operand immI_32_63() %{
3378 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3379 match(ConI);
3380 op_cost(0);
3382 format %{ %}
3383 interface(CONST_INTER);
3384 %}
3386 // Integer Immediate: the value 255
3387 operand immI_255() %{
3388 predicate( n->get_int() == 255 );
3389 match(ConI);
3390 op_cost(0);
3392 format %{ %}
3393 interface(CONST_INTER);
3394 %}
3396 // Long Immediate: the value FF
3397 operand immL_FF() %{
3398 predicate( n->get_long() == 0xFFL );
3399 match(ConL);
3400 op_cost(0);
3402 format %{ %}
3403 interface(CONST_INTER);
3404 %}
3406 // Long Immediate: the value FFFF
3407 operand immL_FFFF() %{
3408 predicate( n->get_long() == 0xFFFFL );
3409 match(ConL);
3410 op_cost(0);
3412 format %{ %}
3413 interface(CONST_INTER);
3414 %}
3416 // Pointer Immediate: 32 or 64-bit
3417 operand immP() %{
3418 match(ConP);
3420 op_cost(5);
3421 // formats are generated automatically for constants and base registers
3422 format %{ %}
3423 interface(CONST_INTER);
3424 %}
3426 operand immP13() %{
3427 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3428 match(ConP);
3429 op_cost(0);
3431 format %{ %}
3432 interface(CONST_INTER);
3433 %}
3435 operand immP0() %{
3436 predicate(n->get_ptr() == 0);
3437 match(ConP);
3438 op_cost(0);
3440 format %{ %}
3441 interface(CONST_INTER);
3442 %}
3444 operand immP_poll() %{
3445 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3446 match(ConP);
3448 // formats are generated automatically for constants and base registers
3449 format %{ %}
3450 interface(CONST_INTER);
3451 %}
3453 // Pointer Immediate
3454 operand immN()
3455 %{
3456 match(ConN);
3458 op_cost(10);
3459 format %{ %}
3460 interface(CONST_INTER);
3461 %}
3463 // NULL Pointer Immediate
3464 operand immN0()
3465 %{
3466 predicate(n->get_narrowcon() == 0);
3467 match(ConN);
3469 op_cost(0);
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3474 operand immL() %{
3475 match(ConL);
3476 op_cost(40);
3477 // formats are generated automatically for constants and base registers
3478 format %{ %}
3479 interface(CONST_INTER);
3480 %}
3482 operand immL0() %{
3483 predicate(n->get_long() == 0L);
3484 match(ConL);
3485 op_cost(0);
3486 // formats are generated automatically for constants and base registers
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3491 // Long Immediate: 13-bit
3492 operand immL13() %{
3493 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3494 match(ConL);
3495 op_cost(0);
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3501 // Long Immediate: low 32-bit mask
3502 operand immL_32bits() %{
3503 predicate(n->get_long() == 0xFFFFFFFFL);
3504 match(ConL);
3505 op_cost(0);
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3511 // Double Immediate
3512 operand immD() %{
3513 match(ConD);
3515 op_cost(40);
3516 format %{ %}
3517 interface(CONST_INTER);
3518 %}
3520 operand immD0() %{
3521 #ifdef _LP64
3522 // on 64-bit architectures this comparision is faster
3523 predicate(jlong_cast(n->getd()) == 0);
3524 #else
3525 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3526 #endif
3527 match(ConD);
3529 op_cost(0);
3530 format %{ %}
3531 interface(CONST_INTER);
3532 %}
3534 // Float Immediate
3535 operand immF() %{
3536 match(ConF);
3538 op_cost(20);
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3543 // Float Immediate: 0
3544 operand immF0() %{
3545 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3546 match(ConF);
3548 op_cost(0);
3549 format %{ %}
3550 interface(CONST_INTER);
3551 %}
3553 // Integer Register Operands
3554 // Integer Register
3555 operand iRegI() %{
3556 constraint(ALLOC_IN_RC(int_reg));
3557 match(RegI);
3559 match(notemp_iRegI);
3560 match(g1RegI);
3561 match(o0RegI);
3562 match(iRegIsafe);
3564 format %{ %}
3565 interface(REG_INTER);
3566 %}
3568 operand notemp_iRegI() %{
3569 constraint(ALLOC_IN_RC(notemp_int_reg));
3570 match(RegI);
3572 match(o0RegI);
3574 format %{ %}
3575 interface(REG_INTER);
3576 %}
3578 operand o0RegI() %{
3579 constraint(ALLOC_IN_RC(o0_regI));
3580 match(iRegI);
3582 format %{ %}
3583 interface(REG_INTER);
3584 %}
3586 // Pointer Register
3587 operand iRegP() %{
3588 constraint(ALLOC_IN_RC(ptr_reg));
3589 match(RegP);
3591 match(lock_ptr_RegP);
3592 match(g1RegP);
3593 match(g2RegP);
3594 match(g3RegP);
3595 match(g4RegP);
3596 match(i0RegP);
3597 match(o0RegP);
3598 match(o1RegP);
3599 match(l7RegP);
3601 format %{ %}
3602 interface(REG_INTER);
3603 %}
3605 operand sp_ptr_RegP() %{
3606 constraint(ALLOC_IN_RC(sp_ptr_reg));
3607 match(RegP);
3608 match(iRegP);
3610 format %{ %}
3611 interface(REG_INTER);
3612 %}
3614 operand lock_ptr_RegP() %{
3615 constraint(ALLOC_IN_RC(lock_ptr_reg));
3616 match(RegP);
3617 match(i0RegP);
3618 match(o0RegP);
3619 match(o1RegP);
3620 match(l7RegP);
3622 format %{ %}
3623 interface(REG_INTER);
3624 %}
3626 operand g1RegP() %{
3627 constraint(ALLOC_IN_RC(g1_regP));
3628 match(iRegP);
3630 format %{ %}
3631 interface(REG_INTER);
3632 %}
3634 operand g2RegP() %{
3635 constraint(ALLOC_IN_RC(g2_regP));
3636 match(iRegP);
3638 format %{ %}
3639 interface(REG_INTER);
3640 %}
3642 operand g3RegP() %{
3643 constraint(ALLOC_IN_RC(g3_regP));
3644 match(iRegP);
3646 format %{ %}
3647 interface(REG_INTER);
3648 %}
3650 operand g1RegI() %{
3651 constraint(ALLOC_IN_RC(g1_regI));
3652 match(iRegI);
3654 format %{ %}
3655 interface(REG_INTER);
3656 %}
3658 operand g3RegI() %{
3659 constraint(ALLOC_IN_RC(g3_regI));
3660 match(iRegI);
3662 format %{ %}
3663 interface(REG_INTER);
3664 %}
3666 operand g4RegI() %{
3667 constraint(ALLOC_IN_RC(g4_regI));
3668 match(iRegI);
3670 format %{ %}
3671 interface(REG_INTER);
3672 %}
3674 operand g4RegP() %{
3675 constraint(ALLOC_IN_RC(g4_regP));
3676 match(iRegP);
3678 format %{ %}
3679 interface(REG_INTER);
3680 %}
3682 operand i0RegP() %{
3683 constraint(ALLOC_IN_RC(i0_regP));
3684 match(iRegP);
3686 format %{ %}
3687 interface(REG_INTER);
3688 %}
3690 operand o0RegP() %{
3691 constraint(ALLOC_IN_RC(o0_regP));
3692 match(iRegP);
3694 format %{ %}
3695 interface(REG_INTER);
3696 %}
3698 operand o1RegP() %{
3699 constraint(ALLOC_IN_RC(o1_regP));
3700 match(iRegP);
3702 format %{ %}
3703 interface(REG_INTER);
3704 %}
3706 operand o2RegP() %{
3707 constraint(ALLOC_IN_RC(o2_regP));
3708 match(iRegP);
3710 format %{ %}
3711 interface(REG_INTER);
3712 %}
3714 operand o7RegP() %{
3715 constraint(ALLOC_IN_RC(o7_regP));
3716 match(iRegP);
3718 format %{ %}
3719 interface(REG_INTER);
3720 %}
3722 operand l7RegP() %{
3723 constraint(ALLOC_IN_RC(l7_regP));
3724 match(iRegP);
3726 format %{ %}
3727 interface(REG_INTER);
3728 %}
3730 operand o7RegI() %{
3731 constraint(ALLOC_IN_RC(o7_regI));
3732 match(iRegI);
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3738 operand iRegN() %{
3739 constraint(ALLOC_IN_RC(int_reg));
3740 match(RegN);
3742 format %{ %}
3743 interface(REG_INTER);
3744 %}
3746 // Long Register
3747 operand iRegL() %{
3748 constraint(ALLOC_IN_RC(long_reg));
3749 match(RegL);
3751 format %{ %}
3752 interface(REG_INTER);
3753 %}
3755 operand o2RegL() %{
3756 constraint(ALLOC_IN_RC(o2_regL));
3757 match(iRegL);
3759 format %{ %}
3760 interface(REG_INTER);
3761 %}
3763 operand o7RegL() %{
3764 constraint(ALLOC_IN_RC(o7_regL));
3765 match(iRegL);
3767 format %{ %}
3768 interface(REG_INTER);
3769 %}
3771 operand g1RegL() %{
3772 constraint(ALLOC_IN_RC(g1_regL));
3773 match(iRegL);
3775 format %{ %}
3776 interface(REG_INTER);
3777 %}
3779 operand g3RegL() %{
3780 constraint(ALLOC_IN_RC(g3_regL));
3781 match(iRegL);
3783 format %{ %}
3784 interface(REG_INTER);
3785 %}
3787 // Int Register safe
3788 // This is 64bit safe
3789 operand iRegIsafe() %{
3790 constraint(ALLOC_IN_RC(long_reg));
3792 match(iRegI);
3794 format %{ %}
3795 interface(REG_INTER);
3796 %}
3798 // Condition Code Flag Register
3799 operand flagsReg() %{
3800 constraint(ALLOC_IN_RC(int_flags));
3801 match(RegFlags);
3803 format %{ "ccr" %} // both ICC and XCC
3804 interface(REG_INTER);
3805 %}
3807 // Condition Code Register, unsigned comparisons.
3808 operand flagsRegU() %{
3809 constraint(ALLOC_IN_RC(int_flags));
3810 match(RegFlags);
3812 format %{ "icc_U" %}
3813 interface(REG_INTER);
3814 %}
3816 // Condition Code Register, pointer comparisons.
3817 operand flagsRegP() %{
3818 constraint(ALLOC_IN_RC(int_flags));
3819 match(RegFlags);
3821 #ifdef _LP64
3822 format %{ "xcc_P" %}
3823 #else
3824 format %{ "icc_P" %}
3825 #endif
3826 interface(REG_INTER);
3827 %}
3829 // Condition Code Register, long comparisons.
3830 operand flagsRegL() %{
3831 constraint(ALLOC_IN_RC(int_flags));
3832 match(RegFlags);
3834 format %{ "xcc_L" %}
3835 interface(REG_INTER);
3836 %}
3838 // Condition Code Register, floating comparisons, unordered same as "less".
3839 operand flagsRegF() %{
3840 constraint(ALLOC_IN_RC(float_flags));
3841 match(RegFlags);
3842 match(flagsRegF0);
3844 format %{ %}
3845 interface(REG_INTER);
3846 %}
3848 operand flagsRegF0() %{
3849 constraint(ALLOC_IN_RC(float_flag0));
3850 match(RegFlags);
3852 format %{ %}
3853 interface(REG_INTER);
3854 %}
3857 // Condition Code Flag Register used by long compare
3858 operand flagsReg_long_LTGE() %{
3859 constraint(ALLOC_IN_RC(int_flags));
3860 match(RegFlags);
3861 format %{ "icc_LTGE" %}
3862 interface(REG_INTER);
3863 %}
3864 operand flagsReg_long_EQNE() %{
3865 constraint(ALLOC_IN_RC(int_flags));
3866 match(RegFlags);
3867 format %{ "icc_EQNE" %}
3868 interface(REG_INTER);
3869 %}
3870 operand flagsReg_long_LEGT() %{
3871 constraint(ALLOC_IN_RC(int_flags));
3872 match(RegFlags);
3873 format %{ "icc_LEGT" %}
3874 interface(REG_INTER);
3875 %}
3878 operand regD() %{
3879 constraint(ALLOC_IN_RC(dflt_reg));
3880 match(RegD);
3882 match(regD_low);
3884 format %{ %}
3885 interface(REG_INTER);
3886 %}
3888 operand regF() %{
3889 constraint(ALLOC_IN_RC(sflt_reg));
3890 match(RegF);
3892 format %{ %}
3893 interface(REG_INTER);
3894 %}
3896 operand regD_low() %{
3897 constraint(ALLOC_IN_RC(dflt_low_reg));
3898 match(regD);
3900 format %{ %}
3901 interface(REG_INTER);
3902 %}
3904 // Special Registers
3906 // Method Register
3907 operand inline_cache_regP(iRegP reg) %{
3908 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3909 match(reg);
3910 format %{ %}
3911 interface(REG_INTER);
3912 %}
3914 operand interpreter_method_oop_regP(iRegP reg) %{
3915 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3916 match(reg);
3917 format %{ %}
3918 interface(REG_INTER);
3919 %}
3922 //----------Complex Operands---------------------------------------------------
3923 // Indirect Memory Reference
3924 operand indirect(sp_ptr_RegP reg) %{
3925 constraint(ALLOC_IN_RC(sp_ptr_reg));
3926 match(reg);
3928 op_cost(100);
3929 format %{ "[$reg]" %}
3930 interface(MEMORY_INTER) %{
3931 base($reg);
3932 index(0x0);
3933 scale(0x0);
3934 disp(0x0);
3935 %}
3936 %}
3938 // Indirect with Offset
3939 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3940 constraint(ALLOC_IN_RC(sp_ptr_reg));
3941 match(AddP reg offset);
3943 op_cost(100);
3944 format %{ "[$reg + $offset]" %}
3945 interface(MEMORY_INTER) %{
3946 base($reg);
3947 index(0x0);
3948 scale(0x0);
3949 disp($offset);
3950 %}
3951 %}
3953 // Note: Intel has a swapped version also, like this:
3954 //operand indOffsetX(iRegI reg, immP offset) %{
3955 // constraint(ALLOC_IN_RC(int_reg));
3956 // match(AddP offset reg);
3957 //
3958 // op_cost(100);
3959 // format %{ "[$reg + $offset]" %}
3960 // interface(MEMORY_INTER) %{
3961 // base($reg);
3962 // index(0x0);
3963 // scale(0x0);
3964 // disp($offset);
3965 // %}
3966 //%}
3967 //// However, it doesn't make sense for SPARC, since
3968 // we have no particularly good way to embed oops in
3969 // single instructions.
3971 // Indirect with Register Index
3972 operand indIndex(iRegP addr, iRegX index) %{
3973 constraint(ALLOC_IN_RC(ptr_reg));
3974 match(AddP addr index);
3976 op_cost(100);
3977 format %{ "[$addr + $index]" %}
3978 interface(MEMORY_INTER) %{
3979 base($addr);
3980 index($index);
3981 scale(0x0);
3982 disp(0x0);
3983 %}
3984 %}
3986 //----------Special Memory Operands--------------------------------------------
3987 // Stack Slot Operand - This operand is used for loading and storing temporary
3988 // values on the stack where a match requires a value to
3989 // flow through memory.
3990 operand stackSlotI(sRegI reg) %{
3991 constraint(ALLOC_IN_RC(stack_slots));
3992 op_cost(100);
3993 //match(RegI);
3994 format %{ "[$reg]" %}
3995 interface(MEMORY_INTER) %{
3996 base(0xE); // R_SP
3997 index(0x0);
3998 scale(0x0);
3999 disp($reg); // Stack Offset
4000 %}
4001 %}
4003 operand stackSlotP(sRegP reg) %{
4004 constraint(ALLOC_IN_RC(stack_slots));
4005 op_cost(100);
4006 //match(RegP);
4007 format %{ "[$reg]" %}
4008 interface(MEMORY_INTER) %{
4009 base(0xE); // R_SP
4010 index(0x0);
4011 scale(0x0);
4012 disp($reg); // Stack Offset
4013 %}
4014 %}
4016 operand stackSlotF(sRegF reg) %{
4017 constraint(ALLOC_IN_RC(stack_slots));
4018 op_cost(100);
4019 //match(RegF);
4020 format %{ "[$reg]" %}
4021 interface(MEMORY_INTER) %{
4022 base(0xE); // R_SP
4023 index(0x0);
4024 scale(0x0);
4025 disp($reg); // Stack Offset
4026 %}
4027 %}
4028 operand stackSlotD(sRegD reg) %{
4029 constraint(ALLOC_IN_RC(stack_slots));
4030 op_cost(100);
4031 //match(RegD);
4032 format %{ "[$reg]" %}
4033 interface(MEMORY_INTER) %{
4034 base(0xE); // R_SP
4035 index(0x0);
4036 scale(0x0);
4037 disp($reg); // Stack Offset
4038 %}
4039 %}
4040 operand stackSlotL(sRegL reg) %{
4041 constraint(ALLOC_IN_RC(stack_slots));
4042 op_cost(100);
4043 //match(RegL);
4044 format %{ "[$reg]" %}
4045 interface(MEMORY_INTER) %{
4046 base(0xE); // R_SP
4047 index(0x0);
4048 scale(0x0);
4049 disp($reg); // Stack Offset
4050 %}
4051 %}
4053 // Operands for expressing Control Flow
4054 // NOTE: Label is a predefined operand which should not be redefined in
4055 // the AD file. It is generically handled within the ADLC.
4057 //----------Conditional Branch Operands----------------------------------------
4058 // Comparison Op - This is the operation of the comparison, and is limited to
4059 // the following set of codes:
4060 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4061 //
4062 // Other attributes of the comparison, such as unsignedness, are specified
4063 // by the comparison instruction that sets a condition code flags register.
4064 // That result is represented by a flags operand whose subtype is appropriate
4065 // to the unsignedness (etc.) of the comparison.
4066 //
4067 // Later, the instruction which matches both the Comparison Op (a Bool) and
4068 // the flags (produced by the Cmp) specifies the coding of the comparison op
4069 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4071 operand cmpOp() %{
4072 match(Bool);
4074 format %{ "" %}
4075 interface(COND_INTER) %{
4076 equal(0x1);
4077 not_equal(0x9);
4078 less(0x3);
4079 greater_equal(0xB);
4080 less_equal(0x2);
4081 greater(0xA);
4082 %}
4083 %}
4085 // Comparison Op, unsigned
4086 operand cmpOpU() %{
4087 match(Bool);
4089 format %{ "u" %}
4090 interface(COND_INTER) %{
4091 equal(0x1);
4092 not_equal(0x9);
4093 less(0x5);
4094 greater_equal(0xD);
4095 less_equal(0x4);
4096 greater(0xC);
4097 %}
4098 %}
4100 // Comparison Op, pointer (same as unsigned)
4101 operand cmpOpP() %{
4102 match(Bool);
4104 format %{ "p" %}
4105 interface(COND_INTER) %{
4106 equal(0x1);
4107 not_equal(0x9);
4108 less(0x5);
4109 greater_equal(0xD);
4110 less_equal(0x4);
4111 greater(0xC);
4112 %}
4113 %}
4115 // Comparison Op, branch-register encoding
4116 operand cmpOp_reg() %{
4117 match(Bool);
4119 format %{ "" %}
4120 interface(COND_INTER) %{
4121 equal (0x1);
4122 not_equal (0x5);
4123 less (0x3);
4124 greater_equal(0x7);
4125 less_equal (0x2);
4126 greater (0x6);
4127 %}
4128 %}
4130 // Comparison Code, floating, unordered same as less
4131 operand cmpOpF() %{
4132 match(Bool);
4134 format %{ "fl" %}
4135 interface(COND_INTER) %{
4136 equal(0x9);
4137 not_equal(0x1);
4138 less(0x3);
4139 greater_equal(0xB);
4140 less_equal(0xE);
4141 greater(0x6);
4142 %}
4143 %}
4145 // Used by long compare
4146 operand cmpOp_commute() %{
4147 match(Bool);
4149 format %{ "" %}
4150 interface(COND_INTER) %{
4151 equal(0x1);
4152 not_equal(0x9);
4153 less(0xA);
4154 greater_equal(0x2);
4155 less_equal(0xB);
4156 greater(0x3);
4157 %}
4158 %}
4160 //----------OPERAND CLASSES----------------------------------------------------
4161 // Operand Classes are groups of operands that are used to simplify
4162 // instruction definitions by not requiring the AD writer to specify separate
4163 // instructions for every form of operand when the instruction accepts
4164 // multiple operand types with the same basic encoding and format. The classic
4165 // case of this is memory operands.
4166 // Indirect is not included since its use is limited to Compare & Swap
4167 opclass memory( indirect, indOffset13, indIndex );
4169 //----------PIPELINE-----------------------------------------------------------
4170 pipeline %{
4172 //----------ATTRIBUTES---------------------------------------------------------
4173 attributes %{
4174 fixed_size_instructions; // Fixed size instructions
4175 branch_has_delay_slot; // Branch has delay slot following
4176 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4177 instruction_unit_size = 4; // An instruction is 4 bytes long
4178 instruction_fetch_unit_size = 16; // The processor fetches one line
4179 instruction_fetch_units = 1; // of 16 bytes
4181 // List of nop instructions
4182 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4183 %}
4185 //----------RESOURCES----------------------------------------------------------
4186 // Resources are the functional units available to the machine
4187 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4189 //----------PIPELINE DESCRIPTION-----------------------------------------------
4190 // Pipeline Description specifies the stages in the machine's pipeline
4192 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4194 //----------PIPELINE CLASSES---------------------------------------------------
4195 // Pipeline Classes describe the stages in which input and output are
4196 // referenced by the hardware pipeline.
4198 // Integer ALU reg-reg operation
4199 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4200 single_instruction;
4201 dst : E(write);
4202 src1 : R(read);
4203 src2 : R(read);
4204 IALU : R;
4205 %}
4207 // Integer ALU reg-reg long operation
4208 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4209 instruction_count(2);
4210 dst : E(write);
4211 src1 : R(read);
4212 src2 : R(read);
4213 IALU : R;
4214 IALU : R;
4215 %}
4217 // Integer ALU reg-reg long dependent operation
4218 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4219 instruction_count(1); multiple_bundles;
4220 dst : E(write);
4221 src1 : R(read);
4222 src2 : R(read);
4223 cr : E(write);
4224 IALU : R(2);
4225 %}
4227 // Integer ALU reg-imm operaion
4228 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4229 single_instruction;
4230 dst : E(write);
4231 src1 : R(read);
4232 IALU : R;
4233 %}
4235 // Integer ALU reg-reg operation with condition code
4236 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4237 single_instruction;
4238 dst : E(write);
4239 cr : E(write);
4240 src1 : R(read);
4241 src2 : R(read);
4242 IALU : R;
4243 %}
4245 // Integer ALU reg-imm operation with condition code
4246 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4247 single_instruction;
4248 dst : E(write);
4249 cr : E(write);
4250 src1 : R(read);
4251 IALU : R;
4252 %}
4254 // Integer ALU zero-reg operation
4255 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4256 single_instruction;
4257 dst : E(write);
4258 src2 : R(read);
4259 IALU : R;
4260 %}
4262 // Integer ALU zero-reg operation with condition code only
4263 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4264 single_instruction;
4265 cr : E(write);
4266 src : R(read);
4267 IALU : R;
4268 %}
4270 // Integer ALU reg-reg operation with condition code only
4271 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4272 single_instruction;
4273 cr : E(write);
4274 src1 : R(read);
4275 src2 : R(read);
4276 IALU : R;
4277 %}
4279 // Integer ALU reg-imm operation with condition code only
4280 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4281 single_instruction;
4282 cr : E(write);
4283 src1 : R(read);
4284 IALU : R;
4285 %}
4287 // Integer ALU reg-reg-zero operation with condition code only
4288 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4289 single_instruction;
4290 cr : E(write);
4291 src1 : R(read);
4292 src2 : R(read);
4293 IALU : R;
4294 %}
4296 // Integer ALU reg-imm-zero operation with condition code only
4297 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4298 single_instruction;
4299 cr : E(write);
4300 src1 : R(read);
4301 IALU : R;
4302 %}
4304 // Integer ALU reg-reg operation with condition code, src1 modified
4305 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4306 single_instruction;
4307 cr : E(write);
4308 src1 : E(write);
4309 src1 : R(read);
4310 src2 : R(read);
4311 IALU : R;
4312 %}
4314 // Integer ALU reg-imm operation with condition code, src1 modified
4315 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4316 single_instruction;
4317 cr : E(write);
4318 src1 : E(write);
4319 src1 : R(read);
4320 IALU : R;
4321 %}
4323 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4324 multiple_bundles;
4325 dst : E(write)+4;
4326 cr : E(write);
4327 src1 : R(read);
4328 src2 : R(read);
4329 IALU : R(3);
4330 BR : R(2);
4331 %}
4333 // Integer ALU operation
4334 pipe_class ialu_none(iRegI dst) %{
4335 single_instruction;
4336 dst : E(write);
4337 IALU : R;
4338 %}
4340 // Integer ALU reg operation
4341 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4342 single_instruction; may_have_no_code;
4343 dst : E(write);
4344 src : R(read);
4345 IALU : R;
4346 %}
4348 // Integer ALU reg conditional operation
4349 // This instruction has a 1 cycle stall, and cannot execute
4350 // in the same cycle as the instruction setting the condition
4351 // code. We kludge this by pretending to read the condition code
4352 // 1 cycle earlier, and by marking the functional units as busy
4353 // for 2 cycles with the result available 1 cycle later than
4354 // is really the case.
4355 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4356 single_instruction;
4357 op2_out : C(write);
4358 op1 : R(read);
4359 cr : R(read); // This is really E, with a 1 cycle stall
4360 BR : R(2);
4361 MS : R(2);
4362 %}
4364 #ifdef _LP64
4365 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4366 instruction_count(1); multiple_bundles;
4367 dst : C(write)+1;
4368 src : R(read)+1;
4369 IALU : R(1);
4370 BR : E(2);
4371 MS : E(2);
4372 %}
4373 #endif
4375 // Integer ALU reg operation
4376 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4377 single_instruction; may_have_no_code;
4378 dst : E(write);
4379 src : R(read);
4380 IALU : R;
4381 %}
4382 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4383 single_instruction; may_have_no_code;
4384 dst : E(write);
4385 src : R(read);
4386 IALU : R;
4387 %}
4389 // Two integer ALU reg operations
4390 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4391 instruction_count(2);
4392 dst : E(write);
4393 src : R(read);
4394 A0 : R;
4395 A1 : R;
4396 %}
4398 // Two integer ALU reg operations
4399 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4400 instruction_count(2); may_have_no_code;
4401 dst : E(write);
4402 src : R(read);
4403 A0 : R;
4404 A1 : R;
4405 %}
4407 // Integer ALU imm operation
4408 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4409 single_instruction;
4410 dst : E(write);
4411 IALU : R;
4412 %}
4414 // Integer ALU reg-reg with carry operation
4415 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4416 single_instruction;
4417 dst : E(write);
4418 src1 : R(read);
4419 src2 : R(read);
4420 IALU : R;
4421 %}
4423 // Integer ALU cc operation
4424 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4425 single_instruction;
4426 dst : E(write);
4427 cc : R(read);
4428 IALU : R;
4429 %}
4431 // Integer ALU cc / second IALU operation
4432 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4433 instruction_count(1); multiple_bundles;
4434 dst : E(write)+1;
4435 src : R(read);
4436 IALU : R;
4437 %}
4439 // Integer ALU cc / second IALU operation
4440 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4441 instruction_count(1); multiple_bundles;
4442 dst : E(write)+1;
4443 p : R(read);
4444 q : R(read);
4445 IALU : R;
4446 %}
4448 // Integer ALU hi-lo-reg operation
4449 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4450 instruction_count(1); multiple_bundles;
4451 dst : E(write)+1;
4452 IALU : R(2);
4453 %}
4455 // Float ALU hi-lo-reg operation (with temp)
4456 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4457 instruction_count(1); multiple_bundles;
4458 dst : E(write)+1;
4459 IALU : R(2);
4460 %}
4462 // Long Constant
4463 pipe_class loadConL( iRegL dst, immL src ) %{
4464 instruction_count(2); multiple_bundles;
4465 dst : E(write)+1;
4466 IALU : R(2);
4467 IALU : R(2);
4468 %}
4470 // Pointer Constant
4471 pipe_class loadConP( iRegP dst, immP src ) %{
4472 instruction_count(0); multiple_bundles;
4473 fixed_latency(6);
4474 %}
4476 // Polling Address
4477 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4478 #ifdef _LP64
4479 instruction_count(0); multiple_bundles;
4480 fixed_latency(6);
4481 #else
4482 dst : E(write);
4483 IALU : R;
4484 #endif
4485 %}
4487 // Long Constant small
4488 pipe_class loadConLlo( iRegL dst, immL src ) %{
4489 instruction_count(2);
4490 dst : E(write);
4491 IALU : R;
4492 IALU : R;
4493 %}
4495 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4496 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4497 instruction_count(1); multiple_bundles;
4498 src : R(read);
4499 dst : M(write)+1;
4500 IALU : R;
4501 MS : E;
4502 %}
4504 // Integer ALU nop operation
4505 pipe_class ialu_nop() %{
4506 single_instruction;
4507 IALU : R;
4508 %}
4510 // Integer ALU nop operation
4511 pipe_class ialu_nop_A0() %{
4512 single_instruction;
4513 A0 : R;
4514 %}
4516 // Integer ALU nop operation
4517 pipe_class ialu_nop_A1() %{
4518 single_instruction;
4519 A1 : R;
4520 %}
4522 // Integer Multiply reg-reg operation
4523 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4524 single_instruction;
4525 dst : E(write);
4526 src1 : R(read);
4527 src2 : R(read);
4528 MS : R(5);
4529 %}
4531 // Integer Multiply reg-imm operation
4532 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4533 single_instruction;
4534 dst : E(write);
4535 src1 : R(read);
4536 MS : R(5);
4537 %}
4539 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4540 single_instruction;
4541 dst : E(write)+4;
4542 src1 : R(read);
4543 src2 : R(read);
4544 MS : R(6);
4545 %}
4547 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4548 single_instruction;
4549 dst : E(write)+4;
4550 src1 : R(read);
4551 MS : R(6);
4552 %}
4554 // Integer Divide reg-reg
4555 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4556 instruction_count(1); multiple_bundles;
4557 dst : E(write);
4558 temp : E(write);
4559 src1 : R(read);
4560 src2 : R(read);
4561 temp : R(read);
4562 MS : R(38);
4563 %}
4565 // Integer Divide reg-imm
4566 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4567 instruction_count(1); multiple_bundles;
4568 dst : E(write);
4569 temp : E(write);
4570 src1 : R(read);
4571 temp : R(read);
4572 MS : R(38);
4573 %}
4575 // Long Divide
4576 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4577 dst : E(write)+71;
4578 src1 : R(read);
4579 src2 : R(read)+1;
4580 MS : R(70);
4581 %}
4583 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4584 dst : E(write)+71;
4585 src1 : R(read);
4586 MS : R(70);
4587 %}
4589 // Floating Point Add Float
4590 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4591 single_instruction;
4592 dst : X(write);
4593 src1 : E(read);
4594 src2 : E(read);
4595 FA : R;
4596 %}
4598 // Floating Point Add Double
4599 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4600 single_instruction;
4601 dst : X(write);
4602 src1 : E(read);
4603 src2 : E(read);
4604 FA : R;
4605 %}
4607 // Floating Point Conditional Move based on integer flags
4608 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4609 single_instruction;
4610 dst : X(write);
4611 src : E(read);
4612 cr : R(read);
4613 FA : R(2);
4614 BR : R(2);
4615 %}
4617 // Floating Point Conditional Move based on integer flags
4618 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4619 single_instruction;
4620 dst : X(write);
4621 src : E(read);
4622 cr : R(read);
4623 FA : R(2);
4624 BR : R(2);
4625 %}
4627 // Floating Point Multiply Float
4628 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4629 single_instruction;
4630 dst : X(write);
4631 src1 : E(read);
4632 src2 : E(read);
4633 FM : R;
4634 %}
4636 // Floating Point Multiply Double
4637 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4638 single_instruction;
4639 dst : X(write);
4640 src1 : E(read);
4641 src2 : E(read);
4642 FM : R;
4643 %}
4645 // Floating Point Divide Float
4646 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4647 single_instruction;
4648 dst : X(write);
4649 src1 : E(read);
4650 src2 : E(read);
4651 FM : R;
4652 FDIV : C(14);
4653 %}
4655 // Floating Point Divide Double
4656 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4657 single_instruction;
4658 dst : X(write);
4659 src1 : E(read);
4660 src2 : E(read);
4661 FM : R;
4662 FDIV : C(17);
4663 %}
4665 // Floating Point Move/Negate/Abs Float
4666 pipe_class faddF_reg(regF dst, regF src) %{
4667 single_instruction;
4668 dst : W(write);
4669 src : E(read);
4670 FA : R(1);
4671 %}
4673 // Floating Point Move/Negate/Abs Double
4674 pipe_class faddD_reg(regD dst, regD src) %{
4675 single_instruction;
4676 dst : W(write);
4677 src : E(read);
4678 FA : R;
4679 %}
4681 // Floating Point Convert F->D
4682 pipe_class fcvtF2D(regD dst, regF src) %{
4683 single_instruction;
4684 dst : X(write);
4685 src : E(read);
4686 FA : R;
4687 %}
4689 // Floating Point Convert I->D
4690 pipe_class fcvtI2D(regD dst, regF src) %{
4691 single_instruction;
4692 dst : X(write);
4693 src : E(read);
4694 FA : R;
4695 %}
4697 // Floating Point Convert LHi->D
4698 pipe_class fcvtLHi2D(regD dst, regD src) %{
4699 single_instruction;
4700 dst : X(write);
4701 src : E(read);
4702 FA : R;
4703 %}
4705 // Floating Point Convert L->D
4706 pipe_class fcvtL2D(regD dst, regF src) %{
4707 single_instruction;
4708 dst : X(write);
4709 src : E(read);
4710 FA : R;
4711 %}
4713 // Floating Point Convert L->F
4714 pipe_class fcvtL2F(regD dst, regF src) %{
4715 single_instruction;
4716 dst : X(write);
4717 src : E(read);
4718 FA : R;
4719 %}
4721 // Floating Point Convert D->F
4722 pipe_class fcvtD2F(regD dst, regF src) %{
4723 single_instruction;
4724 dst : X(write);
4725 src : E(read);
4726 FA : R;
4727 %}
4729 // Floating Point Convert I->L
4730 pipe_class fcvtI2L(regD dst, regF src) %{
4731 single_instruction;
4732 dst : X(write);
4733 src : E(read);
4734 FA : R;
4735 %}
4737 // Floating Point Convert D->F
4738 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4739 instruction_count(1); multiple_bundles;
4740 dst : X(write)+6;
4741 src : E(read);
4742 FA : R;
4743 %}
4745 // Floating Point Convert D->L
4746 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4747 instruction_count(1); multiple_bundles;
4748 dst : X(write)+6;
4749 src : E(read);
4750 FA : R;
4751 %}
4753 // Floating Point Convert F->I
4754 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4755 instruction_count(1); multiple_bundles;
4756 dst : X(write)+6;
4757 src : E(read);
4758 FA : R;
4759 %}
4761 // Floating Point Convert F->L
4762 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4763 instruction_count(1); multiple_bundles;
4764 dst : X(write)+6;
4765 src : E(read);
4766 FA : R;
4767 %}
4769 // Floating Point Convert I->F
4770 pipe_class fcvtI2F(regF dst, regF src) %{
4771 single_instruction;
4772 dst : X(write);
4773 src : E(read);
4774 FA : R;
4775 %}
4777 // Floating Point Compare
4778 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4779 single_instruction;
4780 cr : X(write);
4781 src1 : E(read);
4782 src2 : E(read);
4783 FA : R;
4784 %}
4786 // Floating Point Compare
4787 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4788 single_instruction;
4789 cr : X(write);
4790 src1 : E(read);
4791 src2 : E(read);
4792 FA : R;
4793 %}
4795 // Floating Add Nop
4796 pipe_class fadd_nop() %{
4797 single_instruction;
4798 FA : R;
4799 %}
4801 // Integer Store to Memory
4802 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4803 single_instruction;
4804 mem : R(read);
4805 src : C(read);
4806 MS : R;
4807 %}
4809 // Integer Store to Memory
4810 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4811 single_instruction;
4812 mem : R(read);
4813 src : C(read);
4814 MS : R;
4815 %}
4817 // Integer Store Zero to Memory
4818 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4819 single_instruction;
4820 mem : R(read);
4821 MS : R;
4822 %}
4824 // Special Stack Slot Store
4825 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4826 single_instruction;
4827 stkSlot : R(read);
4828 src : C(read);
4829 MS : R;
4830 %}
4832 // Special Stack Slot Store
4833 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4834 instruction_count(2); multiple_bundles;
4835 stkSlot : R(read);
4836 src : C(read);
4837 MS : R(2);
4838 %}
4840 // Float Store
4841 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4842 single_instruction;
4843 mem : R(read);
4844 src : C(read);
4845 MS : R;
4846 %}
4848 // Float Store
4849 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4850 single_instruction;
4851 mem : R(read);
4852 MS : R;
4853 %}
4855 // Double Store
4856 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4857 instruction_count(1);
4858 mem : R(read);
4859 src : C(read);
4860 MS : R;
4861 %}
4863 // Double Store
4864 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4865 single_instruction;
4866 mem : R(read);
4867 MS : R;
4868 %}
4870 // Special Stack Slot Float Store
4871 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4872 single_instruction;
4873 stkSlot : R(read);
4874 src : C(read);
4875 MS : R;
4876 %}
4878 // Special Stack Slot Double Store
4879 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4880 single_instruction;
4881 stkSlot : R(read);
4882 src : C(read);
4883 MS : R;
4884 %}
4886 // Integer Load (when sign bit propagation not needed)
4887 pipe_class iload_mem(iRegI dst, memory mem) %{
4888 single_instruction;
4889 mem : R(read);
4890 dst : C(write);
4891 MS : R;
4892 %}
4894 // Integer Load from stack operand
4895 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4896 single_instruction;
4897 mem : R(read);
4898 dst : C(write);
4899 MS : R;
4900 %}
4902 // Integer Load (when sign bit propagation or masking is needed)
4903 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4904 single_instruction;
4905 mem : R(read);
4906 dst : M(write);
4907 MS : R;
4908 %}
4910 // Float Load
4911 pipe_class floadF_mem(regF dst, memory mem) %{
4912 single_instruction;
4913 mem : R(read);
4914 dst : M(write);
4915 MS : R;
4916 %}
4918 // Float Load
4919 pipe_class floadD_mem(regD dst, memory mem) %{
4920 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4921 mem : R(read);
4922 dst : M(write);
4923 MS : R;
4924 %}
4926 // Float Load
4927 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
4928 single_instruction;
4929 stkSlot : R(read);
4930 dst : M(write);
4931 MS : R;
4932 %}
4934 // Float Load
4935 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
4936 single_instruction;
4937 stkSlot : R(read);
4938 dst : M(write);
4939 MS : R;
4940 %}
4942 // Memory Nop
4943 pipe_class mem_nop() %{
4944 single_instruction;
4945 MS : R;
4946 %}
4948 pipe_class sethi(iRegP dst, immI src) %{
4949 single_instruction;
4950 dst : E(write);
4951 IALU : R;
4952 %}
4954 pipe_class loadPollP(iRegP poll) %{
4955 single_instruction;
4956 poll : R(read);
4957 MS : R;
4958 %}
4960 pipe_class br(Universe br, label labl) %{
4961 single_instruction_with_delay_slot;
4962 BR : R;
4963 %}
4965 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
4966 single_instruction_with_delay_slot;
4967 cr : E(read);
4968 BR : R;
4969 %}
4971 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
4972 single_instruction_with_delay_slot;
4973 op1 : E(read);
4974 BR : R;
4975 MS : R;
4976 %}
4978 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
4979 single_instruction_with_delay_slot;
4980 cr : E(read);
4981 BR : R;
4982 %}
4984 pipe_class br_nop() %{
4985 single_instruction;
4986 BR : R;
4987 %}
4989 pipe_class simple_call(method meth) %{
4990 instruction_count(2); multiple_bundles; force_serialization;
4991 fixed_latency(100);
4992 BR : R(1);
4993 MS : R(1);
4994 A0 : R(1);
4995 %}
4997 pipe_class compiled_call(method meth) %{
4998 instruction_count(1); multiple_bundles; force_serialization;
4999 fixed_latency(100);
5000 MS : R(1);
5001 %}
5003 pipe_class call(method meth) %{
5004 instruction_count(0); multiple_bundles; force_serialization;
5005 fixed_latency(100);
5006 %}
5008 pipe_class tail_call(Universe ignore, label labl) %{
5009 single_instruction; has_delay_slot;
5010 fixed_latency(100);
5011 BR : R(1);
5012 MS : R(1);
5013 %}
5015 pipe_class ret(Universe ignore) %{
5016 single_instruction; has_delay_slot;
5017 BR : R(1);
5018 MS : R(1);
5019 %}
5021 pipe_class ret_poll(g3RegP poll) %{
5022 instruction_count(3); has_delay_slot;
5023 poll : E(read);
5024 MS : R;
5025 %}
5027 // The real do-nothing guy
5028 pipe_class empty( ) %{
5029 instruction_count(0);
5030 %}
5032 pipe_class long_memory_op() %{
5033 instruction_count(0); multiple_bundles; force_serialization;
5034 fixed_latency(25);
5035 MS : R(1);
5036 %}
5038 // Check-cast
5039 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5040 array : R(read);
5041 match : R(read);
5042 IALU : R(2);
5043 BR : R(2);
5044 MS : R;
5045 %}
5047 // Convert FPU flags into +1,0,-1
5048 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5049 src1 : E(read);
5050 src2 : E(read);
5051 dst : E(write);
5052 FA : R;
5053 MS : R(2);
5054 BR : R(2);
5055 %}
5057 // Compare for p < q, and conditionally add y
5058 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5059 p : E(read);
5060 q : E(read);
5061 y : E(read);
5062 IALU : R(3)
5063 %}
5065 // Perform a compare, then move conditionally in a branch delay slot.
5066 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5067 src2 : E(read);
5068 srcdst : E(read);
5069 IALU : R;
5070 BR : R;
5071 %}
5073 // Define the class for the Nop node
5074 define %{
5075 MachNop = ialu_nop;
5076 %}
5078 %}
5080 //----------INSTRUCTIONS-------------------------------------------------------
5082 //------------Special Stack Slot instructions - no match rules-----------------
5083 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5084 // No match rule to avoid chain rule match.
5085 effect(DEF dst, USE src);
5086 ins_cost(MEMORY_REF_COST);
5087 size(4);
5088 format %{ "LDF $src,$dst\t! stkI to regF" %}
5089 opcode(Assembler::ldf_op3);
5090 ins_encode(simple_form3_mem_reg(src, dst));
5091 ins_pipe(floadF_stk);
5092 %}
5094 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5095 // No match rule to avoid chain rule match.
5096 effect(DEF dst, USE src);
5097 ins_cost(MEMORY_REF_COST);
5098 size(4);
5099 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5100 opcode(Assembler::lddf_op3);
5101 ins_encode(simple_form3_mem_reg(src, dst));
5102 ins_pipe(floadD_stk);
5103 %}
5105 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5106 // No match rule to avoid chain rule match.
5107 effect(DEF dst, USE src);
5108 ins_cost(MEMORY_REF_COST);
5109 size(4);
5110 format %{ "STF $src,$dst\t! regF to stkI" %}
5111 opcode(Assembler::stf_op3);
5112 ins_encode(simple_form3_mem_reg(dst, src));
5113 ins_pipe(fstoreF_stk_reg);
5114 %}
5116 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5117 // No match rule to avoid chain rule match.
5118 effect(DEF dst, USE src);
5119 ins_cost(MEMORY_REF_COST);
5120 size(4);
5121 format %{ "STDF $src,$dst\t! regD to stkL" %}
5122 opcode(Assembler::stdf_op3);
5123 ins_encode(simple_form3_mem_reg(dst, src));
5124 ins_pipe(fstoreD_stk_reg);
5125 %}
5127 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5128 effect(DEF dst, USE src);
5129 ins_cost(MEMORY_REF_COST*2);
5130 size(8);
5131 format %{ "STW $src,$dst.hi\t! long\n\t"
5132 "STW R_G0,$dst.lo" %}
5133 opcode(Assembler::stw_op3);
5134 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5135 ins_pipe(lstoreI_stk_reg);
5136 %}
5138 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5139 // No match rule to avoid chain rule match.
5140 effect(DEF dst, USE src);
5141 ins_cost(MEMORY_REF_COST);
5142 size(4);
5143 format %{ "STX $src,$dst\t! regL to stkD" %}
5144 opcode(Assembler::stx_op3);
5145 ins_encode(simple_form3_mem_reg( dst, src ) );
5146 ins_pipe(istore_stk_reg);
5147 %}
5149 //---------- Chain stack slots between similar types --------
5151 // Load integer from stack slot
5152 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5153 match(Set dst src);
5154 ins_cost(MEMORY_REF_COST);
5156 size(4);
5157 format %{ "LDUW $src,$dst\t!stk" %}
5158 opcode(Assembler::lduw_op3);
5159 ins_encode(simple_form3_mem_reg( src, dst ) );
5160 ins_pipe(iload_mem);
5161 %}
5163 // Store integer to stack slot
5164 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5165 match(Set dst src);
5166 ins_cost(MEMORY_REF_COST);
5168 size(4);
5169 format %{ "STW $src,$dst\t!stk" %}
5170 opcode(Assembler::stw_op3);
5171 ins_encode(simple_form3_mem_reg( dst, src ) );
5172 ins_pipe(istore_mem_reg);
5173 %}
5175 // Load long from stack slot
5176 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5177 match(Set dst src);
5179 ins_cost(MEMORY_REF_COST);
5180 size(4);
5181 format %{ "LDX $src,$dst\t! long" %}
5182 opcode(Assembler::ldx_op3);
5183 ins_encode(simple_form3_mem_reg( src, dst ) );
5184 ins_pipe(iload_mem);
5185 %}
5187 // Store long to stack slot
5188 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5189 match(Set dst src);
5191 ins_cost(MEMORY_REF_COST);
5192 size(4);
5193 format %{ "STX $src,$dst\t! long" %}
5194 opcode(Assembler::stx_op3);
5195 ins_encode(simple_form3_mem_reg( dst, src ) );
5196 ins_pipe(istore_mem_reg);
5197 %}
5199 #ifdef _LP64
5200 // Load pointer from stack slot, 64-bit encoding
5201 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5202 match(Set dst src);
5203 ins_cost(MEMORY_REF_COST);
5204 size(4);
5205 format %{ "LDX $src,$dst\t!ptr" %}
5206 opcode(Assembler::ldx_op3);
5207 ins_encode(simple_form3_mem_reg( src, dst ) );
5208 ins_pipe(iload_mem);
5209 %}
5211 // Store pointer to stack slot
5212 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5213 match(Set dst src);
5214 ins_cost(MEMORY_REF_COST);
5215 size(4);
5216 format %{ "STX $src,$dst\t!ptr" %}
5217 opcode(Assembler::stx_op3);
5218 ins_encode(simple_form3_mem_reg( dst, src ) );
5219 ins_pipe(istore_mem_reg);
5220 %}
5221 #else // _LP64
5222 // Load pointer from stack slot, 32-bit encoding
5223 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5224 match(Set dst src);
5225 ins_cost(MEMORY_REF_COST);
5226 format %{ "LDUW $src,$dst\t!ptr" %}
5227 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5228 ins_encode(simple_form3_mem_reg( src, dst ) );
5229 ins_pipe(iload_mem);
5230 %}
5232 // Store pointer to stack slot
5233 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5234 match(Set dst src);
5235 ins_cost(MEMORY_REF_COST);
5236 format %{ "STW $src,$dst\t!ptr" %}
5237 opcode(Assembler::stw_op3, Assembler::ldst_op);
5238 ins_encode(simple_form3_mem_reg( dst, src ) );
5239 ins_pipe(istore_mem_reg);
5240 %}
5241 #endif // _LP64
5243 //------------Special Nop instructions for bundling - no match rules-----------
5244 // Nop using the A0 functional unit
5245 instruct Nop_A0() %{
5246 ins_cost(0);
5248 format %{ "NOP ! Alu Pipeline" %}
5249 opcode(Assembler::or_op3, Assembler::arith_op);
5250 ins_encode( form2_nop() );
5251 ins_pipe(ialu_nop_A0);
5252 %}
5254 // Nop using the A1 functional unit
5255 instruct Nop_A1( ) %{
5256 ins_cost(0);
5258 format %{ "NOP ! Alu Pipeline" %}
5259 opcode(Assembler::or_op3, Assembler::arith_op);
5260 ins_encode( form2_nop() );
5261 ins_pipe(ialu_nop_A1);
5262 %}
5264 // Nop using the memory functional unit
5265 instruct Nop_MS( ) %{
5266 ins_cost(0);
5268 format %{ "NOP ! Memory Pipeline" %}
5269 ins_encode( emit_mem_nop );
5270 ins_pipe(mem_nop);
5271 %}
5273 // Nop using the floating add functional unit
5274 instruct Nop_FA( ) %{
5275 ins_cost(0);
5277 format %{ "NOP ! Floating Add Pipeline" %}
5278 ins_encode( emit_fadd_nop );
5279 ins_pipe(fadd_nop);
5280 %}
5282 // Nop using the branch functional unit
5283 instruct Nop_BR( ) %{
5284 ins_cost(0);
5286 format %{ "NOP ! Branch Pipeline" %}
5287 ins_encode( emit_br_nop );
5288 ins_pipe(br_nop);
5289 %}
5291 //----------Load/Store/Move Instructions---------------------------------------
5292 //----------Load Instructions--------------------------------------------------
5293 // Load Byte (8bit signed)
5294 instruct loadB(iRegI dst, memory mem) %{
5295 match(Set dst (LoadB mem));
5296 ins_cost(MEMORY_REF_COST);
5298 size(4);
5299 format %{ "LDSB $mem,$dst\t! byte" %}
5300 opcode(Assembler::ldsb_op3);
5301 ins_encode(simple_form3_mem_reg( mem, dst ) );
5302 ins_pipe(iload_mask_mem);
5303 %}
5305 // Load Byte (8bit signed) into a Long Register
5306 instruct loadB2L(iRegL dst, memory mem) %{
5307 match(Set dst (ConvI2L (LoadB mem)));
5308 ins_cost(MEMORY_REF_COST);
5310 size(4);
5311 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5312 opcode(Assembler::ldsb_op3);
5313 ins_encode(simple_form3_mem_reg( mem, dst ) );
5314 ins_pipe(iload_mask_mem);
5315 %}
5317 // Load Unsigned Byte (8bit UNsigned) into an int reg
5318 instruct loadUB(iRegI dst, memory mem) %{
5319 match(Set dst (LoadUB mem));
5320 ins_cost(MEMORY_REF_COST);
5322 size(4);
5323 format %{ "LDUB $mem,$dst\t! ubyte" %}
5324 opcode(Assembler::ldub_op3);
5325 ins_encode(simple_form3_mem_reg( mem, dst ) );
5326 ins_pipe(iload_mask_mem);
5327 %}
5329 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5330 instruct loadUB2L(iRegL dst, memory mem) %{
5331 match(Set dst (ConvI2L (LoadUB mem)));
5332 ins_cost(MEMORY_REF_COST);
5334 size(4);
5335 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5336 opcode(Assembler::ldub_op3);
5337 ins_encode(simple_form3_mem_reg( mem, dst ) );
5338 ins_pipe(iload_mask_mem);
5339 %}
5341 // Load Short (16bit signed)
5342 instruct loadS(iRegI dst, memory mem) %{
5343 match(Set dst (LoadS mem));
5344 ins_cost(MEMORY_REF_COST);
5346 size(4);
5347 format %{ "LDSH $mem,$dst\t! short" %}
5348 opcode(Assembler::ldsh_op3);
5349 ins_encode(simple_form3_mem_reg( mem, dst ) );
5350 ins_pipe(iload_mask_mem);
5351 %}
5353 // Load Short (16bit signed) into a Long Register
5354 instruct loadS2L(iRegL dst, memory mem) %{
5355 match(Set dst (ConvI2L (LoadS mem)));
5356 ins_cost(MEMORY_REF_COST);
5358 size(4);
5359 format %{ "LDSH $mem,$dst\t! short -> long" %}
5360 opcode(Assembler::ldsh_op3);
5361 ins_encode(simple_form3_mem_reg( mem, dst ) );
5362 ins_pipe(iload_mask_mem);
5363 %}
5365 // Load Unsigned Short/Char (16bit UNsigned)
5366 instruct loadUS(iRegI dst, memory mem) %{
5367 match(Set dst (LoadUS mem));
5368 ins_cost(MEMORY_REF_COST);
5370 size(4);
5371 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5372 opcode(Assembler::lduh_op3);
5373 ins_encode(simple_form3_mem_reg( mem, dst ) );
5374 ins_pipe(iload_mask_mem);
5375 %}
5377 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5378 instruct loadUS2L(iRegL dst, memory mem) %{
5379 match(Set dst (ConvI2L (LoadUS mem)));
5380 ins_cost(MEMORY_REF_COST);
5382 size(4);
5383 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5384 opcode(Assembler::lduh_op3);
5385 ins_encode(simple_form3_mem_reg( mem, dst ) );
5386 ins_pipe(iload_mask_mem);
5387 %}
5389 // Load Integer
5390 instruct loadI(iRegI dst, memory mem) %{
5391 match(Set dst (LoadI mem));
5392 ins_cost(MEMORY_REF_COST);
5394 size(4);
5395 format %{ "LDUW $mem,$dst\t! int" %}
5396 opcode(Assembler::lduw_op3);
5397 ins_encode(simple_form3_mem_reg( mem, dst ) );
5398 ins_pipe(iload_mem);
5399 %}
5401 // Load Integer into a Long Register
5402 instruct loadI2L(iRegL dst, memory mem) %{
5403 match(Set dst (ConvI2L (LoadI mem)));
5404 ins_cost(MEMORY_REF_COST);
5406 size(4);
5407 format %{ "LDSW $mem,$dst\t! int -> long" %}
5408 opcode(Assembler::ldsw_op3);
5409 ins_encode(simple_form3_mem_reg( mem, dst ) );
5410 ins_pipe(iload_mem);
5411 %}
5413 // Load Unsigned Integer into a Long Register
5414 instruct loadUI2L(iRegL dst, memory mem) %{
5415 match(Set dst (LoadUI2L mem));
5416 ins_cost(MEMORY_REF_COST);
5418 size(4);
5419 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5420 opcode(Assembler::lduw_op3);
5421 ins_encode(simple_form3_mem_reg( mem, dst ) );
5422 ins_pipe(iload_mem);
5423 %}
5425 // Load Long - aligned
5426 instruct loadL(iRegL dst, memory mem ) %{
5427 match(Set dst (LoadL mem));
5428 ins_cost(MEMORY_REF_COST);
5430 size(4);
5431 format %{ "LDX $mem,$dst\t! long" %}
5432 opcode(Assembler::ldx_op3);
5433 ins_encode(simple_form3_mem_reg( mem, dst ) );
5434 ins_pipe(iload_mem);
5435 %}
5437 // Load Long - UNaligned
5438 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5439 match(Set dst (LoadL_unaligned mem));
5440 effect(KILL tmp);
5441 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5442 size(16);
5443 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5444 "\tLDUW $mem ,$dst\n"
5445 "\tSLLX #32, $dst, $dst\n"
5446 "\tOR $dst, R_O7, $dst" %}
5447 opcode(Assembler::lduw_op3);
5448 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5449 ins_pipe(iload_mem);
5450 %}
5452 // Load Aligned Packed Byte into a Double Register
5453 instruct loadA8B(regD dst, memory mem) %{
5454 match(Set dst (Load8B mem));
5455 ins_cost(MEMORY_REF_COST);
5456 size(4);
5457 format %{ "LDDF $mem,$dst\t! packed8B" %}
5458 opcode(Assembler::lddf_op3);
5459 ins_encode(simple_form3_mem_reg( mem, dst ) );
5460 ins_pipe(floadD_mem);
5461 %}
5463 // Load Aligned Packed Char into a Double Register
5464 instruct loadA4C(regD dst, memory mem) %{
5465 match(Set dst (Load4C mem));
5466 ins_cost(MEMORY_REF_COST);
5467 size(4);
5468 format %{ "LDDF $mem,$dst\t! packed4C" %}
5469 opcode(Assembler::lddf_op3);
5470 ins_encode(simple_form3_mem_reg( mem, dst ) );
5471 ins_pipe(floadD_mem);
5472 %}
5474 // Load Aligned Packed Short into a Double Register
5475 instruct loadA4S(regD dst, memory mem) %{
5476 match(Set dst (Load4S mem));
5477 ins_cost(MEMORY_REF_COST);
5478 size(4);
5479 format %{ "LDDF $mem,$dst\t! packed4S" %}
5480 opcode(Assembler::lddf_op3);
5481 ins_encode(simple_form3_mem_reg( mem, dst ) );
5482 ins_pipe(floadD_mem);
5483 %}
5485 // Load Aligned Packed Int into a Double Register
5486 instruct loadA2I(regD dst, memory mem) %{
5487 match(Set dst (Load2I mem));
5488 ins_cost(MEMORY_REF_COST);
5489 size(4);
5490 format %{ "LDDF $mem,$dst\t! packed2I" %}
5491 opcode(Assembler::lddf_op3);
5492 ins_encode(simple_form3_mem_reg( mem, dst ) );
5493 ins_pipe(floadD_mem);
5494 %}
5496 // Load Range
5497 instruct loadRange(iRegI dst, memory mem) %{
5498 match(Set dst (LoadRange mem));
5499 ins_cost(MEMORY_REF_COST);
5501 size(4);
5502 format %{ "LDUW $mem,$dst\t! range" %}
5503 opcode(Assembler::lduw_op3);
5504 ins_encode(simple_form3_mem_reg( mem, dst ) );
5505 ins_pipe(iload_mem);
5506 %}
5508 // Load Integer into %f register (for fitos/fitod)
5509 instruct loadI_freg(regF dst, memory mem) %{
5510 match(Set dst (LoadI mem));
5511 ins_cost(MEMORY_REF_COST);
5512 size(4);
5514 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5515 opcode(Assembler::ldf_op3);
5516 ins_encode(simple_form3_mem_reg( mem, dst ) );
5517 ins_pipe(floadF_mem);
5518 %}
5520 // Load Pointer
5521 instruct loadP(iRegP dst, memory mem) %{
5522 match(Set dst (LoadP mem));
5523 ins_cost(MEMORY_REF_COST);
5524 size(4);
5526 #ifndef _LP64
5527 format %{ "LDUW $mem,$dst\t! ptr" %}
5528 opcode(Assembler::lduw_op3, 0, REGP_OP);
5529 #else
5530 format %{ "LDX $mem,$dst\t! ptr" %}
5531 opcode(Assembler::ldx_op3, 0, REGP_OP);
5532 #endif
5533 ins_encode( form3_mem_reg( mem, dst ) );
5534 ins_pipe(iload_mem);
5535 %}
5537 // Load Compressed Pointer
5538 instruct loadN(iRegN dst, memory mem) %{
5539 match(Set dst (LoadN mem));
5540 ins_cost(MEMORY_REF_COST);
5541 size(4);
5543 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5544 ins_encode %{
5545 Register index = $mem$$index$$Register;
5546 if (index != G0) {
5547 __ lduw($mem$$base$$Register, index, $dst$$Register);
5548 } else {
5549 __ lduw($mem$$base$$Register, $mem$$disp, $dst$$Register);
5550 }
5551 %}
5552 ins_pipe(iload_mem);
5553 %}
5555 // Load Klass Pointer
5556 instruct loadKlass(iRegP dst, memory mem) %{
5557 match(Set dst (LoadKlass mem));
5558 ins_cost(MEMORY_REF_COST);
5559 size(4);
5561 #ifndef _LP64
5562 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5563 opcode(Assembler::lduw_op3, 0, REGP_OP);
5564 #else
5565 format %{ "LDX $mem,$dst\t! klass ptr" %}
5566 opcode(Assembler::ldx_op3, 0, REGP_OP);
5567 #endif
5568 ins_encode( form3_mem_reg( mem, dst ) );
5569 ins_pipe(iload_mem);
5570 %}
5572 // Load narrow Klass Pointer
5573 instruct loadNKlass(iRegN dst, memory mem) %{
5574 match(Set dst (LoadNKlass mem));
5575 ins_cost(MEMORY_REF_COST);
5576 size(4);
5578 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5580 ins_encode %{
5581 Register base = as_Register($mem$$base);
5582 Register index = as_Register($mem$$index);
5583 Register dst = $dst$$Register;
5584 if (index != G0) {
5585 __ lduw(base, index, dst);
5586 } else {
5587 __ lduw(base, $mem$$disp, dst);
5588 }
5589 %}
5590 ins_pipe(iload_mem);
5591 %}
5593 // Load Double
5594 instruct loadD(regD dst, memory mem) %{
5595 match(Set dst (LoadD mem));
5596 ins_cost(MEMORY_REF_COST);
5598 size(4);
5599 format %{ "LDDF $mem,$dst" %}
5600 opcode(Assembler::lddf_op3);
5601 ins_encode(simple_form3_mem_reg( mem, dst ) );
5602 ins_pipe(floadD_mem);
5603 %}
5605 // Load Double - UNaligned
5606 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5607 match(Set dst (LoadD_unaligned mem));
5608 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5609 size(8);
5610 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5611 "\tLDF $mem+4,$dst.lo\t!" %}
5612 opcode(Assembler::ldf_op3);
5613 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5614 ins_pipe(iload_mem);
5615 %}
5617 // Load Float
5618 instruct loadF(regF dst, memory mem) %{
5619 match(Set dst (LoadF mem));
5620 ins_cost(MEMORY_REF_COST);
5622 size(4);
5623 format %{ "LDF $mem,$dst" %}
5624 opcode(Assembler::ldf_op3);
5625 ins_encode(simple_form3_mem_reg( mem, dst ) );
5626 ins_pipe(floadF_mem);
5627 %}
5629 // Load Constant
5630 instruct loadConI( iRegI dst, immI src ) %{
5631 match(Set dst src);
5632 ins_cost(DEFAULT_COST * 3/2);
5633 format %{ "SET $src,$dst" %}
5634 ins_encode( Set32(src, dst) );
5635 ins_pipe(ialu_hi_lo_reg);
5636 %}
5638 instruct loadConI13( iRegI dst, immI13 src ) %{
5639 match(Set dst src);
5641 size(4);
5642 format %{ "MOV $src,$dst" %}
5643 ins_encode( Set13( src, dst ) );
5644 ins_pipe(ialu_imm);
5645 %}
5647 instruct loadConP(iRegP dst, immP src) %{
5648 match(Set dst src);
5649 ins_cost(DEFAULT_COST * 3/2);
5650 format %{ "SET $src,$dst\t!ptr" %}
5651 // This rule does not use "expand" unlike loadConI because then
5652 // the result type is not known to be an Oop. An ADLC
5653 // enhancement will be needed to make that work - not worth it!
5655 ins_encode( SetPtr( src, dst ) );
5656 ins_pipe(loadConP);
5658 %}
5660 instruct loadConP0(iRegP dst, immP0 src) %{
5661 match(Set dst src);
5663 size(4);
5664 format %{ "CLR $dst\t!ptr" %}
5665 ins_encode( SetNull( dst ) );
5666 ins_pipe(ialu_imm);
5667 %}
5669 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5670 match(Set dst src);
5671 ins_cost(DEFAULT_COST);
5672 format %{ "SET $src,$dst\t!ptr" %}
5673 ins_encode %{
5674 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page());
5675 __ sethi(polling_page, false );
5676 %}
5677 ins_pipe(loadConP_poll);
5678 %}
5680 instruct loadConN0(iRegN dst, immN0 src) %{
5681 match(Set dst src);
5683 size(4);
5684 format %{ "CLR $dst\t! compressed NULL ptr" %}
5685 ins_encode( SetNull( dst ) );
5686 ins_pipe(ialu_imm);
5687 %}
5689 instruct loadConN(iRegN dst, immN src) %{
5690 match(Set dst src);
5691 ins_cost(DEFAULT_COST * 3/2);
5692 format %{ "SET $src,$dst\t! compressed ptr" %}
5693 ins_encode %{
5694 Register dst = $dst$$Register;
5695 __ set_narrow_oop((jobject)$src$$constant, dst);
5696 %}
5697 ins_pipe(ialu_hi_lo_reg);
5698 %}
5700 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5701 // %%% maybe this should work like loadConD
5702 match(Set dst src);
5703 effect(KILL tmp);
5704 ins_cost(DEFAULT_COST * 4);
5705 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5706 ins_encode( LdImmL(src, dst, tmp) );
5707 ins_pipe(loadConL);
5708 %}
5710 instruct loadConL0( iRegL dst, immL0 src ) %{
5711 match(Set dst src);
5712 ins_cost(DEFAULT_COST);
5713 size(4);
5714 format %{ "CLR $dst\t! long" %}
5715 ins_encode( Set13( src, dst ) );
5716 ins_pipe(ialu_imm);
5717 %}
5719 instruct loadConL13( iRegL dst, immL13 src ) %{
5720 match(Set dst src);
5721 ins_cost(DEFAULT_COST * 2);
5723 size(4);
5724 format %{ "MOV $src,$dst\t! long" %}
5725 ins_encode( Set13( src, dst ) );
5726 ins_pipe(ialu_imm);
5727 %}
5729 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
5730 match(Set dst src);
5731 effect(KILL tmp);
5733 #ifdef _LP64
5734 size(36);
5735 #else
5736 size(8);
5737 #endif
5739 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
5740 "LDF [$tmp+lo(&$src)],$dst" %}
5741 ins_encode( LdImmF(src, dst, tmp) );
5742 ins_pipe(loadConFD);
5743 %}
5745 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
5746 match(Set dst src);
5747 effect(KILL tmp);
5749 #ifdef _LP64
5750 size(36);
5751 #else
5752 size(8);
5753 #endif
5755 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
5756 "LDDF [$tmp+lo(&$src)],$dst" %}
5757 ins_encode( LdImmD(src, dst, tmp) );
5758 ins_pipe(loadConFD);
5759 %}
5761 // Prefetch instructions.
5762 // Must be safe to execute with invalid address (cannot fault).
5764 instruct prefetchr( memory mem ) %{
5765 match( PrefetchRead mem );
5766 ins_cost(MEMORY_REF_COST);
5768 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
5769 opcode(Assembler::prefetch_op3);
5770 ins_encode( form3_mem_prefetch_read( mem ) );
5771 ins_pipe(iload_mem);
5772 %}
5774 instruct prefetchw( memory mem ) %{
5775 match( PrefetchWrite mem );
5776 ins_cost(MEMORY_REF_COST);
5778 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
5779 opcode(Assembler::prefetch_op3);
5780 ins_encode( form3_mem_prefetch_write( mem ) );
5781 ins_pipe(iload_mem);
5782 %}
5785 //----------Store Instructions-------------------------------------------------
5786 // Store Byte
5787 instruct storeB(memory mem, iRegI src) %{
5788 match(Set mem (StoreB mem src));
5789 ins_cost(MEMORY_REF_COST);
5791 size(4);
5792 format %{ "STB $src,$mem\t! byte" %}
5793 opcode(Assembler::stb_op3);
5794 ins_encode(simple_form3_mem_reg( mem, src ) );
5795 ins_pipe(istore_mem_reg);
5796 %}
5798 instruct storeB0(memory mem, immI0 src) %{
5799 match(Set mem (StoreB mem src));
5800 ins_cost(MEMORY_REF_COST);
5802 size(4);
5803 format %{ "STB $src,$mem\t! byte" %}
5804 opcode(Assembler::stb_op3);
5805 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5806 ins_pipe(istore_mem_zero);
5807 %}
5809 instruct storeCM0(memory mem, immI0 src) %{
5810 match(Set mem (StoreCM mem src));
5811 ins_cost(MEMORY_REF_COST);
5813 size(4);
5814 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5815 opcode(Assembler::stb_op3);
5816 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5817 ins_pipe(istore_mem_zero);
5818 %}
5820 // Store Char/Short
5821 instruct storeC(memory mem, iRegI src) %{
5822 match(Set mem (StoreC mem src));
5823 ins_cost(MEMORY_REF_COST);
5825 size(4);
5826 format %{ "STH $src,$mem\t! short" %}
5827 opcode(Assembler::sth_op3);
5828 ins_encode(simple_form3_mem_reg( mem, src ) );
5829 ins_pipe(istore_mem_reg);
5830 %}
5832 instruct storeC0(memory mem, immI0 src) %{
5833 match(Set mem (StoreC mem src));
5834 ins_cost(MEMORY_REF_COST);
5836 size(4);
5837 format %{ "STH $src,$mem\t! short" %}
5838 opcode(Assembler::sth_op3);
5839 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5840 ins_pipe(istore_mem_zero);
5841 %}
5843 // Store Integer
5844 instruct storeI(memory mem, iRegI src) %{
5845 match(Set mem (StoreI mem src));
5846 ins_cost(MEMORY_REF_COST);
5848 size(4);
5849 format %{ "STW $src,$mem" %}
5850 opcode(Assembler::stw_op3);
5851 ins_encode(simple_form3_mem_reg( mem, src ) );
5852 ins_pipe(istore_mem_reg);
5853 %}
5855 // Store Long
5856 instruct storeL(memory mem, iRegL src) %{
5857 match(Set mem (StoreL mem src));
5858 ins_cost(MEMORY_REF_COST);
5859 size(4);
5860 format %{ "STX $src,$mem\t! long" %}
5861 opcode(Assembler::stx_op3);
5862 ins_encode(simple_form3_mem_reg( mem, src ) );
5863 ins_pipe(istore_mem_reg);
5864 %}
5866 instruct storeI0(memory mem, immI0 src) %{
5867 match(Set mem (StoreI mem src));
5868 ins_cost(MEMORY_REF_COST);
5870 size(4);
5871 format %{ "STW $src,$mem" %}
5872 opcode(Assembler::stw_op3);
5873 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5874 ins_pipe(istore_mem_zero);
5875 %}
5877 instruct storeL0(memory mem, immL0 src) %{
5878 match(Set mem (StoreL mem src));
5879 ins_cost(MEMORY_REF_COST);
5881 size(4);
5882 format %{ "STX $src,$mem" %}
5883 opcode(Assembler::stx_op3);
5884 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5885 ins_pipe(istore_mem_zero);
5886 %}
5888 // Store Integer from float register (used after fstoi)
5889 instruct storeI_Freg(memory mem, regF src) %{
5890 match(Set mem (StoreI mem src));
5891 ins_cost(MEMORY_REF_COST);
5893 size(4);
5894 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
5895 opcode(Assembler::stf_op3);
5896 ins_encode(simple_form3_mem_reg( mem, src ) );
5897 ins_pipe(fstoreF_mem_reg);
5898 %}
5900 // Store Pointer
5901 instruct storeP(memory dst, sp_ptr_RegP src) %{
5902 match(Set dst (StoreP dst src));
5903 ins_cost(MEMORY_REF_COST);
5904 size(4);
5906 #ifndef _LP64
5907 format %{ "STW $src,$dst\t! ptr" %}
5908 opcode(Assembler::stw_op3, 0, REGP_OP);
5909 #else
5910 format %{ "STX $src,$dst\t! ptr" %}
5911 opcode(Assembler::stx_op3, 0, REGP_OP);
5912 #endif
5913 ins_encode( form3_mem_reg( dst, src ) );
5914 ins_pipe(istore_mem_spORreg);
5915 %}
5917 instruct storeP0(memory dst, immP0 src) %{
5918 match(Set dst (StoreP dst src));
5919 ins_cost(MEMORY_REF_COST);
5920 size(4);
5922 #ifndef _LP64
5923 format %{ "STW $src,$dst\t! ptr" %}
5924 opcode(Assembler::stw_op3, 0, REGP_OP);
5925 #else
5926 format %{ "STX $src,$dst\t! ptr" %}
5927 opcode(Assembler::stx_op3, 0, REGP_OP);
5928 #endif
5929 ins_encode( form3_mem_reg( dst, R_G0 ) );
5930 ins_pipe(istore_mem_zero);
5931 %}
5933 // Store Compressed Pointer
5934 instruct storeN(memory dst, iRegN src) %{
5935 match(Set dst (StoreN dst src));
5936 ins_cost(MEMORY_REF_COST);
5937 size(4);
5939 format %{ "STW $src,$dst\t! compressed ptr" %}
5940 ins_encode %{
5941 Register base = as_Register($dst$$base);
5942 Register index = as_Register($dst$$index);
5943 Register src = $src$$Register;
5944 if (index != G0) {
5945 __ stw(src, base, index);
5946 } else {
5947 __ stw(src, base, $dst$$disp);
5948 }
5949 %}
5950 ins_pipe(istore_mem_spORreg);
5951 %}
5953 instruct storeN0(memory dst, immN0 src) %{
5954 match(Set dst (StoreN dst src));
5955 ins_cost(MEMORY_REF_COST);
5956 size(4);
5958 format %{ "STW $src,$dst\t! compressed ptr" %}
5959 ins_encode %{
5960 Register base = as_Register($dst$$base);
5961 Register index = as_Register($dst$$index);
5962 if (index != G0) {
5963 __ stw(0, base, index);
5964 } else {
5965 __ stw(0, base, $dst$$disp);
5966 }
5967 %}
5968 ins_pipe(istore_mem_zero);
5969 %}
5971 // Store Double
5972 instruct storeD( memory mem, regD src) %{
5973 match(Set mem (StoreD mem src));
5974 ins_cost(MEMORY_REF_COST);
5976 size(4);
5977 format %{ "STDF $src,$mem" %}
5978 opcode(Assembler::stdf_op3);
5979 ins_encode(simple_form3_mem_reg( mem, src ) );
5980 ins_pipe(fstoreD_mem_reg);
5981 %}
5983 instruct storeD0( memory mem, immD0 src) %{
5984 match(Set mem (StoreD mem src));
5985 ins_cost(MEMORY_REF_COST);
5987 size(4);
5988 format %{ "STX $src,$mem" %}
5989 opcode(Assembler::stx_op3);
5990 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5991 ins_pipe(fstoreD_mem_zero);
5992 %}
5994 // Store Float
5995 instruct storeF( memory mem, regF src) %{
5996 match(Set mem (StoreF mem src));
5997 ins_cost(MEMORY_REF_COST);
5999 size(4);
6000 format %{ "STF $src,$mem" %}
6001 opcode(Assembler::stf_op3);
6002 ins_encode(simple_form3_mem_reg( mem, src ) );
6003 ins_pipe(fstoreF_mem_reg);
6004 %}
6006 instruct storeF0( memory mem, immF0 src) %{
6007 match(Set mem (StoreF mem src));
6008 ins_cost(MEMORY_REF_COST);
6010 size(4);
6011 format %{ "STW $src,$mem\t! storeF0" %}
6012 opcode(Assembler::stw_op3);
6013 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6014 ins_pipe(fstoreF_mem_zero);
6015 %}
6017 // Store Aligned Packed Bytes in Double register to memory
6018 instruct storeA8B(memory mem, regD src) %{
6019 match(Set mem (Store8B mem src));
6020 ins_cost(MEMORY_REF_COST);
6021 size(4);
6022 format %{ "STDF $src,$mem\t! packed8B" %}
6023 opcode(Assembler::stdf_op3);
6024 ins_encode(simple_form3_mem_reg( mem, src ) );
6025 ins_pipe(fstoreD_mem_reg);
6026 %}
6028 // Convert oop pointer into compressed form
6029 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6030 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6031 match(Set dst (EncodeP src));
6032 format %{ "encode_heap_oop $src, $dst" %}
6033 ins_encode %{
6034 __ encode_heap_oop($src$$Register, $dst$$Register);
6035 %}
6036 ins_pipe(ialu_reg);
6037 %}
6039 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6040 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6041 match(Set dst (EncodeP src));
6042 format %{ "encode_heap_oop_not_null $src, $dst" %}
6043 ins_encode %{
6044 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6045 %}
6046 ins_pipe(ialu_reg);
6047 %}
6049 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6050 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6051 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6052 match(Set dst (DecodeN src));
6053 format %{ "decode_heap_oop $src, $dst" %}
6054 ins_encode %{
6055 __ decode_heap_oop($src$$Register, $dst$$Register);
6056 %}
6057 ins_pipe(ialu_reg);
6058 %}
6060 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6061 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6062 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6063 match(Set dst (DecodeN src));
6064 format %{ "decode_heap_oop_not_null $src, $dst" %}
6065 ins_encode %{
6066 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6067 %}
6068 ins_pipe(ialu_reg);
6069 %}
6072 // Store Zero into Aligned Packed Bytes
6073 instruct storeA8B0(memory mem, immI0 zero) %{
6074 match(Set mem (Store8B mem zero));
6075 ins_cost(MEMORY_REF_COST);
6076 size(4);
6077 format %{ "STX $zero,$mem\t! packed8B" %}
6078 opcode(Assembler::stx_op3);
6079 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6080 ins_pipe(fstoreD_mem_zero);
6081 %}
6083 // Store Aligned Packed Chars/Shorts in Double register to memory
6084 instruct storeA4C(memory mem, regD src) %{
6085 match(Set mem (Store4C mem src));
6086 ins_cost(MEMORY_REF_COST);
6087 size(4);
6088 format %{ "STDF $src,$mem\t! packed4C" %}
6089 opcode(Assembler::stdf_op3);
6090 ins_encode(simple_form3_mem_reg( mem, src ) );
6091 ins_pipe(fstoreD_mem_reg);
6092 %}
6094 // Store Zero into Aligned Packed Chars/Shorts
6095 instruct storeA4C0(memory mem, immI0 zero) %{
6096 match(Set mem (Store4C mem (Replicate4C zero)));
6097 ins_cost(MEMORY_REF_COST);
6098 size(4);
6099 format %{ "STX $zero,$mem\t! packed4C" %}
6100 opcode(Assembler::stx_op3);
6101 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6102 ins_pipe(fstoreD_mem_zero);
6103 %}
6105 // Store Aligned Packed Ints in Double register to memory
6106 instruct storeA2I(memory mem, regD src) %{
6107 match(Set mem (Store2I mem src));
6108 ins_cost(MEMORY_REF_COST);
6109 size(4);
6110 format %{ "STDF $src,$mem\t! packed2I" %}
6111 opcode(Assembler::stdf_op3);
6112 ins_encode(simple_form3_mem_reg( mem, src ) );
6113 ins_pipe(fstoreD_mem_reg);
6114 %}
6116 // Store Zero into Aligned Packed Ints
6117 instruct storeA2I0(memory mem, immI0 zero) %{
6118 match(Set mem (Store2I mem zero));
6119 ins_cost(MEMORY_REF_COST);
6120 size(4);
6121 format %{ "STX $zero,$mem\t! packed2I" %}
6122 opcode(Assembler::stx_op3);
6123 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6124 ins_pipe(fstoreD_mem_zero);
6125 %}
6128 //----------MemBar Instructions-----------------------------------------------
6129 // Memory barrier flavors
6131 instruct membar_acquire() %{
6132 match(MemBarAcquire);
6133 ins_cost(4*MEMORY_REF_COST);
6135 size(0);
6136 format %{ "MEMBAR-acquire" %}
6137 ins_encode( enc_membar_acquire );
6138 ins_pipe(long_memory_op);
6139 %}
6141 instruct membar_acquire_lock() %{
6142 match(MemBarAcquire);
6143 predicate(Matcher::prior_fast_lock(n));
6144 ins_cost(0);
6146 size(0);
6147 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6148 ins_encode( );
6149 ins_pipe(empty);
6150 %}
6152 instruct membar_release() %{
6153 match(MemBarRelease);
6154 ins_cost(4*MEMORY_REF_COST);
6156 size(0);
6157 format %{ "MEMBAR-release" %}
6158 ins_encode( enc_membar_release );
6159 ins_pipe(long_memory_op);
6160 %}
6162 instruct membar_release_lock() %{
6163 match(MemBarRelease);
6164 predicate(Matcher::post_fast_unlock(n));
6165 ins_cost(0);
6167 size(0);
6168 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6169 ins_encode( );
6170 ins_pipe(empty);
6171 %}
6173 instruct membar_volatile() %{
6174 match(MemBarVolatile);
6175 ins_cost(4*MEMORY_REF_COST);
6177 size(4);
6178 format %{ "MEMBAR-volatile" %}
6179 ins_encode( enc_membar_volatile );
6180 ins_pipe(long_memory_op);
6181 %}
6183 instruct unnecessary_membar_volatile() %{
6184 match(MemBarVolatile);
6185 predicate(Matcher::post_store_load_barrier(n));
6186 ins_cost(0);
6188 size(0);
6189 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6190 ins_encode( );
6191 ins_pipe(empty);
6192 %}
6194 //----------Register Move Instructions-----------------------------------------
6195 instruct roundDouble_nop(regD dst) %{
6196 match(Set dst (RoundDouble dst));
6197 ins_cost(0);
6198 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6199 ins_encode( );
6200 ins_pipe(empty);
6201 %}
6204 instruct roundFloat_nop(regF dst) %{
6205 match(Set dst (RoundFloat dst));
6206 ins_cost(0);
6207 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6208 ins_encode( );
6209 ins_pipe(empty);
6210 %}
6213 // Cast Index to Pointer for unsafe natives
6214 instruct castX2P(iRegX src, iRegP dst) %{
6215 match(Set dst (CastX2P src));
6217 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6218 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6219 ins_pipe(ialu_reg);
6220 %}
6222 // Cast Pointer to Index for unsafe natives
6223 instruct castP2X(iRegP src, iRegX dst) %{
6224 match(Set dst (CastP2X src));
6226 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6227 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6228 ins_pipe(ialu_reg);
6229 %}
6231 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6232 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6233 match(Set stkSlot src); // chain rule
6234 ins_cost(MEMORY_REF_COST);
6235 format %{ "STDF $src,$stkSlot\t!stk" %}
6236 opcode(Assembler::stdf_op3);
6237 ins_encode(simple_form3_mem_reg(stkSlot, src));
6238 ins_pipe(fstoreD_stk_reg);
6239 %}
6241 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6242 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6243 match(Set dst stkSlot); // chain rule
6244 ins_cost(MEMORY_REF_COST);
6245 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6246 opcode(Assembler::lddf_op3);
6247 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6248 ins_pipe(floadD_stk);
6249 %}
6251 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6252 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6253 match(Set stkSlot src); // chain rule
6254 ins_cost(MEMORY_REF_COST);
6255 format %{ "STF $src,$stkSlot\t!stk" %}
6256 opcode(Assembler::stf_op3);
6257 ins_encode(simple_form3_mem_reg(stkSlot, src));
6258 ins_pipe(fstoreF_stk_reg);
6259 %}
6261 //----------Conditional Move---------------------------------------------------
6262 // Conditional move
6263 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6264 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6265 ins_cost(150);
6266 format %{ "MOV$cmp $pcc,$src,$dst" %}
6267 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6268 ins_pipe(ialu_reg);
6269 %}
6271 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6272 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6273 ins_cost(140);
6274 format %{ "MOV$cmp $pcc,$src,$dst" %}
6275 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6276 ins_pipe(ialu_imm);
6277 %}
6279 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6280 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6281 ins_cost(150);
6282 size(4);
6283 format %{ "MOV$cmp $icc,$src,$dst" %}
6284 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6285 ins_pipe(ialu_reg);
6286 %}
6288 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6289 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6290 ins_cost(140);
6291 size(4);
6292 format %{ "MOV$cmp $icc,$src,$dst" %}
6293 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6294 ins_pipe(ialu_imm);
6295 %}
6297 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6298 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6299 ins_cost(150);
6300 size(4);
6301 format %{ "MOV$cmp $icc,$src,$dst" %}
6302 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6303 ins_pipe(ialu_reg);
6304 %}
6306 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6307 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6308 ins_cost(140);
6309 size(4);
6310 format %{ "MOV$cmp $icc,$src,$dst" %}
6311 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6312 ins_pipe(ialu_imm);
6313 %}
6315 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6316 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6317 ins_cost(150);
6318 size(4);
6319 format %{ "MOV$cmp $fcc,$src,$dst" %}
6320 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6321 ins_pipe(ialu_reg);
6322 %}
6324 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6325 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6326 ins_cost(140);
6327 size(4);
6328 format %{ "MOV$cmp $fcc,$src,$dst" %}
6329 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6330 ins_pipe(ialu_imm);
6331 %}
6333 // Conditional move for RegN. Only cmov(reg,reg).
6334 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6335 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6336 ins_cost(150);
6337 format %{ "MOV$cmp $pcc,$src,$dst" %}
6338 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6339 ins_pipe(ialu_reg);
6340 %}
6342 // This instruction also works with CmpN so we don't need cmovNN_reg.
6343 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6344 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6345 ins_cost(150);
6346 size(4);
6347 format %{ "MOV$cmp $icc,$src,$dst" %}
6348 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6349 ins_pipe(ialu_reg);
6350 %}
6352 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6353 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6354 ins_cost(150);
6355 size(4);
6356 format %{ "MOV$cmp $fcc,$src,$dst" %}
6357 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6358 ins_pipe(ialu_reg);
6359 %}
6361 // Conditional move
6362 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6363 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6364 ins_cost(150);
6365 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6366 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6367 ins_pipe(ialu_reg);
6368 %}
6370 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6371 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6372 ins_cost(140);
6373 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6374 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6375 ins_pipe(ialu_imm);
6376 %}
6378 // This instruction also works with CmpN so we don't need cmovPN_reg.
6379 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6380 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6381 ins_cost(150);
6383 size(4);
6384 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6385 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6386 ins_pipe(ialu_reg);
6387 %}
6389 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6390 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6391 ins_cost(140);
6393 size(4);
6394 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6395 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6396 ins_pipe(ialu_imm);
6397 %}
6399 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6400 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6401 ins_cost(150);
6402 size(4);
6403 format %{ "MOV$cmp $fcc,$src,$dst" %}
6404 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6405 ins_pipe(ialu_imm);
6406 %}
6408 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6409 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6410 ins_cost(140);
6411 size(4);
6412 format %{ "MOV$cmp $fcc,$src,$dst" %}
6413 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6414 ins_pipe(ialu_imm);
6415 %}
6417 // Conditional move
6418 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6419 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6420 ins_cost(150);
6421 opcode(0x101);
6422 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6423 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6424 ins_pipe(int_conditional_float_move);
6425 %}
6427 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6428 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6429 ins_cost(150);
6431 size(4);
6432 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6433 opcode(0x101);
6434 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6435 ins_pipe(int_conditional_float_move);
6436 %}
6438 // Conditional move,
6439 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6440 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6441 ins_cost(150);
6442 size(4);
6443 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6444 opcode(0x1);
6445 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6446 ins_pipe(int_conditional_double_move);
6447 %}
6449 // Conditional move
6450 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6451 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6452 ins_cost(150);
6453 size(4);
6454 opcode(0x102);
6455 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6456 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6457 ins_pipe(int_conditional_double_move);
6458 %}
6460 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6461 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6462 ins_cost(150);
6464 size(4);
6465 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6466 opcode(0x102);
6467 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6468 ins_pipe(int_conditional_double_move);
6469 %}
6471 // Conditional move,
6472 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6473 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6474 ins_cost(150);
6475 size(4);
6476 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6477 opcode(0x2);
6478 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6479 ins_pipe(int_conditional_double_move);
6480 %}
6482 // Conditional move
6483 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6484 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6485 ins_cost(150);
6486 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6487 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6488 ins_pipe(ialu_reg);
6489 %}
6491 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6492 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6493 ins_cost(140);
6494 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6495 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6496 ins_pipe(ialu_imm);
6497 %}
6499 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6500 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6501 ins_cost(150);
6503 size(4);
6504 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6505 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6506 ins_pipe(ialu_reg);
6507 %}
6510 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6511 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6512 ins_cost(150);
6514 size(4);
6515 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6516 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6517 ins_pipe(ialu_reg);
6518 %}
6522 //----------OS and Locking Instructions----------------------------------------
6524 // This name is KNOWN by the ADLC and cannot be changed.
6525 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6526 // for this guy.
6527 instruct tlsLoadP(g2RegP dst) %{
6528 match(Set dst (ThreadLocal));
6530 size(0);
6531 ins_cost(0);
6532 format %{ "# TLS is in G2" %}
6533 ins_encode( /*empty encoding*/ );
6534 ins_pipe(ialu_none);
6535 %}
6537 instruct checkCastPP( iRegP dst ) %{
6538 match(Set dst (CheckCastPP dst));
6540 size(0);
6541 format %{ "# checkcastPP of $dst" %}
6542 ins_encode( /*empty encoding*/ );
6543 ins_pipe(empty);
6544 %}
6547 instruct castPP( iRegP dst ) %{
6548 match(Set dst (CastPP dst));
6549 format %{ "# castPP of $dst" %}
6550 ins_encode( /*empty encoding*/ );
6551 ins_pipe(empty);
6552 %}
6554 instruct castII( iRegI dst ) %{
6555 match(Set dst (CastII dst));
6556 format %{ "# castII of $dst" %}
6557 ins_encode( /*empty encoding*/ );
6558 ins_cost(0);
6559 ins_pipe(empty);
6560 %}
6562 //----------Arithmetic Instructions--------------------------------------------
6563 // Addition Instructions
6564 // Register Addition
6565 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6566 match(Set dst (AddI src1 src2));
6568 size(4);
6569 format %{ "ADD $src1,$src2,$dst" %}
6570 ins_encode %{
6571 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6572 %}
6573 ins_pipe(ialu_reg_reg);
6574 %}
6576 // Immediate Addition
6577 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6578 match(Set dst (AddI src1 src2));
6580 size(4);
6581 format %{ "ADD $src1,$src2,$dst" %}
6582 opcode(Assembler::add_op3, Assembler::arith_op);
6583 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6584 ins_pipe(ialu_reg_imm);
6585 %}
6587 // Pointer Register Addition
6588 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6589 match(Set dst (AddP src1 src2));
6591 size(4);
6592 format %{ "ADD $src1,$src2,$dst" %}
6593 opcode(Assembler::add_op3, Assembler::arith_op);
6594 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6595 ins_pipe(ialu_reg_reg);
6596 %}
6598 // Pointer Immediate Addition
6599 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6600 match(Set dst (AddP src1 src2));
6602 size(4);
6603 format %{ "ADD $src1,$src2,$dst" %}
6604 opcode(Assembler::add_op3, Assembler::arith_op);
6605 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6606 ins_pipe(ialu_reg_imm);
6607 %}
6609 // Long Addition
6610 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6611 match(Set dst (AddL src1 src2));
6613 size(4);
6614 format %{ "ADD $src1,$src2,$dst\t! long" %}
6615 opcode(Assembler::add_op3, Assembler::arith_op);
6616 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6617 ins_pipe(ialu_reg_reg);
6618 %}
6620 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6621 match(Set dst (AddL src1 con));
6623 size(4);
6624 format %{ "ADD $src1,$con,$dst" %}
6625 opcode(Assembler::add_op3, Assembler::arith_op);
6626 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6627 ins_pipe(ialu_reg_imm);
6628 %}
6630 //----------Conditional_store--------------------------------------------------
6631 // Conditional-store of the updated heap-top.
6632 // Used during allocation of the shared heap.
6633 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6635 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6636 instruct loadPLocked(iRegP dst, memory mem) %{
6637 match(Set dst (LoadPLocked mem));
6638 ins_cost(MEMORY_REF_COST);
6640 #ifndef _LP64
6641 size(4);
6642 format %{ "LDUW $mem,$dst\t! ptr" %}
6643 opcode(Assembler::lduw_op3, 0, REGP_OP);
6644 #else
6645 format %{ "LDX $mem,$dst\t! ptr" %}
6646 opcode(Assembler::ldx_op3, 0, REGP_OP);
6647 #endif
6648 ins_encode( form3_mem_reg( mem, dst ) );
6649 ins_pipe(iload_mem);
6650 %}
6652 // LoadL-locked. Same as a regular long load when used with a compare-swap
6653 instruct loadLLocked(iRegL dst, memory mem) %{
6654 match(Set dst (LoadLLocked mem));
6655 ins_cost(MEMORY_REF_COST);
6656 size(4);
6657 format %{ "LDX $mem,$dst\t! long" %}
6658 opcode(Assembler::ldx_op3);
6659 ins_encode(simple_form3_mem_reg( mem, dst ) );
6660 ins_pipe(iload_mem);
6661 %}
6663 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6664 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6665 effect( KILL newval );
6666 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6667 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6668 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6669 ins_pipe( long_memory_op );
6670 %}
6672 // Conditional-store of an int value.
6673 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
6674 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
6675 effect( KILL newval );
6676 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6677 "CMP $oldval,$newval\t\t! See if we made progress" %}
6678 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6679 ins_pipe( long_memory_op );
6680 %}
6682 // Conditional-store of a long value.
6683 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
6684 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
6685 effect( KILL newval );
6686 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
6687 "CMP $oldval,$newval\t\t! See if we made progress" %}
6688 ins_encode( enc_cas(mem_ptr,oldval,newval) );
6689 ins_pipe( long_memory_op );
6690 %}
6692 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6694 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6695 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6696 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6697 format %{
6698 "MOV $newval,O7\n\t"
6699 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6700 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6701 "MOV 1,$res\n\t"
6702 "MOVne xcc,R_G0,$res"
6703 %}
6704 ins_encode( enc_casx(mem_ptr, oldval, newval),
6705 enc_lflags_ne_to_boolean(res) );
6706 ins_pipe( long_memory_op );
6707 %}
6710 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6711 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6712 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6713 format %{
6714 "MOV $newval,O7\n\t"
6715 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6716 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6717 "MOV 1,$res\n\t"
6718 "MOVne icc,R_G0,$res"
6719 %}
6720 ins_encode( enc_casi(mem_ptr, oldval, newval),
6721 enc_iflags_ne_to_boolean(res) );
6722 ins_pipe( long_memory_op );
6723 %}
6725 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6726 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6727 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6728 format %{
6729 "MOV $newval,O7\n\t"
6730 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6731 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6732 "MOV 1,$res\n\t"
6733 "MOVne xcc,R_G0,$res"
6734 %}
6735 #ifdef _LP64
6736 ins_encode( enc_casx(mem_ptr, oldval, newval),
6737 enc_lflags_ne_to_boolean(res) );
6738 #else
6739 ins_encode( enc_casi(mem_ptr, oldval, newval),
6740 enc_iflags_ne_to_boolean(res) );
6741 #endif
6742 ins_pipe( long_memory_op );
6743 %}
6745 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6746 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6747 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6748 format %{
6749 "MOV $newval,O7\n\t"
6750 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6751 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6752 "MOV 1,$res\n\t"
6753 "MOVne icc,R_G0,$res"
6754 %}
6755 ins_encode( enc_casi(mem_ptr, oldval, newval),
6756 enc_iflags_ne_to_boolean(res) );
6757 ins_pipe( long_memory_op );
6758 %}
6760 //---------------------
6761 // Subtraction Instructions
6762 // Register Subtraction
6763 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6764 match(Set dst (SubI src1 src2));
6766 size(4);
6767 format %{ "SUB $src1,$src2,$dst" %}
6768 opcode(Assembler::sub_op3, Assembler::arith_op);
6769 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6770 ins_pipe(ialu_reg_reg);
6771 %}
6773 // Immediate Subtraction
6774 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6775 match(Set dst (SubI src1 src2));
6777 size(4);
6778 format %{ "SUB $src1,$src2,$dst" %}
6779 opcode(Assembler::sub_op3, Assembler::arith_op);
6780 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6781 ins_pipe(ialu_reg_imm);
6782 %}
6784 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6785 match(Set dst (SubI zero src2));
6787 size(4);
6788 format %{ "NEG $src2,$dst" %}
6789 opcode(Assembler::sub_op3, Assembler::arith_op);
6790 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6791 ins_pipe(ialu_zero_reg);
6792 %}
6794 // Long subtraction
6795 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6796 match(Set dst (SubL src1 src2));
6798 size(4);
6799 format %{ "SUB $src1,$src2,$dst\t! long" %}
6800 opcode(Assembler::sub_op3, Assembler::arith_op);
6801 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6802 ins_pipe(ialu_reg_reg);
6803 %}
6805 // Immediate Subtraction
6806 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6807 match(Set dst (SubL src1 con));
6809 size(4);
6810 format %{ "SUB $src1,$con,$dst\t! long" %}
6811 opcode(Assembler::sub_op3, Assembler::arith_op);
6812 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6813 ins_pipe(ialu_reg_imm);
6814 %}
6816 // Long negation
6817 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6818 match(Set dst (SubL zero src2));
6820 size(4);
6821 format %{ "NEG $src2,$dst\t! long" %}
6822 opcode(Assembler::sub_op3, Assembler::arith_op);
6823 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6824 ins_pipe(ialu_zero_reg);
6825 %}
6827 // Multiplication Instructions
6828 // Integer Multiplication
6829 // Register Multiplication
6830 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6831 match(Set dst (MulI src1 src2));
6833 size(4);
6834 format %{ "MULX $src1,$src2,$dst" %}
6835 opcode(Assembler::mulx_op3, Assembler::arith_op);
6836 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6837 ins_pipe(imul_reg_reg);
6838 %}
6840 // Immediate Multiplication
6841 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6842 match(Set dst (MulI src1 src2));
6844 size(4);
6845 format %{ "MULX $src1,$src2,$dst" %}
6846 opcode(Assembler::mulx_op3, Assembler::arith_op);
6847 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6848 ins_pipe(imul_reg_imm);
6849 %}
6851 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6852 match(Set dst (MulL src1 src2));
6853 ins_cost(DEFAULT_COST * 5);
6854 size(4);
6855 format %{ "MULX $src1,$src2,$dst\t! long" %}
6856 opcode(Assembler::mulx_op3, Assembler::arith_op);
6857 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6858 ins_pipe(mulL_reg_reg);
6859 %}
6861 // Immediate Multiplication
6862 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
6863 match(Set dst (MulL src1 src2));
6864 ins_cost(DEFAULT_COST * 5);
6865 size(4);
6866 format %{ "MULX $src1,$src2,$dst" %}
6867 opcode(Assembler::mulx_op3, Assembler::arith_op);
6868 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6869 ins_pipe(mulL_reg_imm);
6870 %}
6872 // Integer Division
6873 // Register Division
6874 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
6875 match(Set dst (DivI src1 src2));
6876 ins_cost((2+71)*DEFAULT_COST);
6878 format %{ "SRA $src2,0,$src2\n\t"
6879 "SRA $src1,0,$src1\n\t"
6880 "SDIVX $src1,$src2,$dst" %}
6881 ins_encode( idiv_reg( src1, src2, dst ) );
6882 ins_pipe(sdiv_reg_reg);
6883 %}
6885 // Immediate Division
6886 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
6887 match(Set dst (DivI src1 src2));
6888 ins_cost((2+71)*DEFAULT_COST);
6890 format %{ "SRA $src1,0,$src1\n\t"
6891 "SDIVX $src1,$src2,$dst" %}
6892 ins_encode( idiv_imm( src1, src2, dst ) );
6893 ins_pipe(sdiv_reg_imm);
6894 %}
6896 //----------Div-By-10-Expansion------------------------------------------------
6897 // Extract hi bits of a 32x32->64 bit multiply.
6898 // Expand rule only, not matched
6899 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
6900 effect( DEF dst, USE src1, USE src2 );
6901 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
6902 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
6903 ins_encode( enc_mul_hi(dst,src1,src2));
6904 ins_pipe(sdiv_reg_reg);
6905 %}
6907 // Magic constant, reciprocal of 10
6908 instruct loadConI_x66666667(iRegIsafe dst) %{
6909 effect( DEF dst );
6911 size(8);
6912 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
6913 ins_encode( Set32(0x66666667, dst) );
6914 ins_pipe(ialu_hi_lo_reg);
6915 %}
6917 // Register Shift Right Arithmetic Long by 32-63
6918 instruct sra_31( iRegI dst, iRegI src ) %{
6919 effect( DEF dst, USE src );
6920 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
6921 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
6922 ins_pipe(ialu_reg_reg);
6923 %}
6925 // Arithmetic Shift Right by 8-bit immediate
6926 instruct sra_reg_2( iRegI dst, iRegI src ) %{
6927 effect( DEF dst, USE src );
6928 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
6929 opcode(Assembler::sra_op3, Assembler::arith_op);
6930 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
6931 ins_pipe(ialu_reg_imm);
6932 %}
6934 // Integer DIV with 10
6935 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
6936 match(Set dst (DivI src div));
6937 ins_cost((6+6)*DEFAULT_COST);
6938 expand %{
6939 iRegIsafe tmp1; // Killed temps;
6940 iRegIsafe tmp2; // Killed temps;
6941 iRegI tmp3; // Killed temps;
6942 iRegI tmp4; // Killed temps;
6943 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
6944 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
6945 sra_31( tmp3, src ); // SRA src,31 -> tmp3
6946 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
6947 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
6948 %}
6949 %}
6951 // Register Long Division
6952 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6953 match(Set dst (DivL src1 src2));
6954 ins_cost(DEFAULT_COST*71);
6955 size(4);
6956 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6957 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6958 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6959 ins_pipe(divL_reg_reg);
6960 %}
6962 // Register Long Division
6963 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
6964 match(Set dst (DivL src1 src2));
6965 ins_cost(DEFAULT_COST*71);
6966 size(4);
6967 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6968 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6969 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6970 ins_pipe(divL_reg_imm);
6971 %}
6973 // Integer Remainder
6974 // Register Remainder
6975 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
6976 match(Set dst (ModI src1 src2));
6977 effect( KILL ccr, KILL temp);
6979 format %{ "SREM $src1,$src2,$dst" %}
6980 ins_encode( irem_reg(src1, src2, dst, temp) );
6981 ins_pipe(sdiv_reg_reg);
6982 %}
6984 // Immediate Remainder
6985 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
6986 match(Set dst (ModI src1 src2));
6987 effect( KILL ccr, KILL temp);
6989 format %{ "SREM $src1,$src2,$dst" %}
6990 ins_encode( irem_imm(src1, src2, dst, temp) );
6991 ins_pipe(sdiv_reg_imm);
6992 %}
6994 // Register Long Remainder
6995 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
6996 effect(DEF dst, USE src1, USE src2);
6997 size(4);
6998 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6999 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7000 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7001 ins_pipe(divL_reg_reg);
7002 %}
7004 // Register Long Division
7005 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7006 effect(DEF dst, USE src1, USE src2);
7007 size(4);
7008 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7009 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7010 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7011 ins_pipe(divL_reg_imm);
7012 %}
7014 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7015 effect(DEF dst, USE src1, USE src2);
7016 size(4);
7017 format %{ "MULX $src1,$src2,$dst\t! long" %}
7018 opcode(Assembler::mulx_op3, Assembler::arith_op);
7019 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7020 ins_pipe(mulL_reg_reg);
7021 %}
7023 // Immediate Multiplication
7024 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7025 effect(DEF dst, USE src1, USE src2);
7026 size(4);
7027 format %{ "MULX $src1,$src2,$dst" %}
7028 opcode(Assembler::mulx_op3, Assembler::arith_op);
7029 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7030 ins_pipe(mulL_reg_imm);
7031 %}
7033 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7034 effect(DEF dst, USE src1, USE src2);
7035 size(4);
7036 format %{ "SUB $src1,$src2,$dst\t! long" %}
7037 opcode(Assembler::sub_op3, Assembler::arith_op);
7038 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7039 ins_pipe(ialu_reg_reg);
7040 %}
7042 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7043 effect(DEF dst, USE src1, USE src2);
7044 size(4);
7045 format %{ "SUB $src1,$src2,$dst\t! long" %}
7046 opcode(Assembler::sub_op3, Assembler::arith_op);
7047 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7048 ins_pipe(ialu_reg_reg);
7049 %}
7051 // Register Long Remainder
7052 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7053 match(Set dst (ModL src1 src2));
7054 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7055 expand %{
7056 iRegL tmp1;
7057 iRegL tmp2;
7058 divL_reg_reg_1(tmp1, src1, src2);
7059 mulL_reg_reg_1(tmp2, tmp1, src2);
7060 subL_reg_reg_1(dst, src1, tmp2);
7061 %}
7062 %}
7064 // Register Long Remainder
7065 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7066 match(Set dst (ModL src1 src2));
7067 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7068 expand %{
7069 iRegL tmp1;
7070 iRegL tmp2;
7071 divL_reg_imm13_1(tmp1, src1, src2);
7072 mulL_reg_imm13_1(tmp2, tmp1, src2);
7073 subL_reg_reg_2 (dst, src1, tmp2);
7074 %}
7075 %}
7077 // Integer Shift Instructions
7078 // Register Shift Left
7079 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7080 match(Set dst (LShiftI src1 src2));
7082 size(4);
7083 format %{ "SLL $src1,$src2,$dst" %}
7084 opcode(Assembler::sll_op3, Assembler::arith_op);
7085 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7086 ins_pipe(ialu_reg_reg);
7087 %}
7089 // Register Shift Left Immediate
7090 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7091 match(Set dst (LShiftI src1 src2));
7093 size(4);
7094 format %{ "SLL $src1,$src2,$dst" %}
7095 opcode(Assembler::sll_op3, Assembler::arith_op);
7096 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7097 ins_pipe(ialu_reg_imm);
7098 %}
7100 // Register Shift Left
7101 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7102 match(Set dst (LShiftL src1 src2));
7104 size(4);
7105 format %{ "SLLX $src1,$src2,$dst" %}
7106 opcode(Assembler::sllx_op3, Assembler::arith_op);
7107 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7108 ins_pipe(ialu_reg_reg);
7109 %}
7111 // Register Shift Left Immediate
7112 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7113 match(Set dst (LShiftL src1 src2));
7115 size(4);
7116 format %{ "SLLX $src1,$src2,$dst" %}
7117 opcode(Assembler::sllx_op3, Assembler::arith_op);
7118 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7119 ins_pipe(ialu_reg_imm);
7120 %}
7122 // Register Arithmetic Shift Right
7123 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7124 match(Set dst (RShiftI src1 src2));
7125 size(4);
7126 format %{ "SRA $src1,$src2,$dst" %}
7127 opcode(Assembler::sra_op3, Assembler::arith_op);
7128 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7129 ins_pipe(ialu_reg_reg);
7130 %}
7132 // Register Arithmetic Shift Right Immediate
7133 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7134 match(Set dst (RShiftI src1 src2));
7136 size(4);
7137 format %{ "SRA $src1,$src2,$dst" %}
7138 opcode(Assembler::sra_op3, Assembler::arith_op);
7139 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7140 ins_pipe(ialu_reg_imm);
7141 %}
7143 // Register Shift Right Arithmatic Long
7144 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7145 match(Set dst (RShiftL src1 src2));
7147 size(4);
7148 format %{ "SRAX $src1,$src2,$dst" %}
7149 opcode(Assembler::srax_op3, Assembler::arith_op);
7150 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7151 ins_pipe(ialu_reg_reg);
7152 %}
7154 // Register Shift Left Immediate
7155 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7156 match(Set dst (RShiftL src1 src2));
7158 size(4);
7159 format %{ "SRAX $src1,$src2,$dst" %}
7160 opcode(Assembler::srax_op3, Assembler::arith_op);
7161 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7162 ins_pipe(ialu_reg_imm);
7163 %}
7165 // Register Shift Right
7166 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7167 match(Set dst (URShiftI src1 src2));
7169 size(4);
7170 format %{ "SRL $src1,$src2,$dst" %}
7171 opcode(Assembler::srl_op3, Assembler::arith_op);
7172 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7173 ins_pipe(ialu_reg_reg);
7174 %}
7176 // Register Shift Right Immediate
7177 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7178 match(Set dst (URShiftI src1 src2));
7180 size(4);
7181 format %{ "SRL $src1,$src2,$dst" %}
7182 opcode(Assembler::srl_op3, Assembler::arith_op);
7183 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7184 ins_pipe(ialu_reg_imm);
7185 %}
7187 // Register Shift Right
7188 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7189 match(Set dst (URShiftL src1 src2));
7191 size(4);
7192 format %{ "SRLX $src1,$src2,$dst" %}
7193 opcode(Assembler::srlx_op3, Assembler::arith_op);
7194 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7195 ins_pipe(ialu_reg_reg);
7196 %}
7198 // Register Shift Right Immediate
7199 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7200 match(Set dst (URShiftL src1 src2));
7202 size(4);
7203 format %{ "SRLX $src1,$src2,$dst" %}
7204 opcode(Assembler::srlx_op3, Assembler::arith_op);
7205 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7206 ins_pipe(ialu_reg_imm);
7207 %}
7209 // Register Shift Right Immediate with a CastP2X
7210 #ifdef _LP64
7211 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7212 match(Set dst (URShiftL (CastP2X src1) src2));
7213 size(4);
7214 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7215 opcode(Assembler::srlx_op3, Assembler::arith_op);
7216 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7217 ins_pipe(ialu_reg_imm);
7218 %}
7219 #else
7220 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7221 match(Set dst (URShiftI (CastP2X src1) src2));
7222 size(4);
7223 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7224 opcode(Assembler::srl_op3, Assembler::arith_op);
7225 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7226 ins_pipe(ialu_reg_imm);
7227 %}
7228 #endif
7231 //----------Floating Point Arithmetic Instructions-----------------------------
7233 // Add float single precision
7234 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7235 match(Set dst (AddF src1 src2));
7237 size(4);
7238 format %{ "FADDS $src1,$src2,$dst" %}
7239 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7240 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7241 ins_pipe(faddF_reg_reg);
7242 %}
7244 // Add float double precision
7245 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7246 match(Set dst (AddD src1 src2));
7248 size(4);
7249 format %{ "FADDD $src1,$src2,$dst" %}
7250 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7251 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7252 ins_pipe(faddD_reg_reg);
7253 %}
7255 // Sub float single precision
7256 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7257 match(Set dst (SubF src1 src2));
7259 size(4);
7260 format %{ "FSUBS $src1,$src2,$dst" %}
7261 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7262 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7263 ins_pipe(faddF_reg_reg);
7264 %}
7266 // Sub float double precision
7267 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7268 match(Set dst (SubD src1 src2));
7270 size(4);
7271 format %{ "FSUBD $src1,$src2,$dst" %}
7272 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7273 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7274 ins_pipe(faddD_reg_reg);
7275 %}
7277 // Mul float single precision
7278 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7279 match(Set dst (MulF src1 src2));
7281 size(4);
7282 format %{ "FMULS $src1,$src2,$dst" %}
7283 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7284 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7285 ins_pipe(fmulF_reg_reg);
7286 %}
7288 // Mul float double precision
7289 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7290 match(Set dst (MulD src1 src2));
7292 size(4);
7293 format %{ "FMULD $src1,$src2,$dst" %}
7294 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7295 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7296 ins_pipe(fmulD_reg_reg);
7297 %}
7299 // Div float single precision
7300 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7301 match(Set dst (DivF src1 src2));
7303 size(4);
7304 format %{ "FDIVS $src1,$src2,$dst" %}
7305 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7306 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7307 ins_pipe(fdivF_reg_reg);
7308 %}
7310 // Div float double precision
7311 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7312 match(Set dst (DivD src1 src2));
7314 size(4);
7315 format %{ "FDIVD $src1,$src2,$dst" %}
7316 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7317 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7318 ins_pipe(fdivD_reg_reg);
7319 %}
7321 // Absolute float double precision
7322 instruct absD_reg(regD dst, regD src) %{
7323 match(Set dst (AbsD src));
7325 format %{ "FABSd $src,$dst" %}
7326 ins_encode(fabsd(dst, src));
7327 ins_pipe(faddD_reg);
7328 %}
7330 // Absolute float single precision
7331 instruct absF_reg(regF dst, regF src) %{
7332 match(Set dst (AbsF src));
7334 format %{ "FABSs $src,$dst" %}
7335 ins_encode(fabss(dst, src));
7336 ins_pipe(faddF_reg);
7337 %}
7339 instruct negF_reg(regF dst, regF src) %{
7340 match(Set dst (NegF src));
7342 size(4);
7343 format %{ "FNEGs $src,$dst" %}
7344 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7345 ins_encode(form3_opf_rs2F_rdF(src, dst));
7346 ins_pipe(faddF_reg);
7347 %}
7349 instruct negD_reg(regD dst, regD src) %{
7350 match(Set dst (NegD src));
7352 format %{ "FNEGd $src,$dst" %}
7353 ins_encode(fnegd(dst, src));
7354 ins_pipe(faddD_reg);
7355 %}
7357 // Sqrt float double precision
7358 instruct sqrtF_reg_reg(regF dst, regF src) %{
7359 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7361 size(4);
7362 format %{ "FSQRTS $src,$dst" %}
7363 ins_encode(fsqrts(dst, src));
7364 ins_pipe(fdivF_reg_reg);
7365 %}
7367 // Sqrt float double precision
7368 instruct sqrtD_reg_reg(regD dst, regD src) %{
7369 match(Set dst (SqrtD src));
7371 size(4);
7372 format %{ "FSQRTD $src,$dst" %}
7373 ins_encode(fsqrtd(dst, src));
7374 ins_pipe(fdivD_reg_reg);
7375 %}
7377 //----------Logical Instructions-----------------------------------------------
7378 // And Instructions
7379 // Register And
7380 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7381 match(Set dst (AndI src1 src2));
7383 size(4);
7384 format %{ "AND $src1,$src2,$dst" %}
7385 opcode(Assembler::and_op3, Assembler::arith_op);
7386 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7387 ins_pipe(ialu_reg_reg);
7388 %}
7390 // Immediate And
7391 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7392 match(Set dst (AndI src1 src2));
7394 size(4);
7395 format %{ "AND $src1,$src2,$dst" %}
7396 opcode(Assembler::and_op3, Assembler::arith_op);
7397 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7398 ins_pipe(ialu_reg_imm);
7399 %}
7401 // Register And Long
7402 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7403 match(Set dst (AndL src1 src2));
7405 ins_cost(DEFAULT_COST);
7406 size(4);
7407 format %{ "AND $src1,$src2,$dst\t! long" %}
7408 opcode(Assembler::and_op3, Assembler::arith_op);
7409 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7410 ins_pipe(ialu_reg_reg);
7411 %}
7413 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7414 match(Set dst (AndL src1 con));
7416 ins_cost(DEFAULT_COST);
7417 size(4);
7418 format %{ "AND $src1,$con,$dst\t! long" %}
7419 opcode(Assembler::and_op3, Assembler::arith_op);
7420 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7421 ins_pipe(ialu_reg_imm);
7422 %}
7424 // Or Instructions
7425 // Register Or
7426 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7427 match(Set dst (OrI src1 src2));
7429 size(4);
7430 format %{ "OR $src1,$src2,$dst" %}
7431 opcode(Assembler::or_op3, Assembler::arith_op);
7432 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7433 ins_pipe(ialu_reg_reg);
7434 %}
7436 // Immediate Or
7437 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7438 match(Set dst (OrI src1 src2));
7440 size(4);
7441 format %{ "OR $src1,$src2,$dst" %}
7442 opcode(Assembler::or_op3, Assembler::arith_op);
7443 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7444 ins_pipe(ialu_reg_imm);
7445 %}
7447 // Register Or Long
7448 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7449 match(Set dst (OrL src1 src2));
7451 ins_cost(DEFAULT_COST);
7452 size(4);
7453 format %{ "OR $src1,$src2,$dst\t! long" %}
7454 opcode(Assembler::or_op3, Assembler::arith_op);
7455 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7456 ins_pipe(ialu_reg_reg);
7457 %}
7459 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7460 match(Set dst (OrL src1 con));
7461 ins_cost(DEFAULT_COST*2);
7463 ins_cost(DEFAULT_COST);
7464 size(4);
7465 format %{ "OR $src1,$con,$dst\t! long" %}
7466 opcode(Assembler::or_op3, Assembler::arith_op);
7467 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7468 ins_pipe(ialu_reg_imm);
7469 %}
7471 #ifndef _LP64
7473 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7474 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7475 match(Set dst (OrI src1 (CastP2X src2)));
7477 size(4);
7478 format %{ "OR $src1,$src2,$dst" %}
7479 opcode(Assembler::or_op3, Assembler::arith_op);
7480 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7481 ins_pipe(ialu_reg_reg);
7482 %}
7484 #else
7486 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7487 match(Set dst (OrL src1 (CastP2X src2)));
7489 ins_cost(DEFAULT_COST);
7490 size(4);
7491 format %{ "OR $src1,$src2,$dst\t! long" %}
7492 opcode(Assembler::or_op3, Assembler::arith_op);
7493 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7494 ins_pipe(ialu_reg_reg);
7495 %}
7497 #endif
7499 // Xor Instructions
7500 // Register Xor
7501 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7502 match(Set dst (XorI src1 src2));
7504 size(4);
7505 format %{ "XOR $src1,$src2,$dst" %}
7506 opcode(Assembler::xor_op3, Assembler::arith_op);
7507 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7508 ins_pipe(ialu_reg_reg);
7509 %}
7511 // Immediate Xor
7512 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7513 match(Set dst (XorI src1 src2));
7515 size(4);
7516 format %{ "XOR $src1,$src2,$dst" %}
7517 opcode(Assembler::xor_op3, Assembler::arith_op);
7518 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7519 ins_pipe(ialu_reg_imm);
7520 %}
7522 // Register Xor Long
7523 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7524 match(Set dst (XorL src1 src2));
7526 ins_cost(DEFAULT_COST);
7527 size(4);
7528 format %{ "XOR $src1,$src2,$dst\t! long" %}
7529 opcode(Assembler::xor_op3, Assembler::arith_op);
7530 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7531 ins_pipe(ialu_reg_reg);
7532 %}
7534 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7535 match(Set dst (XorL src1 con));
7537 ins_cost(DEFAULT_COST);
7538 size(4);
7539 format %{ "XOR $src1,$con,$dst\t! long" %}
7540 opcode(Assembler::xor_op3, Assembler::arith_op);
7541 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7542 ins_pipe(ialu_reg_imm);
7543 %}
7545 //----------Convert to Boolean-------------------------------------------------
7546 // Nice hack for 32-bit tests but doesn't work for
7547 // 64-bit pointers.
7548 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7549 match(Set dst (Conv2B src));
7550 effect( KILL ccr );
7551 ins_cost(DEFAULT_COST*2);
7552 format %{ "CMP R_G0,$src\n\t"
7553 "ADDX R_G0,0,$dst" %}
7554 ins_encode( enc_to_bool( src, dst ) );
7555 ins_pipe(ialu_reg_ialu);
7556 %}
7558 #ifndef _LP64
7559 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7560 match(Set dst (Conv2B src));
7561 effect( KILL ccr );
7562 ins_cost(DEFAULT_COST*2);
7563 format %{ "CMP R_G0,$src\n\t"
7564 "ADDX R_G0,0,$dst" %}
7565 ins_encode( enc_to_bool( src, dst ) );
7566 ins_pipe(ialu_reg_ialu);
7567 %}
7568 #else
7569 instruct convP2B( iRegI dst, iRegP src ) %{
7570 match(Set dst (Conv2B src));
7571 ins_cost(DEFAULT_COST*2);
7572 format %{ "MOV $src,$dst\n\t"
7573 "MOVRNZ $src,1,$dst" %}
7574 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7575 ins_pipe(ialu_clr_and_mover);
7576 %}
7577 #endif
7579 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7580 match(Set dst (CmpLTMask p q));
7581 effect( KILL ccr );
7582 ins_cost(DEFAULT_COST*4);
7583 format %{ "CMP $p,$q\n\t"
7584 "MOV #0,$dst\n\t"
7585 "BLT,a .+8\n\t"
7586 "MOV #-1,$dst" %}
7587 ins_encode( enc_ltmask(p,q,dst) );
7588 ins_pipe(ialu_reg_reg_ialu);
7589 %}
7591 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7592 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7593 effect(KILL ccr, TEMP tmp);
7594 ins_cost(DEFAULT_COST*3);
7596 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7597 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7598 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7599 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7600 ins_pipe( cadd_cmpltmask );
7601 %}
7603 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7604 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
7605 effect( KILL ccr, TEMP tmp);
7606 ins_cost(DEFAULT_COST*3);
7608 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7609 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7610 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7611 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7612 ins_pipe( cadd_cmpltmask );
7613 %}
7615 //----------Arithmetic Conversion Instructions---------------------------------
7616 // The conversions operations are all Alpha sorted. Please keep it that way!
7618 instruct convD2F_reg(regF dst, regD src) %{
7619 match(Set dst (ConvD2F src));
7620 size(4);
7621 format %{ "FDTOS $src,$dst" %}
7622 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7623 ins_encode(form3_opf_rs2D_rdF(src, dst));
7624 ins_pipe(fcvtD2F);
7625 %}
7628 // Convert a double to an int in a float register.
7629 // If the double is a NAN, stuff a zero in instead.
7630 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7631 effect(DEF dst, USE src, KILL fcc0);
7632 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7633 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7634 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7635 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7636 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7637 "skip:" %}
7638 ins_encode(form_d2i_helper(src,dst));
7639 ins_pipe(fcvtD2I);
7640 %}
7642 instruct convD2I_reg(stackSlotI dst, regD src) %{
7643 match(Set dst (ConvD2I src));
7644 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7645 expand %{
7646 regF tmp;
7647 convD2I_helper(tmp, src);
7648 regF_to_stkI(dst, tmp);
7649 %}
7650 %}
7652 // Convert a double to a long in a double register.
7653 // If the double is a NAN, stuff a zero in instead.
7654 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7655 effect(DEF dst, USE src, KILL fcc0);
7656 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7657 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7658 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7659 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7660 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7661 "skip:" %}
7662 ins_encode(form_d2l_helper(src,dst));
7663 ins_pipe(fcvtD2L);
7664 %}
7667 // Double to Long conversion
7668 instruct convD2L_reg(stackSlotL dst, regD src) %{
7669 match(Set dst (ConvD2L src));
7670 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7671 expand %{
7672 regD tmp;
7673 convD2L_helper(tmp, src);
7674 regD_to_stkL(dst, tmp);
7675 %}
7676 %}
7679 instruct convF2D_reg(regD dst, regF src) %{
7680 match(Set dst (ConvF2D src));
7681 format %{ "FSTOD $src,$dst" %}
7682 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7683 ins_encode(form3_opf_rs2F_rdD(src, dst));
7684 ins_pipe(fcvtF2D);
7685 %}
7688 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7689 effect(DEF dst, USE src, KILL fcc0);
7690 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7691 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7692 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7693 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7694 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7695 "skip:" %}
7696 ins_encode(form_f2i_helper(src,dst));
7697 ins_pipe(fcvtF2I);
7698 %}
7700 instruct convF2I_reg(stackSlotI dst, regF src) %{
7701 match(Set dst (ConvF2I src));
7702 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7703 expand %{
7704 regF tmp;
7705 convF2I_helper(tmp, src);
7706 regF_to_stkI(dst, tmp);
7707 %}
7708 %}
7711 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
7712 effect(DEF dst, USE src, KILL fcc0);
7713 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7714 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7715 "FSTOX $src,$dst\t! convert in delay slot\n\t"
7716 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7717 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7718 "skip:" %}
7719 ins_encode(form_f2l_helper(src,dst));
7720 ins_pipe(fcvtF2L);
7721 %}
7723 // Float to Long conversion
7724 instruct convF2L_reg(stackSlotL dst, regF src) %{
7725 match(Set dst (ConvF2L src));
7726 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7727 expand %{
7728 regD tmp;
7729 convF2L_helper(tmp, src);
7730 regD_to_stkL(dst, tmp);
7731 %}
7732 %}
7735 instruct convI2D_helper(regD dst, regF tmp) %{
7736 effect(USE tmp, DEF dst);
7737 format %{ "FITOD $tmp,$dst" %}
7738 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7739 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
7740 ins_pipe(fcvtI2D);
7741 %}
7743 instruct convI2D_reg(stackSlotI src, regD dst) %{
7744 match(Set dst (ConvI2D src));
7745 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7746 expand %{
7747 regF tmp;
7748 stkI_to_regF( tmp, src);
7749 convI2D_helper( dst, tmp);
7750 %}
7751 %}
7753 instruct convI2D_mem( regD_low dst, memory mem ) %{
7754 match(Set dst (ConvI2D (LoadI mem)));
7755 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7756 size(8);
7757 format %{ "LDF $mem,$dst\n\t"
7758 "FITOD $dst,$dst" %}
7759 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
7760 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7761 ins_pipe(floadF_mem);
7762 %}
7765 instruct convI2F_helper(regF dst, regF tmp) %{
7766 effect(DEF dst, USE tmp);
7767 format %{ "FITOS $tmp,$dst" %}
7768 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
7769 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
7770 ins_pipe(fcvtI2F);
7771 %}
7773 instruct convI2F_reg( regF dst, stackSlotI src ) %{
7774 match(Set dst (ConvI2F src));
7775 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7776 expand %{
7777 regF tmp;
7778 stkI_to_regF(tmp,src);
7779 convI2F_helper(dst, tmp);
7780 %}
7781 %}
7783 instruct convI2F_mem( regF dst, memory mem ) %{
7784 match(Set dst (ConvI2F (LoadI mem)));
7785 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7786 size(8);
7787 format %{ "LDF $mem,$dst\n\t"
7788 "FITOS $dst,$dst" %}
7789 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
7790 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7791 ins_pipe(floadF_mem);
7792 %}
7795 instruct convI2L_reg(iRegL dst, iRegI src) %{
7796 match(Set dst (ConvI2L src));
7797 size(4);
7798 format %{ "SRA $src,0,$dst\t! int->long" %}
7799 opcode(Assembler::sra_op3, Assembler::arith_op);
7800 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7801 ins_pipe(ialu_reg_reg);
7802 %}
7804 // Zero-extend convert int to long
7805 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
7806 match(Set dst (AndL (ConvI2L src) mask) );
7807 size(4);
7808 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
7809 opcode(Assembler::srl_op3, Assembler::arith_op);
7810 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7811 ins_pipe(ialu_reg_reg);
7812 %}
7814 // Zero-extend long
7815 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
7816 match(Set dst (AndL src mask) );
7817 size(4);
7818 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
7819 opcode(Assembler::srl_op3, Assembler::arith_op);
7820 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7821 ins_pipe(ialu_reg_reg);
7822 %}
7824 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7825 match(Set dst (MoveF2I src));
7826 effect(DEF dst, USE src);
7827 ins_cost(MEMORY_REF_COST);
7829 size(4);
7830 format %{ "LDUW $src,$dst\t! MoveF2I" %}
7831 opcode(Assembler::lduw_op3);
7832 ins_encode(simple_form3_mem_reg( src, dst ) );
7833 ins_pipe(iload_mem);
7834 %}
7836 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
7837 match(Set dst (MoveI2F src));
7838 effect(DEF dst, USE src);
7839 ins_cost(MEMORY_REF_COST);
7841 size(4);
7842 format %{ "LDF $src,$dst\t! MoveI2F" %}
7843 opcode(Assembler::ldf_op3);
7844 ins_encode(simple_form3_mem_reg(src, dst));
7845 ins_pipe(floadF_stk);
7846 %}
7848 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
7849 match(Set dst (MoveD2L src));
7850 effect(DEF dst, USE src);
7851 ins_cost(MEMORY_REF_COST);
7853 size(4);
7854 format %{ "LDX $src,$dst\t! MoveD2L" %}
7855 opcode(Assembler::ldx_op3);
7856 ins_encode(simple_form3_mem_reg( src, dst ) );
7857 ins_pipe(iload_mem);
7858 %}
7860 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
7861 match(Set dst (MoveL2D src));
7862 effect(DEF dst, USE src);
7863 ins_cost(MEMORY_REF_COST);
7865 size(4);
7866 format %{ "LDDF $src,$dst\t! MoveL2D" %}
7867 opcode(Assembler::lddf_op3);
7868 ins_encode(simple_form3_mem_reg(src, dst));
7869 ins_pipe(floadD_stk);
7870 %}
7872 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
7873 match(Set dst (MoveF2I src));
7874 effect(DEF dst, USE src);
7875 ins_cost(MEMORY_REF_COST);
7877 size(4);
7878 format %{ "STF $src,$dst\t!MoveF2I" %}
7879 opcode(Assembler::stf_op3);
7880 ins_encode(simple_form3_mem_reg(dst, src));
7881 ins_pipe(fstoreF_stk_reg);
7882 %}
7884 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
7885 match(Set dst (MoveI2F src));
7886 effect(DEF dst, USE src);
7887 ins_cost(MEMORY_REF_COST);
7889 size(4);
7890 format %{ "STW $src,$dst\t!MoveI2F" %}
7891 opcode(Assembler::stw_op3);
7892 ins_encode(simple_form3_mem_reg( dst, src ) );
7893 ins_pipe(istore_mem_reg);
7894 %}
7896 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
7897 match(Set dst (MoveD2L src));
7898 effect(DEF dst, USE src);
7899 ins_cost(MEMORY_REF_COST);
7901 size(4);
7902 format %{ "STDF $src,$dst\t!MoveD2L" %}
7903 opcode(Assembler::stdf_op3);
7904 ins_encode(simple_form3_mem_reg(dst, src));
7905 ins_pipe(fstoreD_stk_reg);
7906 %}
7908 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
7909 match(Set dst (MoveL2D src));
7910 effect(DEF dst, USE src);
7911 ins_cost(MEMORY_REF_COST);
7913 size(4);
7914 format %{ "STX $src,$dst\t!MoveL2D" %}
7915 opcode(Assembler::stx_op3);
7916 ins_encode(simple_form3_mem_reg( dst, src ) );
7917 ins_pipe(istore_mem_reg);
7918 %}
7921 //-----------
7922 // Long to Double conversion using V8 opcodes.
7923 // Still useful because cheetah traps and becomes
7924 // amazingly slow for some common numbers.
7926 // Magic constant, 0x43300000
7927 instruct loadConI_x43300000(iRegI dst) %{
7928 effect(DEF dst);
7929 size(4);
7930 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
7931 ins_encode(SetHi22(0x43300000, dst));
7932 ins_pipe(ialu_none);
7933 %}
7935 // Magic constant, 0x41f00000
7936 instruct loadConI_x41f00000(iRegI dst) %{
7937 effect(DEF dst);
7938 size(4);
7939 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
7940 ins_encode(SetHi22(0x41f00000, dst));
7941 ins_pipe(ialu_none);
7942 %}
7944 // Construct a double from two float halves
7945 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
7946 effect(DEF dst, USE src1, USE src2);
7947 size(8);
7948 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
7949 "FMOVS $src2.lo,$dst.lo" %}
7950 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
7951 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
7952 ins_pipe(faddD_reg_reg);
7953 %}
7955 // Convert integer in high half of a double register (in the lower half of
7956 // the double register file) to double
7957 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
7958 effect(DEF dst, USE src);
7959 size(4);
7960 format %{ "FITOD $src,$dst" %}
7961 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7962 ins_encode(form3_opf_rs2D_rdD(src, dst));
7963 ins_pipe(fcvtLHi2D);
7964 %}
7966 // Add float double precision
7967 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
7968 effect(DEF dst, USE src1, USE src2);
7969 size(4);
7970 format %{ "FADDD $src1,$src2,$dst" %}
7971 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7972 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7973 ins_pipe(faddD_reg_reg);
7974 %}
7976 // Sub float double precision
7977 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
7978 effect(DEF dst, USE src1, USE src2);
7979 size(4);
7980 format %{ "FSUBD $src1,$src2,$dst" %}
7981 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7982 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7983 ins_pipe(faddD_reg_reg);
7984 %}
7986 // Mul float double precision
7987 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
7988 effect(DEF dst, USE src1, USE src2);
7989 size(4);
7990 format %{ "FMULD $src1,$src2,$dst" %}
7991 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7992 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7993 ins_pipe(fmulD_reg_reg);
7994 %}
7996 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
7997 match(Set dst (ConvL2D src));
7998 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8000 expand %{
8001 regD_low tmpsrc;
8002 iRegI ix43300000;
8003 iRegI ix41f00000;
8004 stackSlotL lx43300000;
8005 stackSlotL lx41f00000;
8006 regD_low dx43300000;
8007 regD dx41f00000;
8008 regD tmp1;
8009 regD_low tmp2;
8010 regD tmp3;
8011 regD tmp4;
8013 stkL_to_regD(tmpsrc, src);
8015 loadConI_x43300000(ix43300000);
8016 loadConI_x41f00000(ix41f00000);
8017 regI_to_stkLHi(lx43300000, ix43300000);
8018 regI_to_stkLHi(lx41f00000, ix41f00000);
8019 stkL_to_regD(dx43300000, lx43300000);
8020 stkL_to_regD(dx41f00000, lx41f00000);
8022 convI2D_regDHi_regD(tmp1, tmpsrc);
8023 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8024 subD_regD_regD(tmp3, tmp2, dx43300000);
8025 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8026 addD_regD_regD(dst, tmp3, tmp4);
8027 %}
8028 %}
8030 // Long to Double conversion using fast fxtof
8031 instruct convL2D_helper(regD dst, regD tmp) %{
8032 effect(DEF dst, USE tmp);
8033 size(4);
8034 format %{ "FXTOD $tmp,$dst" %}
8035 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8036 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8037 ins_pipe(fcvtL2D);
8038 %}
8040 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8041 predicate(VM_Version::has_fast_fxtof());
8042 match(Set dst (ConvL2D src));
8043 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8044 expand %{
8045 regD tmp;
8046 stkL_to_regD(tmp, src);
8047 convL2D_helper(dst, tmp);
8048 %}
8049 %}
8051 //-----------
8052 // Long to Float conversion using V8 opcodes.
8053 // Still useful because cheetah traps and becomes
8054 // amazingly slow for some common numbers.
8056 // Long to Float conversion using fast fxtof
8057 instruct convL2F_helper(regF dst, regD tmp) %{
8058 effect(DEF dst, USE tmp);
8059 size(4);
8060 format %{ "FXTOS $tmp,$dst" %}
8061 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8062 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8063 ins_pipe(fcvtL2F);
8064 %}
8066 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8067 match(Set dst (ConvL2F src));
8068 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8069 expand %{
8070 regD tmp;
8071 stkL_to_regD(tmp, src);
8072 convL2F_helper(dst, tmp);
8073 %}
8074 %}
8075 //-----------
8077 instruct convL2I_reg(iRegI dst, iRegL src) %{
8078 match(Set dst (ConvL2I src));
8079 #ifndef _LP64
8080 format %{ "MOV $src.lo,$dst\t! long->int" %}
8081 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8082 ins_pipe(ialu_move_reg_I_to_L);
8083 #else
8084 size(4);
8085 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8086 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8087 ins_pipe(ialu_reg);
8088 #endif
8089 %}
8091 // Register Shift Right Immediate
8092 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8093 match(Set dst (ConvL2I (RShiftL src cnt)));
8095 size(4);
8096 format %{ "SRAX $src,$cnt,$dst" %}
8097 opcode(Assembler::srax_op3, Assembler::arith_op);
8098 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8099 ins_pipe(ialu_reg_imm);
8100 %}
8102 // Replicate scalar to packed byte values in Double register
8103 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8104 effect(DEF dst, USE src);
8105 format %{ "SLLX $src,56,$dst\n\t"
8106 "SRLX $dst, 8,O7\n\t"
8107 "OR $dst,O7,$dst\n\t"
8108 "SRLX $dst,16,O7\n\t"
8109 "OR $dst,O7,$dst\n\t"
8110 "SRLX $dst,32,O7\n\t"
8111 "OR $dst,O7,$dst\t! replicate8B" %}
8112 ins_encode( enc_repl8b(src, dst));
8113 ins_pipe(ialu_reg);
8114 %}
8116 // Replicate scalar to packed byte values in Double register
8117 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8118 match(Set dst (Replicate8B src));
8119 expand %{
8120 iRegL tmp;
8121 Repl8B_reg_helper(tmp, src);
8122 regL_to_stkD(dst, tmp);
8123 %}
8124 %}
8126 // Replicate scalar constant to packed byte values in Double register
8127 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8128 match(Set dst (Replicate8B src));
8129 #ifdef _LP64
8130 size(36);
8131 #else
8132 size(8);
8133 #endif
8134 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8135 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8136 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8137 ins_pipe(loadConFD);
8138 %}
8140 // Replicate scalar to packed char values into stack slot
8141 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8142 effect(DEF dst, USE src);
8143 format %{ "SLLX $src,48,$dst\n\t"
8144 "SRLX $dst,16,O7\n\t"
8145 "OR $dst,O7,$dst\n\t"
8146 "SRLX $dst,32,O7\n\t"
8147 "OR $dst,O7,$dst\t! replicate4C" %}
8148 ins_encode( enc_repl4s(src, dst) );
8149 ins_pipe(ialu_reg);
8150 %}
8152 // Replicate scalar to packed char values into stack slot
8153 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8154 match(Set dst (Replicate4C src));
8155 expand %{
8156 iRegL tmp;
8157 Repl4C_reg_helper(tmp, src);
8158 regL_to_stkD(dst, tmp);
8159 %}
8160 %}
8162 // Replicate scalar constant to packed char values in Double register
8163 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8164 match(Set dst (Replicate4C src));
8165 #ifdef _LP64
8166 size(36);
8167 #else
8168 size(8);
8169 #endif
8170 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8171 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8172 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8173 ins_pipe(loadConFD);
8174 %}
8176 // Replicate scalar to packed short values into stack slot
8177 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8178 effect(DEF dst, USE src);
8179 format %{ "SLLX $src,48,$dst\n\t"
8180 "SRLX $dst,16,O7\n\t"
8181 "OR $dst,O7,$dst\n\t"
8182 "SRLX $dst,32,O7\n\t"
8183 "OR $dst,O7,$dst\t! replicate4S" %}
8184 ins_encode( enc_repl4s(src, dst) );
8185 ins_pipe(ialu_reg);
8186 %}
8188 // Replicate scalar to packed short values into stack slot
8189 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8190 match(Set dst (Replicate4S src));
8191 expand %{
8192 iRegL tmp;
8193 Repl4S_reg_helper(tmp, src);
8194 regL_to_stkD(dst, tmp);
8195 %}
8196 %}
8198 // Replicate scalar constant to packed short values in Double register
8199 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8200 match(Set dst (Replicate4S src));
8201 #ifdef _LP64
8202 size(36);
8203 #else
8204 size(8);
8205 #endif
8206 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8207 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8208 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8209 ins_pipe(loadConFD);
8210 %}
8212 // Replicate scalar to packed int values in Double register
8213 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8214 effect(DEF dst, USE src);
8215 format %{ "SLLX $src,32,$dst\n\t"
8216 "SRLX $dst,32,O7\n\t"
8217 "OR $dst,O7,$dst\t! replicate2I" %}
8218 ins_encode( enc_repl2i(src, dst));
8219 ins_pipe(ialu_reg);
8220 %}
8222 // Replicate scalar to packed int values in Double register
8223 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8224 match(Set dst (Replicate2I src));
8225 expand %{
8226 iRegL tmp;
8227 Repl2I_reg_helper(tmp, src);
8228 regL_to_stkD(dst, tmp);
8229 %}
8230 %}
8232 // Replicate scalar zero constant to packed int values in Double register
8233 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8234 match(Set dst (Replicate2I src));
8235 #ifdef _LP64
8236 size(36);
8237 #else
8238 size(8);
8239 #endif
8240 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8241 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8242 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8243 ins_pipe(loadConFD);
8244 %}
8246 //----------Control Flow Instructions------------------------------------------
8247 // Compare Instructions
8248 // Compare Integers
8249 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8250 match(Set icc (CmpI op1 op2));
8251 effect( DEF icc, USE op1, USE op2 );
8253 size(4);
8254 format %{ "CMP $op1,$op2" %}
8255 opcode(Assembler::subcc_op3, Assembler::arith_op);
8256 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8257 ins_pipe(ialu_cconly_reg_reg);
8258 %}
8260 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8261 match(Set icc (CmpU op1 op2));
8263 size(4);
8264 format %{ "CMP $op1,$op2\t! unsigned" %}
8265 opcode(Assembler::subcc_op3, Assembler::arith_op);
8266 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8267 ins_pipe(ialu_cconly_reg_reg);
8268 %}
8270 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8271 match(Set icc (CmpI op1 op2));
8272 effect( DEF icc, USE op1 );
8274 size(4);
8275 format %{ "CMP $op1,$op2" %}
8276 opcode(Assembler::subcc_op3, Assembler::arith_op);
8277 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8278 ins_pipe(ialu_cconly_reg_imm);
8279 %}
8281 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8282 match(Set icc (CmpI (AndI op1 op2) zero));
8284 size(4);
8285 format %{ "BTST $op2,$op1" %}
8286 opcode(Assembler::andcc_op3, Assembler::arith_op);
8287 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8288 ins_pipe(ialu_cconly_reg_reg_zero);
8289 %}
8291 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8292 match(Set icc (CmpI (AndI op1 op2) zero));
8294 size(4);
8295 format %{ "BTST $op2,$op1" %}
8296 opcode(Assembler::andcc_op3, Assembler::arith_op);
8297 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8298 ins_pipe(ialu_cconly_reg_imm_zero);
8299 %}
8301 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8302 match(Set xcc (CmpL op1 op2));
8303 effect( DEF xcc, USE op1, USE op2 );
8305 size(4);
8306 format %{ "CMP $op1,$op2\t\t! long" %}
8307 opcode(Assembler::subcc_op3, Assembler::arith_op);
8308 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8309 ins_pipe(ialu_cconly_reg_reg);
8310 %}
8312 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8313 match(Set xcc (CmpL op1 con));
8314 effect( DEF xcc, USE op1, USE con );
8316 size(4);
8317 format %{ "CMP $op1,$con\t\t! long" %}
8318 opcode(Assembler::subcc_op3, Assembler::arith_op);
8319 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8320 ins_pipe(ialu_cconly_reg_reg);
8321 %}
8323 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8324 match(Set xcc (CmpL (AndL op1 op2) zero));
8325 effect( DEF xcc, USE op1, USE op2 );
8327 size(4);
8328 format %{ "BTST $op1,$op2\t\t! long" %}
8329 opcode(Assembler::andcc_op3, Assembler::arith_op);
8330 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8331 ins_pipe(ialu_cconly_reg_reg);
8332 %}
8334 // useful for checking the alignment of a pointer:
8335 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8336 match(Set xcc (CmpL (AndL op1 con) zero));
8337 effect( DEF xcc, USE op1, USE con );
8339 size(4);
8340 format %{ "BTST $op1,$con\t\t! long" %}
8341 opcode(Assembler::andcc_op3, Assembler::arith_op);
8342 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8343 ins_pipe(ialu_cconly_reg_reg);
8344 %}
8346 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8347 match(Set icc (CmpU op1 op2));
8349 size(4);
8350 format %{ "CMP $op1,$op2\t! unsigned" %}
8351 opcode(Assembler::subcc_op3, Assembler::arith_op);
8352 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8353 ins_pipe(ialu_cconly_reg_imm);
8354 %}
8356 // Compare Pointers
8357 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8358 match(Set pcc (CmpP op1 op2));
8360 size(4);
8361 format %{ "CMP $op1,$op2\t! ptr" %}
8362 opcode(Assembler::subcc_op3, Assembler::arith_op);
8363 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8364 ins_pipe(ialu_cconly_reg_reg);
8365 %}
8367 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8368 match(Set pcc (CmpP op1 op2));
8370 size(4);
8371 format %{ "CMP $op1,$op2\t! ptr" %}
8372 opcode(Assembler::subcc_op3, Assembler::arith_op);
8373 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8374 ins_pipe(ialu_cconly_reg_imm);
8375 %}
8377 // Compare Narrow oops
8378 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8379 match(Set icc (CmpN op1 op2));
8381 size(4);
8382 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8383 opcode(Assembler::subcc_op3, Assembler::arith_op);
8384 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8385 ins_pipe(ialu_cconly_reg_reg);
8386 %}
8388 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8389 match(Set icc (CmpN op1 op2));
8391 size(4);
8392 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8393 opcode(Assembler::subcc_op3, Assembler::arith_op);
8394 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8395 ins_pipe(ialu_cconly_reg_imm);
8396 %}
8398 //----------Max and Min--------------------------------------------------------
8399 // Min Instructions
8400 // Conditional move for min
8401 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8402 effect( USE_DEF op2, USE op1, USE icc );
8404 size(4);
8405 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8406 opcode(Assembler::less);
8407 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8408 ins_pipe(ialu_reg_flags);
8409 %}
8411 // Min Register with Register.
8412 instruct minI_eReg(iRegI op1, iRegI op2) %{
8413 match(Set op2 (MinI op1 op2));
8414 ins_cost(DEFAULT_COST*2);
8415 expand %{
8416 flagsReg icc;
8417 compI_iReg(icc,op1,op2);
8418 cmovI_reg_lt(op2,op1,icc);
8419 %}
8420 %}
8422 // Max Instructions
8423 // Conditional move for max
8424 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8425 effect( USE_DEF op2, USE op1, USE icc );
8426 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8427 opcode(Assembler::greater);
8428 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8429 ins_pipe(ialu_reg_flags);
8430 %}
8432 // Max Register with Register
8433 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8434 match(Set op2 (MaxI op1 op2));
8435 ins_cost(DEFAULT_COST*2);
8436 expand %{
8437 flagsReg icc;
8438 compI_iReg(icc,op1,op2);
8439 cmovI_reg_gt(op2,op1,icc);
8440 %}
8441 %}
8444 //----------Float Compares----------------------------------------------------
8445 // Compare floating, generate condition code
8446 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8447 match(Set fcc (CmpF src1 src2));
8449 size(4);
8450 format %{ "FCMPs $fcc,$src1,$src2" %}
8451 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8452 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8453 ins_pipe(faddF_fcc_reg_reg_zero);
8454 %}
8456 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8457 match(Set fcc (CmpD src1 src2));
8459 size(4);
8460 format %{ "FCMPd $fcc,$src1,$src2" %}
8461 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8462 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8463 ins_pipe(faddD_fcc_reg_reg_zero);
8464 %}
8467 // Compare floating, generate -1,0,1
8468 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8469 match(Set dst (CmpF3 src1 src2));
8470 effect(KILL fcc0);
8471 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8472 format %{ "fcmpl $dst,$src1,$src2" %}
8473 // Primary = float
8474 opcode( true );
8475 ins_encode( floating_cmp( dst, src1, src2 ) );
8476 ins_pipe( floating_cmp );
8477 %}
8479 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8480 match(Set dst (CmpD3 src1 src2));
8481 effect(KILL fcc0);
8482 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8483 format %{ "dcmpl $dst,$src1,$src2" %}
8484 // Primary = double (not float)
8485 opcode( false );
8486 ins_encode( floating_cmp( dst, src1, src2 ) );
8487 ins_pipe( floating_cmp );
8488 %}
8490 //----------Branches---------------------------------------------------------
8491 // Jump
8492 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8493 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8494 match(Jump switch_val);
8496 ins_cost(350);
8498 format %{ "SETHI [hi(table_base)],O7\n\t"
8499 "ADD O7, lo(table_base), O7\n\t"
8500 "LD [O7+$switch_val], O7\n\t"
8501 "JUMP O7"
8502 %}
8503 ins_encode( jump_enc( switch_val, table) );
8504 ins_pc_relative(1);
8505 ins_pipe(ialu_reg_reg);
8506 %}
8508 // Direct Branch. Use V8 version with longer range.
8509 instruct branch(label labl) %{
8510 match(Goto);
8511 effect(USE labl);
8513 size(8);
8514 ins_cost(BRANCH_COST);
8515 format %{ "BA $labl" %}
8516 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8517 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8518 ins_encode( enc_ba( labl ) );
8519 ins_pc_relative(1);
8520 ins_pipe(br);
8521 %}
8523 // Conditional Direct Branch
8524 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8525 match(If cmp icc);
8526 effect(USE labl);
8528 size(8);
8529 ins_cost(BRANCH_COST);
8530 format %{ "BP$cmp $icc,$labl" %}
8531 // Prim = bits 24-22, Secnd = bits 31-30
8532 ins_encode( enc_bp( labl, cmp, icc ) );
8533 ins_pc_relative(1);
8534 ins_pipe(br_cc);
8535 %}
8537 // Branch-on-register tests all 64 bits. We assume that values
8538 // in 64-bit registers always remains zero or sign extended
8539 // unless our code munges the high bits. Interrupts can chop
8540 // the high order bits to zero or sign at any time.
8541 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8542 match(If cmp (CmpI op1 zero));
8543 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8544 effect(USE labl);
8546 size(8);
8547 ins_cost(BRANCH_COST);
8548 format %{ "BR$cmp $op1,$labl" %}
8549 ins_encode( enc_bpr( labl, cmp, op1 ) );
8550 ins_pc_relative(1);
8551 ins_pipe(br_reg);
8552 %}
8554 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8555 match(If cmp (CmpP op1 null));
8556 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8557 effect(USE labl);
8559 size(8);
8560 ins_cost(BRANCH_COST);
8561 format %{ "BR$cmp $op1,$labl" %}
8562 ins_encode( enc_bpr( labl, cmp, op1 ) );
8563 ins_pc_relative(1);
8564 ins_pipe(br_reg);
8565 %}
8567 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8568 match(If cmp (CmpL op1 zero));
8569 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8570 effect(USE labl);
8572 size(8);
8573 ins_cost(BRANCH_COST);
8574 format %{ "BR$cmp $op1,$labl" %}
8575 ins_encode( enc_bpr( labl, cmp, op1 ) );
8576 ins_pc_relative(1);
8577 ins_pipe(br_reg);
8578 %}
8580 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8581 match(If cmp icc);
8582 effect(USE labl);
8584 format %{ "BP$cmp $icc,$labl" %}
8585 // Prim = bits 24-22, Secnd = bits 31-30
8586 ins_encode( enc_bp( labl, cmp, icc ) );
8587 ins_pc_relative(1);
8588 ins_pipe(br_cc);
8589 %}
8591 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8592 match(If cmp pcc);
8593 effect(USE labl);
8595 size(8);
8596 ins_cost(BRANCH_COST);
8597 format %{ "BP$cmp $pcc,$labl" %}
8598 // Prim = bits 24-22, Secnd = bits 31-30
8599 ins_encode( enc_bpx( labl, cmp, pcc ) );
8600 ins_pc_relative(1);
8601 ins_pipe(br_cc);
8602 %}
8604 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8605 match(If cmp fcc);
8606 effect(USE labl);
8608 size(8);
8609 ins_cost(BRANCH_COST);
8610 format %{ "FBP$cmp $fcc,$labl" %}
8611 // Prim = bits 24-22, Secnd = bits 31-30
8612 ins_encode( enc_fbp( labl, cmp, fcc ) );
8613 ins_pc_relative(1);
8614 ins_pipe(br_fcc);
8615 %}
8617 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8618 match(CountedLoopEnd cmp icc);
8619 effect(USE labl);
8621 size(8);
8622 ins_cost(BRANCH_COST);
8623 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8624 // Prim = bits 24-22, Secnd = bits 31-30
8625 ins_encode( enc_bp( labl, cmp, icc ) );
8626 ins_pc_relative(1);
8627 ins_pipe(br_cc);
8628 %}
8630 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8631 match(CountedLoopEnd cmp icc);
8632 effect(USE labl);
8634 size(8);
8635 ins_cost(BRANCH_COST);
8636 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8637 // Prim = bits 24-22, Secnd = bits 31-30
8638 ins_encode( enc_bp( labl, cmp, icc ) );
8639 ins_pc_relative(1);
8640 ins_pipe(br_cc);
8641 %}
8643 // ============================================================================
8644 // Long Compare
8645 //
8646 // Currently we hold longs in 2 registers. Comparing such values efficiently
8647 // is tricky. The flavor of compare used depends on whether we are testing
8648 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
8649 // The GE test is the negated LT test. The LE test can be had by commuting
8650 // the operands (yielding a GE test) and then negating; negate again for the
8651 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
8652 // NE test is negated from that.
8654 // Due to a shortcoming in the ADLC, it mixes up expressions like:
8655 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
8656 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
8657 // are collapsed internally in the ADLC's dfa-gen code. The match for
8658 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
8659 // foo match ends up with the wrong leaf. One fix is to not match both
8660 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
8661 // both forms beat the trinary form of long-compare and both are very useful
8662 // on Intel which has so few registers.
8664 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
8665 match(If cmp xcc);
8666 effect(USE labl);
8668 size(8);
8669 ins_cost(BRANCH_COST);
8670 format %{ "BP$cmp $xcc,$labl" %}
8671 // Prim = bits 24-22, Secnd = bits 31-30
8672 ins_encode( enc_bpl( labl, cmp, xcc ) );
8673 ins_pc_relative(1);
8674 ins_pipe(br_cc);
8675 %}
8677 // Manifest a CmpL3 result in an integer register. Very painful.
8678 // This is the test to avoid.
8679 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
8680 match(Set dst (CmpL3 src1 src2) );
8681 effect( KILL ccr );
8682 ins_cost(6*DEFAULT_COST);
8683 size(24);
8684 format %{ "CMP $src1,$src2\t\t! long\n"
8685 "\tBLT,a,pn done\n"
8686 "\tMOV -1,$dst\t! delay slot\n"
8687 "\tBGT,a,pn done\n"
8688 "\tMOV 1,$dst\t! delay slot\n"
8689 "\tCLR $dst\n"
8690 "done:" %}
8691 ins_encode( cmpl_flag(src1,src2,dst) );
8692 ins_pipe(cmpL_reg);
8693 %}
8695 // Conditional move
8696 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
8697 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8698 ins_cost(150);
8699 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8700 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8701 ins_pipe(ialu_reg);
8702 %}
8704 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
8705 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8706 ins_cost(140);
8707 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8708 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8709 ins_pipe(ialu_imm);
8710 %}
8712 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8713 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8714 ins_cost(150);
8715 format %{ "MOV$cmp $xcc,$src,$dst" %}
8716 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8717 ins_pipe(ialu_reg);
8718 %}
8720 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8721 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8722 ins_cost(140);
8723 format %{ "MOV$cmp $xcc,$src,$dst" %}
8724 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8725 ins_pipe(ialu_imm);
8726 %}
8728 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
8729 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
8730 ins_cost(150);
8731 format %{ "MOV$cmp $xcc,$src,$dst" %}
8732 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8733 ins_pipe(ialu_reg);
8734 %}
8736 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8737 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8738 ins_cost(150);
8739 format %{ "MOV$cmp $xcc,$src,$dst" %}
8740 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8741 ins_pipe(ialu_reg);
8742 %}
8744 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8745 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8746 ins_cost(140);
8747 format %{ "MOV$cmp $xcc,$src,$dst" %}
8748 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8749 ins_pipe(ialu_imm);
8750 %}
8752 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8753 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8754 ins_cost(150);
8755 opcode(0x101);
8756 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
8757 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8758 ins_pipe(int_conditional_float_move);
8759 %}
8761 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
8762 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
8763 ins_cost(150);
8764 opcode(0x102);
8765 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
8766 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8767 ins_pipe(int_conditional_float_move);
8768 %}
8770 // ============================================================================
8771 // Safepoint Instruction
8772 instruct safePoint_poll(iRegP poll) %{
8773 match(SafePoint poll);
8774 effect(USE poll);
8776 size(4);
8777 #ifdef _LP64
8778 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
8779 #else
8780 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
8781 #endif
8782 ins_encode %{
8783 __ relocate(relocInfo::poll_type);
8784 __ ld_ptr($poll$$Register, 0, G0);
8785 %}
8786 ins_pipe(loadPollP);
8787 %}
8789 // ============================================================================
8790 // Call Instructions
8791 // Call Java Static Instruction
8792 instruct CallStaticJavaDirect( method meth ) %{
8793 match(CallStaticJava);
8794 effect(USE meth);
8796 size(8);
8797 ins_cost(CALL_COST);
8798 format %{ "CALL,static ; NOP ==> " %}
8799 ins_encode( Java_Static_Call( meth ), call_epilog );
8800 ins_pc_relative(1);
8801 ins_pipe(simple_call);
8802 %}
8804 // Call Java Dynamic Instruction
8805 instruct CallDynamicJavaDirect( method meth ) %{
8806 match(CallDynamicJava);
8807 effect(USE meth);
8809 ins_cost(CALL_COST);
8810 format %{ "SET (empty),R_G5\n\t"
8811 "CALL,dynamic ; NOP ==> " %}
8812 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
8813 ins_pc_relative(1);
8814 ins_pipe(call);
8815 %}
8817 // Call Runtime Instruction
8818 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
8819 match(CallRuntime);
8820 effect(USE meth, KILL l7);
8821 ins_cost(CALL_COST);
8822 format %{ "CALL,runtime" %}
8823 ins_encode( Java_To_Runtime( meth ),
8824 call_epilog, adjust_long_from_native_call );
8825 ins_pc_relative(1);
8826 ins_pipe(simple_call);
8827 %}
8829 // Call runtime without safepoint - same as CallRuntime
8830 instruct CallLeafDirect(method meth, l7RegP l7) %{
8831 match(CallLeaf);
8832 effect(USE meth, KILL l7);
8833 ins_cost(CALL_COST);
8834 format %{ "CALL,runtime leaf" %}
8835 ins_encode( Java_To_Runtime( meth ),
8836 call_epilog,
8837 adjust_long_from_native_call );
8838 ins_pc_relative(1);
8839 ins_pipe(simple_call);
8840 %}
8842 // Call runtime without safepoint - same as CallLeaf
8843 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
8844 match(CallLeafNoFP);
8845 effect(USE meth, KILL l7);
8846 ins_cost(CALL_COST);
8847 format %{ "CALL,runtime leaf nofp" %}
8848 ins_encode( Java_To_Runtime( meth ),
8849 call_epilog,
8850 adjust_long_from_native_call );
8851 ins_pc_relative(1);
8852 ins_pipe(simple_call);
8853 %}
8855 // Tail Call; Jump from runtime stub to Java code.
8856 // Also known as an 'interprocedural jump'.
8857 // Target of jump will eventually return to caller.
8858 // TailJump below removes the return address.
8859 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
8860 match(TailCall jump_target method_oop );
8862 ins_cost(CALL_COST);
8863 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
8864 ins_encode(form_jmpl(jump_target));
8865 ins_pipe(tail_call);
8866 %}
8869 // Return Instruction
8870 instruct Ret() %{
8871 match(Return);
8873 // The epilogue node did the ret already.
8874 size(0);
8875 format %{ "! return" %}
8876 ins_encode();
8877 ins_pipe(empty);
8878 %}
8881 // Tail Jump; remove the return address; jump to target.
8882 // TailCall above leaves the return address around.
8883 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
8884 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
8885 // "restore" before this instruction (in Epilogue), we need to materialize it
8886 // in %i0.
8887 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
8888 match( TailJump jump_target ex_oop );
8889 ins_cost(CALL_COST);
8890 format %{ "! discard R_O7\n\t"
8891 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
8892 ins_encode(form_jmpl_set_exception_pc(jump_target));
8893 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
8894 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
8895 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
8896 ins_pipe(tail_call);
8897 %}
8899 // Create exception oop: created by stack-crawling runtime code.
8900 // Created exception is now available to this handler, and is setup
8901 // just prior to jumping to this handler. No code emitted.
8902 instruct CreateException( o0RegP ex_oop )
8903 %{
8904 match(Set ex_oop (CreateEx));
8905 ins_cost(0);
8907 size(0);
8908 // use the following format syntax
8909 format %{ "! exception oop is in R_O0; no code emitted" %}
8910 ins_encode();
8911 ins_pipe(empty);
8912 %}
8915 // Rethrow exception:
8916 // The exception oop will come in the first argument position.
8917 // Then JUMP (not call) to the rethrow stub code.
8918 instruct RethrowException()
8919 %{
8920 match(Rethrow);
8921 ins_cost(CALL_COST);
8923 // use the following format syntax
8924 format %{ "Jmp rethrow_stub" %}
8925 ins_encode(enc_rethrow);
8926 ins_pipe(tail_call);
8927 %}
8930 // Die now
8931 instruct ShouldNotReachHere( )
8932 %{
8933 match(Halt);
8934 ins_cost(CALL_COST);
8936 size(4);
8937 // Use the following format syntax
8938 format %{ "ILLTRAP ; ShouldNotReachHere" %}
8939 ins_encode( form2_illtrap() );
8940 ins_pipe(tail_call);
8941 %}
8943 // ============================================================================
8944 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
8945 // array for an instance of the superklass. Set a hidden internal cache on a
8946 // hit (cache is checked with exposed code in gen_subtype_check()). Return
8947 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
8948 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
8949 match(Set index (PartialSubtypeCheck sub super));
8950 effect( KILL pcc, KILL o7 );
8951 ins_cost(DEFAULT_COST*10);
8952 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
8953 ins_encode( enc_PartialSubtypeCheck() );
8954 ins_pipe(partial_subtype_check_pipe);
8955 %}
8957 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
8958 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
8959 effect( KILL idx, KILL o7 );
8960 ins_cost(DEFAULT_COST*10);
8961 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
8962 ins_encode( enc_PartialSubtypeCheck() );
8963 ins_pipe(partial_subtype_check_pipe);
8964 %}
8967 // ============================================================================
8968 // inlined locking and unlocking
8970 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8971 match(Set pcc (FastLock object box));
8973 effect(KILL scratch, TEMP scratch2);
8974 ins_cost(100);
8976 size(4*112); // conservative overestimation ...
8977 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8978 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
8979 ins_pipe(long_memory_op);
8980 %}
8983 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8984 match(Set pcc (FastUnlock object box));
8985 effect(KILL scratch, TEMP scratch2);
8986 ins_cost(100);
8988 size(4*120); // conservative overestimation ...
8989 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8990 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
8991 ins_pipe(long_memory_op);
8992 %}
8994 // Count and Base registers are fixed because the allocator cannot
8995 // kill unknown registers. The encodings are generic.
8996 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
8997 match(Set dummy (ClearArray cnt base));
8998 effect(TEMP temp, KILL ccr);
8999 ins_cost(300);
9000 format %{ "MOV $cnt,$temp\n"
9001 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9002 " BRge loop\t\t! Clearing loop\n"
9003 " STX G0,[$base+$temp]\t! delay slot" %}
9004 ins_encode( enc_Clear_Array(cnt, base, temp) );
9005 ins_pipe(long_memory_op);
9006 %}
9008 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
9009 o7RegI tmp3, flagsReg ccr) %{
9010 match(Set result (StrComp str1 str2));
9011 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
9012 ins_cost(300);
9013 format %{ "String Compare $str1,$str2 -> $result" %}
9014 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
9015 ins_pipe(long_memory_op);
9016 %}
9019 //---------- Population Count Instructions -------------------------------------
9021 instruct popCountI(iRegI dst, iRegI src) %{
9022 predicate(UsePopCountInstruction);
9023 match(Set dst (PopCountI src));
9025 format %{ "POPC $src, $dst" %}
9026 ins_encode %{
9027 __ popc($src$$Register, $dst$$Register);
9028 %}
9029 ins_pipe(ialu_reg);
9030 %}
9032 // Note: Long.bitCount(long) returns an int.
9033 instruct popCountL(iRegI dst, iRegL src) %{
9034 predicate(UsePopCountInstruction);
9035 match(Set dst (PopCountL src));
9037 format %{ "POPC $src, $dst" %}
9038 ins_encode %{
9039 __ popc($src$$Register, $dst$$Register);
9040 %}
9041 ins_pipe(ialu_reg);
9042 %}
9045 // ============================================================================
9046 //------------Bytes reverse--------------------------------------------------
9048 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9049 match(Set dst (ReverseBytesI src));
9050 effect(DEF dst, USE src);
9052 // Op cost is artificially doubled to make sure that load or store
9053 // instructions are preferred over this one which requires a spill
9054 // onto a stack slot.
9055 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9056 size(8);
9057 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9058 opcode(Assembler::lduwa_op3);
9059 ins_encode( form3_mem_reg_little(src, dst) );
9060 ins_pipe( iload_mem );
9061 %}
9063 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9064 match(Set dst (ReverseBytesL src));
9065 effect(DEF dst, USE src);
9067 // Op cost is artificially doubled to make sure that load or store
9068 // instructions are preferred over this one which requires a spill
9069 // onto a stack slot.
9070 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9071 size(8);
9072 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9074 opcode(Assembler::ldxa_op3);
9075 ins_encode( form3_mem_reg_little(src, dst) );
9076 ins_pipe( iload_mem );
9077 %}
9079 // Load Integer reversed byte order
9080 instruct loadI_reversed(iRegI dst, memory src) %{
9081 match(Set dst (ReverseBytesI (LoadI src)));
9083 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9084 size(8);
9085 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9087 opcode(Assembler::lduwa_op3);
9088 ins_encode( form3_mem_reg_little( src, dst) );
9089 ins_pipe(iload_mem);
9090 %}
9092 // Load Long - aligned and reversed
9093 instruct loadL_reversed(iRegL dst, memory src) %{
9094 match(Set dst (ReverseBytesL (LoadL src)));
9096 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9097 size(8);
9098 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9100 opcode(Assembler::ldxa_op3);
9101 ins_encode( form3_mem_reg_little( src, dst ) );
9102 ins_pipe(iload_mem);
9103 %}
9105 // Store Integer reversed byte order
9106 instruct storeI_reversed(memory dst, iRegI src) %{
9107 match(Set dst (StoreI dst (ReverseBytesI src)));
9109 ins_cost(MEMORY_REF_COST);
9110 size(8);
9111 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9113 opcode(Assembler::stwa_op3);
9114 ins_encode( form3_mem_reg_little( dst, src) );
9115 ins_pipe(istore_mem_reg);
9116 %}
9118 // Store Long reversed byte order
9119 instruct storeL_reversed(memory dst, iRegL src) %{
9120 match(Set dst (StoreL dst (ReverseBytesL src)));
9122 ins_cost(MEMORY_REF_COST);
9123 size(8);
9124 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9126 opcode(Assembler::stxa_op3);
9127 ins_encode( form3_mem_reg_little( dst, src) );
9128 ins_pipe(istore_mem_reg);
9129 %}
9131 //----------PEEPHOLE RULES-----------------------------------------------------
9132 // These must follow all instruction definitions as they use the names
9133 // defined in the instructions definitions.
9134 //
9135 // peepmatch ( root_instr_name [preceding_instruction]* );
9136 //
9137 // peepconstraint %{
9138 // (instruction_number.operand_name relational_op instruction_number.operand_name
9139 // [, ...] );
9140 // // instruction numbers are zero-based using left to right order in peepmatch
9141 //
9142 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9143 // // provide an instruction_number.operand_name for each operand that appears
9144 // // in the replacement instruction's match rule
9145 //
9146 // ---------VM FLAGS---------------------------------------------------------
9147 //
9148 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9149 //
9150 // Each peephole rule is given an identifying number starting with zero and
9151 // increasing by one in the order seen by the parser. An individual peephole
9152 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9153 // on the command-line.
9154 //
9155 // ---------CURRENT LIMITATIONS----------------------------------------------
9156 //
9157 // Only match adjacent instructions in same basic block
9158 // Only equality constraints
9159 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9160 // Only one replacement instruction
9161 //
9162 // ---------EXAMPLE----------------------------------------------------------
9163 //
9164 // // pertinent parts of existing instructions in architecture description
9165 // instruct movI(eRegI dst, eRegI src) %{
9166 // match(Set dst (CopyI src));
9167 // %}
9168 //
9169 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9170 // match(Set dst (AddI dst src));
9171 // effect(KILL cr);
9172 // %}
9173 //
9174 // // Change (inc mov) to lea
9175 // peephole %{
9176 // // increment preceeded by register-register move
9177 // peepmatch ( incI_eReg movI );
9178 // // require that the destination register of the increment
9179 // // match the destination register of the move
9180 // peepconstraint ( 0.dst == 1.dst );
9181 // // construct a replacement instruction that sets
9182 // // the destination to ( move's source register + one )
9183 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9184 // %}
9185 //
9187 // // Change load of spilled value to only a spill
9188 // instruct storeI(memory mem, eRegI src) %{
9189 // match(Set mem (StoreI mem src));
9190 // %}
9191 //
9192 // instruct loadI(eRegI dst, memory mem) %{
9193 // match(Set dst (LoadI mem));
9194 // %}
9195 //
9196 // peephole %{
9197 // peepmatch ( loadI storeI );
9198 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9199 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9200 // %}
9202 //----------SMARTSPILL RULES---------------------------------------------------
9203 // These must follow all instruction definitions as they use the names
9204 // defined in the instructions definitions.
9205 //
9206 // SPARC will probably not have any of these rules due to RISC instruction set.
9208 //----------PIPELINE-----------------------------------------------------------
9209 // Rules which define the behavior of the target architectures pipeline.