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src/cpu/x86/vm/vm_version_x86.hpp@bb1da64b0492
src/cpu/x86/vm/vm_version_x86.hpp
Fri, 16 Aug 2019 16:50:17 +0200
- author
- eosterlund
- date
- Fri, 16 Aug 2019 16:50:17 +0200
- changeset 9834
- bb1da64b0492
- parent 8729
- 402618d5afc9
- child 8856
- ac27a9c85bea
- permissions
- -rw-r--r--
8229345: Memory leak due to vtable stubs not being shared on SPARC
Reviewed-by: mdoerr, dholmes, kvn
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
31 class VM_Version : public Abstract_VM_Version {
32 public:
33 // cpuid result register layouts. These are all unions of a uint32_t
34 // (in case anyone wants access to the register as a whole) and a bitfield.
36 union StdCpuid1Eax {
37 uint32_t value;
38 struct {
39 uint32_t stepping : 4,
40 model : 4,
41 family : 4,
42 proc_type : 2,
43 : 2,
44 ext_model : 4,
45 ext_family : 8,
46 : 4;
47 } bits;
48 };
50 union StdCpuid1Ebx { // example, unused
51 uint32_t value;
52 struct {
53 uint32_t brand_id : 8,
54 clflush_size : 8,
55 threads_per_cpu : 8,
56 apic_id : 8;
57 } bits;
58 };
60 union StdCpuid1Ecx {
61 uint32_t value;
62 struct {
63 uint32_t sse3 : 1,
64 clmul : 1,
65 : 1,
66 monitor : 1,
67 : 1,
68 vmx : 1,
69 : 1,
70 est : 1,
71 : 1,
72 ssse3 : 1,
73 cid : 1,
74 : 2,
75 cmpxchg16: 1,
76 : 4,
77 dca : 1,
78 sse4_1 : 1,
79 sse4_2 : 1,
80 : 2,
81 popcnt : 1,
82 : 1,
83 aes : 1,
84 : 1,
85 osxsave : 1,
86 avx : 1,
87 : 3;
88 } bits;
89 };
91 union StdCpuid1Edx {
92 uint32_t value;
93 struct {
94 uint32_t : 4,
95 tsc : 1,
96 : 3,
97 cmpxchg8 : 1,
98 : 6,
99 cmov : 1,
100 : 3,
101 clflush : 1,
102 : 3,
103 mmx : 1,
104 fxsr : 1,
105 sse : 1,
106 sse2 : 1,
107 : 1,
108 ht : 1,
109 : 3;
110 } bits;
111 };
113 union DcpCpuid4Eax {
114 uint32_t value;
115 struct {
116 uint32_t cache_type : 5,
117 : 21,
118 cores_per_cpu : 6;
119 } bits;
120 };
122 union DcpCpuid4Ebx {
123 uint32_t value;
124 struct {
125 uint32_t L1_line_size : 12,
126 partitions : 10,
127 associativity : 10;
128 } bits;
129 };
131 union TplCpuidBEbx {
132 uint32_t value;
133 struct {
134 uint32_t logical_cpus : 16,
135 : 16;
136 } bits;
137 };
139 union ExtCpuid1Ecx {
140 uint32_t value;
141 struct {
142 uint32_t LahfSahf : 1,
143 CmpLegacy : 1,
144 : 3,
145 lzcnt_intel : 1,
146 lzcnt : 1,
147 sse4a : 1,
148 misalignsse : 1,
149 prefetchw : 1,
150 : 22;
151 } bits;
152 };
154 union ExtCpuid1Edx {
155 uint32_t value;
156 struct {
157 uint32_t : 22,
158 mmx_amd : 1,
159 mmx : 1,
160 fxsr : 1,
161 : 4,
162 long_mode : 1,
163 tdnow2 : 1,
164 tdnow : 1;
165 } bits;
166 };
168 union ExtCpuid5Ex {
169 uint32_t value;
170 struct {
171 uint32_t L1_line_size : 8,
172 L1_tag_lines : 8,
173 L1_assoc : 8,
174 L1_size : 8;
175 } bits;
176 };
178 union ExtCpuid7Edx {
179 uint32_t value;
180 struct {
181 uint32_t : 8,
182 tsc_invariance : 1,
183 : 23;
184 } bits;
185 };
187 union ExtCpuid8Ecx {
188 uint32_t value;
189 struct {
190 uint32_t cores_per_cpu : 8,
191 : 24;
192 } bits;
193 };
195 union SefCpuid7Eax {
196 uint32_t value;
197 };
199 union SefCpuid7Ebx {
200 uint32_t value;
201 struct {
202 uint32_t fsgsbase : 1,
203 : 2,
204 bmi1 : 1,
205 : 1,
206 avx2 : 1,
207 : 2,
208 bmi2 : 1,
209 erms : 1,
210 : 1,
211 rtm : 1,
212 : 7,
213 adx : 1,
214 : 12;
215 } bits;
216 };
218 union XemXcr0Eax {
219 uint32_t value;
220 struct {
221 uint32_t x87 : 1,
222 sse : 1,
223 ymm : 1,
224 : 29;
225 } bits;
226 };
228 protected:
229 static int _cpu;
230 static int _model;
231 static int _stepping;
232 static int _cpuFeatures; // features returned by the "cpuid" instruction
233 // 0 if this instruction is not available
234 static const char* _features_str;
236 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
237 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
239 enum {
240 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
241 CPU_CMOV = (1 << 1),
242 CPU_FXSR = (1 << 2),
243 CPU_HT = (1 << 3),
244 CPU_MMX = (1 << 4),
245 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
246 // may not necessarily support other 3dnow instructions
247 CPU_SSE = (1 << 6),
248 CPU_SSE2 = (1 << 7),
249 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
250 CPU_SSSE3 = (1 << 9),
251 CPU_SSE4A = (1 << 10),
252 CPU_SSE4_1 = (1 << 11),
253 CPU_SSE4_2 = (1 << 12),
254 CPU_POPCNT = (1 << 13),
255 CPU_LZCNT = (1 << 14),
256 CPU_TSC = (1 << 15),
257 CPU_TSCINV = (1 << 16),
258 CPU_AVX = (1 << 17),
259 CPU_AVX2 = (1 << 18),
260 CPU_AES = (1 << 19),
261 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
262 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
263 CPU_BMI1 = (1 << 22),
264 CPU_BMI2 = (1 << 23),
265 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
266 CPU_ADX = (1 << 25)
267 } cpuFeatureFlags;
269 enum {
270 // AMD
271 CPU_FAMILY_AMD_11H = 0x11,
272 // Intel
273 CPU_FAMILY_INTEL_CORE = 6,
274 CPU_MODEL_NEHALEM = 0x1e,
275 CPU_MODEL_NEHALEM_EP = 0x1a,
276 CPU_MODEL_NEHALEM_EX = 0x2e,
277 CPU_MODEL_WESTMERE = 0x25,
278 CPU_MODEL_WESTMERE_EP = 0x2c,
279 CPU_MODEL_WESTMERE_EX = 0x2f,
280 CPU_MODEL_SANDYBRIDGE = 0x2a,
281 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
282 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
283 CPU_MODEL_HASWELL_E3 = 0x3c,
284 CPU_MODEL_HASWELL_E7 = 0x3f,
285 CPU_MODEL_BROADWELL = 0x3d
286 } cpuExtendedFamily;
288 // cpuid information block. All info derived from executing cpuid with
289 // various function numbers is stored here. Intel and AMD info is
290 // merged in this block: accessor methods disentangle it.
291 //
292 // The info block is laid out in subblocks of 4 dwords corresponding to
293 // eax, ebx, ecx and edx, whether or not they contain anything useful.
294 struct CpuidInfo {
295 // cpuid function 0
296 uint32_t std_max_function;
297 uint32_t std_vendor_name_0;
298 uint32_t std_vendor_name_1;
299 uint32_t std_vendor_name_2;
301 // cpuid function 1
302 StdCpuid1Eax std_cpuid1_eax;
303 StdCpuid1Ebx std_cpuid1_ebx;
304 StdCpuid1Ecx std_cpuid1_ecx;
305 StdCpuid1Edx std_cpuid1_edx;
307 // cpuid function 4 (deterministic cache parameters)
308 DcpCpuid4Eax dcp_cpuid4_eax;
309 DcpCpuid4Ebx dcp_cpuid4_ebx;
310 uint32_t dcp_cpuid4_ecx; // unused currently
311 uint32_t dcp_cpuid4_edx; // unused currently
313 // cpuid function 7 (structured extended features)
314 SefCpuid7Eax sef_cpuid7_eax;
315 SefCpuid7Ebx sef_cpuid7_ebx;
316 uint32_t sef_cpuid7_ecx; // unused currently
317 uint32_t sef_cpuid7_edx; // unused currently
319 // cpuid function 0xB (processor topology)
320 // ecx = 0
321 uint32_t tpl_cpuidB0_eax;
322 TplCpuidBEbx tpl_cpuidB0_ebx;
323 uint32_t tpl_cpuidB0_ecx; // unused currently
324 uint32_t tpl_cpuidB0_edx; // unused currently
326 // ecx = 1
327 uint32_t tpl_cpuidB1_eax;
328 TplCpuidBEbx tpl_cpuidB1_ebx;
329 uint32_t tpl_cpuidB1_ecx; // unused currently
330 uint32_t tpl_cpuidB1_edx; // unused currently
332 // ecx = 2
333 uint32_t tpl_cpuidB2_eax;
334 TplCpuidBEbx tpl_cpuidB2_ebx;
335 uint32_t tpl_cpuidB2_ecx; // unused currently
336 uint32_t tpl_cpuidB2_edx; // unused currently
338 // cpuid function 0x80000000 // example, unused
339 uint32_t ext_max_function;
340 uint32_t ext_vendor_name_0;
341 uint32_t ext_vendor_name_1;
342 uint32_t ext_vendor_name_2;
344 // cpuid function 0x80000001
345 uint32_t ext_cpuid1_eax; // reserved
346 uint32_t ext_cpuid1_ebx; // reserved
347 ExtCpuid1Ecx ext_cpuid1_ecx;
348 ExtCpuid1Edx ext_cpuid1_edx;
350 // cpuid functions 0x80000002 thru 0x80000004: example, unused
351 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
352 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
353 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
355 // cpuid function 0x80000005 // AMD L1, Intel reserved
356 uint32_t ext_cpuid5_eax; // unused currently
357 uint32_t ext_cpuid5_ebx; // reserved
358 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
359 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
361 // cpuid function 0x80000007
362 uint32_t ext_cpuid7_eax; // reserved
363 uint32_t ext_cpuid7_ebx; // reserved
364 uint32_t ext_cpuid7_ecx; // reserved
365 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
367 // cpuid function 0x80000008
368 uint32_t ext_cpuid8_eax; // unused currently
369 uint32_t ext_cpuid8_ebx; // reserved
370 ExtCpuid8Ecx ext_cpuid8_ecx;
371 uint32_t ext_cpuid8_edx; // reserved
373 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
374 XemXcr0Eax xem_xcr0_eax;
375 uint32_t xem_xcr0_edx; // reserved
377 // Space to save ymm registers after signal handle
378 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
379 };
381 // The actual cpuid info block
382 static CpuidInfo _cpuid_info;
384 // Extractors and predicates
385 static uint32_t extended_cpu_family() {
386 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
387 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
388 return result;
389 }
391 static uint32_t extended_cpu_model() {
392 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
393 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
394 return result;
395 }
397 static uint32_t cpu_stepping() {
398 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
399 return result;
400 }
402 static uint logical_processor_count() {
403 uint result = threads_per_core();
404 return result;
405 }
407 static uint32_t feature_flags() {
408 uint32_t result = 0;
409 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
410 result |= CPU_CX8;
411 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
412 result |= CPU_CMOV;
413 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
414 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
415 result |= CPU_FXSR;
416 // HT flag is set for multi-core processors also.
417 if (threads_per_core() > 1)
418 result |= CPU_HT;
419 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
420 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
421 result |= CPU_MMX;
422 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
423 result |= CPU_SSE;
424 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
425 result |= CPU_SSE2;
426 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
427 result |= CPU_SSE3;
428 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
429 result |= CPU_SSSE3;
430 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
431 result |= CPU_SSE4_1;
432 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
433 result |= CPU_SSE4_2;
434 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
435 result |= CPU_POPCNT;
436 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
437 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
438 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
439 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
440 result |= CPU_AVX;
441 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
442 result |= CPU_AVX2;
443 }
444 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
445 result |= CPU_BMI1;
446 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
447 result |= CPU_TSC;
448 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
449 result |= CPU_TSCINV;
450 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
451 result |= CPU_AES;
452 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
453 result |= CPU_ERMS;
454 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
455 result |= CPU_CLMUL;
456 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
457 result |= CPU_RTM;
459 // AMD features.
460 if (is_amd()) {
461 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
462 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
463 result |= CPU_3DNOW_PREFETCH;
464 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
465 result |= CPU_LZCNT;
466 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
467 result |= CPU_SSE4A;
468 }
469 // Intel features.
470 if(is_intel()) {
471 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
472 result |= CPU_ADX;
473 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
474 result |= CPU_BMI2;
475 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
476 result |= CPU_LZCNT;
477 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
478 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
479 result |= CPU_3DNOW_PREFETCH;
480 }
481 }
483 return result;
484 }
486 static bool os_supports_avx_vectors() {
487 if (!supports_avx()) {
488 return false;
489 }
490 // Verify that OS save/restore all bits of AVX registers
491 // during signal processing.
492 int nreg = 2 LP64_ONLY(+2);
493 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
494 if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
495 return false;
496 }
497 }
498 return true;
499 }
501 static void get_processor_features();
503 public:
504 // Offsets for cpuid asm stub
505 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
506 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
507 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
508 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
509 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
510 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
511 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
512 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
513 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
514 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
515 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
516 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
517 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
519 // The value used to check ymm register after signal handle
520 static int ymm_test_value() { return 0xCAFEBABE; }
522 static void get_cpu_info_wrapper();
523 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
524 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
525 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
526 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
528 static void clean_cpuFeatures() { _cpuFeatures = 0; }
529 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); }
532 // Initialization
533 static void initialize();
535 // Override Abstract_VM_Version implementation
536 static bool use_biased_locking();
538 // Asserts
539 static void assert_is_initialized() {
540 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
541 }
543 //
544 // Processor family:
545 // 3 - 386
546 // 4 - 486
547 // 5 - Pentium
548 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
549 // Pentium M, Core Solo, Core Duo, Core2 Duo
550 // family 6 model: 9, 13, 14, 15
551 // 0x0f - Pentium 4, Opteron
552 //
553 // Note: The cpu family should be used to select between
554 // instruction sequences which are valid on all Intel
555 // processors. Use the feature test functions below to
556 // determine whether a particular instruction is supported.
557 //
558 static int cpu_family() { return _cpu;}
559 static bool is_P6() { return cpu_family() >= 6; }
560 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
561 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
563 static bool supports_processor_topology() {
564 return (_cpuid_info.std_max_function >= 0xB) &&
565 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
566 // Some cpus have max cpuid >= 0xB but do not support processor topology.
567 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
568 }
570 static uint cores_per_cpu() {
571 uint result = 1;
572 if (is_intel()) {
573 bool supports_topology = supports_processor_topology();
574 if (supports_topology) {
575 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
576 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
577 }
578 if (!supports_topology || result == 0) {
579 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
580 }
581 } else if (is_amd()) {
582 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
583 }
584 return result;
585 }
587 static uint threads_per_core() {
588 uint result = 1;
589 if (is_intel() && supports_processor_topology()) {
590 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
591 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
592 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
593 cores_per_cpu();
594 }
595 return (result == 0 ? 1 : result);
596 }
598 static intx L1_line_size() {
599 intx result = 0;
600 if (is_intel()) {
601 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
602 } else if (is_amd()) {
603 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
604 }
605 if (result < 32) // not defined ?
606 result = 32; // 32 bytes by default on x86 and other x64
607 return result;
608 }
610 static intx prefetch_data_size() {
611 return L1_line_size();
612 }
614 //
615 // Feature identification
616 //
617 static bool supports_cpuid() { return _cpuFeatures != 0; }
618 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
619 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
620 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
621 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
622 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
623 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
624 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
625 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
626 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
627 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
628 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
629 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
630 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; }
631 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
632 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
633 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; }
634 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; }
635 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; }
636 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; }
637 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
638 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
639 static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; }
640 // Intel features
641 static bool is_intel_family_core() { return is_intel() &&
642 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
644 static bool is_intel_tsc_synched_at_init() {
645 if (is_intel_family_core()) {
646 uint32_t ext_model = extended_cpu_model();
647 if (ext_model == CPU_MODEL_NEHALEM_EP ||
648 ext_model == CPU_MODEL_WESTMERE_EP ||
649 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
650 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
651 // <= 2-socket invariant tsc support. EX versions are usually used
652 // in > 2-socket systems and likely don't synchronize tscs at
653 // initialization.
654 // Code that uses tsc values must be prepared for them to arbitrarily
655 // jump forward or backward.
656 return true;
657 }
658 }
659 return false;
660 }
662 // AMD features
663 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
664 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
665 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
666 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
668 static bool is_amd_Barcelona() { return is_amd() &&
669 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
671 // Intel and AMD newer cores support fast timestamps well
672 static bool supports_tscinv_bit() {
673 return (_cpuFeatures & CPU_TSCINV) != 0;
674 }
675 static bool supports_tscinv() {
676 return supports_tscinv_bit() &&
677 ( (is_amd() && !is_amd_Barcelona()) ||
678 is_intel_tsc_synched_at_init() );
679 }
681 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
682 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
683 supports_sse3() && _model != 0x1C; }
685 static bool supports_compare_and_exchange() { return true; }
687 static const char* cpu_features() { return _features_str; }
689 static intx allocate_prefetch_distance() {
690 // This method should be called before allocate_prefetch_style().
691 //
692 // Hardware prefetching (distance/size in bytes):
693 // Pentium 3 - 64 / 32
694 // Pentium 4 - 256 / 128
695 // Athlon - 64 / 32 ????
696 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
697 // Core - 128 / 64
698 //
699 // Software prefetching (distance in bytes / instruction with best score):
700 // Pentium 3 - 128 / prefetchnta
701 // Pentium 4 - 512 / prefetchnta
702 // Athlon - 128 / prefetchnta
703 // Opteron - 256 / prefetchnta
704 // Core - 256 / prefetchnta
705 // It will be used only when AllocatePrefetchStyle > 0
707 intx count = AllocatePrefetchDistance;
708 if (count < 0) { // default ?
709 if (is_amd()) { // AMD
710 if (supports_sse2())
711 count = 256; // Opteron
712 else
713 count = 128; // Athlon
714 } else { // Intel
715 if (supports_sse2())
716 if (cpu_family() == 6) {
717 count = 256; // Pentium M, Core, Core2
718 } else {
719 count = 512; // Pentium 4
720 }
721 else
722 count = 128; // Pentium 3 (and all other old CPUs)
723 }
724 }
725 return count;
726 }
727 static intx allocate_prefetch_style() {
728 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
729 // Return 0 if AllocatePrefetchDistance was not defined.
730 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
731 }
733 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
734 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
735 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
736 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
738 // gc copy/scan is disabled if prefetchw isn't supported, because
739 // Prefetch::write emits an inlined prefetchw on Linux.
740 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
741 // The used prefetcht0 instruction works for both amd64 and em64t.
742 static intx prefetch_copy_interval_in_bytes() {
743 intx interval = PrefetchCopyIntervalInBytes;
744 return interval >= 0 ? interval : 576;
745 }
746 static intx prefetch_scan_interval_in_bytes() {
747 intx interval = PrefetchScanIntervalInBytes;
748 return interval >= 0 ? interval : 576;
749 }
750 static intx prefetch_fields_ahead() {
751 intx count = PrefetchFieldsAhead;
752 return count >= 0 ? count : 1;
753 }
754 };
756 #endif // CPU_X86_VM_VM_VERSION_X86_HPP
