Fri, 26 Aug 2011 08:52:22 -0700
7059037: Use BIS for zeroing on T4
Summary: Use BIS for zeroing new allocated big (2Kb and more) objects and arrays.
Reviewed-by: never, twisti, ysr
1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 extern bool use_block_zeroing(Node* count);
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
471 %}
473 source %{
474 #define __ _masm.
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
532 // ****************************************************************************
534 // REQUIRED FUNCTIONALITY
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedOops) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_oop_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if( Assembler::is_simm13(v_off) ) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 int bit_width = width * 8;
682 jlong elt_val = con;
683 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
684 jlong val = elt_val;
685 for (int i = 0; i < count - 1; i++) {
686 val <<= bit_width;
687 val |= elt_val;
688 }
689 jdouble dval = *((jdouble*) &val); // coerce to double type
690 return dval;
691 }
693 // Standard Sparc opcode form2 field breakdown
694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
695 f0 &= (1<<19)-1; // Mask displacement to 19 bits
696 int op = (f30 << 30) |
697 (f29 << 29) |
698 (f25 << 25) |
699 (f22 << 22) |
700 (f20 << 20) |
701 (f19 << 19) |
702 (f0 << 0);
703 cbuf.insts()->emit_int32(op);
704 }
706 // Standard Sparc opcode form2 field breakdown
707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
708 f0 >>= 10; // Drop 10 bits
709 f0 &= (1<<22)-1; // Mask displacement to 22 bits
710 int op = (f30 << 30) |
711 (f25 << 25) |
712 (f22 << 22) |
713 (f0 << 0);
714 cbuf.insts()->emit_int32(op);
715 }
717 // Standard Sparc opcode form3 field breakdown
718 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
719 int op = (f30 << 30) |
720 (f25 << 25) |
721 (f19 << 19) |
722 (f14 << 14) |
723 (f5 << 5) |
724 (f0 << 0);
725 cbuf.insts()->emit_int32(op);
726 }
728 // Standard Sparc opcode form3 field breakdown
729 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
730 simm13 &= (1<<13)-1; // Mask to 13 bits
731 int op = (f30 << 30) |
732 (f25 << 25) |
733 (f19 << 19) |
734 (f14 << 14) |
735 (1 << 13) | // bit to indicate immediate-mode
736 (simm13<<0);
737 cbuf.insts()->emit_int32(op);
738 }
740 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
741 simm10 &= (1<<10)-1; // Mask to 10 bits
742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
743 }
745 #ifdef ASSERT
746 // Helper function for VerifyOops in emit_form3_mem_reg
747 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
748 warning("VerifyOops encountered unexpected instruction:");
749 n->dump(2);
750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
751 }
752 #endif
755 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
756 int src1_enc, int disp32, int src2_enc, int dst_enc) {
758 #ifdef ASSERT
759 // The following code implements the +VerifyOops feature.
760 // It verifies oop values which are loaded into or stored out of
761 // the current method activation. +VerifyOops complements techniques
762 // like ScavengeALot, because it eagerly inspects oops in transit,
763 // as they enter or leave the stack, as opposed to ScavengeALot,
764 // which inspects oops "at rest", in the stack or heap, at safepoints.
765 // For this reason, +VerifyOops can sometimes detect bugs very close
766 // to their point of creation. It can also serve as a cross-check
767 // on the validity of oop maps, when used toegether with ScavengeALot.
769 // It would be good to verify oops at other points, especially
770 // when an oop is used as a base pointer for a load or store.
771 // This is presently difficult, because it is hard to know when
772 // a base address is biased or not. (If we had such information,
773 // it would be easy and useful to make a two-argument version of
774 // verify_oop which unbiases the base, and performs verification.)
776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
777 bool is_verified_oop_base = false;
778 bool is_verified_oop_load = false;
779 bool is_verified_oop_store = false;
780 int tmp_enc = -1;
781 if (VerifyOops && src1_enc != R_SP_enc) {
782 // classify the op, mainly for an assert check
783 int st_op = 0, ld_op = 0;
784 switch (primary) {
785 case Assembler::stb_op3: st_op = Op_StoreB; break;
786 case Assembler::sth_op3: st_op = Op_StoreC; break;
787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
788 case Assembler::stw_op3: st_op = Op_StoreI; break;
789 case Assembler::std_op3: st_op = Op_StoreL; break;
790 case Assembler::stf_op3: st_op = Op_StoreF; break;
791 case Assembler::stdf_op3: st_op = Op_StoreD; break;
793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
794 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
795 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
796 case Assembler::ldx_op3: // may become LoadP or stay LoadI
797 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
798 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
799 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
800 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
801 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
805 default: ShouldNotReachHere();
806 }
807 if (tertiary == REGP_OP) {
808 if (st_op == Op_StoreI) st_op = Op_StoreP;
809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
810 else ShouldNotReachHere();
811 if (st_op) {
812 // a store
813 // inputs are (0:control, 1:memory, 2:address, 3:value)
814 Node* n2 = n->in(3);
815 if (n2 != NULL) {
816 const Type* t = n2->bottom_type();
817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 } else {
820 // a load
821 const Type* t = n->bottom_type();
822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 }
826 if (ld_op) {
827 // a Load
828 // inputs are (0:control, 1:memory, 2:address)
829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
830 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
831 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
832 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
833 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
834 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
835 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
839 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
841 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
843 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
844 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
845 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
846 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
847 !(n->rule() == loadUB_rule)) {
848 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
849 }
850 } else if (st_op) {
851 // a Store
852 // inputs are (0:control, 1:memory, 2:address, 3:value)
853 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
854 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
855 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
856 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
857 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
858 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
859 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
860 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
912 uint index = src2_enc;
913 int disp = disp32;
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
916 disp += STACK_BIAS;
918 // We should have a compiler bailout here rather than a guarantee.
919 // Better yet would be some mechanism to handle variable-size matches correctly.
920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
922 if( disp == 0 ) {
923 // use reg-reg form
924 // bit 13 is already zero
925 instr |= index;
926 } else {
927 // use reg-imm form
928 instr |= 0x00002000; // set bit 13 to one
929 instr |= disp & 0x1FFF;
930 }
932 cbuf.insts()->emit_int32(instr);
934 #ifdef ASSERT
935 {
936 MacroAssembler _masm(&cbuf);
937 if (is_verified_oop_base) {
938 __ verify_oop(reg_to_register_object(src1_enc));
939 }
940 if (is_verified_oop_store) {
941 __ verify_oop(reg_to_register_object(dst_enc));
942 }
943 if (tmp_enc != -1) {
944 __ mov(O7, reg_to_register_object(tmp_enc));
945 }
946 if (is_verified_oop_load) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 }
950 #endif
951 }
953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
954 // The method which records debug information at every safepoint
955 // expects the call to be the first instruction in the snippet as
956 // it creates a PcDesc structure which tracks the offset of a call
957 // from the start of the codeBlob. This offset is computed as
958 // code_end() - code_begin() of the code which has been emitted
959 // so far.
960 // In this particular case we have skirted around the problem by
961 // putting the "mov" instruction in the delay slot but the problem
962 // may bite us again at some other point and a cleaner/generic
963 // solution using relocations would be needed.
964 MacroAssembler _masm(&cbuf);
965 __ set_inst_mark();
967 // We flush the current window just so that there is a valid stack copy
968 // the fact that the current window becomes active again instantly is
969 // not a problem there is nothing live in it.
971 #ifdef ASSERT
972 int startpos = __ offset();
973 #endif /* ASSERT */
975 __ call((address)entry_point, rtype);
977 if (preserve_g2) __ delayed()->mov(G2, L7);
978 else __ delayed()->nop();
980 if (preserve_g2) __ mov(L7, G2);
982 #ifdef ASSERT
983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
984 #ifdef _LP64
985 // Trash argument dump slots.
986 __ set(0xb0b8ac0db0b8ac0d, G1);
987 __ mov(G1, G5);
988 __ stx(G1, SP, STACK_BIAS + 0x80);
989 __ stx(G1, SP, STACK_BIAS + 0x88);
990 __ stx(G1, SP, STACK_BIAS + 0x90);
991 __ stx(G1, SP, STACK_BIAS + 0x98);
992 __ stx(G1, SP, STACK_BIAS + 0xA0);
993 __ stx(G1, SP, STACK_BIAS + 0xA8);
994 #else // _LP64
995 // this is also a native call, so smash the first 7 stack locations,
996 // and the various registers
998 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
999 // while [SP+0x44..0x58] are the argument dump slots.
1000 __ set((intptr_t)0xbaadf00d, G1);
1001 __ mov(G1, G5);
1002 __ sllx(G1, 32, G1);
1003 __ or3(G1, G5, G1);
1004 __ mov(G1, G5);
1005 __ stx(G1, SP, 0x40);
1006 __ stx(G1, SP, 0x48);
1007 __ stx(G1, SP, 0x50);
1008 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1009 #endif // _LP64
1010 }
1011 #endif /*ASSERT*/
1012 }
1014 //=============================================================================
1015 // REQUIRED FUNCTIONALITY for encoding
1016 void emit_lo(CodeBuffer &cbuf, int val) { }
1017 void emit_hi(CodeBuffer &cbuf, int val) { }
1020 //=============================================================================
1021 const bool Matcher::constant_table_absolute_addressing = false;
1022 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1024 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1025 Compile* C = ra_->C;
1026 Compile::ConstantTable& constant_table = C->constant_table();
1027 MacroAssembler _masm(&cbuf);
1029 Register r = as_Register(ra_->get_encode(this));
1030 CodeSection* cs = __ code()->consts();
1031 int consts_size = cs->align_at_start(cs->size());
1033 if (UseRDPCForConstantTableBase) {
1034 // For the following RDPC logic to work correctly the consts
1035 // section must be allocated right before the insts section. This
1036 // assert checks for that. The layout and the SECT_* constants
1037 // are defined in src/share/vm/asm/codeBuffer.hpp.
1038 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1039 int offset = __ offset();
1040 int disp;
1042 // If the displacement from the current PC to the constant table
1043 // base fits into simm13 we set the constant table base to the
1044 // current PC.
1045 if (__ is_simm13(-(consts_size + offset))) {
1046 constant_table.set_table_base_offset(-(consts_size + offset));
1047 disp = 0;
1048 } else {
1049 // If the offset of the top constant (last entry in the table)
1050 // fits into simm13 we set the constant table base to the actual
1051 // table base.
1052 if (__ is_simm13(constant_table.top_offset())) {
1053 constant_table.set_table_base_offset(0);
1054 disp = consts_size + offset;
1055 } else {
1056 // Otherwise we set the constant table base in the middle of the
1057 // constant table.
1058 int half_consts_size = consts_size / 2;
1059 assert(half_consts_size * 2 == consts_size, "sanity");
1060 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1061 disp = half_consts_size + offset;
1062 }
1063 }
1065 __ rdpc(r);
1067 if (disp != 0) {
1068 assert(r != O7, "need temporary");
1069 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1070 }
1071 }
1072 else {
1073 // Materialize the constant table base.
1074 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1075 address baseaddr = cs->start() + -(constant_table.table_base_offset());
1076 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1077 AddressLiteral base(baseaddr, rspec);
1078 __ set(base, r);
1079 }
1080 }
1082 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1083 if (UseRDPCForConstantTableBase) {
1084 // This is really the worst case but generally it's only 1 instruction.
1085 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1086 } else {
1087 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1088 }
1089 }
1091 #ifndef PRODUCT
1092 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1093 char reg[128];
1094 ra_->dump_register(this, reg);
1095 if (UseRDPCForConstantTableBase) {
1096 st->print("RDPC %s\t! constant table base", reg);
1097 } else {
1098 st->print("SET &constanttable,%s\t! constant table base", reg);
1099 }
1100 }
1101 #endif
1104 //=============================================================================
1106 #ifndef PRODUCT
1107 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1108 Compile* C = ra_->C;
1110 for (int i = 0; i < OptoPrologueNops; i++) {
1111 st->print_cr("NOP"); st->print("\t");
1112 }
1114 if( VerifyThread ) {
1115 st->print_cr("Verify_Thread"); st->print("\t");
1116 }
1118 size_t framesize = C->frame_slots() << LogBytesPerInt;
1120 // Calls to C2R adapters often do not accept exceptional returns.
1121 // We require that their callers must bang for them. But be careful, because
1122 // some VM calls (such as call site linkage) can use several kilobytes of
1123 // stack. But the stack safety zone should account for that.
1124 // See bugs 4446381, 4468289, 4497237.
1125 if (C->need_stack_bang(framesize)) {
1126 st->print_cr("! stack bang"); st->print("\t");
1127 }
1129 if (Assembler::is_simm13(-framesize)) {
1130 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1131 } else {
1132 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1133 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1134 st->print ("SAVE R_SP,R_G3,R_SP");
1135 }
1137 }
1138 #endif
1140 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1141 Compile* C = ra_->C;
1142 MacroAssembler _masm(&cbuf);
1144 for (int i = 0; i < OptoPrologueNops; i++) {
1145 __ nop();
1146 }
1148 __ verify_thread();
1150 size_t framesize = C->frame_slots() << LogBytesPerInt;
1151 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1152 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1154 // Calls to C2R adapters often do not accept exceptional returns.
1155 // We require that their callers must bang for them. But be careful, because
1156 // some VM calls (such as call site linkage) can use several kilobytes of
1157 // stack. But the stack safety zone should account for that.
1158 // See bugs 4446381, 4468289, 4497237.
1159 if (C->need_stack_bang(framesize)) {
1160 __ generate_stack_overflow_check(framesize);
1161 }
1163 if (Assembler::is_simm13(-framesize)) {
1164 __ save(SP, -framesize, SP);
1165 } else {
1166 __ sethi(-framesize & ~0x3ff, G3);
1167 __ add(G3, -framesize & 0x3ff, G3);
1168 __ save(SP, G3, SP);
1169 }
1170 C->set_frame_complete( __ offset() );
1171 }
1173 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1174 return MachNode::size(ra_);
1175 }
1177 int MachPrologNode::reloc() const {
1178 return 10; // a large enough number
1179 }
1181 //=============================================================================
1182 #ifndef PRODUCT
1183 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1186 if( do_polling() && ra_->C->is_method_compilation() ) {
1187 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1188 #ifdef _LP64
1189 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1190 #else
1191 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1192 #endif
1193 }
1195 if( do_polling() )
1196 st->print("RET\n\t");
1198 st->print("RESTORE");
1199 }
1200 #endif
1202 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1203 MacroAssembler _masm(&cbuf);
1204 Compile* C = ra_->C;
1206 __ verify_thread();
1208 // If this does safepoint polling, then do it here
1209 if( do_polling() && ra_->C->is_method_compilation() ) {
1210 AddressLiteral polling_page(os::get_polling_page());
1211 __ sethi(polling_page, L0);
1212 __ relocate(relocInfo::poll_return_type);
1213 __ ld_ptr( L0, 0, G0 );
1214 }
1216 // If this is a return, then stuff the restore in the delay slot
1217 if( do_polling() ) {
1218 __ ret();
1219 __ delayed()->restore();
1220 } else {
1221 __ restore();
1222 }
1223 }
1225 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1226 return MachNode::size(ra_);
1227 }
1229 int MachEpilogNode::reloc() const {
1230 return 16; // a large enough number
1231 }
1233 const Pipeline * MachEpilogNode::pipeline() const {
1234 return MachNode::pipeline_class();
1235 }
1237 int MachEpilogNode::safepoint_offset() const {
1238 assert( do_polling(), "no return for this epilog node");
1239 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1240 }
1242 //=============================================================================
1244 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1245 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1246 static enum RC rc_class( OptoReg::Name reg ) {
1247 if( !OptoReg::is_valid(reg) ) return rc_bad;
1248 if (OptoReg::is_stack(reg)) return rc_stack;
1249 VMReg r = OptoReg::as_VMReg(reg);
1250 if (r->is_Register()) return rc_int;
1251 assert(r->is_FloatRegister(), "must be");
1252 return rc_float;
1253 }
1255 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1256 if( cbuf ) {
1257 // Better yet would be some mechanism to handle variable-size matches correctly
1258 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1259 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1260 } else {
1261 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1262 }
1263 }
1264 #ifndef PRODUCT
1265 else if( !do_size ) {
1266 if( size != 0 ) st->print("\n\t");
1267 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1268 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1269 }
1270 #endif
1271 return size+4;
1272 }
1274 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1275 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1276 #ifndef PRODUCT
1277 else if( !do_size ) {
1278 if( size != 0 ) st->print("\n\t");
1279 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1280 }
1281 #endif
1282 return size+4;
1283 }
1285 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1286 PhaseRegAlloc *ra_,
1287 bool do_size,
1288 outputStream* st ) const {
1289 // Get registers to move
1290 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1291 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1292 OptoReg::Name dst_second = ra_->get_reg_second(this );
1293 OptoReg::Name dst_first = ra_->get_reg_first(this );
1295 enum RC src_second_rc = rc_class(src_second);
1296 enum RC src_first_rc = rc_class(src_first);
1297 enum RC dst_second_rc = rc_class(dst_second);
1298 enum RC dst_first_rc = rc_class(dst_first);
1300 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1302 // Generate spill code!
1303 int size = 0;
1305 if( src_first == dst_first && src_second == dst_second )
1306 return size; // Self copy, no move
1308 // --------------------------------------
1309 // Check for mem-mem move. Load into unused float registers and fall into
1310 // the float-store case.
1311 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1312 int offset = ra_->reg2offset(src_first);
1313 // Further check for aligned-adjacent pair, so we can use a double load
1314 if( (src_first&1)==0 && src_first+1 == src_second ) {
1315 src_second = OptoReg::Name(R_F31_num);
1316 src_second_rc = rc_float;
1317 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1318 } else {
1319 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1320 }
1321 src_first = OptoReg::Name(R_F30_num);
1322 src_first_rc = rc_float;
1323 }
1325 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1326 int offset = ra_->reg2offset(src_second);
1327 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1328 src_second = OptoReg::Name(R_F31_num);
1329 src_second_rc = rc_float;
1330 }
1332 // --------------------------------------
1333 // Check for float->int copy; requires a trip through memory
1334 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1335 int offset = frame::register_save_words*wordSize;
1336 if (cbuf) {
1337 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1338 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1339 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1340 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1341 }
1342 #ifndef PRODUCT
1343 else if (!do_size) {
1344 if (size != 0) st->print("\n\t");
1345 st->print( "SUB R_SP,16,R_SP\n");
1346 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1347 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1348 st->print("\tADD R_SP,16,R_SP\n");
1349 }
1350 #endif
1351 size += 16;
1352 }
1354 // Check for float->int copy on T4
1355 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1356 // Further check for aligned-adjacent pair, so we can use a double move
1357 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1358 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1359 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1360 }
1361 // Check for int->float copy on T4
1362 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1363 // Further check for aligned-adjacent pair, so we can use a double move
1364 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1365 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1367 }
1369 // --------------------------------------
1370 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1371 // In such cases, I have to do the big-endian swap. For aligned targets, the
1372 // hardware does the flop for me. Doubles are always aligned, so no problem
1373 // there. Misaligned sources only come from native-long-returns (handled
1374 // special below).
1375 #ifndef _LP64
1376 if( src_first_rc == rc_int && // source is already big-endian
1377 src_second_rc != rc_bad && // 64-bit move
1378 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1379 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1380 // Do the big-endian flop.
1381 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1382 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1383 }
1384 #endif
1386 // --------------------------------------
1387 // Check for integer reg-reg copy
1388 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1389 #ifndef _LP64
1390 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1391 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1392 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1393 // operand contains the least significant word of the 64-bit value and vice versa.
1394 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1395 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1396 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1397 if( cbuf ) {
1398 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1399 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1400 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1401 #ifndef PRODUCT
1402 } else if( !do_size ) {
1403 if( size != 0 ) st->print("\n\t");
1404 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1405 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1406 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1407 #endif
1408 }
1409 return size+12;
1410 }
1411 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1412 // returning a long value in I0/I1
1413 // a SpillCopy must be able to target a return instruction's reg_class
1414 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1415 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1416 // operand contains the least significant word of the 64-bit value and vice versa.
1417 OptoReg::Name tdest = dst_first;
1419 if (src_first == dst_first) {
1420 tdest = OptoReg::Name(R_O7_num);
1421 size += 4;
1422 }
1424 if( cbuf ) {
1425 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1426 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1427 // ShrL_reg_imm6
1428 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1429 // ShrR_reg_imm6 src, 0, dst
1430 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1431 if (tdest != dst_first) {
1432 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1433 }
1434 }
1435 #ifndef PRODUCT
1436 else if( !do_size ) {
1437 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1438 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1439 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1440 if (tdest != dst_first) {
1441 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1442 }
1443 }
1444 #endif // PRODUCT
1445 return size+8;
1446 }
1447 #endif // !_LP64
1448 // Else normal reg-reg copy
1449 assert( src_second != dst_first, "smashed second before evacuating it" );
1450 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1451 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1452 // This moves an aligned adjacent pair.
1453 // See if we are done.
1454 if( src_first+1 == src_second && dst_first+1 == dst_second )
1455 return size;
1456 }
1458 // Check for integer store
1459 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1460 int offset = ra_->reg2offset(dst_first);
1461 // Further check for aligned-adjacent pair, so we can use a double store
1462 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1463 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1464 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1465 }
1467 // Check for integer load
1468 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1469 int offset = ra_->reg2offset(src_first);
1470 // Further check for aligned-adjacent pair, so we can use a double load
1471 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1472 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1473 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1474 }
1476 // Check for float reg-reg copy
1477 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1478 // Further check for aligned-adjacent pair, so we can use a double move
1479 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1480 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1481 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1482 }
1484 // Check for float store
1485 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1486 int offset = ra_->reg2offset(dst_first);
1487 // Further check for aligned-adjacent pair, so we can use a double store
1488 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1489 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1490 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1491 }
1493 // Check for float load
1494 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1495 int offset = ra_->reg2offset(src_first);
1496 // Further check for aligned-adjacent pair, so we can use a double load
1497 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1498 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1499 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1500 }
1502 // --------------------------------------------------------------------
1503 // Check for hi bits still needing moving. Only happens for misaligned
1504 // arguments to native calls.
1505 if( src_second == dst_second )
1506 return size; // Self copy; no move
1507 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1509 #ifndef _LP64
1510 // In the LP64 build, all registers can be moved as aligned/adjacent
1511 // pairs, so there's never any need to move the high bits separately.
1512 // The 32-bit builds have to deal with the 32-bit ABI which can force
1513 // all sorts of silly alignment problems.
1515 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1516 // 32-bits of a 64-bit register, but are needed in low bits of another
1517 // register (else it's a hi-bits-to-hi-bits copy which should have
1518 // happened already as part of a 64-bit move)
1519 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1520 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1521 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1522 // Shift src_second down to dst_second's low bits.
1523 if( cbuf ) {
1524 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1525 #ifndef PRODUCT
1526 } else if( !do_size ) {
1527 if( size != 0 ) st->print("\n\t");
1528 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1529 #endif
1530 }
1531 return size+4;
1532 }
1534 // Check for high word integer store. Must down-shift the hi bits
1535 // into a temp register, then fall into the case of storing int bits.
1536 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1537 // Shift src_second down to dst_second's low bits.
1538 if( cbuf ) {
1539 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1540 #ifndef PRODUCT
1541 } else if( !do_size ) {
1542 if( size != 0 ) st->print("\n\t");
1543 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1544 #endif
1545 }
1546 size+=4;
1547 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1548 }
1550 // Check for high word integer load
1551 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1552 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1554 // Check for high word integer store
1555 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1556 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1558 // Check for high word float store
1559 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1560 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1562 #endif // !_LP64
1564 Unimplemented();
1565 }
1567 #ifndef PRODUCT
1568 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1569 implementation( NULL, ra_, false, st );
1570 }
1571 #endif
1573 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1574 implementation( &cbuf, ra_, false, NULL );
1575 }
1577 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1578 return implementation( NULL, ra_, true, NULL );
1579 }
1581 //=============================================================================
1582 #ifndef PRODUCT
1583 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1584 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1585 }
1586 #endif
1588 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1589 MacroAssembler _masm(&cbuf);
1590 for(int i = 0; i < _count; i += 1) {
1591 __ nop();
1592 }
1593 }
1595 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1596 return 4 * _count;
1597 }
1600 //=============================================================================
1601 #ifndef PRODUCT
1602 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1603 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1604 int reg = ra_->get_reg_first(this);
1605 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1606 }
1607 #endif
1609 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1610 MacroAssembler _masm(&cbuf);
1611 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1612 int reg = ra_->get_encode(this);
1614 if (Assembler::is_simm13(offset)) {
1615 __ add(SP, offset, reg_to_register_object(reg));
1616 } else {
1617 __ set(offset, O7);
1618 __ add(SP, O7, reg_to_register_object(reg));
1619 }
1620 }
1622 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1623 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1624 assert(ra_ == ra_->C->regalloc(), "sanity");
1625 return ra_->C->scratch_emit_size(this);
1626 }
1628 //=============================================================================
1630 // emit call stub, compiled java to interpretor
1631 void emit_java_to_interp(CodeBuffer &cbuf ) {
1633 // Stub is fixed up when the corresponding call is converted from calling
1634 // compiled code to calling interpreted code.
1635 // set (empty), G5
1636 // jmp -1
1638 address mark = cbuf.insts_mark(); // get mark within main instrs section
1640 MacroAssembler _masm(&cbuf);
1642 address base =
1643 __ start_a_stub(Compile::MAX_stubs_size);
1644 if (base == NULL) return; // CodeBuffer::expand failed
1646 // static stub relocation stores the instruction address of the call
1647 __ relocate(static_stub_Relocation::spec(mark));
1649 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1651 __ set_inst_mark();
1652 AddressLiteral addrlit(-1);
1653 __ JUMP(addrlit, G3, 0);
1655 __ delayed()->nop();
1657 // Update current stubs pointer and restore code_end.
1658 __ end_a_stub();
1659 }
1661 // size of call stub, compiled java to interpretor
1662 uint size_java_to_interp() {
1663 // This doesn't need to be accurate but it must be larger or equal to
1664 // the real size of the stub.
1665 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1666 NativeJump::instruction_size + // sethi; jmp; nop
1667 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1668 }
1669 // relocation entries for call stub, compiled java to interpretor
1670 uint reloc_java_to_interp() {
1671 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1672 }
1675 //=============================================================================
1676 #ifndef PRODUCT
1677 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1678 st->print_cr("\nUEP:");
1679 #ifdef _LP64
1680 if (UseCompressedOops) {
1681 assert(Universe::heap() != NULL, "java heap should be initialized");
1682 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1683 st->print_cr("\tSLL R_G5,3,R_G5");
1684 if (Universe::narrow_oop_base() != NULL)
1685 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1686 } else {
1687 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1688 }
1689 st->print_cr("\tCMP R_G5,R_G3" );
1690 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1691 #else // _LP64
1692 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1693 st->print_cr("\tCMP R_G5,R_G3" );
1694 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1695 #endif // _LP64
1696 }
1697 #endif
1699 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1700 MacroAssembler _masm(&cbuf);
1701 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1702 Register temp_reg = G3;
1703 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1705 // Load klass from receiver
1706 __ load_klass(O0, temp_reg);
1707 // Compare against expected klass
1708 __ cmp(temp_reg, G5_ic_reg);
1709 // Branch to miss code, checks xcc or icc depending
1710 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1711 }
1713 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1714 return MachNode::size(ra_);
1715 }
1718 //=============================================================================
1720 uint size_exception_handler() {
1721 if (TraceJumps) {
1722 return (400); // just a guess
1723 }
1724 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1725 }
1727 uint size_deopt_handler() {
1728 if (TraceJumps) {
1729 return (400); // just a guess
1730 }
1731 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1732 }
1734 // Emit exception handler code.
1735 int emit_exception_handler(CodeBuffer& cbuf) {
1736 Register temp_reg = G3;
1737 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1738 MacroAssembler _masm(&cbuf);
1740 address base =
1741 __ start_a_stub(size_exception_handler());
1742 if (base == NULL) return 0; // CodeBuffer::expand failed
1744 int offset = __ offset();
1746 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1747 __ delayed()->nop();
1749 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1751 __ end_a_stub();
1753 return offset;
1754 }
1756 int emit_deopt_handler(CodeBuffer& cbuf) {
1757 // Can't use any of the current frame's registers as we may have deopted
1758 // at a poll and everything (including G3) can be live.
1759 Register temp_reg = L0;
1760 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1761 MacroAssembler _masm(&cbuf);
1763 address base =
1764 __ start_a_stub(size_deopt_handler());
1765 if (base == NULL) return 0; // CodeBuffer::expand failed
1767 int offset = __ offset();
1768 __ save_frame(0);
1769 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1770 __ delayed()->restore();
1772 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1774 __ end_a_stub();
1775 return offset;
1777 }
1779 // Given a register encoding, produce a Integer Register object
1780 static Register reg_to_register_object(int register_encoding) {
1781 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1782 return as_Register(register_encoding);
1783 }
1785 // Given a register encoding, produce a single-precision Float Register object
1786 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1787 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1788 return as_SingleFloatRegister(register_encoding);
1789 }
1791 // Given a register encoding, produce a double-precision Float Register object
1792 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1793 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1794 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1795 return as_DoubleFloatRegister(register_encoding);
1796 }
1798 const bool Matcher::match_rule_supported(int opcode) {
1799 if (!has_match_rule(opcode))
1800 return false;
1802 switch (opcode) {
1803 case Op_CountLeadingZerosI:
1804 case Op_CountLeadingZerosL:
1805 case Op_CountTrailingZerosI:
1806 case Op_CountTrailingZerosL:
1807 if (!UsePopCountInstruction)
1808 return false;
1809 break;
1810 }
1812 return true; // Per default match rules are supported.
1813 }
1815 int Matcher::regnum_to_fpu_offset(int regnum) {
1816 return regnum - 32; // The FP registers are in the second chunk
1817 }
1819 #ifdef ASSERT
1820 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1821 #endif
1823 // Vector width in bytes
1824 const uint Matcher::vector_width_in_bytes(void) {
1825 return 8;
1826 }
1828 // Vector ideal reg
1829 const uint Matcher::vector_ideal_reg(void) {
1830 return Op_RegD;
1831 }
1833 // USII supports fxtof through the whole range of number, USIII doesn't
1834 const bool Matcher::convL2FSupported(void) {
1835 return VM_Version::has_fast_fxtof();
1836 }
1838 // Is this branch offset short enough that a short branch can be used?
1839 //
1840 // NOTE: If the platform does not provide any short branch variants, then
1841 // this method should return false for offset 0.
1842 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1843 // The passed offset is relative to address of the branch.
1844 // Don't need to adjust the offset.
1845 return UseCBCond && Assembler::is_simm(offset, 12);
1846 }
1848 const bool Matcher::isSimpleConstant64(jlong value) {
1849 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1850 // Depends on optimizations in MacroAssembler::setx.
1851 int hi = (int)(value >> 32);
1852 int lo = (int)(value & ~0);
1853 return (hi == 0) || (hi == -1) || (lo == 0);
1854 }
1856 // No scaling for the parameter the ClearArray node.
1857 const bool Matcher::init_array_count_is_in_bytes = true;
1859 // Threshold size for cleararray.
1860 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1862 // Should the Matcher clone shifts on addressing modes, expecting them to
1863 // be subsumed into complex addressing expressions or compute them into
1864 // registers? True for Intel but false for most RISCs
1865 const bool Matcher::clone_shift_expressions = false;
1867 // Do we need to mask the count passed to shift instructions or does
1868 // the cpu only look at the lower 5/6 bits anyway?
1869 const bool Matcher::need_masked_shift_count = false;
1871 bool Matcher::narrow_oop_use_complex_address() {
1872 NOT_LP64(ShouldNotCallThis());
1873 assert(UseCompressedOops, "only for compressed oops code");
1874 return false;
1875 }
1877 // Is it better to copy float constants, or load them directly from memory?
1878 // Intel can load a float constant from a direct address, requiring no
1879 // extra registers. Most RISCs will have to materialize an address into a
1880 // register first, so they would do better to copy the constant from stack.
1881 const bool Matcher::rematerialize_float_constants = false;
1883 // If CPU can load and store mis-aligned doubles directly then no fixup is
1884 // needed. Else we split the double into 2 integer pieces and move it
1885 // piece-by-piece. Only happens when passing doubles into C code as the
1886 // Java calling convention forces doubles to be aligned.
1887 #ifdef _LP64
1888 const bool Matcher::misaligned_doubles_ok = true;
1889 #else
1890 const bool Matcher::misaligned_doubles_ok = false;
1891 #endif
1893 // No-op on SPARC.
1894 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1895 }
1897 // Advertise here if the CPU requires explicit rounding operations
1898 // to implement the UseStrictFP mode.
1899 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1901 // Are floats conerted to double when stored to stack during deoptimization?
1902 // Sparc does not handle callee-save floats.
1903 bool Matcher::float_in_double() { return false; }
1905 // Do ints take an entire long register or just half?
1906 // Note that we if-def off of _LP64.
1907 // The relevant question is how the int is callee-saved. In _LP64
1908 // the whole long is written but de-opt'ing will have to extract
1909 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1910 #ifdef _LP64
1911 const bool Matcher::int_in_long = true;
1912 #else
1913 const bool Matcher::int_in_long = false;
1914 #endif
1916 // Return whether or not this register is ever used as an argument. This
1917 // function is used on startup to build the trampoline stubs in generateOptoStub.
1918 // Registers not mentioned will be killed by the VM call in the trampoline, and
1919 // arguments in those registers not be available to the callee.
1920 bool Matcher::can_be_java_arg( int reg ) {
1921 // Standard sparc 6 args in registers
1922 if( reg == R_I0_num ||
1923 reg == R_I1_num ||
1924 reg == R_I2_num ||
1925 reg == R_I3_num ||
1926 reg == R_I4_num ||
1927 reg == R_I5_num ) return true;
1928 #ifdef _LP64
1929 // 64-bit builds can pass 64-bit pointers and longs in
1930 // the high I registers
1931 if( reg == R_I0H_num ||
1932 reg == R_I1H_num ||
1933 reg == R_I2H_num ||
1934 reg == R_I3H_num ||
1935 reg == R_I4H_num ||
1936 reg == R_I5H_num ) return true;
1938 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1939 return true;
1940 }
1942 #else
1943 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1944 // Longs cannot be passed in O regs, because O regs become I regs
1945 // after a 'save' and I regs get their high bits chopped off on
1946 // interrupt.
1947 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1948 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1949 #endif
1950 // A few float args in registers
1951 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1953 return false;
1954 }
1956 bool Matcher::is_spillable_arg( int reg ) {
1957 return can_be_java_arg(reg);
1958 }
1960 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1961 // Use hardware SDIVX instruction when it is
1962 // faster than a code which use multiply.
1963 return VM_Version::has_fast_idiv();
1964 }
1966 // Register for DIVI projection of divmodI
1967 RegMask Matcher::divI_proj_mask() {
1968 ShouldNotReachHere();
1969 return RegMask();
1970 }
1972 // Register for MODI projection of divmodI
1973 RegMask Matcher::modI_proj_mask() {
1974 ShouldNotReachHere();
1975 return RegMask();
1976 }
1978 // Register for DIVL projection of divmodL
1979 RegMask Matcher::divL_proj_mask() {
1980 ShouldNotReachHere();
1981 return RegMask();
1982 }
1984 // Register for MODL projection of divmodL
1985 RegMask Matcher::modL_proj_mask() {
1986 ShouldNotReachHere();
1987 return RegMask();
1988 }
1990 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1991 return L7_REGP_mask;
1992 }
1994 %}
1997 // The intptr_t operand types, defined by textual substitution.
1998 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1999 #ifdef _LP64
2000 #define immX immL
2001 #define immX13 immL13
2002 #define immX13m7 immL13m7
2003 #define iRegX iRegL
2004 #define g1RegX g1RegL
2005 #else
2006 #define immX immI
2007 #define immX13 immI13
2008 #define immX13m7 immI13m7
2009 #define iRegX iRegI
2010 #define g1RegX g1RegI
2011 #endif
2013 //----------ENCODING BLOCK-----------------------------------------------------
2014 // This block specifies the encoding classes used by the compiler to output
2015 // byte streams. Encoding classes are parameterized macros used by
2016 // Machine Instruction Nodes in order to generate the bit encoding of the
2017 // instruction. Operands specify their base encoding interface with the
2018 // interface keyword. There are currently supported four interfaces,
2019 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2020 // operand to generate a function which returns its register number when
2021 // queried. CONST_INTER causes an operand to generate a function which
2022 // returns the value of the constant when queried. MEMORY_INTER causes an
2023 // operand to generate four functions which return the Base Register, the
2024 // Index Register, the Scale Value, and the Offset Value of the operand when
2025 // queried. COND_INTER causes an operand to generate six functions which
2026 // return the encoding code (ie - encoding bits for the instruction)
2027 // associated with each basic boolean condition for a conditional instruction.
2028 //
2029 // Instructions specify two basic values for encoding. Again, a function
2030 // is available to check if the constant displacement is an oop. They use the
2031 // ins_encode keyword to specify their encoding classes (which must be
2032 // a sequence of enc_class names, and their parameters, specified in
2033 // the encoding block), and they use the
2034 // opcode keyword to specify, in order, their primary, secondary, and
2035 // tertiary opcode. Only the opcode sections which a particular instruction
2036 // needs for encoding need to be specified.
2037 encode %{
2038 enc_class enc_untested %{
2039 #ifdef ASSERT
2040 MacroAssembler _masm(&cbuf);
2041 __ untested("encoding");
2042 #endif
2043 %}
2045 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2046 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2047 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2048 %}
2050 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2051 emit_form3_mem_reg(cbuf, this, $primary, -1,
2052 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2053 %}
2055 enc_class form3_mem_prefetch_read( memory mem ) %{
2056 emit_form3_mem_reg(cbuf, this, $primary, -1,
2057 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2058 %}
2060 enc_class form3_mem_prefetch_write( memory mem ) %{
2061 emit_form3_mem_reg(cbuf, this, $primary, -1,
2062 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2063 %}
2065 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2066 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2067 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2068 guarantee($mem$$index == R_G0_enc, "double index?");
2069 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2070 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2071 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2072 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2073 %}
2075 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2076 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2077 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2078 guarantee($mem$$index == R_G0_enc, "double index?");
2079 // Load long with 2 instructions
2080 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2081 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2082 %}
2084 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2085 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2086 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2087 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2088 %}
2090 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2091 // Encode a reg-reg copy. If it is useless, then empty encoding.
2092 if( $rs2$$reg != $rd$$reg )
2093 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2094 %}
2096 // Target lo half of long
2097 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2098 // Encode a reg-reg copy. If it is useless, then empty encoding.
2099 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2100 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2101 %}
2103 // Source lo half of long
2104 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2105 // Encode a reg-reg copy. If it is useless, then empty encoding.
2106 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2107 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2108 %}
2110 // Target hi half of long
2111 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2112 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2113 %}
2115 // Source lo half of long, and leave it sign extended.
2116 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2117 // Sign extend low half
2118 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2119 %}
2121 // Source hi half of long, and leave it sign extended.
2122 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2123 // Shift high half to low half
2124 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2125 %}
2127 // Source hi half of long
2128 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2129 // Encode a reg-reg copy. If it is useless, then empty encoding.
2130 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2131 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2132 %}
2134 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2135 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2136 %}
2138 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2139 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2140 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2141 %}
2143 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2144 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2145 // clear if nothing else is happening
2146 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2147 // blt,a,pn done
2148 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2149 // mov dst,-1 in delay slot
2150 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2151 %}
2153 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2154 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2155 %}
2157 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2158 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2159 %}
2161 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2162 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2163 %}
2165 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2166 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2167 %}
2169 enc_class move_return_pc_to_o1() %{
2170 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2171 %}
2173 #ifdef _LP64
2174 /* %%% merge with enc_to_bool */
2175 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2176 MacroAssembler _masm(&cbuf);
2178 Register src_reg = reg_to_register_object($src$$reg);
2179 Register dst_reg = reg_to_register_object($dst$$reg);
2180 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2181 %}
2182 #endif
2184 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2185 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2186 MacroAssembler _masm(&cbuf);
2188 Register p_reg = reg_to_register_object($p$$reg);
2189 Register q_reg = reg_to_register_object($q$$reg);
2190 Register y_reg = reg_to_register_object($y$$reg);
2191 Register tmp_reg = reg_to_register_object($tmp$$reg);
2193 __ subcc( p_reg, q_reg, p_reg );
2194 __ add ( p_reg, y_reg, tmp_reg );
2195 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2196 %}
2198 enc_class form_d2i_helper(regD src, regF dst) %{
2199 // fcmp %fcc0,$src,$src
2200 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2201 // branch %fcc0 not-nan, predict taken
2202 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2203 // fdtoi $src,$dst
2204 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2205 // fitos $dst,$dst (if nan)
2206 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2207 // clear $dst (if nan)
2208 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2209 // carry on here...
2210 %}
2212 enc_class form_d2l_helper(regD src, regD dst) %{
2213 // fcmp %fcc0,$src,$src check for NAN
2214 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2215 // branch %fcc0 not-nan, predict taken
2216 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2217 // fdtox $src,$dst convert in delay slot
2218 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2219 // fxtod $dst,$dst (if nan)
2220 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2221 // clear $dst (if nan)
2222 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2223 // carry on here...
2224 %}
2226 enc_class form_f2i_helper(regF src, regF dst) %{
2227 // fcmps %fcc0,$src,$src
2228 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2229 // branch %fcc0 not-nan, predict taken
2230 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2231 // fstoi $src,$dst
2232 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2233 // fitos $dst,$dst (if nan)
2234 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2235 // clear $dst (if nan)
2236 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2237 // carry on here...
2238 %}
2240 enc_class form_f2l_helper(regF src, regD dst) %{
2241 // fcmps %fcc0,$src,$src
2242 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2243 // branch %fcc0 not-nan, predict taken
2244 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2245 // fstox $src,$dst
2246 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2247 // fxtod $dst,$dst (if nan)
2248 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2249 // clear $dst (if nan)
2250 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2251 // carry on here...
2252 %}
2254 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2255 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2256 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2257 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2259 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2261 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2262 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2264 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2265 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2266 %}
2268 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2269 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2270 %}
2272 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2273 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2274 %}
2276 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2277 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2278 %}
2280 enc_class form3_convI2F(regF rs2, regF rd) %{
2281 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2282 %}
2284 // Encloding class for traceable jumps
2285 enc_class form_jmpl(g3RegP dest) %{
2286 emit_jmpl(cbuf, $dest$$reg);
2287 %}
2289 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2290 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2291 %}
2293 enc_class form2_nop() %{
2294 emit_nop(cbuf);
2295 %}
2297 enc_class form2_illtrap() %{
2298 emit_illtrap(cbuf);
2299 %}
2302 // Compare longs and convert into -1, 0, 1.
2303 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2304 // CMP $src1,$src2
2305 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2306 // blt,a,pn done
2307 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2308 // mov dst,-1 in delay slot
2309 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2310 // bgt,a,pn done
2311 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2312 // mov dst,1 in delay slot
2313 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2314 // CLR $dst
2315 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2316 %}
2318 enc_class enc_PartialSubtypeCheck() %{
2319 MacroAssembler _masm(&cbuf);
2320 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2321 __ delayed()->nop();
2322 %}
2324 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2325 MacroAssembler _masm(&cbuf);
2326 Label* L = $labl$$label;
2327 Assembler::Predict predict_taken =
2328 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2330 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2331 __ delayed()->nop();
2332 %}
2334 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2335 MacroAssembler _masm(&cbuf);
2336 Label* L = $labl$$label;
2337 Assembler::Predict predict_taken =
2338 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2340 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2341 __ delayed()->nop();
2342 %}
2344 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2345 int op = (Assembler::arith_op << 30) |
2346 ($dst$$reg << 25) |
2347 (Assembler::movcc_op3 << 19) |
2348 (1 << 18) | // cc2 bit for 'icc'
2349 ($cmp$$cmpcode << 14) |
2350 (0 << 13) | // select register move
2351 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2352 ($src$$reg << 0);
2353 cbuf.insts()->emit_int32(op);
2354 %}
2356 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2357 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2358 int op = (Assembler::arith_op << 30) |
2359 ($dst$$reg << 25) |
2360 (Assembler::movcc_op3 << 19) |
2361 (1 << 18) | // cc2 bit for 'icc'
2362 ($cmp$$cmpcode << 14) |
2363 (1 << 13) | // select immediate move
2364 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2365 (simm11 << 0);
2366 cbuf.insts()->emit_int32(op);
2367 %}
2369 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2370 int op = (Assembler::arith_op << 30) |
2371 ($dst$$reg << 25) |
2372 (Assembler::movcc_op3 << 19) |
2373 (0 << 18) | // cc2 bit for 'fccX'
2374 ($cmp$$cmpcode << 14) |
2375 (0 << 13) | // select register move
2376 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2377 ($src$$reg << 0);
2378 cbuf.insts()->emit_int32(op);
2379 %}
2381 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2382 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2383 int op = (Assembler::arith_op << 30) |
2384 ($dst$$reg << 25) |
2385 (Assembler::movcc_op3 << 19) |
2386 (0 << 18) | // cc2 bit for 'fccX'
2387 ($cmp$$cmpcode << 14) |
2388 (1 << 13) | // select immediate move
2389 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2390 (simm11 << 0);
2391 cbuf.insts()->emit_int32(op);
2392 %}
2394 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2395 int op = (Assembler::arith_op << 30) |
2396 ($dst$$reg << 25) |
2397 (Assembler::fpop2_op3 << 19) |
2398 (0 << 18) |
2399 ($cmp$$cmpcode << 14) |
2400 (1 << 13) | // select register move
2401 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2402 ($primary << 5) | // select single, double or quad
2403 ($src$$reg << 0);
2404 cbuf.insts()->emit_int32(op);
2405 %}
2407 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2408 int op = (Assembler::arith_op << 30) |
2409 ($dst$$reg << 25) |
2410 (Assembler::fpop2_op3 << 19) |
2411 (0 << 18) |
2412 ($cmp$$cmpcode << 14) |
2413 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2414 ($primary << 5) | // select single, double or quad
2415 ($src$$reg << 0);
2416 cbuf.insts()->emit_int32(op);
2417 %}
2419 // Used by the MIN/MAX encodings. Same as a CMOV, but
2420 // the condition comes from opcode-field instead of an argument.
2421 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2422 int op = (Assembler::arith_op << 30) |
2423 ($dst$$reg << 25) |
2424 (Assembler::movcc_op3 << 19) |
2425 (1 << 18) | // cc2 bit for 'icc'
2426 ($primary << 14) |
2427 (0 << 13) | // select register move
2428 (0 << 11) | // cc1, cc0 bits for 'icc'
2429 ($src$$reg << 0);
2430 cbuf.insts()->emit_int32(op);
2431 %}
2433 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2434 int op = (Assembler::arith_op << 30) |
2435 ($dst$$reg << 25) |
2436 (Assembler::movcc_op3 << 19) |
2437 (6 << 16) | // cc2 bit for 'xcc'
2438 ($primary << 14) |
2439 (0 << 13) | // select register move
2440 (0 << 11) | // cc1, cc0 bits for 'icc'
2441 ($src$$reg << 0);
2442 cbuf.insts()->emit_int32(op);
2443 %}
2445 enc_class Set13( immI13 src, iRegI rd ) %{
2446 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2447 %}
2449 enc_class SetHi22( immI src, iRegI rd ) %{
2450 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2451 %}
2453 enc_class Set32( immI src, iRegI rd ) %{
2454 MacroAssembler _masm(&cbuf);
2455 __ set($src$$constant, reg_to_register_object($rd$$reg));
2456 %}
2458 enc_class call_epilog %{
2459 if( VerifyStackAtCalls ) {
2460 MacroAssembler _masm(&cbuf);
2461 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2462 Register temp_reg = G3;
2463 __ add(SP, framesize, temp_reg);
2464 __ cmp(temp_reg, FP);
2465 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2466 }
2467 %}
2469 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2470 // to G1 so the register allocator will not have to deal with the misaligned register
2471 // pair.
2472 enc_class adjust_long_from_native_call %{
2473 #ifndef _LP64
2474 if (returns_long()) {
2475 // sllx O0,32,O0
2476 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2477 // srl O1,0,O1
2478 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2479 // or O0,O1,G1
2480 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2481 }
2482 #endif
2483 %}
2485 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2486 // CALL directly to the runtime
2487 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2488 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2489 /*preserve_g2=*/true);
2490 %}
2492 enc_class preserve_SP %{
2493 MacroAssembler _masm(&cbuf);
2494 __ mov(SP, L7_mh_SP_save);
2495 %}
2497 enc_class restore_SP %{
2498 MacroAssembler _masm(&cbuf);
2499 __ mov(L7_mh_SP_save, SP);
2500 %}
2502 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2503 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2504 // who we intended to call.
2505 if ( !_method ) {
2506 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2507 } else if (_optimized_virtual) {
2508 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2509 } else {
2510 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2511 }
2512 if( _method ) { // Emit stub for static call
2513 emit_java_to_interp(cbuf);
2514 }
2515 %}
2517 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2518 MacroAssembler _masm(&cbuf);
2519 __ set_inst_mark();
2520 int vtable_index = this->_vtable_index;
2521 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2522 if (vtable_index < 0) {
2523 // must be invalid_vtable_index, not nonvirtual_vtable_index
2524 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2525 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2526 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2527 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2528 // !!!!!
2529 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2530 // emit_call_dynamic_prologue( cbuf );
2531 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2533 address virtual_call_oop_addr = __ inst_mark();
2534 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2535 // who we intended to call.
2536 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2537 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2538 } else {
2539 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2540 // Just go thru the vtable
2541 // get receiver klass (receiver already checked for non-null)
2542 // If we end up going thru a c2i adapter interpreter expects method in G5
2543 int off = __ offset();
2544 __ load_klass(O0, G3_scratch);
2545 int klass_load_size;
2546 if (UseCompressedOops) {
2547 assert(Universe::heap() != NULL, "java heap should be initialized");
2548 if (Universe::narrow_oop_base() == NULL)
2549 klass_load_size = 2*BytesPerInstWord;
2550 else
2551 klass_load_size = 3*BytesPerInstWord;
2552 } else {
2553 klass_load_size = 1*BytesPerInstWord;
2554 }
2555 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2556 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2557 if( __ is_simm13(v_off) ) {
2558 __ ld_ptr(G3, v_off, G5_method);
2559 } else {
2560 // Generate 2 instructions
2561 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2562 __ or3(G5_method, v_off & 0x3ff, G5_method);
2563 // ld_ptr, set_hi, set
2564 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2565 "Unexpected instruction size(s)");
2566 __ ld_ptr(G3, G5_method, G5_method);
2567 }
2568 // NOTE: for vtable dispatches, the vtable entry will never be null.
2569 // However it may very well end up in handle_wrong_method if the
2570 // method is abstract for the particular class.
2571 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2572 // jump to target (either compiled code or c2iadapter)
2573 __ jmpl(G3_scratch, G0, O7);
2574 __ delayed()->nop();
2575 }
2576 %}
2578 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2579 MacroAssembler _masm(&cbuf);
2581 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2582 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2583 // we might be calling a C2I adapter which needs it.
2585 assert(temp_reg != G5_ic_reg, "conflicting registers");
2586 // Load nmethod
2587 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2589 // CALL to compiled java, indirect the contents of G3
2590 __ set_inst_mark();
2591 __ callr(temp_reg, G0);
2592 __ delayed()->nop();
2593 %}
2595 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2596 MacroAssembler _masm(&cbuf);
2597 Register Rdividend = reg_to_register_object($src1$$reg);
2598 Register Rdivisor = reg_to_register_object($src2$$reg);
2599 Register Rresult = reg_to_register_object($dst$$reg);
2601 __ sra(Rdivisor, 0, Rdivisor);
2602 __ sra(Rdividend, 0, Rdividend);
2603 __ sdivx(Rdividend, Rdivisor, Rresult);
2604 %}
2606 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2607 MacroAssembler _masm(&cbuf);
2609 Register Rdividend = reg_to_register_object($src1$$reg);
2610 int divisor = $imm$$constant;
2611 Register Rresult = reg_to_register_object($dst$$reg);
2613 __ sra(Rdividend, 0, Rdividend);
2614 __ sdivx(Rdividend, divisor, Rresult);
2615 %}
2617 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2618 MacroAssembler _masm(&cbuf);
2619 Register Rsrc1 = reg_to_register_object($src1$$reg);
2620 Register Rsrc2 = reg_to_register_object($src2$$reg);
2621 Register Rdst = reg_to_register_object($dst$$reg);
2623 __ sra( Rsrc1, 0, Rsrc1 );
2624 __ sra( Rsrc2, 0, Rsrc2 );
2625 __ mulx( Rsrc1, Rsrc2, Rdst );
2626 __ srlx( Rdst, 32, Rdst );
2627 %}
2629 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2630 MacroAssembler _masm(&cbuf);
2631 Register Rdividend = reg_to_register_object($src1$$reg);
2632 Register Rdivisor = reg_to_register_object($src2$$reg);
2633 Register Rresult = reg_to_register_object($dst$$reg);
2634 Register Rscratch = reg_to_register_object($scratch$$reg);
2636 assert(Rdividend != Rscratch, "");
2637 assert(Rdivisor != Rscratch, "");
2639 __ sra(Rdividend, 0, Rdividend);
2640 __ sra(Rdivisor, 0, Rdivisor);
2641 __ sdivx(Rdividend, Rdivisor, Rscratch);
2642 __ mulx(Rscratch, Rdivisor, Rscratch);
2643 __ sub(Rdividend, Rscratch, Rresult);
2644 %}
2646 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2647 MacroAssembler _masm(&cbuf);
2649 Register Rdividend = reg_to_register_object($src1$$reg);
2650 int divisor = $imm$$constant;
2651 Register Rresult = reg_to_register_object($dst$$reg);
2652 Register Rscratch = reg_to_register_object($scratch$$reg);
2654 assert(Rdividend != Rscratch, "");
2656 __ sra(Rdividend, 0, Rdividend);
2657 __ sdivx(Rdividend, divisor, Rscratch);
2658 __ mulx(Rscratch, divisor, Rscratch);
2659 __ sub(Rdividend, Rscratch, Rresult);
2660 %}
2662 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2663 MacroAssembler _masm(&cbuf);
2665 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2666 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2668 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2669 %}
2671 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2672 MacroAssembler _masm(&cbuf);
2674 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2675 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2677 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2678 %}
2680 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2681 MacroAssembler _masm(&cbuf);
2683 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2684 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2686 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2687 %}
2689 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2690 MacroAssembler _masm(&cbuf);
2692 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2693 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2695 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2696 %}
2698 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2699 MacroAssembler _masm(&cbuf);
2701 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2702 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2704 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2705 %}
2707 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2708 MacroAssembler _masm(&cbuf);
2710 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2711 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2713 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2714 %}
2716 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2717 MacroAssembler _masm(&cbuf);
2719 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2720 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2722 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2723 %}
2725 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2726 MacroAssembler _masm(&cbuf);
2728 Register Roop = reg_to_register_object($oop$$reg);
2729 Register Rbox = reg_to_register_object($box$$reg);
2730 Register Rscratch = reg_to_register_object($scratch$$reg);
2731 Register Rmark = reg_to_register_object($scratch2$$reg);
2733 assert(Roop != Rscratch, "");
2734 assert(Roop != Rmark, "");
2735 assert(Rbox != Rscratch, "");
2736 assert(Rbox != Rmark, "");
2738 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2739 %}
2741 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2742 MacroAssembler _masm(&cbuf);
2744 Register Roop = reg_to_register_object($oop$$reg);
2745 Register Rbox = reg_to_register_object($box$$reg);
2746 Register Rscratch = reg_to_register_object($scratch$$reg);
2747 Register Rmark = reg_to_register_object($scratch2$$reg);
2749 assert(Roop != Rscratch, "");
2750 assert(Roop != Rmark, "");
2751 assert(Rbox != Rscratch, "");
2752 assert(Rbox != Rmark, "");
2754 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2755 %}
2757 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2758 MacroAssembler _masm(&cbuf);
2759 Register Rmem = reg_to_register_object($mem$$reg);
2760 Register Rold = reg_to_register_object($old$$reg);
2761 Register Rnew = reg_to_register_object($new$$reg);
2763 // casx_under_lock picks 1 of 3 encodings:
2764 // For 32-bit pointers you get a 32-bit CAS
2765 // For 64-bit pointers you get a 64-bit CASX
2766 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2767 __ cmp( Rold, Rnew );
2768 %}
2770 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2771 Register Rmem = reg_to_register_object($mem$$reg);
2772 Register Rold = reg_to_register_object($old$$reg);
2773 Register Rnew = reg_to_register_object($new$$reg);
2775 MacroAssembler _masm(&cbuf);
2776 __ mov(Rnew, O7);
2777 __ casx(Rmem, Rold, O7);
2778 __ cmp( Rold, O7 );
2779 %}
2781 // raw int cas, used for compareAndSwap
2782 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2783 Register Rmem = reg_to_register_object($mem$$reg);
2784 Register Rold = reg_to_register_object($old$$reg);
2785 Register Rnew = reg_to_register_object($new$$reg);
2787 MacroAssembler _masm(&cbuf);
2788 __ mov(Rnew, O7);
2789 __ cas(Rmem, Rold, O7);
2790 __ cmp( Rold, O7 );
2791 %}
2793 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2794 Register Rres = reg_to_register_object($res$$reg);
2796 MacroAssembler _masm(&cbuf);
2797 __ mov(1, Rres);
2798 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2799 %}
2801 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2802 Register Rres = reg_to_register_object($res$$reg);
2804 MacroAssembler _masm(&cbuf);
2805 __ mov(1, Rres);
2806 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2807 %}
2809 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2810 MacroAssembler _masm(&cbuf);
2811 Register Rdst = reg_to_register_object($dst$$reg);
2812 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2813 : reg_to_DoubleFloatRegister_object($src1$$reg);
2814 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2815 : reg_to_DoubleFloatRegister_object($src2$$reg);
2817 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2818 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2819 %}
2822 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2823 Label Ldone, Lloop;
2824 MacroAssembler _masm(&cbuf);
2826 Register str1_reg = reg_to_register_object($str1$$reg);
2827 Register str2_reg = reg_to_register_object($str2$$reg);
2828 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2829 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2830 Register result_reg = reg_to_register_object($result$$reg);
2832 assert(result_reg != str1_reg &&
2833 result_reg != str2_reg &&
2834 result_reg != cnt1_reg &&
2835 result_reg != cnt2_reg ,
2836 "need different registers");
2838 // Compute the minimum of the string lengths(str1_reg) and the
2839 // difference of the string lengths (stack)
2841 // See if the lengths are different, and calculate min in str1_reg.
2842 // Stash diff in O7 in case we need it for a tie-breaker.
2843 Label Lskip;
2844 __ subcc(cnt1_reg, cnt2_reg, O7);
2845 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2846 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2847 // cnt2 is shorter, so use its count:
2848 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2849 __ bind(Lskip);
2851 // reallocate cnt1_reg, cnt2_reg, result_reg
2852 // Note: limit_reg holds the string length pre-scaled by 2
2853 Register limit_reg = cnt1_reg;
2854 Register chr2_reg = cnt2_reg;
2855 Register chr1_reg = result_reg;
2856 // str{12} are the base pointers
2858 // Is the minimum length zero?
2859 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2860 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2861 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2863 // Load first characters
2864 __ lduh(str1_reg, 0, chr1_reg);
2865 __ lduh(str2_reg, 0, chr2_reg);
2867 // Compare first characters
2868 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2869 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2870 assert(chr1_reg == result_reg, "result must be pre-placed");
2871 __ delayed()->nop();
2873 {
2874 // Check after comparing first character to see if strings are equivalent
2875 Label LSkip2;
2876 // Check if the strings start at same location
2877 __ cmp(str1_reg, str2_reg);
2878 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2879 __ delayed()->nop();
2881 // Check if the length difference is zero (in O7)
2882 __ cmp(G0, O7);
2883 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2884 __ delayed()->mov(G0, result_reg); // result is zero
2886 // Strings might not be equal
2887 __ bind(LSkip2);
2888 }
2890 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2891 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2892 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2894 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2895 __ add(str1_reg, limit_reg, str1_reg);
2896 __ add(str2_reg, limit_reg, str2_reg);
2897 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2899 // Compare the rest of the characters
2900 __ lduh(str1_reg, limit_reg, chr1_reg);
2901 __ bind(Lloop);
2902 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2903 __ lduh(str2_reg, limit_reg, chr2_reg);
2904 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2905 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2906 assert(chr1_reg == result_reg, "result must be pre-placed");
2907 __ delayed()->inccc(limit_reg, sizeof(jchar));
2908 // annul LDUH if branch is not taken to prevent access past end of string
2909 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2910 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2912 // If strings are equal up to min length, return the length difference.
2913 __ mov(O7, result_reg);
2915 // Otherwise, return the difference between the first mismatched chars.
2916 __ bind(Ldone);
2917 %}
2919 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2920 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2921 MacroAssembler _masm(&cbuf);
2923 Register str1_reg = reg_to_register_object($str1$$reg);
2924 Register str2_reg = reg_to_register_object($str2$$reg);
2925 Register cnt_reg = reg_to_register_object($cnt$$reg);
2926 Register tmp1_reg = O7;
2927 Register result_reg = reg_to_register_object($result$$reg);
2929 assert(result_reg != str1_reg &&
2930 result_reg != str2_reg &&
2931 result_reg != cnt_reg &&
2932 result_reg != tmp1_reg ,
2933 "need different registers");
2935 __ cmp(str1_reg, str2_reg); //same char[] ?
2936 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2937 __ delayed()->add(G0, 1, result_reg);
2939 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2940 __ delayed()->add(G0, 1, result_reg); // count == 0
2942 //rename registers
2943 Register limit_reg = cnt_reg;
2944 Register chr1_reg = result_reg;
2945 Register chr2_reg = tmp1_reg;
2947 //check for alignment and position the pointers to the ends
2948 __ or3(str1_reg, str2_reg, chr1_reg);
2949 __ andcc(chr1_reg, 0x3, chr1_reg);
2950 // notZero means at least one not 4-byte aligned.
2951 // We could optimize the case when both arrays are not aligned
2952 // but it is not frequent case and it requires additional checks.
2953 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2954 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2956 // Compare char[] arrays aligned to 4 bytes.
2957 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2958 chr1_reg, chr2_reg, Ldone);
2959 __ ba(Ldone);
2960 __ delayed()->add(G0, 1, result_reg);
2962 // char by char compare
2963 __ bind(Lchar);
2964 __ add(str1_reg, limit_reg, str1_reg);
2965 __ add(str2_reg, limit_reg, str2_reg);
2966 __ neg(limit_reg); //negate count
2968 __ lduh(str1_reg, limit_reg, chr1_reg);
2969 // Lchar_loop
2970 __ bind(Lchar_loop);
2971 __ lduh(str2_reg, limit_reg, chr2_reg);
2972 __ cmp(chr1_reg, chr2_reg);
2973 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2974 __ delayed()->mov(G0, result_reg); //not equal
2975 __ inccc(limit_reg, sizeof(jchar));
2976 // annul LDUH if branch is not taken to prevent access past end of string
2977 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2978 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2980 __ add(G0, 1, result_reg); //equal
2982 __ bind(Ldone);
2983 %}
2985 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2986 Label Lvector, Ldone, Lloop;
2987 MacroAssembler _masm(&cbuf);
2989 Register ary1_reg = reg_to_register_object($ary1$$reg);
2990 Register ary2_reg = reg_to_register_object($ary2$$reg);
2991 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2992 Register tmp2_reg = O7;
2993 Register result_reg = reg_to_register_object($result$$reg);
2995 int length_offset = arrayOopDesc::length_offset_in_bytes();
2996 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
2998 // return true if the same array
2999 __ cmp(ary1_reg, ary2_reg);
3000 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3001 __ delayed()->add(G0, 1, result_reg); // equal
3003 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3004 __ delayed()->mov(G0, result_reg); // not equal
3006 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3007 __ delayed()->mov(G0, result_reg); // not equal
3009 //load the lengths of arrays
3010 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3011 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3013 // return false if the two arrays are not equal length
3014 __ cmp(tmp1_reg, tmp2_reg);
3015 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3016 __ delayed()->mov(G0, result_reg); // not equal
3018 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3019 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3021 // load array addresses
3022 __ add(ary1_reg, base_offset, ary1_reg);
3023 __ add(ary2_reg, base_offset, ary2_reg);
3025 // renaming registers
3026 Register chr1_reg = result_reg; // for characters in ary1
3027 Register chr2_reg = tmp2_reg; // for characters in ary2
3028 Register limit_reg = tmp1_reg; // length
3030 // set byte count
3031 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3033 // Compare char[] arrays aligned to 4 bytes.
3034 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3035 chr1_reg, chr2_reg, Ldone);
3036 __ add(G0, 1, result_reg); // equals
3038 __ bind(Ldone);
3039 %}
3041 enc_class enc_rethrow() %{
3042 cbuf.set_insts_mark();
3043 Register temp_reg = G3;
3044 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3045 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3046 MacroAssembler _masm(&cbuf);
3047 #ifdef ASSERT
3048 __ save_frame(0);
3049 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3050 __ sethi(last_rethrow_addrlit, L1);
3051 Address addr(L1, last_rethrow_addrlit.low10());
3052 __ get_pc(L2);
3053 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3054 __ st_ptr(L2, addr);
3055 __ restore();
3056 #endif
3057 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3058 __ delayed()->nop();
3059 %}
3061 enc_class emit_mem_nop() %{
3062 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3063 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3064 %}
3066 enc_class emit_fadd_nop() %{
3067 // Generates the instruction FMOVS f31,f31
3068 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3069 %}
3071 enc_class emit_br_nop() %{
3072 // Generates the instruction BPN,PN .
3073 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3074 %}
3076 enc_class enc_membar_acquire %{
3077 MacroAssembler _masm(&cbuf);
3078 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3079 %}
3081 enc_class enc_membar_release %{
3082 MacroAssembler _masm(&cbuf);
3083 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3084 %}
3086 enc_class enc_membar_volatile %{
3087 MacroAssembler _masm(&cbuf);
3088 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3089 %}
3091 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3092 MacroAssembler _masm(&cbuf);
3093 Register src_reg = reg_to_register_object($src$$reg);
3094 Register dst_reg = reg_to_register_object($dst$$reg);
3095 __ sllx(src_reg, 56, dst_reg);
3096 __ srlx(dst_reg, 8, O7);
3097 __ or3 (dst_reg, O7, dst_reg);
3098 __ srlx(dst_reg, 16, O7);
3099 __ or3 (dst_reg, O7, dst_reg);
3100 __ srlx(dst_reg, 32, O7);
3101 __ or3 (dst_reg, O7, dst_reg);
3102 %}
3104 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3105 MacroAssembler _masm(&cbuf);
3106 Register src_reg = reg_to_register_object($src$$reg);
3107 Register dst_reg = reg_to_register_object($dst$$reg);
3108 __ sll(src_reg, 24, dst_reg);
3109 __ srl(dst_reg, 8, O7);
3110 __ or3(dst_reg, O7, dst_reg);
3111 __ srl(dst_reg, 16, O7);
3112 __ or3(dst_reg, O7, dst_reg);
3113 %}
3115 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3116 MacroAssembler _masm(&cbuf);
3117 Register src_reg = reg_to_register_object($src$$reg);
3118 Register dst_reg = reg_to_register_object($dst$$reg);
3119 __ sllx(src_reg, 48, dst_reg);
3120 __ srlx(dst_reg, 16, O7);
3121 __ or3 (dst_reg, O7, dst_reg);
3122 __ srlx(dst_reg, 32, O7);
3123 __ or3 (dst_reg, O7, dst_reg);
3124 %}
3126 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3127 MacroAssembler _masm(&cbuf);
3128 Register src_reg = reg_to_register_object($src$$reg);
3129 Register dst_reg = reg_to_register_object($dst$$reg);
3130 __ sllx(src_reg, 32, dst_reg);
3131 __ srlx(dst_reg, 32, O7);
3132 __ or3 (dst_reg, O7, dst_reg);
3133 %}
3135 %}
3137 //----------FRAME--------------------------------------------------------------
3138 // Definition of frame structure and management information.
3139 //
3140 // S T A C K L A Y O U T Allocators stack-slot number
3141 // | (to get allocators register number
3142 // G Owned by | | v add VMRegImpl::stack0)
3143 // r CALLER | |
3144 // o | +--------+ pad to even-align allocators stack-slot
3145 // w V | pad0 | numbers; owned by CALLER
3146 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3147 // h ^ | in | 5
3148 // | | args | 4 Holes in incoming args owned by SELF
3149 // | | | | 3
3150 // | | +--------+
3151 // V | | old out| Empty on Intel, window on Sparc
3152 // | old |preserve| Must be even aligned.
3153 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3154 // | | in | 3 area for Intel ret address
3155 // Owned by |preserve| Empty on Sparc.
3156 // SELF +--------+
3157 // | | pad2 | 2 pad to align old SP
3158 // | +--------+ 1
3159 // | | locks | 0
3160 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3161 // | | pad1 | 11 pad to align new SP
3162 // | +--------+
3163 // | | | 10
3164 // | | spills | 9 spills
3165 // V | | 8 (pad0 slot for callee)
3166 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3167 // ^ | out | 7
3168 // | | args | 6 Holes in outgoing args owned by CALLEE
3169 // Owned by +--------+
3170 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3171 // | new |preserve| Must be even-aligned.
3172 // | SP-+--------+----> Matcher::_new_SP, even aligned
3173 // | | |
3174 //
3175 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3176 // known from SELF's arguments and the Java calling convention.
3177 // Region 6-7 is determined per call site.
3178 // Note 2: If the calling convention leaves holes in the incoming argument
3179 // area, those holes are owned by SELF. Holes in the outgoing area
3180 // are owned by the CALLEE. Holes should not be nessecary in the
3181 // incoming area, as the Java calling convention is completely under
3182 // the control of the AD file. Doubles can be sorted and packed to
3183 // avoid holes. Holes in the outgoing arguments may be nessecary for
3184 // varargs C calling conventions.
3185 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3186 // even aligned with pad0 as needed.
3187 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3188 // region 6-11 is even aligned; it may be padded out more so that
3189 // the region from SP to FP meets the minimum stack alignment.
3191 frame %{
3192 // What direction does stack grow in (assumed to be same for native & Java)
3193 stack_direction(TOWARDS_LOW);
3195 // These two registers define part of the calling convention
3196 // between compiled code and the interpreter.
3197 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3198 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3200 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3201 cisc_spilling_operand_name(indOffset);
3203 // Number of stack slots consumed by a Monitor enter
3204 #ifdef _LP64
3205 sync_stack_slots(2);
3206 #else
3207 sync_stack_slots(1);
3208 #endif
3210 // Compiled code's Frame Pointer
3211 frame_pointer(R_SP);
3213 // Stack alignment requirement
3214 stack_alignment(StackAlignmentInBytes);
3215 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3216 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3218 // Number of stack slots between incoming argument block and the start of
3219 // a new frame. The PROLOG must add this many slots to the stack. The
3220 // EPILOG must remove this many slots.
3221 in_preserve_stack_slots(0);
3223 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3224 // for calls to C. Supports the var-args backing area for register parms.
3225 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3226 #ifdef _LP64
3227 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3228 varargs_C_out_slots_killed(12);
3229 #else
3230 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3231 varargs_C_out_slots_killed( 7);
3232 #endif
3234 // The after-PROLOG location of the return address. Location of
3235 // return address specifies a type (REG or STACK) and a number
3236 // representing the register number (i.e. - use a register name) or
3237 // stack slot.
3238 return_addr(REG R_I7); // Ret Addr is in register I7
3240 // Body of function which returns an OptoRegs array locating
3241 // arguments either in registers or in stack slots for calling
3242 // java
3243 calling_convention %{
3244 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3246 %}
3248 // Body of function which returns an OptoRegs array locating
3249 // arguments either in registers or in stack slots for callin
3250 // C.
3251 c_calling_convention %{
3252 // This is obviously always outgoing
3253 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3254 %}
3256 // Location of native (C/C++) and interpreter return values. This is specified to
3257 // be the same as Java. In the 32-bit VM, long values are actually returned from
3258 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3259 // to and from the register pairs is done by the appropriate call and epilog
3260 // opcodes. This simplifies the register allocator.
3261 c_return_value %{
3262 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3263 #ifdef _LP64
3264 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3265 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3266 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3267 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3268 #else // !_LP64
3269 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3270 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3271 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3272 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3273 #endif
3274 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3275 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3276 %}
3278 // Location of compiled Java return values. Same as C
3279 return_value %{
3280 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3281 #ifdef _LP64
3282 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3283 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3284 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3285 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3286 #else // !_LP64
3287 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3288 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3289 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3290 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3291 #endif
3292 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3293 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3294 %}
3296 %}
3299 //----------ATTRIBUTES---------------------------------------------------------
3300 //----------Operand Attributes-------------------------------------------------
3301 op_attrib op_cost(1); // Required cost attribute
3303 //----------Instruction Attributes---------------------------------------------
3304 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3305 ins_attrib ins_size(32); // Required size attribute (in bits)
3306 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3307 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3308 // non-matching short branch variant of some
3309 // long branch?
3311 //----------OPERANDS-----------------------------------------------------------
3312 // Operand definitions must precede instruction definitions for correct parsing
3313 // in the ADLC because operands constitute user defined types which are used in
3314 // instruction definitions.
3316 //----------Simple Operands----------------------------------------------------
3317 // Immediate Operands
3318 // Integer Immediate: 32-bit
3319 operand immI() %{
3320 match(ConI);
3322 op_cost(0);
3323 // formats are generated automatically for constants and base registers
3324 format %{ %}
3325 interface(CONST_INTER);
3326 %}
3328 // Integer Immediate: 8-bit
3329 operand immI8() %{
3330 predicate(Assembler::is_simm(n->get_int(), 8));
3331 match(ConI);
3332 op_cost(0);
3333 format %{ %}
3334 interface(CONST_INTER);
3335 %}
3337 // Integer Immediate: 13-bit
3338 operand immI13() %{
3339 predicate(Assembler::is_simm13(n->get_int()));
3340 match(ConI);
3341 op_cost(0);
3343 format %{ %}
3344 interface(CONST_INTER);
3345 %}
3347 // Integer Immediate: 13-bit minus 7
3348 operand immI13m7() %{
3349 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3350 match(ConI);
3351 op_cost(0);
3353 format %{ %}
3354 interface(CONST_INTER);
3355 %}
3357 // Integer Immediate: 16-bit
3358 operand immI16() %{
3359 predicate(Assembler::is_simm(n->get_int(), 16));
3360 match(ConI);
3361 op_cost(0);
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3366 // Unsigned (positive) Integer Immediate: 13-bit
3367 operand immU13() %{
3368 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3369 match(ConI);
3370 op_cost(0);
3372 format %{ %}
3373 interface(CONST_INTER);
3374 %}
3376 // Integer Immediate: 6-bit
3377 operand immU6() %{
3378 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3379 match(ConI);
3380 op_cost(0);
3381 format %{ %}
3382 interface(CONST_INTER);
3383 %}
3385 // Integer Immediate: 11-bit
3386 operand immI11() %{
3387 predicate(Assembler::is_simm(n->get_int(),11));
3388 match(ConI);
3389 op_cost(0);
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3394 // Integer Immediate: 5-bit
3395 operand immI5() %{
3396 predicate(Assembler::is_simm(n->get_int(), 5));
3397 match(ConI);
3398 op_cost(0);
3399 format %{ %}
3400 interface(CONST_INTER);
3401 %}
3403 // Integer Immediate: 0-bit
3404 operand immI0() %{
3405 predicate(n->get_int() == 0);
3406 match(ConI);
3407 op_cost(0);
3409 format %{ %}
3410 interface(CONST_INTER);
3411 %}
3413 // Integer Immediate: the value 10
3414 operand immI10() %{
3415 predicate(n->get_int() == 10);
3416 match(ConI);
3417 op_cost(0);
3419 format %{ %}
3420 interface(CONST_INTER);
3421 %}
3423 // Integer Immediate: the values 0-31
3424 operand immU5() %{
3425 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3426 match(ConI);
3427 op_cost(0);
3429 format %{ %}
3430 interface(CONST_INTER);
3431 %}
3433 // Integer Immediate: the values 1-31
3434 operand immI_1_31() %{
3435 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3436 match(ConI);
3437 op_cost(0);
3439 format %{ %}
3440 interface(CONST_INTER);
3441 %}
3443 // Integer Immediate: the values 32-63
3444 operand immI_32_63() %{
3445 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3446 match(ConI);
3447 op_cost(0);
3449 format %{ %}
3450 interface(CONST_INTER);
3451 %}
3453 // Immediates for special shifts (sign extend)
3455 // Integer Immediate: the value 16
3456 operand immI_16() %{
3457 predicate(n->get_int() == 16);
3458 match(ConI);
3459 op_cost(0);
3461 format %{ %}
3462 interface(CONST_INTER);
3463 %}
3465 // Integer Immediate: the value 24
3466 operand immI_24() %{
3467 predicate(n->get_int() == 24);
3468 match(ConI);
3469 op_cost(0);
3471 format %{ %}
3472 interface(CONST_INTER);
3473 %}
3475 // Integer Immediate: the value 255
3476 operand immI_255() %{
3477 predicate( n->get_int() == 255 );
3478 match(ConI);
3479 op_cost(0);
3481 format %{ %}
3482 interface(CONST_INTER);
3483 %}
3485 // Integer Immediate: the value 65535
3486 operand immI_65535() %{
3487 predicate(n->get_int() == 65535);
3488 match(ConI);
3489 op_cost(0);
3491 format %{ %}
3492 interface(CONST_INTER);
3493 %}
3495 // Long Immediate: the value FF
3496 operand immL_FF() %{
3497 predicate( n->get_long() == 0xFFL );
3498 match(ConL);
3499 op_cost(0);
3501 format %{ %}
3502 interface(CONST_INTER);
3503 %}
3505 // Long Immediate: the value FFFF
3506 operand immL_FFFF() %{
3507 predicate( n->get_long() == 0xFFFFL );
3508 match(ConL);
3509 op_cost(0);
3511 format %{ %}
3512 interface(CONST_INTER);
3513 %}
3515 // Pointer Immediate: 32 or 64-bit
3516 operand immP() %{
3517 match(ConP);
3519 op_cost(5);
3520 // formats are generated automatically for constants and base registers
3521 format %{ %}
3522 interface(CONST_INTER);
3523 %}
3525 #ifdef _LP64
3526 // Pointer Immediate: 64-bit
3527 operand immP_set() %{
3528 predicate(!VM_Version::is_niagara_plus());
3529 match(ConP);
3531 op_cost(5);
3532 // formats are generated automatically for constants and base registers
3533 format %{ %}
3534 interface(CONST_INTER);
3535 %}
3537 // Pointer Immediate: 64-bit
3538 // From Niagara2 processors on a load should be better than materializing.
3539 operand immP_load() %{
3540 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3541 match(ConP);
3543 op_cost(5);
3544 // formats are generated automatically for constants and base registers
3545 format %{ %}
3546 interface(CONST_INTER);
3547 %}
3549 // Pointer Immediate: 64-bit
3550 operand immP_no_oop_cheap() %{
3551 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3552 match(ConP);
3554 op_cost(5);
3555 // formats are generated automatically for constants and base registers
3556 format %{ %}
3557 interface(CONST_INTER);
3558 %}
3559 #endif
3561 operand immP13() %{
3562 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3563 match(ConP);
3564 op_cost(0);
3566 format %{ %}
3567 interface(CONST_INTER);
3568 %}
3570 operand immP0() %{
3571 predicate(n->get_ptr() == 0);
3572 match(ConP);
3573 op_cost(0);
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3579 operand immP_poll() %{
3580 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3581 match(ConP);
3583 // formats are generated automatically for constants and base registers
3584 format %{ %}
3585 interface(CONST_INTER);
3586 %}
3588 // Pointer Immediate
3589 operand immN()
3590 %{
3591 match(ConN);
3593 op_cost(10);
3594 format %{ %}
3595 interface(CONST_INTER);
3596 %}
3598 // NULL Pointer Immediate
3599 operand immN0()
3600 %{
3601 predicate(n->get_narrowcon() == 0);
3602 match(ConN);
3604 op_cost(0);
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3609 operand immL() %{
3610 match(ConL);
3611 op_cost(40);
3612 // formats are generated automatically for constants and base registers
3613 format %{ %}
3614 interface(CONST_INTER);
3615 %}
3617 operand immL0() %{
3618 predicate(n->get_long() == 0L);
3619 match(ConL);
3620 op_cost(0);
3621 // formats are generated automatically for constants and base registers
3622 format %{ %}
3623 interface(CONST_INTER);
3624 %}
3626 // Integer Immediate: 5-bit
3627 operand immL5() %{
3628 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm((int)n->get_long(), 5));
3629 match(ConL);
3630 op_cost(0);
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3635 // Long Immediate: 13-bit
3636 operand immL13() %{
3637 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3638 match(ConL);
3639 op_cost(0);
3641 format %{ %}
3642 interface(CONST_INTER);
3643 %}
3645 // Long Immediate: 13-bit minus 7
3646 operand immL13m7() %{
3647 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3648 match(ConL);
3649 op_cost(0);
3651 format %{ %}
3652 interface(CONST_INTER);
3653 %}
3655 // Long Immediate: low 32-bit mask
3656 operand immL_32bits() %{
3657 predicate(n->get_long() == 0xFFFFFFFFL);
3658 match(ConL);
3659 op_cost(0);
3661 format %{ %}
3662 interface(CONST_INTER);
3663 %}
3665 // Long Immediate: cheap (materialize in <= 3 instructions)
3666 operand immL_cheap() %{
3667 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3668 match(ConL);
3669 op_cost(0);
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3675 // Long Immediate: expensive (materialize in > 3 instructions)
3676 operand immL_expensive() %{
3677 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3678 match(ConL);
3679 op_cost(0);
3681 format %{ %}
3682 interface(CONST_INTER);
3683 %}
3685 // Double Immediate
3686 operand immD() %{
3687 match(ConD);
3689 op_cost(40);
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3694 operand immD0() %{
3695 #ifdef _LP64
3696 // on 64-bit architectures this comparision is faster
3697 predicate(jlong_cast(n->getd()) == 0);
3698 #else
3699 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3700 #endif
3701 match(ConD);
3703 op_cost(0);
3704 format %{ %}
3705 interface(CONST_INTER);
3706 %}
3708 // Float Immediate
3709 operand immF() %{
3710 match(ConF);
3712 op_cost(20);
3713 format %{ %}
3714 interface(CONST_INTER);
3715 %}
3717 // Float Immediate: 0
3718 operand immF0() %{
3719 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3720 match(ConF);
3722 op_cost(0);
3723 format %{ %}
3724 interface(CONST_INTER);
3725 %}
3727 // Integer Register Operands
3728 // Integer Register
3729 operand iRegI() %{
3730 constraint(ALLOC_IN_RC(int_reg));
3731 match(RegI);
3733 match(notemp_iRegI);
3734 match(g1RegI);
3735 match(o0RegI);
3736 match(iRegIsafe);
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3742 operand notemp_iRegI() %{
3743 constraint(ALLOC_IN_RC(notemp_int_reg));
3744 match(RegI);
3746 match(o0RegI);
3748 format %{ %}
3749 interface(REG_INTER);
3750 %}
3752 operand o0RegI() %{
3753 constraint(ALLOC_IN_RC(o0_regI));
3754 match(iRegI);
3756 format %{ %}
3757 interface(REG_INTER);
3758 %}
3760 // Pointer Register
3761 operand iRegP() %{
3762 constraint(ALLOC_IN_RC(ptr_reg));
3763 match(RegP);
3765 match(lock_ptr_RegP);
3766 match(g1RegP);
3767 match(g2RegP);
3768 match(g3RegP);
3769 match(g4RegP);
3770 match(i0RegP);
3771 match(o0RegP);
3772 match(o1RegP);
3773 match(l7RegP);
3775 format %{ %}
3776 interface(REG_INTER);
3777 %}
3779 operand sp_ptr_RegP() %{
3780 constraint(ALLOC_IN_RC(sp_ptr_reg));
3781 match(RegP);
3782 match(iRegP);
3784 format %{ %}
3785 interface(REG_INTER);
3786 %}
3788 operand lock_ptr_RegP() %{
3789 constraint(ALLOC_IN_RC(lock_ptr_reg));
3790 match(RegP);
3791 match(i0RegP);
3792 match(o0RegP);
3793 match(o1RegP);
3794 match(l7RegP);
3796 format %{ %}
3797 interface(REG_INTER);
3798 %}
3800 operand g1RegP() %{
3801 constraint(ALLOC_IN_RC(g1_regP));
3802 match(iRegP);
3804 format %{ %}
3805 interface(REG_INTER);
3806 %}
3808 operand g2RegP() %{
3809 constraint(ALLOC_IN_RC(g2_regP));
3810 match(iRegP);
3812 format %{ %}
3813 interface(REG_INTER);
3814 %}
3816 operand g3RegP() %{
3817 constraint(ALLOC_IN_RC(g3_regP));
3818 match(iRegP);
3820 format %{ %}
3821 interface(REG_INTER);
3822 %}
3824 operand g1RegI() %{
3825 constraint(ALLOC_IN_RC(g1_regI));
3826 match(iRegI);
3828 format %{ %}
3829 interface(REG_INTER);
3830 %}
3832 operand g3RegI() %{
3833 constraint(ALLOC_IN_RC(g3_regI));
3834 match(iRegI);
3836 format %{ %}
3837 interface(REG_INTER);
3838 %}
3840 operand g4RegI() %{
3841 constraint(ALLOC_IN_RC(g4_regI));
3842 match(iRegI);
3844 format %{ %}
3845 interface(REG_INTER);
3846 %}
3848 operand g4RegP() %{
3849 constraint(ALLOC_IN_RC(g4_regP));
3850 match(iRegP);
3852 format %{ %}
3853 interface(REG_INTER);
3854 %}
3856 operand i0RegP() %{
3857 constraint(ALLOC_IN_RC(i0_regP));
3858 match(iRegP);
3860 format %{ %}
3861 interface(REG_INTER);
3862 %}
3864 operand o0RegP() %{
3865 constraint(ALLOC_IN_RC(o0_regP));
3866 match(iRegP);
3868 format %{ %}
3869 interface(REG_INTER);
3870 %}
3872 operand o1RegP() %{
3873 constraint(ALLOC_IN_RC(o1_regP));
3874 match(iRegP);
3876 format %{ %}
3877 interface(REG_INTER);
3878 %}
3880 operand o2RegP() %{
3881 constraint(ALLOC_IN_RC(o2_regP));
3882 match(iRegP);
3884 format %{ %}
3885 interface(REG_INTER);
3886 %}
3888 operand o7RegP() %{
3889 constraint(ALLOC_IN_RC(o7_regP));
3890 match(iRegP);
3892 format %{ %}
3893 interface(REG_INTER);
3894 %}
3896 operand l7RegP() %{
3897 constraint(ALLOC_IN_RC(l7_regP));
3898 match(iRegP);
3900 format %{ %}
3901 interface(REG_INTER);
3902 %}
3904 operand o7RegI() %{
3905 constraint(ALLOC_IN_RC(o7_regI));
3906 match(iRegI);
3908 format %{ %}
3909 interface(REG_INTER);
3910 %}
3912 operand iRegN() %{
3913 constraint(ALLOC_IN_RC(int_reg));
3914 match(RegN);
3916 format %{ %}
3917 interface(REG_INTER);
3918 %}
3920 // Long Register
3921 operand iRegL() %{
3922 constraint(ALLOC_IN_RC(long_reg));
3923 match(RegL);
3925 format %{ %}
3926 interface(REG_INTER);
3927 %}
3929 operand o2RegL() %{
3930 constraint(ALLOC_IN_RC(o2_regL));
3931 match(iRegL);
3933 format %{ %}
3934 interface(REG_INTER);
3935 %}
3937 operand o7RegL() %{
3938 constraint(ALLOC_IN_RC(o7_regL));
3939 match(iRegL);
3941 format %{ %}
3942 interface(REG_INTER);
3943 %}
3945 operand g1RegL() %{
3946 constraint(ALLOC_IN_RC(g1_regL));
3947 match(iRegL);
3949 format %{ %}
3950 interface(REG_INTER);
3951 %}
3953 operand g3RegL() %{
3954 constraint(ALLOC_IN_RC(g3_regL));
3955 match(iRegL);
3957 format %{ %}
3958 interface(REG_INTER);
3959 %}
3961 // Int Register safe
3962 // This is 64bit safe
3963 operand iRegIsafe() %{
3964 constraint(ALLOC_IN_RC(long_reg));
3966 match(iRegI);
3968 format %{ %}
3969 interface(REG_INTER);
3970 %}
3972 // Condition Code Flag Register
3973 operand flagsReg() %{
3974 constraint(ALLOC_IN_RC(int_flags));
3975 match(RegFlags);
3977 format %{ "ccr" %} // both ICC and XCC
3978 interface(REG_INTER);
3979 %}
3981 // Condition Code Register, unsigned comparisons.
3982 operand flagsRegU() %{
3983 constraint(ALLOC_IN_RC(int_flags));
3984 match(RegFlags);
3986 format %{ "icc_U" %}
3987 interface(REG_INTER);
3988 %}
3990 // Condition Code Register, pointer comparisons.
3991 operand flagsRegP() %{
3992 constraint(ALLOC_IN_RC(int_flags));
3993 match(RegFlags);
3995 #ifdef _LP64
3996 format %{ "xcc_P" %}
3997 #else
3998 format %{ "icc_P" %}
3999 #endif
4000 interface(REG_INTER);
4001 %}
4003 // Condition Code Register, long comparisons.
4004 operand flagsRegL() %{
4005 constraint(ALLOC_IN_RC(int_flags));
4006 match(RegFlags);
4008 format %{ "xcc_L" %}
4009 interface(REG_INTER);
4010 %}
4012 // Condition Code Register, floating comparisons, unordered same as "less".
4013 operand flagsRegF() %{
4014 constraint(ALLOC_IN_RC(float_flags));
4015 match(RegFlags);
4016 match(flagsRegF0);
4018 format %{ %}
4019 interface(REG_INTER);
4020 %}
4022 operand flagsRegF0() %{
4023 constraint(ALLOC_IN_RC(float_flag0));
4024 match(RegFlags);
4026 format %{ %}
4027 interface(REG_INTER);
4028 %}
4031 // Condition Code Flag Register used by long compare
4032 operand flagsReg_long_LTGE() %{
4033 constraint(ALLOC_IN_RC(int_flags));
4034 match(RegFlags);
4035 format %{ "icc_LTGE" %}
4036 interface(REG_INTER);
4037 %}
4038 operand flagsReg_long_EQNE() %{
4039 constraint(ALLOC_IN_RC(int_flags));
4040 match(RegFlags);
4041 format %{ "icc_EQNE" %}
4042 interface(REG_INTER);
4043 %}
4044 operand flagsReg_long_LEGT() %{
4045 constraint(ALLOC_IN_RC(int_flags));
4046 match(RegFlags);
4047 format %{ "icc_LEGT" %}
4048 interface(REG_INTER);
4049 %}
4052 operand regD() %{
4053 constraint(ALLOC_IN_RC(dflt_reg));
4054 match(RegD);
4056 match(regD_low);
4058 format %{ %}
4059 interface(REG_INTER);
4060 %}
4062 operand regF() %{
4063 constraint(ALLOC_IN_RC(sflt_reg));
4064 match(RegF);
4066 format %{ %}
4067 interface(REG_INTER);
4068 %}
4070 operand regD_low() %{
4071 constraint(ALLOC_IN_RC(dflt_low_reg));
4072 match(regD);
4074 format %{ %}
4075 interface(REG_INTER);
4076 %}
4078 // Special Registers
4080 // Method Register
4081 operand inline_cache_regP(iRegP reg) %{
4082 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4083 match(reg);
4084 format %{ %}
4085 interface(REG_INTER);
4086 %}
4088 operand interpreter_method_oop_regP(iRegP reg) %{
4089 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4090 match(reg);
4091 format %{ %}
4092 interface(REG_INTER);
4093 %}
4096 //----------Complex Operands---------------------------------------------------
4097 // Indirect Memory Reference
4098 operand indirect(sp_ptr_RegP reg) %{
4099 constraint(ALLOC_IN_RC(sp_ptr_reg));
4100 match(reg);
4102 op_cost(100);
4103 format %{ "[$reg]" %}
4104 interface(MEMORY_INTER) %{
4105 base($reg);
4106 index(0x0);
4107 scale(0x0);
4108 disp(0x0);
4109 %}
4110 %}
4112 // Indirect with simm13 Offset
4113 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4114 constraint(ALLOC_IN_RC(sp_ptr_reg));
4115 match(AddP reg offset);
4117 op_cost(100);
4118 format %{ "[$reg + $offset]" %}
4119 interface(MEMORY_INTER) %{
4120 base($reg);
4121 index(0x0);
4122 scale(0x0);
4123 disp($offset);
4124 %}
4125 %}
4127 // Indirect with simm13 Offset minus 7
4128 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4129 constraint(ALLOC_IN_RC(sp_ptr_reg));
4130 match(AddP reg offset);
4132 op_cost(100);
4133 format %{ "[$reg + $offset]" %}
4134 interface(MEMORY_INTER) %{
4135 base($reg);
4136 index(0x0);
4137 scale(0x0);
4138 disp($offset);
4139 %}
4140 %}
4142 // Note: Intel has a swapped version also, like this:
4143 //operand indOffsetX(iRegI reg, immP offset) %{
4144 // constraint(ALLOC_IN_RC(int_reg));
4145 // match(AddP offset reg);
4146 //
4147 // op_cost(100);
4148 // format %{ "[$reg + $offset]" %}
4149 // interface(MEMORY_INTER) %{
4150 // base($reg);
4151 // index(0x0);
4152 // scale(0x0);
4153 // disp($offset);
4154 // %}
4155 //%}
4156 //// However, it doesn't make sense for SPARC, since
4157 // we have no particularly good way to embed oops in
4158 // single instructions.
4160 // Indirect with Register Index
4161 operand indIndex(iRegP addr, iRegX index) %{
4162 constraint(ALLOC_IN_RC(ptr_reg));
4163 match(AddP addr index);
4165 op_cost(100);
4166 format %{ "[$addr + $index]" %}
4167 interface(MEMORY_INTER) %{
4168 base($addr);
4169 index($index);
4170 scale(0x0);
4171 disp(0x0);
4172 %}
4173 %}
4175 //----------Special Memory Operands--------------------------------------------
4176 // Stack Slot Operand - This operand is used for loading and storing temporary
4177 // values on the stack where a match requires a value to
4178 // flow through memory.
4179 operand stackSlotI(sRegI reg) %{
4180 constraint(ALLOC_IN_RC(stack_slots));
4181 op_cost(100);
4182 //match(RegI);
4183 format %{ "[$reg]" %}
4184 interface(MEMORY_INTER) %{
4185 base(0xE); // R_SP
4186 index(0x0);
4187 scale(0x0);
4188 disp($reg); // Stack Offset
4189 %}
4190 %}
4192 operand stackSlotP(sRegP reg) %{
4193 constraint(ALLOC_IN_RC(stack_slots));
4194 op_cost(100);
4195 //match(RegP);
4196 format %{ "[$reg]" %}
4197 interface(MEMORY_INTER) %{
4198 base(0xE); // R_SP
4199 index(0x0);
4200 scale(0x0);
4201 disp($reg); // Stack Offset
4202 %}
4203 %}
4205 operand stackSlotF(sRegF reg) %{
4206 constraint(ALLOC_IN_RC(stack_slots));
4207 op_cost(100);
4208 //match(RegF);
4209 format %{ "[$reg]" %}
4210 interface(MEMORY_INTER) %{
4211 base(0xE); // R_SP
4212 index(0x0);
4213 scale(0x0);
4214 disp($reg); // Stack Offset
4215 %}
4216 %}
4217 operand stackSlotD(sRegD reg) %{
4218 constraint(ALLOC_IN_RC(stack_slots));
4219 op_cost(100);
4220 //match(RegD);
4221 format %{ "[$reg]" %}
4222 interface(MEMORY_INTER) %{
4223 base(0xE); // R_SP
4224 index(0x0);
4225 scale(0x0);
4226 disp($reg); // Stack Offset
4227 %}
4228 %}
4229 operand stackSlotL(sRegL reg) %{
4230 constraint(ALLOC_IN_RC(stack_slots));
4231 op_cost(100);
4232 //match(RegL);
4233 format %{ "[$reg]" %}
4234 interface(MEMORY_INTER) %{
4235 base(0xE); // R_SP
4236 index(0x0);
4237 scale(0x0);
4238 disp($reg); // Stack Offset
4239 %}
4240 %}
4242 // Operands for expressing Control Flow
4243 // NOTE: Label is a predefined operand which should not be redefined in
4244 // the AD file. It is generically handled within the ADLC.
4246 //----------Conditional Branch Operands----------------------------------------
4247 // Comparison Op - This is the operation of the comparison, and is limited to
4248 // the following set of codes:
4249 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4250 //
4251 // Other attributes of the comparison, such as unsignedness, are specified
4252 // by the comparison instruction that sets a condition code flags register.
4253 // That result is represented by a flags operand whose subtype is appropriate
4254 // to the unsignedness (etc.) of the comparison.
4255 //
4256 // Later, the instruction which matches both the Comparison Op (a Bool) and
4257 // the flags (produced by the Cmp) specifies the coding of the comparison op
4258 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4260 operand cmpOp() %{
4261 match(Bool);
4263 format %{ "" %}
4264 interface(COND_INTER) %{
4265 equal(0x1);
4266 not_equal(0x9);
4267 less(0x3);
4268 greater_equal(0xB);
4269 less_equal(0x2);
4270 greater(0xA);
4271 %}
4272 %}
4274 // Comparison Op, unsigned
4275 operand cmpOpU() %{
4276 match(Bool);
4278 format %{ "u" %}
4279 interface(COND_INTER) %{
4280 equal(0x1);
4281 not_equal(0x9);
4282 less(0x5);
4283 greater_equal(0xD);
4284 less_equal(0x4);
4285 greater(0xC);
4286 %}
4287 %}
4289 // Comparison Op, pointer (same as unsigned)
4290 operand cmpOpP() %{
4291 match(Bool);
4293 format %{ "p" %}
4294 interface(COND_INTER) %{
4295 equal(0x1);
4296 not_equal(0x9);
4297 less(0x5);
4298 greater_equal(0xD);
4299 less_equal(0x4);
4300 greater(0xC);
4301 %}
4302 %}
4304 // Comparison Op, branch-register encoding
4305 operand cmpOp_reg() %{
4306 match(Bool);
4308 format %{ "" %}
4309 interface(COND_INTER) %{
4310 equal (0x1);
4311 not_equal (0x5);
4312 less (0x3);
4313 greater_equal(0x7);
4314 less_equal (0x2);
4315 greater (0x6);
4316 %}
4317 %}
4319 // Comparison Code, floating, unordered same as less
4320 operand cmpOpF() %{
4321 match(Bool);
4323 format %{ "fl" %}
4324 interface(COND_INTER) %{
4325 equal(0x9);
4326 not_equal(0x1);
4327 less(0x3);
4328 greater_equal(0xB);
4329 less_equal(0xE);
4330 greater(0x6);
4331 %}
4332 %}
4334 // Used by long compare
4335 operand cmpOp_commute() %{
4336 match(Bool);
4338 format %{ "" %}
4339 interface(COND_INTER) %{
4340 equal(0x1);
4341 not_equal(0x9);
4342 less(0xA);
4343 greater_equal(0x2);
4344 less_equal(0xB);
4345 greater(0x3);
4346 %}
4347 %}
4349 //----------OPERAND CLASSES----------------------------------------------------
4350 // Operand Classes are groups of operands that are used to simplify
4351 // instruction definitions by not requiring the AD writer to specify separate
4352 // instructions for every form of operand when the instruction accepts
4353 // multiple operand types with the same basic encoding and format. The classic
4354 // case of this is memory operands.
4355 opclass memory( indirect, indOffset13, indIndex );
4356 opclass indIndexMemory( indIndex );
4358 //----------PIPELINE-----------------------------------------------------------
4359 pipeline %{
4361 //----------ATTRIBUTES---------------------------------------------------------
4362 attributes %{
4363 fixed_size_instructions; // Fixed size instructions
4364 branch_has_delay_slot; // Branch has delay slot following
4365 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4366 instruction_unit_size = 4; // An instruction is 4 bytes long
4367 instruction_fetch_unit_size = 16; // The processor fetches one line
4368 instruction_fetch_units = 1; // of 16 bytes
4370 // List of nop instructions
4371 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4372 %}
4374 //----------RESOURCES----------------------------------------------------------
4375 // Resources are the functional units available to the machine
4376 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4378 //----------PIPELINE DESCRIPTION-----------------------------------------------
4379 // Pipeline Description specifies the stages in the machine's pipeline
4381 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4383 //----------PIPELINE CLASSES---------------------------------------------------
4384 // Pipeline Classes describe the stages in which input and output are
4385 // referenced by the hardware pipeline.
4387 // Integer ALU reg-reg operation
4388 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4389 single_instruction;
4390 dst : E(write);
4391 src1 : R(read);
4392 src2 : R(read);
4393 IALU : R;
4394 %}
4396 // Integer ALU reg-reg long operation
4397 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4398 instruction_count(2);
4399 dst : E(write);
4400 src1 : R(read);
4401 src2 : R(read);
4402 IALU : R;
4403 IALU : R;
4404 %}
4406 // Integer ALU reg-reg long dependent operation
4407 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4408 instruction_count(1); multiple_bundles;
4409 dst : E(write);
4410 src1 : R(read);
4411 src2 : R(read);
4412 cr : E(write);
4413 IALU : R(2);
4414 %}
4416 // Integer ALU reg-imm operaion
4417 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4418 single_instruction;
4419 dst : E(write);
4420 src1 : R(read);
4421 IALU : R;
4422 %}
4424 // Integer ALU reg-reg operation with condition code
4425 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4426 single_instruction;
4427 dst : E(write);
4428 cr : E(write);
4429 src1 : R(read);
4430 src2 : R(read);
4431 IALU : R;
4432 %}
4434 // Integer ALU reg-imm operation with condition code
4435 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4436 single_instruction;
4437 dst : E(write);
4438 cr : E(write);
4439 src1 : R(read);
4440 IALU : R;
4441 %}
4443 // Integer ALU zero-reg operation
4444 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4445 single_instruction;
4446 dst : E(write);
4447 src2 : R(read);
4448 IALU : R;
4449 %}
4451 // Integer ALU zero-reg operation with condition code only
4452 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4453 single_instruction;
4454 cr : E(write);
4455 src : R(read);
4456 IALU : R;
4457 %}
4459 // Integer ALU reg-reg operation with condition code only
4460 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4461 single_instruction;
4462 cr : E(write);
4463 src1 : R(read);
4464 src2 : R(read);
4465 IALU : R;
4466 %}
4468 // Integer ALU reg-imm operation with condition code only
4469 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4470 single_instruction;
4471 cr : E(write);
4472 src1 : R(read);
4473 IALU : R;
4474 %}
4476 // Integer ALU reg-reg-zero operation with condition code only
4477 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4478 single_instruction;
4479 cr : E(write);
4480 src1 : R(read);
4481 src2 : R(read);
4482 IALU : R;
4483 %}
4485 // Integer ALU reg-imm-zero operation with condition code only
4486 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4487 single_instruction;
4488 cr : E(write);
4489 src1 : R(read);
4490 IALU : R;
4491 %}
4493 // Integer ALU reg-reg operation with condition code, src1 modified
4494 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4495 single_instruction;
4496 cr : E(write);
4497 src1 : E(write);
4498 src1 : R(read);
4499 src2 : R(read);
4500 IALU : R;
4501 %}
4503 // Integer ALU reg-imm operation with condition code, src1 modified
4504 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4505 single_instruction;
4506 cr : E(write);
4507 src1 : E(write);
4508 src1 : R(read);
4509 IALU : R;
4510 %}
4512 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4513 multiple_bundles;
4514 dst : E(write)+4;
4515 cr : E(write);
4516 src1 : R(read);
4517 src2 : R(read);
4518 IALU : R(3);
4519 BR : R(2);
4520 %}
4522 // Integer ALU operation
4523 pipe_class ialu_none(iRegI dst) %{
4524 single_instruction;
4525 dst : E(write);
4526 IALU : R;
4527 %}
4529 // Integer ALU reg operation
4530 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4531 single_instruction; may_have_no_code;
4532 dst : E(write);
4533 src : R(read);
4534 IALU : R;
4535 %}
4537 // Integer ALU reg conditional operation
4538 // This instruction has a 1 cycle stall, and cannot execute
4539 // in the same cycle as the instruction setting the condition
4540 // code. We kludge this by pretending to read the condition code
4541 // 1 cycle earlier, and by marking the functional units as busy
4542 // for 2 cycles with the result available 1 cycle later than
4543 // is really the case.
4544 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4545 single_instruction;
4546 op2_out : C(write);
4547 op1 : R(read);
4548 cr : R(read); // This is really E, with a 1 cycle stall
4549 BR : R(2);
4550 MS : R(2);
4551 %}
4553 #ifdef _LP64
4554 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4555 instruction_count(1); multiple_bundles;
4556 dst : C(write)+1;
4557 src : R(read)+1;
4558 IALU : R(1);
4559 BR : E(2);
4560 MS : E(2);
4561 %}
4562 #endif
4564 // Integer ALU reg operation
4565 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4566 single_instruction; may_have_no_code;
4567 dst : E(write);
4568 src : R(read);
4569 IALU : R;
4570 %}
4571 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4572 single_instruction; may_have_no_code;
4573 dst : E(write);
4574 src : R(read);
4575 IALU : R;
4576 %}
4578 // Two integer ALU reg operations
4579 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4580 instruction_count(2);
4581 dst : E(write);
4582 src : R(read);
4583 A0 : R;
4584 A1 : R;
4585 %}
4587 // Two integer ALU reg operations
4588 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4589 instruction_count(2); may_have_no_code;
4590 dst : E(write);
4591 src : R(read);
4592 A0 : R;
4593 A1 : R;
4594 %}
4596 // Integer ALU imm operation
4597 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4598 single_instruction;
4599 dst : E(write);
4600 IALU : R;
4601 %}
4603 // Integer ALU reg-reg with carry operation
4604 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4605 single_instruction;
4606 dst : E(write);
4607 src1 : R(read);
4608 src2 : R(read);
4609 IALU : R;
4610 %}
4612 // Integer ALU cc operation
4613 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4614 single_instruction;
4615 dst : E(write);
4616 cc : R(read);
4617 IALU : R;
4618 %}
4620 // Integer ALU cc / second IALU operation
4621 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4622 instruction_count(1); multiple_bundles;
4623 dst : E(write)+1;
4624 src : R(read);
4625 IALU : R;
4626 %}
4628 // Integer ALU cc / second IALU operation
4629 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4630 instruction_count(1); multiple_bundles;
4631 dst : E(write)+1;
4632 p : R(read);
4633 q : R(read);
4634 IALU : R;
4635 %}
4637 // Integer ALU hi-lo-reg operation
4638 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4639 instruction_count(1); multiple_bundles;
4640 dst : E(write)+1;
4641 IALU : R(2);
4642 %}
4644 // Float ALU hi-lo-reg operation (with temp)
4645 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4646 instruction_count(1); multiple_bundles;
4647 dst : E(write)+1;
4648 IALU : R(2);
4649 %}
4651 // Long Constant
4652 pipe_class loadConL( iRegL dst, immL src ) %{
4653 instruction_count(2); multiple_bundles;
4654 dst : E(write)+1;
4655 IALU : R(2);
4656 IALU : R(2);
4657 %}
4659 // Pointer Constant
4660 pipe_class loadConP( iRegP dst, immP src ) %{
4661 instruction_count(0); multiple_bundles;
4662 fixed_latency(6);
4663 %}
4665 // Polling Address
4666 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4667 #ifdef _LP64
4668 instruction_count(0); multiple_bundles;
4669 fixed_latency(6);
4670 #else
4671 dst : E(write);
4672 IALU : R;
4673 #endif
4674 %}
4676 // Long Constant small
4677 pipe_class loadConLlo( iRegL dst, immL src ) %{
4678 instruction_count(2);
4679 dst : E(write);
4680 IALU : R;
4681 IALU : R;
4682 %}
4684 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4685 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4686 instruction_count(1); multiple_bundles;
4687 src : R(read);
4688 dst : M(write)+1;
4689 IALU : R;
4690 MS : E;
4691 %}
4693 // Integer ALU nop operation
4694 pipe_class ialu_nop() %{
4695 single_instruction;
4696 IALU : R;
4697 %}
4699 // Integer ALU nop operation
4700 pipe_class ialu_nop_A0() %{
4701 single_instruction;
4702 A0 : R;
4703 %}
4705 // Integer ALU nop operation
4706 pipe_class ialu_nop_A1() %{
4707 single_instruction;
4708 A1 : R;
4709 %}
4711 // Integer Multiply reg-reg operation
4712 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4713 single_instruction;
4714 dst : E(write);
4715 src1 : R(read);
4716 src2 : R(read);
4717 MS : R(5);
4718 %}
4720 // Integer Multiply reg-imm operation
4721 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4722 single_instruction;
4723 dst : E(write);
4724 src1 : R(read);
4725 MS : R(5);
4726 %}
4728 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4729 single_instruction;
4730 dst : E(write)+4;
4731 src1 : R(read);
4732 src2 : R(read);
4733 MS : R(6);
4734 %}
4736 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4737 single_instruction;
4738 dst : E(write)+4;
4739 src1 : R(read);
4740 MS : R(6);
4741 %}
4743 // Integer Divide reg-reg
4744 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4745 instruction_count(1); multiple_bundles;
4746 dst : E(write);
4747 temp : E(write);
4748 src1 : R(read);
4749 src2 : R(read);
4750 temp : R(read);
4751 MS : R(38);
4752 %}
4754 // Integer Divide reg-imm
4755 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4756 instruction_count(1); multiple_bundles;
4757 dst : E(write);
4758 temp : E(write);
4759 src1 : R(read);
4760 temp : R(read);
4761 MS : R(38);
4762 %}
4764 // Long Divide
4765 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4766 dst : E(write)+71;
4767 src1 : R(read);
4768 src2 : R(read)+1;
4769 MS : R(70);
4770 %}
4772 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4773 dst : E(write)+71;
4774 src1 : R(read);
4775 MS : R(70);
4776 %}
4778 // Floating Point Add Float
4779 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4780 single_instruction;
4781 dst : X(write);
4782 src1 : E(read);
4783 src2 : E(read);
4784 FA : R;
4785 %}
4787 // Floating Point Add Double
4788 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4789 single_instruction;
4790 dst : X(write);
4791 src1 : E(read);
4792 src2 : E(read);
4793 FA : R;
4794 %}
4796 // Floating Point Conditional Move based on integer flags
4797 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4798 single_instruction;
4799 dst : X(write);
4800 src : E(read);
4801 cr : R(read);
4802 FA : R(2);
4803 BR : R(2);
4804 %}
4806 // Floating Point Conditional Move based on integer flags
4807 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4808 single_instruction;
4809 dst : X(write);
4810 src : E(read);
4811 cr : R(read);
4812 FA : R(2);
4813 BR : R(2);
4814 %}
4816 // Floating Point Multiply Float
4817 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4818 single_instruction;
4819 dst : X(write);
4820 src1 : E(read);
4821 src2 : E(read);
4822 FM : R;
4823 %}
4825 // Floating Point Multiply Double
4826 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4827 single_instruction;
4828 dst : X(write);
4829 src1 : E(read);
4830 src2 : E(read);
4831 FM : R;
4832 %}
4834 // Floating Point Divide Float
4835 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4836 single_instruction;
4837 dst : X(write);
4838 src1 : E(read);
4839 src2 : E(read);
4840 FM : R;
4841 FDIV : C(14);
4842 %}
4844 // Floating Point Divide Double
4845 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4846 single_instruction;
4847 dst : X(write);
4848 src1 : E(read);
4849 src2 : E(read);
4850 FM : R;
4851 FDIV : C(17);
4852 %}
4854 // Floating Point Move/Negate/Abs Float
4855 pipe_class faddF_reg(regF dst, regF src) %{
4856 single_instruction;
4857 dst : W(write);
4858 src : E(read);
4859 FA : R(1);
4860 %}
4862 // Floating Point Move/Negate/Abs Double
4863 pipe_class faddD_reg(regD dst, regD src) %{
4864 single_instruction;
4865 dst : W(write);
4866 src : E(read);
4867 FA : R;
4868 %}
4870 // Floating Point Convert F->D
4871 pipe_class fcvtF2D(regD dst, regF src) %{
4872 single_instruction;
4873 dst : X(write);
4874 src : E(read);
4875 FA : R;
4876 %}
4878 // Floating Point Convert I->D
4879 pipe_class fcvtI2D(regD dst, regF src) %{
4880 single_instruction;
4881 dst : X(write);
4882 src : E(read);
4883 FA : R;
4884 %}
4886 // Floating Point Convert LHi->D
4887 pipe_class fcvtLHi2D(regD dst, regD src) %{
4888 single_instruction;
4889 dst : X(write);
4890 src : E(read);
4891 FA : R;
4892 %}
4894 // Floating Point Convert L->D
4895 pipe_class fcvtL2D(regD dst, regF src) %{
4896 single_instruction;
4897 dst : X(write);
4898 src : E(read);
4899 FA : R;
4900 %}
4902 // Floating Point Convert L->F
4903 pipe_class fcvtL2F(regD dst, regF src) %{
4904 single_instruction;
4905 dst : X(write);
4906 src : E(read);
4907 FA : R;
4908 %}
4910 // Floating Point Convert D->F
4911 pipe_class fcvtD2F(regD dst, regF src) %{
4912 single_instruction;
4913 dst : X(write);
4914 src : E(read);
4915 FA : R;
4916 %}
4918 // Floating Point Convert I->L
4919 pipe_class fcvtI2L(regD dst, regF src) %{
4920 single_instruction;
4921 dst : X(write);
4922 src : E(read);
4923 FA : R;
4924 %}
4926 // Floating Point Convert D->F
4927 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4928 instruction_count(1); multiple_bundles;
4929 dst : X(write)+6;
4930 src : E(read);
4931 FA : R;
4932 %}
4934 // Floating Point Convert D->L
4935 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4936 instruction_count(1); multiple_bundles;
4937 dst : X(write)+6;
4938 src : E(read);
4939 FA : R;
4940 %}
4942 // Floating Point Convert F->I
4943 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4944 instruction_count(1); multiple_bundles;
4945 dst : X(write)+6;
4946 src : E(read);
4947 FA : R;
4948 %}
4950 // Floating Point Convert F->L
4951 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4952 instruction_count(1); multiple_bundles;
4953 dst : X(write)+6;
4954 src : E(read);
4955 FA : R;
4956 %}
4958 // Floating Point Convert I->F
4959 pipe_class fcvtI2F(regF dst, regF src) %{
4960 single_instruction;
4961 dst : X(write);
4962 src : E(read);
4963 FA : R;
4964 %}
4966 // Floating Point Compare
4967 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4968 single_instruction;
4969 cr : X(write);
4970 src1 : E(read);
4971 src2 : E(read);
4972 FA : R;
4973 %}
4975 // Floating Point Compare
4976 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4977 single_instruction;
4978 cr : X(write);
4979 src1 : E(read);
4980 src2 : E(read);
4981 FA : R;
4982 %}
4984 // Floating Add Nop
4985 pipe_class fadd_nop() %{
4986 single_instruction;
4987 FA : R;
4988 %}
4990 // Integer Store to Memory
4991 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4992 single_instruction;
4993 mem : R(read);
4994 src : C(read);
4995 MS : R;
4996 %}
4998 // Integer Store to Memory
4999 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5000 single_instruction;
5001 mem : R(read);
5002 src : C(read);
5003 MS : R;
5004 %}
5006 // Integer Store Zero to Memory
5007 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5008 single_instruction;
5009 mem : R(read);
5010 MS : R;
5011 %}
5013 // Special Stack Slot Store
5014 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5015 single_instruction;
5016 stkSlot : R(read);
5017 src : C(read);
5018 MS : R;
5019 %}
5021 // Special Stack Slot Store
5022 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5023 instruction_count(2); multiple_bundles;
5024 stkSlot : R(read);
5025 src : C(read);
5026 MS : R(2);
5027 %}
5029 // Float Store
5030 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5031 single_instruction;
5032 mem : R(read);
5033 src : C(read);
5034 MS : R;
5035 %}
5037 // Float Store
5038 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5039 single_instruction;
5040 mem : R(read);
5041 MS : R;
5042 %}
5044 // Double Store
5045 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5046 instruction_count(1);
5047 mem : R(read);
5048 src : C(read);
5049 MS : R;
5050 %}
5052 // Double Store
5053 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5054 single_instruction;
5055 mem : R(read);
5056 MS : R;
5057 %}
5059 // Special Stack Slot Float Store
5060 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5061 single_instruction;
5062 stkSlot : R(read);
5063 src : C(read);
5064 MS : R;
5065 %}
5067 // Special Stack Slot Double Store
5068 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5069 single_instruction;
5070 stkSlot : R(read);
5071 src : C(read);
5072 MS : R;
5073 %}
5075 // Integer Load (when sign bit propagation not needed)
5076 pipe_class iload_mem(iRegI dst, memory mem) %{
5077 single_instruction;
5078 mem : R(read);
5079 dst : C(write);
5080 MS : R;
5081 %}
5083 // Integer Load from stack operand
5084 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5085 single_instruction;
5086 mem : R(read);
5087 dst : C(write);
5088 MS : R;
5089 %}
5091 // Integer Load (when sign bit propagation or masking is needed)
5092 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5093 single_instruction;
5094 mem : R(read);
5095 dst : M(write);
5096 MS : R;
5097 %}
5099 // Float Load
5100 pipe_class floadF_mem(regF dst, memory mem) %{
5101 single_instruction;
5102 mem : R(read);
5103 dst : M(write);
5104 MS : R;
5105 %}
5107 // Float Load
5108 pipe_class floadD_mem(regD dst, memory mem) %{
5109 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5110 mem : R(read);
5111 dst : M(write);
5112 MS : R;
5113 %}
5115 // Float Load
5116 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5117 single_instruction;
5118 stkSlot : R(read);
5119 dst : M(write);
5120 MS : R;
5121 %}
5123 // Float Load
5124 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5125 single_instruction;
5126 stkSlot : R(read);
5127 dst : M(write);
5128 MS : R;
5129 %}
5131 // Memory Nop
5132 pipe_class mem_nop() %{
5133 single_instruction;
5134 MS : R;
5135 %}
5137 pipe_class sethi(iRegP dst, immI src) %{
5138 single_instruction;
5139 dst : E(write);
5140 IALU : R;
5141 %}
5143 pipe_class loadPollP(iRegP poll) %{
5144 single_instruction;
5145 poll : R(read);
5146 MS : R;
5147 %}
5149 pipe_class br(Universe br, label labl) %{
5150 single_instruction_with_delay_slot;
5151 BR : R;
5152 %}
5154 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5155 single_instruction_with_delay_slot;
5156 cr : E(read);
5157 BR : R;
5158 %}
5160 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5161 single_instruction_with_delay_slot;
5162 op1 : E(read);
5163 BR : R;
5164 MS : R;
5165 %}
5167 // Compare and branch
5168 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5169 instruction_count(2); has_delay_slot;
5170 cr : E(write);
5171 src1 : R(read);
5172 src2 : R(read);
5173 IALU : R;
5174 BR : R;
5175 %}
5177 // Compare and branch
5178 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5179 instruction_count(2); has_delay_slot;
5180 cr : E(write);
5181 src1 : R(read);
5182 IALU : R;
5183 BR : R;
5184 %}
5186 // Compare and branch using cbcond
5187 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5188 single_instruction;
5189 src1 : E(read);
5190 src2 : E(read);
5191 IALU : R;
5192 BR : R;
5193 %}
5195 // Compare and branch using cbcond
5196 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5197 single_instruction;
5198 src1 : E(read);
5199 IALU : R;
5200 BR : R;
5201 %}
5203 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5204 single_instruction_with_delay_slot;
5205 cr : E(read);
5206 BR : R;
5207 %}
5209 pipe_class br_nop() %{
5210 single_instruction;
5211 BR : R;
5212 %}
5214 pipe_class simple_call(method meth) %{
5215 instruction_count(2); multiple_bundles; force_serialization;
5216 fixed_latency(100);
5217 BR : R(1);
5218 MS : R(1);
5219 A0 : R(1);
5220 %}
5222 pipe_class compiled_call(method meth) %{
5223 instruction_count(1); multiple_bundles; force_serialization;
5224 fixed_latency(100);
5225 MS : R(1);
5226 %}
5228 pipe_class call(method meth) %{
5229 instruction_count(0); multiple_bundles; force_serialization;
5230 fixed_latency(100);
5231 %}
5233 pipe_class tail_call(Universe ignore, label labl) %{
5234 single_instruction; has_delay_slot;
5235 fixed_latency(100);
5236 BR : R(1);
5237 MS : R(1);
5238 %}
5240 pipe_class ret(Universe ignore) %{
5241 single_instruction; has_delay_slot;
5242 BR : R(1);
5243 MS : R(1);
5244 %}
5246 pipe_class ret_poll(g3RegP poll) %{
5247 instruction_count(3); has_delay_slot;
5248 poll : E(read);
5249 MS : R;
5250 %}
5252 // The real do-nothing guy
5253 pipe_class empty( ) %{
5254 instruction_count(0);
5255 %}
5257 pipe_class long_memory_op() %{
5258 instruction_count(0); multiple_bundles; force_serialization;
5259 fixed_latency(25);
5260 MS : R(1);
5261 %}
5263 // Check-cast
5264 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5265 array : R(read);
5266 match : R(read);
5267 IALU : R(2);
5268 BR : R(2);
5269 MS : R;
5270 %}
5272 // Convert FPU flags into +1,0,-1
5273 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5274 src1 : E(read);
5275 src2 : E(read);
5276 dst : E(write);
5277 FA : R;
5278 MS : R(2);
5279 BR : R(2);
5280 %}
5282 // Compare for p < q, and conditionally add y
5283 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5284 p : E(read);
5285 q : E(read);
5286 y : E(read);
5287 IALU : R(3)
5288 %}
5290 // Perform a compare, then move conditionally in a branch delay slot.
5291 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5292 src2 : E(read);
5293 srcdst : E(read);
5294 IALU : R;
5295 BR : R;
5296 %}
5298 // Define the class for the Nop node
5299 define %{
5300 MachNop = ialu_nop;
5301 %}
5303 %}
5305 //----------INSTRUCTIONS-------------------------------------------------------
5307 //------------Special Stack Slot instructions - no match rules-----------------
5308 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5309 // No match rule to avoid chain rule match.
5310 effect(DEF dst, USE src);
5311 ins_cost(MEMORY_REF_COST);
5312 size(4);
5313 format %{ "LDF $src,$dst\t! stkI to regF" %}
5314 opcode(Assembler::ldf_op3);
5315 ins_encode(simple_form3_mem_reg(src, dst));
5316 ins_pipe(floadF_stk);
5317 %}
5319 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5320 // No match rule to avoid chain rule match.
5321 effect(DEF dst, USE src);
5322 ins_cost(MEMORY_REF_COST);
5323 size(4);
5324 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5325 opcode(Assembler::lddf_op3);
5326 ins_encode(simple_form3_mem_reg(src, dst));
5327 ins_pipe(floadD_stk);
5328 %}
5330 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5331 // No match rule to avoid chain rule match.
5332 effect(DEF dst, USE src);
5333 ins_cost(MEMORY_REF_COST);
5334 size(4);
5335 format %{ "STF $src,$dst\t! regF to stkI" %}
5336 opcode(Assembler::stf_op3);
5337 ins_encode(simple_form3_mem_reg(dst, src));
5338 ins_pipe(fstoreF_stk_reg);
5339 %}
5341 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5342 // No match rule to avoid chain rule match.
5343 effect(DEF dst, USE src);
5344 ins_cost(MEMORY_REF_COST);
5345 size(4);
5346 format %{ "STDF $src,$dst\t! regD to stkL" %}
5347 opcode(Assembler::stdf_op3);
5348 ins_encode(simple_form3_mem_reg(dst, src));
5349 ins_pipe(fstoreD_stk_reg);
5350 %}
5352 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5353 effect(DEF dst, USE src);
5354 ins_cost(MEMORY_REF_COST*2);
5355 size(8);
5356 format %{ "STW $src,$dst.hi\t! long\n\t"
5357 "STW R_G0,$dst.lo" %}
5358 opcode(Assembler::stw_op3);
5359 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5360 ins_pipe(lstoreI_stk_reg);
5361 %}
5363 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5364 // No match rule to avoid chain rule match.
5365 effect(DEF dst, USE src);
5366 ins_cost(MEMORY_REF_COST);
5367 size(4);
5368 format %{ "STX $src,$dst\t! regL to stkD" %}
5369 opcode(Assembler::stx_op3);
5370 ins_encode(simple_form3_mem_reg( dst, src ) );
5371 ins_pipe(istore_stk_reg);
5372 %}
5374 //---------- Chain stack slots between similar types --------
5376 // Load integer from stack slot
5377 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5378 match(Set dst src);
5379 ins_cost(MEMORY_REF_COST);
5381 size(4);
5382 format %{ "LDUW $src,$dst\t!stk" %}
5383 opcode(Assembler::lduw_op3);
5384 ins_encode(simple_form3_mem_reg( src, dst ) );
5385 ins_pipe(iload_mem);
5386 %}
5388 // Store integer to stack slot
5389 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5390 match(Set dst src);
5391 ins_cost(MEMORY_REF_COST);
5393 size(4);
5394 format %{ "STW $src,$dst\t!stk" %}
5395 opcode(Assembler::stw_op3);
5396 ins_encode(simple_form3_mem_reg( dst, src ) );
5397 ins_pipe(istore_mem_reg);
5398 %}
5400 // Load long from stack slot
5401 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5402 match(Set dst src);
5404 ins_cost(MEMORY_REF_COST);
5405 size(4);
5406 format %{ "LDX $src,$dst\t! long" %}
5407 opcode(Assembler::ldx_op3);
5408 ins_encode(simple_form3_mem_reg( src, dst ) );
5409 ins_pipe(iload_mem);
5410 %}
5412 // Store long to stack slot
5413 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5414 match(Set dst src);
5416 ins_cost(MEMORY_REF_COST);
5417 size(4);
5418 format %{ "STX $src,$dst\t! long" %}
5419 opcode(Assembler::stx_op3);
5420 ins_encode(simple_form3_mem_reg( dst, src ) );
5421 ins_pipe(istore_mem_reg);
5422 %}
5424 #ifdef _LP64
5425 // Load pointer from stack slot, 64-bit encoding
5426 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5427 match(Set dst src);
5428 ins_cost(MEMORY_REF_COST);
5429 size(4);
5430 format %{ "LDX $src,$dst\t!ptr" %}
5431 opcode(Assembler::ldx_op3);
5432 ins_encode(simple_form3_mem_reg( src, dst ) );
5433 ins_pipe(iload_mem);
5434 %}
5436 // Store pointer to stack slot
5437 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5438 match(Set dst src);
5439 ins_cost(MEMORY_REF_COST);
5440 size(4);
5441 format %{ "STX $src,$dst\t!ptr" %}
5442 opcode(Assembler::stx_op3);
5443 ins_encode(simple_form3_mem_reg( dst, src ) );
5444 ins_pipe(istore_mem_reg);
5445 %}
5446 #else // _LP64
5447 // Load pointer from stack slot, 32-bit encoding
5448 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5449 match(Set dst src);
5450 ins_cost(MEMORY_REF_COST);
5451 format %{ "LDUW $src,$dst\t!ptr" %}
5452 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5453 ins_encode(simple_form3_mem_reg( src, dst ) );
5454 ins_pipe(iload_mem);
5455 %}
5457 // Store pointer to stack slot
5458 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5459 match(Set dst src);
5460 ins_cost(MEMORY_REF_COST);
5461 format %{ "STW $src,$dst\t!ptr" %}
5462 opcode(Assembler::stw_op3, Assembler::ldst_op);
5463 ins_encode(simple_form3_mem_reg( dst, src ) );
5464 ins_pipe(istore_mem_reg);
5465 %}
5466 #endif // _LP64
5468 //------------Special Nop instructions for bundling - no match rules-----------
5469 // Nop using the A0 functional unit
5470 instruct Nop_A0() %{
5471 ins_cost(0);
5473 format %{ "NOP ! Alu Pipeline" %}
5474 opcode(Assembler::or_op3, Assembler::arith_op);
5475 ins_encode( form2_nop() );
5476 ins_pipe(ialu_nop_A0);
5477 %}
5479 // Nop using the A1 functional unit
5480 instruct Nop_A1( ) %{
5481 ins_cost(0);
5483 format %{ "NOP ! Alu Pipeline" %}
5484 opcode(Assembler::or_op3, Assembler::arith_op);
5485 ins_encode( form2_nop() );
5486 ins_pipe(ialu_nop_A1);
5487 %}
5489 // Nop using the memory functional unit
5490 instruct Nop_MS( ) %{
5491 ins_cost(0);
5493 format %{ "NOP ! Memory Pipeline" %}
5494 ins_encode( emit_mem_nop );
5495 ins_pipe(mem_nop);
5496 %}
5498 // Nop using the floating add functional unit
5499 instruct Nop_FA( ) %{
5500 ins_cost(0);
5502 format %{ "NOP ! Floating Add Pipeline" %}
5503 ins_encode( emit_fadd_nop );
5504 ins_pipe(fadd_nop);
5505 %}
5507 // Nop using the branch functional unit
5508 instruct Nop_BR( ) %{
5509 ins_cost(0);
5511 format %{ "NOP ! Branch Pipeline" %}
5512 ins_encode( emit_br_nop );
5513 ins_pipe(br_nop);
5514 %}
5516 //----------Load/Store/Move Instructions---------------------------------------
5517 //----------Load Instructions--------------------------------------------------
5518 // Load Byte (8bit signed)
5519 instruct loadB(iRegI dst, memory mem) %{
5520 match(Set dst (LoadB mem));
5521 ins_cost(MEMORY_REF_COST);
5523 size(4);
5524 format %{ "LDSB $mem,$dst\t! byte" %}
5525 ins_encode %{
5526 __ ldsb($mem$$Address, $dst$$Register);
5527 %}
5528 ins_pipe(iload_mask_mem);
5529 %}
5531 // Load Byte (8bit signed) into a Long Register
5532 instruct loadB2L(iRegL dst, memory mem) %{
5533 match(Set dst (ConvI2L (LoadB mem)));
5534 ins_cost(MEMORY_REF_COST);
5536 size(4);
5537 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5538 ins_encode %{
5539 __ ldsb($mem$$Address, $dst$$Register);
5540 %}
5541 ins_pipe(iload_mask_mem);
5542 %}
5544 // Load Unsigned Byte (8bit UNsigned) into an int reg
5545 instruct loadUB(iRegI dst, memory mem) %{
5546 match(Set dst (LoadUB mem));
5547 ins_cost(MEMORY_REF_COST);
5549 size(4);
5550 format %{ "LDUB $mem,$dst\t! ubyte" %}
5551 ins_encode %{
5552 __ ldub($mem$$Address, $dst$$Register);
5553 %}
5554 ins_pipe(iload_mem);
5555 %}
5557 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5558 instruct loadUB2L(iRegL dst, memory mem) %{
5559 match(Set dst (ConvI2L (LoadUB mem)));
5560 ins_cost(MEMORY_REF_COST);
5562 size(4);
5563 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5564 ins_encode %{
5565 __ ldub($mem$$Address, $dst$$Register);
5566 %}
5567 ins_pipe(iload_mem);
5568 %}
5570 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5571 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5572 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5573 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5575 size(2*4);
5576 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5577 "AND $dst,$mask,$dst" %}
5578 ins_encode %{
5579 __ ldub($mem$$Address, $dst$$Register);
5580 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5581 %}
5582 ins_pipe(iload_mem);
5583 %}
5585 // Load Short (16bit signed)
5586 instruct loadS(iRegI dst, memory mem) %{
5587 match(Set dst (LoadS mem));
5588 ins_cost(MEMORY_REF_COST);
5590 size(4);
5591 format %{ "LDSH $mem,$dst\t! short" %}
5592 ins_encode %{
5593 __ ldsh($mem$$Address, $dst$$Register);
5594 %}
5595 ins_pipe(iload_mask_mem);
5596 %}
5598 // Load Short (16 bit signed) to Byte (8 bit signed)
5599 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5600 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5601 ins_cost(MEMORY_REF_COST);
5603 size(4);
5605 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5606 ins_encode %{
5607 __ ldsb($mem$$Address, $dst$$Register, 1);
5608 %}
5609 ins_pipe(iload_mask_mem);
5610 %}
5612 // Load Short (16bit signed) into a Long Register
5613 instruct loadS2L(iRegL dst, memory mem) %{
5614 match(Set dst (ConvI2L (LoadS mem)));
5615 ins_cost(MEMORY_REF_COST);
5617 size(4);
5618 format %{ "LDSH $mem,$dst\t! short -> long" %}
5619 ins_encode %{
5620 __ ldsh($mem$$Address, $dst$$Register);
5621 %}
5622 ins_pipe(iload_mask_mem);
5623 %}
5625 // Load Unsigned Short/Char (16bit UNsigned)
5626 instruct loadUS(iRegI dst, memory mem) %{
5627 match(Set dst (LoadUS mem));
5628 ins_cost(MEMORY_REF_COST);
5630 size(4);
5631 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5632 ins_encode %{
5633 __ lduh($mem$$Address, $dst$$Register);
5634 %}
5635 ins_pipe(iload_mem);
5636 %}
5638 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5639 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5640 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5641 ins_cost(MEMORY_REF_COST);
5643 size(4);
5644 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5645 ins_encode %{
5646 __ ldsb($mem$$Address, $dst$$Register, 1);
5647 %}
5648 ins_pipe(iload_mask_mem);
5649 %}
5651 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5652 instruct loadUS2L(iRegL dst, memory mem) %{
5653 match(Set dst (ConvI2L (LoadUS mem)));
5654 ins_cost(MEMORY_REF_COST);
5656 size(4);
5657 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5658 ins_encode %{
5659 __ lduh($mem$$Address, $dst$$Register);
5660 %}
5661 ins_pipe(iload_mem);
5662 %}
5664 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5665 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5666 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5667 ins_cost(MEMORY_REF_COST);
5669 size(4);
5670 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5671 ins_encode %{
5672 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5673 %}
5674 ins_pipe(iload_mem);
5675 %}
5677 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5678 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5679 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5680 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5682 size(2*4);
5683 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5684 "AND $dst,$mask,$dst" %}
5685 ins_encode %{
5686 Register Rdst = $dst$$Register;
5687 __ lduh($mem$$Address, Rdst);
5688 __ and3(Rdst, $mask$$constant, Rdst);
5689 %}
5690 ins_pipe(iload_mem);
5691 %}
5693 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5694 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5695 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5696 effect(TEMP dst, TEMP tmp);
5697 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5699 size((3+1)*4); // set may use two instructions.
5700 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5701 "SET $mask,$tmp\n\t"
5702 "AND $dst,$tmp,$dst" %}
5703 ins_encode %{
5704 Register Rdst = $dst$$Register;
5705 Register Rtmp = $tmp$$Register;
5706 __ lduh($mem$$Address, Rdst);
5707 __ set($mask$$constant, Rtmp);
5708 __ and3(Rdst, Rtmp, Rdst);
5709 %}
5710 ins_pipe(iload_mem);
5711 %}
5713 // Load Integer
5714 instruct loadI(iRegI dst, memory mem) %{
5715 match(Set dst (LoadI mem));
5716 ins_cost(MEMORY_REF_COST);
5718 size(4);
5719 format %{ "LDUW $mem,$dst\t! int" %}
5720 ins_encode %{
5721 __ lduw($mem$$Address, $dst$$Register);
5722 %}
5723 ins_pipe(iload_mem);
5724 %}
5726 // Load Integer to Byte (8 bit signed)
5727 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5728 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5729 ins_cost(MEMORY_REF_COST);
5731 size(4);
5733 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5734 ins_encode %{
5735 __ ldsb($mem$$Address, $dst$$Register, 3);
5736 %}
5737 ins_pipe(iload_mask_mem);
5738 %}
5740 // Load Integer to Unsigned Byte (8 bit UNsigned)
5741 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5742 match(Set dst (AndI (LoadI mem) mask));
5743 ins_cost(MEMORY_REF_COST);
5745 size(4);
5747 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5748 ins_encode %{
5749 __ ldub($mem$$Address, $dst$$Register, 3);
5750 %}
5751 ins_pipe(iload_mask_mem);
5752 %}
5754 // Load Integer to Short (16 bit signed)
5755 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5756 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5757 ins_cost(MEMORY_REF_COST);
5759 size(4);
5761 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5762 ins_encode %{
5763 __ ldsh($mem$$Address, $dst$$Register, 2);
5764 %}
5765 ins_pipe(iload_mask_mem);
5766 %}
5768 // Load Integer to Unsigned Short (16 bit UNsigned)
5769 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5770 match(Set dst (AndI (LoadI mem) mask));
5771 ins_cost(MEMORY_REF_COST);
5773 size(4);
5775 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5776 ins_encode %{
5777 __ lduh($mem$$Address, $dst$$Register, 2);
5778 %}
5779 ins_pipe(iload_mask_mem);
5780 %}
5782 // Load Integer into a Long Register
5783 instruct loadI2L(iRegL dst, memory mem) %{
5784 match(Set dst (ConvI2L (LoadI mem)));
5785 ins_cost(MEMORY_REF_COST);
5787 size(4);
5788 format %{ "LDSW $mem,$dst\t! int -> long" %}
5789 ins_encode %{
5790 __ ldsw($mem$$Address, $dst$$Register);
5791 %}
5792 ins_pipe(iload_mask_mem);
5793 %}
5795 // Load Integer with mask 0xFF into a Long Register
5796 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5797 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5798 ins_cost(MEMORY_REF_COST);
5800 size(4);
5801 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5802 ins_encode %{
5803 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5804 %}
5805 ins_pipe(iload_mem);
5806 %}
5808 // Load Integer with mask 0xFFFF into a Long Register
5809 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5810 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5811 ins_cost(MEMORY_REF_COST);
5813 size(4);
5814 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5815 ins_encode %{
5816 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5817 %}
5818 ins_pipe(iload_mem);
5819 %}
5821 // Load Integer with a 13-bit mask into a Long Register
5822 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5823 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5824 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5826 size(2*4);
5827 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5828 "AND $dst,$mask,$dst" %}
5829 ins_encode %{
5830 Register Rdst = $dst$$Register;
5831 __ lduw($mem$$Address, Rdst);
5832 __ and3(Rdst, $mask$$constant, Rdst);
5833 %}
5834 ins_pipe(iload_mem);
5835 %}
5837 // Load Integer with a 32-bit mask into a Long Register
5838 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5839 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5840 effect(TEMP dst, TEMP tmp);
5841 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5843 size((3+1)*4); // set may use two instructions.
5844 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5845 "SET $mask,$tmp\n\t"
5846 "AND $dst,$tmp,$dst" %}
5847 ins_encode %{
5848 Register Rdst = $dst$$Register;
5849 Register Rtmp = $tmp$$Register;
5850 __ lduw($mem$$Address, Rdst);
5851 __ set($mask$$constant, Rtmp);
5852 __ and3(Rdst, Rtmp, Rdst);
5853 %}
5854 ins_pipe(iload_mem);
5855 %}
5857 // Load Unsigned Integer into a Long Register
5858 instruct loadUI2L(iRegL dst, memory mem) %{
5859 match(Set dst (LoadUI2L mem));
5860 ins_cost(MEMORY_REF_COST);
5862 size(4);
5863 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5864 ins_encode %{
5865 __ lduw($mem$$Address, $dst$$Register);
5866 %}
5867 ins_pipe(iload_mem);
5868 %}
5870 // Load Long - aligned
5871 instruct loadL(iRegL dst, memory mem ) %{
5872 match(Set dst (LoadL mem));
5873 ins_cost(MEMORY_REF_COST);
5875 size(4);
5876 format %{ "LDX $mem,$dst\t! long" %}
5877 ins_encode %{
5878 __ ldx($mem$$Address, $dst$$Register);
5879 %}
5880 ins_pipe(iload_mem);
5881 %}
5883 // Load Long - UNaligned
5884 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5885 match(Set dst (LoadL_unaligned mem));
5886 effect(KILL tmp);
5887 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5888 size(16);
5889 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5890 "\tLDUW $mem ,$dst\n"
5891 "\tSLLX #32, $dst, $dst\n"
5892 "\tOR $dst, R_O7, $dst" %}
5893 opcode(Assembler::lduw_op3);
5894 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5895 ins_pipe(iload_mem);
5896 %}
5898 // Load Aligned Packed Byte into a Double Register
5899 instruct loadA8B(regD dst, memory mem) %{
5900 match(Set dst (Load8B mem));
5901 ins_cost(MEMORY_REF_COST);
5902 size(4);
5903 format %{ "LDDF $mem,$dst\t! packed8B" %}
5904 opcode(Assembler::lddf_op3);
5905 ins_encode(simple_form3_mem_reg( mem, dst ) );
5906 ins_pipe(floadD_mem);
5907 %}
5909 // Load Aligned Packed Char into a Double Register
5910 instruct loadA4C(regD dst, memory mem) %{
5911 match(Set dst (Load4C mem));
5912 ins_cost(MEMORY_REF_COST);
5913 size(4);
5914 format %{ "LDDF $mem,$dst\t! packed4C" %}
5915 opcode(Assembler::lddf_op3);
5916 ins_encode(simple_form3_mem_reg( mem, dst ) );
5917 ins_pipe(floadD_mem);
5918 %}
5920 // Load Aligned Packed Short into a Double Register
5921 instruct loadA4S(regD dst, memory mem) %{
5922 match(Set dst (Load4S mem));
5923 ins_cost(MEMORY_REF_COST);
5924 size(4);
5925 format %{ "LDDF $mem,$dst\t! packed4S" %}
5926 opcode(Assembler::lddf_op3);
5927 ins_encode(simple_form3_mem_reg( mem, dst ) );
5928 ins_pipe(floadD_mem);
5929 %}
5931 // Load Aligned Packed Int into a Double Register
5932 instruct loadA2I(regD dst, memory mem) %{
5933 match(Set dst (Load2I mem));
5934 ins_cost(MEMORY_REF_COST);
5935 size(4);
5936 format %{ "LDDF $mem,$dst\t! packed2I" %}
5937 opcode(Assembler::lddf_op3);
5938 ins_encode(simple_form3_mem_reg( mem, dst ) );
5939 ins_pipe(floadD_mem);
5940 %}
5942 // Load Range
5943 instruct loadRange(iRegI dst, memory mem) %{
5944 match(Set dst (LoadRange mem));
5945 ins_cost(MEMORY_REF_COST);
5947 size(4);
5948 format %{ "LDUW $mem,$dst\t! range" %}
5949 opcode(Assembler::lduw_op3);
5950 ins_encode(simple_form3_mem_reg( mem, dst ) );
5951 ins_pipe(iload_mem);
5952 %}
5954 // Load Integer into %f register (for fitos/fitod)
5955 instruct loadI_freg(regF dst, memory mem) %{
5956 match(Set dst (LoadI mem));
5957 ins_cost(MEMORY_REF_COST);
5958 size(4);
5960 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5961 opcode(Assembler::ldf_op3);
5962 ins_encode(simple_form3_mem_reg( mem, dst ) );
5963 ins_pipe(floadF_mem);
5964 %}
5966 // Load Pointer
5967 instruct loadP(iRegP dst, memory mem) %{
5968 match(Set dst (LoadP mem));
5969 ins_cost(MEMORY_REF_COST);
5970 size(4);
5972 #ifndef _LP64
5973 format %{ "LDUW $mem,$dst\t! ptr" %}
5974 ins_encode %{
5975 __ lduw($mem$$Address, $dst$$Register);
5976 %}
5977 #else
5978 format %{ "LDX $mem,$dst\t! ptr" %}
5979 ins_encode %{
5980 __ ldx($mem$$Address, $dst$$Register);
5981 %}
5982 #endif
5983 ins_pipe(iload_mem);
5984 %}
5986 // Load Compressed Pointer
5987 instruct loadN(iRegN dst, memory mem) %{
5988 match(Set dst (LoadN mem));
5989 ins_cost(MEMORY_REF_COST);
5990 size(4);
5992 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5993 ins_encode %{
5994 __ lduw($mem$$Address, $dst$$Register);
5995 %}
5996 ins_pipe(iload_mem);
5997 %}
5999 // Load Klass Pointer
6000 instruct loadKlass(iRegP dst, memory mem) %{
6001 match(Set dst (LoadKlass mem));
6002 ins_cost(MEMORY_REF_COST);
6003 size(4);
6005 #ifndef _LP64
6006 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6007 ins_encode %{
6008 __ lduw($mem$$Address, $dst$$Register);
6009 %}
6010 #else
6011 format %{ "LDX $mem,$dst\t! klass ptr" %}
6012 ins_encode %{
6013 __ ldx($mem$$Address, $dst$$Register);
6014 %}
6015 #endif
6016 ins_pipe(iload_mem);
6017 %}
6019 // Load narrow Klass Pointer
6020 instruct loadNKlass(iRegN dst, memory mem) %{
6021 match(Set dst (LoadNKlass mem));
6022 ins_cost(MEMORY_REF_COST);
6023 size(4);
6025 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6026 ins_encode %{
6027 __ lduw($mem$$Address, $dst$$Register);
6028 %}
6029 ins_pipe(iload_mem);
6030 %}
6032 // Load Double
6033 instruct loadD(regD dst, memory mem) %{
6034 match(Set dst (LoadD mem));
6035 ins_cost(MEMORY_REF_COST);
6037 size(4);
6038 format %{ "LDDF $mem,$dst" %}
6039 opcode(Assembler::lddf_op3);
6040 ins_encode(simple_form3_mem_reg( mem, dst ) );
6041 ins_pipe(floadD_mem);
6042 %}
6044 // Load Double - UNaligned
6045 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6046 match(Set dst (LoadD_unaligned mem));
6047 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6048 size(8);
6049 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6050 "\tLDF $mem+4,$dst.lo\t!" %}
6051 opcode(Assembler::ldf_op3);
6052 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6053 ins_pipe(iload_mem);
6054 %}
6056 // Load Float
6057 instruct loadF(regF dst, memory mem) %{
6058 match(Set dst (LoadF mem));
6059 ins_cost(MEMORY_REF_COST);
6061 size(4);
6062 format %{ "LDF $mem,$dst" %}
6063 opcode(Assembler::ldf_op3);
6064 ins_encode(simple_form3_mem_reg( mem, dst ) );
6065 ins_pipe(floadF_mem);
6066 %}
6068 // Load Constant
6069 instruct loadConI( iRegI dst, immI src ) %{
6070 match(Set dst src);
6071 ins_cost(DEFAULT_COST * 3/2);
6072 format %{ "SET $src,$dst" %}
6073 ins_encode( Set32(src, dst) );
6074 ins_pipe(ialu_hi_lo_reg);
6075 %}
6077 instruct loadConI13( iRegI dst, immI13 src ) %{
6078 match(Set dst src);
6080 size(4);
6081 format %{ "MOV $src,$dst" %}
6082 ins_encode( Set13( src, dst ) );
6083 ins_pipe(ialu_imm);
6084 %}
6086 #ifndef _LP64
6087 instruct loadConP(iRegP dst, immP con) %{
6088 match(Set dst con);
6089 ins_cost(DEFAULT_COST * 3/2);
6090 format %{ "SET $con,$dst\t!ptr" %}
6091 ins_encode %{
6092 // [RGV] This next line should be generated from ADLC
6093 if (_opnds[1]->constant_is_oop()) {
6094 intptr_t val = $con$$constant;
6095 __ set_oop_constant((jobject) val, $dst$$Register);
6096 } else { // non-oop pointers, e.g. card mark base, heap top
6097 __ set($con$$constant, $dst$$Register);
6098 }
6099 %}
6100 ins_pipe(loadConP);
6101 %}
6102 #else
6103 instruct loadConP_set(iRegP dst, immP_set con) %{
6104 match(Set dst con);
6105 ins_cost(DEFAULT_COST * 3/2);
6106 format %{ "SET $con,$dst\t! ptr" %}
6107 ins_encode %{
6108 // [RGV] This next line should be generated from ADLC
6109 if (_opnds[1]->constant_is_oop()) {
6110 intptr_t val = $con$$constant;
6111 __ set_oop_constant((jobject) val, $dst$$Register);
6112 } else { // non-oop pointers, e.g. card mark base, heap top
6113 __ set($con$$constant, $dst$$Register);
6114 }
6115 %}
6116 ins_pipe(loadConP);
6117 %}
6119 instruct loadConP_load(iRegP dst, immP_load con) %{
6120 match(Set dst con);
6121 ins_cost(MEMORY_REF_COST);
6122 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6123 ins_encode %{
6124 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6125 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6126 %}
6127 ins_pipe(loadConP);
6128 %}
6130 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6131 match(Set dst con);
6132 ins_cost(DEFAULT_COST * 3/2);
6133 format %{ "SET $con,$dst\t! non-oop ptr" %}
6134 ins_encode %{
6135 __ set($con$$constant, $dst$$Register);
6136 %}
6137 ins_pipe(loadConP);
6138 %}
6139 #endif // _LP64
6141 instruct loadConP0(iRegP dst, immP0 src) %{
6142 match(Set dst src);
6144 size(4);
6145 format %{ "CLR $dst\t!ptr" %}
6146 ins_encode %{
6147 __ clr($dst$$Register);
6148 %}
6149 ins_pipe(ialu_imm);
6150 %}
6152 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6153 match(Set dst src);
6154 ins_cost(DEFAULT_COST);
6155 format %{ "SET $src,$dst\t!ptr" %}
6156 ins_encode %{
6157 AddressLiteral polling_page(os::get_polling_page());
6158 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6159 %}
6160 ins_pipe(loadConP_poll);
6161 %}
6163 instruct loadConN0(iRegN dst, immN0 src) %{
6164 match(Set dst src);
6166 size(4);
6167 format %{ "CLR $dst\t! compressed NULL ptr" %}
6168 ins_encode %{
6169 __ clr($dst$$Register);
6170 %}
6171 ins_pipe(ialu_imm);
6172 %}
6174 instruct loadConN(iRegN dst, immN src) %{
6175 match(Set dst src);
6176 ins_cost(DEFAULT_COST * 3/2);
6177 format %{ "SET $src,$dst\t! compressed ptr" %}
6178 ins_encode %{
6179 Register dst = $dst$$Register;
6180 __ set_narrow_oop((jobject)$src$$constant, dst);
6181 %}
6182 ins_pipe(ialu_hi_lo_reg);
6183 %}
6185 // Materialize long value (predicated by immL_cheap).
6186 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6187 match(Set dst con);
6188 effect(KILL tmp);
6189 ins_cost(DEFAULT_COST * 3);
6190 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6191 ins_encode %{
6192 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6193 %}
6194 ins_pipe(loadConL);
6195 %}
6197 // Load long value from constant table (predicated by immL_expensive).
6198 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6199 match(Set dst con);
6200 ins_cost(MEMORY_REF_COST);
6201 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6202 ins_encode %{
6203 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6204 __ ldx($constanttablebase, con_offset, $dst$$Register);
6205 %}
6206 ins_pipe(loadConL);
6207 %}
6209 instruct loadConL0( iRegL dst, immL0 src ) %{
6210 match(Set dst src);
6211 ins_cost(DEFAULT_COST);
6212 size(4);
6213 format %{ "CLR $dst\t! long" %}
6214 ins_encode( Set13( src, dst ) );
6215 ins_pipe(ialu_imm);
6216 %}
6218 instruct loadConL13( iRegL dst, immL13 src ) %{
6219 match(Set dst src);
6220 ins_cost(DEFAULT_COST * 2);
6222 size(4);
6223 format %{ "MOV $src,$dst\t! long" %}
6224 ins_encode( Set13( src, dst ) );
6225 ins_pipe(ialu_imm);
6226 %}
6228 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6229 match(Set dst con);
6230 effect(KILL tmp);
6231 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6232 ins_encode %{
6233 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6234 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6235 %}
6236 ins_pipe(loadConFD);
6237 %}
6239 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6240 match(Set dst con);
6241 effect(KILL tmp);
6242 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6243 ins_encode %{
6244 // XXX This is a quick fix for 6833573.
6245 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6246 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6247 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6248 %}
6249 ins_pipe(loadConFD);
6250 %}
6252 // Prefetch instructions.
6253 // Must be safe to execute with invalid address (cannot fault).
6255 instruct prefetchr( memory mem ) %{
6256 match( PrefetchRead mem );
6257 ins_cost(MEMORY_REF_COST);
6258 size(4);
6260 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6261 opcode(Assembler::prefetch_op3);
6262 ins_encode( form3_mem_prefetch_read( mem ) );
6263 ins_pipe(iload_mem);
6264 %}
6266 instruct prefetchw( memory mem ) %{
6267 match( PrefetchWrite mem );
6268 ins_cost(MEMORY_REF_COST);
6269 size(4);
6271 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6272 opcode(Assembler::prefetch_op3);
6273 ins_encode( form3_mem_prefetch_write( mem ) );
6274 ins_pipe(iload_mem);
6275 %}
6277 // Prefetch instructions for allocation.
6279 instruct prefetchAlloc( memory mem ) %{
6280 predicate(AllocatePrefetchInstr == 0);
6281 match( PrefetchAllocation mem );
6282 ins_cost(MEMORY_REF_COST);
6283 size(4);
6285 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6286 opcode(Assembler::prefetch_op3);
6287 ins_encode( form3_mem_prefetch_write( mem ) );
6288 ins_pipe(iload_mem);
6289 %}
6291 // Use BIS instruction to prefetch for allocation.
6292 // Could fault, need space at the end of TLAB.
6293 instruct prefetchAlloc_bis( iRegP dst ) %{
6294 predicate(AllocatePrefetchInstr == 1);
6295 match( PrefetchAllocation dst );
6296 ins_cost(MEMORY_REF_COST);
6297 size(4);
6299 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6300 ins_encode %{
6301 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6302 %}
6303 ins_pipe(istore_mem_reg);
6304 %}
6306 // Next code is used for finding next cache line address to prefetch.
6307 #ifndef _LP64
6308 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6309 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6310 ins_cost(DEFAULT_COST);
6311 size(4);
6313 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6314 ins_encode %{
6315 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6316 %}
6317 ins_pipe(ialu_reg_imm);
6318 %}
6319 #else
6320 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6321 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6322 ins_cost(DEFAULT_COST);
6323 size(4);
6325 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6326 ins_encode %{
6327 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6328 %}
6329 ins_pipe(ialu_reg_imm);
6330 %}
6331 #endif
6333 //----------Store Instructions-------------------------------------------------
6334 // Store Byte
6335 instruct storeB(memory mem, iRegI src) %{
6336 match(Set mem (StoreB mem src));
6337 ins_cost(MEMORY_REF_COST);
6339 size(4);
6340 format %{ "STB $src,$mem\t! byte" %}
6341 opcode(Assembler::stb_op3);
6342 ins_encode(simple_form3_mem_reg( mem, src ) );
6343 ins_pipe(istore_mem_reg);
6344 %}
6346 instruct storeB0(memory mem, immI0 src) %{
6347 match(Set mem (StoreB mem src));
6348 ins_cost(MEMORY_REF_COST);
6350 size(4);
6351 format %{ "STB $src,$mem\t! byte" %}
6352 opcode(Assembler::stb_op3);
6353 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6354 ins_pipe(istore_mem_zero);
6355 %}
6357 instruct storeCM0(memory mem, immI0 src) %{
6358 match(Set mem (StoreCM mem src));
6359 ins_cost(MEMORY_REF_COST);
6361 size(4);
6362 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6363 opcode(Assembler::stb_op3);
6364 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6365 ins_pipe(istore_mem_zero);
6366 %}
6368 // Store Char/Short
6369 instruct storeC(memory mem, iRegI src) %{
6370 match(Set mem (StoreC mem src));
6371 ins_cost(MEMORY_REF_COST);
6373 size(4);
6374 format %{ "STH $src,$mem\t! short" %}
6375 opcode(Assembler::sth_op3);
6376 ins_encode(simple_form3_mem_reg( mem, src ) );
6377 ins_pipe(istore_mem_reg);
6378 %}
6380 instruct storeC0(memory mem, immI0 src) %{
6381 match(Set mem (StoreC mem src));
6382 ins_cost(MEMORY_REF_COST);
6384 size(4);
6385 format %{ "STH $src,$mem\t! short" %}
6386 opcode(Assembler::sth_op3);
6387 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6388 ins_pipe(istore_mem_zero);
6389 %}
6391 // Store Integer
6392 instruct storeI(memory mem, iRegI src) %{
6393 match(Set mem (StoreI mem src));
6394 ins_cost(MEMORY_REF_COST);
6396 size(4);
6397 format %{ "STW $src,$mem" %}
6398 opcode(Assembler::stw_op3);
6399 ins_encode(simple_form3_mem_reg( mem, src ) );
6400 ins_pipe(istore_mem_reg);
6401 %}
6403 // Store Long
6404 instruct storeL(memory mem, iRegL src) %{
6405 match(Set mem (StoreL mem src));
6406 ins_cost(MEMORY_REF_COST);
6407 size(4);
6408 format %{ "STX $src,$mem\t! long" %}
6409 opcode(Assembler::stx_op3);
6410 ins_encode(simple_form3_mem_reg( mem, src ) );
6411 ins_pipe(istore_mem_reg);
6412 %}
6414 instruct storeI0(memory mem, immI0 src) %{
6415 match(Set mem (StoreI mem src));
6416 ins_cost(MEMORY_REF_COST);
6418 size(4);
6419 format %{ "STW $src,$mem" %}
6420 opcode(Assembler::stw_op3);
6421 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6422 ins_pipe(istore_mem_zero);
6423 %}
6425 instruct storeL0(memory mem, immL0 src) %{
6426 match(Set mem (StoreL mem src));
6427 ins_cost(MEMORY_REF_COST);
6429 size(4);
6430 format %{ "STX $src,$mem" %}
6431 opcode(Assembler::stx_op3);
6432 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6433 ins_pipe(istore_mem_zero);
6434 %}
6436 // Store Integer from float register (used after fstoi)
6437 instruct storeI_Freg(memory mem, regF src) %{
6438 match(Set mem (StoreI mem src));
6439 ins_cost(MEMORY_REF_COST);
6441 size(4);
6442 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6443 opcode(Assembler::stf_op3);
6444 ins_encode(simple_form3_mem_reg( mem, src ) );
6445 ins_pipe(fstoreF_mem_reg);
6446 %}
6448 // Store Pointer
6449 instruct storeP(memory dst, sp_ptr_RegP src) %{
6450 match(Set dst (StoreP dst src));
6451 ins_cost(MEMORY_REF_COST);
6452 size(4);
6454 #ifndef _LP64
6455 format %{ "STW $src,$dst\t! ptr" %}
6456 opcode(Assembler::stw_op3, 0, REGP_OP);
6457 #else
6458 format %{ "STX $src,$dst\t! ptr" %}
6459 opcode(Assembler::stx_op3, 0, REGP_OP);
6460 #endif
6461 ins_encode( form3_mem_reg( dst, src ) );
6462 ins_pipe(istore_mem_spORreg);
6463 %}
6465 instruct storeP0(memory dst, immP0 src) %{
6466 match(Set dst (StoreP dst src));
6467 ins_cost(MEMORY_REF_COST);
6468 size(4);
6470 #ifndef _LP64
6471 format %{ "STW $src,$dst\t! ptr" %}
6472 opcode(Assembler::stw_op3, 0, REGP_OP);
6473 #else
6474 format %{ "STX $src,$dst\t! ptr" %}
6475 opcode(Assembler::stx_op3, 0, REGP_OP);
6476 #endif
6477 ins_encode( form3_mem_reg( dst, R_G0 ) );
6478 ins_pipe(istore_mem_zero);
6479 %}
6481 // Store Compressed Pointer
6482 instruct storeN(memory dst, iRegN src) %{
6483 match(Set dst (StoreN dst src));
6484 ins_cost(MEMORY_REF_COST);
6485 size(4);
6487 format %{ "STW $src,$dst\t! compressed ptr" %}
6488 ins_encode %{
6489 Register base = as_Register($dst$$base);
6490 Register index = as_Register($dst$$index);
6491 Register src = $src$$Register;
6492 if (index != G0) {
6493 __ stw(src, base, index);
6494 } else {
6495 __ stw(src, base, $dst$$disp);
6496 }
6497 %}
6498 ins_pipe(istore_mem_spORreg);
6499 %}
6501 instruct storeN0(memory dst, immN0 src) %{
6502 match(Set dst (StoreN dst src));
6503 ins_cost(MEMORY_REF_COST);
6504 size(4);
6506 format %{ "STW $src,$dst\t! compressed ptr" %}
6507 ins_encode %{
6508 Register base = as_Register($dst$$base);
6509 Register index = as_Register($dst$$index);
6510 if (index != G0) {
6511 __ stw(0, base, index);
6512 } else {
6513 __ stw(0, base, $dst$$disp);
6514 }
6515 %}
6516 ins_pipe(istore_mem_zero);
6517 %}
6519 // Store Double
6520 instruct storeD( memory mem, regD src) %{
6521 match(Set mem (StoreD mem src));
6522 ins_cost(MEMORY_REF_COST);
6524 size(4);
6525 format %{ "STDF $src,$mem" %}
6526 opcode(Assembler::stdf_op3);
6527 ins_encode(simple_form3_mem_reg( mem, src ) );
6528 ins_pipe(fstoreD_mem_reg);
6529 %}
6531 instruct storeD0( memory mem, immD0 src) %{
6532 match(Set mem (StoreD mem src));
6533 ins_cost(MEMORY_REF_COST);
6535 size(4);
6536 format %{ "STX $src,$mem" %}
6537 opcode(Assembler::stx_op3);
6538 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6539 ins_pipe(fstoreD_mem_zero);
6540 %}
6542 // Store Float
6543 instruct storeF( memory mem, regF src) %{
6544 match(Set mem (StoreF mem src));
6545 ins_cost(MEMORY_REF_COST);
6547 size(4);
6548 format %{ "STF $src,$mem" %}
6549 opcode(Assembler::stf_op3);
6550 ins_encode(simple_form3_mem_reg( mem, src ) );
6551 ins_pipe(fstoreF_mem_reg);
6552 %}
6554 instruct storeF0( memory mem, immF0 src) %{
6555 match(Set mem (StoreF mem src));
6556 ins_cost(MEMORY_REF_COST);
6558 size(4);
6559 format %{ "STW $src,$mem\t! storeF0" %}
6560 opcode(Assembler::stw_op3);
6561 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6562 ins_pipe(fstoreF_mem_zero);
6563 %}
6565 // Store Aligned Packed Bytes in Double register to memory
6566 instruct storeA8B(memory mem, regD src) %{
6567 match(Set mem (Store8B mem src));
6568 ins_cost(MEMORY_REF_COST);
6569 size(4);
6570 format %{ "STDF $src,$mem\t! packed8B" %}
6571 opcode(Assembler::stdf_op3);
6572 ins_encode(simple_form3_mem_reg( mem, src ) );
6573 ins_pipe(fstoreD_mem_reg);
6574 %}
6576 // Convert oop pointer into compressed form
6577 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6578 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6579 match(Set dst (EncodeP src));
6580 format %{ "encode_heap_oop $src, $dst" %}
6581 ins_encode %{
6582 __ encode_heap_oop($src$$Register, $dst$$Register);
6583 %}
6584 ins_pipe(ialu_reg);
6585 %}
6587 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6588 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6589 match(Set dst (EncodeP src));
6590 format %{ "encode_heap_oop_not_null $src, $dst" %}
6591 ins_encode %{
6592 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6593 %}
6594 ins_pipe(ialu_reg);
6595 %}
6597 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6598 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6599 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6600 match(Set dst (DecodeN src));
6601 format %{ "decode_heap_oop $src, $dst" %}
6602 ins_encode %{
6603 __ decode_heap_oop($src$$Register, $dst$$Register);
6604 %}
6605 ins_pipe(ialu_reg);
6606 %}
6608 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6609 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6610 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6611 match(Set dst (DecodeN src));
6612 format %{ "decode_heap_oop_not_null $src, $dst" %}
6613 ins_encode %{
6614 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6615 %}
6616 ins_pipe(ialu_reg);
6617 %}
6620 // Store Zero into Aligned Packed Bytes
6621 instruct storeA8B0(memory mem, immI0 zero) %{
6622 match(Set mem (Store8B mem zero));
6623 ins_cost(MEMORY_REF_COST);
6624 size(4);
6625 format %{ "STX $zero,$mem\t! packed8B" %}
6626 opcode(Assembler::stx_op3);
6627 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6628 ins_pipe(fstoreD_mem_zero);
6629 %}
6631 // Store Aligned Packed Chars/Shorts in Double register to memory
6632 instruct storeA4C(memory mem, regD src) %{
6633 match(Set mem (Store4C mem src));
6634 ins_cost(MEMORY_REF_COST);
6635 size(4);
6636 format %{ "STDF $src,$mem\t! packed4C" %}
6637 opcode(Assembler::stdf_op3);
6638 ins_encode(simple_form3_mem_reg( mem, src ) );
6639 ins_pipe(fstoreD_mem_reg);
6640 %}
6642 // Store Zero into Aligned Packed Chars/Shorts
6643 instruct storeA4C0(memory mem, immI0 zero) %{
6644 match(Set mem (Store4C mem (Replicate4C zero)));
6645 ins_cost(MEMORY_REF_COST);
6646 size(4);
6647 format %{ "STX $zero,$mem\t! packed4C" %}
6648 opcode(Assembler::stx_op3);
6649 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6650 ins_pipe(fstoreD_mem_zero);
6651 %}
6653 // Store Aligned Packed Ints in Double register to memory
6654 instruct storeA2I(memory mem, regD src) %{
6655 match(Set mem (Store2I mem src));
6656 ins_cost(MEMORY_REF_COST);
6657 size(4);
6658 format %{ "STDF $src,$mem\t! packed2I" %}
6659 opcode(Assembler::stdf_op3);
6660 ins_encode(simple_form3_mem_reg( mem, src ) );
6661 ins_pipe(fstoreD_mem_reg);
6662 %}
6664 // Store Zero into Aligned Packed Ints
6665 instruct storeA2I0(memory mem, immI0 zero) %{
6666 match(Set mem (Store2I mem zero));
6667 ins_cost(MEMORY_REF_COST);
6668 size(4);
6669 format %{ "STX $zero,$mem\t! packed2I" %}
6670 opcode(Assembler::stx_op3);
6671 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6672 ins_pipe(fstoreD_mem_zero);
6673 %}
6676 //----------MemBar Instructions-----------------------------------------------
6677 // Memory barrier flavors
6679 instruct membar_acquire() %{
6680 match(MemBarAcquire);
6681 ins_cost(4*MEMORY_REF_COST);
6683 size(0);
6684 format %{ "MEMBAR-acquire" %}
6685 ins_encode( enc_membar_acquire );
6686 ins_pipe(long_memory_op);
6687 %}
6689 instruct membar_acquire_lock() %{
6690 match(MemBarAcquireLock);
6691 ins_cost(0);
6693 size(0);
6694 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6695 ins_encode( );
6696 ins_pipe(empty);
6697 %}
6699 instruct membar_release() %{
6700 match(MemBarRelease);
6701 ins_cost(4*MEMORY_REF_COST);
6703 size(0);
6704 format %{ "MEMBAR-release" %}
6705 ins_encode( enc_membar_release );
6706 ins_pipe(long_memory_op);
6707 %}
6709 instruct membar_release_lock() %{
6710 match(MemBarReleaseLock);
6711 ins_cost(0);
6713 size(0);
6714 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6715 ins_encode( );
6716 ins_pipe(empty);
6717 %}
6719 instruct membar_volatile() %{
6720 match(MemBarVolatile);
6721 ins_cost(4*MEMORY_REF_COST);
6723 size(4);
6724 format %{ "MEMBAR-volatile" %}
6725 ins_encode( enc_membar_volatile );
6726 ins_pipe(long_memory_op);
6727 %}
6729 instruct unnecessary_membar_volatile() %{
6730 match(MemBarVolatile);
6731 predicate(Matcher::post_store_load_barrier(n));
6732 ins_cost(0);
6734 size(0);
6735 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6736 ins_encode( );
6737 ins_pipe(empty);
6738 %}
6740 //----------Register Move Instructions-----------------------------------------
6741 instruct roundDouble_nop(regD dst) %{
6742 match(Set dst (RoundDouble dst));
6743 ins_cost(0);
6744 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6745 ins_encode( );
6746 ins_pipe(empty);
6747 %}
6750 instruct roundFloat_nop(regF dst) %{
6751 match(Set dst (RoundFloat dst));
6752 ins_cost(0);
6753 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6754 ins_encode( );
6755 ins_pipe(empty);
6756 %}
6759 // Cast Index to Pointer for unsafe natives
6760 instruct castX2P(iRegX src, iRegP dst) %{
6761 match(Set dst (CastX2P src));
6763 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6764 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6765 ins_pipe(ialu_reg);
6766 %}
6768 // Cast Pointer to Index for unsafe natives
6769 instruct castP2X(iRegP src, iRegX dst) %{
6770 match(Set dst (CastP2X src));
6772 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6773 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6774 ins_pipe(ialu_reg);
6775 %}
6777 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6778 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6779 match(Set stkSlot src); // chain rule
6780 ins_cost(MEMORY_REF_COST);
6781 format %{ "STDF $src,$stkSlot\t!stk" %}
6782 opcode(Assembler::stdf_op3);
6783 ins_encode(simple_form3_mem_reg(stkSlot, src));
6784 ins_pipe(fstoreD_stk_reg);
6785 %}
6787 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6788 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6789 match(Set dst stkSlot); // chain rule
6790 ins_cost(MEMORY_REF_COST);
6791 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6792 opcode(Assembler::lddf_op3);
6793 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6794 ins_pipe(floadD_stk);
6795 %}
6797 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6798 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6799 match(Set stkSlot src); // chain rule
6800 ins_cost(MEMORY_REF_COST);
6801 format %{ "STF $src,$stkSlot\t!stk" %}
6802 opcode(Assembler::stf_op3);
6803 ins_encode(simple_form3_mem_reg(stkSlot, src));
6804 ins_pipe(fstoreF_stk_reg);
6805 %}
6807 //----------Conditional Move---------------------------------------------------
6808 // Conditional move
6809 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6810 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6811 ins_cost(150);
6812 format %{ "MOV$cmp $pcc,$src,$dst" %}
6813 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6814 ins_pipe(ialu_reg);
6815 %}
6817 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6818 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6819 ins_cost(140);
6820 format %{ "MOV$cmp $pcc,$src,$dst" %}
6821 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6822 ins_pipe(ialu_imm);
6823 %}
6825 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6826 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6827 ins_cost(150);
6828 size(4);
6829 format %{ "MOV$cmp $icc,$src,$dst" %}
6830 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6831 ins_pipe(ialu_reg);
6832 %}
6834 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6835 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6836 ins_cost(140);
6837 size(4);
6838 format %{ "MOV$cmp $icc,$src,$dst" %}
6839 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6840 ins_pipe(ialu_imm);
6841 %}
6843 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6844 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6845 ins_cost(150);
6846 size(4);
6847 format %{ "MOV$cmp $icc,$src,$dst" %}
6848 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6849 ins_pipe(ialu_reg);
6850 %}
6852 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6853 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6854 ins_cost(140);
6855 size(4);
6856 format %{ "MOV$cmp $icc,$src,$dst" %}
6857 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6858 ins_pipe(ialu_imm);
6859 %}
6861 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6862 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6863 ins_cost(150);
6864 size(4);
6865 format %{ "MOV$cmp $fcc,$src,$dst" %}
6866 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6867 ins_pipe(ialu_reg);
6868 %}
6870 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6871 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6872 ins_cost(140);
6873 size(4);
6874 format %{ "MOV$cmp $fcc,$src,$dst" %}
6875 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6876 ins_pipe(ialu_imm);
6877 %}
6879 // Conditional move for RegN. Only cmov(reg,reg).
6880 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6881 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6882 ins_cost(150);
6883 format %{ "MOV$cmp $pcc,$src,$dst" %}
6884 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6885 ins_pipe(ialu_reg);
6886 %}
6888 // This instruction also works with CmpN so we don't need cmovNN_reg.
6889 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6890 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6891 ins_cost(150);
6892 size(4);
6893 format %{ "MOV$cmp $icc,$src,$dst" %}
6894 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6895 ins_pipe(ialu_reg);
6896 %}
6898 // This instruction also works with CmpN so we don't need cmovNN_reg.
6899 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6900 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6901 ins_cost(150);
6902 size(4);
6903 format %{ "MOV$cmp $icc,$src,$dst" %}
6904 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6905 ins_pipe(ialu_reg);
6906 %}
6908 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6909 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6910 ins_cost(150);
6911 size(4);
6912 format %{ "MOV$cmp $fcc,$src,$dst" %}
6913 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6914 ins_pipe(ialu_reg);
6915 %}
6917 // Conditional move
6918 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6919 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6920 ins_cost(150);
6921 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6922 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6923 ins_pipe(ialu_reg);
6924 %}
6926 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6927 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6928 ins_cost(140);
6929 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6930 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6931 ins_pipe(ialu_imm);
6932 %}
6934 // This instruction also works with CmpN so we don't need cmovPN_reg.
6935 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6936 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6937 ins_cost(150);
6939 size(4);
6940 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6941 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6942 ins_pipe(ialu_reg);
6943 %}
6945 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6946 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6947 ins_cost(150);
6949 size(4);
6950 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6951 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6952 ins_pipe(ialu_reg);
6953 %}
6955 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6956 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6957 ins_cost(140);
6959 size(4);
6960 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6961 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6962 ins_pipe(ialu_imm);
6963 %}
6965 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6966 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6967 ins_cost(140);
6969 size(4);
6970 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6971 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6972 ins_pipe(ialu_imm);
6973 %}
6975 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6976 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6977 ins_cost(150);
6978 size(4);
6979 format %{ "MOV$cmp $fcc,$src,$dst" %}
6980 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6981 ins_pipe(ialu_imm);
6982 %}
6984 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6985 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6986 ins_cost(140);
6987 size(4);
6988 format %{ "MOV$cmp $fcc,$src,$dst" %}
6989 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6990 ins_pipe(ialu_imm);
6991 %}
6993 // Conditional move
6994 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6995 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6996 ins_cost(150);
6997 opcode(0x101);
6998 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6999 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7000 ins_pipe(int_conditional_float_move);
7001 %}
7003 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7004 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7005 ins_cost(150);
7007 size(4);
7008 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7009 opcode(0x101);
7010 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7011 ins_pipe(int_conditional_float_move);
7012 %}
7014 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7015 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7016 ins_cost(150);
7018 size(4);
7019 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7020 opcode(0x101);
7021 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7022 ins_pipe(int_conditional_float_move);
7023 %}
7025 // Conditional move,
7026 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7027 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7028 ins_cost(150);
7029 size(4);
7030 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7031 opcode(0x1);
7032 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7033 ins_pipe(int_conditional_double_move);
7034 %}
7036 // Conditional move
7037 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7038 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7039 ins_cost(150);
7040 size(4);
7041 opcode(0x102);
7042 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7043 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7044 ins_pipe(int_conditional_double_move);
7045 %}
7047 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7048 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7049 ins_cost(150);
7051 size(4);
7052 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7053 opcode(0x102);
7054 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7055 ins_pipe(int_conditional_double_move);
7056 %}
7058 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7059 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7060 ins_cost(150);
7062 size(4);
7063 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7064 opcode(0x102);
7065 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7066 ins_pipe(int_conditional_double_move);
7067 %}
7069 // Conditional move,
7070 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7071 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7072 ins_cost(150);
7073 size(4);
7074 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7075 opcode(0x2);
7076 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7077 ins_pipe(int_conditional_double_move);
7078 %}
7080 // Conditional move
7081 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7082 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7083 ins_cost(150);
7084 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7085 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7086 ins_pipe(ialu_reg);
7087 %}
7089 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7090 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7091 ins_cost(140);
7092 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7093 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7094 ins_pipe(ialu_imm);
7095 %}
7097 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7098 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7099 ins_cost(150);
7101 size(4);
7102 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7103 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7104 ins_pipe(ialu_reg);
7105 %}
7108 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7109 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7110 ins_cost(150);
7112 size(4);
7113 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7114 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7115 ins_pipe(ialu_reg);
7116 %}
7119 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7120 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7121 ins_cost(150);
7123 size(4);
7124 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7125 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7126 ins_pipe(ialu_reg);
7127 %}
7131 //----------OS and Locking Instructions----------------------------------------
7133 // This name is KNOWN by the ADLC and cannot be changed.
7134 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7135 // for this guy.
7136 instruct tlsLoadP(g2RegP dst) %{
7137 match(Set dst (ThreadLocal));
7139 size(0);
7140 ins_cost(0);
7141 format %{ "# TLS is in G2" %}
7142 ins_encode( /*empty encoding*/ );
7143 ins_pipe(ialu_none);
7144 %}
7146 instruct checkCastPP( iRegP dst ) %{
7147 match(Set dst (CheckCastPP dst));
7149 size(0);
7150 format %{ "# checkcastPP of $dst" %}
7151 ins_encode( /*empty encoding*/ );
7152 ins_pipe(empty);
7153 %}
7156 instruct castPP( iRegP dst ) %{
7157 match(Set dst (CastPP dst));
7158 format %{ "# castPP of $dst" %}
7159 ins_encode( /*empty encoding*/ );
7160 ins_pipe(empty);
7161 %}
7163 instruct castII( iRegI dst ) %{
7164 match(Set dst (CastII dst));
7165 format %{ "# castII of $dst" %}
7166 ins_encode( /*empty encoding*/ );
7167 ins_cost(0);
7168 ins_pipe(empty);
7169 %}
7171 //----------Arithmetic Instructions--------------------------------------------
7172 // Addition Instructions
7173 // Register Addition
7174 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7175 match(Set dst (AddI src1 src2));
7177 size(4);
7178 format %{ "ADD $src1,$src2,$dst" %}
7179 ins_encode %{
7180 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7181 %}
7182 ins_pipe(ialu_reg_reg);
7183 %}
7185 // Immediate Addition
7186 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7187 match(Set dst (AddI src1 src2));
7189 size(4);
7190 format %{ "ADD $src1,$src2,$dst" %}
7191 opcode(Assembler::add_op3, Assembler::arith_op);
7192 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7193 ins_pipe(ialu_reg_imm);
7194 %}
7196 // Pointer Register Addition
7197 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7198 match(Set dst (AddP src1 src2));
7200 size(4);
7201 format %{ "ADD $src1,$src2,$dst" %}
7202 opcode(Assembler::add_op3, Assembler::arith_op);
7203 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7204 ins_pipe(ialu_reg_reg);
7205 %}
7207 // Pointer Immediate Addition
7208 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7209 match(Set dst (AddP src1 src2));
7211 size(4);
7212 format %{ "ADD $src1,$src2,$dst" %}
7213 opcode(Assembler::add_op3, Assembler::arith_op);
7214 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7215 ins_pipe(ialu_reg_imm);
7216 %}
7218 // Long Addition
7219 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7220 match(Set dst (AddL src1 src2));
7222 size(4);
7223 format %{ "ADD $src1,$src2,$dst\t! long" %}
7224 opcode(Assembler::add_op3, Assembler::arith_op);
7225 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7226 ins_pipe(ialu_reg_reg);
7227 %}
7229 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7230 match(Set dst (AddL src1 con));
7232 size(4);
7233 format %{ "ADD $src1,$con,$dst" %}
7234 opcode(Assembler::add_op3, Assembler::arith_op);
7235 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7236 ins_pipe(ialu_reg_imm);
7237 %}
7239 //----------Conditional_store--------------------------------------------------
7240 // Conditional-store of the updated heap-top.
7241 // Used during allocation of the shared heap.
7242 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7244 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7245 instruct loadPLocked(iRegP dst, memory mem) %{
7246 match(Set dst (LoadPLocked mem));
7247 ins_cost(MEMORY_REF_COST);
7249 #ifndef _LP64
7250 size(4);
7251 format %{ "LDUW $mem,$dst\t! ptr" %}
7252 opcode(Assembler::lduw_op3, 0, REGP_OP);
7253 #else
7254 format %{ "LDX $mem,$dst\t! ptr" %}
7255 opcode(Assembler::ldx_op3, 0, REGP_OP);
7256 #endif
7257 ins_encode( form3_mem_reg( mem, dst ) );
7258 ins_pipe(iload_mem);
7259 %}
7261 // LoadL-locked. Same as a regular long load when used with a compare-swap
7262 instruct loadLLocked(iRegL dst, memory mem) %{
7263 match(Set dst (LoadLLocked mem));
7264 ins_cost(MEMORY_REF_COST);
7265 size(4);
7266 format %{ "LDX $mem,$dst\t! long" %}
7267 opcode(Assembler::ldx_op3);
7268 ins_encode(simple_form3_mem_reg( mem, dst ) );
7269 ins_pipe(iload_mem);
7270 %}
7272 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7273 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7274 effect( KILL newval );
7275 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7276 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7277 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7278 ins_pipe( long_memory_op );
7279 %}
7281 // Conditional-store of an int value.
7282 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7283 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7284 effect( KILL newval );
7285 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7286 "CMP $oldval,$newval\t\t! See if we made progress" %}
7287 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7288 ins_pipe( long_memory_op );
7289 %}
7291 // Conditional-store of a long value.
7292 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7293 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7294 effect( KILL newval );
7295 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7296 "CMP $oldval,$newval\t\t! See if we made progress" %}
7297 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7298 ins_pipe( long_memory_op );
7299 %}
7301 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7303 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7304 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7305 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7306 format %{
7307 "MOV $newval,O7\n\t"
7308 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7309 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7310 "MOV 1,$res\n\t"
7311 "MOVne xcc,R_G0,$res"
7312 %}
7313 ins_encode( enc_casx(mem_ptr, oldval, newval),
7314 enc_lflags_ne_to_boolean(res) );
7315 ins_pipe( long_memory_op );
7316 %}
7319 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7320 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7321 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7322 format %{
7323 "MOV $newval,O7\n\t"
7324 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7325 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7326 "MOV 1,$res\n\t"
7327 "MOVne icc,R_G0,$res"
7328 %}
7329 ins_encode( enc_casi(mem_ptr, oldval, newval),
7330 enc_iflags_ne_to_boolean(res) );
7331 ins_pipe( long_memory_op );
7332 %}
7334 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7335 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7336 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7337 format %{
7338 "MOV $newval,O7\n\t"
7339 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7340 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7341 "MOV 1,$res\n\t"
7342 "MOVne xcc,R_G0,$res"
7343 %}
7344 #ifdef _LP64
7345 ins_encode( enc_casx(mem_ptr, oldval, newval),
7346 enc_lflags_ne_to_boolean(res) );
7347 #else
7348 ins_encode( enc_casi(mem_ptr, oldval, newval),
7349 enc_iflags_ne_to_boolean(res) );
7350 #endif
7351 ins_pipe( long_memory_op );
7352 %}
7354 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7355 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7356 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7357 format %{
7358 "MOV $newval,O7\n\t"
7359 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7360 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7361 "MOV 1,$res\n\t"
7362 "MOVne icc,R_G0,$res"
7363 %}
7364 ins_encode( enc_casi(mem_ptr, oldval, newval),
7365 enc_iflags_ne_to_boolean(res) );
7366 ins_pipe( long_memory_op );
7367 %}
7369 //---------------------
7370 // Subtraction Instructions
7371 // Register Subtraction
7372 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7373 match(Set dst (SubI src1 src2));
7375 size(4);
7376 format %{ "SUB $src1,$src2,$dst" %}
7377 opcode(Assembler::sub_op3, Assembler::arith_op);
7378 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7379 ins_pipe(ialu_reg_reg);
7380 %}
7382 // Immediate Subtraction
7383 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7384 match(Set dst (SubI src1 src2));
7386 size(4);
7387 format %{ "SUB $src1,$src2,$dst" %}
7388 opcode(Assembler::sub_op3, Assembler::arith_op);
7389 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7390 ins_pipe(ialu_reg_imm);
7391 %}
7393 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7394 match(Set dst (SubI zero src2));
7396 size(4);
7397 format %{ "NEG $src2,$dst" %}
7398 opcode(Assembler::sub_op3, Assembler::arith_op);
7399 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7400 ins_pipe(ialu_zero_reg);
7401 %}
7403 // Long subtraction
7404 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7405 match(Set dst (SubL src1 src2));
7407 size(4);
7408 format %{ "SUB $src1,$src2,$dst\t! long" %}
7409 opcode(Assembler::sub_op3, Assembler::arith_op);
7410 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7411 ins_pipe(ialu_reg_reg);
7412 %}
7414 // Immediate Subtraction
7415 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7416 match(Set dst (SubL src1 con));
7418 size(4);
7419 format %{ "SUB $src1,$con,$dst\t! long" %}
7420 opcode(Assembler::sub_op3, Assembler::arith_op);
7421 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7422 ins_pipe(ialu_reg_imm);
7423 %}
7425 // Long negation
7426 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7427 match(Set dst (SubL zero src2));
7429 size(4);
7430 format %{ "NEG $src2,$dst\t! long" %}
7431 opcode(Assembler::sub_op3, Assembler::arith_op);
7432 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7433 ins_pipe(ialu_zero_reg);
7434 %}
7436 // Multiplication Instructions
7437 // Integer Multiplication
7438 // Register Multiplication
7439 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7440 match(Set dst (MulI src1 src2));
7442 size(4);
7443 format %{ "MULX $src1,$src2,$dst" %}
7444 opcode(Assembler::mulx_op3, Assembler::arith_op);
7445 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7446 ins_pipe(imul_reg_reg);
7447 %}
7449 // Immediate Multiplication
7450 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7451 match(Set dst (MulI src1 src2));
7453 size(4);
7454 format %{ "MULX $src1,$src2,$dst" %}
7455 opcode(Assembler::mulx_op3, Assembler::arith_op);
7456 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7457 ins_pipe(imul_reg_imm);
7458 %}
7460 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7461 match(Set dst (MulL src1 src2));
7462 ins_cost(DEFAULT_COST * 5);
7463 size(4);
7464 format %{ "MULX $src1,$src2,$dst\t! long" %}
7465 opcode(Assembler::mulx_op3, Assembler::arith_op);
7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7467 ins_pipe(mulL_reg_reg);
7468 %}
7470 // Immediate Multiplication
7471 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7472 match(Set dst (MulL src1 src2));
7473 ins_cost(DEFAULT_COST * 5);
7474 size(4);
7475 format %{ "MULX $src1,$src2,$dst" %}
7476 opcode(Assembler::mulx_op3, Assembler::arith_op);
7477 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7478 ins_pipe(mulL_reg_imm);
7479 %}
7481 // Integer Division
7482 // Register Division
7483 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7484 match(Set dst (DivI src1 src2));
7485 ins_cost((2+71)*DEFAULT_COST);
7487 format %{ "SRA $src2,0,$src2\n\t"
7488 "SRA $src1,0,$src1\n\t"
7489 "SDIVX $src1,$src2,$dst" %}
7490 ins_encode( idiv_reg( src1, src2, dst ) );
7491 ins_pipe(sdiv_reg_reg);
7492 %}
7494 // Immediate Division
7495 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7496 match(Set dst (DivI src1 src2));
7497 ins_cost((2+71)*DEFAULT_COST);
7499 format %{ "SRA $src1,0,$src1\n\t"
7500 "SDIVX $src1,$src2,$dst" %}
7501 ins_encode( idiv_imm( src1, src2, dst ) );
7502 ins_pipe(sdiv_reg_imm);
7503 %}
7505 //----------Div-By-10-Expansion------------------------------------------------
7506 // Extract hi bits of a 32x32->64 bit multiply.
7507 // Expand rule only, not matched
7508 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7509 effect( DEF dst, USE src1, USE src2 );
7510 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7511 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7512 ins_encode( enc_mul_hi(dst,src1,src2));
7513 ins_pipe(sdiv_reg_reg);
7514 %}
7516 // Magic constant, reciprocal of 10
7517 instruct loadConI_x66666667(iRegIsafe dst) %{
7518 effect( DEF dst );
7520 size(8);
7521 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7522 ins_encode( Set32(0x66666667, dst) );
7523 ins_pipe(ialu_hi_lo_reg);
7524 %}
7526 // Register Shift Right Arithmetic Long by 32-63
7527 instruct sra_31( iRegI dst, iRegI src ) %{
7528 effect( DEF dst, USE src );
7529 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7530 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7531 ins_pipe(ialu_reg_reg);
7532 %}
7534 // Arithmetic Shift Right by 8-bit immediate
7535 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7536 effect( DEF dst, USE src );
7537 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7538 opcode(Assembler::sra_op3, Assembler::arith_op);
7539 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7540 ins_pipe(ialu_reg_imm);
7541 %}
7543 // Integer DIV with 10
7544 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7545 match(Set dst (DivI src div));
7546 ins_cost((6+6)*DEFAULT_COST);
7547 expand %{
7548 iRegIsafe tmp1; // Killed temps;
7549 iRegIsafe tmp2; // Killed temps;
7550 iRegI tmp3; // Killed temps;
7551 iRegI tmp4; // Killed temps;
7552 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7553 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7554 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7555 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7556 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7557 %}
7558 %}
7560 // Register Long Division
7561 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7562 match(Set dst (DivL src1 src2));
7563 ins_cost(DEFAULT_COST*71);
7564 size(4);
7565 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7566 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7567 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7568 ins_pipe(divL_reg_reg);
7569 %}
7571 // Register Long Division
7572 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7573 match(Set dst (DivL src1 src2));
7574 ins_cost(DEFAULT_COST*71);
7575 size(4);
7576 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7577 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7578 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7579 ins_pipe(divL_reg_imm);
7580 %}
7582 // Integer Remainder
7583 // Register Remainder
7584 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7585 match(Set dst (ModI src1 src2));
7586 effect( KILL ccr, KILL temp);
7588 format %{ "SREM $src1,$src2,$dst" %}
7589 ins_encode( irem_reg(src1, src2, dst, temp) );
7590 ins_pipe(sdiv_reg_reg);
7591 %}
7593 // Immediate Remainder
7594 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7595 match(Set dst (ModI src1 src2));
7596 effect( KILL ccr, KILL temp);
7598 format %{ "SREM $src1,$src2,$dst" %}
7599 ins_encode( irem_imm(src1, src2, dst, temp) );
7600 ins_pipe(sdiv_reg_imm);
7601 %}
7603 // Register Long Remainder
7604 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7605 effect(DEF dst, USE src1, USE src2);
7606 size(4);
7607 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7608 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7609 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7610 ins_pipe(divL_reg_reg);
7611 %}
7613 // Register Long Division
7614 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7615 effect(DEF dst, USE src1, USE src2);
7616 size(4);
7617 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7618 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7619 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7620 ins_pipe(divL_reg_imm);
7621 %}
7623 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7624 effect(DEF dst, USE src1, USE src2);
7625 size(4);
7626 format %{ "MULX $src1,$src2,$dst\t! long" %}
7627 opcode(Assembler::mulx_op3, Assembler::arith_op);
7628 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7629 ins_pipe(mulL_reg_reg);
7630 %}
7632 // Immediate Multiplication
7633 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7634 effect(DEF dst, USE src1, USE src2);
7635 size(4);
7636 format %{ "MULX $src1,$src2,$dst" %}
7637 opcode(Assembler::mulx_op3, Assembler::arith_op);
7638 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7639 ins_pipe(mulL_reg_imm);
7640 %}
7642 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7643 effect(DEF dst, USE src1, USE src2);
7644 size(4);
7645 format %{ "SUB $src1,$src2,$dst\t! long" %}
7646 opcode(Assembler::sub_op3, Assembler::arith_op);
7647 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7648 ins_pipe(ialu_reg_reg);
7649 %}
7651 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7652 effect(DEF dst, USE src1, USE src2);
7653 size(4);
7654 format %{ "SUB $src1,$src2,$dst\t! long" %}
7655 opcode(Assembler::sub_op3, Assembler::arith_op);
7656 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7657 ins_pipe(ialu_reg_reg);
7658 %}
7660 // Register Long Remainder
7661 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7662 match(Set dst (ModL src1 src2));
7663 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7664 expand %{
7665 iRegL tmp1;
7666 iRegL tmp2;
7667 divL_reg_reg_1(tmp1, src1, src2);
7668 mulL_reg_reg_1(tmp2, tmp1, src2);
7669 subL_reg_reg_1(dst, src1, tmp2);
7670 %}
7671 %}
7673 // Register Long Remainder
7674 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7675 match(Set dst (ModL src1 src2));
7676 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7677 expand %{
7678 iRegL tmp1;
7679 iRegL tmp2;
7680 divL_reg_imm13_1(tmp1, src1, src2);
7681 mulL_reg_imm13_1(tmp2, tmp1, src2);
7682 subL_reg_reg_2 (dst, src1, tmp2);
7683 %}
7684 %}
7686 // Integer Shift Instructions
7687 // Register Shift Left
7688 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7689 match(Set dst (LShiftI src1 src2));
7691 size(4);
7692 format %{ "SLL $src1,$src2,$dst" %}
7693 opcode(Assembler::sll_op3, Assembler::arith_op);
7694 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7695 ins_pipe(ialu_reg_reg);
7696 %}
7698 // Register Shift Left Immediate
7699 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7700 match(Set dst (LShiftI src1 src2));
7702 size(4);
7703 format %{ "SLL $src1,$src2,$dst" %}
7704 opcode(Assembler::sll_op3, Assembler::arith_op);
7705 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7706 ins_pipe(ialu_reg_imm);
7707 %}
7709 // Register Shift Left
7710 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7711 match(Set dst (LShiftL src1 src2));
7713 size(4);
7714 format %{ "SLLX $src1,$src2,$dst" %}
7715 opcode(Assembler::sllx_op3, Assembler::arith_op);
7716 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7717 ins_pipe(ialu_reg_reg);
7718 %}
7720 // Register Shift Left Immediate
7721 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7722 match(Set dst (LShiftL src1 src2));
7724 size(4);
7725 format %{ "SLLX $src1,$src2,$dst" %}
7726 opcode(Assembler::sllx_op3, Assembler::arith_op);
7727 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7728 ins_pipe(ialu_reg_imm);
7729 %}
7731 // Register Arithmetic Shift Right
7732 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7733 match(Set dst (RShiftI src1 src2));
7734 size(4);
7735 format %{ "SRA $src1,$src2,$dst" %}
7736 opcode(Assembler::sra_op3, Assembler::arith_op);
7737 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7738 ins_pipe(ialu_reg_reg);
7739 %}
7741 // Register Arithmetic Shift Right Immediate
7742 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7743 match(Set dst (RShiftI src1 src2));
7745 size(4);
7746 format %{ "SRA $src1,$src2,$dst" %}
7747 opcode(Assembler::sra_op3, Assembler::arith_op);
7748 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7749 ins_pipe(ialu_reg_imm);
7750 %}
7752 // Register Shift Right Arithmatic Long
7753 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7754 match(Set dst (RShiftL src1 src2));
7756 size(4);
7757 format %{ "SRAX $src1,$src2,$dst" %}
7758 opcode(Assembler::srax_op3, Assembler::arith_op);
7759 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7760 ins_pipe(ialu_reg_reg);
7761 %}
7763 // Register Shift Left Immediate
7764 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7765 match(Set dst (RShiftL src1 src2));
7767 size(4);
7768 format %{ "SRAX $src1,$src2,$dst" %}
7769 opcode(Assembler::srax_op3, Assembler::arith_op);
7770 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7771 ins_pipe(ialu_reg_imm);
7772 %}
7774 // Register Shift Right
7775 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7776 match(Set dst (URShiftI src1 src2));
7778 size(4);
7779 format %{ "SRL $src1,$src2,$dst" %}
7780 opcode(Assembler::srl_op3, Assembler::arith_op);
7781 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7782 ins_pipe(ialu_reg_reg);
7783 %}
7785 // Register Shift Right Immediate
7786 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7787 match(Set dst (URShiftI src1 src2));
7789 size(4);
7790 format %{ "SRL $src1,$src2,$dst" %}
7791 opcode(Assembler::srl_op3, Assembler::arith_op);
7792 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7793 ins_pipe(ialu_reg_imm);
7794 %}
7796 // Register Shift Right
7797 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7798 match(Set dst (URShiftL src1 src2));
7800 size(4);
7801 format %{ "SRLX $src1,$src2,$dst" %}
7802 opcode(Assembler::srlx_op3, Assembler::arith_op);
7803 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7804 ins_pipe(ialu_reg_reg);
7805 %}
7807 // Register Shift Right Immediate
7808 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7809 match(Set dst (URShiftL src1 src2));
7811 size(4);
7812 format %{ "SRLX $src1,$src2,$dst" %}
7813 opcode(Assembler::srlx_op3, Assembler::arith_op);
7814 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7815 ins_pipe(ialu_reg_imm);
7816 %}
7818 // Register Shift Right Immediate with a CastP2X
7819 #ifdef _LP64
7820 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7821 match(Set dst (URShiftL (CastP2X src1) src2));
7822 size(4);
7823 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7824 opcode(Assembler::srlx_op3, Assembler::arith_op);
7825 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7826 ins_pipe(ialu_reg_imm);
7827 %}
7828 #else
7829 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7830 match(Set dst (URShiftI (CastP2X src1) src2));
7831 size(4);
7832 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7833 opcode(Assembler::srl_op3, Assembler::arith_op);
7834 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7835 ins_pipe(ialu_reg_imm);
7836 %}
7837 #endif
7840 //----------Floating Point Arithmetic Instructions-----------------------------
7842 // Add float single precision
7843 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7844 match(Set dst (AddF src1 src2));
7846 size(4);
7847 format %{ "FADDS $src1,$src2,$dst" %}
7848 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7849 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7850 ins_pipe(faddF_reg_reg);
7851 %}
7853 // Add float double precision
7854 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7855 match(Set dst (AddD src1 src2));
7857 size(4);
7858 format %{ "FADDD $src1,$src2,$dst" %}
7859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7860 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7861 ins_pipe(faddD_reg_reg);
7862 %}
7864 // Sub float single precision
7865 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7866 match(Set dst (SubF src1 src2));
7868 size(4);
7869 format %{ "FSUBS $src1,$src2,$dst" %}
7870 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7871 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7872 ins_pipe(faddF_reg_reg);
7873 %}
7875 // Sub float double precision
7876 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7877 match(Set dst (SubD src1 src2));
7879 size(4);
7880 format %{ "FSUBD $src1,$src2,$dst" %}
7881 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7882 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7883 ins_pipe(faddD_reg_reg);
7884 %}
7886 // Mul float single precision
7887 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7888 match(Set dst (MulF src1 src2));
7890 size(4);
7891 format %{ "FMULS $src1,$src2,$dst" %}
7892 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7893 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7894 ins_pipe(fmulF_reg_reg);
7895 %}
7897 // Mul float double precision
7898 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7899 match(Set dst (MulD src1 src2));
7901 size(4);
7902 format %{ "FMULD $src1,$src2,$dst" %}
7903 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7904 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7905 ins_pipe(fmulD_reg_reg);
7906 %}
7908 // Div float single precision
7909 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7910 match(Set dst (DivF src1 src2));
7912 size(4);
7913 format %{ "FDIVS $src1,$src2,$dst" %}
7914 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7915 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7916 ins_pipe(fdivF_reg_reg);
7917 %}
7919 // Div float double precision
7920 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7921 match(Set dst (DivD src1 src2));
7923 size(4);
7924 format %{ "FDIVD $src1,$src2,$dst" %}
7925 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7926 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7927 ins_pipe(fdivD_reg_reg);
7928 %}
7930 // Absolute float double precision
7931 instruct absD_reg(regD dst, regD src) %{
7932 match(Set dst (AbsD src));
7934 format %{ "FABSd $src,$dst" %}
7935 ins_encode(fabsd(dst, src));
7936 ins_pipe(faddD_reg);
7937 %}
7939 // Absolute float single precision
7940 instruct absF_reg(regF dst, regF src) %{
7941 match(Set dst (AbsF src));
7943 format %{ "FABSs $src,$dst" %}
7944 ins_encode(fabss(dst, src));
7945 ins_pipe(faddF_reg);
7946 %}
7948 instruct negF_reg(regF dst, regF src) %{
7949 match(Set dst (NegF src));
7951 size(4);
7952 format %{ "FNEGs $src,$dst" %}
7953 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7954 ins_encode(form3_opf_rs2F_rdF(src, dst));
7955 ins_pipe(faddF_reg);
7956 %}
7958 instruct negD_reg(regD dst, regD src) %{
7959 match(Set dst (NegD src));
7961 format %{ "FNEGd $src,$dst" %}
7962 ins_encode(fnegd(dst, src));
7963 ins_pipe(faddD_reg);
7964 %}
7966 // Sqrt float double precision
7967 instruct sqrtF_reg_reg(regF dst, regF src) %{
7968 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7970 size(4);
7971 format %{ "FSQRTS $src,$dst" %}
7972 ins_encode(fsqrts(dst, src));
7973 ins_pipe(fdivF_reg_reg);
7974 %}
7976 // Sqrt float double precision
7977 instruct sqrtD_reg_reg(regD dst, regD src) %{
7978 match(Set dst (SqrtD src));
7980 size(4);
7981 format %{ "FSQRTD $src,$dst" %}
7982 ins_encode(fsqrtd(dst, src));
7983 ins_pipe(fdivD_reg_reg);
7984 %}
7986 //----------Logical Instructions-----------------------------------------------
7987 // And Instructions
7988 // Register And
7989 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7990 match(Set dst (AndI src1 src2));
7992 size(4);
7993 format %{ "AND $src1,$src2,$dst" %}
7994 opcode(Assembler::and_op3, Assembler::arith_op);
7995 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7996 ins_pipe(ialu_reg_reg);
7997 %}
7999 // Immediate And
8000 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8001 match(Set dst (AndI src1 src2));
8003 size(4);
8004 format %{ "AND $src1,$src2,$dst" %}
8005 opcode(Assembler::and_op3, Assembler::arith_op);
8006 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8007 ins_pipe(ialu_reg_imm);
8008 %}
8010 // Register And Long
8011 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8012 match(Set dst (AndL src1 src2));
8014 ins_cost(DEFAULT_COST);
8015 size(4);
8016 format %{ "AND $src1,$src2,$dst\t! long" %}
8017 opcode(Assembler::and_op3, Assembler::arith_op);
8018 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8019 ins_pipe(ialu_reg_reg);
8020 %}
8022 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8023 match(Set dst (AndL src1 con));
8025 ins_cost(DEFAULT_COST);
8026 size(4);
8027 format %{ "AND $src1,$con,$dst\t! long" %}
8028 opcode(Assembler::and_op3, Assembler::arith_op);
8029 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8030 ins_pipe(ialu_reg_imm);
8031 %}
8033 // Or Instructions
8034 // Register Or
8035 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8036 match(Set dst (OrI src1 src2));
8038 size(4);
8039 format %{ "OR $src1,$src2,$dst" %}
8040 opcode(Assembler::or_op3, Assembler::arith_op);
8041 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8042 ins_pipe(ialu_reg_reg);
8043 %}
8045 // Immediate Or
8046 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8047 match(Set dst (OrI src1 src2));
8049 size(4);
8050 format %{ "OR $src1,$src2,$dst" %}
8051 opcode(Assembler::or_op3, Assembler::arith_op);
8052 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8053 ins_pipe(ialu_reg_imm);
8054 %}
8056 // Register Or Long
8057 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8058 match(Set dst (OrL src1 src2));
8060 ins_cost(DEFAULT_COST);
8061 size(4);
8062 format %{ "OR $src1,$src2,$dst\t! long" %}
8063 opcode(Assembler::or_op3, Assembler::arith_op);
8064 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8065 ins_pipe(ialu_reg_reg);
8066 %}
8068 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8069 match(Set dst (OrL src1 con));
8070 ins_cost(DEFAULT_COST*2);
8072 ins_cost(DEFAULT_COST);
8073 size(4);
8074 format %{ "OR $src1,$con,$dst\t! long" %}
8075 opcode(Assembler::or_op3, Assembler::arith_op);
8076 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8077 ins_pipe(ialu_reg_imm);
8078 %}
8080 #ifndef _LP64
8082 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8083 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8084 match(Set dst (OrI src1 (CastP2X src2)));
8086 size(4);
8087 format %{ "OR $src1,$src2,$dst" %}
8088 opcode(Assembler::or_op3, Assembler::arith_op);
8089 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8090 ins_pipe(ialu_reg_reg);
8091 %}
8093 #else
8095 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8096 match(Set dst (OrL src1 (CastP2X src2)));
8098 ins_cost(DEFAULT_COST);
8099 size(4);
8100 format %{ "OR $src1,$src2,$dst\t! long" %}
8101 opcode(Assembler::or_op3, Assembler::arith_op);
8102 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8103 ins_pipe(ialu_reg_reg);
8104 %}
8106 #endif
8108 // Xor Instructions
8109 // Register Xor
8110 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8111 match(Set dst (XorI src1 src2));
8113 size(4);
8114 format %{ "XOR $src1,$src2,$dst" %}
8115 opcode(Assembler::xor_op3, Assembler::arith_op);
8116 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8117 ins_pipe(ialu_reg_reg);
8118 %}
8120 // Immediate Xor
8121 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8122 match(Set dst (XorI src1 src2));
8124 size(4);
8125 format %{ "XOR $src1,$src2,$dst" %}
8126 opcode(Assembler::xor_op3, Assembler::arith_op);
8127 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8128 ins_pipe(ialu_reg_imm);
8129 %}
8131 // Register Xor Long
8132 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8133 match(Set dst (XorL src1 src2));
8135 ins_cost(DEFAULT_COST);
8136 size(4);
8137 format %{ "XOR $src1,$src2,$dst\t! long" %}
8138 opcode(Assembler::xor_op3, Assembler::arith_op);
8139 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8140 ins_pipe(ialu_reg_reg);
8141 %}
8143 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8144 match(Set dst (XorL src1 con));
8146 ins_cost(DEFAULT_COST);
8147 size(4);
8148 format %{ "XOR $src1,$con,$dst\t! long" %}
8149 opcode(Assembler::xor_op3, Assembler::arith_op);
8150 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8151 ins_pipe(ialu_reg_imm);
8152 %}
8154 //----------Convert to Boolean-------------------------------------------------
8155 // Nice hack for 32-bit tests but doesn't work for
8156 // 64-bit pointers.
8157 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8158 match(Set dst (Conv2B src));
8159 effect( KILL ccr );
8160 ins_cost(DEFAULT_COST*2);
8161 format %{ "CMP R_G0,$src\n\t"
8162 "ADDX R_G0,0,$dst" %}
8163 ins_encode( enc_to_bool( src, dst ) );
8164 ins_pipe(ialu_reg_ialu);
8165 %}
8167 #ifndef _LP64
8168 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8169 match(Set dst (Conv2B src));
8170 effect( KILL ccr );
8171 ins_cost(DEFAULT_COST*2);
8172 format %{ "CMP R_G0,$src\n\t"
8173 "ADDX R_G0,0,$dst" %}
8174 ins_encode( enc_to_bool( src, dst ) );
8175 ins_pipe(ialu_reg_ialu);
8176 %}
8177 #else
8178 instruct convP2B( iRegI dst, iRegP src ) %{
8179 match(Set dst (Conv2B src));
8180 ins_cost(DEFAULT_COST*2);
8181 format %{ "MOV $src,$dst\n\t"
8182 "MOVRNZ $src,1,$dst" %}
8183 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8184 ins_pipe(ialu_clr_and_mover);
8185 %}
8186 #endif
8188 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8189 match(Set dst (CmpLTMask src zero));
8190 effect(KILL ccr);
8191 size(4);
8192 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8193 ins_encode %{
8194 __ sra($src$$Register, 31, $dst$$Register);
8195 %}
8196 ins_pipe(ialu_reg_imm);
8197 %}
8199 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8200 match(Set dst (CmpLTMask p q));
8201 effect( KILL ccr );
8202 ins_cost(DEFAULT_COST*4);
8203 format %{ "CMP $p,$q\n\t"
8204 "MOV #0,$dst\n\t"
8205 "BLT,a .+8\n\t"
8206 "MOV #-1,$dst" %}
8207 ins_encode( enc_ltmask(p,q,dst) );
8208 ins_pipe(ialu_reg_reg_ialu);
8209 %}
8211 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8212 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8213 effect(KILL ccr, TEMP tmp);
8214 ins_cost(DEFAULT_COST*3);
8216 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8217 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8218 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8219 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8220 ins_pipe( cadd_cmpltmask );
8221 %}
8224 //-----------------------------------------------------------------
8225 // Direct raw moves between float and general registers using VIS3.
8227 // ins_pipe(faddF_reg);
8228 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8229 predicate(UseVIS >= 3);
8230 match(Set dst (MoveF2I src));
8232 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8233 ins_encode %{
8234 __ movstouw($src$$FloatRegister, $dst$$Register);
8235 %}
8236 ins_pipe(ialu_reg_reg);
8237 %}
8239 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8240 predicate(UseVIS >= 3);
8241 match(Set dst (MoveI2F src));
8243 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8244 ins_encode %{
8245 __ movwtos($src$$Register, $dst$$FloatRegister);
8246 %}
8247 ins_pipe(ialu_reg_reg);
8248 %}
8250 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8251 predicate(UseVIS >= 3);
8252 match(Set dst (MoveD2L src));
8254 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8255 ins_encode %{
8256 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8257 %}
8258 ins_pipe(ialu_reg_reg);
8259 %}
8261 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8262 predicate(UseVIS >= 3);
8263 match(Set dst (MoveL2D src));
8265 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8266 ins_encode %{
8267 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8268 %}
8269 ins_pipe(ialu_reg_reg);
8270 %}
8273 // Raw moves between float and general registers using stack.
8275 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8276 match(Set dst (MoveF2I src));
8277 effect(DEF dst, USE src);
8278 ins_cost(MEMORY_REF_COST);
8280 size(4);
8281 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8282 opcode(Assembler::lduw_op3);
8283 ins_encode(simple_form3_mem_reg( src, dst ) );
8284 ins_pipe(iload_mem);
8285 %}
8287 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8288 match(Set dst (MoveI2F src));
8289 effect(DEF dst, USE src);
8290 ins_cost(MEMORY_REF_COST);
8292 size(4);
8293 format %{ "LDF $src,$dst\t! MoveI2F" %}
8294 opcode(Assembler::ldf_op3);
8295 ins_encode(simple_form3_mem_reg(src, dst));
8296 ins_pipe(floadF_stk);
8297 %}
8299 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8300 match(Set dst (MoveD2L src));
8301 effect(DEF dst, USE src);
8302 ins_cost(MEMORY_REF_COST);
8304 size(4);
8305 format %{ "LDX $src,$dst\t! MoveD2L" %}
8306 opcode(Assembler::ldx_op3);
8307 ins_encode(simple_form3_mem_reg( src, dst ) );
8308 ins_pipe(iload_mem);
8309 %}
8311 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8312 match(Set dst (MoveL2D src));
8313 effect(DEF dst, USE src);
8314 ins_cost(MEMORY_REF_COST);
8316 size(4);
8317 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8318 opcode(Assembler::lddf_op3);
8319 ins_encode(simple_form3_mem_reg(src, dst));
8320 ins_pipe(floadD_stk);
8321 %}
8323 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8324 match(Set dst (MoveF2I src));
8325 effect(DEF dst, USE src);
8326 ins_cost(MEMORY_REF_COST);
8328 size(4);
8329 format %{ "STF $src,$dst\t! MoveF2I" %}
8330 opcode(Assembler::stf_op3);
8331 ins_encode(simple_form3_mem_reg(dst, src));
8332 ins_pipe(fstoreF_stk_reg);
8333 %}
8335 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8336 match(Set dst (MoveI2F src));
8337 effect(DEF dst, USE src);
8338 ins_cost(MEMORY_REF_COST);
8340 size(4);
8341 format %{ "STW $src,$dst\t! MoveI2F" %}
8342 opcode(Assembler::stw_op3);
8343 ins_encode(simple_form3_mem_reg( dst, src ) );
8344 ins_pipe(istore_mem_reg);
8345 %}
8347 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8348 match(Set dst (MoveD2L src));
8349 effect(DEF dst, USE src);
8350 ins_cost(MEMORY_REF_COST);
8352 size(4);
8353 format %{ "STDF $src,$dst\t! MoveD2L" %}
8354 opcode(Assembler::stdf_op3);
8355 ins_encode(simple_form3_mem_reg(dst, src));
8356 ins_pipe(fstoreD_stk_reg);
8357 %}
8359 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8360 match(Set dst (MoveL2D src));
8361 effect(DEF dst, USE src);
8362 ins_cost(MEMORY_REF_COST);
8364 size(4);
8365 format %{ "STX $src,$dst\t! MoveL2D" %}
8366 opcode(Assembler::stx_op3);
8367 ins_encode(simple_form3_mem_reg( dst, src ) );
8368 ins_pipe(istore_mem_reg);
8369 %}
8372 //----------Arithmetic Conversion Instructions---------------------------------
8373 // The conversions operations are all Alpha sorted. Please keep it that way!
8375 instruct convD2F_reg(regF dst, regD src) %{
8376 match(Set dst (ConvD2F src));
8377 size(4);
8378 format %{ "FDTOS $src,$dst" %}
8379 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8380 ins_encode(form3_opf_rs2D_rdF(src, dst));
8381 ins_pipe(fcvtD2F);
8382 %}
8385 // Convert a double to an int in a float register.
8386 // If the double is a NAN, stuff a zero in instead.
8387 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8388 effect(DEF dst, USE src, KILL fcc0);
8389 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8390 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8391 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8392 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8393 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8394 "skip:" %}
8395 ins_encode(form_d2i_helper(src,dst));
8396 ins_pipe(fcvtD2I);
8397 %}
8399 instruct convD2I_stk(stackSlotI dst, regD src) %{
8400 match(Set dst (ConvD2I src));
8401 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8402 expand %{
8403 regF tmp;
8404 convD2I_helper(tmp, src);
8405 regF_to_stkI(dst, tmp);
8406 %}
8407 %}
8409 instruct convD2I_reg(iRegI dst, regD src) %{
8410 predicate(UseVIS >= 3);
8411 match(Set dst (ConvD2I src));
8412 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8413 expand %{
8414 regF tmp;
8415 convD2I_helper(tmp, src);
8416 MoveF2I_reg_reg(dst, tmp);
8417 %}
8418 %}
8421 // Convert a double to a long in a double register.
8422 // If the double is a NAN, stuff a zero in instead.
8423 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8424 effect(DEF dst, USE src, KILL fcc0);
8425 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8426 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8427 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8428 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8429 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8430 "skip:" %}
8431 ins_encode(form_d2l_helper(src,dst));
8432 ins_pipe(fcvtD2L);
8433 %}
8435 instruct convD2L_stk(stackSlotL dst, regD src) %{
8436 match(Set dst (ConvD2L src));
8437 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8438 expand %{
8439 regD tmp;
8440 convD2L_helper(tmp, src);
8441 regD_to_stkL(dst, tmp);
8442 %}
8443 %}
8445 instruct convD2L_reg(iRegL dst, regD src) %{
8446 predicate(UseVIS >= 3);
8447 match(Set dst (ConvD2L src));
8448 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8449 expand %{
8450 regD tmp;
8451 convD2L_helper(tmp, src);
8452 MoveD2L_reg_reg(dst, tmp);
8453 %}
8454 %}
8457 instruct convF2D_reg(regD dst, regF src) %{
8458 match(Set dst (ConvF2D src));
8459 format %{ "FSTOD $src,$dst" %}
8460 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8461 ins_encode(form3_opf_rs2F_rdD(src, dst));
8462 ins_pipe(fcvtF2D);
8463 %}
8466 // Convert a float to an int in a float register.
8467 // If the float is a NAN, stuff a zero in instead.
8468 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8469 effect(DEF dst, USE src, KILL fcc0);
8470 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8471 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8472 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8473 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8474 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8475 "skip:" %}
8476 ins_encode(form_f2i_helper(src,dst));
8477 ins_pipe(fcvtF2I);
8478 %}
8480 instruct convF2I_stk(stackSlotI dst, regF src) %{
8481 match(Set dst (ConvF2I src));
8482 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8483 expand %{
8484 regF tmp;
8485 convF2I_helper(tmp, src);
8486 regF_to_stkI(dst, tmp);
8487 %}
8488 %}
8490 instruct convF2I_reg(iRegI dst, regF src) %{
8491 predicate(UseVIS >= 3);
8492 match(Set dst (ConvF2I src));
8493 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8494 expand %{
8495 regF tmp;
8496 convF2I_helper(tmp, src);
8497 MoveF2I_reg_reg(dst, tmp);
8498 %}
8499 %}
8502 // Convert a float to a long in a float register.
8503 // If the float is a NAN, stuff a zero in instead.
8504 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8505 effect(DEF dst, USE src, KILL fcc0);
8506 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8507 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8508 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8509 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8510 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8511 "skip:" %}
8512 ins_encode(form_f2l_helper(src,dst));
8513 ins_pipe(fcvtF2L);
8514 %}
8516 instruct convF2L_stk(stackSlotL dst, regF src) %{
8517 match(Set dst (ConvF2L src));
8518 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8519 expand %{
8520 regD tmp;
8521 convF2L_helper(tmp, src);
8522 regD_to_stkL(dst, tmp);
8523 %}
8524 %}
8526 instruct convF2L_reg(iRegL dst, regF src) %{
8527 predicate(UseVIS >= 3);
8528 match(Set dst (ConvF2L src));
8529 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8530 expand %{
8531 regD tmp;
8532 convF2L_helper(tmp, src);
8533 MoveD2L_reg_reg(dst, tmp);
8534 %}
8535 %}
8538 instruct convI2D_helper(regD dst, regF tmp) %{
8539 effect(USE tmp, DEF dst);
8540 format %{ "FITOD $tmp,$dst" %}
8541 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8542 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8543 ins_pipe(fcvtI2D);
8544 %}
8546 instruct convI2D_stk(stackSlotI src, regD dst) %{
8547 match(Set dst (ConvI2D src));
8548 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8549 expand %{
8550 regF tmp;
8551 stkI_to_regF(tmp, src);
8552 convI2D_helper(dst, tmp);
8553 %}
8554 %}
8556 instruct convI2D_reg(regD_low dst, iRegI src) %{
8557 predicate(UseVIS >= 3);
8558 match(Set dst (ConvI2D src));
8559 expand %{
8560 regF tmp;
8561 MoveI2F_reg_reg(tmp, src);
8562 convI2D_helper(dst, tmp);
8563 %}
8564 %}
8566 instruct convI2D_mem(regD_low dst, memory mem) %{
8567 match(Set dst (ConvI2D (LoadI mem)));
8568 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8569 size(8);
8570 format %{ "LDF $mem,$dst\n\t"
8571 "FITOD $dst,$dst" %}
8572 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8573 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8574 ins_pipe(floadF_mem);
8575 %}
8578 instruct convI2F_helper(regF dst, regF tmp) %{
8579 effect(DEF dst, USE tmp);
8580 format %{ "FITOS $tmp,$dst" %}
8581 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8582 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8583 ins_pipe(fcvtI2F);
8584 %}
8586 instruct convI2F_stk(regF dst, stackSlotI src) %{
8587 match(Set dst (ConvI2F src));
8588 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8589 expand %{
8590 regF tmp;
8591 stkI_to_regF(tmp,src);
8592 convI2F_helper(dst, tmp);
8593 %}
8594 %}
8596 instruct convI2F_reg(regF dst, iRegI src) %{
8597 predicate(UseVIS >= 3);
8598 match(Set dst (ConvI2F src));
8599 ins_cost(DEFAULT_COST);
8600 expand %{
8601 regF tmp;
8602 MoveI2F_reg_reg(tmp, src);
8603 convI2F_helper(dst, tmp);
8604 %}
8605 %}
8607 instruct convI2F_mem( regF dst, memory mem ) %{
8608 match(Set dst (ConvI2F (LoadI mem)));
8609 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8610 size(8);
8611 format %{ "LDF $mem,$dst\n\t"
8612 "FITOS $dst,$dst" %}
8613 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8614 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8615 ins_pipe(floadF_mem);
8616 %}
8619 instruct convI2L_reg(iRegL dst, iRegI src) %{
8620 match(Set dst (ConvI2L src));
8621 size(4);
8622 format %{ "SRA $src,0,$dst\t! int->long" %}
8623 opcode(Assembler::sra_op3, Assembler::arith_op);
8624 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8625 ins_pipe(ialu_reg_reg);
8626 %}
8628 // Zero-extend convert int to long
8629 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8630 match(Set dst (AndL (ConvI2L src) mask) );
8631 size(4);
8632 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8633 opcode(Assembler::srl_op3, Assembler::arith_op);
8634 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8635 ins_pipe(ialu_reg_reg);
8636 %}
8638 // Zero-extend long
8639 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8640 match(Set dst (AndL src mask) );
8641 size(4);
8642 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8643 opcode(Assembler::srl_op3, Assembler::arith_op);
8644 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8645 ins_pipe(ialu_reg_reg);
8646 %}
8649 //-----------
8650 // Long to Double conversion using V8 opcodes.
8651 // Still useful because cheetah traps and becomes
8652 // amazingly slow for some common numbers.
8654 // Magic constant, 0x43300000
8655 instruct loadConI_x43300000(iRegI dst) %{
8656 effect(DEF dst);
8657 size(4);
8658 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8659 ins_encode(SetHi22(0x43300000, dst));
8660 ins_pipe(ialu_none);
8661 %}
8663 // Magic constant, 0x41f00000
8664 instruct loadConI_x41f00000(iRegI dst) %{
8665 effect(DEF dst);
8666 size(4);
8667 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8668 ins_encode(SetHi22(0x41f00000, dst));
8669 ins_pipe(ialu_none);
8670 %}
8672 // Construct a double from two float halves
8673 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8674 effect(DEF dst, USE src1, USE src2);
8675 size(8);
8676 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8677 "FMOVS $src2.lo,$dst.lo" %}
8678 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8679 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8680 ins_pipe(faddD_reg_reg);
8681 %}
8683 // Convert integer in high half of a double register (in the lower half of
8684 // the double register file) to double
8685 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8686 effect(DEF dst, USE src);
8687 size(4);
8688 format %{ "FITOD $src,$dst" %}
8689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8690 ins_encode(form3_opf_rs2D_rdD(src, dst));
8691 ins_pipe(fcvtLHi2D);
8692 %}
8694 // Add float double precision
8695 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8696 effect(DEF dst, USE src1, USE src2);
8697 size(4);
8698 format %{ "FADDD $src1,$src2,$dst" %}
8699 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8700 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8701 ins_pipe(faddD_reg_reg);
8702 %}
8704 // Sub float double precision
8705 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8706 effect(DEF dst, USE src1, USE src2);
8707 size(4);
8708 format %{ "FSUBD $src1,$src2,$dst" %}
8709 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8710 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8711 ins_pipe(faddD_reg_reg);
8712 %}
8714 // Mul float double precision
8715 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8716 effect(DEF dst, USE src1, USE src2);
8717 size(4);
8718 format %{ "FMULD $src1,$src2,$dst" %}
8719 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8720 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8721 ins_pipe(fmulD_reg_reg);
8722 %}
8724 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8725 match(Set dst (ConvL2D src));
8726 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8728 expand %{
8729 regD_low tmpsrc;
8730 iRegI ix43300000;
8731 iRegI ix41f00000;
8732 stackSlotL lx43300000;
8733 stackSlotL lx41f00000;
8734 regD_low dx43300000;
8735 regD dx41f00000;
8736 regD tmp1;
8737 regD_low tmp2;
8738 regD tmp3;
8739 regD tmp4;
8741 stkL_to_regD(tmpsrc, src);
8743 loadConI_x43300000(ix43300000);
8744 loadConI_x41f00000(ix41f00000);
8745 regI_to_stkLHi(lx43300000, ix43300000);
8746 regI_to_stkLHi(lx41f00000, ix41f00000);
8747 stkL_to_regD(dx43300000, lx43300000);
8748 stkL_to_regD(dx41f00000, lx41f00000);
8750 convI2D_regDHi_regD(tmp1, tmpsrc);
8751 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8752 subD_regD_regD(tmp3, tmp2, dx43300000);
8753 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8754 addD_regD_regD(dst, tmp3, tmp4);
8755 %}
8756 %}
8758 // Long to Double conversion using fast fxtof
8759 instruct convL2D_helper(regD dst, regD tmp) %{
8760 effect(DEF dst, USE tmp);
8761 size(4);
8762 format %{ "FXTOD $tmp,$dst" %}
8763 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8764 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8765 ins_pipe(fcvtL2D);
8766 %}
8768 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8769 predicate(VM_Version::has_fast_fxtof());
8770 match(Set dst (ConvL2D src));
8771 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8772 expand %{
8773 regD tmp;
8774 stkL_to_regD(tmp, src);
8775 convL2D_helper(dst, tmp);
8776 %}
8777 %}
8779 instruct convL2D_reg(regD dst, iRegL src) %{
8780 predicate(UseVIS >= 3);
8781 match(Set dst (ConvL2D src));
8782 expand %{
8783 regD tmp;
8784 MoveL2D_reg_reg(tmp, src);
8785 convL2D_helper(dst, tmp);
8786 %}
8787 %}
8789 // Long to Float conversion using fast fxtof
8790 instruct convL2F_helper(regF dst, regD tmp) %{
8791 effect(DEF dst, USE tmp);
8792 size(4);
8793 format %{ "FXTOS $tmp,$dst" %}
8794 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8795 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8796 ins_pipe(fcvtL2F);
8797 %}
8799 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8800 match(Set dst (ConvL2F src));
8801 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8802 expand %{
8803 regD tmp;
8804 stkL_to_regD(tmp, src);
8805 convL2F_helper(dst, tmp);
8806 %}
8807 %}
8809 instruct convL2F_reg(regF dst, iRegL src) %{
8810 predicate(UseVIS >= 3);
8811 match(Set dst (ConvL2F src));
8812 ins_cost(DEFAULT_COST);
8813 expand %{
8814 regD tmp;
8815 MoveL2D_reg_reg(tmp, src);
8816 convL2F_helper(dst, tmp);
8817 %}
8818 %}
8820 //-----------
8822 instruct convL2I_reg(iRegI dst, iRegL src) %{
8823 match(Set dst (ConvL2I src));
8824 #ifndef _LP64
8825 format %{ "MOV $src.lo,$dst\t! long->int" %}
8826 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8827 ins_pipe(ialu_move_reg_I_to_L);
8828 #else
8829 size(4);
8830 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8831 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8832 ins_pipe(ialu_reg);
8833 #endif
8834 %}
8836 // Register Shift Right Immediate
8837 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8838 match(Set dst (ConvL2I (RShiftL src cnt)));
8840 size(4);
8841 format %{ "SRAX $src,$cnt,$dst" %}
8842 opcode(Assembler::srax_op3, Assembler::arith_op);
8843 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8844 ins_pipe(ialu_reg_imm);
8845 %}
8847 // Replicate scalar to packed byte values in Double register
8848 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8849 effect(DEF dst, USE src);
8850 format %{ "SLLX $src,56,$dst\n\t"
8851 "SRLX $dst, 8,O7\n\t"
8852 "OR $dst,O7,$dst\n\t"
8853 "SRLX $dst,16,O7\n\t"
8854 "OR $dst,O7,$dst\n\t"
8855 "SRLX $dst,32,O7\n\t"
8856 "OR $dst,O7,$dst\t! replicate8B" %}
8857 ins_encode( enc_repl8b(src, dst));
8858 ins_pipe(ialu_reg);
8859 %}
8861 // Replicate scalar to packed byte values in Double register
8862 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8863 match(Set dst (Replicate8B src));
8864 expand %{
8865 iRegL tmp;
8866 Repl8B_reg_helper(tmp, src);
8867 regL_to_stkD(dst, tmp);
8868 %}
8869 %}
8871 // Replicate scalar constant to packed byte values in Double register
8872 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8873 match(Set dst (Replicate8B con));
8874 effect(KILL tmp);
8875 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8876 ins_encode %{
8877 // XXX This is a quick fix for 6833573.
8878 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8879 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8880 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8881 %}
8882 ins_pipe(loadConFD);
8883 %}
8885 // Replicate scalar to packed char values into stack slot
8886 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8887 effect(DEF dst, USE src);
8888 format %{ "SLLX $src,48,$dst\n\t"
8889 "SRLX $dst,16,O7\n\t"
8890 "OR $dst,O7,$dst\n\t"
8891 "SRLX $dst,32,O7\n\t"
8892 "OR $dst,O7,$dst\t! replicate4C" %}
8893 ins_encode( enc_repl4s(src, dst) );
8894 ins_pipe(ialu_reg);
8895 %}
8897 // Replicate scalar to packed char values into stack slot
8898 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8899 match(Set dst (Replicate4C src));
8900 expand %{
8901 iRegL tmp;
8902 Repl4C_reg_helper(tmp, src);
8903 regL_to_stkD(dst, tmp);
8904 %}
8905 %}
8907 // Replicate scalar constant to packed char values in Double register
8908 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8909 match(Set dst (Replicate4C con));
8910 effect(KILL tmp);
8911 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8912 ins_encode %{
8913 // XXX This is a quick fix for 6833573.
8914 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8915 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8916 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8917 %}
8918 ins_pipe(loadConFD);
8919 %}
8921 // Replicate scalar to packed short values into stack slot
8922 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8923 effect(DEF dst, USE src);
8924 format %{ "SLLX $src,48,$dst\n\t"
8925 "SRLX $dst,16,O7\n\t"
8926 "OR $dst,O7,$dst\n\t"
8927 "SRLX $dst,32,O7\n\t"
8928 "OR $dst,O7,$dst\t! replicate4S" %}
8929 ins_encode( enc_repl4s(src, dst) );
8930 ins_pipe(ialu_reg);
8931 %}
8933 // Replicate scalar to packed short values into stack slot
8934 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8935 match(Set dst (Replicate4S src));
8936 expand %{
8937 iRegL tmp;
8938 Repl4S_reg_helper(tmp, src);
8939 regL_to_stkD(dst, tmp);
8940 %}
8941 %}
8943 // Replicate scalar constant to packed short values in Double register
8944 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8945 match(Set dst (Replicate4S con));
8946 effect(KILL tmp);
8947 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8948 ins_encode %{
8949 // XXX This is a quick fix for 6833573.
8950 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8951 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8952 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8953 %}
8954 ins_pipe(loadConFD);
8955 %}
8957 // Replicate scalar to packed int values in Double register
8958 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8959 effect(DEF dst, USE src);
8960 format %{ "SLLX $src,32,$dst\n\t"
8961 "SRLX $dst,32,O7\n\t"
8962 "OR $dst,O7,$dst\t! replicate2I" %}
8963 ins_encode( enc_repl2i(src, dst));
8964 ins_pipe(ialu_reg);
8965 %}
8967 // Replicate scalar to packed int values in Double register
8968 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8969 match(Set dst (Replicate2I src));
8970 expand %{
8971 iRegL tmp;
8972 Repl2I_reg_helper(tmp, src);
8973 regL_to_stkD(dst, tmp);
8974 %}
8975 %}
8977 // Replicate scalar zero constant to packed int values in Double register
8978 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
8979 match(Set dst (Replicate2I con));
8980 effect(KILL tmp);
8981 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8982 ins_encode %{
8983 // XXX This is a quick fix for 6833573.
8984 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8985 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
8986 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8987 %}
8988 ins_pipe(loadConFD);
8989 %}
8991 //----------Control Flow Instructions------------------------------------------
8992 // Compare Instructions
8993 // Compare Integers
8994 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8995 match(Set icc (CmpI op1 op2));
8996 effect( DEF icc, USE op1, USE op2 );
8998 size(4);
8999 format %{ "CMP $op1,$op2" %}
9000 opcode(Assembler::subcc_op3, Assembler::arith_op);
9001 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9002 ins_pipe(ialu_cconly_reg_reg);
9003 %}
9005 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
9006 match(Set icc (CmpU op1 op2));
9008 size(4);
9009 format %{ "CMP $op1,$op2\t! unsigned" %}
9010 opcode(Assembler::subcc_op3, Assembler::arith_op);
9011 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9012 ins_pipe(ialu_cconly_reg_reg);
9013 %}
9015 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
9016 match(Set icc (CmpI op1 op2));
9017 effect( DEF icc, USE op1 );
9019 size(4);
9020 format %{ "CMP $op1,$op2" %}
9021 opcode(Assembler::subcc_op3, Assembler::arith_op);
9022 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9023 ins_pipe(ialu_cconly_reg_imm);
9024 %}
9026 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
9027 match(Set icc (CmpI (AndI op1 op2) zero));
9029 size(4);
9030 format %{ "BTST $op2,$op1" %}
9031 opcode(Assembler::andcc_op3, Assembler::arith_op);
9032 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9033 ins_pipe(ialu_cconly_reg_reg_zero);
9034 %}
9036 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
9037 match(Set icc (CmpI (AndI op1 op2) zero));
9039 size(4);
9040 format %{ "BTST $op2,$op1" %}
9041 opcode(Assembler::andcc_op3, Assembler::arith_op);
9042 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9043 ins_pipe(ialu_cconly_reg_imm_zero);
9044 %}
9046 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
9047 match(Set xcc (CmpL op1 op2));
9048 effect( DEF xcc, USE op1, USE op2 );
9050 size(4);
9051 format %{ "CMP $op1,$op2\t\t! long" %}
9052 opcode(Assembler::subcc_op3, Assembler::arith_op);
9053 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9054 ins_pipe(ialu_cconly_reg_reg);
9055 %}
9057 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
9058 match(Set xcc (CmpL op1 con));
9059 effect( DEF xcc, USE op1, USE con );
9061 size(4);
9062 format %{ "CMP $op1,$con\t\t! long" %}
9063 opcode(Assembler::subcc_op3, Assembler::arith_op);
9064 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9065 ins_pipe(ialu_cconly_reg_reg);
9066 %}
9068 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
9069 match(Set xcc (CmpL (AndL op1 op2) zero));
9070 effect( DEF xcc, USE op1, USE op2 );
9072 size(4);
9073 format %{ "BTST $op1,$op2\t\t! long" %}
9074 opcode(Assembler::andcc_op3, Assembler::arith_op);
9075 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9076 ins_pipe(ialu_cconly_reg_reg);
9077 %}
9079 // useful for checking the alignment of a pointer:
9080 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9081 match(Set xcc (CmpL (AndL op1 con) zero));
9082 effect( DEF xcc, USE op1, USE con );
9084 size(4);
9085 format %{ "BTST $op1,$con\t\t! long" %}
9086 opcode(Assembler::andcc_op3, Assembler::arith_op);
9087 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9088 ins_pipe(ialu_cconly_reg_reg);
9089 %}
9091 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
9092 match(Set icc (CmpU op1 op2));
9094 size(4);
9095 format %{ "CMP $op1,$op2\t! unsigned" %}
9096 opcode(Assembler::subcc_op3, Assembler::arith_op);
9097 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9098 ins_pipe(ialu_cconly_reg_imm);
9099 %}
9101 // Compare Pointers
9102 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9103 match(Set pcc (CmpP op1 op2));
9105 size(4);
9106 format %{ "CMP $op1,$op2\t! ptr" %}
9107 opcode(Assembler::subcc_op3, Assembler::arith_op);
9108 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9109 ins_pipe(ialu_cconly_reg_reg);
9110 %}
9112 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9113 match(Set pcc (CmpP op1 op2));
9115 size(4);
9116 format %{ "CMP $op1,$op2\t! ptr" %}
9117 opcode(Assembler::subcc_op3, Assembler::arith_op);
9118 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9119 ins_pipe(ialu_cconly_reg_imm);
9120 %}
9122 // Compare Narrow oops
9123 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9124 match(Set icc (CmpN op1 op2));
9126 size(4);
9127 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9128 opcode(Assembler::subcc_op3, Assembler::arith_op);
9129 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9130 ins_pipe(ialu_cconly_reg_reg);
9131 %}
9133 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9134 match(Set icc (CmpN op1 op2));
9136 size(4);
9137 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9138 opcode(Assembler::subcc_op3, Assembler::arith_op);
9139 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9140 ins_pipe(ialu_cconly_reg_imm);
9141 %}
9143 //----------Max and Min--------------------------------------------------------
9144 // Min Instructions
9145 // Conditional move for min
9146 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9147 effect( USE_DEF op2, USE op1, USE icc );
9149 size(4);
9150 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9151 opcode(Assembler::less);
9152 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9153 ins_pipe(ialu_reg_flags);
9154 %}
9156 // Min Register with Register.
9157 instruct minI_eReg(iRegI op1, iRegI op2) %{
9158 match(Set op2 (MinI op1 op2));
9159 ins_cost(DEFAULT_COST*2);
9160 expand %{
9161 flagsReg icc;
9162 compI_iReg(icc,op1,op2);
9163 cmovI_reg_lt(op2,op1,icc);
9164 %}
9165 %}
9167 // Max Instructions
9168 // Conditional move for max
9169 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9170 effect( USE_DEF op2, USE op1, USE icc );
9171 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9172 opcode(Assembler::greater);
9173 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9174 ins_pipe(ialu_reg_flags);
9175 %}
9177 // Max Register with Register
9178 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9179 match(Set op2 (MaxI op1 op2));
9180 ins_cost(DEFAULT_COST*2);
9181 expand %{
9182 flagsReg icc;
9183 compI_iReg(icc,op1,op2);
9184 cmovI_reg_gt(op2,op1,icc);
9185 %}
9186 %}
9189 //----------Float Compares----------------------------------------------------
9190 // Compare floating, generate condition code
9191 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9192 match(Set fcc (CmpF src1 src2));
9194 size(4);
9195 format %{ "FCMPs $fcc,$src1,$src2" %}
9196 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9197 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9198 ins_pipe(faddF_fcc_reg_reg_zero);
9199 %}
9201 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9202 match(Set fcc (CmpD src1 src2));
9204 size(4);
9205 format %{ "FCMPd $fcc,$src1,$src2" %}
9206 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9207 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9208 ins_pipe(faddD_fcc_reg_reg_zero);
9209 %}
9212 // Compare floating, generate -1,0,1
9213 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9214 match(Set dst (CmpF3 src1 src2));
9215 effect(KILL fcc0);
9216 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9217 format %{ "fcmpl $dst,$src1,$src2" %}
9218 // Primary = float
9219 opcode( true );
9220 ins_encode( floating_cmp( dst, src1, src2 ) );
9221 ins_pipe( floating_cmp );
9222 %}
9224 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9225 match(Set dst (CmpD3 src1 src2));
9226 effect(KILL fcc0);
9227 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9228 format %{ "dcmpl $dst,$src1,$src2" %}
9229 // Primary = double (not float)
9230 opcode( false );
9231 ins_encode( floating_cmp( dst, src1, src2 ) );
9232 ins_pipe( floating_cmp );
9233 %}
9235 //----------Branches---------------------------------------------------------
9236 // Jump
9237 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9238 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9239 match(Jump switch_val);
9241 ins_cost(350);
9243 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9244 "LD [O7 + $switch_val], O7\n\t"
9245 "JUMP O7"
9246 %}
9247 ins_encode %{
9248 // Calculate table address into a register.
9249 Register table_reg;
9250 Register label_reg = O7;
9251 if (constant_offset() == 0) {
9252 table_reg = $constanttablebase;
9253 } else {
9254 table_reg = O7;
9255 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9256 __ add($constanttablebase, con_offset, table_reg);
9257 }
9259 // Jump to base address + switch value
9260 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9261 __ jmp(label_reg, G0);
9262 __ delayed()->nop();
9263 %}
9264 ins_pipe(ialu_reg_reg);
9265 %}
9267 // Direct Branch. Use V8 version with longer range.
9268 instruct branch(label labl) %{
9269 match(Goto);
9270 effect(USE labl);
9272 size(8);
9273 ins_cost(BRANCH_COST);
9274 format %{ "BA $labl" %}
9275 ins_encode %{
9276 Label* L = $labl$$label;
9277 __ ba(*L);
9278 __ delayed()->nop();
9279 %}
9280 ins_pipe(br);
9281 %}
9283 // Direct Branch, short with no delay slot
9284 instruct branch_short(label labl) %{
9285 match(Goto);
9286 predicate(UseCBCond);
9287 effect(USE labl);
9289 size(4);
9290 ins_cost(BRANCH_COST);
9291 format %{ "BA $labl\t! short branch" %}
9292 ins_encode %{
9293 Label* L = $labl$$label;
9294 assert(__ use_cbcond(*L), "back to back cbcond");
9295 __ ba_short(*L);
9296 %}
9297 ins_short_branch(1);
9298 ins_avoid_back_to_back(1);
9299 ins_pipe(cbcond_reg_imm);
9300 %}
9302 // Conditional Direct Branch
9303 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9304 match(If cmp icc);
9305 effect(USE labl);
9307 size(8);
9308 ins_cost(BRANCH_COST);
9309 format %{ "BP$cmp $icc,$labl" %}
9310 // Prim = bits 24-22, Secnd = bits 31-30
9311 ins_encode( enc_bp( labl, cmp, icc ) );
9312 ins_pipe(br_cc);
9313 %}
9315 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9316 match(If cmp icc);
9317 effect(USE labl);
9319 ins_cost(BRANCH_COST);
9320 format %{ "BP$cmp $icc,$labl" %}
9321 // Prim = bits 24-22, Secnd = bits 31-30
9322 ins_encode( enc_bp( labl, cmp, icc ) );
9323 ins_pipe(br_cc);
9324 %}
9326 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9327 match(If cmp pcc);
9328 effect(USE labl);
9330 size(8);
9331 ins_cost(BRANCH_COST);
9332 format %{ "BP$cmp $pcc,$labl" %}
9333 ins_encode %{
9334 Label* L = $labl$$label;
9335 Assembler::Predict predict_taken =
9336 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9338 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9339 __ delayed()->nop();
9340 %}
9341 ins_pipe(br_cc);
9342 %}
9344 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9345 match(If cmp fcc);
9346 effect(USE labl);
9348 size(8);
9349 ins_cost(BRANCH_COST);
9350 format %{ "FBP$cmp $fcc,$labl" %}
9351 ins_encode %{
9352 Label* L = $labl$$label;
9353 Assembler::Predict predict_taken =
9354 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9356 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9357 __ delayed()->nop();
9358 %}
9359 ins_pipe(br_fcc);
9360 %}
9362 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9363 match(CountedLoopEnd cmp icc);
9364 effect(USE labl);
9366 size(8);
9367 ins_cost(BRANCH_COST);
9368 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9369 // Prim = bits 24-22, Secnd = bits 31-30
9370 ins_encode( enc_bp( labl, cmp, icc ) );
9371 ins_pipe(br_cc);
9372 %}
9374 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9375 match(CountedLoopEnd cmp icc);
9376 effect(USE labl);
9378 size(8);
9379 ins_cost(BRANCH_COST);
9380 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9381 // Prim = bits 24-22, Secnd = bits 31-30
9382 ins_encode( enc_bp( labl, cmp, icc ) );
9383 ins_pipe(br_cc);
9384 %}
9386 // Compare and branch instructions
9387 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9388 match(If cmp (CmpI op1 op2));
9389 effect(USE labl, KILL icc);
9391 size(12);
9392 ins_cost(BRANCH_COST);
9393 format %{ "CMP $op1,$op2\t! int\n\t"
9394 "BP$cmp $labl" %}
9395 ins_encode %{
9396 Label* L = $labl$$label;
9397 Assembler::Predict predict_taken =
9398 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9399 __ cmp($op1$$Register, $op2$$Register);
9400 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9401 __ delayed()->nop();
9402 %}
9403 ins_pipe(cmp_br_reg_reg);
9404 %}
9406 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9407 match(If cmp (CmpI op1 op2));
9408 effect(USE labl, KILL icc);
9410 size(12);
9411 ins_cost(BRANCH_COST);
9412 format %{ "CMP $op1,$op2\t! int\n\t"
9413 "BP$cmp $labl" %}
9414 ins_encode %{
9415 Label* L = $labl$$label;
9416 Assembler::Predict predict_taken =
9417 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9418 __ cmp($op1$$Register, $op2$$constant);
9419 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9420 __ delayed()->nop();
9421 %}
9422 ins_pipe(cmp_br_reg_imm);
9423 %}
9425 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9426 match(If cmp (CmpU op1 op2));
9427 effect(USE labl, KILL icc);
9429 size(12);
9430 ins_cost(BRANCH_COST);
9431 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9432 "BP$cmp $labl" %}
9433 ins_encode %{
9434 Label* L = $labl$$label;
9435 Assembler::Predict predict_taken =
9436 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9437 __ cmp($op1$$Register, $op2$$Register);
9438 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9439 __ delayed()->nop();
9440 %}
9441 ins_pipe(cmp_br_reg_reg);
9442 %}
9444 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9445 match(If cmp (CmpU op1 op2));
9446 effect(USE labl, KILL icc);
9448 size(12);
9449 ins_cost(BRANCH_COST);
9450 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9451 "BP$cmp $labl" %}
9452 ins_encode %{
9453 Label* L = $labl$$label;
9454 Assembler::Predict predict_taken =
9455 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9456 __ cmp($op1$$Register, $op2$$constant);
9457 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9458 __ delayed()->nop();
9459 %}
9460 ins_pipe(cmp_br_reg_imm);
9461 %}
9463 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9464 match(If cmp (CmpL op1 op2));
9465 effect(USE labl, KILL xcc);
9467 size(12);
9468 ins_cost(BRANCH_COST);
9469 format %{ "CMP $op1,$op2\t! long\n\t"
9470 "BP$cmp $labl" %}
9471 ins_encode %{
9472 Label* L = $labl$$label;
9473 Assembler::Predict predict_taken =
9474 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9475 __ cmp($op1$$Register, $op2$$Register);
9476 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9477 __ delayed()->nop();
9478 %}
9479 ins_pipe(cmp_br_reg_reg);
9480 %}
9482 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9483 match(If cmp (CmpL op1 op2));
9484 effect(USE labl, KILL xcc);
9486 size(12);
9487 ins_cost(BRANCH_COST);
9488 format %{ "CMP $op1,$op2\t! long\n\t"
9489 "BP$cmp $labl" %}
9490 ins_encode %{
9491 Label* L = $labl$$label;
9492 Assembler::Predict predict_taken =
9493 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9494 __ cmp($op1$$Register, $op2$$constant);
9495 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9496 __ delayed()->nop();
9497 %}
9498 ins_pipe(cmp_br_reg_imm);
9499 %}
9501 // Compare Pointers and branch
9502 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9503 match(If cmp (CmpP op1 op2));
9504 effect(USE labl, KILL pcc);
9506 size(12);
9507 ins_cost(BRANCH_COST);
9508 format %{ "CMP $op1,$op2\t! ptr\n\t"
9509 "B$cmp $labl" %}
9510 ins_encode %{
9511 Label* L = $labl$$label;
9512 Assembler::Predict predict_taken =
9513 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9514 __ cmp($op1$$Register, $op2$$Register);
9515 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9516 __ delayed()->nop();
9517 %}
9518 ins_pipe(cmp_br_reg_reg);
9519 %}
9521 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9522 match(If cmp (CmpP op1 null));
9523 effect(USE labl, KILL pcc);
9525 size(12);
9526 ins_cost(BRANCH_COST);
9527 format %{ "CMP $op1,0\t! ptr\n\t"
9528 "B$cmp $labl" %}
9529 ins_encode %{
9530 Label* L = $labl$$label;
9531 Assembler::Predict predict_taken =
9532 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9533 __ cmp($op1$$Register, G0);
9534 // bpr() is not used here since it has shorter distance.
9535 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9536 __ delayed()->nop();
9537 %}
9538 ins_pipe(cmp_br_reg_reg);
9539 %}
9541 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9542 match(If cmp (CmpN op1 op2));
9543 effect(USE labl, KILL icc);
9545 size(12);
9546 ins_cost(BRANCH_COST);
9547 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9548 "BP$cmp $labl" %}
9549 ins_encode %{
9550 Label* L = $labl$$label;
9551 Assembler::Predict predict_taken =
9552 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9553 __ cmp($op1$$Register, $op2$$Register);
9554 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9555 __ delayed()->nop();
9556 %}
9557 ins_pipe(cmp_br_reg_reg);
9558 %}
9560 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9561 match(If cmp (CmpN op1 null));
9562 effect(USE labl, KILL icc);
9564 size(12);
9565 ins_cost(BRANCH_COST);
9566 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9567 "BP$cmp $labl" %}
9568 ins_encode %{
9569 Label* L = $labl$$label;
9570 Assembler::Predict predict_taken =
9571 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9572 __ cmp($op1$$Register, G0);
9573 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9574 __ delayed()->nop();
9575 %}
9576 ins_pipe(cmp_br_reg_reg);
9577 %}
9579 // Loop back branch
9580 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9581 match(CountedLoopEnd cmp (CmpI op1 op2));
9582 effect(USE labl, KILL icc);
9584 size(12);
9585 ins_cost(BRANCH_COST);
9586 format %{ "CMP $op1,$op2\t! int\n\t"
9587 "BP$cmp $labl\t! Loop end" %}
9588 ins_encode %{
9589 Label* L = $labl$$label;
9590 Assembler::Predict predict_taken =
9591 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9592 __ cmp($op1$$Register, $op2$$Register);
9593 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9594 __ delayed()->nop();
9595 %}
9596 ins_pipe(cmp_br_reg_reg);
9597 %}
9599 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9600 match(CountedLoopEnd cmp (CmpI op1 op2));
9601 effect(USE labl, KILL icc);
9603 size(12);
9604 ins_cost(BRANCH_COST);
9605 format %{ "CMP $op1,$op2\t! int\n\t"
9606 "BP$cmp $labl\t! Loop end" %}
9607 ins_encode %{
9608 Label* L = $labl$$label;
9609 Assembler::Predict predict_taken =
9610 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9611 __ cmp($op1$$Register, $op2$$constant);
9612 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9613 __ delayed()->nop();
9614 %}
9615 ins_pipe(cmp_br_reg_imm);
9616 %}
9618 // Short compare and branch instructions
9619 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9620 match(If cmp (CmpI op1 op2));
9621 predicate(UseCBCond);
9622 effect(USE labl, KILL icc);
9624 size(4);
9625 ins_cost(BRANCH_COST);
9626 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9627 ins_encode %{
9628 Label* L = $labl$$label;
9629 assert(__ use_cbcond(*L), "back to back cbcond");
9630 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9631 %}
9632 ins_short_branch(1);
9633 ins_avoid_back_to_back(1);
9634 ins_pipe(cbcond_reg_reg);
9635 %}
9637 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9638 match(If cmp (CmpI op1 op2));
9639 predicate(UseCBCond);
9640 effect(USE labl, KILL icc);
9642 size(4);
9643 ins_cost(BRANCH_COST);
9644 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9645 ins_encode %{
9646 Label* L = $labl$$label;
9647 assert(__ use_cbcond(*L), "back to back cbcond");
9648 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9649 %}
9650 ins_short_branch(1);
9651 ins_avoid_back_to_back(1);
9652 ins_pipe(cbcond_reg_imm);
9653 %}
9655 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9656 match(If cmp (CmpU op1 op2));
9657 predicate(UseCBCond);
9658 effect(USE labl, KILL icc);
9660 size(4);
9661 ins_cost(BRANCH_COST);
9662 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9663 ins_encode %{
9664 Label* L = $labl$$label;
9665 assert(__ use_cbcond(*L), "back to back cbcond");
9666 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9667 %}
9668 ins_short_branch(1);
9669 ins_avoid_back_to_back(1);
9670 ins_pipe(cbcond_reg_reg);
9671 %}
9673 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9674 match(If cmp (CmpU op1 op2));
9675 predicate(UseCBCond);
9676 effect(USE labl, KILL icc);
9678 size(4);
9679 ins_cost(BRANCH_COST);
9680 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9681 ins_encode %{
9682 Label* L = $labl$$label;
9683 assert(__ use_cbcond(*L), "back to back cbcond");
9684 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9685 %}
9686 ins_short_branch(1);
9687 ins_avoid_back_to_back(1);
9688 ins_pipe(cbcond_reg_imm);
9689 %}
9691 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9692 match(If cmp (CmpL op1 op2));
9693 predicate(UseCBCond);
9694 effect(USE labl, KILL xcc);
9696 size(4);
9697 ins_cost(BRANCH_COST);
9698 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9699 ins_encode %{
9700 Label* L = $labl$$label;
9701 assert(__ use_cbcond(*L), "back to back cbcond");
9702 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9703 %}
9704 ins_short_branch(1);
9705 ins_avoid_back_to_back(1);
9706 ins_pipe(cbcond_reg_reg);
9707 %}
9709 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9710 match(If cmp (CmpL op1 op2));
9711 predicate(UseCBCond);
9712 effect(USE labl, KILL xcc);
9714 size(4);
9715 ins_cost(BRANCH_COST);
9716 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9717 ins_encode %{
9718 Label* L = $labl$$label;
9719 assert(__ use_cbcond(*L), "back to back cbcond");
9720 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9721 %}
9722 ins_short_branch(1);
9723 ins_avoid_back_to_back(1);
9724 ins_pipe(cbcond_reg_imm);
9725 %}
9727 // Compare Pointers and branch
9728 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9729 match(If cmp (CmpP op1 op2));
9730 predicate(UseCBCond);
9731 effect(USE labl, KILL pcc);
9733 size(4);
9734 ins_cost(BRANCH_COST);
9735 #ifdef _LP64
9736 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9737 #else
9738 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9739 #endif
9740 ins_encode %{
9741 Label* L = $labl$$label;
9742 assert(__ use_cbcond(*L), "back to back cbcond");
9743 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9744 %}
9745 ins_short_branch(1);
9746 ins_avoid_back_to_back(1);
9747 ins_pipe(cbcond_reg_reg);
9748 %}
9750 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9751 match(If cmp (CmpP op1 null));
9752 predicate(UseCBCond);
9753 effect(USE labl, KILL pcc);
9755 size(4);
9756 ins_cost(BRANCH_COST);
9757 #ifdef _LP64
9758 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9759 #else
9760 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9761 #endif
9762 ins_encode %{
9763 Label* L = $labl$$label;
9764 assert(__ use_cbcond(*L), "back to back cbcond");
9765 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9766 %}
9767 ins_short_branch(1);
9768 ins_avoid_back_to_back(1);
9769 ins_pipe(cbcond_reg_reg);
9770 %}
9772 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9773 match(If cmp (CmpN op1 op2));
9774 predicate(UseCBCond);
9775 effect(USE labl, KILL icc);
9777 size(4);
9778 ins_cost(BRANCH_COST);
9779 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9780 ins_encode %{
9781 Label* L = $labl$$label;
9782 assert(__ use_cbcond(*L), "back to back cbcond");
9783 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9784 %}
9785 ins_short_branch(1);
9786 ins_avoid_back_to_back(1);
9787 ins_pipe(cbcond_reg_reg);
9788 %}
9790 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9791 match(If cmp (CmpN op1 null));
9792 predicate(UseCBCond);
9793 effect(USE labl, KILL icc);
9795 size(4);
9796 ins_cost(BRANCH_COST);
9797 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9798 ins_encode %{
9799 Label* L = $labl$$label;
9800 assert(__ use_cbcond(*L), "back to back cbcond");
9801 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9802 %}
9803 ins_short_branch(1);
9804 ins_avoid_back_to_back(1);
9805 ins_pipe(cbcond_reg_reg);
9806 %}
9808 // Loop back branch
9809 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9810 match(CountedLoopEnd cmp (CmpI op1 op2));
9811 predicate(UseCBCond);
9812 effect(USE labl, KILL icc);
9814 size(4);
9815 ins_cost(BRANCH_COST);
9816 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9817 ins_encode %{
9818 Label* L = $labl$$label;
9819 assert(__ use_cbcond(*L), "back to back cbcond");
9820 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9821 %}
9822 ins_short_branch(1);
9823 ins_avoid_back_to_back(1);
9824 ins_pipe(cbcond_reg_reg);
9825 %}
9827 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9828 match(CountedLoopEnd cmp (CmpI op1 op2));
9829 predicate(UseCBCond);
9830 effect(USE labl, KILL icc);
9832 size(4);
9833 ins_cost(BRANCH_COST);
9834 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9835 ins_encode %{
9836 Label* L = $labl$$label;
9837 assert(__ use_cbcond(*L), "back to back cbcond");
9838 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9839 %}
9840 ins_short_branch(1);
9841 ins_avoid_back_to_back(1);
9842 ins_pipe(cbcond_reg_imm);
9843 %}
9845 // Branch-on-register tests all 64 bits. We assume that values
9846 // in 64-bit registers always remains zero or sign extended
9847 // unless our code munges the high bits. Interrupts can chop
9848 // the high order bits to zero or sign at any time.
9849 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9850 match(If cmp (CmpI op1 zero));
9851 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9852 effect(USE labl);
9854 size(8);
9855 ins_cost(BRANCH_COST);
9856 format %{ "BR$cmp $op1,$labl" %}
9857 ins_encode( enc_bpr( labl, cmp, op1 ) );
9858 ins_pipe(br_reg);
9859 %}
9861 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9862 match(If cmp (CmpP op1 null));
9863 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9864 effect(USE labl);
9866 size(8);
9867 ins_cost(BRANCH_COST);
9868 format %{ "BR$cmp $op1,$labl" %}
9869 ins_encode( enc_bpr( labl, cmp, op1 ) );
9870 ins_pipe(br_reg);
9871 %}
9873 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9874 match(If cmp (CmpL op1 zero));
9875 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9876 effect(USE labl);
9878 size(8);
9879 ins_cost(BRANCH_COST);
9880 format %{ "BR$cmp $op1,$labl" %}
9881 ins_encode( enc_bpr( labl, cmp, op1 ) );
9882 ins_pipe(br_reg);
9883 %}
9886 // ============================================================================
9887 // Long Compare
9888 //
9889 // Currently we hold longs in 2 registers. Comparing such values efficiently
9890 // is tricky. The flavor of compare used depends on whether we are testing
9891 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9892 // The GE test is the negated LT test. The LE test can be had by commuting
9893 // the operands (yielding a GE test) and then negating; negate again for the
9894 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9895 // NE test is negated from that.
9897 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9898 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9899 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9900 // are collapsed internally in the ADLC's dfa-gen code. The match for
9901 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9902 // foo match ends up with the wrong leaf. One fix is to not match both
9903 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9904 // both forms beat the trinary form of long-compare and both are very useful
9905 // on Intel which has so few registers.
9907 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9908 match(If cmp xcc);
9909 effect(USE labl);
9911 size(8);
9912 ins_cost(BRANCH_COST);
9913 format %{ "BP$cmp $xcc,$labl" %}
9914 ins_encode %{
9915 Label* L = $labl$$label;
9916 Assembler::Predict predict_taken =
9917 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9919 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9920 __ delayed()->nop();
9921 %}
9922 ins_pipe(br_cc);
9923 %}
9925 // Manifest a CmpL3 result in an integer register. Very painful.
9926 // This is the test to avoid.
9927 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9928 match(Set dst (CmpL3 src1 src2) );
9929 effect( KILL ccr );
9930 ins_cost(6*DEFAULT_COST);
9931 size(24);
9932 format %{ "CMP $src1,$src2\t\t! long\n"
9933 "\tBLT,a,pn done\n"
9934 "\tMOV -1,$dst\t! delay slot\n"
9935 "\tBGT,a,pn done\n"
9936 "\tMOV 1,$dst\t! delay slot\n"
9937 "\tCLR $dst\n"
9938 "done:" %}
9939 ins_encode( cmpl_flag(src1,src2,dst) );
9940 ins_pipe(cmpL_reg);
9941 %}
9943 // Conditional move
9944 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9945 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9946 ins_cost(150);
9947 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9948 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9949 ins_pipe(ialu_reg);
9950 %}
9952 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9953 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9954 ins_cost(140);
9955 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9956 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9957 ins_pipe(ialu_imm);
9958 %}
9960 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9961 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9962 ins_cost(150);
9963 format %{ "MOV$cmp $xcc,$src,$dst" %}
9964 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9965 ins_pipe(ialu_reg);
9966 %}
9968 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9969 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9970 ins_cost(140);
9971 format %{ "MOV$cmp $xcc,$src,$dst" %}
9972 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9973 ins_pipe(ialu_imm);
9974 %}
9976 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9977 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9978 ins_cost(150);
9979 format %{ "MOV$cmp $xcc,$src,$dst" %}
9980 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9981 ins_pipe(ialu_reg);
9982 %}
9984 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9985 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9986 ins_cost(150);
9987 format %{ "MOV$cmp $xcc,$src,$dst" %}
9988 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9989 ins_pipe(ialu_reg);
9990 %}
9992 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9993 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9994 ins_cost(140);
9995 format %{ "MOV$cmp $xcc,$src,$dst" %}
9996 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9997 ins_pipe(ialu_imm);
9998 %}
10000 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
10001 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
10002 ins_cost(150);
10003 opcode(0x101);
10004 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
10005 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
10006 ins_pipe(int_conditional_float_move);
10007 %}
10009 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
10010 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
10011 ins_cost(150);
10012 opcode(0x102);
10013 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
10014 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
10015 ins_pipe(int_conditional_float_move);
10016 %}
10018 // ============================================================================
10019 // Safepoint Instruction
10020 instruct safePoint_poll(iRegP poll) %{
10021 match(SafePoint poll);
10022 effect(USE poll);
10024 size(4);
10025 #ifdef _LP64
10026 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
10027 #else
10028 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
10029 #endif
10030 ins_encode %{
10031 __ relocate(relocInfo::poll_type);
10032 __ ld_ptr($poll$$Register, 0, G0);
10033 %}
10034 ins_pipe(loadPollP);
10035 %}
10037 // ============================================================================
10038 // Call Instructions
10039 // Call Java Static Instruction
10040 instruct CallStaticJavaDirect( method meth ) %{
10041 match(CallStaticJava);
10042 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
10043 effect(USE meth);
10045 size(8);
10046 ins_cost(CALL_COST);
10047 format %{ "CALL,static ; NOP ==> " %}
10048 ins_encode( Java_Static_Call( meth ), call_epilog );
10049 ins_pipe(simple_call);
10050 %}
10052 // Call Java Static Instruction (method handle version)
10053 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
10054 match(CallStaticJava);
10055 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
10056 effect(USE meth, KILL l7_mh_SP_save);
10058 size(16);
10059 ins_cost(CALL_COST);
10060 format %{ "CALL,static/MethodHandle" %}
10061 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
10062 ins_pipe(simple_call);
10063 %}
10065 // Call Java Dynamic Instruction
10066 instruct CallDynamicJavaDirect( method meth ) %{
10067 match(CallDynamicJava);
10068 effect(USE meth);
10070 ins_cost(CALL_COST);
10071 format %{ "SET (empty),R_G5\n\t"
10072 "CALL,dynamic ; NOP ==> " %}
10073 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
10074 ins_pipe(call);
10075 %}
10077 // Call Runtime Instruction
10078 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10079 match(CallRuntime);
10080 effect(USE meth, KILL l7);
10081 ins_cost(CALL_COST);
10082 format %{ "CALL,runtime" %}
10083 ins_encode( Java_To_Runtime( meth ),
10084 call_epilog, adjust_long_from_native_call );
10085 ins_pipe(simple_call);
10086 %}
10088 // Call runtime without safepoint - same as CallRuntime
10089 instruct CallLeafDirect(method meth, l7RegP l7) %{
10090 match(CallLeaf);
10091 effect(USE meth, KILL l7);
10092 ins_cost(CALL_COST);
10093 format %{ "CALL,runtime leaf" %}
10094 ins_encode( Java_To_Runtime( meth ),
10095 call_epilog,
10096 adjust_long_from_native_call );
10097 ins_pipe(simple_call);
10098 %}
10100 // Call runtime without safepoint - same as CallLeaf
10101 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10102 match(CallLeafNoFP);
10103 effect(USE meth, KILL l7);
10104 ins_cost(CALL_COST);
10105 format %{ "CALL,runtime leaf nofp" %}
10106 ins_encode( Java_To_Runtime( meth ),
10107 call_epilog,
10108 adjust_long_from_native_call );
10109 ins_pipe(simple_call);
10110 %}
10112 // Tail Call; Jump from runtime stub to Java code.
10113 // Also known as an 'interprocedural jump'.
10114 // Target of jump will eventually return to caller.
10115 // TailJump below removes the return address.
10116 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10117 match(TailCall jump_target method_oop );
10119 ins_cost(CALL_COST);
10120 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10121 ins_encode(form_jmpl(jump_target));
10122 ins_pipe(tail_call);
10123 %}
10126 // Return Instruction
10127 instruct Ret() %{
10128 match(Return);
10130 // The epilogue node did the ret already.
10131 size(0);
10132 format %{ "! return" %}
10133 ins_encode();
10134 ins_pipe(empty);
10135 %}
10138 // Tail Jump; remove the return address; jump to target.
10139 // TailCall above leaves the return address around.
10140 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10141 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10142 // "restore" before this instruction (in Epilogue), we need to materialize it
10143 // in %i0.
10144 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10145 match( TailJump jump_target ex_oop );
10146 ins_cost(CALL_COST);
10147 format %{ "! discard R_O7\n\t"
10148 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10149 ins_encode(form_jmpl_set_exception_pc(jump_target));
10150 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10151 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10152 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10153 ins_pipe(tail_call);
10154 %}
10156 // Create exception oop: created by stack-crawling runtime code.
10157 // Created exception is now available to this handler, and is setup
10158 // just prior to jumping to this handler. No code emitted.
10159 instruct CreateException( o0RegP ex_oop )
10160 %{
10161 match(Set ex_oop (CreateEx));
10162 ins_cost(0);
10164 size(0);
10165 // use the following format syntax
10166 format %{ "! exception oop is in R_O0; no code emitted" %}
10167 ins_encode();
10168 ins_pipe(empty);
10169 %}
10172 // Rethrow exception:
10173 // The exception oop will come in the first argument position.
10174 // Then JUMP (not call) to the rethrow stub code.
10175 instruct RethrowException()
10176 %{
10177 match(Rethrow);
10178 ins_cost(CALL_COST);
10180 // use the following format syntax
10181 format %{ "Jmp rethrow_stub" %}
10182 ins_encode(enc_rethrow);
10183 ins_pipe(tail_call);
10184 %}
10187 // Die now
10188 instruct ShouldNotReachHere( )
10189 %{
10190 match(Halt);
10191 ins_cost(CALL_COST);
10193 size(4);
10194 // Use the following format syntax
10195 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10196 ins_encode( form2_illtrap() );
10197 ins_pipe(tail_call);
10198 %}
10200 // ============================================================================
10201 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10202 // array for an instance of the superklass. Set a hidden internal cache on a
10203 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10204 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10205 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10206 match(Set index (PartialSubtypeCheck sub super));
10207 effect( KILL pcc, KILL o7 );
10208 ins_cost(DEFAULT_COST*10);
10209 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10210 ins_encode( enc_PartialSubtypeCheck() );
10211 ins_pipe(partial_subtype_check_pipe);
10212 %}
10214 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10215 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10216 effect( KILL idx, KILL o7 );
10217 ins_cost(DEFAULT_COST*10);
10218 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10219 ins_encode( enc_PartialSubtypeCheck() );
10220 ins_pipe(partial_subtype_check_pipe);
10221 %}
10224 // ============================================================================
10225 // inlined locking and unlocking
10227 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
10228 match(Set pcc (FastLock object box));
10230 effect(KILL scratch, TEMP scratch2);
10231 ins_cost(100);
10233 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
10234 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10235 ins_pipe(long_memory_op);
10236 %}
10239 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
10240 match(Set pcc (FastUnlock object box));
10241 effect(KILL scratch, TEMP scratch2);
10242 ins_cost(100);
10244 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
10245 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10246 ins_pipe(long_memory_op);
10247 %}
10249 // The encodings are generic.
10250 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10251 predicate(!use_block_zeroing(n->in(2)) );
10252 match(Set dummy (ClearArray cnt base));
10253 effect(TEMP temp, KILL ccr);
10254 ins_cost(300);
10255 format %{ "MOV $cnt,$temp\n"
10256 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10257 " BRge loop\t\t! Clearing loop\n"
10258 " STX G0,[$base+$temp]\t! delay slot" %}
10260 ins_encode %{
10261 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10262 Register nof_bytes_arg = $cnt$$Register;
10263 Register nof_bytes_tmp = $temp$$Register;
10264 Register base_pointer_arg = $base$$Register;
10266 Label loop;
10267 __ mov(nof_bytes_arg, nof_bytes_tmp);
10269 // Loop and clear, walking backwards through the array.
10270 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10271 __ bind(loop);
10272 __ deccc(nof_bytes_tmp, 8);
10273 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10274 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10275 // %%%% this mini-loop must not cross a cache boundary!
10276 %}
10277 ins_pipe(long_memory_op);
10278 %}
10280 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10281 predicate(use_block_zeroing(n->in(2)));
10282 match(Set dummy (ClearArray cnt base));
10283 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10284 ins_cost(300);
10285 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10287 ins_encode %{
10289 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10290 Register to = $base$$Register;
10291 Register count = $cnt$$Register;
10293 Label Ldone;
10294 __ nop(); // Separate short branches
10295 // Use BIS for zeroing (temp is not used).
10296 __ bis_zeroing(to, count, G0, Ldone);
10297 __ bind(Ldone);
10299 %}
10300 ins_pipe(long_memory_op);
10301 %}
10303 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10304 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10305 match(Set dummy (ClearArray cnt base));
10306 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10307 ins_cost(300);
10308 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10310 ins_encode %{
10312 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10313 Register to = $base$$Register;
10314 Register count = $cnt$$Register;
10315 Register temp = $tmp$$Register;
10317 Label Ldone;
10318 __ nop(); // Separate short branches
10319 // Use BIS for zeroing
10320 __ bis_zeroing(to, count, temp, Ldone);
10321 __ bind(Ldone);
10323 %}
10324 ins_pipe(long_memory_op);
10325 %}
10327 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10328 o7RegI tmp, flagsReg ccr) %{
10329 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10330 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10331 ins_cost(300);
10332 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10333 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10334 ins_pipe(long_memory_op);
10335 %}
10337 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10338 o7RegI tmp, flagsReg ccr) %{
10339 match(Set result (StrEquals (Binary str1 str2) cnt));
10340 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10341 ins_cost(300);
10342 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10343 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10344 ins_pipe(long_memory_op);
10345 %}
10347 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10348 o7RegI tmp2, flagsReg ccr) %{
10349 match(Set result (AryEq ary1 ary2));
10350 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10351 ins_cost(300);
10352 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10353 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10354 ins_pipe(long_memory_op);
10355 %}
10358 //---------- Zeros Count Instructions ------------------------------------------
10360 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10361 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10362 match(Set dst (CountLeadingZerosI src));
10363 effect(TEMP dst, TEMP tmp, KILL cr);
10365 // x |= (x >> 1);
10366 // x |= (x >> 2);
10367 // x |= (x >> 4);
10368 // x |= (x >> 8);
10369 // x |= (x >> 16);
10370 // return (WORDBITS - popc(x));
10371 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10372 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10373 "OR $dst,$tmp,$dst\n\t"
10374 "SRL $dst,2,$tmp\n\t"
10375 "OR $dst,$tmp,$dst\n\t"
10376 "SRL $dst,4,$tmp\n\t"
10377 "OR $dst,$tmp,$dst\n\t"
10378 "SRL $dst,8,$tmp\n\t"
10379 "OR $dst,$tmp,$dst\n\t"
10380 "SRL $dst,16,$tmp\n\t"
10381 "OR $dst,$tmp,$dst\n\t"
10382 "POPC $dst,$dst\n\t"
10383 "MOV 32,$tmp\n\t"
10384 "SUB $tmp,$dst,$dst" %}
10385 ins_encode %{
10386 Register Rdst = $dst$$Register;
10387 Register Rsrc = $src$$Register;
10388 Register Rtmp = $tmp$$Register;
10389 __ srl(Rsrc, 1, Rtmp);
10390 __ srl(Rsrc, 0, Rdst);
10391 __ or3(Rdst, Rtmp, Rdst);
10392 __ srl(Rdst, 2, Rtmp);
10393 __ or3(Rdst, Rtmp, Rdst);
10394 __ srl(Rdst, 4, Rtmp);
10395 __ or3(Rdst, Rtmp, Rdst);
10396 __ srl(Rdst, 8, Rtmp);
10397 __ or3(Rdst, Rtmp, Rdst);
10398 __ srl(Rdst, 16, Rtmp);
10399 __ or3(Rdst, Rtmp, Rdst);
10400 __ popc(Rdst, Rdst);
10401 __ mov(BitsPerInt, Rtmp);
10402 __ sub(Rtmp, Rdst, Rdst);
10403 %}
10404 ins_pipe(ialu_reg);
10405 %}
10407 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10408 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10409 match(Set dst (CountLeadingZerosL src));
10410 effect(TEMP dst, TEMP tmp, KILL cr);
10412 // x |= (x >> 1);
10413 // x |= (x >> 2);
10414 // x |= (x >> 4);
10415 // x |= (x >> 8);
10416 // x |= (x >> 16);
10417 // x |= (x >> 32);
10418 // return (WORDBITS - popc(x));
10419 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10420 "OR $src,$tmp,$dst\n\t"
10421 "SRLX $dst,2,$tmp\n\t"
10422 "OR $dst,$tmp,$dst\n\t"
10423 "SRLX $dst,4,$tmp\n\t"
10424 "OR $dst,$tmp,$dst\n\t"
10425 "SRLX $dst,8,$tmp\n\t"
10426 "OR $dst,$tmp,$dst\n\t"
10427 "SRLX $dst,16,$tmp\n\t"
10428 "OR $dst,$tmp,$dst\n\t"
10429 "SRLX $dst,32,$tmp\n\t"
10430 "OR $dst,$tmp,$dst\n\t"
10431 "POPC $dst,$dst\n\t"
10432 "MOV 64,$tmp\n\t"
10433 "SUB $tmp,$dst,$dst" %}
10434 ins_encode %{
10435 Register Rdst = $dst$$Register;
10436 Register Rsrc = $src$$Register;
10437 Register Rtmp = $tmp$$Register;
10438 __ srlx(Rsrc, 1, Rtmp);
10439 __ or3( Rsrc, Rtmp, Rdst);
10440 __ srlx(Rdst, 2, Rtmp);
10441 __ or3( Rdst, Rtmp, Rdst);
10442 __ srlx(Rdst, 4, Rtmp);
10443 __ or3( Rdst, Rtmp, Rdst);
10444 __ srlx(Rdst, 8, Rtmp);
10445 __ or3( Rdst, Rtmp, Rdst);
10446 __ srlx(Rdst, 16, Rtmp);
10447 __ or3( Rdst, Rtmp, Rdst);
10448 __ srlx(Rdst, 32, Rtmp);
10449 __ or3( Rdst, Rtmp, Rdst);
10450 __ popc(Rdst, Rdst);
10451 __ mov(BitsPerLong, Rtmp);
10452 __ sub(Rtmp, Rdst, Rdst);
10453 %}
10454 ins_pipe(ialu_reg);
10455 %}
10457 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
10458 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10459 match(Set dst (CountTrailingZerosI src));
10460 effect(TEMP dst, KILL cr);
10462 // return popc(~x & (x - 1));
10463 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10464 "ANDN $dst,$src,$dst\n\t"
10465 "SRL $dst,R_G0,$dst\n\t"
10466 "POPC $dst,$dst" %}
10467 ins_encode %{
10468 Register Rdst = $dst$$Register;
10469 Register Rsrc = $src$$Register;
10470 __ sub(Rsrc, 1, Rdst);
10471 __ andn(Rdst, Rsrc, Rdst);
10472 __ srl(Rdst, G0, Rdst);
10473 __ popc(Rdst, Rdst);
10474 %}
10475 ins_pipe(ialu_reg);
10476 %}
10478 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
10479 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10480 match(Set dst (CountTrailingZerosL src));
10481 effect(TEMP dst, KILL cr);
10483 // return popc(~x & (x - 1));
10484 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10485 "ANDN $dst,$src,$dst\n\t"
10486 "POPC $dst,$dst" %}
10487 ins_encode %{
10488 Register Rdst = $dst$$Register;
10489 Register Rsrc = $src$$Register;
10490 __ sub(Rsrc, 1, Rdst);
10491 __ andn(Rdst, Rsrc, Rdst);
10492 __ popc(Rdst, Rdst);
10493 %}
10494 ins_pipe(ialu_reg);
10495 %}
10498 //---------- Population Count Instructions -------------------------------------
10500 instruct popCountI(iRegI dst, iRegI src) %{
10501 predicate(UsePopCountInstruction);
10502 match(Set dst (PopCountI src));
10504 format %{ "POPC $src, $dst" %}
10505 ins_encode %{
10506 __ popc($src$$Register, $dst$$Register);
10507 %}
10508 ins_pipe(ialu_reg);
10509 %}
10511 // Note: Long.bitCount(long) returns an int.
10512 instruct popCountL(iRegI dst, iRegL src) %{
10513 predicate(UsePopCountInstruction);
10514 match(Set dst (PopCountL src));
10516 format %{ "POPC $src, $dst" %}
10517 ins_encode %{
10518 __ popc($src$$Register, $dst$$Register);
10519 %}
10520 ins_pipe(ialu_reg);
10521 %}
10524 // ============================================================================
10525 //------------Bytes reverse--------------------------------------------------
10527 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10528 match(Set dst (ReverseBytesI src));
10530 // Op cost is artificially doubled to make sure that load or store
10531 // instructions are preferred over this one which requires a spill
10532 // onto a stack slot.
10533 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10534 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10536 ins_encode %{
10537 __ set($src$$disp + STACK_BIAS, O7);
10538 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10539 %}
10540 ins_pipe( iload_mem );
10541 %}
10543 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10544 match(Set dst (ReverseBytesL src));
10546 // Op cost is artificially doubled to make sure that load or store
10547 // instructions are preferred over this one which requires a spill
10548 // onto a stack slot.
10549 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10550 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10552 ins_encode %{
10553 __ set($src$$disp + STACK_BIAS, O7);
10554 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10555 %}
10556 ins_pipe( iload_mem );
10557 %}
10559 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10560 match(Set dst (ReverseBytesUS src));
10562 // Op cost is artificially doubled to make sure that load or store
10563 // instructions are preferred over this one which requires a spill
10564 // onto a stack slot.
10565 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10566 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10568 ins_encode %{
10569 // the value was spilled as an int so bias the load
10570 __ set($src$$disp + STACK_BIAS + 2, O7);
10571 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10572 %}
10573 ins_pipe( iload_mem );
10574 %}
10576 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10577 match(Set dst (ReverseBytesS src));
10579 // Op cost is artificially doubled to make sure that load or store
10580 // instructions are preferred over this one which requires a spill
10581 // onto a stack slot.
10582 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10583 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10585 ins_encode %{
10586 // the value was spilled as an int so bias the load
10587 __ set($src$$disp + STACK_BIAS + 2, O7);
10588 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10589 %}
10590 ins_pipe( iload_mem );
10591 %}
10593 // Load Integer reversed byte order
10594 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10595 match(Set dst (ReverseBytesI (LoadI src)));
10597 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10598 size(4);
10599 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10601 ins_encode %{
10602 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10603 %}
10604 ins_pipe(iload_mem);
10605 %}
10607 // Load Long - aligned and reversed
10608 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10609 match(Set dst (ReverseBytesL (LoadL src)));
10611 ins_cost(MEMORY_REF_COST);
10612 size(4);
10613 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10615 ins_encode %{
10616 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10617 %}
10618 ins_pipe(iload_mem);
10619 %}
10621 // Load unsigned short / char reversed byte order
10622 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10623 match(Set dst (ReverseBytesUS (LoadUS src)));
10625 ins_cost(MEMORY_REF_COST);
10626 size(4);
10627 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10629 ins_encode %{
10630 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10631 %}
10632 ins_pipe(iload_mem);
10633 %}
10635 // Load short reversed byte order
10636 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10637 match(Set dst (ReverseBytesS (LoadS src)));
10639 ins_cost(MEMORY_REF_COST);
10640 size(4);
10641 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10643 ins_encode %{
10644 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10645 %}
10646 ins_pipe(iload_mem);
10647 %}
10649 // Store Integer reversed byte order
10650 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10651 match(Set dst (StoreI dst (ReverseBytesI src)));
10653 ins_cost(MEMORY_REF_COST);
10654 size(4);
10655 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10657 ins_encode %{
10658 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10659 %}
10660 ins_pipe(istore_mem_reg);
10661 %}
10663 // Store Long reversed byte order
10664 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10665 match(Set dst (StoreL dst (ReverseBytesL src)));
10667 ins_cost(MEMORY_REF_COST);
10668 size(4);
10669 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10671 ins_encode %{
10672 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10673 %}
10674 ins_pipe(istore_mem_reg);
10675 %}
10677 // Store unsighed short/char reversed byte order
10678 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10679 match(Set dst (StoreC dst (ReverseBytesUS src)));
10681 ins_cost(MEMORY_REF_COST);
10682 size(4);
10683 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10685 ins_encode %{
10686 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10687 %}
10688 ins_pipe(istore_mem_reg);
10689 %}
10691 // Store short reversed byte order
10692 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10693 match(Set dst (StoreC dst (ReverseBytesS src)));
10695 ins_cost(MEMORY_REF_COST);
10696 size(4);
10697 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10699 ins_encode %{
10700 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10701 %}
10702 ins_pipe(istore_mem_reg);
10703 %}
10705 //----------PEEPHOLE RULES-----------------------------------------------------
10706 // These must follow all instruction definitions as they use the names
10707 // defined in the instructions definitions.
10708 //
10709 // peepmatch ( root_instr_name [preceding_instruction]* );
10710 //
10711 // peepconstraint %{
10712 // (instruction_number.operand_name relational_op instruction_number.operand_name
10713 // [, ...] );
10714 // // instruction numbers are zero-based using left to right order in peepmatch
10715 //
10716 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10717 // // provide an instruction_number.operand_name for each operand that appears
10718 // // in the replacement instruction's match rule
10719 //
10720 // ---------VM FLAGS---------------------------------------------------------
10721 //
10722 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10723 //
10724 // Each peephole rule is given an identifying number starting with zero and
10725 // increasing by one in the order seen by the parser. An individual peephole
10726 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10727 // on the command-line.
10728 //
10729 // ---------CURRENT LIMITATIONS----------------------------------------------
10730 //
10731 // Only match adjacent instructions in same basic block
10732 // Only equality constraints
10733 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10734 // Only one replacement instruction
10735 //
10736 // ---------EXAMPLE----------------------------------------------------------
10737 //
10738 // // pertinent parts of existing instructions in architecture description
10739 // instruct movI(eRegI dst, eRegI src) %{
10740 // match(Set dst (CopyI src));
10741 // %}
10742 //
10743 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10744 // match(Set dst (AddI dst src));
10745 // effect(KILL cr);
10746 // %}
10747 //
10748 // // Change (inc mov) to lea
10749 // peephole %{
10750 // // increment preceeded by register-register move
10751 // peepmatch ( incI_eReg movI );
10752 // // require that the destination register of the increment
10753 // // match the destination register of the move
10754 // peepconstraint ( 0.dst == 1.dst );
10755 // // construct a replacement instruction that sets
10756 // // the destination to ( move's source register + one )
10757 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10758 // %}
10759 //
10761 // // Change load of spilled value to only a spill
10762 // instruct storeI(memory mem, eRegI src) %{
10763 // match(Set mem (StoreI mem src));
10764 // %}
10765 //
10766 // instruct loadI(eRegI dst, memory mem) %{
10767 // match(Set dst (LoadI mem));
10768 // %}
10769 //
10770 // peephole %{
10771 // peepmatch ( loadI storeI );
10772 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10773 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10774 // %}
10776 //----------SMARTSPILL RULES---------------------------------------------------
10777 // These must follow all instruction definitions as they use the names
10778 // defined in the instructions definitions.
10779 //
10780 // SPARC will probably not have any of these rules due to RISC instruction set.
10782 //----------PIPELINE-----------------------------------------------------------
10783 // Rules which define the behavior of the target architectures pipeline.