Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/x86/vm/x86_64.ad@b744678d4d71
src/cpu/x86/vm/x86_64.ad
Fri, 10 Oct 2008 09:47:56 -0700
- author
- rasbold
- date
- Fri, 10 Oct 2008 09:47:56 -0700
- changeset 838
- b744678d4d71
- parent 739
- dc7f315e41f7
- child 850
- 4d9884b01ba6
- permissions
- -rw-r--r--
6752257: Use NOT instead of XOR -1 on x86
Summary: add match rule for xor -1
Reviewed-by: never, kvn
1 //
2 // Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // AMD64 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
89 #ifdef _WIN64
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
97 #else
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
105 #endif
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
132 // Floating Point Registers
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
135 // Word a in each register holds a Float, words ab hold a Double. We
136 // currently do not use the SIMD capabilities, so registers cd are
137 // unused at the moment.
138 // XMM8-XMM15 must be encoded with REX.
139 // Linux ABI: No register preserved across function calls
140 // XMM0-XMM7 might hold parameters
141 // Windows ABI: XMM6-XMM15 preserved across function calls
142 // XMM0-XMM3 might hold parameters
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
162 #ifdef _WIN64
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
194 #else
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
226 #endif // _WIN64
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
230 // Specify priority of register selection within phases of register
231 // allocation. Highest priority is first. A useful heuristic is to
232 // give registers a low priority when they are required by machine
233 // instructions, like EAX and EDX on I486, and choose no-save registers
234 // before save-on-call, & save-on-call before save-on-entry. Registers
235 // which participate in fixed calling sequences should come last.
236 // Registers which are used as pairs must fall on an even boundary.
238 alloc_class chunk0(R10, R10_H,
239 R11, R11_H,
240 R8, R8_H,
241 R9, R9_H,
242 R12, R12_H,
243 RCX, RCX_H,
244 RBX, RBX_H,
245 RDI, RDI_H,
246 RDX, RDX_H,
247 RSI, RSI_H,
248 RAX, RAX_H,
249 RBP, RBP_H,
250 R13, R13_H,
251 R14, R14_H,
252 R15, R15_H,
253 RSP, RSP_H);
255 // XXX probably use 8-15 first on Linux
256 alloc_class chunk1(XMM0, XMM0_H,
257 XMM1, XMM1_H,
258 XMM2, XMM2_H,
259 XMM3, XMM3_H,
260 XMM4, XMM4_H,
261 XMM5, XMM5_H,
262 XMM6, XMM6_H,
263 XMM7, XMM7_H,
264 XMM8, XMM8_H,
265 XMM9, XMM9_H,
266 XMM10, XMM10_H,
267 XMM11, XMM11_H,
268 XMM12, XMM12_H,
269 XMM13, XMM13_H,
270 XMM14, XMM14_H,
271 XMM15, XMM15_H);
273 alloc_class chunk2(RFLAGS);
276 //----------Architecture Description Register Classes--------------------------
277 // Several register classes are automatically defined based upon information in
278 // this architecture description.
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // Class for all pointer registers (including RSP)
286 reg_class any_reg(RAX, RAX_H,
287 RDX, RDX_H,
288 RBP, RBP_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 RBX, RBX_H,
293 RSP, RSP_H,
294 R8, R8_H,
295 R9, R9_H,
296 R10, R10_H,
297 R11, R11_H,
298 R12, R12_H,
299 R13, R13_H,
300 R14, R14_H,
301 R15, R15_H);
303 // Class for all pointer registers except RSP
304 reg_class ptr_reg(RAX, RAX_H,
305 RDX, RDX_H,
306 RBP, RBP_H,
307 RDI, RDI_H,
308 RSI, RSI_H,
309 RCX, RCX_H,
310 RBX, RBX_H,
311 R8, R8_H,
312 R9, R9_H,
313 R10, R10_H,
314 R11, R11_H,
315 R13, R13_H,
316 R14, R14_H);
318 // Class for all pointer registers except RAX and RSP
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
320 RBP, RBP_H,
321 RDI, RDI_H,
322 RSI, RSI_H,
323 RCX, RCX_H,
324 RBX, RBX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R12, R12_H,
330 R13, R13_H,
331 R14, R14_H);
333 reg_class ptr_no_rbp_reg(RDX, RDX_H,
334 RAX, RAX_H,
335 RDI, RDI_H,
336 RSI, RSI_H,
337 RCX, RCX_H,
338 RBX, RBX_H,
339 R8, R8_H,
340 R9, R9_H,
341 R10, R10_H,
342 R11, R11_H,
343 R12, R12_H,
344 R13, R13_H,
345 R14, R14_H);
347 // Class for all pointer registers except RAX, RBX and RSP
348 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
349 RBP, RBP_H,
350 RDI, RDI_H,
351 RSI, RSI_H,
352 RCX, RCX_H,
353 R8, R8_H,
354 R9, R9_H,
355 R10, R10_H,
356 R11, R11_H,
357 R12, R12_H,
358 R13, R13_H,
359 R14, R14_H);
361 // Singleton class for RAX pointer register
362 reg_class ptr_rax_reg(RAX, RAX_H);
364 // Singleton class for RBX pointer register
365 reg_class ptr_rbx_reg(RBX, RBX_H);
367 // Singleton class for RSI pointer register
368 reg_class ptr_rsi_reg(RSI, RSI_H);
370 // Singleton class for RDI pointer register
371 reg_class ptr_rdi_reg(RDI, RDI_H);
373 // Singleton class for RBP pointer register
374 reg_class ptr_rbp_reg(RBP, RBP_H);
376 // Singleton class for stack pointer
377 reg_class ptr_rsp_reg(RSP, RSP_H);
379 // Singleton class for TLS pointer
380 reg_class ptr_r15_reg(R15, R15_H);
382 // Class for all long registers (except RSP)
383 reg_class long_reg(RAX, RAX_H,
384 RDX, RDX_H,
385 RBP, RBP_H,
386 RDI, RDI_H,
387 RSI, RSI_H,
388 RCX, RCX_H,
389 RBX, RBX_H,
390 R8, R8_H,
391 R9, R9_H,
392 R10, R10_H,
393 R11, R11_H,
394 R13, R13_H,
395 R14, R14_H);
397 // Class for all long registers except RAX, RDX (and RSP)
398 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
399 RDI, RDI_H,
400 RSI, RSI_H,
401 RCX, RCX_H,
402 RBX, RBX_H,
403 R8, R8_H,
404 R9, R9_H,
405 R10, R10_H,
406 R11, R11_H,
407 R13, R13_H,
408 R14, R14_H);
410 // Class for all long registers except RCX (and RSP)
411 reg_class long_no_rcx_reg(RBP, RBP_H,
412 RDI, RDI_H,
413 RSI, RSI_H,
414 RAX, RAX_H,
415 RDX, RDX_H,
416 RBX, RBX_H,
417 R8, R8_H,
418 R9, R9_H,
419 R10, R10_H,
420 R11, R11_H,
421 R13, R13_H,
422 R14, R14_H);
424 // Class for all long registers except RAX (and RSP)
425 reg_class long_no_rax_reg(RBP, RBP_H,
426 RDX, RDX_H,
427 RDI, RDI_H,
428 RSI, RSI_H,
429 RCX, RCX_H,
430 RBX, RBX_H,
431 R8, R8_H,
432 R9, R9_H,
433 R10, R10_H,
434 R11, R11_H,
435 R13, R13_H,
436 R14, R14_H);
438 // Singleton class for RAX long register
439 reg_class long_rax_reg(RAX, RAX_H);
441 // Singleton class for RCX long register
442 reg_class long_rcx_reg(RCX, RCX_H);
444 // Singleton class for RDX long register
445 reg_class long_rdx_reg(RDX, RDX_H);
447 // Singleton class for R12 long register
448 reg_class long_r12_reg(R12, R12_H);
450 // Class for all int registers (except RSP)
451 reg_class int_reg(RAX,
452 RDX,
453 RBP,
454 RDI,
455 RSI,
456 RCX,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
465 // Class for all int registers except RCX (and RSP)
466 reg_class int_no_rcx_reg(RAX,
467 RDX,
468 RBP,
469 RDI,
470 RSI,
471 RBX,
472 R8,
473 R9,
474 R10,
475 R11,
476 R13,
477 R14);
479 // Class for all int registers except RAX, RDX (and RSP)
480 reg_class int_no_rax_rdx_reg(RBP,
481 RDI,
482 RSI,
483 RCX,
484 RBX,
485 R8,
486 R9,
487 R10,
488 R11,
489 R13,
490 R14);
492 // Singleton class for RAX int register
493 reg_class int_rax_reg(RAX);
495 // Singleton class for RBX int register
496 reg_class int_rbx_reg(RBX);
498 // Singleton class for RCX int register
499 reg_class int_rcx_reg(RCX);
501 // Singleton class for RCX int register
502 reg_class int_rdx_reg(RDX);
504 // Singleton class for RCX int register
505 reg_class int_rdi_reg(RDI);
507 // Singleton class for instruction pointer
508 // reg_class ip_reg(RIP);
510 // Singleton class for condition codes
511 reg_class int_flags(RFLAGS);
513 // Class for all float registers
514 reg_class float_reg(XMM0,
515 XMM1,
516 XMM2,
517 XMM3,
518 XMM4,
519 XMM5,
520 XMM6,
521 XMM7,
522 XMM8,
523 XMM9,
524 XMM10,
525 XMM11,
526 XMM12,
527 XMM13,
528 XMM14,
529 XMM15);
531 // Class for all double registers
532 reg_class double_reg(XMM0, XMM0_H,
533 XMM1, XMM1_H,
534 XMM2, XMM2_H,
535 XMM3, XMM3_H,
536 XMM4, XMM4_H,
537 XMM5, XMM5_H,
538 XMM6, XMM6_H,
539 XMM7, XMM7_H,
540 XMM8, XMM8_H,
541 XMM9, XMM9_H,
542 XMM10, XMM10_H,
543 XMM11, XMM11_H,
544 XMM12, XMM12_H,
545 XMM13, XMM13_H,
546 XMM14, XMM14_H,
547 XMM15, XMM15_H);
548 %}
551 //----------SOURCE BLOCK-------------------------------------------------------
552 // This is a block of C++ code which provides values, functions, and
553 // definitions necessary in the rest of the architecture description
554 source %{
555 #define RELOC_IMM64 Assembler::imm_operand
556 #define RELOC_DISP32 Assembler::disp32_operand
558 #define __ _masm.
560 // !!!!! Special hack to get all types of calls to specify the byte offset
561 // from the start of the call to the point where the return address
562 // will point.
563 int MachCallStaticJavaNode::ret_addr_offset()
564 {
565 return 5; // 5 bytes from start of call to where return address points
566 }
568 int MachCallDynamicJavaNode::ret_addr_offset()
569 {
570 return 15; // 15 bytes from start of call to where return address points
571 }
573 // In os_cpu .ad file
574 // int MachCallRuntimeNode::ret_addr_offset()
576 // Indicate if the safepoint node needs the polling page as an input.
577 // Since amd64 does not have absolute addressing but RIP-relative
578 // addressing and the polling page is within 2G, it doesn't.
579 bool SafePointNode::needs_polling_address_input()
580 {
581 return false;
582 }
584 //
585 // Compute padding required for nodes which need alignment
586 //
588 // The address of the call instruction needs to be 4-byte aligned to
589 // ensure that it does not span a cache line so that it can be patched.
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
591 {
592 current_offset += 1; // skip call opcode byte
593 return round_to(current_offset, alignment_required()) - current_offset;
594 }
596 // The address of the call instruction needs to be 4-byte aligned to
597 // ensure that it does not span a cache line so that it can be patched.
598 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
599 {
600 current_offset += 11; // skip movq instruction + call opcode byte
601 return round_to(current_offset, alignment_required()) - current_offset;
602 }
604 #ifndef PRODUCT
605 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
606 {
607 st->print("INT3");
608 }
609 #endif
611 // EMIT_RM()
612 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3)
613 {
614 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
615 *(cbuf.code_end()) = c;
616 cbuf.set_code_end(cbuf.code_end() + 1);
617 }
619 // EMIT_CC()
620 void emit_cc(CodeBuffer &cbuf, int f1, int f2)
621 {
622 unsigned char c = (unsigned char) (f1 | f2);
623 *(cbuf.code_end()) = c;
624 cbuf.set_code_end(cbuf.code_end() + 1);
625 }
627 // EMIT_OPCODE()
628 void emit_opcode(CodeBuffer &cbuf, int code)
629 {
630 *(cbuf.code_end()) = (unsigned char) code;
631 cbuf.set_code_end(cbuf.code_end() + 1);
632 }
634 // EMIT_OPCODE() w/ relocation information
635 void emit_opcode(CodeBuffer &cbuf,
636 int code, relocInfo::relocType reloc, int offset, int format)
637 {
638 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format);
639 emit_opcode(cbuf, code);
640 }
642 // EMIT_D8()
643 void emit_d8(CodeBuffer &cbuf, int d8)
644 {
645 *(cbuf.code_end()) = (unsigned char) d8;
646 cbuf.set_code_end(cbuf.code_end() + 1);
647 }
649 // EMIT_D16()
650 void emit_d16(CodeBuffer &cbuf, int d16)
651 {
652 *((short *)(cbuf.code_end())) = d16;
653 cbuf.set_code_end(cbuf.code_end() + 2);
654 }
656 // EMIT_D32()
657 void emit_d32(CodeBuffer &cbuf, int d32)
658 {
659 *((int *)(cbuf.code_end())) = d32;
660 cbuf.set_code_end(cbuf.code_end() + 4);
661 }
663 // EMIT_D64()
664 void emit_d64(CodeBuffer &cbuf, int64_t d64)
665 {
666 *((int64_t*) (cbuf.code_end())) = d64;
667 cbuf.set_code_end(cbuf.code_end() + 8);
668 }
670 // emit 32 bit value and construct relocation entry from relocInfo::relocType
671 void emit_d32_reloc(CodeBuffer& cbuf,
672 int d32,
673 relocInfo::relocType reloc,
674 int format)
675 {
676 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
677 cbuf.relocate(cbuf.inst_mark(), reloc, format);
679 *((int*) (cbuf.code_end())) = d32;
680 cbuf.set_code_end(cbuf.code_end() + 4);
681 }
683 // emit 32 bit value and construct relocation entry from RelocationHolder
684 void emit_d32_reloc(CodeBuffer& cbuf,
685 int d32,
686 RelocationHolder const& rspec,
687 int format)
688 {
689 #ifdef ASSERT
690 if (rspec.reloc()->type() == relocInfo::oop_type &&
691 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
692 assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code");
693 }
694 #endif
695 cbuf.relocate(cbuf.inst_mark(), rspec, format);
697 *((int* )(cbuf.code_end())) = d32;
698 cbuf.set_code_end(cbuf.code_end() + 4);
699 }
701 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
702 address next_ip = cbuf.code_end() + 4;
703 emit_d32_reloc(cbuf, (int) (addr - next_ip),
704 external_word_Relocation::spec(addr),
705 RELOC_DISP32);
706 }
709 // emit 64 bit value and construct relocation entry from relocInfo::relocType
710 void emit_d64_reloc(CodeBuffer& cbuf,
711 int64_t d64,
712 relocInfo::relocType reloc,
713 int format)
714 {
715 cbuf.relocate(cbuf.inst_mark(), reloc, format);
717 *((int64_t*) (cbuf.code_end())) = d64;
718 cbuf.set_code_end(cbuf.code_end() + 8);
719 }
721 // emit 64 bit value and construct relocation entry from RelocationHolder
722 void emit_d64_reloc(CodeBuffer& cbuf,
723 int64_t d64,
724 RelocationHolder const& rspec,
725 int format)
726 {
727 #ifdef ASSERT
728 if (rspec.reloc()->type() == relocInfo::oop_type &&
729 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
730 assert(oop(d64)->is_oop() && oop(d64)->is_perm(),
731 "cannot embed non-perm oops in code");
732 }
733 #endif
734 cbuf.relocate(cbuf.inst_mark(), rspec, format);
736 *((int64_t*) (cbuf.code_end())) = d64;
737 cbuf.set_code_end(cbuf.code_end() + 8);
738 }
740 // Access stack slot for load or store
741 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
742 {
743 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
744 if (-0x80 <= disp && disp < 0x80) {
745 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
746 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
747 emit_d8(cbuf, disp); // Displacement // R/M byte
748 } else {
749 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
750 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
751 emit_d32(cbuf, disp); // Displacement // R/M byte
752 }
753 }
755 // rRegI ereg, memory mem) %{ // emit_reg_mem
756 void encode_RegMem(CodeBuffer &cbuf,
757 int reg,
758 int base, int index, int scale, int disp, bool disp_is_oop)
759 {
760 assert(!disp_is_oop, "cannot have disp");
761 int regenc = reg & 7;
762 int baseenc = base & 7;
763 int indexenc = index & 7;
765 // There is no index & no scale, use form without SIB byte
766 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
767 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
768 if (disp == 0 && base != RBP_enc && base != R13_enc) {
769 emit_rm(cbuf, 0x0, regenc, baseenc); // *
770 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
771 // If 8-bit displacement, mode 0x1
772 emit_rm(cbuf, 0x1, regenc, baseenc); // *
773 emit_d8(cbuf, disp);
774 } else {
775 // If 32-bit displacement
776 if (base == -1) { // Special flag for absolute address
777 emit_rm(cbuf, 0x0, regenc, 0x5); // *
778 if (disp_is_oop) {
779 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
780 } else {
781 emit_d32(cbuf, disp);
782 }
783 } else {
784 // Normal base + offset
785 emit_rm(cbuf, 0x2, regenc, baseenc); // *
786 if (disp_is_oop) {
787 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
788 } else {
789 emit_d32(cbuf, disp);
790 }
791 }
792 }
793 } else {
794 // Else, encode with the SIB byte
795 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
796 if (disp == 0 && base != RBP_enc && base != R13_enc) {
797 // If no displacement
798 emit_rm(cbuf, 0x0, regenc, 0x4); // *
799 emit_rm(cbuf, scale, indexenc, baseenc);
800 } else {
801 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
802 // If 8-bit displacement, mode 0x1
803 emit_rm(cbuf, 0x1, regenc, 0x4); // *
804 emit_rm(cbuf, scale, indexenc, baseenc);
805 emit_d8(cbuf, disp);
806 } else {
807 // If 32-bit displacement
808 if (base == 0x04 ) {
809 emit_rm(cbuf, 0x2, regenc, 0x4);
810 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
811 } else {
812 emit_rm(cbuf, 0x2, regenc, 0x4);
813 emit_rm(cbuf, scale, indexenc, baseenc); // *
814 }
815 if (disp_is_oop) {
816 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
817 } else {
818 emit_d32(cbuf, disp);
819 }
820 }
821 }
822 }
823 }
825 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
826 {
827 if (dstenc != srcenc) {
828 if (dstenc < 8) {
829 if (srcenc >= 8) {
830 emit_opcode(cbuf, Assembler::REX_B);
831 srcenc -= 8;
832 }
833 } else {
834 if (srcenc < 8) {
835 emit_opcode(cbuf, Assembler::REX_R);
836 } else {
837 emit_opcode(cbuf, Assembler::REX_RB);
838 srcenc -= 8;
839 }
840 dstenc -= 8;
841 }
843 emit_opcode(cbuf, 0x8B);
844 emit_rm(cbuf, 0x3, dstenc, srcenc);
845 }
846 }
848 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
849 if( dst_encoding == src_encoding ) {
850 // reg-reg copy, use an empty encoding
851 } else {
852 MacroAssembler _masm(&cbuf);
854 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
855 }
856 }
859 //=============================================================================
860 #ifndef PRODUCT
861 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
862 {
863 Compile* C = ra_->C;
865 int framesize = C->frame_slots() << LogBytesPerInt;
866 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
867 // Remove wordSize for return adr already pushed
868 // and another for the RBP we are going to save
869 framesize -= 2*wordSize;
870 bool need_nop = true;
872 // Calls to C2R adapters often do not accept exceptional returns.
873 // We require that their callers must bang for them. But be
874 // careful, because some VM calls (such as call site linkage) can
875 // use several kilobytes of stack. But the stack safety zone should
876 // account for that. See bugs 4446381, 4468289, 4497237.
877 if (C->need_stack_bang(framesize)) {
878 st->print_cr("# stack bang"); st->print("\t");
879 need_nop = false;
880 }
881 st->print_cr("pushq rbp"); st->print("\t");
883 if (VerifyStackAtCalls) {
884 // Majik cookie to verify stack depth
885 st->print_cr("pushq 0xffffffffbadb100d"
886 "\t# Majik cookie for stack depth check");
887 st->print("\t");
888 framesize -= wordSize; // Remove 2 for cookie
889 need_nop = false;
890 }
892 if (framesize) {
893 st->print("subq rsp, #%d\t# Create frame", framesize);
894 if (framesize < 0x80 && need_nop) {
895 st->print("\n\tnop\t# nop for patch_verified_entry");
896 }
897 }
898 }
899 #endif
901 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
902 {
903 Compile* C = ra_->C;
905 // WARNING: Initial instruction MUST be 5 bytes or longer so that
906 // NativeJump::patch_verified_entry will be able to patch out the entry
907 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
908 // depth is ok at 5 bytes, the frame allocation can be either 3 or
909 // 6 bytes. So if we don't do the fldcw or the push then we must
910 // use the 6 byte frame allocation even if we have no frame. :-(
911 // If method sets FPU control word do it now
913 int framesize = C->frame_slots() << LogBytesPerInt;
914 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
915 // Remove wordSize for return adr already pushed
916 // and another for the RBP we are going to save
917 framesize -= 2*wordSize;
918 bool need_nop = true;
920 // Calls to C2R adapters often do not accept exceptional returns.
921 // We require that their callers must bang for them. But be
922 // careful, because some VM calls (such as call site linkage) can
923 // use several kilobytes of stack. But the stack safety zone should
924 // account for that. See bugs 4446381, 4468289, 4497237.
925 if (C->need_stack_bang(framesize)) {
926 MacroAssembler masm(&cbuf);
927 masm.generate_stack_overflow_check(framesize);
928 need_nop = false;
929 }
931 // We always push rbp so that on return to interpreter rbp will be
932 // restored correctly and we can correct the stack.
933 emit_opcode(cbuf, 0x50 | RBP_enc);
935 if (VerifyStackAtCalls) {
936 // Majik cookie to verify stack depth
937 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
938 emit_d32(cbuf, 0xbadb100d);
939 framesize -= wordSize; // Remove 2 for cookie
940 need_nop = false;
941 }
943 if (framesize) {
944 emit_opcode(cbuf, Assembler::REX_W);
945 if (framesize < 0x80) {
946 emit_opcode(cbuf, 0x83); // sub SP,#framesize
947 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
948 emit_d8(cbuf, framesize);
949 if (need_nop) {
950 emit_opcode(cbuf, 0x90); // nop
951 }
952 } else {
953 emit_opcode(cbuf, 0x81); // sub SP,#framesize
954 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
955 emit_d32(cbuf, framesize);
956 }
957 }
959 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
961 #ifdef ASSERT
962 if (VerifyStackAtCalls) {
963 Label L;
964 MacroAssembler masm(&cbuf);
965 masm.push(rax);
966 masm.mov(rax, rsp);
967 masm.andptr(rax, StackAlignmentInBytes-1);
968 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
969 masm.pop(rax);
970 masm.jcc(Assembler::equal, L);
971 masm.stop("Stack is not properly aligned!");
972 masm.bind(L);
973 }
974 #endif
975 }
977 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
978 {
979 return MachNode::size(ra_); // too many variables; just compute it
980 // the hard way
981 }
983 int MachPrologNode::reloc() const
984 {
985 return 0; // a large enough number
986 }
988 //=============================================================================
989 #ifndef PRODUCT
990 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
991 {
992 Compile* C = ra_->C;
993 int framesize = C->frame_slots() << LogBytesPerInt;
994 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
995 // Remove word for return adr already pushed
996 // and RBP
997 framesize -= 2*wordSize;
999 if (framesize) {
1000 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
1001 st->print("\t");
1002 }
1004 st->print_cr("popq\trbp");
1005 if (do_polling() && C->is_method_compilation()) {
1006 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
1007 "# Safepoint: poll for GC");
1008 st->print("\t");
1009 }
1010 }
1011 #endif
1013 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1014 {
1015 Compile* C = ra_->C;
1016 int framesize = C->frame_slots() << LogBytesPerInt;
1017 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1018 // Remove word for return adr already pushed
1019 // and RBP
1020 framesize -= 2*wordSize;
1022 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1024 if (framesize) {
1025 emit_opcode(cbuf, Assembler::REX_W);
1026 if (framesize < 0x80) {
1027 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1028 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1029 emit_d8(cbuf, framesize);
1030 } else {
1031 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1032 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1033 emit_d32(cbuf, framesize);
1034 }
1035 }
1037 // popq rbp
1038 emit_opcode(cbuf, 0x58 | RBP_enc);
1040 if (do_polling() && C->is_method_compilation()) {
1041 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
1042 // XXX reg_mem doesn't support RIP-relative addressing yet
1043 cbuf.set_inst_mark();
1044 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX
1045 emit_opcode(cbuf, 0x85); // testl
1046 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
1047 // cbuf.inst_mark() is beginning of instruction
1048 emit_d32_reloc(cbuf, os::get_polling_page());
1049 // relocInfo::poll_return_type,
1050 }
1051 }
1053 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1054 {
1055 Compile* C = ra_->C;
1056 int framesize = C->frame_slots() << LogBytesPerInt;
1057 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1058 // Remove word for return adr already pushed
1059 // and RBP
1060 framesize -= 2*wordSize;
1062 uint size = 0;
1064 if (do_polling() && C->is_method_compilation()) {
1065 size += 6;
1066 }
1068 // count popq rbp
1069 size++;
1071 if (framesize) {
1072 if (framesize < 0x80) {
1073 size += 4;
1074 } else if (framesize) {
1075 size += 7;
1076 }
1077 }
1079 return size;
1080 }
1082 int MachEpilogNode::reloc() const
1083 {
1084 return 2; // a large enough number
1085 }
1087 const Pipeline* MachEpilogNode::pipeline() const
1088 {
1089 return MachNode::pipeline_class();
1090 }
1092 int MachEpilogNode::safepoint_offset() const
1093 {
1094 return 0;
1095 }
1097 //=============================================================================
1099 enum RC {
1100 rc_bad,
1101 rc_int,
1102 rc_float,
1103 rc_stack
1104 };
1106 static enum RC rc_class(OptoReg::Name reg)
1107 {
1108 if( !OptoReg::is_valid(reg) ) return rc_bad;
1110 if (OptoReg::is_stack(reg)) return rc_stack;
1112 VMReg r = OptoReg::as_VMReg(reg);
1114 if (r->is_Register()) return rc_int;
1116 assert(r->is_XMMRegister(), "must be");
1117 return rc_float;
1118 }
1120 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1121 PhaseRegAlloc* ra_,
1122 bool do_size,
1123 outputStream* st) const
1124 {
1126 // Get registers to move
1127 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1128 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1129 OptoReg::Name dst_second = ra_->get_reg_second(this);
1130 OptoReg::Name dst_first = ra_->get_reg_first(this);
1132 enum RC src_second_rc = rc_class(src_second);
1133 enum RC src_first_rc = rc_class(src_first);
1134 enum RC dst_second_rc = rc_class(dst_second);
1135 enum RC dst_first_rc = rc_class(dst_first);
1137 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1138 "must move at least 1 register" );
1140 if (src_first == dst_first && src_second == dst_second) {
1141 // Self copy, no move
1142 return 0;
1143 } else if (src_first_rc == rc_stack) {
1144 // mem ->
1145 if (dst_first_rc == rc_stack) {
1146 // mem -> mem
1147 assert(src_second != dst_first, "overlap");
1148 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1149 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1150 // 64-bit
1151 int src_offset = ra_->reg2offset(src_first);
1152 int dst_offset = ra_->reg2offset(dst_first);
1153 if (cbuf) {
1154 emit_opcode(*cbuf, 0xFF);
1155 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
1157 emit_opcode(*cbuf, 0x8F);
1158 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
1160 #ifndef PRODUCT
1161 } else if (!do_size) {
1162 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1163 "popq [rsp + #%d]",
1164 src_offset,
1165 dst_offset);
1166 #endif
1167 }
1168 return
1169 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
1170 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
1171 } else {
1172 // 32-bit
1173 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1174 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1175 // No pushl/popl, so:
1176 int src_offset = ra_->reg2offset(src_first);
1177 int dst_offset = ra_->reg2offset(dst_first);
1178 if (cbuf) {
1179 emit_opcode(*cbuf, Assembler::REX_W);
1180 emit_opcode(*cbuf, 0x89);
1181 emit_opcode(*cbuf, 0x44);
1182 emit_opcode(*cbuf, 0x24);
1183 emit_opcode(*cbuf, 0xF8);
1185 emit_opcode(*cbuf, 0x8B);
1186 encode_RegMem(*cbuf,
1187 RAX_enc,
1188 RSP_enc, 0x4, 0, src_offset,
1189 false);
1191 emit_opcode(*cbuf, 0x89);
1192 encode_RegMem(*cbuf,
1193 RAX_enc,
1194 RSP_enc, 0x4, 0, dst_offset,
1195 false);
1197 emit_opcode(*cbuf, Assembler::REX_W);
1198 emit_opcode(*cbuf, 0x8B);
1199 emit_opcode(*cbuf, 0x44);
1200 emit_opcode(*cbuf, 0x24);
1201 emit_opcode(*cbuf, 0xF8);
1203 #ifndef PRODUCT
1204 } else if (!do_size) {
1205 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1206 "movl rax, [rsp + #%d]\n\t"
1207 "movl [rsp + #%d], rax\n\t"
1208 "movq rax, [rsp - #8]",
1209 src_offset,
1210 dst_offset);
1211 #endif
1212 }
1213 return
1214 5 + // movq
1215 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
1216 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
1217 5; // movq
1218 }
1219 } else if (dst_first_rc == rc_int) {
1220 // mem -> gpr
1221 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1222 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1223 // 64-bit
1224 int offset = ra_->reg2offset(src_first);
1225 if (cbuf) {
1226 if (Matcher::_regEncode[dst_first] < 8) {
1227 emit_opcode(*cbuf, Assembler::REX_W);
1228 } else {
1229 emit_opcode(*cbuf, Assembler::REX_WR);
1230 }
1231 emit_opcode(*cbuf, 0x8B);
1232 encode_RegMem(*cbuf,
1233 Matcher::_regEncode[dst_first],
1234 RSP_enc, 0x4, 0, offset,
1235 false);
1236 #ifndef PRODUCT
1237 } else if (!do_size) {
1238 st->print("movq %s, [rsp + #%d]\t# spill",
1239 Matcher::regName[dst_first],
1240 offset);
1241 #endif
1242 }
1243 return
1244 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1245 } else {
1246 // 32-bit
1247 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1248 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1249 int offset = ra_->reg2offset(src_first);
1250 if (cbuf) {
1251 if (Matcher::_regEncode[dst_first] >= 8) {
1252 emit_opcode(*cbuf, Assembler::REX_R);
1253 }
1254 emit_opcode(*cbuf, 0x8B);
1255 encode_RegMem(*cbuf,
1256 Matcher::_regEncode[dst_first],
1257 RSP_enc, 0x4, 0, offset,
1258 false);
1259 #ifndef PRODUCT
1260 } else if (!do_size) {
1261 st->print("movl %s, [rsp + #%d]\t# spill",
1262 Matcher::regName[dst_first],
1263 offset);
1264 #endif
1265 }
1266 return
1267 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1268 ((Matcher::_regEncode[dst_first] < 8)
1269 ? 3
1270 : 4); // REX
1271 }
1272 } else if (dst_first_rc == rc_float) {
1273 // mem-> xmm
1274 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1275 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1276 // 64-bit
1277 int offset = ra_->reg2offset(src_first);
1278 if (cbuf) {
1279 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1280 if (Matcher::_regEncode[dst_first] >= 8) {
1281 emit_opcode(*cbuf, Assembler::REX_R);
1282 }
1283 emit_opcode(*cbuf, 0x0F);
1284 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1285 encode_RegMem(*cbuf,
1286 Matcher::_regEncode[dst_first],
1287 RSP_enc, 0x4, 0, offset,
1288 false);
1289 #ifndef PRODUCT
1290 } else if (!do_size) {
1291 st->print("%s %s, [rsp + #%d]\t# spill",
1292 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1293 Matcher::regName[dst_first],
1294 offset);
1295 #endif
1296 }
1297 return
1298 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1299 ((Matcher::_regEncode[dst_first] < 8)
1300 ? 5
1301 : 6); // REX
1302 } else {
1303 // 32-bit
1304 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1305 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1306 int offset = ra_->reg2offset(src_first);
1307 if (cbuf) {
1308 emit_opcode(*cbuf, 0xF3);
1309 if (Matcher::_regEncode[dst_first] >= 8) {
1310 emit_opcode(*cbuf, Assembler::REX_R);
1311 }
1312 emit_opcode(*cbuf, 0x0F);
1313 emit_opcode(*cbuf, 0x10);
1314 encode_RegMem(*cbuf,
1315 Matcher::_regEncode[dst_first],
1316 RSP_enc, 0x4, 0, offset,
1317 false);
1318 #ifndef PRODUCT
1319 } else if (!do_size) {
1320 st->print("movss %s, [rsp + #%d]\t# spill",
1321 Matcher::regName[dst_first],
1322 offset);
1323 #endif
1324 }
1325 return
1326 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1327 ((Matcher::_regEncode[dst_first] < 8)
1328 ? 5
1329 : 6); // REX
1330 }
1331 }
1332 } else if (src_first_rc == rc_int) {
1333 // gpr ->
1334 if (dst_first_rc == rc_stack) {
1335 // gpr -> mem
1336 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1337 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1338 // 64-bit
1339 int offset = ra_->reg2offset(dst_first);
1340 if (cbuf) {
1341 if (Matcher::_regEncode[src_first] < 8) {
1342 emit_opcode(*cbuf, Assembler::REX_W);
1343 } else {
1344 emit_opcode(*cbuf, Assembler::REX_WR);
1345 }
1346 emit_opcode(*cbuf, 0x89);
1347 encode_RegMem(*cbuf,
1348 Matcher::_regEncode[src_first],
1349 RSP_enc, 0x4, 0, offset,
1350 false);
1351 #ifndef PRODUCT
1352 } else if (!do_size) {
1353 st->print("movq [rsp + #%d], %s\t# spill",
1354 offset,
1355 Matcher::regName[src_first]);
1356 #endif
1357 }
1358 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1359 } else {
1360 // 32-bit
1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1363 int offset = ra_->reg2offset(dst_first);
1364 if (cbuf) {
1365 if (Matcher::_regEncode[src_first] >= 8) {
1366 emit_opcode(*cbuf, Assembler::REX_R);
1367 }
1368 emit_opcode(*cbuf, 0x89);
1369 encode_RegMem(*cbuf,
1370 Matcher::_regEncode[src_first],
1371 RSP_enc, 0x4, 0, offset,
1372 false);
1373 #ifndef PRODUCT
1374 } else if (!do_size) {
1375 st->print("movl [rsp + #%d], %s\t# spill",
1376 offset,
1377 Matcher::regName[src_first]);
1378 #endif
1379 }
1380 return
1381 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1382 ((Matcher::_regEncode[src_first] < 8)
1383 ? 3
1384 : 4); // REX
1385 }
1386 } else if (dst_first_rc == rc_int) {
1387 // gpr -> gpr
1388 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1389 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1390 // 64-bit
1391 if (cbuf) {
1392 if (Matcher::_regEncode[dst_first] < 8) {
1393 if (Matcher::_regEncode[src_first] < 8) {
1394 emit_opcode(*cbuf, Assembler::REX_W);
1395 } else {
1396 emit_opcode(*cbuf, Assembler::REX_WB);
1397 }
1398 } else {
1399 if (Matcher::_regEncode[src_first] < 8) {
1400 emit_opcode(*cbuf, Assembler::REX_WR);
1401 } else {
1402 emit_opcode(*cbuf, Assembler::REX_WRB);
1403 }
1404 }
1405 emit_opcode(*cbuf, 0x8B);
1406 emit_rm(*cbuf, 0x3,
1407 Matcher::_regEncode[dst_first] & 7,
1408 Matcher::_regEncode[src_first] & 7);
1409 #ifndef PRODUCT
1410 } else if (!do_size) {
1411 st->print("movq %s, %s\t# spill",
1412 Matcher::regName[dst_first],
1413 Matcher::regName[src_first]);
1414 #endif
1415 }
1416 return 3; // REX
1417 } else {
1418 // 32-bit
1419 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1420 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1421 if (cbuf) {
1422 if (Matcher::_regEncode[dst_first] < 8) {
1423 if (Matcher::_regEncode[src_first] >= 8) {
1424 emit_opcode(*cbuf, Assembler::REX_B);
1425 }
1426 } else {
1427 if (Matcher::_regEncode[src_first] < 8) {
1428 emit_opcode(*cbuf, Assembler::REX_R);
1429 } else {
1430 emit_opcode(*cbuf, Assembler::REX_RB);
1431 }
1432 }
1433 emit_opcode(*cbuf, 0x8B);
1434 emit_rm(*cbuf, 0x3,
1435 Matcher::_regEncode[dst_first] & 7,
1436 Matcher::_regEncode[src_first] & 7);
1437 #ifndef PRODUCT
1438 } else if (!do_size) {
1439 st->print("movl %s, %s\t# spill",
1440 Matcher::regName[dst_first],
1441 Matcher::regName[src_first]);
1442 #endif
1443 }
1444 return
1445 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1446 ? 2
1447 : 3; // REX
1448 }
1449 } else if (dst_first_rc == rc_float) {
1450 // gpr -> xmm
1451 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1452 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1453 // 64-bit
1454 if (cbuf) {
1455 emit_opcode(*cbuf, 0x66);
1456 if (Matcher::_regEncode[dst_first] < 8) {
1457 if (Matcher::_regEncode[src_first] < 8) {
1458 emit_opcode(*cbuf, Assembler::REX_W);
1459 } else {
1460 emit_opcode(*cbuf, Assembler::REX_WB);
1461 }
1462 } else {
1463 if (Matcher::_regEncode[src_first] < 8) {
1464 emit_opcode(*cbuf, Assembler::REX_WR);
1465 } else {
1466 emit_opcode(*cbuf, Assembler::REX_WRB);
1467 }
1468 }
1469 emit_opcode(*cbuf, 0x0F);
1470 emit_opcode(*cbuf, 0x6E);
1471 emit_rm(*cbuf, 0x3,
1472 Matcher::_regEncode[dst_first] & 7,
1473 Matcher::_regEncode[src_first] & 7);
1474 #ifndef PRODUCT
1475 } else if (!do_size) {
1476 st->print("movdq %s, %s\t# spill",
1477 Matcher::regName[dst_first],
1478 Matcher::regName[src_first]);
1479 #endif
1480 }
1481 return 5; // REX
1482 } else {
1483 // 32-bit
1484 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1485 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1486 if (cbuf) {
1487 emit_opcode(*cbuf, 0x66);
1488 if (Matcher::_regEncode[dst_first] < 8) {
1489 if (Matcher::_regEncode[src_first] >= 8) {
1490 emit_opcode(*cbuf, Assembler::REX_B);
1491 }
1492 } else {
1493 if (Matcher::_regEncode[src_first] < 8) {
1494 emit_opcode(*cbuf, Assembler::REX_R);
1495 } else {
1496 emit_opcode(*cbuf, Assembler::REX_RB);
1497 }
1498 }
1499 emit_opcode(*cbuf, 0x0F);
1500 emit_opcode(*cbuf, 0x6E);
1501 emit_rm(*cbuf, 0x3,
1502 Matcher::_regEncode[dst_first] & 7,
1503 Matcher::_regEncode[src_first] & 7);
1504 #ifndef PRODUCT
1505 } else if (!do_size) {
1506 st->print("movdl %s, %s\t# spill",
1507 Matcher::regName[dst_first],
1508 Matcher::regName[src_first]);
1509 #endif
1510 }
1511 return
1512 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1513 ? 4
1514 : 5; // REX
1515 }
1516 }
1517 } else if (src_first_rc == rc_float) {
1518 // xmm ->
1519 if (dst_first_rc == rc_stack) {
1520 // xmm -> mem
1521 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1522 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1523 // 64-bit
1524 int offset = ra_->reg2offset(dst_first);
1525 if (cbuf) {
1526 emit_opcode(*cbuf, 0xF2);
1527 if (Matcher::_regEncode[src_first] >= 8) {
1528 emit_opcode(*cbuf, Assembler::REX_R);
1529 }
1530 emit_opcode(*cbuf, 0x0F);
1531 emit_opcode(*cbuf, 0x11);
1532 encode_RegMem(*cbuf,
1533 Matcher::_regEncode[src_first],
1534 RSP_enc, 0x4, 0, offset,
1535 false);
1536 #ifndef PRODUCT
1537 } else if (!do_size) {
1538 st->print("movsd [rsp + #%d], %s\t# spill",
1539 offset,
1540 Matcher::regName[src_first]);
1541 #endif
1542 }
1543 return
1544 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1545 ((Matcher::_regEncode[src_first] < 8)
1546 ? 5
1547 : 6); // REX
1548 } else {
1549 // 32-bit
1550 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1551 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1552 int offset = ra_->reg2offset(dst_first);
1553 if (cbuf) {
1554 emit_opcode(*cbuf, 0xF3);
1555 if (Matcher::_regEncode[src_first] >= 8) {
1556 emit_opcode(*cbuf, Assembler::REX_R);
1557 }
1558 emit_opcode(*cbuf, 0x0F);
1559 emit_opcode(*cbuf, 0x11);
1560 encode_RegMem(*cbuf,
1561 Matcher::_regEncode[src_first],
1562 RSP_enc, 0x4, 0, offset,
1563 false);
1564 #ifndef PRODUCT
1565 } else if (!do_size) {
1566 st->print("movss [rsp + #%d], %s\t# spill",
1567 offset,
1568 Matcher::regName[src_first]);
1569 #endif
1570 }
1571 return
1572 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1573 ((Matcher::_regEncode[src_first] < 8)
1574 ? 5
1575 : 6); // REX
1576 }
1577 } else if (dst_first_rc == rc_int) {
1578 // xmm -> gpr
1579 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1580 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1581 // 64-bit
1582 if (cbuf) {
1583 emit_opcode(*cbuf, 0x66);
1584 if (Matcher::_regEncode[dst_first] < 8) {
1585 if (Matcher::_regEncode[src_first] < 8) {
1586 emit_opcode(*cbuf, Assembler::REX_W);
1587 } else {
1588 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
1589 }
1590 } else {
1591 if (Matcher::_regEncode[src_first] < 8) {
1592 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
1593 } else {
1594 emit_opcode(*cbuf, Assembler::REX_WRB);
1595 }
1596 }
1597 emit_opcode(*cbuf, 0x0F);
1598 emit_opcode(*cbuf, 0x7E);
1599 emit_rm(*cbuf, 0x3,
1600 Matcher::_regEncode[dst_first] & 7,
1601 Matcher::_regEncode[src_first] & 7);
1602 #ifndef PRODUCT
1603 } else if (!do_size) {
1604 st->print("movdq %s, %s\t# spill",
1605 Matcher::regName[dst_first],
1606 Matcher::regName[src_first]);
1607 #endif
1608 }
1609 return 5; // REX
1610 } else {
1611 // 32-bit
1612 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1613 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1614 if (cbuf) {
1615 emit_opcode(*cbuf, 0x66);
1616 if (Matcher::_regEncode[dst_first] < 8) {
1617 if (Matcher::_regEncode[src_first] >= 8) {
1618 emit_opcode(*cbuf, Assembler::REX_R); // attention!
1619 }
1620 } else {
1621 if (Matcher::_regEncode[src_first] < 8) {
1622 emit_opcode(*cbuf, Assembler::REX_B); // attention!
1623 } else {
1624 emit_opcode(*cbuf, Assembler::REX_RB);
1625 }
1626 }
1627 emit_opcode(*cbuf, 0x0F);
1628 emit_opcode(*cbuf, 0x7E);
1629 emit_rm(*cbuf, 0x3,
1630 Matcher::_regEncode[dst_first] & 7,
1631 Matcher::_regEncode[src_first] & 7);
1632 #ifndef PRODUCT
1633 } else if (!do_size) {
1634 st->print("movdl %s, %s\t# spill",
1635 Matcher::regName[dst_first],
1636 Matcher::regName[src_first]);
1637 #endif
1638 }
1639 return
1640 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1641 ? 4
1642 : 5; // REX
1643 }
1644 } else if (dst_first_rc == rc_float) {
1645 // xmm -> xmm
1646 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1647 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1648 // 64-bit
1649 if (cbuf) {
1650 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
1651 if (Matcher::_regEncode[dst_first] < 8) {
1652 if (Matcher::_regEncode[src_first] >= 8) {
1653 emit_opcode(*cbuf, Assembler::REX_B);
1654 }
1655 } else {
1656 if (Matcher::_regEncode[src_first] < 8) {
1657 emit_opcode(*cbuf, Assembler::REX_R);
1658 } else {
1659 emit_opcode(*cbuf, Assembler::REX_RB);
1660 }
1661 }
1662 emit_opcode(*cbuf, 0x0F);
1663 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1664 emit_rm(*cbuf, 0x3,
1665 Matcher::_regEncode[dst_first] & 7,
1666 Matcher::_regEncode[src_first] & 7);
1667 #ifndef PRODUCT
1668 } else if (!do_size) {
1669 st->print("%s %s, %s\t# spill",
1670 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1671 Matcher::regName[dst_first],
1672 Matcher::regName[src_first]);
1673 #endif
1674 }
1675 return
1676 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1677 ? 4
1678 : 5; // REX
1679 } else {
1680 // 32-bit
1681 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1682 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1683 if (cbuf) {
1684 if (!UseXmmRegToRegMoveAll)
1685 emit_opcode(*cbuf, 0xF3);
1686 if (Matcher::_regEncode[dst_first] < 8) {
1687 if (Matcher::_regEncode[src_first] >= 8) {
1688 emit_opcode(*cbuf, Assembler::REX_B);
1689 }
1690 } else {
1691 if (Matcher::_regEncode[src_first] < 8) {
1692 emit_opcode(*cbuf, Assembler::REX_R);
1693 } else {
1694 emit_opcode(*cbuf, Assembler::REX_RB);
1695 }
1696 }
1697 emit_opcode(*cbuf, 0x0F);
1698 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1699 emit_rm(*cbuf, 0x3,
1700 Matcher::_regEncode[dst_first] & 7,
1701 Matcher::_regEncode[src_first] & 7);
1702 #ifndef PRODUCT
1703 } else if (!do_size) {
1704 st->print("%s %s, %s\t# spill",
1705 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1706 Matcher::regName[dst_first],
1707 Matcher::regName[src_first]);
1708 #endif
1709 }
1710 return
1711 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1712 ? (UseXmmRegToRegMoveAll ? 3 : 4)
1713 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
1714 }
1715 }
1716 }
1718 assert(0," foo ");
1719 Unimplemented();
1721 return 0;
1722 }
1724 #ifndef PRODUCT
1725 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1726 {
1727 implementation(NULL, ra_, false, st);
1728 }
1729 #endif
1731 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1732 {
1733 implementation(&cbuf, ra_, false, NULL);
1734 }
1736 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1737 {
1738 return implementation(NULL, ra_, true, NULL);
1739 }
1741 //=============================================================================
1742 #ifndef PRODUCT
1743 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
1744 {
1745 st->print("nop \t# %d bytes pad for loops and calls", _count);
1746 }
1747 #endif
1749 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
1750 {
1751 MacroAssembler _masm(&cbuf);
1752 __ nop(_count);
1753 }
1755 uint MachNopNode::size(PhaseRegAlloc*) const
1756 {
1757 return _count;
1758 }
1761 //=============================================================================
1762 #ifndef PRODUCT
1763 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1764 {
1765 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1766 int reg = ra_->get_reg_first(this);
1767 st->print("leaq %s, [rsp + #%d]\t# box lock",
1768 Matcher::regName[reg], offset);
1769 }
1770 #endif
1772 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1773 {
1774 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1775 int reg = ra_->get_encode(this);
1776 if (offset >= 0x80) {
1777 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1778 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1779 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1780 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1781 emit_d32(cbuf, offset);
1782 } else {
1783 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1784 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1785 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1786 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1787 emit_d8(cbuf, offset);
1788 }
1789 }
1791 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1792 {
1793 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1794 return (offset < 0x80) ? 5 : 8; // REX
1795 }
1797 //=============================================================================
1799 // emit call stub, compiled java to interpreter
1800 void emit_java_to_interp(CodeBuffer& cbuf)
1801 {
1802 // Stub is fixed up when the corresponding call is converted from
1803 // calling compiled code to calling interpreted code.
1804 // movq rbx, 0
1805 // jmp -5 # to self
1807 address mark = cbuf.inst_mark(); // get mark within main instrs section
1809 // Note that the code buffer's inst_mark is always relative to insts.
1810 // That's why we must use the macroassembler to generate a stub.
1811 MacroAssembler _masm(&cbuf);
1813 address base =
1814 __ start_a_stub(Compile::MAX_stubs_size);
1815 if (base == NULL) return; // CodeBuffer::expand failed
1816 // static stub relocation stores the instruction address of the call
1817 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1818 // static stub relocation also tags the methodOop in the code-stream.
1819 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1820 // This is recognized as unresolved by relocs/nativeinst/ic code
1821 __ jump(RuntimeAddress(__ pc()));
1823 // Update current stubs pointer and restore code_end.
1824 __ end_a_stub();
1825 }
1827 // size of call stub, compiled java to interpretor
1828 uint size_java_to_interp()
1829 {
1830 return 15; // movq (1+1+8); jmp (1+4)
1831 }
1833 // relocation entries for call stub, compiled java to interpretor
1834 uint reloc_java_to_interp()
1835 {
1836 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1837 }
1839 //=============================================================================
1840 #ifndef PRODUCT
1841 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1842 {
1843 if (UseCompressedOops) {
1844 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes());
1845 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]");
1846 st->print_cr("cmpq rax, rscratch1\t # Inline cache check");
1847 } else {
1848 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
1849 "# Inline cache check", oopDesc::klass_offset_in_bytes());
1850 }
1851 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1852 st->print_cr("\tnop");
1853 if (!OptoBreakpoint) {
1854 st->print_cr("\tnop");
1855 }
1856 }
1857 #endif
1859 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1860 {
1861 MacroAssembler masm(&cbuf);
1862 #ifdef ASSERT
1863 uint code_size = cbuf.code_size();
1864 #endif
1865 if (UseCompressedOops) {
1866 masm.load_klass(rscratch1, j_rarg0);
1867 masm.cmpptr(rax, rscratch1);
1868 } else {
1869 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1870 }
1872 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1874 /* WARNING these NOPs are critical so that verified entry point is properly
1875 aligned for patching by NativeJump::patch_verified_entry() */
1876 int nops_cnt = 1;
1877 if (!OptoBreakpoint) {
1878 // Leave space for int3
1879 nops_cnt += 1;
1880 }
1881 if (UseCompressedOops) {
1882 // ??? divisible by 4 is aligned?
1883 nops_cnt += 1;
1884 }
1885 masm.nop(nops_cnt);
1887 assert(cbuf.code_size() - code_size == size(ra_),
1888 "checking code size of inline cache node");
1889 }
1891 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1892 {
1893 if (UseCompressedOops) {
1894 return OptoBreakpoint ? 19 : 20;
1895 } else {
1896 return OptoBreakpoint ? 11 : 12;
1897 }
1898 }
1901 //=============================================================================
1902 uint size_exception_handler()
1903 {
1904 // NativeCall instruction size is the same as NativeJump.
1905 // Note that this value is also credited (in output.cpp) to
1906 // the size of the code section.
1907 return NativeJump::instruction_size;
1908 }
1910 // Emit exception handler code.
1911 int emit_exception_handler(CodeBuffer& cbuf)
1912 {
1914 // Note that the code buffer's inst_mark is always relative to insts.
1915 // That's why we must use the macroassembler to generate a handler.
1916 MacroAssembler _masm(&cbuf);
1917 address base =
1918 __ start_a_stub(size_exception_handler());
1919 if (base == NULL) return 0; // CodeBuffer::expand failed
1920 int offset = __ offset();
1921 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1922 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1923 __ end_a_stub();
1924 return offset;
1925 }
1927 uint size_deopt_handler()
1928 {
1929 // three 5 byte instructions
1930 return 15;
1931 }
1933 // Emit deopt handler code.
1934 int emit_deopt_handler(CodeBuffer& cbuf)
1935 {
1937 // Note that the code buffer's inst_mark is always relative to insts.
1938 // That's why we must use the macroassembler to generate a handler.
1939 MacroAssembler _masm(&cbuf);
1940 address base =
1941 __ start_a_stub(size_deopt_handler());
1942 if (base == NULL) return 0; // CodeBuffer::expand failed
1943 int offset = __ offset();
1944 address the_pc = (address) __ pc();
1945 Label next;
1946 // push a "the_pc" on the stack without destroying any registers
1947 // as they all may be live.
1949 // push address of "next"
1950 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1951 __ bind(next);
1952 // adjust it so it matches "the_pc"
1953 __ subptr(Address(rsp, 0), __ offset() - offset);
1954 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1955 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1956 __ end_a_stub();
1957 return offset;
1958 }
1960 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1961 int mark = cbuf.insts()->mark_off();
1962 MacroAssembler _masm(&cbuf);
1963 address double_address = __ double_constant(x);
1964 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1965 emit_d32_reloc(cbuf,
1966 (int) (double_address - cbuf.code_end() - 4),
1967 internal_word_Relocation::spec(double_address),
1968 RELOC_DISP32);
1969 }
1971 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1972 int mark = cbuf.insts()->mark_off();
1973 MacroAssembler _masm(&cbuf);
1974 address float_address = __ float_constant(x);
1975 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1976 emit_d32_reloc(cbuf,
1977 (int) (float_address - cbuf.code_end() - 4),
1978 internal_word_Relocation::spec(float_address),
1979 RELOC_DISP32);
1980 }
1983 int Matcher::regnum_to_fpu_offset(int regnum)
1984 {
1985 return regnum - 32; // The FP registers are in the second chunk
1986 }
1988 // This is UltraSparc specific, true just means we have fast l2f conversion
1989 const bool Matcher::convL2FSupported(void) {
1990 return true;
1991 }
1993 // Vector width in bytes
1994 const uint Matcher::vector_width_in_bytes(void) {
1995 return 8;
1996 }
1998 // Vector ideal reg
1999 const uint Matcher::vector_ideal_reg(void) {
2000 return Op_RegD;
2001 }
2003 // Is this branch offset short enough that a short branch can be used?
2004 //
2005 // NOTE: If the platform does not provide any short branch variants, then
2006 // this method should return false for offset 0.
2007 bool Matcher::is_short_branch_offset(int offset)
2008 {
2009 return -0x80 <= offset && offset < 0x80;
2010 }
2012 const bool Matcher::isSimpleConstant64(jlong value) {
2013 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
2014 //return value == (int) value; // Cf. storeImmL and immL32.
2016 // Probably always true, even if a temp register is required.
2017 return true;
2018 }
2020 // The ecx parameter to rep stosq for the ClearArray node is in words.
2021 const bool Matcher::init_array_count_is_in_bytes = false;
2023 // Threshold size for cleararray.
2024 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2026 // Should the Matcher clone shifts on addressing modes, expecting them
2027 // to be subsumed into complex addressing expressions or compute them
2028 // into registers? True for Intel but false for most RISCs
2029 const bool Matcher::clone_shift_expressions = true;
2031 // Is it better to copy float constants, or load them directly from
2032 // memory? Intel can load a float constant from a direct address,
2033 // requiring no extra registers. Most RISCs will have to materialize
2034 // an address into a register first, so they would do better to copy
2035 // the constant from stack.
2036 const bool Matcher::rematerialize_float_constants = true; // XXX
2038 // If CPU can load and store mis-aligned doubles directly then no
2039 // fixup is needed. Else we split the double into 2 integer pieces
2040 // and move it piece-by-piece. Only happens when passing doubles into
2041 // C code as the Java calling convention forces doubles to be aligned.
2042 const bool Matcher::misaligned_doubles_ok = true;
2044 // No-op on amd64
2045 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
2047 // Advertise here if the CPU requires explicit rounding operations to
2048 // implement the UseStrictFP mode.
2049 const bool Matcher::strict_fp_requires_explicit_rounding = true;
2051 // Do floats take an entire double register or just half?
2052 const bool Matcher::float_in_double = true;
2053 // Do ints take an entire long register or just half?
2054 const bool Matcher::int_in_long = true;
2056 // Return whether or not this register is ever used as an argument.
2057 // This function is used on startup to build the trampoline stubs in
2058 // generateOptoStub. Registers not mentioned will be killed by the VM
2059 // call in the trampoline, and arguments in those registers not be
2060 // available to the callee.
2061 bool Matcher::can_be_java_arg(int reg)
2062 {
2063 return
2064 reg == RDI_num || reg == RDI_H_num ||
2065 reg == RSI_num || reg == RSI_H_num ||
2066 reg == RDX_num || reg == RDX_H_num ||
2067 reg == RCX_num || reg == RCX_H_num ||
2068 reg == R8_num || reg == R8_H_num ||
2069 reg == R9_num || reg == R9_H_num ||
2070 reg == R12_num || reg == R12_H_num ||
2071 reg == XMM0_num || reg == XMM0_H_num ||
2072 reg == XMM1_num || reg == XMM1_H_num ||
2073 reg == XMM2_num || reg == XMM2_H_num ||
2074 reg == XMM3_num || reg == XMM3_H_num ||
2075 reg == XMM4_num || reg == XMM4_H_num ||
2076 reg == XMM5_num || reg == XMM5_H_num ||
2077 reg == XMM6_num || reg == XMM6_H_num ||
2078 reg == XMM7_num || reg == XMM7_H_num;
2079 }
2081 bool Matcher::is_spillable_arg(int reg)
2082 {
2083 return can_be_java_arg(reg);
2084 }
2086 // Register for DIVI projection of divmodI
2087 RegMask Matcher::divI_proj_mask() {
2088 return INT_RAX_REG_mask;
2089 }
2091 // Register for MODI projection of divmodI
2092 RegMask Matcher::modI_proj_mask() {
2093 return INT_RDX_REG_mask;
2094 }
2096 // Register for DIVL projection of divmodL
2097 RegMask Matcher::divL_proj_mask() {
2098 return LONG_RAX_REG_mask;
2099 }
2101 // Register for MODL projection of divmodL
2102 RegMask Matcher::modL_proj_mask() {
2103 return LONG_RDX_REG_mask;
2104 }
2106 static Address build_address(int b, int i, int s, int d) {
2107 Register index = as_Register(i);
2108 Address::ScaleFactor scale = (Address::ScaleFactor)s;
2109 if (index == rsp) {
2110 index = noreg;
2111 scale = Address::no_scale;
2112 }
2113 Address addr(as_Register(b), index, scale, d);
2114 return addr;
2115 }
2117 %}
2119 //----------ENCODING BLOCK-----------------------------------------------------
2120 // This block specifies the encoding classes used by the compiler to
2121 // output byte streams. Encoding classes are parameterized macros
2122 // used by Machine Instruction Nodes in order to generate the bit
2123 // encoding of the instruction. Operands specify their base encoding
2124 // interface with the interface keyword. There are currently
2125 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2126 // COND_INTER. REG_INTER causes an operand to generate a function
2127 // which returns its register number when queried. CONST_INTER causes
2128 // an operand to generate a function which returns the value of the
2129 // constant when queried. MEMORY_INTER causes an operand to generate
2130 // four functions which return the Base Register, the Index Register,
2131 // the Scale Value, and the Offset Value of the operand when queried.
2132 // COND_INTER causes an operand to generate six functions which return
2133 // the encoding code (ie - encoding bits for the instruction)
2134 // associated with each basic boolean condition for a conditional
2135 // instruction.
2136 //
2137 // Instructions specify two basic values for encoding. Again, a
2138 // function is available to check if the constant displacement is an
2139 // oop. They use the ins_encode keyword to specify their encoding
2140 // classes (which must be a sequence of enc_class names, and their
2141 // parameters, specified in the encoding block), and they use the
2142 // opcode keyword to specify, in order, their primary, secondary, and
2143 // tertiary opcode. Only the opcode sections which a particular
2144 // instruction needs for encoding need to be specified.
2145 encode %{
2146 // Build emit functions for each basic byte or larger field in the
2147 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2148 // from C++ code in the enc_class source block. Emit functions will
2149 // live in the main source block for now. In future, we can
2150 // generalize this by adding a syntax that specifies the sizes of
2151 // fields in an order, so that the adlc can build the emit functions
2152 // automagically
2154 // Emit primary opcode
2155 enc_class OpcP
2156 %{
2157 emit_opcode(cbuf, $primary);
2158 %}
2160 // Emit secondary opcode
2161 enc_class OpcS
2162 %{
2163 emit_opcode(cbuf, $secondary);
2164 %}
2166 // Emit tertiary opcode
2167 enc_class OpcT
2168 %{
2169 emit_opcode(cbuf, $tertiary);
2170 %}
2172 // Emit opcode directly
2173 enc_class Opcode(immI d8)
2174 %{
2175 emit_opcode(cbuf, $d8$$constant);
2176 %}
2178 // Emit size prefix
2179 enc_class SizePrefix
2180 %{
2181 emit_opcode(cbuf, 0x66);
2182 %}
2184 enc_class reg(rRegI reg)
2185 %{
2186 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
2187 %}
2189 enc_class reg_reg(rRegI dst, rRegI src)
2190 %{
2191 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2192 %}
2194 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
2195 %{
2196 emit_opcode(cbuf, $opcode$$constant);
2197 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2198 %}
2200 enc_class cmpfp_fixup()
2201 %{
2202 // jnp,s exit
2203 emit_opcode(cbuf, 0x7B);
2204 emit_d8(cbuf, 0x0A);
2206 // pushfq
2207 emit_opcode(cbuf, 0x9C);
2209 // andq $0xffffff2b, (%rsp)
2210 emit_opcode(cbuf, Assembler::REX_W);
2211 emit_opcode(cbuf, 0x81);
2212 emit_opcode(cbuf, 0x24);
2213 emit_opcode(cbuf, 0x24);
2214 emit_d32(cbuf, 0xffffff2b);
2216 // popfq
2217 emit_opcode(cbuf, 0x9D);
2219 // nop (target for branch to avoid branch to branch)
2220 emit_opcode(cbuf, 0x90);
2221 %}
2223 enc_class cmpfp3(rRegI dst)
2224 %{
2225 int dstenc = $dst$$reg;
2227 // movl $dst, -1
2228 if (dstenc >= 8) {
2229 emit_opcode(cbuf, Assembler::REX_B);
2230 }
2231 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2232 emit_d32(cbuf, -1);
2234 // jp,s done
2235 emit_opcode(cbuf, 0x7A);
2236 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
2238 // jb,s done
2239 emit_opcode(cbuf, 0x72);
2240 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2242 // setne $dst
2243 if (dstenc >= 4) {
2244 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2245 }
2246 emit_opcode(cbuf, 0x0F);
2247 emit_opcode(cbuf, 0x95);
2248 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2250 // movzbl $dst, $dst
2251 if (dstenc >= 4) {
2252 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2253 }
2254 emit_opcode(cbuf, 0x0F);
2255 emit_opcode(cbuf, 0xB6);
2256 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2257 %}
2259 enc_class cdql_enc(no_rax_rdx_RegI div)
2260 %{
2261 // Full implementation of Java idiv and irem; checks for
2262 // special case as described in JVM spec., p.243 & p.271.
2263 //
2264 // normal case special case
2265 //
2266 // input : rax: dividend min_int
2267 // reg: divisor -1
2268 //
2269 // output: rax: quotient (= rax idiv reg) min_int
2270 // rdx: remainder (= rax irem reg) 0
2271 //
2272 // Code sequnce:
2273 //
2274 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
2275 // 5: 75 07/08 jne e <normal>
2276 // 7: 33 d2 xor %edx,%edx
2277 // [div >= 8 -> offset + 1]
2278 // [REX_B]
2279 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
2280 // c: 74 03/04 je 11 <done>
2281 // 000000000000000e <normal>:
2282 // e: 99 cltd
2283 // [div >= 8 -> offset + 1]
2284 // [REX_B]
2285 // f: f7 f9 idiv $div
2286 // 0000000000000011 <done>:
2288 // cmp $0x80000000,%eax
2289 emit_opcode(cbuf, 0x3d);
2290 emit_d8(cbuf, 0x00);
2291 emit_d8(cbuf, 0x00);
2292 emit_d8(cbuf, 0x00);
2293 emit_d8(cbuf, 0x80);
2295 // jne e <normal>
2296 emit_opcode(cbuf, 0x75);
2297 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
2299 // xor %edx,%edx
2300 emit_opcode(cbuf, 0x33);
2301 emit_d8(cbuf, 0xD2);
2303 // cmp $0xffffffffffffffff,%ecx
2304 if ($div$$reg >= 8) {
2305 emit_opcode(cbuf, Assembler::REX_B);
2306 }
2307 emit_opcode(cbuf, 0x83);
2308 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2309 emit_d8(cbuf, 0xFF);
2311 // je 11 <done>
2312 emit_opcode(cbuf, 0x74);
2313 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2315 // <normal>
2316 // cltd
2317 emit_opcode(cbuf, 0x99);
2319 // idivl (note: must be emitted by the user of this rule)
2320 // <done>
2321 %}
2323 enc_class cdqq_enc(no_rax_rdx_RegL div)
2324 %{
2325 // Full implementation of Java ldiv and lrem; checks for
2326 // special case as described in JVM spec., p.243 & p.271.
2327 //
2328 // normal case special case
2329 //
2330 // input : rax: dividend min_long
2331 // reg: divisor -1
2332 //
2333 // output: rax: quotient (= rax idiv reg) min_long
2334 // rdx: remainder (= rax irem reg) 0
2335 //
2336 // Code sequnce:
2337 //
2338 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2339 // 7: 00 00 80
2340 // a: 48 39 d0 cmp %rdx,%rax
2341 // d: 75 08 jne 17 <normal>
2342 // f: 33 d2 xor %edx,%edx
2343 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2344 // 15: 74 05 je 1c <done>
2345 // 0000000000000017 <normal>:
2346 // 17: 48 99 cqto
2347 // 19: 48 f7 f9 idiv $div
2348 // 000000000000001c <done>:
2350 // mov $0x8000000000000000,%rdx
2351 emit_opcode(cbuf, Assembler::REX_W);
2352 emit_opcode(cbuf, 0xBA);
2353 emit_d8(cbuf, 0x00);
2354 emit_d8(cbuf, 0x00);
2355 emit_d8(cbuf, 0x00);
2356 emit_d8(cbuf, 0x00);
2357 emit_d8(cbuf, 0x00);
2358 emit_d8(cbuf, 0x00);
2359 emit_d8(cbuf, 0x00);
2360 emit_d8(cbuf, 0x80);
2362 // cmp %rdx,%rax
2363 emit_opcode(cbuf, Assembler::REX_W);
2364 emit_opcode(cbuf, 0x39);
2365 emit_d8(cbuf, 0xD0);
2367 // jne 17 <normal>
2368 emit_opcode(cbuf, 0x75);
2369 emit_d8(cbuf, 0x08);
2371 // xor %edx,%edx
2372 emit_opcode(cbuf, 0x33);
2373 emit_d8(cbuf, 0xD2);
2375 // cmp $0xffffffffffffffff,$div
2376 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2377 emit_opcode(cbuf, 0x83);
2378 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2379 emit_d8(cbuf, 0xFF);
2381 // je 1e <done>
2382 emit_opcode(cbuf, 0x74);
2383 emit_d8(cbuf, 0x05);
2385 // <normal>
2386 // cqto
2387 emit_opcode(cbuf, Assembler::REX_W);
2388 emit_opcode(cbuf, 0x99);
2390 // idivq (note: must be emitted by the user of this rule)
2391 // <done>
2392 %}
2394 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2395 enc_class OpcSE(immI imm)
2396 %{
2397 // Emit primary opcode and set sign-extend bit
2398 // Check for 8-bit immediate, and set sign extend bit in opcode
2399 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2400 emit_opcode(cbuf, $primary | 0x02);
2401 } else {
2402 // 32-bit immediate
2403 emit_opcode(cbuf, $primary);
2404 }
2405 %}
2407 enc_class OpcSErm(rRegI dst, immI imm)
2408 %{
2409 // OpcSEr/m
2410 int dstenc = $dst$$reg;
2411 if (dstenc >= 8) {
2412 emit_opcode(cbuf, Assembler::REX_B);
2413 dstenc -= 8;
2414 }
2415 // Emit primary opcode and set sign-extend bit
2416 // Check for 8-bit immediate, and set sign extend bit in opcode
2417 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2418 emit_opcode(cbuf, $primary | 0x02);
2419 } else {
2420 // 32-bit immediate
2421 emit_opcode(cbuf, $primary);
2422 }
2423 // Emit r/m byte with secondary opcode, after primary opcode.
2424 emit_rm(cbuf, 0x3, $secondary, dstenc);
2425 %}
2427 enc_class OpcSErm_wide(rRegL dst, immI imm)
2428 %{
2429 // OpcSEr/m
2430 int dstenc = $dst$$reg;
2431 if (dstenc < 8) {
2432 emit_opcode(cbuf, Assembler::REX_W);
2433 } else {
2434 emit_opcode(cbuf, Assembler::REX_WB);
2435 dstenc -= 8;
2436 }
2437 // Emit primary opcode and set sign-extend bit
2438 // Check for 8-bit immediate, and set sign extend bit in opcode
2439 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2440 emit_opcode(cbuf, $primary | 0x02);
2441 } else {
2442 // 32-bit immediate
2443 emit_opcode(cbuf, $primary);
2444 }
2445 // Emit r/m byte with secondary opcode, after primary opcode.
2446 emit_rm(cbuf, 0x3, $secondary, dstenc);
2447 %}
2449 enc_class Con8or32(immI imm)
2450 %{
2451 // Check for 8-bit immediate, and set sign extend bit in opcode
2452 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2453 $$$emit8$imm$$constant;
2454 } else {
2455 // 32-bit immediate
2456 $$$emit32$imm$$constant;
2457 }
2458 %}
2460 enc_class Lbl(label labl)
2461 %{
2462 // JMP, CALL
2463 Label* l = $labl$$label;
2464 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2465 %}
2467 enc_class LblShort(label labl)
2468 %{
2469 // JMP, CALL
2470 Label* l = $labl$$label;
2471 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2472 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2473 emit_d8(cbuf, disp);
2474 %}
2476 enc_class opc2_reg(rRegI dst)
2477 %{
2478 // BSWAP
2479 emit_cc(cbuf, $secondary, $dst$$reg);
2480 %}
2482 enc_class opc3_reg(rRegI dst)
2483 %{
2484 // BSWAP
2485 emit_cc(cbuf, $tertiary, $dst$$reg);
2486 %}
2488 enc_class reg_opc(rRegI div)
2489 %{
2490 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2491 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2492 %}
2494 enc_class Jcc(cmpOp cop, label labl)
2495 %{
2496 // JCC
2497 Label* l = $labl$$label;
2498 $$$emit8$primary;
2499 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2500 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2501 %}
2503 enc_class JccShort (cmpOp cop, label labl)
2504 %{
2505 // JCC
2506 Label *l = $labl$$label;
2507 emit_cc(cbuf, $primary, $cop$$cmpcode);
2508 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2509 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2510 emit_d8(cbuf, disp);
2511 %}
2513 enc_class enc_cmov(cmpOp cop)
2514 %{
2515 // CMOV
2516 $$$emit8$primary;
2517 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2518 %}
2520 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
2521 %{
2522 // Invert sense of branch from sense of cmov
2523 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2524 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
2525 ? (UseXmmRegToRegMoveAll ? 3 : 4)
2526 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
2527 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
2528 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
2529 if ($dst$$reg < 8) {
2530 if ($src$$reg >= 8) {
2531 emit_opcode(cbuf, Assembler::REX_B);
2532 }
2533 } else {
2534 if ($src$$reg < 8) {
2535 emit_opcode(cbuf, Assembler::REX_R);
2536 } else {
2537 emit_opcode(cbuf, Assembler::REX_RB);
2538 }
2539 }
2540 emit_opcode(cbuf, 0x0F);
2541 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2542 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2543 %}
2545 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
2546 %{
2547 // Invert sense of branch from sense of cmov
2548 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2549 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
2551 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
2552 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
2553 if ($dst$$reg < 8) {
2554 if ($src$$reg >= 8) {
2555 emit_opcode(cbuf, Assembler::REX_B);
2556 }
2557 } else {
2558 if ($src$$reg < 8) {
2559 emit_opcode(cbuf, Assembler::REX_R);
2560 } else {
2561 emit_opcode(cbuf, Assembler::REX_RB);
2562 }
2563 }
2564 emit_opcode(cbuf, 0x0F);
2565 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2566 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2567 %}
2569 enc_class enc_PartialSubtypeCheck()
2570 %{
2571 Register Rrdi = as_Register(RDI_enc); // result register
2572 Register Rrax = as_Register(RAX_enc); // super class
2573 Register Rrcx = as_Register(RCX_enc); // killed
2574 Register Rrsi = as_Register(RSI_enc); // sub class
2575 Label hit, miss, cmiss;
2577 MacroAssembler _masm(&cbuf);
2578 // Compare super with sub directly, since super is not in its own SSA.
2579 // The compiler used to emit this test, but we fold it in here,
2580 // to allow platform-specific tweaking on sparc.
2581 __ cmpptr(Rrax, Rrsi);
2582 __ jcc(Assembler::equal, hit);
2583 #ifndef PRODUCT
2584 __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
2585 __ incrementl(Address(Rrcx, 0));
2586 #endif //PRODUCT
2587 __ movptr(Rrdi, Address(Rrsi,
2588 sizeof(oopDesc) +
2589 Klass::secondary_supers_offset_in_bytes()));
2590 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes()));
2591 __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
2592 if (UseCompressedOops) {
2593 __ encode_heap_oop(Rrax);
2594 __ repne_scanl();
2595 __ jcc(Assembler::notEqual, cmiss);
2596 __ decode_heap_oop(Rrax);
2597 __ movptr(Address(Rrsi,
2598 sizeof(oopDesc) +
2599 Klass::secondary_super_cache_offset_in_bytes()),
2600 Rrax);
2601 __ jmp(hit);
2602 __ bind(cmiss);
2603 __ decode_heap_oop(Rrax);
2604 __ jmp(miss);
2605 } else {
2606 __ repne_scan();
2607 __ jcc(Assembler::notEqual, miss);
2608 __ movptr(Address(Rrsi,
2609 sizeof(oopDesc) +
2610 Klass::secondary_super_cache_offset_in_bytes()),
2611 Rrax);
2612 }
2613 __ bind(hit);
2614 if ($primary) {
2615 __ xorptr(Rrdi, Rrdi);
2616 }
2617 __ bind(miss);
2618 %}
2620 enc_class Java_To_Interpreter(method meth)
2621 %{
2622 // CALL Java_To_Interpreter
2623 // This is the instruction starting address for relocation info.
2624 cbuf.set_inst_mark();
2625 $$$emit8$primary;
2626 // CALL directly to the runtime
2627 emit_d32_reloc(cbuf,
2628 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2629 runtime_call_Relocation::spec(),
2630 RELOC_DISP32);
2631 %}
2633 enc_class Java_Static_Call(method meth)
2634 %{
2635 // JAVA STATIC CALL
2636 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2637 // determine who we intended to call.
2638 cbuf.set_inst_mark();
2639 $$$emit8$primary;
2641 if (!_method) {
2642 emit_d32_reloc(cbuf,
2643 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2644 runtime_call_Relocation::spec(),
2645 RELOC_DISP32);
2646 } else if (_optimized_virtual) {
2647 emit_d32_reloc(cbuf,
2648 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2649 opt_virtual_call_Relocation::spec(),
2650 RELOC_DISP32);
2651 } else {
2652 emit_d32_reloc(cbuf,
2653 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2654 static_call_Relocation::spec(),
2655 RELOC_DISP32);
2656 }
2657 if (_method) {
2658 // Emit stub for static call
2659 emit_java_to_interp(cbuf);
2660 }
2661 %}
2663 enc_class Java_Dynamic_Call(method meth)
2664 %{
2665 // JAVA DYNAMIC CALL
2666 // !!!!!
2667 // Generate "movq rax, -1", placeholder instruction to load oop-info
2668 // emit_call_dynamic_prologue( cbuf );
2669 cbuf.set_inst_mark();
2671 // movq rax, -1
2672 emit_opcode(cbuf, Assembler::REX_W);
2673 emit_opcode(cbuf, 0xB8 | RAX_enc);
2674 emit_d64_reloc(cbuf,
2675 (int64_t) Universe::non_oop_word(),
2676 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2677 address virtual_call_oop_addr = cbuf.inst_mark();
2678 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2679 // who we intended to call.
2680 cbuf.set_inst_mark();
2681 $$$emit8$primary;
2682 emit_d32_reloc(cbuf,
2683 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2684 virtual_call_Relocation::spec(virtual_call_oop_addr),
2685 RELOC_DISP32);
2686 %}
2688 enc_class Java_Compiled_Call(method meth)
2689 %{
2690 // JAVA COMPILED CALL
2691 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2693 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2694 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2696 // callq *disp(%rax)
2697 cbuf.set_inst_mark();
2698 $$$emit8$primary;
2699 if (disp < 0x80) {
2700 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2701 emit_d8(cbuf, disp); // Displacement
2702 } else {
2703 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2704 emit_d32(cbuf, disp); // Displacement
2705 }
2706 %}
2708 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2709 %{
2710 // SAL, SAR, SHR
2711 int dstenc = $dst$$reg;
2712 if (dstenc >= 8) {
2713 emit_opcode(cbuf, Assembler::REX_B);
2714 dstenc -= 8;
2715 }
2716 $$$emit8$primary;
2717 emit_rm(cbuf, 0x3, $secondary, dstenc);
2718 $$$emit8$shift$$constant;
2719 %}
2721 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2722 %{
2723 // SAL, SAR, SHR
2724 int dstenc = $dst$$reg;
2725 if (dstenc < 8) {
2726 emit_opcode(cbuf, Assembler::REX_W);
2727 } else {
2728 emit_opcode(cbuf, Assembler::REX_WB);
2729 dstenc -= 8;
2730 }
2731 $$$emit8$primary;
2732 emit_rm(cbuf, 0x3, $secondary, dstenc);
2733 $$$emit8$shift$$constant;
2734 %}
2736 enc_class load_immI(rRegI dst, immI src)
2737 %{
2738 int dstenc = $dst$$reg;
2739 if (dstenc >= 8) {
2740 emit_opcode(cbuf, Assembler::REX_B);
2741 dstenc -= 8;
2742 }
2743 emit_opcode(cbuf, 0xB8 | dstenc);
2744 $$$emit32$src$$constant;
2745 %}
2747 enc_class load_immL(rRegL dst, immL src)
2748 %{
2749 int dstenc = $dst$$reg;
2750 if (dstenc < 8) {
2751 emit_opcode(cbuf, Assembler::REX_W);
2752 } else {
2753 emit_opcode(cbuf, Assembler::REX_WB);
2754 dstenc -= 8;
2755 }
2756 emit_opcode(cbuf, 0xB8 | dstenc);
2757 emit_d64(cbuf, $src$$constant);
2758 %}
2760 enc_class load_immUL32(rRegL dst, immUL32 src)
2761 %{
2762 // same as load_immI, but this time we care about zeroes in the high word
2763 int dstenc = $dst$$reg;
2764 if (dstenc >= 8) {
2765 emit_opcode(cbuf, Assembler::REX_B);
2766 dstenc -= 8;
2767 }
2768 emit_opcode(cbuf, 0xB8 | dstenc);
2769 $$$emit32$src$$constant;
2770 %}
2772 enc_class load_immL32(rRegL dst, immL32 src)
2773 %{
2774 int dstenc = $dst$$reg;
2775 if (dstenc < 8) {
2776 emit_opcode(cbuf, Assembler::REX_W);
2777 } else {
2778 emit_opcode(cbuf, Assembler::REX_WB);
2779 dstenc -= 8;
2780 }
2781 emit_opcode(cbuf, 0xC7);
2782 emit_rm(cbuf, 0x03, 0x00, dstenc);
2783 $$$emit32$src$$constant;
2784 %}
2786 enc_class load_immP31(rRegP dst, immP32 src)
2787 %{
2788 // same as load_immI, but this time we care about zeroes in the high word
2789 int dstenc = $dst$$reg;
2790 if (dstenc >= 8) {
2791 emit_opcode(cbuf, Assembler::REX_B);
2792 dstenc -= 8;
2793 }
2794 emit_opcode(cbuf, 0xB8 | dstenc);
2795 $$$emit32$src$$constant;
2796 %}
2798 enc_class load_immP(rRegP dst, immP src)
2799 %{
2800 int dstenc = $dst$$reg;
2801 if (dstenc < 8) {
2802 emit_opcode(cbuf, Assembler::REX_W);
2803 } else {
2804 emit_opcode(cbuf, Assembler::REX_WB);
2805 dstenc -= 8;
2806 }
2807 emit_opcode(cbuf, 0xB8 | dstenc);
2808 // This next line should be generated from ADLC
2809 if ($src->constant_is_oop()) {
2810 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2811 } else {
2812 emit_d64(cbuf, $src$$constant);
2813 }
2814 %}
2816 enc_class load_immF(regF dst, immF con)
2817 %{
2818 // XXX reg_mem doesn't support RIP-relative addressing yet
2819 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2820 emit_float_constant(cbuf, $con$$constant);
2821 %}
2823 enc_class load_immD(regD dst, immD con)
2824 %{
2825 // XXX reg_mem doesn't support RIP-relative addressing yet
2826 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2827 emit_double_constant(cbuf, $con$$constant);
2828 %}
2830 enc_class load_conF (regF dst, immF con) %{ // Load float constant
2831 emit_opcode(cbuf, 0xF3);
2832 if ($dst$$reg >= 8) {
2833 emit_opcode(cbuf, Assembler::REX_R);
2834 }
2835 emit_opcode(cbuf, 0x0F);
2836 emit_opcode(cbuf, 0x10);
2837 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2838 emit_float_constant(cbuf, $con$$constant);
2839 %}
2841 enc_class load_conD (regD dst, immD con) %{ // Load double constant
2842 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2843 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2844 if ($dst$$reg >= 8) {
2845 emit_opcode(cbuf, Assembler::REX_R);
2846 }
2847 emit_opcode(cbuf, 0x0F);
2848 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2849 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2850 emit_double_constant(cbuf, $con$$constant);
2851 %}
2853 // Encode a reg-reg copy. If it is useless, then empty encoding.
2854 enc_class enc_copy(rRegI dst, rRegI src)
2855 %{
2856 encode_copy(cbuf, $dst$$reg, $src$$reg);
2857 %}
2859 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2860 enc_class enc_CopyXD( RegD dst, RegD src ) %{
2861 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2862 %}
2864 enc_class enc_copy_always(rRegI dst, rRegI src)
2865 %{
2866 int srcenc = $src$$reg;
2867 int dstenc = $dst$$reg;
2869 if (dstenc < 8) {
2870 if (srcenc >= 8) {
2871 emit_opcode(cbuf, Assembler::REX_B);
2872 srcenc -= 8;
2873 }
2874 } else {
2875 if (srcenc < 8) {
2876 emit_opcode(cbuf, Assembler::REX_R);
2877 } else {
2878 emit_opcode(cbuf, Assembler::REX_RB);
2879 srcenc -= 8;
2880 }
2881 dstenc -= 8;
2882 }
2884 emit_opcode(cbuf, 0x8B);
2885 emit_rm(cbuf, 0x3, dstenc, srcenc);
2886 %}
2888 enc_class enc_copy_wide(rRegL dst, rRegL src)
2889 %{
2890 int srcenc = $src$$reg;
2891 int dstenc = $dst$$reg;
2893 if (dstenc != srcenc) {
2894 if (dstenc < 8) {
2895 if (srcenc < 8) {
2896 emit_opcode(cbuf, Assembler::REX_W);
2897 } else {
2898 emit_opcode(cbuf, Assembler::REX_WB);
2899 srcenc -= 8;
2900 }
2901 } else {
2902 if (srcenc < 8) {
2903 emit_opcode(cbuf, Assembler::REX_WR);
2904 } else {
2905 emit_opcode(cbuf, Assembler::REX_WRB);
2906 srcenc -= 8;
2907 }
2908 dstenc -= 8;
2909 }
2910 emit_opcode(cbuf, 0x8B);
2911 emit_rm(cbuf, 0x3, dstenc, srcenc);
2912 }
2913 %}
2915 enc_class Con32(immI src)
2916 %{
2917 // Output immediate
2918 $$$emit32$src$$constant;
2919 %}
2921 enc_class Con64(immL src)
2922 %{
2923 // Output immediate
2924 emit_d64($src$$constant);
2925 %}
2927 enc_class Con32F_as_bits(immF src)
2928 %{
2929 // Output Float immediate bits
2930 jfloat jf = $src$$constant;
2931 jint jf_as_bits = jint_cast(jf);
2932 emit_d32(cbuf, jf_as_bits);
2933 %}
2935 enc_class Con16(immI src)
2936 %{
2937 // Output immediate
2938 $$$emit16$src$$constant;
2939 %}
2941 // How is this different from Con32??? XXX
2942 enc_class Con_d32(immI src)
2943 %{
2944 emit_d32(cbuf,$src$$constant);
2945 %}
2947 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2948 // Output immediate memory reference
2949 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2950 emit_d32(cbuf, 0x00);
2951 %}
2953 enc_class jump_enc(rRegL switch_val, rRegI dest) %{
2954 MacroAssembler masm(&cbuf);
2956 Register switch_reg = as_Register($switch_val$$reg);
2957 Register dest_reg = as_Register($dest$$reg);
2958 address table_base = masm.address_table_constant(_index2label);
2960 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2961 // to do that and the compiler is using that register as one it can allocate.
2962 // So we build it all by hand.
2963 // Address index(noreg, switch_reg, Address::times_1);
2964 // ArrayAddress dispatch(table, index);
2966 Address dispatch(dest_reg, switch_reg, Address::times_1);
2968 masm.lea(dest_reg, InternalAddress(table_base));
2969 masm.jmp(dispatch);
2970 %}
2972 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
2973 MacroAssembler masm(&cbuf);
2975 Register switch_reg = as_Register($switch_val$$reg);
2976 Register dest_reg = as_Register($dest$$reg);
2977 address table_base = masm.address_table_constant(_index2label);
2979 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2980 // to do that and the compiler is using that register as one it can allocate.
2981 // So we build it all by hand.
2982 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2983 // ArrayAddress dispatch(table, index);
2985 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2987 masm.lea(dest_reg, InternalAddress(table_base));
2988 masm.jmp(dispatch);
2989 %}
2991 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
2992 MacroAssembler masm(&cbuf);
2994 Register switch_reg = as_Register($switch_val$$reg);
2995 Register dest_reg = as_Register($dest$$reg);
2996 address table_base = masm.address_table_constant(_index2label);
2998 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2999 // to do that and the compiler is using that register as one it can allocate.
3000 // So we build it all by hand.
3001 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3002 // ArrayAddress dispatch(table, index);
3004 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3005 masm.lea(dest_reg, InternalAddress(table_base));
3006 masm.jmp(dispatch);
3008 %}
3010 enc_class lock_prefix()
3011 %{
3012 if (os::is_MP()) {
3013 emit_opcode(cbuf, 0xF0); // lock
3014 }
3015 %}
3017 enc_class REX_mem(memory mem)
3018 %{
3019 if ($mem$$base >= 8) {
3020 if ($mem$$index < 8) {
3021 emit_opcode(cbuf, Assembler::REX_B);
3022 } else {
3023 emit_opcode(cbuf, Assembler::REX_XB);
3024 }
3025 } else {
3026 if ($mem$$index >= 8) {
3027 emit_opcode(cbuf, Assembler::REX_X);
3028 }
3029 }
3030 %}
3032 enc_class REX_mem_wide(memory mem)
3033 %{
3034 if ($mem$$base >= 8) {
3035 if ($mem$$index < 8) {
3036 emit_opcode(cbuf, Assembler::REX_WB);
3037 } else {
3038 emit_opcode(cbuf, Assembler::REX_WXB);
3039 }
3040 } else {
3041 if ($mem$$index < 8) {
3042 emit_opcode(cbuf, Assembler::REX_W);
3043 } else {
3044 emit_opcode(cbuf, Assembler::REX_WX);
3045 }
3046 }
3047 %}
3049 // for byte regs
3050 enc_class REX_breg(rRegI reg)
3051 %{
3052 if ($reg$$reg >= 4) {
3053 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3054 }
3055 %}
3057 // for byte regs
3058 enc_class REX_reg_breg(rRegI dst, rRegI src)
3059 %{
3060 if ($dst$$reg < 8) {
3061 if ($src$$reg >= 4) {
3062 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3063 }
3064 } else {
3065 if ($src$$reg < 8) {
3066 emit_opcode(cbuf, Assembler::REX_R);
3067 } else {
3068 emit_opcode(cbuf, Assembler::REX_RB);
3069 }
3070 }
3071 %}
3073 // for byte regs
3074 enc_class REX_breg_mem(rRegI reg, memory mem)
3075 %{
3076 if ($reg$$reg < 8) {
3077 if ($mem$$base < 8) {
3078 if ($mem$$index >= 8) {
3079 emit_opcode(cbuf, Assembler::REX_X);
3080 } else if ($reg$$reg >= 4) {
3081 emit_opcode(cbuf, Assembler::REX);
3082 }
3083 } else {
3084 if ($mem$$index < 8) {
3085 emit_opcode(cbuf, Assembler::REX_B);
3086 } else {
3087 emit_opcode(cbuf, Assembler::REX_XB);
3088 }
3089 }
3090 } else {
3091 if ($mem$$base < 8) {
3092 if ($mem$$index < 8) {
3093 emit_opcode(cbuf, Assembler::REX_R);
3094 } else {
3095 emit_opcode(cbuf, Assembler::REX_RX);
3096 }
3097 } else {
3098 if ($mem$$index < 8) {
3099 emit_opcode(cbuf, Assembler::REX_RB);
3100 } else {
3101 emit_opcode(cbuf, Assembler::REX_RXB);
3102 }
3103 }
3104 }
3105 %}
3107 enc_class REX_reg(rRegI reg)
3108 %{
3109 if ($reg$$reg >= 8) {
3110 emit_opcode(cbuf, Assembler::REX_B);
3111 }
3112 %}
3114 enc_class REX_reg_wide(rRegI reg)
3115 %{
3116 if ($reg$$reg < 8) {
3117 emit_opcode(cbuf, Assembler::REX_W);
3118 } else {
3119 emit_opcode(cbuf, Assembler::REX_WB);
3120 }
3121 %}
3123 enc_class REX_reg_reg(rRegI dst, rRegI src)
3124 %{
3125 if ($dst$$reg < 8) {
3126 if ($src$$reg >= 8) {
3127 emit_opcode(cbuf, Assembler::REX_B);
3128 }
3129 } else {
3130 if ($src$$reg < 8) {
3131 emit_opcode(cbuf, Assembler::REX_R);
3132 } else {
3133 emit_opcode(cbuf, Assembler::REX_RB);
3134 }
3135 }
3136 %}
3138 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
3139 %{
3140 if ($dst$$reg < 8) {
3141 if ($src$$reg < 8) {
3142 emit_opcode(cbuf, Assembler::REX_W);
3143 } else {
3144 emit_opcode(cbuf, Assembler::REX_WB);
3145 }
3146 } else {
3147 if ($src$$reg < 8) {
3148 emit_opcode(cbuf, Assembler::REX_WR);
3149 } else {
3150 emit_opcode(cbuf, Assembler::REX_WRB);
3151 }
3152 }
3153 %}
3155 enc_class REX_reg_mem(rRegI reg, memory mem)
3156 %{
3157 if ($reg$$reg < 8) {
3158 if ($mem$$base < 8) {
3159 if ($mem$$index >= 8) {
3160 emit_opcode(cbuf, Assembler::REX_X);
3161 }
3162 } else {
3163 if ($mem$$index < 8) {
3164 emit_opcode(cbuf, Assembler::REX_B);
3165 } else {
3166 emit_opcode(cbuf, Assembler::REX_XB);
3167 }
3168 }
3169 } else {
3170 if ($mem$$base < 8) {
3171 if ($mem$$index < 8) {
3172 emit_opcode(cbuf, Assembler::REX_R);
3173 } else {
3174 emit_opcode(cbuf, Assembler::REX_RX);
3175 }
3176 } else {
3177 if ($mem$$index < 8) {
3178 emit_opcode(cbuf, Assembler::REX_RB);
3179 } else {
3180 emit_opcode(cbuf, Assembler::REX_RXB);
3181 }
3182 }
3183 }
3184 %}
3186 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
3187 %{
3188 if ($reg$$reg < 8) {
3189 if ($mem$$base < 8) {
3190 if ($mem$$index < 8) {
3191 emit_opcode(cbuf, Assembler::REX_W);
3192 } else {
3193 emit_opcode(cbuf, Assembler::REX_WX);
3194 }
3195 } else {
3196 if ($mem$$index < 8) {
3197 emit_opcode(cbuf, Assembler::REX_WB);
3198 } else {
3199 emit_opcode(cbuf, Assembler::REX_WXB);
3200 }
3201 }
3202 } else {
3203 if ($mem$$base < 8) {
3204 if ($mem$$index < 8) {
3205 emit_opcode(cbuf, Assembler::REX_WR);
3206 } else {
3207 emit_opcode(cbuf, Assembler::REX_WRX);
3208 }
3209 } else {
3210 if ($mem$$index < 8) {
3211 emit_opcode(cbuf, Assembler::REX_WRB);
3212 } else {
3213 emit_opcode(cbuf, Assembler::REX_WRXB);
3214 }
3215 }
3216 }
3217 %}
3219 enc_class reg_mem(rRegI ereg, memory mem)
3220 %{
3221 // High registers handle in encode_RegMem
3222 int reg = $ereg$$reg;
3223 int base = $mem$$base;
3224 int index = $mem$$index;
3225 int scale = $mem$$scale;
3226 int disp = $mem$$disp;
3227 bool disp_is_oop = $mem->disp_is_oop();
3229 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
3230 %}
3232 enc_class RM_opc_mem(immI rm_opcode, memory mem)
3233 %{
3234 int rm_byte_opcode = $rm_opcode$$constant;
3236 // High registers handle in encode_RegMem
3237 int base = $mem$$base;
3238 int index = $mem$$index;
3239 int scale = $mem$$scale;
3240 int displace = $mem$$disp;
3242 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
3243 // working with static
3244 // globals
3245 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
3246 disp_is_oop);
3247 %}
3249 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
3250 %{
3251 int reg_encoding = $dst$$reg;
3252 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
3253 int index = 0x04; // 0x04 indicates no index
3254 int scale = 0x00; // 0x00 indicates no scale
3255 int displace = $src1$$constant; // 0x00 indicates no displacement
3256 bool disp_is_oop = false;
3257 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
3258 disp_is_oop);
3259 %}
3261 enc_class neg_reg(rRegI dst)
3262 %{
3263 int dstenc = $dst$$reg;
3264 if (dstenc >= 8) {
3265 emit_opcode(cbuf, Assembler::REX_B);
3266 dstenc -= 8;
3267 }
3268 // NEG $dst
3269 emit_opcode(cbuf, 0xF7);
3270 emit_rm(cbuf, 0x3, 0x03, dstenc);
3271 %}
3273 enc_class neg_reg_wide(rRegI dst)
3274 %{
3275 int dstenc = $dst$$reg;
3276 if (dstenc < 8) {
3277 emit_opcode(cbuf, Assembler::REX_W);
3278 } else {
3279 emit_opcode(cbuf, Assembler::REX_WB);
3280 dstenc -= 8;
3281 }
3282 // NEG $dst
3283 emit_opcode(cbuf, 0xF7);
3284 emit_rm(cbuf, 0x3, 0x03, dstenc);
3285 %}
3287 enc_class setLT_reg(rRegI dst)
3288 %{
3289 int dstenc = $dst$$reg;
3290 if (dstenc >= 8) {
3291 emit_opcode(cbuf, Assembler::REX_B);
3292 dstenc -= 8;
3293 } else if (dstenc >= 4) {
3294 emit_opcode(cbuf, Assembler::REX);
3295 }
3296 // SETLT $dst
3297 emit_opcode(cbuf, 0x0F);
3298 emit_opcode(cbuf, 0x9C);
3299 emit_rm(cbuf, 0x3, 0x0, dstenc);
3300 %}
3302 enc_class setNZ_reg(rRegI dst)
3303 %{
3304 int dstenc = $dst$$reg;
3305 if (dstenc >= 8) {
3306 emit_opcode(cbuf, Assembler::REX_B);
3307 dstenc -= 8;
3308 } else if (dstenc >= 4) {
3309 emit_opcode(cbuf, Assembler::REX);
3310 }
3311 // SETNZ $dst
3312 emit_opcode(cbuf, 0x0F);
3313 emit_opcode(cbuf, 0x95);
3314 emit_rm(cbuf, 0x3, 0x0, dstenc);
3315 %}
3317 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
3318 rcx_RegI tmp)
3319 %{
3320 // cadd_cmpLT
3322 int tmpReg = $tmp$$reg;
3324 int penc = $p$$reg;
3325 int qenc = $q$$reg;
3326 int yenc = $y$$reg;
3328 // subl $p,$q
3329 if (penc < 8) {
3330 if (qenc >= 8) {
3331 emit_opcode(cbuf, Assembler::REX_B);
3332 }
3333 } else {
3334 if (qenc < 8) {
3335 emit_opcode(cbuf, Assembler::REX_R);
3336 } else {
3337 emit_opcode(cbuf, Assembler::REX_RB);
3338 }
3339 }
3340 emit_opcode(cbuf, 0x2B);
3341 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
3343 // sbbl $tmp, $tmp
3344 emit_opcode(cbuf, 0x1B);
3345 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
3347 // andl $tmp, $y
3348 if (yenc >= 8) {
3349 emit_opcode(cbuf, Assembler::REX_B);
3350 }
3351 emit_opcode(cbuf, 0x23);
3352 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
3354 // addl $p,$tmp
3355 if (penc >= 8) {
3356 emit_opcode(cbuf, Assembler::REX_R);
3357 }
3358 emit_opcode(cbuf, 0x03);
3359 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
3360 %}
3362 // Compare the lonogs and set -1, 0, or 1 into dst
3363 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
3364 %{
3365 int src1enc = $src1$$reg;
3366 int src2enc = $src2$$reg;
3367 int dstenc = $dst$$reg;
3369 // cmpq $src1, $src2
3370 if (src1enc < 8) {
3371 if (src2enc < 8) {
3372 emit_opcode(cbuf, Assembler::REX_W);
3373 } else {
3374 emit_opcode(cbuf, Assembler::REX_WB);
3375 }
3376 } else {
3377 if (src2enc < 8) {
3378 emit_opcode(cbuf, Assembler::REX_WR);
3379 } else {
3380 emit_opcode(cbuf, Assembler::REX_WRB);
3381 }
3382 }
3383 emit_opcode(cbuf, 0x3B);
3384 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
3386 // movl $dst, -1
3387 if (dstenc >= 8) {
3388 emit_opcode(cbuf, Assembler::REX_B);
3389 }
3390 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
3391 emit_d32(cbuf, -1);
3393 // jl,s done
3394 emit_opcode(cbuf, 0x7C);
3395 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
3397 // setne $dst
3398 if (dstenc >= 4) {
3399 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
3400 }
3401 emit_opcode(cbuf, 0x0F);
3402 emit_opcode(cbuf, 0x95);
3403 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
3405 // movzbl $dst, $dst
3406 if (dstenc >= 4) {
3407 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
3408 }
3409 emit_opcode(cbuf, 0x0F);
3410 emit_opcode(cbuf, 0xB6);
3411 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
3412 %}
3414 enc_class Push_ResultXD(regD dst) %{
3415 int dstenc = $dst$$reg;
3417 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
3419 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
3420 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
3421 if (dstenc >= 8) {
3422 emit_opcode(cbuf, Assembler::REX_R);
3423 }
3424 emit_opcode (cbuf, 0x0F );
3425 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
3426 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
3428 // add rsp,8
3429 emit_opcode(cbuf, Assembler::REX_W);
3430 emit_opcode(cbuf,0x83);
3431 emit_rm(cbuf,0x3, 0x0, RSP_enc);
3432 emit_d8(cbuf,0x08);
3433 %}
3435 enc_class Push_SrcXD(regD src) %{
3436 int srcenc = $src$$reg;
3438 // subq rsp,#8
3439 emit_opcode(cbuf, Assembler::REX_W);
3440 emit_opcode(cbuf, 0x83);
3441 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3442 emit_d8(cbuf, 0x8);
3444 // movsd [rsp],src
3445 emit_opcode(cbuf, 0xF2);
3446 if (srcenc >= 8) {
3447 emit_opcode(cbuf, Assembler::REX_R);
3448 }
3449 emit_opcode(cbuf, 0x0F);
3450 emit_opcode(cbuf, 0x11);
3451 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
3453 // fldd [rsp]
3454 emit_opcode(cbuf, 0x66);
3455 emit_opcode(cbuf, 0xDD);
3456 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
3457 %}
3460 enc_class movq_ld(regD dst, memory mem) %{
3461 MacroAssembler _masm(&cbuf);
3462 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3463 __ movq(as_XMMRegister($dst$$reg), madr);
3464 %}
3466 enc_class movq_st(memory mem, regD src) %{
3467 MacroAssembler _masm(&cbuf);
3468 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3469 __ movq(madr, as_XMMRegister($src$$reg));
3470 %}
3472 enc_class pshufd_8x8(regF dst, regF src) %{
3473 MacroAssembler _masm(&cbuf);
3475 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3476 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3477 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3478 %}
3480 enc_class pshufd_4x16(regF dst, regF src) %{
3481 MacroAssembler _masm(&cbuf);
3483 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3484 %}
3486 enc_class pshufd(regD dst, regD src, int mode) %{
3487 MacroAssembler _masm(&cbuf);
3489 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3490 %}
3492 enc_class pxor(regD dst, regD src) %{
3493 MacroAssembler _masm(&cbuf);
3495 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3496 %}
3498 enc_class mov_i2x(regD dst, rRegI src) %{
3499 MacroAssembler _masm(&cbuf);
3501 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3502 %}
3504 // obj: object to lock
3505 // box: box address (header location) -- killed
3506 // tmp: rax -- killed
3507 // scr: rbx -- killed
3508 //
3509 // What follows is a direct transliteration of fast_lock() and fast_unlock()
3510 // from i486.ad. See that file for comments.
3511 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
3512 // use the shorter encoding. (Movl clears the high-order 32-bits).
3515 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
3516 %{
3517 Register objReg = as_Register((int)$obj$$reg);
3518 Register boxReg = as_Register((int)$box$$reg);
3519 Register tmpReg = as_Register($tmp$$reg);
3520 Register scrReg = as_Register($scr$$reg);
3521 MacroAssembler masm(&cbuf);
3523 // Verify uniqueness of register assignments -- necessary but not sufficient
3524 assert (objReg != boxReg && objReg != tmpReg &&
3525 objReg != scrReg && tmpReg != scrReg, "invariant") ;
3527 if (_counters != NULL) {
3528 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3529 }
3530 if (EmitSync & 1) {
3531 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3532 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3533 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
3534 } else
3535 if (EmitSync & 2) {
3536 Label DONE_LABEL;
3537 if (UseBiasedLocking) {
3538 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3539 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3540 }
3541 // QQQ was movl...
3542 masm.movptr(tmpReg, 0x1);
3543 masm.orptr(tmpReg, Address(objReg, 0));
3544 masm.movptr(Address(boxReg, 0), tmpReg);
3545 if (os::is_MP()) {
3546 masm.lock();
3547 }
3548 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3549 masm.jcc(Assembler::equal, DONE_LABEL);
3551 // Recursive locking
3552 masm.subptr(tmpReg, rsp);
3553 masm.andptr(tmpReg, 7 - os::vm_page_size());
3554 masm.movptr(Address(boxReg, 0), tmpReg);
3556 masm.bind(DONE_LABEL);
3557 masm.nop(); // avoid branch to branch
3558 } else {
3559 Label DONE_LABEL, IsInflated, Egress;
3561 masm.movptr(tmpReg, Address(objReg, 0)) ;
3562 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
3563 masm.jcc (Assembler::notZero, IsInflated) ;
3565 // it's stack-locked, biased or neutral
3566 // TODO: optimize markword triage order to reduce the number of
3567 // conditional branches in the most common cases.
3568 // Beware -- there's a subtle invariant that fetch of the markword
3569 // at [FETCH], below, will never observe a biased encoding (*101b).
3570 // If this invariant is not held we'll suffer exclusion (safety) failure.
3572 if (UseBiasedLocking) {
3573 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
3574 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3575 }
3577 // was q will it destroy high?
3578 masm.orl (tmpReg, 1) ;
3579 masm.movptr(Address(boxReg, 0), tmpReg) ;
3580 if (os::is_MP()) { masm.lock(); }
3581 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3582 if (_counters != NULL) {
3583 masm.cond_inc32(Assembler::equal,
3584 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3585 }
3586 masm.jcc (Assembler::equal, DONE_LABEL);
3588 // Recursive locking
3589 masm.subptr(tmpReg, rsp);
3590 masm.andptr(tmpReg, 7 - os::vm_page_size());
3591 masm.movptr(Address(boxReg, 0), tmpReg);
3592 if (_counters != NULL) {
3593 masm.cond_inc32(Assembler::equal,
3594 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3595 }
3596 masm.jmp (DONE_LABEL) ;
3598 masm.bind (IsInflated) ;
3599 // It's inflated
3601 // TODO: someday avoid the ST-before-CAS penalty by
3602 // relocating (deferring) the following ST.
3603 // We should also think about trying a CAS without having
3604 // fetched _owner. If the CAS is successful we may
3605 // avoid an RTO->RTS upgrade on the $line.
3606 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3607 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3609 masm.mov (boxReg, tmpReg) ;
3610 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3611 masm.testptr(tmpReg, tmpReg) ;
3612 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3614 // It's inflated and appears unlocked
3615 if (os::is_MP()) { masm.lock(); }
3616 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3617 // Intentional fall-through into DONE_LABEL ...
3619 masm.bind (DONE_LABEL) ;
3620 masm.nop () ; // avoid jmp to jmp
3621 }
3622 %}
3624 // obj: object to unlock
3625 // box: box address (displaced header location), killed
3626 // RBX: killed tmp; cannot be obj nor box
3627 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
3628 %{
3630 Register objReg = as_Register($obj$$reg);
3631 Register boxReg = as_Register($box$$reg);
3632 Register tmpReg = as_Register($tmp$$reg);
3633 MacroAssembler masm(&cbuf);
3635 if (EmitSync & 4) {
3636 masm.cmpptr(rsp, 0) ;
3637 } else
3638 if (EmitSync & 8) {
3639 Label DONE_LABEL;
3640 if (UseBiasedLocking) {
3641 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3642 }
3644 // Check whether the displaced header is 0
3645 //(=> recursive unlock)
3646 masm.movptr(tmpReg, Address(boxReg, 0));
3647 masm.testptr(tmpReg, tmpReg);
3648 masm.jcc(Assembler::zero, DONE_LABEL);
3650 // If not recursive lock, reset the header to displaced header
3651 if (os::is_MP()) {
3652 masm.lock();
3653 }
3654 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3655 masm.bind(DONE_LABEL);
3656 masm.nop(); // avoid branch to branch
3657 } else {
3658 Label DONE_LABEL, Stacked, CheckSucc ;
3660 if (UseBiasedLocking) {
3661 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3662 }
3664 masm.movptr(tmpReg, Address(objReg, 0)) ;
3665 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
3666 masm.jcc (Assembler::zero, DONE_LABEL) ;
3667 masm.testl (tmpReg, 0x02) ;
3668 masm.jcc (Assembler::zero, Stacked) ;
3670 // It's inflated
3671 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3672 masm.xorptr(boxReg, r15_thread) ;
3673 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3674 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3675 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3676 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3677 masm.jcc (Assembler::notZero, CheckSucc) ;
3678 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3679 masm.jmp (DONE_LABEL) ;
3681 if ((EmitSync & 65536) == 0) {
3682 Label LSuccess, LGoSlowPath ;
3683 masm.bind (CheckSucc) ;
3684 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3685 masm.jcc (Assembler::zero, LGoSlowPath) ;
3687 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
3688 // the explicit ST;MEMBAR combination, but masm doesn't currently support
3689 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
3690 // are all faster when the write buffer is populated.
3691 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3692 if (os::is_MP()) {
3693 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
3694 }
3695 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3696 masm.jcc (Assembler::notZero, LSuccess) ;
3698 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
3699 if (os::is_MP()) { masm.lock(); }
3700 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3701 masm.jcc (Assembler::notEqual, LSuccess) ;
3702 // Intentional fall-through into slow-path
3704 masm.bind (LGoSlowPath) ;
3705 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3706 masm.jmp (DONE_LABEL) ;
3708 masm.bind (LSuccess) ;
3709 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
3710 masm.jmp (DONE_LABEL) ;
3711 }
3713 masm.bind (Stacked) ;
3714 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
3715 if (os::is_MP()) { masm.lock(); }
3716 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3718 if (EmitSync & 65536) {
3719 masm.bind (CheckSucc) ;
3720 }
3721 masm.bind(DONE_LABEL);
3722 if (EmitSync & 32768) {
3723 masm.nop(); // avoid branch to branch
3724 }
3725 }
3726 %}
3728 enc_class enc_String_Compare()
3729 %{
3730 Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3731 POP_LABEL, DONE_LABEL, CONT_LABEL,
3732 WHILE_HEAD_LABEL;
3733 MacroAssembler masm(&cbuf);
3735 // Get the first character position in both strings
3736 // [8] char array, [12] offset, [16] count
3737 int value_offset = java_lang_String::value_offset_in_bytes();
3738 int offset_offset = java_lang_String::offset_offset_in_bytes();
3739 int count_offset = java_lang_String::count_offset_in_bytes();
3740 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3742 masm.load_heap_oop(rax, Address(rsi, value_offset));
3743 masm.movl(rcx, Address(rsi, offset_offset));
3744 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3745 masm.load_heap_oop(rbx, Address(rdi, value_offset));
3746 masm.movl(rcx, Address(rdi, offset_offset));
3747 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3749 // Compute the minimum of the string lengths(rsi) and the
3750 // difference of the string lengths (stack)
3752 masm.movl(rdi, Address(rdi, count_offset));
3753 masm.movl(rsi, Address(rsi, count_offset));
3754 masm.movl(rcx, rdi);
3755 masm.subl(rdi, rsi);
3756 masm.push(rdi);
3757 masm.cmov(Assembler::lessEqual, rsi, rcx);
3759 // Is the minimum length zero?
3760 masm.bind(RCX_GOOD_LABEL);
3761 masm.testl(rsi, rsi);
3762 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3764 // Load first characters
3765 masm.load_unsigned_word(rcx, Address(rbx, 0));
3766 masm.load_unsigned_word(rdi, Address(rax, 0));
3768 // Compare first characters
3769 masm.subl(rcx, rdi);
3770 masm.jcc(Assembler::notZero, POP_LABEL);
3771 masm.decrementl(rsi);
3772 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3774 {
3775 // Check after comparing first character to see if strings are equivalent
3776 Label LSkip2;
3777 // Check if the strings start at same location
3778 masm.cmpptr(rbx, rax);
3779 masm.jcc(Assembler::notEqual, LSkip2);
3781 // Check if the length difference is zero (from stack)
3782 masm.cmpl(Address(rsp, 0), 0x0);
3783 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3785 // Strings might not be equivalent
3786 masm.bind(LSkip2);
3787 }
3789 // Shift RAX and RBX to the end of the arrays, negate min
3790 masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
3791 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
3792 masm.negptr(rsi);
3794 // Compare the rest of the characters
3795 masm.bind(WHILE_HEAD_LABEL);
3796 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
3797 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
3798 masm.subl(rcx, rdi);
3799 masm.jcc(Assembler::notZero, POP_LABEL);
3800 masm.increment(rsi);
3801 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3803 // Strings are equal up to min length. Return the length difference.
3804 masm.bind(LENGTH_DIFF_LABEL);
3805 masm.pop(rcx);
3806 masm.jmp(DONE_LABEL);
3808 // Discard the stored length difference
3809 masm.bind(POP_LABEL);
3810 masm.addptr(rsp, 8);
3812 // That's it
3813 masm.bind(DONE_LABEL);
3814 %}
3816 enc_class enc_Array_Equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, rbx_RegI tmp2, rcx_RegI result) %{
3817 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
3818 MacroAssembler masm(&cbuf);
3820 Register ary1Reg = as_Register($ary1$$reg);
3821 Register ary2Reg = as_Register($ary2$$reg);
3822 Register tmp1Reg = as_Register($tmp1$$reg);
3823 Register tmp2Reg = as_Register($tmp2$$reg);
3824 Register resultReg = as_Register($result$$reg);
3826 int length_offset = arrayOopDesc::length_offset_in_bytes();
3827 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3829 // Check the input args
3830 masm.cmpq(ary1Reg, ary2Reg);
3831 masm.jcc(Assembler::equal, TRUE_LABEL);
3832 masm.testq(ary1Reg, ary1Reg);
3833 masm.jcc(Assembler::zero, FALSE_LABEL);
3834 masm.testq(ary2Reg, ary2Reg);
3835 masm.jcc(Assembler::zero, FALSE_LABEL);
3837 // Check the lengths
3838 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
3839 masm.movl(resultReg, Address(ary2Reg, length_offset));
3840 masm.cmpl(tmp2Reg, resultReg);
3841 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3842 masm.testl(resultReg, resultReg);
3843 masm.jcc(Assembler::zero, TRUE_LABEL);
3845 // Get the number of 4 byte vectors to compare
3846 masm.shrl(resultReg, 1);
3848 // Check for odd-length arrays
3849 masm.andl(tmp2Reg, 1);
3850 masm.testl(tmp2Reg, tmp2Reg);
3851 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR);
3853 // Compare 2-byte "tail" at end of arrays
3854 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3855 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3856 masm.cmpl(tmp1Reg, tmp2Reg);
3857 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3858 masm.testl(resultReg, resultReg);
3859 masm.jcc(Assembler::zero, TRUE_LABEL);
3861 // Setup compare loop
3862 masm.bind(COMPARE_LOOP_HDR);
3863 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
3864 masm.leaq(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3865 masm.leaq(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3866 masm.negq(resultReg);
3868 // 4-byte-wide compare loop
3869 masm.bind(COMPARE_LOOP);
3870 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
3871 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
3872 masm.cmpl(ary1Reg, ary2Reg);
3873 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3874 masm.incrementq(resultReg);
3875 masm.jcc(Assembler::notZero, COMPARE_LOOP);
3877 masm.bind(TRUE_LABEL);
3878 masm.movl(resultReg, 1); // return true
3879 masm.jmp(DONE_LABEL);
3881 masm.bind(FALSE_LABEL);
3882 masm.xorl(resultReg, resultReg); // return false
3884 // That's it
3885 masm.bind(DONE_LABEL);
3886 %}
3888 enc_class enc_rethrow()
3889 %{
3890 cbuf.set_inst_mark();
3891 emit_opcode(cbuf, 0xE9); // jmp entry
3892 emit_d32_reloc(cbuf,
3893 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4),
3894 runtime_call_Relocation::spec(),
3895 RELOC_DISP32);
3896 %}
3898 enc_class absF_encoding(regF dst)
3899 %{
3900 int dstenc = $dst$$reg;
3901 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
3903 cbuf.set_inst_mark();
3904 if (dstenc >= 8) {
3905 emit_opcode(cbuf, Assembler::REX_R);
3906 dstenc -= 8;
3907 }
3908 // XXX reg_mem doesn't support RIP-relative addressing yet
3909 emit_opcode(cbuf, 0x0F);
3910 emit_opcode(cbuf, 0x54);
3911 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3912 emit_d32_reloc(cbuf, signmask_address);
3913 %}
3915 enc_class absD_encoding(regD dst)
3916 %{
3917 int dstenc = $dst$$reg;
3918 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
3920 cbuf.set_inst_mark();
3921 emit_opcode(cbuf, 0x66);
3922 if (dstenc >= 8) {
3923 emit_opcode(cbuf, Assembler::REX_R);
3924 dstenc -= 8;
3925 }
3926 // XXX reg_mem doesn't support RIP-relative addressing yet
3927 emit_opcode(cbuf, 0x0F);
3928 emit_opcode(cbuf, 0x54);
3929 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3930 emit_d32_reloc(cbuf, signmask_address);
3931 %}
3933 enc_class negF_encoding(regF dst)
3934 %{
3935 int dstenc = $dst$$reg;
3936 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
3938 cbuf.set_inst_mark();
3939 if (dstenc >= 8) {
3940 emit_opcode(cbuf, Assembler::REX_R);
3941 dstenc -= 8;
3942 }
3943 // XXX reg_mem doesn't support RIP-relative addressing yet
3944 emit_opcode(cbuf, 0x0F);
3945 emit_opcode(cbuf, 0x57);
3946 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3947 emit_d32_reloc(cbuf, signflip_address);
3948 %}
3950 enc_class negD_encoding(regD dst)
3951 %{
3952 int dstenc = $dst$$reg;
3953 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
3955 cbuf.set_inst_mark();
3956 emit_opcode(cbuf, 0x66);
3957 if (dstenc >= 8) {
3958 emit_opcode(cbuf, Assembler::REX_R);
3959 dstenc -= 8;
3960 }
3961 // XXX reg_mem doesn't support RIP-relative addressing yet
3962 emit_opcode(cbuf, 0x0F);
3963 emit_opcode(cbuf, 0x57);
3964 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3965 emit_d32_reloc(cbuf, signflip_address);
3966 %}
3968 enc_class f2i_fixup(rRegI dst, regF src)
3969 %{
3970 int dstenc = $dst$$reg;
3971 int srcenc = $src$$reg;
3973 // cmpl $dst, #0x80000000
3974 if (dstenc >= 8) {
3975 emit_opcode(cbuf, Assembler::REX_B);
3976 }
3977 emit_opcode(cbuf, 0x81);
3978 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
3979 emit_d32(cbuf, 0x80000000);
3981 // jne,s done
3982 emit_opcode(cbuf, 0x75);
3983 if (srcenc < 8 && dstenc < 8) {
3984 emit_d8(cbuf, 0xF);
3985 } else if (srcenc >= 8 && dstenc >= 8) {
3986 emit_d8(cbuf, 0x11);
3987 } else {
3988 emit_d8(cbuf, 0x10);
3989 }
3991 // subq rsp, #8
3992 emit_opcode(cbuf, Assembler::REX_W);
3993 emit_opcode(cbuf, 0x83);
3994 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3995 emit_d8(cbuf, 8);
3997 // movss [rsp], $src
3998 emit_opcode(cbuf, 0xF3);
3999 if (srcenc >= 8) {
4000 emit_opcode(cbuf, Assembler::REX_R);
4001 }
4002 emit_opcode(cbuf, 0x0F);
4003 emit_opcode(cbuf, 0x11);
4004 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4006 // call f2i_fixup
4007 cbuf.set_inst_mark();
4008 emit_opcode(cbuf, 0xE8);
4009 emit_d32_reloc(cbuf,
4010 (int)
4011 (StubRoutines::x86::f2i_fixup() - cbuf.code_end() - 4),
4012 runtime_call_Relocation::spec(),
4013 RELOC_DISP32);
4015 // popq $dst
4016 if (dstenc >= 8) {
4017 emit_opcode(cbuf, Assembler::REX_B);
4018 }
4019 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4021 // done:
4022 %}
4024 enc_class f2l_fixup(rRegL dst, regF src)
4025 %{
4026 int dstenc = $dst$$reg;
4027 int srcenc = $src$$reg;
4028 address const_address = (address) StubRoutines::x86::double_sign_flip();
4030 // cmpq $dst, [0x8000000000000000]
4031 cbuf.set_inst_mark();
4032 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
4033 emit_opcode(cbuf, 0x39);
4034 // XXX reg_mem doesn't support RIP-relative addressing yet
4035 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
4036 emit_d32_reloc(cbuf, const_address);
4039 // jne,s done
4040 emit_opcode(cbuf, 0x75);
4041 if (srcenc < 8 && dstenc < 8) {
4042 emit_d8(cbuf, 0xF);
4043 } else if (srcenc >= 8 && dstenc >= 8) {
4044 emit_d8(cbuf, 0x11);
4045 } else {
4046 emit_d8(cbuf, 0x10);
4047 }
4049 // subq rsp, #8
4050 emit_opcode(cbuf, Assembler::REX_W);
4051 emit_opcode(cbuf, 0x83);
4052 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4053 emit_d8(cbuf, 8);
4055 // movss [rsp], $src
4056 emit_opcode(cbuf, 0xF3);
4057 if (srcenc >= 8) {
4058 emit_opcode(cbuf, Assembler::REX_R);
4059 }
4060 emit_opcode(cbuf, 0x0F);
4061 emit_opcode(cbuf, 0x11);
4062 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4064 // call f2l_fixup
4065 cbuf.set_inst_mark();
4066 emit_opcode(cbuf, 0xE8);
4067 emit_d32_reloc(cbuf,
4068 (int)
4069 (StubRoutines::x86::f2l_fixup() - cbuf.code_end() - 4),
4070 runtime_call_Relocation::spec(),
4071 RELOC_DISP32);
4073 // popq $dst
4074 if (dstenc >= 8) {
4075 emit_opcode(cbuf, Assembler::REX_B);
4076 }
4077 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4079 // done:
4080 %}
4082 enc_class d2i_fixup(rRegI dst, regD src)
4083 %{
4084 int dstenc = $dst$$reg;
4085 int srcenc = $src$$reg;
4087 // cmpl $dst, #0x80000000
4088 if (dstenc >= 8) {
4089 emit_opcode(cbuf, Assembler::REX_B);
4090 }
4091 emit_opcode(cbuf, 0x81);
4092 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
4093 emit_d32(cbuf, 0x80000000);
4095 // jne,s done
4096 emit_opcode(cbuf, 0x75);
4097 if (srcenc < 8 && dstenc < 8) {
4098 emit_d8(cbuf, 0xF);
4099 } else if (srcenc >= 8 && dstenc >= 8) {
4100 emit_d8(cbuf, 0x11);
4101 } else {
4102 emit_d8(cbuf, 0x10);
4103 }
4105 // subq rsp, #8
4106 emit_opcode(cbuf, Assembler::REX_W);
4107 emit_opcode(cbuf, 0x83);
4108 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4109 emit_d8(cbuf, 8);
4111 // movsd [rsp], $src
4112 emit_opcode(cbuf, 0xF2);
4113 if (srcenc >= 8) {
4114 emit_opcode(cbuf, Assembler::REX_R);
4115 }
4116 emit_opcode(cbuf, 0x0F);
4117 emit_opcode(cbuf, 0x11);
4118 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4120 // call d2i_fixup
4121 cbuf.set_inst_mark();
4122 emit_opcode(cbuf, 0xE8);
4123 emit_d32_reloc(cbuf,
4124 (int)
4125 (StubRoutines::x86::d2i_fixup() - cbuf.code_end() - 4),
4126 runtime_call_Relocation::spec(),
4127 RELOC_DISP32);
4129 // popq $dst
4130 if (dstenc >= 8) {
4131 emit_opcode(cbuf, Assembler::REX_B);
4132 }
4133 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4135 // done:
4136 %}
4138 enc_class d2l_fixup(rRegL dst, regD src)
4139 %{
4140 int dstenc = $dst$$reg;
4141 int srcenc = $src$$reg;
4142 address const_address = (address) StubRoutines::x86::double_sign_flip();
4144 // cmpq $dst, [0x8000000000000000]
4145 cbuf.set_inst_mark();
4146 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
4147 emit_opcode(cbuf, 0x39);
4148 // XXX reg_mem doesn't support RIP-relative addressing yet
4149 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
4150 emit_d32_reloc(cbuf, const_address);
4153 // jne,s done
4154 emit_opcode(cbuf, 0x75);
4155 if (srcenc < 8 && dstenc < 8) {
4156 emit_d8(cbuf, 0xF);
4157 } else if (srcenc >= 8 && dstenc >= 8) {
4158 emit_d8(cbuf, 0x11);
4159 } else {
4160 emit_d8(cbuf, 0x10);
4161 }
4163 // subq rsp, #8
4164 emit_opcode(cbuf, Assembler::REX_W);
4165 emit_opcode(cbuf, 0x83);
4166 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4167 emit_d8(cbuf, 8);
4169 // movsd [rsp], $src
4170 emit_opcode(cbuf, 0xF2);
4171 if (srcenc >= 8) {
4172 emit_opcode(cbuf, Assembler::REX_R);
4173 }
4174 emit_opcode(cbuf, 0x0F);
4175 emit_opcode(cbuf, 0x11);
4176 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4178 // call d2l_fixup
4179 cbuf.set_inst_mark();
4180 emit_opcode(cbuf, 0xE8);
4181 emit_d32_reloc(cbuf,
4182 (int)
4183 (StubRoutines::x86::d2l_fixup() - cbuf.code_end() - 4),
4184 runtime_call_Relocation::spec(),
4185 RELOC_DISP32);
4187 // popq $dst
4188 if (dstenc >= 8) {
4189 emit_opcode(cbuf, Assembler::REX_B);
4190 }
4191 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4193 // done:
4194 %}
4196 enc_class enc_membar_acquire
4197 %{
4198 // [jk] not needed currently, if you enable this and it really
4199 // emits code don't forget to the remove the "size(0)" line in
4200 // membar_acquire()
4201 // MacroAssembler masm(&cbuf);
4202 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore |
4203 // Assembler::LoadLoad));
4204 %}
4206 enc_class enc_membar_release
4207 %{
4208 // [jk] not needed currently, if you enable this and it really
4209 // emits code don't forget to the remove the "size(0)" line in
4210 // membar_release()
4211 // MacroAssembler masm(&cbuf);
4212 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore |
4213 // Assembler::StoreStore));
4214 %}
4216 enc_class enc_membar_volatile
4217 %{
4218 MacroAssembler masm(&cbuf);
4219 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
4220 Assembler::StoreStore));
4221 %}
4223 // Safepoint Poll. This polls the safepoint page, and causes an
4224 // exception if it is not readable. Unfortunately, it kills
4225 // RFLAGS in the process.
4226 enc_class enc_safepoint_poll
4227 %{
4228 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
4229 // XXX reg_mem doesn't support RIP-relative addressing yet
4230 cbuf.set_inst_mark();
4231 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); // XXX
4232 emit_opcode(cbuf, 0x85); // testl
4233 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
4234 // cbuf.inst_mark() is beginning of instruction
4235 emit_d32_reloc(cbuf, os::get_polling_page());
4236 // relocInfo::poll_type,
4237 %}
4238 %}
4242 //----------FRAME--------------------------------------------------------------
4243 // Definition of frame structure and management information.
4244 //
4245 // S T A C K L A Y O U T Allocators stack-slot number
4246 // | (to get allocators register number
4247 // G Owned by | | v add OptoReg::stack0())
4248 // r CALLER | |
4249 // o | +--------+ pad to even-align allocators stack-slot
4250 // w V | pad0 | numbers; owned by CALLER
4251 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4252 // h ^ | in | 5
4253 // | | args | 4 Holes in incoming args owned by SELF
4254 // | | | | 3
4255 // | | +--------+
4256 // V | | old out| Empty on Intel, window on Sparc
4257 // | old |preserve| Must be even aligned.
4258 // | SP-+--------+----> Matcher::_old_SP, even aligned
4259 // | | in | 3 area for Intel ret address
4260 // Owned by |preserve| Empty on Sparc.
4261 // SELF +--------+
4262 // | | pad2 | 2 pad to align old SP
4263 // | +--------+ 1
4264 // | | locks | 0
4265 // | +--------+----> OptoReg::stack0(), even aligned
4266 // | | pad1 | 11 pad to align new SP
4267 // | +--------+
4268 // | | | 10
4269 // | | spills | 9 spills
4270 // V | | 8 (pad0 slot for callee)
4271 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4272 // ^ | out | 7
4273 // | | args | 6 Holes in outgoing args owned by CALLEE
4274 // Owned by +--------+
4275 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4276 // | new |preserve| Must be even-aligned.
4277 // | SP-+--------+----> Matcher::_new_SP, even aligned
4278 // | | |
4279 //
4280 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4281 // known from SELF's arguments and the Java calling convention.
4282 // Region 6-7 is determined per call site.
4283 // Note 2: If the calling convention leaves holes in the incoming argument
4284 // area, those holes are owned by SELF. Holes in the outgoing area
4285 // are owned by the CALLEE. Holes should not be nessecary in the
4286 // incoming area, as the Java calling convention is completely under
4287 // the control of the AD file. Doubles can be sorted and packed to
4288 // avoid holes. Holes in the outgoing arguments may be nessecary for
4289 // varargs C calling conventions.
4290 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4291 // even aligned with pad0 as needed.
4292 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4293 // region 6-11 is even aligned; it may be padded out more so that
4294 // the region from SP to FP meets the minimum stack alignment.
4295 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
4296 // alignment. Region 11, pad1, may be dynamically extended so that
4297 // SP meets the minimum alignment.
4299 frame
4300 %{
4301 // What direction does stack grow in (assumed to be same for C & Java)
4302 stack_direction(TOWARDS_LOW);
4304 // These three registers define part of the calling convention
4305 // between compiled code and the interpreter.
4306 inline_cache_reg(RAX); // Inline Cache Register
4307 interpreter_method_oop_reg(RBX); // Method Oop Register when
4308 // calling interpreter
4310 // Optional: name the operand used by cisc-spilling to access
4311 // [stack_pointer + offset]
4312 cisc_spilling_operand_name(indOffset32);
4314 // Number of stack slots consumed by locking an object
4315 sync_stack_slots(2);
4317 // Compiled code's Frame Pointer
4318 frame_pointer(RSP);
4320 // Interpreter stores its frame pointer in a register which is
4321 // stored to the stack by I2CAdaptors.
4322 // I2CAdaptors convert from interpreted java to compiled java.
4323 interpreter_frame_pointer(RBP);
4325 // Stack alignment requirement
4326 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
4328 // Number of stack slots between incoming argument block and the start of
4329 // a new frame. The PROLOG must add this many slots to the stack. The
4330 // EPILOG must remove this many slots. amd64 needs two slots for
4331 // return address.
4332 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
4334 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4335 // for calls to C. Supports the var-args backing area for register parms.
4336 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
4338 // The after-PROLOG location of the return address. Location of
4339 // return address specifies a type (REG or STACK) and a number
4340 // representing the register number (i.e. - use a register name) or
4341 // stack slot.
4342 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4343 // Otherwise, it is above the locks and verification slot and alignment word
4344 return_addr(STACK - 2 +
4345 round_to(2 + 2 * VerifyStackAtCalls +
4346 Compile::current()->fixed_slots(),
4347 WordsPerLong * 2));
4349 // Body of function which returns an integer array locating
4350 // arguments either in registers or in stack slots. Passed an array
4351 // of ideal registers called "sig" and a "length" count. Stack-slot
4352 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4353 // arguments for a CALLEE. Incoming stack arguments are
4354 // automatically biased by the preserve_stack_slots field above.
4356 calling_convention
4357 %{
4358 // No difference between ingoing/outgoing just pass false
4359 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4360 %}
4362 c_calling_convention
4363 %{
4364 // This is obviously always outgoing
4365 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4366 %}
4368 // Location of compiled Java return values. Same as C for now.
4369 return_value
4370 %{
4371 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
4372 "only return normal values");
4374 static const int lo[Op_RegL + 1] = {
4375 0,
4376 0,
4377 RAX_num, // Op_RegN
4378 RAX_num, // Op_RegI
4379 RAX_num, // Op_RegP
4380 XMM0_num, // Op_RegF
4381 XMM0_num, // Op_RegD
4382 RAX_num // Op_RegL
4383 };
4384 static const int hi[Op_RegL + 1] = {
4385 0,
4386 0,
4387 OptoReg::Bad, // Op_RegN
4388 OptoReg::Bad, // Op_RegI
4389 RAX_H_num, // Op_RegP
4390 OptoReg::Bad, // Op_RegF
4391 XMM0_H_num, // Op_RegD
4392 RAX_H_num // Op_RegL
4393 };
4394 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
4395 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
4396 %}
4397 %}
4399 //----------ATTRIBUTES---------------------------------------------------------
4400 //----------Operand Attributes-------------------------------------------------
4401 op_attrib op_cost(0); // Required cost attribute
4403 //----------Instruction Attributes---------------------------------------------
4404 ins_attrib ins_cost(100); // Required cost attribute
4405 ins_attrib ins_size(8); // Required size attribute (in bits)
4406 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4407 ins_attrib ins_short_branch(0); // Required flag: is this instruction
4408 // a non-matching short branch variant
4409 // of some long branch?
4410 ins_attrib ins_alignment(1); // Required alignment attribute (must
4411 // be a power of 2) specifies the
4412 // alignment that some part of the
4413 // instruction (not necessarily the
4414 // start) requires. If > 1, a
4415 // compute_padding() function must be
4416 // provided for the instruction
4418 //----------OPERANDS-----------------------------------------------------------
4419 // Operand definitions must precede instruction definitions for correct parsing
4420 // in the ADLC because operands constitute user defined types which are used in
4421 // instruction definitions.
4423 //----------Simple Operands----------------------------------------------------
4424 // Immediate Operands
4425 // Integer Immediate
4426 operand immI()
4427 %{
4428 match(ConI);
4430 op_cost(10);
4431 format %{ %}
4432 interface(CONST_INTER);
4433 %}
4435 // Constant for test vs zero
4436 operand immI0()
4437 %{
4438 predicate(n->get_int() == 0);
4439 match(ConI);
4441 op_cost(0);
4442 format %{ %}
4443 interface(CONST_INTER);
4444 %}
4446 // Constant for increment
4447 operand immI1()
4448 %{
4449 predicate(n->get_int() == 1);
4450 match(ConI);
4452 op_cost(0);
4453 format %{ %}
4454 interface(CONST_INTER);
4455 %}
4457 // Constant for decrement
4458 operand immI_M1()
4459 %{
4460 predicate(n->get_int() == -1);
4461 match(ConI);
4463 op_cost(0);
4464 format %{ %}
4465 interface(CONST_INTER);
4466 %}
4468 // Valid scale values for addressing modes
4469 operand immI2()
4470 %{
4471 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4472 match(ConI);
4474 format %{ %}
4475 interface(CONST_INTER);
4476 %}
4478 operand immI8()
4479 %{
4480 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
4481 match(ConI);
4483 op_cost(5);
4484 format %{ %}
4485 interface(CONST_INTER);
4486 %}
4488 operand immI16()
4489 %{
4490 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4491 match(ConI);
4493 op_cost(10);
4494 format %{ %}
4495 interface(CONST_INTER);
4496 %}
4498 // Constant for long shifts
4499 operand immI_32()
4500 %{
4501 predicate( n->get_int() == 32 );
4502 match(ConI);
4504 op_cost(0);
4505 format %{ %}
4506 interface(CONST_INTER);
4507 %}
4509 // Constant for long shifts
4510 operand immI_64()
4511 %{
4512 predicate( n->get_int() == 64 );
4513 match(ConI);
4515 op_cost(0);
4516 format %{ %}
4517 interface(CONST_INTER);
4518 %}
4520 // Pointer Immediate
4521 operand immP()
4522 %{
4523 match(ConP);
4525 op_cost(10);
4526 format %{ %}
4527 interface(CONST_INTER);
4528 %}
4530 // NULL Pointer Immediate
4531 operand immP0()
4532 %{
4533 predicate(n->get_ptr() == 0);
4534 match(ConP);
4536 op_cost(5);
4537 format %{ %}
4538 interface(CONST_INTER);
4539 %}
4541 // Pointer Immediate
4542 operand immN() %{
4543 match(ConN);
4545 op_cost(10);
4546 format %{ %}
4547 interface(CONST_INTER);
4548 %}
4550 // NULL Pointer Immediate
4551 operand immN0() %{
4552 predicate(n->get_narrowcon() == 0);
4553 match(ConN);
4555 op_cost(5);
4556 format %{ %}
4557 interface(CONST_INTER);
4558 %}
4560 operand immP31()
4561 %{
4562 predicate(!n->as_Type()->type()->isa_oopptr()
4563 && (n->get_ptr() >> 31) == 0);
4564 match(ConP);
4566 op_cost(5);
4567 format %{ %}
4568 interface(CONST_INTER);
4569 %}
4572 // Long Immediate
4573 operand immL()
4574 %{
4575 match(ConL);
4577 op_cost(20);
4578 format %{ %}
4579 interface(CONST_INTER);
4580 %}
4582 // Long Immediate 8-bit
4583 operand immL8()
4584 %{
4585 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
4586 match(ConL);
4588 op_cost(5);
4589 format %{ %}
4590 interface(CONST_INTER);
4591 %}
4593 // Long Immediate 32-bit unsigned
4594 operand immUL32()
4595 %{
4596 predicate(n->get_long() == (unsigned int) (n->get_long()));
4597 match(ConL);
4599 op_cost(10);
4600 format %{ %}
4601 interface(CONST_INTER);
4602 %}
4604 // Long Immediate 32-bit signed
4605 operand immL32()
4606 %{
4607 predicate(n->get_long() == (int) (n->get_long()));
4608 match(ConL);
4610 op_cost(15);
4611 format %{ %}
4612 interface(CONST_INTER);
4613 %}
4615 // Long Immediate zero
4616 operand immL0()
4617 %{
4618 predicate(n->get_long() == 0L);
4619 match(ConL);
4621 op_cost(10);
4622 format %{ %}
4623 interface(CONST_INTER);
4624 %}
4626 // Constant for increment
4627 operand immL1()
4628 %{
4629 predicate(n->get_long() == 1);
4630 match(ConL);
4632 format %{ %}
4633 interface(CONST_INTER);
4634 %}
4636 // Constant for decrement
4637 operand immL_M1()
4638 %{
4639 predicate(n->get_long() == -1);
4640 match(ConL);
4642 format %{ %}
4643 interface(CONST_INTER);
4644 %}
4646 // Long Immediate: the value 10
4647 operand immL10()
4648 %{
4649 predicate(n->get_long() == 10);
4650 match(ConL);
4652 format %{ %}
4653 interface(CONST_INTER);
4654 %}
4656 // Long immediate from 0 to 127.
4657 // Used for a shorter form of long mul by 10.
4658 operand immL_127()
4659 %{
4660 predicate(0 <= n->get_long() && n->get_long() < 0x80);
4661 match(ConL);
4663 op_cost(10);
4664 format %{ %}
4665 interface(CONST_INTER);
4666 %}
4668 // Long Immediate: low 32-bit mask
4669 operand immL_32bits()
4670 %{
4671 predicate(n->get_long() == 0xFFFFFFFFL);
4672 match(ConL);
4673 op_cost(20);
4675 format %{ %}
4676 interface(CONST_INTER);
4677 %}
4679 // Float Immediate zero
4680 operand immF0()
4681 %{
4682 predicate(jint_cast(n->getf()) == 0);
4683 match(ConF);
4685 op_cost(5);
4686 format %{ %}
4687 interface(CONST_INTER);
4688 %}
4690 // Float Immediate
4691 operand immF()
4692 %{
4693 match(ConF);
4695 op_cost(15);
4696 format %{ %}
4697 interface(CONST_INTER);
4698 %}
4700 // Double Immediate zero
4701 operand immD0()
4702 %{
4703 predicate(jlong_cast(n->getd()) == 0);
4704 match(ConD);
4706 op_cost(5);
4707 format %{ %}
4708 interface(CONST_INTER);
4709 %}
4711 // Double Immediate
4712 operand immD()
4713 %{
4714 match(ConD);
4716 op_cost(15);
4717 format %{ %}
4718 interface(CONST_INTER);
4719 %}
4721 // Immediates for special shifts (sign extend)
4723 // Constants for increment
4724 operand immI_16()
4725 %{
4726 predicate(n->get_int() == 16);
4727 match(ConI);
4729 format %{ %}
4730 interface(CONST_INTER);
4731 %}
4733 operand immI_24()
4734 %{
4735 predicate(n->get_int() == 24);
4736 match(ConI);
4738 format %{ %}
4739 interface(CONST_INTER);
4740 %}
4742 // Constant for byte-wide masking
4743 operand immI_255()
4744 %{
4745 predicate(n->get_int() == 255);
4746 match(ConI);
4748 format %{ %}
4749 interface(CONST_INTER);
4750 %}
4752 // Constant for short-wide masking
4753 operand immI_65535()
4754 %{
4755 predicate(n->get_int() == 65535);
4756 match(ConI);
4758 format %{ %}
4759 interface(CONST_INTER);
4760 %}
4762 // Constant for byte-wide masking
4763 operand immL_255()
4764 %{
4765 predicate(n->get_long() == 255);
4766 match(ConL);
4768 format %{ %}
4769 interface(CONST_INTER);
4770 %}
4772 // Constant for short-wide masking
4773 operand immL_65535()
4774 %{
4775 predicate(n->get_long() == 65535);
4776 match(ConL);
4778 format %{ %}
4779 interface(CONST_INTER);
4780 %}
4782 // Register Operands
4783 // Integer Register
4784 operand rRegI()
4785 %{
4786 constraint(ALLOC_IN_RC(int_reg));
4787 match(RegI);
4789 match(rax_RegI);
4790 match(rbx_RegI);
4791 match(rcx_RegI);
4792 match(rdx_RegI);
4793 match(rdi_RegI);
4795 format %{ %}
4796 interface(REG_INTER);
4797 %}
4799 // Special Registers
4800 operand rax_RegI()
4801 %{
4802 constraint(ALLOC_IN_RC(int_rax_reg));
4803 match(RegI);
4804 match(rRegI);
4806 format %{ "RAX" %}
4807 interface(REG_INTER);
4808 %}
4810 // Special Registers
4811 operand rbx_RegI()
4812 %{
4813 constraint(ALLOC_IN_RC(int_rbx_reg));
4814 match(RegI);
4815 match(rRegI);
4817 format %{ "RBX" %}
4818 interface(REG_INTER);
4819 %}
4821 operand rcx_RegI()
4822 %{
4823 constraint(ALLOC_IN_RC(int_rcx_reg));
4824 match(RegI);
4825 match(rRegI);
4827 format %{ "RCX" %}
4828 interface(REG_INTER);
4829 %}
4831 operand rdx_RegI()
4832 %{
4833 constraint(ALLOC_IN_RC(int_rdx_reg));
4834 match(RegI);
4835 match(rRegI);
4837 format %{ "RDX" %}
4838 interface(REG_INTER);
4839 %}
4841 operand rdi_RegI()
4842 %{
4843 constraint(ALLOC_IN_RC(int_rdi_reg));
4844 match(RegI);
4845 match(rRegI);
4847 format %{ "RDI" %}
4848 interface(REG_INTER);
4849 %}
4851 operand no_rcx_RegI()
4852 %{
4853 constraint(ALLOC_IN_RC(int_no_rcx_reg));
4854 match(RegI);
4855 match(rax_RegI);
4856 match(rbx_RegI);
4857 match(rdx_RegI);
4858 match(rdi_RegI);
4860 format %{ %}
4861 interface(REG_INTER);
4862 %}
4864 operand no_rax_rdx_RegI()
4865 %{
4866 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
4867 match(RegI);
4868 match(rbx_RegI);
4869 match(rcx_RegI);
4870 match(rdi_RegI);
4872 format %{ %}
4873 interface(REG_INTER);
4874 %}
4876 // Pointer Register
4877 operand any_RegP()
4878 %{
4879 constraint(ALLOC_IN_RC(any_reg));
4880 match(RegP);
4881 match(rax_RegP);
4882 match(rbx_RegP);
4883 match(rdi_RegP);
4884 match(rsi_RegP);
4885 match(rbp_RegP);
4886 match(r15_RegP);
4887 match(rRegP);
4889 format %{ %}
4890 interface(REG_INTER);
4891 %}
4893 operand rRegP()
4894 %{
4895 constraint(ALLOC_IN_RC(ptr_reg));
4896 match(RegP);
4897 match(rax_RegP);
4898 match(rbx_RegP);
4899 match(rdi_RegP);
4900 match(rsi_RegP);
4901 match(rbp_RegP);
4902 match(r15_RegP); // See Q&A below about r15_RegP.
4904 format %{ %}
4905 interface(REG_INTER);
4906 %}
4909 operand r12RegL() %{
4910 constraint(ALLOC_IN_RC(long_r12_reg));
4911 match(RegL);
4913 format %{ %}
4914 interface(REG_INTER);
4915 %}
4917 operand rRegN() %{
4918 constraint(ALLOC_IN_RC(int_reg));
4919 match(RegN);
4921 format %{ %}
4922 interface(REG_INTER);
4923 %}
4925 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
4926 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
4927 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
4928 // The output of an instruction is controlled by the allocator, which respects
4929 // register class masks, not match rules. Unless an instruction mentions
4930 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
4931 // by the allocator as an input.
4933 operand no_rax_RegP()
4934 %{
4935 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
4936 match(RegP);
4937 match(rbx_RegP);
4938 match(rsi_RegP);
4939 match(rdi_RegP);
4941 format %{ %}
4942 interface(REG_INTER);
4943 %}
4945 operand no_rbp_RegP()
4946 %{
4947 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
4948 match(RegP);
4949 match(rbx_RegP);
4950 match(rsi_RegP);
4951 match(rdi_RegP);
4953 format %{ %}
4954 interface(REG_INTER);
4955 %}
4957 operand no_rax_rbx_RegP()
4958 %{
4959 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
4960 match(RegP);
4961 match(rsi_RegP);
4962 match(rdi_RegP);
4964 format %{ %}
4965 interface(REG_INTER);
4966 %}
4968 // Special Registers
4969 // Return a pointer value
4970 operand rax_RegP()
4971 %{
4972 constraint(ALLOC_IN_RC(ptr_rax_reg));
4973 match(RegP);
4974 match(rRegP);
4976 format %{ %}
4977 interface(REG_INTER);
4978 %}
4980 // Special Registers
4981 // Return a compressed pointer value
4982 operand rax_RegN()
4983 %{
4984 constraint(ALLOC_IN_RC(int_rax_reg));
4985 match(RegN);
4986 match(rRegN);
4988 format %{ %}
4989 interface(REG_INTER);
4990 %}
4992 // Used in AtomicAdd
4993 operand rbx_RegP()
4994 %{
4995 constraint(ALLOC_IN_RC(ptr_rbx_reg));
4996 match(RegP);
4997 match(rRegP);
4999 format %{ %}
5000 interface(REG_INTER);
5001 %}
5003 operand rsi_RegP()
5004 %{
5005 constraint(ALLOC_IN_RC(ptr_rsi_reg));
5006 match(RegP);
5007 match(rRegP);
5009 format %{ %}
5010 interface(REG_INTER);
5011 %}
5013 // Used in rep stosq
5014 operand rdi_RegP()
5015 %{
5016 constraint(ALLOC_IN_RC(ptr_rdi_reg));
5017 match(RegP);
5018 match(rRegP);
5020 format %{ %}
5021 interface(REG_INTER);
5022 %}
5024 operand rbp_RegP()
5025 %{
5026 constraint(ALLOC_IN_RC(ptr_rbp_reg));
5027 match(RegP);
5028 match(rRegP);
5030 format %{ %}
5031 interface(REG_INTER);
5032 %}
5034 operand r15_RegP()
5035 %{
5036 constraint(ALLOC_IN_RC(ptr_r15_reg));
5037 match(RegP);
5038 match(rRegP);
5040 format %{ %}
5041 interface(REG_INTER);
5042 %}
5044 operand rRegL()
5045 %{
5046 constraint(ALLOC_IN_RC(long_reg));
5047 match(RegL);
5048 match(rax_RegL);
5049 match(rdx_RegL);
5051 format %{ %}
5052 interface(REG_INTER);
5053 %}
5055 // Special Registers
5056 operand no_rax_rdx_RegL()
5057 %{
5058 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
5059 match(RegL);
5060 match(rRegL);
5062 format %{ %}
5063 interface(REG_INTER);
5064 %}
5066 operand no_rax_RegL()
5067 %{
5068 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
5069 match(RegL);
5070 match(rRegL);
5071 match(rdx_RegL);
5073 format %{ %}
5074 interface(REG_INTER);
5075 %}
5077 operand no_rcx_RegL()
5078 %{
5079 constraint(ALLOC_IN_RC(long_no_rcx_reg));
5080 match(RegL);
5081 match(rRegL);
5083 format %{ %}
5084 interface(REG_INTER);
5085 %}
5087 operand rax_RegL()
5088 %{
5089 constraint(ALLOC_IN_RC(long_rax_reg));
5090 match(RegL);
5091 match(rRegL);
5093 format %{ "RAX" %}
5094 interface(REG_INTER);
5095 %}
5097 operand rcx_RegL()
5098 %{
5099 constraint(ALLOC_IN_RC(long_rcx_reg));
5100 match(RegL);
5101 match(rRegL);
5103 format %{ %}
5104 interface(REG_INTER);
5105 %}
5107 operand rdx_RegL()
5108 %{
5109 constraint(ALLOC_IN_RC(long_rdx_reg));
5110 match(RegL);
5111 match(rRegL);
5113 format %{ %}
5114 interface(REG_INTER);
5115 %}
5117 // Flags register, used as output of compare instructions
5118 operand rFlagsReg()
5119 %{
5120 constraint(ALLOC_IN_RC(int_flags));
5121 match(RegFlags);
5123 format %{ "RFLAGS" %}
5124 interface(REG_INTER);
5125 %}
5127 // Flags register, used as output of FLOATING POINT compare instructions
5128 operand rFlagsRegU()
5129 %{
5130 constraint(ALLOC_IN_RC(int_flags));
5131 match(RegFlags);
5133 format %{ "RFLAGS_U" %}
5134 interface(REG_INTER);
5135 %}
5137 // Float register operands
5138 operand regF()
5139 %{
5140 constraint(ALLOC_IN_RC(float_reg));
5141 match(RegF);
5143 format %{ %}
5144 interface(REG_INTER);
5145 %}
5147 // Double register operands
5148 operand regD()
5149 %{
5150 constraint(ALLOC_IN_RC(double_reg));
5151 match(RegD);
5153 format %{ %}
5154 interface(REG_INTER);
5155 %}
5158 //----------Memory Operands----------------------------------------------------
5159 // Direct Memory Operand
5160 // operand direct(immP addr)
5161 // %{
5162 // match(addr);
5164 // format %{ "[$addr]" %}
5165 // interface(MEMORY_INTER) %{
5166 // base(0xFFFFFFFF);
5167 // index(0x4);
5168 // scale(0x0);
5169 // disp($addr);
5170 // %}
5171 // %}
5173 // Indirect Memory Operand
5174 operand indirect(any_RegP reg)
5175 %{
5176 constraint(ALLOC_IN_RC(ptr_reg));
5177 match(reg);
5179 format %{ "[$reg]" %}
5180 interface(MEMORY_INTER) %{
5181 base($reg);
5182 index(0x4);
5183 scale(0x0);
5184 disp(0x0);
5185 %}
5186 %}
5188 // Indirect Memory Plus Short Offset Operand
5189 operand indOffset8(any_RegP reg, immL8 off)
5190 %{
5191 constraint(ALLOC_IN_RC(ptr_reg));
5192 match(AddP reg off);
5194 format %{ "[$reg + $off (8-bit)]" %}
5195 interface(MEMORY_INTER) %{
5196 base($reg);
5197 index(0x4);
5198 scale(0x0);
5199 disp($off);
5200 %}
5201 %}
5203 // Indirect Memory Plus Long Offset Operand
5204 operand indOffset32(any_RegP reg, immL32 off)
5205 %{
5206 constraint(ALLOC_IN_RC(ptr_reg));
5207 match(AddP reg off);
5209 format %{ "[$reg + $off (32-bit)]" %}
5210 interface(MEMORY_INTER) %{
5211 base($reg);
5212 index(0x4);
5213 scale(0x0);
5214 disp($off);
5215 %}
5216 %}
5218 // Indirect Memory Plus Index Register Plus Offset Operand
5219 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
5220 %{
5221 constraint(ALLOC_IN_RC(ptr_reg));
5222 match(AddP (AddP reg lreg) off);
5224 op_cost(10);
5225 format %{"[$reg + $off + $lreg]" %}
5226 interface(MEMORY_INTER) %{
5227 base($reg);
5228 index($lreg);
5229 scale(0x0);
5230 disp($off);
5231 %}
5232 %}
5234 // Indirect Memory Plus Index Register Plus Offset Operand
5235 operand indIndex(any_RegP reg, rRegL lreg)
5236 %{
5237 constraint(ALLOC_IN_RC(ptr_reg));
5238 match(AddP reg lreg);
5240 op_cost(10);
5241 format %{"[$reg + $lreg]" %}
5242 interface(MEMORY_INTER) %{
5243 base($reg);
5244 index($lreg);
5245 scale(0x0);
5246 disp(0x0);
5247 %}
5248 %}
5250 // Indirect Memory Times Scale Plus Index Register
5251 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
5252 %{
5253 constraint(ALLOC_IN_RC(ptr_reg));
5254 match(AddP reg (LShiftL lreg scale));
5256 op_cost(10);
5257 format %{"[$reg + $lreg << $scale]" %}
5258 interface(MEMORY_INTER) %{
5259 base($reg);
5260 index($lreg);
5261 scale($scale);
5262 disp(0x0);
5263 %}
5264 %}
5266 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5267 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
5268 %{
5269 constraint(ALLOC_IN_RC(ptr_reg));
5270 match(AddP (AddP reg (LShiftL lreg scale)) off);
5272 op_cost(10);
5273 format %{"[$reg + $off + $lreg << $scale]" %}
5274 interface(MEMORY_INTER) %{
5275 base($reg);
5276 index($lreg);
5277 scale($scale);
5278 disp($off);
5279 %}
5280 %}
5282 // Indirect Narrow Oop Plus Offset Operand
5283 operand indNarrowOopOffset(rRegN src, immL32 off) %{
5284 constraint(ALLOC_IN_RC(ptr_reg));
5285 match(AddP (DecodeN src) off);
5287 op_cost(10);
5288 format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %}
5289 interface(MEMORY_INTER) %{
5290 base(0xc); // R12
5291 index($src);
5292 scale(0x3);
5293 disp($off);
5294 %}
5295 %}
5297 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
5298 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
5299 %{
5300 constraint(ALLOC_IN_RC(ptr_reg));
5301 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5302 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
5304 op_cost(10);
5305 format %{"[$reg + $off + $idx << $scale]" %}
5306 interface(MEMORY_INTER) %{
5307 base($reg);
5308 index($idx);
5309 scale($scale);
5310 disp($off);
5311 %}
5312 %}
5314 //----------Special Memory Operands--------------------------------------------
5315 // Stack Slot Operand - This operand is used for loading and storing temporary
5316 // values on the stack where a match requires a value to
5317 // flow through memory.
5318 operand stackSlotP(sRegP reg)
5319 %{
5320 constraint(ALLOC_IN_RC(stack_slots));
5321 // No match rule because this operand is only generated in matching
5323 format %{ "[$reg]" %}
5324 interface(MEMORY_INTER) %{
5325 base(0x4); // RSP
5326 index(0x4); // No Index
5327 scale(0x0); // No Scale
5328 disp($reg); // Stack Offset
5329 %}
5330 %}
5332 operand stackSlotI(sRegI reg)
5333 %{
5334 constraint(ALLOC_IN_RC(stack_slots));
5335 // No match rule because this operand is only generated in matching
5337 format %{ "[$reg]" %}
5338 interface(MEMORY_INTER) %{
5339 base(0x4); // RSP
5340 index(0x4); // No Index
5341 scale(0x0); // No Scale
5342 disp($reg); // Stack Offset
5343 %}
5344 %}
5346 operand stackSlotF(sRegF reg)
5347 %{
5348 constraint(ALLOC_IN_RC(stack_slots));
5349 // No match rule because this operand is only generated in matching
5351 format %{ "[$reg]" %}
5352 interface(MEMORY_INTER) %{
5353 base(0x4); // RSP
5354 index(0x4); // No Index
5355 scale(0x0); // No Scale
5356 disp($reg); // Stack Offset
5357 %}
5358 %}
5360 operand stackSlotD(sRegD reg)
5361 %{
5362 constraint(ALLOC_IN_RC(stack_slots));
5363 // No match rule because this operand is only generated in matching
5365 format %{ "[$reg]" %}
5366 interface(MEMORY_INTER) %{
5367 base(0x4); // RSP
5368 index(0x4); // No Index
5369 scale(0x0); // No Scale
5370 disp($reg); // Stack Offset
5371 %}
5372 %}
5373 operand stackSlotL(sRegL reg)
5374 %{
5375 constraint(ALLOC_IN_RC(stack_slots));
5376 // No match rule because this operand is only generated in matching
5378 format %{ "[$reg]" %}
5379 interface(MEMORY_INTER) %{
5380 base(0x4); // RSP
5381 index(0x4); // No Index
5382 scale(0x0); // No Scale
5383 disp($reg); // Stack Offset
5384 %}
5385 %}
5387 //----------Conditional Branch Operands----------------------------------------
5388 // Comparison Op - This is the operation of the comparison, and is limited to
5389 // the following set of codes:
5390 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5391 //
5392 // Other attributes of the comparison, such as unsignedness, are specified
5393 // by the comparison instruction that sets a condition code flags register.
5394 // That result is represented by a flags operand whose subtype is appropriate
5395 // to the unsignedness (etc.) of the comparison.
5396 //
5397 // Later, the instruction which matches both the Comparison Op (a Bool) and
5398 // the flags (produced by the Cmp) specifies the coding of the comparison op
5399 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5401 // Comparision Code
5402 operand cmpOp()
5403 %{
5404 match(Bool);
5406 format %{ "" %}
5407 interface(COND_INTER) %{
5408 equal(0x4);
5409 not_equal(0x5);
5410 less(0xC);
5411 greater_equal(0xD);
5412 less_equal(0xE);
5413 greater(0xF);
5414 %}
5415 %}
5417 // Comparison Code, unsigned compare. Used by FP also, with
5418 // C2 (unordered) turned into GT or LT already. The other bits
5419 // C0 and C3 are turned into Carry & Zero flags.
5420 operand cmpOpU()
5421 %{
5422 match(Bool);
5424 format %{ "" %}
5425 interface(COND_INTER) %{
5426 equal(0x4);
5427 not_equal(0x5);
5428 less(0x2);
5429 greater_equal(0x3);
5430 less_equal(0x6);
5431 greater(0x7);
5432 %}
5433 %}
5436 //----------OPERAND CLASSES----------------------------------------------------
5437 // Operand Classes are groups of operands that are used as to simplify
5438 // instruction definitions by not requiring the AD writer to specify seperate
5439 // instructions for every form of operand when the instruction accepts
5440 // multiple operand types with the same basic encoding and format. The classic
5441 // case of this is memory operands.
5443 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
5444 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
5445 indNarrowOopOffset);
5447 //----------PIPELINE-----------------------------------------------------------
5448 // Rules which define the behavior of the target architectures pipeline.
5449 pipeline %{
5451 //----------ATTRIBUTES---------------------------------------------------------
5452 attributes %{
5453 variable_size_instructions; // Fixed size instructions
5454 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5455 instruction_unit_size = 1; // An instruction is 1 bytes long
5456 instruction_fetch_unit_size = 16; // The processor fetches one line
5457 instruction_fetch_units = 1; // of 16 bytes
5459 // List of nop instructions
5460 nops( MachNop );
5461 %}
5463 //----------RESOURCES----------------------------------------------------------
5464 // Resources are the functional units available to the machine
5466 // Generic P2/P3 pipeline
5467 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5468 // 3 instructions decoded per cycle.
5469 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5470 // 3 ALU op, only ALU0 handles mul instructions.
5471 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5472 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
5473 BR, FPU,
5474 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
5476 //----------PIPELINE DESCRIPTION-----------------------------------------------
5477 // Pipeline Description specifies the stages in the machine's pipeline
5479 // Generic P2/P3 pipeline
5480 pipe_desc(S0, S1, S2, S3, S4, S5);
5482 //----------PIPELINE CLASSES---------------------------------------------------
5483 // Pipeline Classes describe the stages in which input and output are
5484 // referenced by the hardware pipeline.
5486 // Naming convention: ialu or fpu
5487 // Then: _reg
5488 // Then: _reg if there is a 2nd register
5489 // Then: _long if it's a pair of instructions implementing a long
5490 // Then: _fat if it requires the big decoder
5491 // Or: _mem if it requires the big decoder and a memory unit.
5493 // Integer ALU reg operation
5494 pipe_class ialu_reg(rRegI dst)
5495 %{
5496 single_instruction;
5497 dst : S4(write);
5498 dst : S3(read);
5499 DECODE : S0; // any decoder
5500 ALU : S3; // any alu
5501 %}
5503 // Long ALU reg operation
5504 pipe_class ialu_reg_long(rRegL dst)
5505 %{
5506 instruction_count(2);
5507 dst : S4(write);
5508 dst : S3(read);
5509 DECODE : S0(2); // any 2 decoders
5510 ALU : S3(2); // both alus
5511 %}
5513 // Integer ALU reg operation using big decoder
5514 pipe_class ialu_reg_fat(rRegI dst)
5515 %{
5516 single_instruction;
5517 dst : S4(write);
5518 dst : S3(read);
5519 D0 : S0; // big decoder only
5520 ALU : S3; // any alu
5521 %}
5523 // Long ALU reg operation using big decoder
5524 pipe_class ialu_reg_long_fat(rRegL dst)
5525 %{
5526 instruction_count(2);
5527 dst : S4(write);
5528 dst : S3(read);
5529 D0 : S0(2); // big decoder only; twice
5530 ALU : S3(2); // any 2 alus
5531 %}
5533 // Integer ALU reg-reg operation
5534 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
5535 %{
5536 single_instruction;
5537 dst : S4(write);
5538 src : S3(read);
5539 DECODE : S0; // any decoder
5540 ALU : S3; // any alu
5541 %}
5543 // Long ALU reg-reg operation
5544 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
5545 %{
5546 instruction_count(2);
5547 dst : S4(write);
5548 src : S3(read);
5549 DECODE : S0(2); // any 2 decoders
5550 ALU : S3(2); // both alus
5551 %}
5553 // Integer ALU reg-reg operation
5554 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
5555 %{
5556 single_instruction;
5557 dst : S4(write);
5558 src : S3(read);
5559 D0 : S0; // big decoder only
5560 ALU : S3; // any alu
5561 %}
5563 // Long ALU reg-reg operation
5564 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
5565 %{
5566 instruction_count(2);
5567 dst : S4(write);
5568 src : S3(read);
5569 D0 : S0(2); // big decoder only; twice
5570 ALU : S3(2); // both alus
5571 %}
5573 // Integer ALU reg-mem operation
5574 pipe_class ialu_reg_mem(rRegI dst, memory mem)
5575 %{
5576 single_instruction;
5577 dst : S5(write);
5578 mem : S3(read);
5579 D0 : S0; // big decoder only
5580 ALU : S4; // any alu
5581 MEM : S3; // any mem
5582 %}
5584 // Integer mem operation (prefetch)
5585 pipe_class ialu_mem(memory mem)
5586 %{
5587 single_instruction;
5588 mem : S3(read);
5589 D0 : S0; // big decoder only
5590 MEM : S3; // any mem
5591 %}
5593 // Integer Store to Memory
5594 pipe_class ialu_mem_reg(memory mem, rRegI src)
5595 %{
5596 single_instruction;
5597 mem : S3(read);
5598 src : S5(read);
5599 D0 : S0; // big decoder only
5600 ALU : S4; // any alu
5601 MEM : S3;
5602 %}
5604 // // Long Store to Memory
5605 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
5606 // %{
5607 // instruction_count(2);
5608 // mem : S3(read);
5609 // src : S5(read);
5610 // D0 : S0(2); // big decoder only; twice
5611 // ALU : S4(2); // any 2 alus
5612 // MEM : S3(2); // Both mems
5613 // %}
5615 // Integer Store to Memory
5616 pipe_class ialu_mem_imm(memory mem)
5617 %{
5618 single_instruction;
5619 mem : S3(read);
5620 D0 : S0; // big decoder only
5621 ALU : S4; // any alu
5622 MEM : S3;
5623 %}
5625 // Integer ALU0 reg-reg operation
5626 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
5627 %{
5628 single_instruction;
5629 dst : S4(write);
5630 src : S3(read);
5631 D0 : S0; // Big decoder only
5632 ALU0 : S3; // only alu0
5633 %}
5635 // Integer ALU0 reg-mem operation
5636 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
5637 %{
5638 single_instruction;
5639 dst : S5(write);
5640 mem : S3(read);
5641 D0 : S0; // big decoder only
5642 ALU0 : S4; // ALU0 only
5643 MEM : S3; // any mem
5644 %}
5646 // Integer ALU reg-reg operation
5647 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
5648 %{
5649 single_instruction;
5650 cr : S4(write);
5651 src1 : S3(read);
5652 src2 : S3(read);
5653 DECODE : S0; // any decoder
5654 ALU : S3; // any alu
5655 %}
5657 // Integer ALU reg-imm operation
5658 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
5659 %{
5660 single_instruction;
5661 cr : S4(write);
5662 src1 : S3(read);
5663 DECODE : S0; // any decoder
5664 ALU : S3; // any alu
5665 %}
5667 // Integer ALU reg-mem operation
5668 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
5669 %{
5670 single_instruction;
5671 cr : S4(write);
5672 src1 : S3(read);
5673 src2 : S3(read);
5674 D0 : S0; // big decoder only
5675 ALU : S4; // any alu
5676 MEM : S3;
5677 %}
5679 // Conditional move reg-reg
5680 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
5681 %{
5682 instruction_count(4);
5683 y : S4(read);
5684 q : S3(read);
5685 p : S3(read);
5686 DECODE : S0(4); // any decoder
5687 %}
5689 // Conditional move reg-reg
5690 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
5691 %{
5692 single_instruction;
5693 dst : S4(write);
5694 src : S3(read);
5695 cr : S3(read);
5696 DECODE : S0; // any decoder
5697 %}
5699 // Conditional move reg-mem
5700 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
5701 %{
5702 single_instruction;
5703 dst : S4(write);
5704 src : S3(read);
5705 cr : S3(read);
5706 DECODE : S0; // any decoder
5707 MEM : S3;
5708 %}
5710 // Conditional move reg-reg long
5711 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
5712 %{
5713 single_instruction;
5714 dst : S4(write);
5715 src : S3(read);
5716 cr : S3(read);
5717 DECODE : S0(2); // any 2 decoders
5718 %}
5720 // XXX
5721 // // Conditional move double reg-reg
5722 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
5723 // %{
5724 // single_instruction;
5725 // dst : S4(write);
5726 // src : S3(read);
5727 // cr : S3(read);
5728 // DECODE : S0; // any decoder
5729 // %}
5731 // Float reg-reg operation
5732 pipe_class fpu_reg(regD dst)
5733 %{
5734 instruction_count(2);
5735 dst : S3(read);
5736 DECODE : S0(2); // any 2 decoders
5737 FPU : S3;
5738 %}
5740 // Float reg-reg operation
5741 pipe_class fpu_reg_reg(regD dst, regD src)
5742 %{
5743 instruction_count(2);
5744 dst : S4(write);
5745 src : S3(read);
5746 DECODE : S0(2); // any 2 decoders
5747 FPU : S3;
5748 %}
5750 // Float reg-reg operation
5751 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
5752 %{
5753 instruction_count(3);
5754 dst : S4(write);
5755 src1 : S3(read);
5756 src2 : S3(read);
5757 DECODE : S0(3); // any 3 decoders
5758 FPU : S3(2);
5759 %}
5761 // Float reg-reg operation
5762 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
5763 %{
5764 instruction_count(4);
5765 dst : S4(write);
5766 src1 : S3(read);
5767 src2 : S3(read);
5768 src3 : S3(read);
5769 DECODE : S0(4); // any 3 decoders
5770 FPU : S3(2);
5771 %}
5773 // Float reg-reg operation
5774 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
5775 %{
5776 instruction_count(4);
5777 dst : S4(write);
5778 src1 : S3(read);
5779 src2 : S3(read);
5780 src3 : S3(read);
5781 DECODE : S1(3); // any 3 decoders
5782 D0 : S0; // Big decoder only
5783 FPU : S3(2);
5784 MEM : S3;
5785 %}
5787 // Float reg-mem operation
5788 pipe_class fpu_reg_mem(regD dst, memory mem)
5789 %{
5790 instruction_count(2);
5791 dst : S5(write);
5792 mem : S3(read);
5793 D0 : S0; // big decoder only
5794 DECODE : S1; // any decoder for FPU POP
5795 FPU : S4;
5796 MEM : S3; // any mem
5797 %}
5799 // Float reg-mem operation
5800 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
5801 %{
5802 instruction_count(3);
5803 dst : S5(write);
5804 src1 : S3(read);
5805 mem : S3(read);
5806 D0 : S0; // big decoder only
5807 DECODE : S1(2); // any decoder for FPU POP
5808 FPU : S4;
5809 MEM : S3; // any mem
5810 %}
5812 // Float mem-reg operation
5813 pipe_class fpu_mem_reg(memory mem, regD src)
5814 %{
5815 instruction_count(2);
5816 src : S5(read);
5817 mem : S3(read);
5818 DECODE : S0; // any decoder for FPU PUSH
5819 D0 : S1; // big decoder only
5820 FPU : S4;
5821 MEM : S3; // any mem
5822 %}
5824 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
5825 %{
5826 instruction_count(3);
5827 src1 : S3(read);
5828 src2 : S3(read);
5829 mem : S3(read);
5830 DECODE : S0(2); // any decoder for FPU PUSH
5831 D0 : S1; // big decoder only
5832 FPU : S4;
5833 MEM : S3; // any mem
5834 %}
5836 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
5837 %{
5838 instruction_count(3);
5839 src1 : S3(read);
5840 src2 : S3(read);
5841 mem : S4(read);
5842 DECODE : S0; // any decoder for FPU PUSH
5843 D0 : S0(2); // big decoder only
5844 FPU : S4;
5845 MEM : S3(2); // any mem
5846 %}
5848 pipe_class fpu_mem_mem(memory dst, memory src1)
5849 %{
5850 instruction_count(2);
5851 src1 : S3(read);
5852 dst : S4(read);
5853 D0 : S0(2); // big decoder only
5854 MEM : S3(2); // any mem
5855 %}
5857 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
5858 %{
5859 instruction_count(3);
5860 src1 : S3(read);
5861 src2 : S3(read);
5862 dst : S4(read);
5863 D0 : S0(3); // big decoder only
5864 FPU : S4;
5865 MEM : S3(3); // any mem
5866 %}
5868 pipe_class fpu_mem_reg_con(memory mem, regD src1)
5869 %{
5870 instruction_count(3);
5871 src1 : S4(read);
5872 mem : S4(read);
5873 DECODE : S0; // any decoder for FPU PUSH
5874 D0 : S0(2); // big decoder only
5875 FPU : S4;
5876 MEM : S3(2); // any mem
5877 %}
5879 // Float load constant
5880 pipe_class fpu_reg_con(regD dst)
5881 %{
5882 instruction_count(2);
5883 dst : S5(write);
5884 D0 : S0; // big decoder only for the load
5885 DECODE : S1; // any decoder for FPU POP
5886 FPU : S4;
5887 MEM : S3; // any mem
5888 %}
5890 // Float load constant
5891 pipe_class fpu_reg_reg_con(regD dst, regD src)
5892 %{
5893 instruction_count(3);
5894 dst : S5(write);
5895 src : S3(read);
5896 D0 : S0; // big decoder only for the load
5897 DECODE : S1(2); // any decoder for FPU POP
5898 FPU : S4;
5899 MEM : S3; // any mem
5900 %}
5902 // UnConditional branch
5903 pipe_class pipe_jmp(label labl)
5904 %{
5905 single_instruction;
5906 BR : S3;
5907 %}
5909 // Conditional branch
5910 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
5911 %{
5912 single_instruction;
5913 cr : S1(read);
5914 BR : S3;
5915 %}
5917 // Allocation idiom
5918 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
5919 %{
5920 instruction_count(1); force_serialization;
5921 fixed_latency(6);
5922 heap_ptr : S3(read);
5923 DECODE : S0(3);
5924 D0 : S2;
5925 MEM : S3;
5926 ALU : S3(2);
5927 dst : S5(write);
5928 BR : S5;
5929 %}
5931 // Generic big/slow expanded idiom
5932 pipe_class pipe_slow()
5933 %{
5934 instruction_count(10); multiple_bundles; force_serialization;
5935 fixed_latency(100);
5936 D0 : S0(2);
5937 MEM : S3(2);
5938 %}
5940 // The real do-nothing guy
5941 pipe_class empty()
5942 %{
5943 instruction_count(0);
5944 %}
5946 // Define the class for the Nop node
5947 define
5948 %{
5949 MachNop = empty;
5950 %}
5952 %}
5954 //----------INSTRUCTIONS-------------------------------------------------------
5955 //
5956 // match -- States which machine-independent subtree may be replaced
5957 // by this instruction.
5958 // ins_cost -- The estimated cost of this instruction is used by instruction
5959 // selection to identify a minimum cost tree of machine
5960 // instructions that matches a tree of machine-independent
5961 // instructions.
5962 // format -- A string providing the disassembly for this instruction.
5963 // The value of an instruction's operand may be inserted
5964 // by referring to it with a '$' prefix.
5965 // opcode -- Three instruction opcodes may be provided. These are referred
5966 // to within an encode class as $primary, $secondary, and $tertiary
5967 // rrspectively. The primary opcode is commonly used to
5968 // indicate the type of machine instruction, while secondary
5969 // and tertiary are often used for prefix options or addressing
5970 // modes.
5971 // ins_encode -- A list of encode classes with parameters. The encode class
5972 // name must have been defined in an 'enc_class' specification
5973 // in the encode section of the architecture description.
5976 //----------Load/Store/Move Instructions---------------------------------------
5977 //----------Load Instructions--------------------------------------------------
5979 // Load Byte (8 bit signed)
5980 instruct loadB(rRegI dst, memory mem)
5981 %{
5982 match(Set dst (LoadB mem));
5984 ins_cost(125);
5985 format %{ "movsbl $dst, $mem\t# byte" %}
5986 opcode(0x0F, 0xBE);
5987 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5988 ins_pipe(ialu_reg_mem);
5989 %}
5991 // Load Byte (8 bit signed) into long
5992 // instruct loadB2L(rRegL dst, memory mem)
5993 // %{
5994 // match(Set dst (ConvI2L (LoadB mem)));
5996 // ins_cost(125);
5997 // format %{ "movsbq $dst, $mem\t# byte -> long" %}
5998 // opcode(0x0F, 0xBE);
5999 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6000 // ins_pipe(ialu_reg_mem);
6001 // %}
6003 // Load Byte (8 bit UNsigned)
6004 instruct loadUB(rRegI dst, memory mem, immI_255 bytemask)
6005 %{
6006 match(Set dst (AndI (LoadB mem) bytemask));
6008 ins_cost(125);
6009 format %{ "movzbl $dst, $mem\t# ubyte" %}
6010 opcode(0x0F, 0xB6);
6011 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6012 ins_pipe(ialu_reg_mem);
6013 %}
6015 // Load Byte (8 bit UNsigned) into long
6016 // instruct loadUB2L(rRegL dst, memory mem, immI_255 bytemask)
6017 // %{
6018 // match(Set dst (ConvI2L (AndI (LoadB mem) bytemask)));
6020 // ins_cost(125);
6021 // format %{ "movzbl $dst, $mem\t# ubyte -> long" %}
6022 // opcode(0x0F, 0xB6);
6023 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6024 // ins_pipe(ialu_reg_mem);
6025 // %}
6027 // Load Short (16 bit signed)
6028 instruct loadS(rRegI dst, memory mem)
6029 %{
6030 match(Set dst (LoadS mem));
6032 ins_cost(125); // XXX
6033 format %{ "movswl $dst, $mem\t# short" %}
6034 opcode(0x0F, 0xBF);
6035 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6036 ins_pipe(ialu_reg_mem);
6037 %}
6039 // Load Short (16 bit signed) into long
6040 // instruct loadS2L(rRegL dst, memory mem)
6041 // %{
6042 // match(Set dst (ConvI2L (LoadS mem)));
6044 // ins_cost(125); // XXX
6045 // format %{ "movswq $dst, $mem\t# short -> long" %}
6046 // opcode(0x0F, 0xBF);
6047 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6048 // ins_pipe(ialu_reg_mem);
6049 // %}
6051 // Load Char (16 bit UNsigned)
6052 instruct loadC(rRegI dst, memory mem)
6053 %{
6054 match(Set dst (LoadC mem));
6056 ins_cost(125);
6057 format %{ "movzwl $dst, $mem\t# char" %}
6058 opcode(0x0F, 0xB7);
6059 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6060 ins_pipe(ialu_reg_mem);
6061 %}
6063 // Load Char (16 bit UNsigned) into long
6064 // instruct loadC2L(rRegL dst, memory mem)
6065 // %{
6066 // match(Set dst (ConvI2L (LoadC mem)));
6068 // ins_cost(125);
6069 // format %{ "movzwl $dst, $mem\t# char -> long" %}
6070 // opcode(0x0F, 0xB7);
6071 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6072 // ins_pipe(ialu_reg_mem);
6073 // %}
6075 // Load Integer
6076 instruct loadI(rRegI dst, memory mem)
6077 %{
6078 match(Set dst (LoadI mem));
6080 ins_cost(125); // XXX
6081 format %{ "movl $dst, $mem\t# int" %}
6082 opcode(0x8B);
6083 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6084 ins_pipe(ialu_reg_mem);
6085 %}
6087 // Load Long
6088 instruct loadL(rRegL dst, memory mem)
6089 %{
6090 match(Set dst (LoadL mem));
6092 ins_cost(125); // XXX
6093 format %{ "movq $dst, $mem\t# long" %}
6094 opcode(0x8B);
6095 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6096 ins_pipe(ialu_reg_mem); // XXX
6097 %}
6099 // Load Range
6100 instruct loadRange(rRegI dst, memory mem)
6101 %{
6102 match(Set dst (LoadRange mem));
6104 ins_cost(125); // XXX
6105 format %{ "movl $dst, $mem\t# range" %}
6106 opcode(0x8B);
6107 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6108 ins_pipe(ialu_reg_mem);
6109 %}
6111 // Load Pointer
6112 instruct loadP(rRegP dst, memory mem)
6113 %{
6114 match(Set dst (LoadP mem));
6116 ins_cost(125); // XXX
6117 format %{ "movq $dst, $mem\t# ptr" %}
6118 opcode(0x8B);
6119 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6120 ins_pipe(ialu_reg_mem); // XXX
6121 %}
6123 // Load Compressed Pointer
6124 instruct loadN(rRegN dst, memory mem)
6125 %{
6126 match(Set dst (LoadN mem));
6128 ins_cost(125); // XXX
6129 format %{ "movl $dst, $mem\t# compressed ptr" %}
6130 ins_encode %{
6131 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6132 Register dst = as_Register($dst$$reg);
6133 __ movl(dst, addr);
6134 %}
6135 ins_pipe(ialu_reg_mem); // XXX
6136 %}
6139 // Load Klass Pointer
6140 instruct loadKlass(rRegP dst, memory mem)
6141 %{
6142 match(Set dst (LoadKlass mem));
6144 ins_cost(125); // XXX
6145 format %{ "movq $dst, $mem\t# class" %}
6146 opcode(0x8B);
6147 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6148 ins_pipe(ialu_reg_mem); // XXX
6149 %}
6151 // Load narrow Klass Pointer
6152 instruct loadNKlass(rRegN dst, memory mem)
6153 %{
6154 match(Set dst (LoadNKlass mem));
6156 ins_cost(125); // XXX
6157 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
6158 ins_encode %{
6159 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6160 Register dst = as_Register($dst$$reg);
6161 __ movl(dst, addr);
6162 %}
6163 ins_pipe(ialu_reg_mem); // XXX
6164 %}
6166 // Load Float
6167 instruct loadF(regF dst, memory mem)
6168 %{
6169 match(Set dst (LoadF mem));
6171 ins_cost(145); // XXX
6172 format %{ "movss $dst, $mem\t# float" %}
6173 opcode(0xF3, 0x0F, 0x10);
6174 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6175 ins_pipe(pipe_slow); // XXX
6176 %}
6178 // Load Double
6179 instruct loadD_partial(regD dst, memory mem)
6180 %{
6181 predicate(!UseXmmLoadAndClearUpper);
6182 match(Set dst (LoadD mem));
6184 ins_cost(145); // XXX
6185 format %{ "movlpd $dst, $mem\t# double" %}
6186 opcode(0x66, 0x0F, 0x12);
6187 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6188 ins_pipe(pipe_slow); // XXX
6189 %}
6191 instruct loadD(regD dst, memory mem)
6192 %{
6193 predicate(UseXmmLoadAndClearUpper);
6194 match(Set dst (LoadD mem));
6196 ins_cost(145); // XXX
6197 format %{ "movsd $dst, $mem\t# double" %}
6198 opcode(0xF2, 0x0F, 0x10);
6199 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6200 ins_pipe(pipe_slow); // XXX
6201 %}
6203 // Load Aligned Packed Byte to XMM register
6204 instruct loadA8B(regD dst, memory mem) %{
6205 match(Set dst (Load8B mem));
6206 ins_cost(125);
6207 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6208 ins_encode( movq_ld(dst, mem));
6209 ins_pipe( pipe_slow );
6210 %}
6212 // Load Aligned Packed Short to XMM register
6213 instruct loadA4S(regD dst, memory mem) %{
6214 match(Set dst (Load4S mem));
6215 ins_cost(125);
6216 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6217 ins_encode( movq_ld(dst, mem));
6218 ins_pipe( pipe_slow );
6219 %}
6221 // Load Aligned Packed Char to XMM register
6222 instruct loadA4C(regD dst, memory mem) %{
6223 match(Set dst (Load4C mem));
6224 ins_cost(125);
6225 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6226 ins_encode( movq_ld(dst, mem));
6227 ins_pipe( pipe_slow );
6228 %}
6230 // Load Aligned Packed Integer to XMM register
6231 instruct load2IU(regD dst, memory mem) %{
6232 match(Set dst (Load2I mem));
6233 ins_cost(125);
6234 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6235 ins_encode( movq_ld(dst, mem));
6236 ins_pipe( pipe_slow );
6237 %}
6239 // Load Aligned Packed Single to XMM
6240 instruct loadA2F(regD dst, memory mem) %{
6241 match(Set dst (Load2F mem));
6242 ins_cost(145);
6243 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6244 ins_encode( movq_ld(dst, mem));
6245 ins_pipe( pipe_slow );
6246 %}
6248 // Load Effective Address
6249 instruct leaP8(rRegP dst, indOffset8 mem)
6250 %{
6251 match(Set dst mem);
6253 ins_cost(110); // XXX
6254 format %{ "leaq $dst, $mem\t# ptr 8" %}
6255 opcode(0x8D);
6256 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6257 ins_pipe(ialu_reg_reg_fat);
6258 %}
6260 instruct leaP32(rRegP dst, indOffset32 mem)
6261 %{
6262 match(Set dst mem);
6264 ins_cost(110);
6265 format %{ "leaq $dst, $mem\t# ptr 32" %}
6266 opcode(0x8D);
6267 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6268 ins_pipe(ialu_reg_reg_fat);
6269 %}
6271 // instruct leaPIdx(rRegP dst, indIndex mem)
6272 // %{
6273 // match(Set dst mem);
6275 // ins_cost(110);
6276 // format %{ "leaq $dst, $mem\t# ptr idx" %}
6277 // opcode(0x8D);
6278 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6279 // ins_pipe(ialu_reg_reg_fat);
6280 // %}
6282 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
6283 %{
6284 match(Set dst mem);
6286 ins_cost(110);
6287 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
6288 opcode(0x8D);
6289 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6290 ins_pipe(ialu_reg_reg_fat);
6291 %}
6293 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
6294 %{
6295 match(Set dst mem);
6297 ins_cost(110);
6298 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
6299 opcode(0x8D);
6300 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6301 ins_pipe(ialu_reg_reg_fat);
6302 %}
6304 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
6305 %{
6306 match(Set dst mem);
6308 ins_cost(110);
6309 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
6310 opcode(0x8D);
6311 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6312 ins_pipe(ialu_reg_reg_fat);
6313 %}
6315 instruct loadConI(rRegI dst, immI src)
6316 %{
6317 match(Set dst src);
6319 format %{ "movl $dst, $src\t# int" %}
6320 ins_encode(load_immI(dst, src));
6321 ins_pipe(ialu_reg_fat); // XXX
6322 %}
6324 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
6325 %{
6326 match(Set dst src);
6327 effect(KILL cr);
6329 ins_cost(50);
6330 format %{ "xorl $dst, $dst\t# int" %}
6331 opcode(0x33); /* + rd */
6332 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6333 ins_pipe(ialu_reg);
6334 %}
6336 instruct loadConL(rRegL dst, immL src)
6337 %{
6338 match(Set dst src);
6340 ins_cost(150);
6341 format %{ "movq $dst, $src\t# long" %}
6342 ins_encode(load_immL(dst, src));
6343 ins_pipe(ialu_reg);
6344 %}
6346 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
6347 %{
6348 match(Set dst src);
6349 effect(KILL cr);
6351 ins_cost(50);
6352 format %{ "xorl $dst, $dst\t# long" %}
6353 opcode(0x33); /* + rd */
6354 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6355 ins_pipe(ialu_reg); // XXX
6356 %}
6358 instruct loadConUL32(rRegL dst, immUL32 src)
6359 %{
6360 match(Set dst src);
6362 ins_cost(60);
6363 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
6364 ins_encode(load_immUL32(dst, src));
6365 ins_pipe(ialu_reg);
6366 %}
6368 instruct loadConL32(rRegL dst, immL32 src)
6369 %{
6370 match(Set dst src);
6372 ins_cost(70);
6373 format %{ "movq $dst, $src\t# long (32-bit)" %}
6374 ins_encode(load_immL32(dst, src));
6375 ins_pipe(ialu_reg);
6376 %}
6378 instruct loadConP(rRegP dst, immP src)
6379 %{
6380 match(Set dst src);
6382 format %{ "movq $dst, $src\t# ptr" %}
6383 ins_encode(load_immP(dst, src));
6384 ins_pipe(ialu_reg_fat); // XXX
6385 %}
6387 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
6388 %{
6389 match(Set dst src);
6390 effect(KILL cr);
6392 ins_cost(50);
6393 format %{ "xorl $dst, $dst\t# ptr" %}
6394 opcode(0x33); /* + rd */
6395 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6396 ins_pipe(ialu_reg);
6397 %}
6399 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
6400 %{
6401 match(Set dst src);
6402 effect(KILL cr);
6404 ins_cost(60);
6405 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
6406 ins_encode(load_immP31(dst, src));
6407 ins_pipe(ialu_reg);
6408 %}
6410 instruct loadConF(regF dst, immF src)
6411 %{
6412 match(Set dst src);
6413 ins_cost(125);
6415 format %{ "movss $dst, [$src]" %}
6416 ins_encode(load_conF(dst, src));
6417 ins_pipe(pipe_slow);
6418 %}
6420 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6421 match(Set dst src);
6422 effect(KILL cr);
6423 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
6424 ins_encode %{
6425 Register dst = $dst$$Register;
6426 __ xorq(dst, dst);
6427 %}
6428 ins_pipe(ialu_reg);
6429 %}
6431 instruct loadConN(rRegN dst, immN src) %{
6432 match(Set dst src);
6434 ins_cost(125);
6435 format %{ "movl $dst, $src\t# compressed ptr" %}
6436 ins_encode %{
6437 address con = (address)$src$$constant;
6438 Register dst = $dst$$Register;
6439 if (con == NULL) {
6440 ShouldNotReachHere();
6441 } else {
6442 __ set_narrow_oop(dst, (jobject)$src$$constant);
6443 }
6444 %}
6445 ins_pipe(ialu_reg_fat); // XXX
6446 %}
6448 instruct loadConF0(regF dst, immF0 src)
6449 %{
6450 match(Set dst src);
6451 ins_cost(100);
6453 format %{ "xorps $dst, $dst\t# float 0.0" %}
6454 opcode(0x0F, 0x57);
6455 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
6456 ins_pipe(pipe_slow);
6457 %}
6459 // Use the same format since predicate() can not be used here.
6460 instruct loadConD(regD dst, immD src)
6461 %{
6462 match(Set dst src);
6463 ins_cost(125);
6465 format %{ "movsd $dst, [$src]" %}
6466 ins_encode(load_conD(dst, src));
6467 ins_pipe(pipe_slow);
6468 %}
6470 instruct loadConD0(regD dst, immD0 src)
6471 %{
6472 match(Set dst src);
6473 ins_cost(100);
6475 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6476 opcode(0x66, 0x0F, 0x57);
6477 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst));
6478 ins_pipe(pipe_slow);
6479 %}
6481 instruct loadSSI(rRegI dst, stackSlotI src)
6482 %{
6483 match(Set dst src);
6485 ins_cost(125);
6486 format %{ "movl $dst, $src\t# int stk" %}
6487 opcode(0x8B);
6488 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6489 ins_pipe(ialu_reg_mem);
6490 %}
6492 instruct loadSSL(rRegL dst, stackSlotL src)
6493 %{
6494 match(Set dst src);
6496 ins_cost(125);
6497 format %{ "movq $dst, $src\t# long stk" %}
6498 opcode(0x8B);
6499 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6500 ins_pipe(ialu_reg_mem);
6501 %}
6503 instruct loadSSP(rRegP dst, stackSlotP src)
6504 %{
6505 match(Set dst src);
6507 ins_cost(125);
6508 format %{ "movq $dst, $src\t# ptr stk" %}
6509 opcode(0x8B);
6510 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6511 ins_pipe(ialu_reg_mem);
6512 %}
6514 instruct loadSSF(regF dst, stackSlotF src)
6515 %{
6516 match(Set dst src);
6518 ins_cost(125);
6519 format %{ "movss $dst, $src\t# float stk" %}
6520 opcode(0xF3, 0x0F, 0x10);
6521 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
6522 ins_pipe(pipe_slow); // XXX
6523 %}
6525 // Use the same format since predicate() can not be used here.
6526 instruct loadSSD(regD dst, stackSlotD src)
6527 %{
6528 match(Set dst src);
6530 ins_cost(125);
6531 format %{ "movsd $dst, $src\t# double stk" %}
6532 ins_encode %{
6533 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6534 %}
6535 ins_pipe(pipe_slow); // XXX
6536 %}
6538 // Prefetch instructions.
6539 // Must be safe to execute with invalid address (cannot fault).
6541 instruct prefetchr( memory mem ) %{
6542 predicate(ReadPrefetchInstr==3);
6543 match(PrefetchRead mem);
6544 ins_cost(125);
6546 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6547 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
6548 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6549 ins_pipe(ialu_mem);
6550 %}
6552 instruct prefetchrNTA( memory mem ) %{
6553 predicate(ReadPrefetchInstr==0);
6554 match(PrefetchRead mem);
6555 ins_cost(125);
6557 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6558 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6559 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6560 ins_pipe(ialu_mem);
6561 %}
6563 instruct prefetchrT0( memory mem ) %{
6564 predicate(ReadPrefetchInstr==1);
6565 match(PrefetchRead mem);
6566 ins_cost(125);
6568 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6569 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6570 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6571 ins_pipe(ialu_mem);
6572 %}
6574 instruct prefetchrT2( memory mem ) %{
6575 predicate(ReadPrefetchInstr==2);
6576 match(PrefetchRead mem);
6577 ins_cost(125);
6579 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6580 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6581 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6582 ins_pipe(ialu_mem);
6583 %}
6585 instruct prefetchw( memory mem ) %{
6586 predicate(AllocatePrefetchInstr==3);
6587 match(PrefetchWrite mem);
6588 ins_cost(125);
6590 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
6591 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6592 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6593 ins_pipe(ialu_mem);
6594 %}
6596 instruct prefetchwNTA( memory mem ) %{
6597 predicate(AllocatePrefetchInstr==0);
6598 match(PrefetchWrite mem);
6599 ins_cost(125);
6601 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6602 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6603 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6604 ins_pipe(ialu_mem);
6605 %}
6607 instruct prefetchwT0( memory mem ) %{
6608 predicate(AllocatePrefetchInstr==1);
6609 match(PrefetchWrite mem);
6610 ins_cost(125);
6612 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
6613 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6614 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6615 ins_pipe(ialu_mem);
6616 %}
6618 instruct prefetchwT2( memory mem ) %{
6619 predicate(AllocatePrefetchInstr==2);
6620 match(PrefetchWrite mem);
6621 ins_cost(125);
6623 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
6624 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6625 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6626 ins_pipe(ialu_mem);
6627 %}
6629 //----------Store Instructions-------------------------------------------------
6631 // Store Byte
6632 instruct storeB(memory mem, rRegI src)
6633 %{
6634 match(Set mem (StoreB mem src));
6636 ins_cost(125); // XXX
6637 format %{ "movb $mem, $src\t# byte" %}
6638 opcode(0x88);
6639 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6640 ins_pipe(ialu_mem_reg);
6641 %}
6643 // Store Char/Short
6644 instruct storeC(memory mem, rRegI src)
6645 %{
6646 match(Set mem (StoreC mem src));
6648 ins_cost(125); // XXX
6649 format %{ "movw $mem, $src\t# char/short" %}
6650 opcode(0x89);
6651 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6652 ins_pipe(ialu_mem_reg);
6653 %}
6655 // Store Integer
6656 instruct storeI(memory mem, rRegI src)
6657 %{
6658 match(Set mem (StoreI mem src));
6660 ins_cost(125); // XXX
6661 format %{ "movl $mem, $src\t# int" %}
6662 opcode(0x89);
6663 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6664 ins_pipe(ialu_mem_reg);
6665 %}
6667 // Store Long
6668 instruct storeL(memory mem, rRegL src)
6669 %{
6670 match(Set mem (StoreL mem src));
6672 ins_cost(125); // XXX
6673 format %{ "movq $mem, $src\t# long" %}
6674 opcode(0x89);
6675 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6676 ins_pipe(ialu_mem_reg); // XXX
6677 %}
6679 // Store Pointer
6680 instruct storeP(memory mem, any_RegP src)
6681 %{
6682 match(Set mem (StoreP mem src));
6684 ins_cost(125); // XXX
6685 format %{ "movq $mem, $src\t# ptr" %}
6686 opcode(0x89);
6687 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6688 ins_pipe(ialu_mem_reg);
6689 %}
6691 // Store NULL Pointer, mark word, or other simple pointer constant.
6692 instruct storeImmP(memory mem, immP31 src)
6693 %{
6694 match(Set mem (StoreP mem src));
6696 ins_cost(125); // XXX
6697 format %{ "movq $mem, $src\t# ptr" %}
6698 opcode(0xC7); /* C7 /0 */
6699 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6700 ins_pipe(ialu_mem_imm);
6701 %}
6703 // Store Compressed Pointer
6704 instruct storeN(memory mem, rRegN src)
6705 %{
6706 match(Set mem (StoreN mem src));
6708 ins_cost(125); // XXX
6709 format %{ "movl $mem, $src\t# compressed ptr" %}
6710 ins_encode %{
6711 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6712 Register src = as_Register($src$$reg);
6713 __ movl(addr, src);
6714 %}
6715 ins_pipe(ialu_mem_reg);
6716 %}
6718 // Store Integer Immediate
6719 instruct storeImmI(memory mem, immI src)
6720 %{
6721 match(Set mem (StoreI mem src));
6723 ins_cost(150);
6724 format %{ "movl $mem, $src\t# int" %}
6725 opcode(0xC7); /* C7 /0 */
6726 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6727 ins_pipe(ialu_mem_imm);
6728 %}
6730 // Store Long Immediate
6731 instruct storeImmL(memory mem, immL32 src)
6732 %{
6733 match(Set mem (StoreL mem src));
6735 ins_cost(150);
6736 format %{ "movq $mem, $src\t# long" %}
6737 opcode(0xC7); /* C7 /0 */
6738 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6739 ins_pipe(ialu_mem_imm);
6740 %}
6742 // Store Short/Char Immediate
6743 instruct storeImmI16(memory mem, immI16 src)
6744 %{
6745 predicate(UseStoreImmI16);
6746 match(Set mem (StoreC mem src));
6748 ins_cost(150);
6749 format %{ "movw $mem, $src\t# short/char" %}
6750 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6751 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6752 ins_pipe(ialu_mem_imm);
6753 %}
6755 // Store Byte Immediate
6756 instruct storeImmB(memory mem, immI8 src)
6757 %{
6758 match(Set mem (StoreB mem src));
6760 ins_cost(150); // XXX
6761 format %{ "movb $mem, $src\t# byte" %}
6762 opcode(0xC6); /* C6 /0 */
6763 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6764 ins_pipe(ialu_mem_imm);
6765 %}
6767 // Store Aligned Packed Byte XMM register to memory
6768 instruct storeA8B(memory mem, regD src) %{
6769 match(Set mem (Store8B mem src));
6770 ins_cost(145);
6771 format %{ "MOVQ $mem,$src\t! packed8B" %}
6772 ins_encode( movq_st(mem, src));
6773 ins_pipe( pipe_slow );
6774 %}
6776 // Store Aligned Packed Char/Short XMM register to memory
6777 instruct storeA4C(memory mem, regD src) %{
6778 match(Set mem (Store4C mem src));
6779 ins_cost(145);
6780 format %{ "MOVQ $mem,$src\t! packed4C" %}
6781 ins_encode( movq_st(mem, src));
6782 ins_pipe( pipe_slow );
6783 %}
6785 // Store Aligned Packed Integer XMM register to memory
6786 instruct storeA2I(memory mem, regD src) %{
6787 match(Set mem (Store2I mem src));
6788 ins_cost(145);
6789 format %{ "MOVQ $mem,$src\t! packed2I" %}
6790 ins_encode( movq_st(mem, src));
6791 ins_pipe( pipe_slow );
6792 %}
6794 // Store CMS card-mark Immediate
6795 instruct storeImmCM0(memory mem, immI0 src)
6796 %{
6797 match(Set mem (StoreCM mem src));
6799 ins_cost(150); // XXX
6800 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6801 opcode(0xC6); /* C6 /0 */
6802 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6803 ins_pipe(ialu_mem_imm);
6804 %}
6806 // Store Aligned Packed Single Float XMM register to memory
6807 instruct storeA2F(memory mem, regD src) %{
6808 match(Set mem (Store2F mem src));
6809 ins_cost(145);
6810 format %{ "MOVQ $mem,$src\t! packed2F" %}
6811 ins_encode( movq_st(mem, src));
6812 ins_pipe( pipe_slow );
6813 %}
6815 // Store Float
6816 instruct storeF(memory mem, regF src)
6817 %{
6818 match(Set mem (StoreF mem src));
6820 ins_cost(95); // XXX
6821 format %{ "movss $mem, $src\t# float" %}
6822 opcode(0xF3, 0x0F, 0x11);
6823 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
6824 ins_pipe(pipe_slow); // XXX
6825 %}
6827 // Store immediate Float value (it is faster than store from XMM register)
6828 instruct storeF_imm(memory mem, immF src)
6829 %{
6830 match(Set mem (StoreF mem src));
6832 ins_cost(50);
6833 format %{ "movl $mem, $src\t# float" %}
6834 opcode(0xC7); /* C7 /0 */
6835 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6836 ins_pipe(ialu_mem_imm);
6837 %}
6839 // Store Double
6840 instruct storeD(memory mem, regD src)
6841 %{
6842 match(Set mem (StoreD mem src));
6844 ins_cost(95); // XXX
6845 format %{ "movsd $mem, $src\t# double" %}
6846 opcode(0xF2, 0x0F, 0x11);
6847 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
6848 ins_pipe(pipe_slow); // XXX
6849 %}
6851 // Store immediate double 0.0 (it is faster than store from XMM register)
6852 instruct storeD0_imm(memory mem, immD0 src)
6853 %{
6854 match(Set mem (StoreD mem src));
6856 ins_cost(50);
6857 format %{ "movq $mem, $src\t# double 0." %}
6858 opcode(0xC7); /* C7 /0 */
6859 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6860 ins_pipe(ialu_mem_imm);
6861 %}
6863 instruct storeSSI(stackSlotI dst, rRegI src)
6864 %{
6865 match(Set dst src);
6867 ins_cost(100);
6868 format %{ "movl $dst, $src\t# int stk" %}
6869 opcode(0x89);
6870 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6871 ins_pipe( ialu_mem_reg );
6872 %}
6874 instruct storeSSL(stackSlotL dst, rRegL src)
6875 %{
6876 match(Set dst src);
6878 ins_cost(100);
6879 format %{ "movq $dst, $src\t# long stk" %}
6880 opcode(0x89);
6881 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6882 ins_pipe(ialu_mem_reg);
6883 %}
6885 instruct storeSSP(stackSlotP dst, rRegP src)
6886 %{
6887 match(Set dst src);
6889 ins_cost(100);
6890 format %{ "movq $dst, $src\t# ptr stk" %}
6891 opcode(0x89);
6892 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6893 ins_pipe(ialu_mem_reg);
6894 %}
6896 instruct storeSSF(stackSlotF dst, regF src)
6897 %{
6898 match(Set dst src);
6900 ins_cost(95); // XXX
6901 format %{ "movss $dst, $src\t# float stk" %}
6902 opcode(0xF3, 0x0F, 0x11);
6903 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
6904 ins_pipe(pipe_slow); // XXX
6905 %}
6907 instruct storeSSD(stackSlotD dst, regD src)
6908 %{
6909 match(Set dst src);
6911 ins_cost(95); // XXX
6912 format %{ "movsd $dst, $src\t# double stk" %}
6913 opcode(0xF2, 0x0F, 0x11);
6914 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
6915 ins_pipe(pipe_slow); // XXX
6916 %}
6918 //----------BSWAP Instructions-------------------------------------------------
6919 instruct bytes_reverse_int(rRegI dst) %{
6920 match(Set dst (ReverseBytesI dst));
6922 format %{ "bswapl $dst" %}
6923 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6924 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6925 ins_pipe( ialu_reg );
6926 %}
6928 instruct bytes_reverse_long(rRegL dst) %{
6929 match(Set dst (ReverseBytesL dst));
6931 format %{ "bswapq $dst" %}
6933 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6934 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6935 ins_pipe( ialu_reg);
6936 %}
6938 instruct loadI_reversed(rRegI dst, memory src) %{
6939 match(Set dst (ReverseBytesI (LoadI src)));
6941 format %{ "bswap_movl $dst, $src" %}
6942 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
6943 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst));
6944 ins_pipe( ialu_reg_mem );
6945 %}
6947 instruct loadL_reversed(rRegL dst, memory src) %{
6948 match(Set dst (ReverseBytesL (LoadL src)));
6950 format %{ "bswap_movq $dst, $src" %}
6951 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
6952 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst));
6953 ins_pipe( ialu_reg_mem );
6954 %}
6956 instruct storeI_reversed(memory dst, rRegI src) %{
6957 match(Set dst (StoreI dst (ReverseBytesI src)));
6959 format %{ "movl_bswap $dst, $src" %}
6960 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
6961 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
6962 ins_pipe( ialu_mem_reg );
6963 %}
6965 instruct storeL_reversed(memory dst, rRegL src) %{
6966 match(Set dst (StoreL dst (ReverseBytesL src)));
6968 format %{ "movq_bswap $dst, $src" %}
6969 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
6970 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
6971 ins_pipe( ialu_mem_reg );
6972 %}
6974 //----------MemBar Instructions-----------------------------------------------
6975 // Memory barrier flavors
6977 instruct membar_acquire()
6978 %{
6979 match(MemBarAcquire);
6980 ins_cost(0);
6982 size(0);
6983 format %{ "MEMBAR-acquire" %}
6984 ins_encode();
6985 ins_pipe(empty);
6986 %}
6988 instruct membar_acquire_lock()
6989 %{
6990 match(MemBarAcquire);
6991 predicate(Matcher::prior_fast_lock(n));
6992 ins_cost(0);
6994 size(0);
6995 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6996 ins_encode();
6997 ins_pipe(empty);
6998 %}
7000 instruct membar_release()
7001 %{
7002 match(MemBarRelease);
7003 ins_cost(0);
7005 size(0);
7006 format %{ "MEMBAR-release" %}
7007 ins_encode();
7008 ins_pipe(empty);
7009 %}
7011 instruct membar_release_lock()
7012 %{
7013 match(MemBarRelease);
7014 predicate(Matcher::post_fast_unlock(n));
7015 ins_cost(0);
7017 size(0);
7018 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7019 ins_encode();
7020 ins_pipe(empty);
7021 %}
7023 instruct membar_volatile()
7024 %{
7025 match(MemBarVolatile);
7026 ins_cost(400);
7028 format %{ "MEMBAR-volatile" %}
7029 ins_encode(enc_membar_volatile);
7030 ins_pipe(pipe_slow);
7031 %}
7033 instruct unnecessary_membar_volatile()
7034 %{
7035 match(MemBarVolatile);
7036 predicate(Matcher::post_store_load_barrier(n));
7037 ins_cost(0);
7039 size(0);
7040 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7041 ins_encode();
7042 ins_pipe(empty);
7043 %}
7045 //----------Move Instructions--------------------------------------------------
7047 instruct castX2P(rRegP dst, rRegL src)
7048 %{
7049 match(Set dst (CastX2P src));
7051 format %{ "movq $dst, $src\t# long->ptr" %}
7052 ins_encode(enc_copy_wide(dst, src));
7053 ins_pipe(ialu_reg_reg); // XXX
7054 %}
7056 instruct castP2X(rRegL dst, rRegP src)
7057 %{
7058 match(Set dst (CastP2X src));
7060 format %{ "movq $dst, $src\t# ptr -> long" %}
7061 ins_encode(enc_copy_wide(dst, src));
7062 ins_pipe(ialu_reg_reg); // XXX
7063 %}
7066 // Convert oop pointer into compressed form
7067 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
7068 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
7069 match(Set dst (EncodeP src));
7070 effect(KILL cr);
7071 format %{ "encode_heap_oop $dst,$src" %}
7072 ins_encode %{
7073 Register s = $src$$Register;
7074 Register d = $dst$$Register;
7075 if (s != d) {
7076 __ movq(d, s);
7077 }
7078 __ encode_heap_oop(d);
7079 %}
7080 ins_pipe(ialu_reg_long);
7081 %}
7083 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7084 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
7085 match(Set dst (EncodeP src));
7086 effect(KILL cr);
7087 format %{ "encode_heap_oop_not_null $dst,$src" %}
7088 ins_encode %{
7089 Register s = $src$$Register;
7090 Register d = $dst$$Register;
7091 __ encode_heap_oop_not_null(d, s);
7092 %}
7093 ins_pipe(ialu_reg_long);
7094 %}
7096 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7097 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
7098 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
7099 match(Set dst (DecodeN src));
7100 effect(KILL cr);
7101 format %{ "decode_heap_oop $dst,$src" %}
7102 ins_encode %{
7103 Register s = $src$$Register;
7104 Register d = $dst$$Register;
7105 if (s != d) {
7106 __ movq(d, s);
7107 }
7108 __ decode_heap_oop(d);
7109 %}
7110 ins_pipe(ialu_reg_long);
7111 %}
7113 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{
7114 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
7115 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
7116 match(Set dst (DecodeN src));
7117 format %{ "decode_heap_oop_not_null $dst,$src" %}
7118 ins_encode %{
7119 Register s = $src$$Register;
7120 Register d = $dst$$Register;
7121 __ decode_heap_oop_not_null(d, s);
7122 %}
7123 ins_pipe(ialu_reg_long);
7124 %}
7127 //----------Conditional Move---------------------------------------------------
7128 // Jump
7129 // dummy instruction for generating temp registers
7130 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7131 match(Jump (LShiftL switch_val shift));
7132 ins_cost(350);
7133 predicate(false);
7134 effect(TEMP dest);
7136 format %{ "leaq $dest, table_base\n\t"
7137 "jmp [$dest + $switch_val << $shift]\n\t" %}
7138 ins_encode(jump_enc_offset(switch_val, shift, dest));
7139 ins_pipe(pipe_jmp);
7140 ins_pc_relative(1);
7141 %}
7143 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7144 match(Jump (AddL (LShiftL switch_val shift) offset));
7145 ins_cost(350);
7146 effect(TEMP dest);
7148 format %{ "leaq $dest, table_base\n\t"
7149 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7150 ins_encode(jump_enc_addr(switch_val, shift, offset, dest));
7151 ins_pipe(pipe_jmp);
7152 ins_pc_relative(1);
7153 %}
7155 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7156 match(Jump switch_val);
7157 ins_cost(350);
7158 effect(TEMP dest);
7160 format %{ "leaq $dest, table_base\n\t"
7161 "jmp [$dest + $switch_val]\n\t" %}
7162 ins_encode(jump_enc(switch_val, dest));
7163 ins_pipe(pipe_jmp);
7164 ins_pc_relative(1);
7165 %}
7167 // Conditional move
7168 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7169 %{
7170 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7172 ins_cost(200); // XXX
7173 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7174 opcode(0x0F, 0x40);
7175 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7176 ins_pipe(pipe_cmov_reg);
7177 %}
7179 instruct cmovI_regU(rRegI dst, rRegI src, rFlagsRegU cr, cmpOpU cop)
7180 %{
7181 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7183 ins_cost(200); // XXX
7184 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7185 opcode(0x0F, 0x40);
7186 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7187 ins_pipe(pipe_cmov_reg);
7188 %}
7190 // Conditional move
7191 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src)
7192 %{
7193 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7195 ins_cost(250); // XXX
7196 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7197 opcode(0x0F, 0x40);
7198 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7199 ins_pipe(pipe_cmov_mem);
7200 %}
7202 // Conditional move
7203 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7204 %{
7205 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7207 ins_cost(250); // XXX
7208 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7209 opcode(0x0F, 0x40);
7210 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7211 ins_pipe(pipe_cmov_mem);
7212 %}
7214 // Conditional move
7215 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7216 %{
7217 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7219 ins_cost(200); // XXX
7220 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7221 opcode(0x0F, 0x40);
7222 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7223 ins_pipe(pipe_cmov_reg);
7224 %}
7226 // Conditional move
7227 instruct cmovN_regU(rRegN dst, rRegN src, rFlagsRegU cr, cmpOpU cop)
7228 %{
7229 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7231 ins_cost(200); // XXX
7232 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7233 opcode(0x0F, 0x40);
7234 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7235 ins_pipe(pipe_cmov_reg);
7236 %}
7238 // Conditional move
7239 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7240 %{
7241 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7243 ins_cost(200); // XXX
7244 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7245 opcode(0x0F, 0x40);
7246 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7247 ins_pipe(pipe_cmov_reg); // XXX
7248 %}
7250 // Conditional move
7251 instruct cmovP_regU(rRegP dst, rRegP src, rFlagsRegU cr, cmpOpU cop)
7252 %{
7253 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7255 ins_cost(200); // XXX
7256 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7257 opcode(0x0F, 0x40);
7258 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7259 ins_pipe(pipe_cmov_reg); // XXX
7260 %}
7262 // DISABLED: Requires the ADLC to emit a bottom_type call that
7263 // correctly meets the two pointer arguments; one is an incoming
7264 // register but the other is a memory operand. ALSO appears to
7265 // be buggy with implicit null checks.
7266 //
7267 //// Conditional move
7268 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7269 //%{
7270 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7271 // ins_cost(250);
7272 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7273 // opcode(0x0F,0x40);
7274 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7275 // ins_pipe( pipe_cmov_mem );
7276 //%}
7277 //
7278 //// Conditional move
7279 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7280 //%{
7281 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7282 // ins_cost(250);
7283 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7284 // opcode(0x0F,0x40);
7285 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7286 // ins_pipe( pipe_cmov_mem );
7287 //%}
7289 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7290 %{
7291 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7293 ins_cost(200); // XXX
7294 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7295 opcode(0x0F, 0x40);
7296 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7297 ins_pipe(pipe_cmov_reg); // XXX
7298 %}
7300 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7301 %{
7302 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7304 ins_cost(200); // XXX
7305 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7306 opcode(0x0F, 0x40);
7307 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7308 ins_pipe(pipe_cmov_mem); // XXX
7309 %}
7311 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7312 %{
7313 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7315 ins_cost(200); // XXX
7316 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7317 opcode(0x0F, 0x40);
7318 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7319 ins_pipe(pipe_cmov_reg); // XXX
7320 %}
7322 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7323 %{
7324 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7326 ins_cost(200); // XXX
7327 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7328 opcode(0x0F, 0x40);
7329 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7330 ins_pipe(pipe_cmov_mem); // XXX
7331 %}
7333 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7334 %{
7335 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7337 ins_cost(200); // XXX
7338 format %{ "jn$cop skip\t# signed cmove float\n\t"
7339 "movss $dst, $src\n"
7340 "skip:" %}
7341 ins_encode(enc_cmovf_branch(cop, dst, src));
7342 ins_pipe(pipe_slow);
7343 %}
7345 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7346 // %{
7347 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7349 // ins_cost(200); // XXX
7350 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7351 // "movss $dst, $src\n"
7352 // "skip:" %}
7353 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7354 // ins_pipe(pipe_slow);
7355 // %}
7357 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7358 %{
7359 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7361 ins_cost(200); // XXX
7362 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7363 "movss $dst, $src\n"
7364 "skip:" %}
7365 ins_encode(enc_cmovf_branch(cop, dst, src));
7366 ins_pipe(pipe_slow);
7367 %}
7369 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7370 %{
7371 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7373 ins_cost(200); // XXX
7374 format %{ "jn$cop skip\t# signed cmove double\n\t"
7375 "movsd $dst, $src\n"
7376 "skip:" %}
7377 ins_encode(enc_cmovd_branch(cop, dst, src));
7378 ins_pipe(pipe_slow);
7379 %}
7381 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7382 %{
7383 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7385 ins_cost(200); // XXX
7386 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7387 "movsd $dst, $src\n"
7388 "skip:" %}
7389 ins_encode(enc_cmovd_branch(cop, dst, src));
7390 ins_pipe(pipe_slow);
7391 %}
7393 //----------Arithmetic Instructions--------------------------------------------
7394 //----------Addition Instructions----------------------------------------------
7396 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7397 %{
7398 match(Set dst (AddI dst src));
7399 effect(KILL cr);
7401 format %{ "addl $dst, $src\t# int" %}
7402 opcode(0x03);
7403 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7404 ins_pipe(ialu_reg_reg);
7405 %}
7407 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7408 %{
7409 match(Set dst (AddI dst src));
7410 effect(KILL cr);
7412 format %{ "addl $dst, $src\t# int" %}
7413 opcode(0x81, 0x00); /* /0 id */
7414 ins_encode(OpcSErm(dst, src), Con8or32(src));
7415 ins_pipe( ialu_reg );
7416 %}
7418 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7419 %{
7420 match(Set dst (AddI dst (LoadI src)));
7421 effect(KILL cr);
7423 ins_cost(125); // XXX
7424 format %{ "addl $dst, $src\t# int" %}
7425 opcode(0x03);
7426 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7427 ins_pipe(ialu_reg_mem);
7428 %}
7430 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7431 %{
7432 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7433 effect(KILL cr);
7435 ins_cost(150); // XXX
7436 format %{ "addl $dst, $src\t# int" %}
7437 opcode(0x01); /* Opcode 01 /r */
7438 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7439 ins_pipe(ialu_mem_reg);
7440 %}
7442 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7443 %{
7444 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7445 effect(KILL cr);
7447 ins_cost(125); // XXX
7448 format %{ "addl $dst, $src\t# int" %}
7449 opcode(0x81); /* Opcode 81 /0 id */
7450 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7451 ins_pipe(ialu_mem_imm);
7452 %}
7454 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7455 %{
7456 predicate(UseIncDec);
7457 match(Set dst (AddI dst src));
7458 effect(KILL cr);
7460 format %{ "incl $dst\t# int" %}
7461 opcode(0xFF, 0x00); // FF /0
7462 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7463 ins_pipe(ialu_reg);
7464 %}
7466 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7467 %{
7468 predicate(UseIncDec);
7469 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7470 effect(KILL cr);
7472 ins_cost(125); // XXX
7473 format %{ "incl $dst\t# int" %}
7474 opcode(0xFF); /* Opcode FF /0 */
7475 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7476 ins_pipe(ialu_mem_imm);
7477 %}
7479 // XXX why does that use AddI
7480 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7481 %{
7482 predicate(UseIncDec);
7483 match(Set dst (AddI dst src));
7484 effect(KILL cr);
7486 format %{ "decl $dst\t# int" %}
7487 opcode(0xFF, 0x01); // FF /1
7488 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7489 ins_pipe(ialu_reg);
7490 %}
7492 // XXX why does that use AddI
7493 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7494 %{
7495 predicate(UseIncDec);
7496 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7497 effect(KILL cr);
7499 ins_cost(125); // XXX
7500 format %{ "decl $dst\t# int" %}
7501 opcode(0xFF); /* Opcode FF /1 */
7502 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7503 ins_pipe(ialu_mem_imm);
7504 %}
7506 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7507 %{
7508 match(Set dst (AddI src0 src1));
7510 ins_cost(110);
7511 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7512 opcode(0x8D); /* 0x8D /r */
7513 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7514 ins_pipe(ialu_reg_reg);
7515 %}
7517 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7518 %{
7519 match(Set dst (AddL dst src));
7520 effect(KILL cr);
7522 format %{ "addq $dst, $src\t# long" %}
7523 opcode(0x03);
7524 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7525 ins_pipe(ialu_reg_reg);
7526 %}
7528 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7529 %{
7530 match(Set dst (AddL dst src));
7531 effect(KILL cr);
7533 format %{ "addq $dst, $src\t# long" %}
7534 opcode(0x81, 0x00); /* /0 id */
7535 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7536 ins_pipe( ialu_reg );
7537 %}
7539 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7540 %{
7541 match(Set dst (AddL dst (LoadL src)));
7542 effect(KILL cr);
7544 ins_cost(125); // XXX
7545 format %{ "addq $dst, $src\t# long" %}
7546 opcode(0x03);
7547 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7548 ins_pipe(ialu_reg_mem);
7549 %}
7551 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7552 %{
7553 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7554 effect(KILL cr);
7556 ins_cost(150); // XXX
7557 format %{ "addq $dst, $src\t# long" %}
7558 opcode(0x01); /* Opcode 01 /r */
7559 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7560 ins_pipe(ialu_mem_reg);
7561 %}
7563 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7564 %{
7565 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7566 effect(KILL cr);
7568 ins_cost(125); // XXX
7569 format %{ "addq $dst, $src\t# long" %}
7570 opcode(0x81); /* Opcode 81 /0 id */
7571 ins_encode(REX_mem_wide(dst),
7572 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7573 ins_pipe(ialu_mem_imm);
7574 %}
7576 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7577 %{
7578 predicate(UseIncDec);
7579 match(Set dst (AddL dst src));
7580 effect(KILL cr);
7582 format %{ "incq $dst\t# long" %}
7583 opcode(0xFF, 0x00); // FF /0
7584 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7585 ins_pipe(ialu_reg);
7586 %}
7588 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7589 %{
7590 predicate(UseIncDec);
7591 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7592 effect(KILL cr);
7594 ins_cost(125); // XXX
7595 format %{ "incq $dst\t# long" %}
7596 opcode(0xFF); /* Opcode FF /0 */
7597 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7598 ins_pipe(ialu_mem_imm);
7599 %}
7601 // XXX why does that use AddL
7602 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7603 %{
7604 predicate(UseIncDec);
7605 match(Set dst (AddL dst src));
7606 effect(KILL cr);
7608 format %{ "decq $dst\t# long" %}
7609 opcode(0xFF, 0x01); // FF /1
7610 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7611 ins_pipe(ialu_reg);
7612 %}
7614 // XXX why does that use AddL
7615 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7616 %{
7617 predicate(UseIncDec);
7618 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7619 effect(KILL cr);
7621 ins_cost(125); // XXX
7622 format %{ "decq $dst\t# long" %}
7623 opcode(0xFF); /* Opcode FF /1 */
7624 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7625 ins_pipe(ialu_mem_imm);
7626 %}
7628 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7629 %{
7630 match(Set dst (AddL src0 src1));
7632 ins_cost(110);
7633 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7634 opcode(0x8D); /* 0x8D /r */
7635 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7636 ins_pipe(ialu_reg_reg);
7637 %}
7639 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7640 %{
7641 match(Set dst (AddP dst src));
7642 effect(KILL cr);
7644 format %{ "addq $dst, $src\t# ptr" %}
7645 opcode(0x03);
7646 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7647 ins_pipe(ialu_reg_reg);
7648 %}
7650 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7651 %{
7652 match(Set dst (AddP dst src));
7653 effect(KILL cr);
7655 format %{ "addq $dst, $src\t# ptr" %}
7656 opcode(0x81, 0x00); /* /0 id */
7657 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7658 ins_pipe( ialu_reg );
7659 %}
7661 // XXX addP mem ops ????
7663 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7664 %{
7665 match(Set dst (AddP src0 src1));
7667 ins_cost(110);
7668 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7669 opcode(0x8D); /* 0x8D /r */
7670 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7671 ins_pipe(ialu_reg_reg);
7672 %}
7674 instruct checkCastPP(rRegP dst)
7675 %{
7676 match(Set dst (CheckCastPP dst));
7678 size(0);
7679 format %{ "# checkcastPP of $dst" %}
7680 ins_encode(/* empty encoding */);
7681 ins_pipe(empty);
7682 %}
7684 instruct castPP(rRegP dst)
7685 %{
7686 match(Set dst (CastPP dst));
7688 size(0);
7689 format %{ "# castPP of $dst" %}
7690 ins_encode(/* empty encoding */);
7691 ins_pipe(empty);
7692 %}
7694 instruct castII(rRegI dst)
7695 %{
7696 match(Set dst (CastII dst));
7698 size(0);
7699 format %{ "# castII of $dst" %}
7700 ins_encode(/* empty encoding */);
7701 ins_cost(0);
7702 ins_pipe(empty);
7703 %}
7705 // LoadP-locked same as a regular LoadP when used with compare-swap
7706 instruct loadPLocked(rRegP dst, memory mem)
7707 %{
7708 match(Set dst (LoadPLocked mem));
7710 ins_cost(125); // XXX
7711 format %{ "movq $dst, $mem\t# ptr locked" %}
7712 opcode(0x8B);
7713 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7714 ins_pipe(ialu_reg_mem); // XXX
7715 %}
7717 // LoadL-locked - same as a regular LoadL when used with compare-swap
7718 instruct loadLLocked(rRegL dst, memory mem)
7719 %{
7720 match(Set dst (LoadLLocked mem));
7722 ins_cost(125); // XXX
7723 format %{ "movq $dst, $mem\t# long locked" %}
7724 opcode(0x8B);
7725 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7726 ins_pipe(ialu_reg_mem); // XXX
7727 %}
7729 // Conditional-store of the updated heap-top.
7730 // Used during allocation of the shared heap.
7731 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7733 instruct storePConditional(memory heap_top_ptr,
7734 rax_RegP oldval, rRegP newval,
7735 rFlagsReg cr)
7736 %{
7737 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7739 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7740 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7741 opcode(0x0F, 0xB1);
7742 ins_encode(lock_prefix,
7743 REX_reg_mem_wide(newval, heap_top_ptr),
7744 OpcP, OpcS,
7745 reg_mem(newval, heap_top_ptr));
7746 ins_pipe(pipe_cmpxchg);
7747 %}
7749 // Conditional-store of a long value
7750 // Returns a boolean value (0/1) on success. Implemented with a
7751 // CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI
7753 instruct storeLConditional(rRegI res,
7754 memory mem_ptr,
7755 rax_RegL oldval, rRegL newval,
7756 rFlagsReg cr)
7757 %{
7758 match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
7759 effect(KILL cr);
7761 format %{ "cmpxchgq $mem_ptr, $newval\t# (long) "
7762 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7763 "sete $res\n\t"
7764 "movzbl $res, $res" %}
7765 opcode(0x0F, 0xB1);
7766 ins_encode(lock_prefix,
7767 REX_reg_mem_wide(newval, mem_ptr),
7768 OpcP, OpcS,
7769 reg_mem(newval, mem_ptr),
7770 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7771 REX_reg_breg(res, res), // movzbl
7772 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7773 ins_pipe(pipe_cmpxchg);
7774 %}
7776 // Conditional-store of a long value
7777 // ZF flag is set on success, reset otherwise. Implemented with a
7778 // CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI
7779 instruct storeLConditional_flags(memory mem_ptr,
7780 rax_RegL oldval, rRegL newval,
7781 rFlagsReg cr,
7782 immI0 zero)
7783 %{
7784 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
7786 format %{ "cmpxchgq $mem_ptr, $newval\t# (long) "
7787 "If rax == $mem_ptr then store $newval into $mem_ptr" %}
7788 opcode(0x0F, 0xB1);
7789 ins_encode(lock_prefix,
7790 REX_reg_mem_wide(newval, mem_ptr),
7791 OpcP, OpcS,
7792 reg_mem(newval, mem_ptr));
7793 ins_pipe(pipe_cmpxchg);
7794 %}
7796 instruct compareAndSwapP(rRegI res,
7797 memory mem_ptr,
7798 rax_RegP oldval, rRegP newval,
7799 rFlagsReg cr)
7800 %{
7801 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7802 effect(KILL cr, KILL oldval);
7804 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7805 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7806 "sete $res\n\t"
7807 "movzbl $res, $res" %}
7808 opcode(0x0F, 0xB1);
7809 ins_encode(lock_prefix,
7810 REX_reg_mem_wide(newval, mem_ptr),
7811 OpcP, OpcS,
7812 reg_mem(newval, mem_ptr),
7813 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7814 REX_reg_breg(res, res), // movzbl
7815 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7816 ins_pipe( pipe_cmpxchg );
7817 %}
7819 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7820 instruct compareAndSwapL(rRegI res,
7821 memory mem_ptr,
7822 rax_RegL oldval, rRegL newval,
7823 rFlagsReg cr)
7824 %{
7825 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7826 effect(KILL cr, KILL oldval);
7828 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7829 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7830 "sete $res\n\t"
7831 "movzbl $res, $res" %}
7832 opcode(0x0F, 0xB1);
7833 ins_encode(lock_prefix,
7834 REX_reg_mem_wide(newval, mem_ptr),
7835 OpcP, OpcS,
7836 reg_mem(newval, mem_ptr),
7837 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7838 REX_reg_breg(res, res), // movzbl
7839 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7840 ins_pipe( pipe_cmpxchg );
7841 %}
7843 instruct compareAndSwapI(rRegI res,
7844 memory mem_ptr,
7845 rax_RegI oldval, rRegI newval,
7846 rFlagsReg cr)
7847 %{
7848 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7849 effect(KILL cr, KILL oldval);
7851 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7852 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7853 "sete $res\n\t"
7854 "movzbl $res, $res" %}
7855 opcode(0x0F, 0xB1);
7856 ins_encode(lock_prefix,
7857 REX_reg_mem(newval, mem_ptr),
7858 OpcP, OpcS,
7859 reg_mem(newval, mem_ptr),
7860 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7861 REX_reg_breg(res, res), // movzbl
7862 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7863 ins_pipe( pipe_cmpxchg );
7864 %}
7867 instruct compareAndSwapN(rRegI res,
7868 memory mem_ptr,
7869 rax_RegN oldval, rRegN newval,
7870 rFlagsReg cr) %{
7871 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7872 effect(KILL cr, KILL oldval);
7874 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7875 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7876 "sete $res\n\t"
7877 "movzbl $res, $res" %}
7878 opcode(0x0F, 0xB1);
7879 ins_encode(lock_prefix,
7880 REX_reg_mem(newval, mem_ptr),
7881 OpcP, OpcS,
7882 reg_mem(newval, mem_ptr),
7883 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7884 REX_reg_breg(res, res), // movzbl
7885 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7886 ins_pipe( pipe_cmpxchg );
7887 %}
7889 //----------Subtraction Instructions-------------------------------------------
7891 // Integer Subtraction Instructions
7892 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7893 %{
7894 match(Set dst (SubI dst src));
7895 effect(KILL cr);
7897 format %{ "subl $dst, $src\t# int" %}
7898 opcode(0x2B);
7899 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7900 ins_pipe(ialu_reg_reg);
7901 %}
7903 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7904 %{
7905 match(Set dst (SubI dst src));
7906 effect(KILL cr);
7908 format %{ "subl $dst, $src\t# int" %}
7909 opcode(0x81, 0x05); /* Opcode 81 /5 */
7910 ins_encode(OpcSErm(dst, src), Con8or32(src));
7911 ins_pipe(ialu_reg);
7912 %}
7914 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7915 %{
7916 match(Set dst (SubI dst (LoadI src)));
7917 effect(KILL cr);
7919 ins_cost(125);
7920 format %{ "subl $dst, $src\t# int" %}
7921 opcode(0x2B);
7922 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7923 ins_pipe(ialu_reg_mem);
7924 %}
7926 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7927 %{
7928 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7929 effect(KILL cr);
7931 ins_cost(150);
7932 format %{ "subl $dst, $src\t# int" %}
7933 opcode(0x29); /* Opcode 29 /r */
7934 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7935 ins_pipe(ialu_mem_reg);
7936 %}
7938 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7939 %{
7940 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7941 effect(KILL cr);
7943 ins_cost(125); // XXX
7944 format %{ "subl $dst, $src\t# int" %}
7945 opcode(0x81); /* Opcode 81 /5 id */
7946 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7947 ins_pipe(ialu_mem_imm);
7948 %}
7950 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7951 %{
7952 match(Set dst (SubL dst src));
7953 effect(KILL cr);
7955 format %{ "subq $dst, $src\t# long" %}
7956 opcode(0x2B);
7957 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7958 ins_pipe(ialu_reg_reg);
7959 %}
7961 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7962 %{
7963 match(Set dst (SubL dst src));
7964 effect(KILL cr);
7966 format %{ "subq $dst, $src\t# long" %}
7967 opcode(0x81, 0x05); /* Opcode 81 /5 */
7968 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7969 ins_pipe(ialu_reg);
7970 %}
7972 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7973 %{
7974 match(Set dst (SubL dst (LoadL src)));
7975 effect(KILL cr);
7977 ins_cost(125);
7978 format %{ "subq $dst, $src\t# long" %}
7979 opcode(0x2B);
7980 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7981 ins_pipe(ialu_reg_mem);
7982 %}
7984 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7985 %{
7986 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7987 effect(KILL cr);
7989 ins_cost(150);
7990 format %{ "subq $dst, $src\t# long" %}
7991 opcode(0x29); /* Opcode 29 /r */
7992 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7993 ins_pipe(ialu_mem_reg);
7994 %}
7996 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7997 %{
7998 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7999 effect(KILL cr);
8001 ins_cost(125); // XXX
8002 format %{ "subq $dst, $src\t# long" %}
8003 opcode(0x81); /* Opcode 81 /5 id */
8004 ins_encode(REX_mem_wide(dst),
8005 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8006 ins_pipe(ialu_mem_imm);
8007 %}
8009 // Subtract from a pointer
8010 // XXX hmpf???
8011 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8012 %{
8013 match(Set dst (AddP dst (SubI zero src)));
8014 effect(KILL cr);
8016 format %{ "subq $dst, $src\t# ptr - int" %}
8017 opcode(0x2B);
8018 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8019 ins_pipe(ialu_reg_reg);
8020 %}
8022 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8023 %{
8024 match(Set dst (SubI zero dst));
8025 effect(KILL cr);
8027 format %{ "negl $dst\t# int" %}
8028 opcode(0xF7, 0x03); // Opcode F7 /3
8029 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8030 ins_pipe(ialu_reg);
8031 %}
8033 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8034 %{
8035 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8036 effect(KILL cr);
8038 format %{ "negl $dst\t# int" %}
8039 opcode(0xF7, 0x03); // Opcode F7 /3
8040 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8041 ins_pipe(ialu_reg);
8042 %}
8044 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8045 %{
8046 match(Set dst (SubL zero dst));
8047 effect(KILL cr);
8049 format %{ "negq $dst\t# long" %}
8050 opcode(0xF7, 0x03); // Opcode F7 /3
8051 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8052 ins_pipe(ialu_reg);
8053 %}
8055 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8056 %{
8057 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8058 effect(KILL cr);
8060 format %{ "negq $dst\t# long" %}
8061 opcode(0xF7, 0x03); // Opcode F7 /3
8062 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8063 ins_pipe(ialu_reg);
8064 %}
8067 //----------Multiplication/Division Instructions-------------------------------
8068 // Integer Multiplication Instructions
8069 // Multiply Register
8071 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8072 %{
8073 match(Set dst (MulI dst src));
8074 effect(KILL cr);
8076 ins_cost(300);
8077 format %{ "imull $dst, $src\t# int" %}
8078 opcode(0x0F, 0xAF);
8079 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8080 ins_pipe(ialu_reg_reg_alu0);
8081 %}
8083 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8084 %{
8085 match(Set dst (MulI src imm));
8086 effect(KILL cr);
8088 ins_cost(300);
8089 format %{ "imull $dst, $src, $imm\t# int" %}
8090 opcode(0x69); /* 69 /r id */
8091 ins_encode(REX_reg_reg(dst, src),
8092 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8093 ins_pipe(ialu_reg_reg_alu0);
8094 %}
8096 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8097 %{
8098 match(Set dst (MulI dst (LoadI src)));
8099 effect(KILL cr);
8101 ins_cost(350);
8102 format %{ "imull $dst, $src\t# int" %}
8103 opcode(0x0F, 0xAF);
8104 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8105 ins_pipe(ialu_reg_mem_alu0);
8106 %}
8108 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8109 %{
8110 match(Set dst (MulI (LoadI src) imm));
8111 effect(KILL cr);
8113 ins_cost(300);
8114 format %{ "imull $dst, $src, $imm\t# int" %}
8115 opcode(0x69); /* 69 /r id */
8116 ins_encode(REX_reg_mem(dst, src),
8117 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8118 ins_pipe(ialu_reg_mem_alu0);
8119 %}
8121 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8122 %{
8123 match(Set dst (MulL dst src));
8124 effect(KILL cr);
8126 ins_cost(300);
8127 format %{ "imulq $dst, $src\t# long" %}
8128 opcode(0x0F, 0xAF);
8129 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8130 ins_pipe(ialu_reg_reg_alu0);
8131 %}
8133 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8134 %{
8135 match(Set dst (MulL src imm));
8136 effect(KILL cr);
8138 ins_cost(300);
8139 format %{ "imulq $dst, $src, $imm\t# long" %}
8140 opcode(0x69); /* 69 /r id */
8141 ins_encode(REX_reg_reg_wide(dst, src),
8142 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8143 ins_pipe(ialu_reg_reg_alu0);
8144 %}
8146 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8147 %{
8148 match(Set dst (MulL dst (LoadL src)));
8149 effect(KILL cr);
8151 ins_cost(350);
8152 format %{ "imulq $dst, $src\t# long" %}
8153 opcode(0x0F, 0xAF);
8154 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8155 ins_pipe(ialu_reg_mem_alu0);
8156 %}
8158 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8159 %{
8160 match(Set dst (MulL (LoadL src) imm));
8161 effect(KILL cr);
8163 ins_cost(300);
8164 format %{ "imulq $dst, $src, $imm\t# long" %}
8165 opcode(0x69); /* 69 /r id */
8166 ins_encode(REX_reg_mem_wide(dst, src),
8167 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8168 ins_pipe(ialu_reg_mem_alu0);
8169 %}
8171 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8172 %{
8173 match(Set dst (MulHiL src rax));
8174 effect(USE_KILL rax, KILL cr);
8176 ins_cost(300);
8177 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8178 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8179 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8180 ins_pipe(ialu_reg_reg_alu0);
8181 %}
8183 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8184 rFlagsReg cr)
8185 %{
8186 match(Set rax (DivI rax div));
8187 effect(KILL rdx, KILL cr);
8189 ins_cost(30*100+10*100); // XXX
8190 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8191 "jne,s normal\n\t"
8192 "xorl rdx, rdx\n\t"
8193 "cmpl $div, -1\n\t"
8194 "je,s done\n"
8195 "normal: cdql\n\t"
8196 "idivl $div\n"
8197 "done:" %}
8198 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8199 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8200 ins_pipe(ialu_reg_reg_alu0);
8201 %}
8203 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8204 rFlagsReg cr)
8205 %{
8206 match(Set rax (DivL rax div));
8207 effect(KILL rdx, KILL cr);
8209 ins_cost(30*100+10*100); // XXX
8210 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8211 "cmpq rax, rdx\n\t"
8212 "jne,s normal\n\t"
8213 "xorl rdx, rdx\n\t"
8214 "cmpq $div, -1\n\t"
8215 "je,s done\n"
8216 "normal: cdqq\n\t"
8217 "idivq $div\n"
8218 "done:" %}
8219 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8220 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8221 ins_pipe(ialu_reg_reg_alu0);
8222 %}
8224 // Integer DIVMOD with Register, both quotient and mod results
8225 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8226 rFlagsReg cr)
8227 %{
8228 match(DivModI rax div);
8229 effect(KILL cr);
8231 ins_cost(30*100+10*100); // XXX
8232 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8233 "jne,s normal\n\t"
8234 "xorl rdx, rdx\n\t"
8235 "cmpl $div, -1\n\t"
8236 "je,s done\n"
8237 "normal: cdql\n\t"
8238 "idivl $div\n"
8239 "done:" %}
8240 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8241 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8242 ins_pipe(pipe_slow);
8243 %}
8245 // Long DIVMOD with Register, both quotient and mod results
8246 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8247 rFlagsReg cr)
8248 %{
8249 match(DivModL rax div);
8250 effect(KILL cr);
8252 ins_cost(30*100+10*100); // XXX
8253 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8254 "cmpq rax, rdx\n\t"
8255 "jne,s normal\n\t"
8256 "xorl rdx, rdx\n\t"
8257 "cmpq $div, -1\n\t"
8258 "je,s done\n"
8259 "normal: cdqq\n\t"
8260 "idivq $div\n"
8261 "done:" %}
8262 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8263 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8264 ins_pipe(pipe_slow);
8265 %}
8267 //----------- DivL-By-Constant-Expansions--------------------------------------
8268 // DivI cases are handled by the compiler
8270 // Magic constant, reciprical of 10
8271 instruct loadConL_0x6666666666666667(rRegL dst)
8272 %{
8273 effect(DEF dst);
8275 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8276 ins_encode(load_immL(dst, 0x6666666666666667));
8277 ins_pipe(ialu_reg);
8278 %}
8280 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8281 %{
8282 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8284 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8285 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8286 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8287 ins_pipe(ialu_reg_reg_alu0);
8288 %}
8290 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8291 %{
8292 effect(USE_DEF dst, KILL cr);
8294 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8295 opcode(0xC1, 0x7); /* C1 /7 ib */
8296 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8297 ins_pipe(ialu_reg);
8298 %}
8300 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8301 %{
8302 effect(USE_DEF dst, KILL cr);
8304 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8305 opcode(0xC1, 0x7); /* C1 /7 ib */
8306 ins_encode(reg_opc_imm_wide(dst, 0x2));
8307 ins_pipe(ialu_reg);
8308 %}
8310 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8311 %{
8312 match(Set dst (DivL src div));
8314 ins_cost((5+8)*100);
8315 expand %{
8316 rax_RegL rax; // Killed temp
8317 rFlagsReg cr; // Killed
8318 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8319 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8320 sarL_rReg_63(src, cr); // sarq src, 63
8321 sarL_rReg_2(dst, cr); // sarq rdx, 2
8322 subL_rReg(dst, src, cr); // subl rdx, src
8323 %}
8324 %}
8326 //-----------------------------------------------------------------------------
8328 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8329 rFlagsReg cr)
8330 %{
8331 match(Set rdx (ModI rax div));
8332 effect(KILL rax, KILL cr);
8334 ins_cost(300); // XXX
8335 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8336 "jne,s normal\n\t"
8337 "xorl rdx, rdx\n\t"
8338 "cmpl $div, -1\n\t"
8339 "je,s done\n"
8340 "normal: cdql\n\t"
8341 "idivl $div\n"
8342 "done:" %}
8343 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8344 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8345 ins_pipe(ialu_reg_reg_alu0);
8346 %}
8348 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8349 rFlagsReg cr)
8350 %{
8351 match(Set rdx (ModL rax div));
8352 effect(KILL rax, KILL cr);
8354 ins_cost(300); // XXX
8355 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8356 "cmpq rax, rdx\n\t"
8357 "jne,s normal\n\t"
8358 "xorl rdx, rdx\n\t"
8359 "cmpq $div, -1\n\t"
8360 "je,s done\n"
8361 "normal: cdqq\n\t"
8362 "idivq $div\n"
8363 "done:" %}
8364 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8365 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8366 ins_pipe(ialu_reg_reg_alu0);
8367 %}
8369 // Integer Shift Instructions
8370 // Shift Left by one
8371 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8372 %{
8373 match(Set dst (LShiftI dst shift));
8374 effect(KILL cr);
8376 format %{ "sall $dst, $shift" %}
8377 opcode(0xD1, 0x4); /* D1 /4 */
8378 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8379 ins_pipe(ialu_reg);
8380 %}
8382 // Shift Left by one
8383 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8384 %{
8385 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8386 effect(KILL cr);
8388 format %{ "sall $dst, $shift\t" %}
8389 opcode(0xD1, 0x4); /* D1 /4 */
8390 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8391 ins_pipe(ialu_mem_imm);
8392 %}
8394 // Shift Left by 8-bit immediate
8395 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8396 %{
8397 match(Set dst (LShiftI dst shift));
8398 effect(KILL cr);
8400 format %{ "sall $dst, $shift" %}
8401 opcode(0xC1, 0x4); /* C1 /4 ib */
8402 ins_encode(reg_opc_imm(dst, shift));
8403 ins_pipe(ialu_reg);
8404 %}
8406 // Shift Left by 8-bit immediate
8407 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8408 %{
8409 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8410 effect(KILL cr);
8412 format %{ "sall $dst, $shift" %}
8413 opcode(0xC1, 0x4); /* C1 /4 ib */
8414 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8415 ins_pipe(ialu_mem_imm);
8416 %}
8418 // Shift Left by variable
8419 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8420 %{
8421 match(Set dst (LShiftI dst shift));
8422 effect(KILL cr);
8424 format %{ "sall $dst, $shift" %}
8425 opcode(0xD3, 0x4); /* D3 /4 */
8426 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8427 ins_pipe(ialu_reg_reg);
8428 %}
8430 // Shift Left by variable
8431 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8432 %{
8433 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8434 effect(KILL cr);
8436 format %{ "sall $dst, $shift" %}
8437 opcode(0xD3, 0x4); /* D3 /4 */
8438 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8439 ins_pipe(ialu_mem_reg);
8440 %}
8442 // Arithmetic shift right by one
8443 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8444 %{
8445 match(Set dst (RShiftI dst shift));
8446 effect(KILL cr);
8448 format %{ "sarl $dst, $shift" %}
8449 opcode(0xD1, 0x7); /* D1 /7 */
8450 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8451 ins_pipe(ialu_reg);
8452 %}
8454 // Arithmetic shift right by one
8455 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8456 %{
8457 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8458 effect(KILL cr);
8460 format %{ "sarl $dst, $shift" %}
8461 opcode(0xD1, 0x7); /* D1 /7 */
8462 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8463 ins_pipe(ialu_mem_imm);
8464 %}
8466 // Arithmetic Shift Right by 8-bit immediate
8467 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8468 %{
8469 match(Set dst (RShiftI dst shift));
8470 effect(KILL cr);
8472 format %{ "sarl $dst, $shift" %}
8473 opcode(0xC1, 0x7); /* C1 /7 ib */
8474 ins_encode(reg_opc_imm(dst, shift));
8475 ins_pipe(ialu_mem_imm);
8476 %}
8478 // Arithmetic Shift Right by 8-bit immediate
8479 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8480 %{
8481 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8482 effect(KILL cr);
8484 format %{ "sarl $dst, $shift" %}
8485 opcode(0xC1, 0x7); /* C1 /7 ib */
8486 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8487 ins_pipe(ialu_mem_imm);
8488 %}
8490 // Arithmetic Shift Right by variable
8491 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8492 %{
8493 match(Set dst (RShiftI dst shift));
8494 effect(KILL cr);
8496 format %{ "sarl $dst, $shift" %}
8497 opcode(0xD3, 0x7); /* D3 /7 */
8498 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8499 ins_pipe(ialu_reg_reg);
8500 %}
8502 // Arithmetic Shift Right by variable
8503 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8504 %{
8505 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8506 effect(KILL cr);
8508 format %{ "sarl $dst, $shift" %}
8509 opcode(0xD3, 0x7); /* D3 /7 */
8510 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8511 ins_pipe(ialu_mem_reg);
8512 %}
8514 // Logical shift right by one
8515 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8516 %{
8517 match(Set dst (URShiftI dst shift));
8518 effect(KILL cr);
8520 format %{ "shrl $dst, $shift" %}
8521 opcode(0xD1, 0x5); /* D1 /5 */
8522 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8523 ins_pipe(ialu_reg);
8524 %}
8526 // Logical shift right by one
8527 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8528 %{
8529 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8530 effect(KILL cr);
8532 format %{ "shrl $dst, $shift" %}
8533 opcode(0xD1, 0x5); /* D1 /5 */
8534 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8535 ins_pipe(ialu_mem_imm);
8536 %}
8538 // Logical Shift Right by 8-bit immediate
8539 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8540 %{
8541 match(Set dst (URShiftI dst shift));
8542 effect(KILL cr);
8544 format %{ "shrl $dst, $shift" %}
8545 opcode(0xC1, 0x5); /* C1 /5 ib */
8546 ins_encode(reg_opc_imm(dst, shift));
8547 ins_pipe(ialu_reg);
8548 %}
8550 // Logical Shift Right by 8-bit immediate
8551 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8552 %{
8553 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8554 effect(KILL cr);
8556 format %{ "shrl $dst, $shift" %}
8557 opcode(0xC1, 0x5); /* C1 /5 ib */
8558 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8559 ins_pipe(ialu_mem_imm);
8560 %}
8562 // Logical Shift Right by variable
8563 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8564 %{
8565 match(Set dst (URShiftI dst shift));
8566 effect(KILL cr);
8568 format %{ "shrl $dst, $shift" %}
8569 opcode(0xD3, 0x5); /* D3 /5 */
8570 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8571 ins_pipe(ialu_reg_reg);
8572 %}
8574 // Logical Shift Right by variable
8575 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8576 %{
8577 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8578 effect(KILL cr);
8580 format %{ "shrl $dst, $shift" %}
8581 opcode(0xD3, 0x5); /* D3 /5 */
8582 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8583 ins_pipe(ialu_mem_reg);
8584 %}
8586 // Long Shift Instructions
8587 // Shift Left by one
8588 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8589 %{
8590 match(Set dst (LShiftL dst shift));
8591 effect(KILL cr);
8593 format %{ "salq $dst, $shift" %}
8594 opcode(0xD1, 0x4); /* D1 /4 */
8595 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8596 ins_pipe(ialu_reg);
8597 %}
8599 // Shift Left by one
8600 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8601 %{
8602 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8603 effect(KILL cr);
8605 format %{ "salq $dst, $shift" %}
8606 opcode(0xD1, 0x4); /* D1 /4 */
8607 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8608 ins_pipe(ialu_mem_imm);
8609 %}
8611 // Shift Left by 8-bit immediate
8612 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8613 %{
8614 match(Set dst (LShiftL dst shift));
8615 effect(KILL cr);
8617 format %{ "salq $dst, $shift" %}
8618 opcode(0xC1, 0x4); /* C1 /4 ib */
8619 ins_encode(reg_opc_imm_wide(dst, shift));
8620 ins_pipe(ialu_reg);
8621 %}
8623 // Shift Left by 8-bit immediate
8624 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8625 %{
8626 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8627 effect(KILL cr);
8629 format %{ "salq $dst, $shift" %}
8630 opcode(0xC1, 0x4); /* C1 /4 ib */
8631 ins_encode(REX_mem_wide(dst), OpcP,
8632 RM_opc_mem(secondary, dst), Con8or32(shift));
8633 ins_pipe(ialu_mem_imm);
8634 %}
8636 // Shift Left by variable
8637 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8638 %{
8639 match(Set dst (LShiftL dst shift));
8640 effect(KILL cr);
8642 format %{ "salq $dst, $shift" %}
8643 opcode(0xD3, 0x4); /* D3 /4 */
8644 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8645 ins_pipe(ialu_reg_reg);
8646 %}
8648 // Shift Left by variable
8649 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8650 %{
8651 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8652 effect(KILL cr);
8654 format %{ "salq $dst, $shift" %}
8655 opcode(0xD3, 0x4); /* D3 /4 */
8656 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8657 ins_pipe(ialu_mem_reg);
8658 %}
8660 // Arithmetic shift right by one
8661 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8662 %{
8663 match(Set dst (RShiftL dst shift));
8664 effect(KILL cr);
8666 format %{ "sarq $dst, $shift" %}
8667 opcode(0xD1, 0x7); /* D1 /7 */
8668 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8669 ins_pipe(ialu_reg);
8670 %}
8672 // Arithmetic shift right by one
8673 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8674 %{
8675 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8676 effect(KILL cr);
8678 format %{ "sarq $dst, $shift" %}
8679 opcode(0xD1, 0x7); /* D1 /7 */
8680 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8681 ins_pipe(ialu_mem_imm);
8682 %}
8684 // Arithmetic Shift Right by 8-bit immediate
8685 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8686 %{
8687 match(Set dst (RShiftL dst shift));
8688 effect(KILL cr);
8690 format %{ "sarq $dst, $shift" %}
8691 opcode(0xC1, 0x7); /* C1 /7 ib */
8692 ins_encode(reg_opc_imm_wide(dst, shift));
8693 ins_pipe(ialu_mem_imm);
8694 %}
8696 // Arithmetic Shift Right by 8-bit immediate
8697 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8698 %{
8699 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8700 effect(KILL cr);
8702 format %{ "sarq $dst, $shift" %}
8703 opcode(0xC1, 0x7); /* C1 /7 ib */
8704 ins_encode(REX_mem_wide(dst), OpcP,
8705 RM_opc_mem(secondary, dst), Con8or32(shift));
8706 ins_pipe(ialu_mem_imm);
8707 %}
8709 // Arithmetic Shift Right by variable
8710 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8711 %{
8712 match(Set dst (RShiftL dst shift));
8713 effect(KILL cr);
8715 format %{ "sarq $dst, $shift" %}
8716 opcode(0xD3, 0x7); /* D3 /7 */
8717 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8718 ins_pipe(ialu_reg_reg);
8719 %}
8721 // Arithmetic Shift Right by variable
8722 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8723 %{
8724 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8725 effect(KILL cr);
8727 format %{ "sarq $dst, $shift" %}
8728 opcode(0xD3, 0x7); /* D3 /7 */
8729 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8730 ins_pipe(ialu_mem_reg);
8731 %}
8733 // Logical shift right by one
8734 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8735 %{
8736 match(Set dst (URShiftL dst shift));
8737 effect(KILL cr);
8739 format %{ "shrq $dst, $shift" %}
8740 opcode(0xD1, 0x5); /* D1 /5 */
8741 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8742 ins_pipe(ialu_reg);
8743 %}
8745 // Logical shift right by one
8746 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8747 %{
8748 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8749 effect(KILL cr);
8751 format %{ "shrq $dst, $shift" %}
8752 opcode(0xD1, 0x5); /* D1 /5 */
8753 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8754 ins_pipe(ialu_mem_imm);
8755 %}
8757 // Logical Shift Right by 8-bit immediate
8758 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8759 %{
8760 match(Set dst (URShiftL dst shift));
8761 effect(KILL cr);
8763 format %{ "shrq $dst, $shift" %}
8764 opcode(0xC1, 0x5); /* C1 /5 ib */
8765 ins_encode(reg_opc_imm_wide(dst, shift));
8766 ins_pipe(ialu_reg);
8767 %}
8769 // Logical Shift Right by 8-bit immediate
8770 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8771 %{
8772 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8773 effect(KILL cr);
8775 format %{ "shrq $dst, $shift" %}
8776 opcode(0xC1, 0x5); /* C1 /5 ib */
8777 ins_encode(REX_mem_wide(dst), OpcP,
8778 RM_opc_mem(secondary, dst), Con8or32(shift));
8779 ins_pipe(ialu_mem_imm);
8780 %}
8782 // Logical Shift Right by variable
8783 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8784 %{
8785 match(Set dst (URShiftL dst shift));
8786 effect(KILL cr);
8788 format %{ "shrq $dst, $shift" %}
8789 opcode(0xD3, 0x5); /* D3 /5 */
8790 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8791 ins_pipe(ialu_reg_reg);
8792 %}
8794 // Logical Shift Right by variable
8795 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8796 %{
8797 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8798 effect(KILL cr);
8800 format %{ "shrq $dst, $shift" %}
8801 opcode(0xD3, 0x5); /* D3 /5 */
8802 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8803 ins_pipe(ialu_mem_reg);
8804 %}
8806 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8807 // This idiom is used by the compiler for the i2b bytecode.
8808 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8809 %{
8810 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8812 format %{ "movsbl $dst, $src\t# i2b" %}
8813 opcode(0x0F, 0xBE);
8814 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8815 ins_pipe(ialu_reg_reg);
8816 %}
8818 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8819 // This idiom is used by the compiler the i2s bytecode.
8820 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8821 %{
8822 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8824 format %{ "movswl $dst, $src\t# i2s" %}
8825 opcode(0x0F, 0xBF);
8826 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8827 ins_pipe(ialu_reg_reg);
8828 %}
8830 // ROL/ROR instructions
8832 // ROL expand
8833 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8834 effect(KILL cr, USE_DEF dst);
8836 format %{ "roll $dst" %}
8837 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8838 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8839 ins_pipe(ialu_reg);
8840 %}
8842 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8843 effect(USE_DEF dst, USE shift, KILL cr);
8845 format %{ "roll $dst, $shift" %}
8846 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8847 ins_encode( reg_opc_imm(dst, shift) );
8848 ins_pipe(ialu_reg);
8849 %}
8851 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8852 %{
8853 effect(USE_DEF dst, USE shift, KILL cr);
8855 format %{ "roll $dst, $shift" %}
8856 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8857 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8858 ins_pipe(ialu_reg_reg);
8859 %}
8860 // end of ROL expand
8862 // Rotate Left by one
8863 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8864 %{
8865 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8867 expand %{
8868 rolI_rReg_imm1(dst, cr);
8869 %}
8870 %}
8872 // Rotate Left by 8-bit immediate
8873 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8874 %{
8875 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8876 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8878 expand %{
8879 rolI_rReg_imm8(dst, lshift, cr);
8880 %}
8881 %}
8883 // Rotate Left by variable
8884 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8885 %{
8886 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8888 expand %{
8889 rolI_rReg_CL(dst, shift, cr);
8890 %}
8891 %}
8893 // Rotate Left by variable
8894 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8895 %{
8896 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8898 expand %{
8899 rolI_rReg_CL(dst, shift, cr);
8900 %}
8901 %}
8903 // ROR expand
8904 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8905 %{
8906 effect(USE_DEF dst, KILL cr);
8908 format %{ "rorl $dst" %}
8909 opcode(0xD1, 0x1); /* D1 /1 */
8910 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8911 ins_pipe(ialu_reg);
8912 %}
8914 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8915 %{
8916 effect(USE_DEF dst, USE shift, KILL cr);
8918 format %{ "rorl $dst, $shift" %}
8919 opcode(0xC1, 0x1); /* C1 /1 ib */
8920 ins_encode(reg_opc_imm(dst, shift));
8921 ins_pipe(ialu_reg);
8922 %}
8924 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8925 %{
8926 effect(USE_DEF dst, USE shift, KILL cr);
8928 format %{ "rorl $dst, $shift" %}
8929 opcode(0xD3, 0x1); /* D3 /1 */
8930 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8931 ins_pipe(ialu_reg_reg);
8932 %}
8933 // end of ROR expand
8935 // Rotate Right by one
8936 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8937 %{
8938 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8940 expand %{
8941 rorI_rReg_imm1(dst, cr);
8942 %}
8943 %}
8945 // Rotate Right by 8-bit immediate
8946 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8947 %{
8948 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8949 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8951 expand %{
8952 rorI_rReg_imm8(dst, rshift, cr);
8953 %}
8954 %}
8956 // Rotate Right by variable
8957 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8958 %{
8959 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8961 expand %{
8962 rorI_rReg_CL(dst, shift, cr);
8963 %}
8964 %}
8966 // Rotate Right by variable
8967 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8968 %{
8969 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8971 expand %{
8972 rorI_rReg_CL(dst, shift, cr);
8973 %}
8974 %}
8976 // for long rotate
8977 // ROL expand
8978 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8979 effect(USE_DEF dst, KILL cr);
8981 format %{ "rolq $dst" %}
8982 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8983 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8984 ins_pipe(ialu_reg);
8985 %}
8987 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8988 effect(USE_DEF dst, USE shift, KILL cr);
8990 format %{ "rolq $dst, $shift" %}
8991 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8992 ins_encode( reg_opc_imm_wide(dst, shift) );
8993 ins_pipe(ialu_reg);
8994 %}
8996 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8997 %{
8998 effect(USE_DEF dst, USE shift, KILL cr);
9000 format %{ "rolq $dst, $shift" %}
9001 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9002 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9003 ins_pipe(ialu_reg_reg);
9004 %}
9005 // end of ROL expand
9007 // Rotate Left by one
9008 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9009 %{
9010 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9012 expand %{
9013 rolL_rReg_imm1(dst, cr);
9014 %}
9015 %}
9017 // Rotate Left by 8-bit immediate
9018 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9019 %{
9020 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9021 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9023 expand %{
9024 rolL_rReg_imm8(dst, lshift, cr);
9025 %}
9026 %}
9028 // Rotate Left by variable
9029 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9030 %{
9031 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9033 expand %{
9034 rolL_rReg_CL(dst, shift, cr);
9035 %}
9036 %}
9038 // Rotate Left by variable
9039 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9040 %{
9041 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9043 expand %{
9044 rolL_rReg_CL(dst, shift, cr);
9045 %}
9046 %}
9048 // ROR expand
9049 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9050 %{
9051 effect(USE_DEF dst, KILL cr);
9053 format %{ "rorq $dst" %}
9054 opcode(0xD1, 0x1); /* D1 /1 */
9055 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9056 ins_pipe(ialu_reg);
9057 %}
9059 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9060 %{
9061 effect(USE_DEF dst, USE shift, KILL cr);
9063 format %{ "rorq $dst, $shift" %}
9064 opcode(0xC1, 0x1); /* C1 /1 ib */
9065 ins_encode(reg_opc_imm_wide(dst, shift));
9066 ins_pipe(ialu_reg);
9067 %}
9069 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9070 %{
9071 effect(USE_DEF dst, USE shift, KILL cr);
9073 format %{ "rorq $dst, $shift" %}
9074 opcode(0xD3, 0x1); /* D3 /1 */
9075 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9076 ins_pipe(ialu_reg_reg);
9077 %}
9078 // end of ROR expand
9080 // Rotate Right by one
9081 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9082 %{
9083 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9085 expand %{
9086 rorL_rReg_imm1(dst, cr);
9087 %}
9088 %}
9090 // Rotate Right by 8-bit immediate
9091 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9092 %{
9093 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9094 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9096 expand %{
9097 rorL_rReg_imm8(dst, rshift, cr);
9098 %}
9099 %}
9101 // Rotate Right by variable
9102 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9103 %{
9104 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9106 expand %{
9107 rorL_rReg_CL(dst, shift, cr);
9108 %}
9109 %}
9111 // Rotate Right by variable
9112 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9113 %{
9114 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9116 expand %{
9117 rorL_rReg_CL(dst, shift, cr);
9118 %}
9119 %}
9121 // Logical Instructions
9123 // Integer Logical Instructions
9125 // And Instructions
9126 // And Register with Register
9127 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9128 %{
9129 match(Set dst (AndI dst src));
9130 effect(KILL cr);
9132 format %{ "andl $dst, $src\t# int" %}
9133 opcode(0x23);
9134 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9135 ins_pipe(ialu_reg_reg);
9136 %}
9138 // And Register with Immediate 255
9139 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9140 %{
9141 match(Set dst (AndI dst src));
9143 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9144 opcode(0x0F, 0xB6);
9145 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9146 ins_pipe(ialu_reg);
9147 %}
9149 // And Register with Immediate 255 and promote to long
9150 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9151 %{
9152 match(Set dst (ConvI2L (AndI src mask)));
9154 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9155 opcode(0x0F, 0xB6);
9156 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9157 ins_pipe(ialu_reg);
9158 %}
9160 // And Register with Immediate 65535
9161 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9162 %{
9163 match(Set dst (AndI dst src));
9165 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9166 opcode(0x0F, 0xB7);
9167 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9168 ins_pipe(ialu_reg);
9169 %}
9171 // And Register with Immediate 65535 and promote to long
9172 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9173 %{
9174 match(Set dst (ConvI2L (AndI src mask)));
9176 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9177 opcode(0x0F, 0xB7);
9178 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9179 ins_pipe(ialu_reg);
9180 %}
9182 // And Register with Immediate
9183 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9184 %{
9185 match(Set dst (AndI dst src));
9186 effect(KILL cr);
9188 format %{ "andl $dst, $src\t# int" %}
9189 opcode(0x81, 0x04); /* Opcode 81 /4 */
9190 ins_encode(OpcSErm(dst, src), Con8or32(src));
9191 ins_pipe(ialu_reg);
9192 %}
9194 // And Register with Memory
9195 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9196 %{
9197 match(Set dst (AndI dst (LoadI src)));
9198 effect(KILL cr);
9200 ins_cost(125);
9201 format %{ "andl $dst, $src\t# int" %}
9202 opcode(0x23);
9203 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9204 ins_pipe(ialu_reg_mem);
9205 %}
9207 // And Memory with Register
9208 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9209 %{
9210 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9211 effect(KILL cr);
9213 ins_cost(150);
9214 format %{ "andl $dst, $src\t# int" %}
9215 opcode(0x21); /* Opcode 21 /r */
9216 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9217 ins_pipe(ialu_mem_reg);
9218 %}
9220 // And Memory with Immediate
9221 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9222 %{
9223 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9224 effect(KILL cr);
9226 ins_cost(125);
9227 format %{ "andl $dst, $src\t# int" %}
9228 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9229 ins_encode(REX_mem(dst), OpcSE(src),
9230 RM_opc_mem(secondary, dst), Con8or32(src));
9231 ins_pipe(ialu_mem_imm);
9232 %}
9234 // Or Instructions
9235 // Or Register with Register
9236 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9237 %{
9238 match(Set dst (OrI dst src));
9239 effect(KILL cr);
9241 format %{ "orl $dst, $src\t# int" %}
9242 opcode(0x0B);
9243 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9244 ins_pipe(ialu_reg_reg);
9245 %}
9247 // Or Register with Immediate
9248 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9249 %{
9250 match(Set dst (OrI dst src));
9251 effect(KILL cr);
9253 format %{ "orl $dst, $src\t# int" %}
9254 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9255 ins_encode(OpcSErm(dst, src), Con8or32(src));
9256 ins_pipe(ialu_reg);
9257 %}
9259 // Or Register with Memory
9260 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9261 %{
9262 match(Set dst (OrI dst (LoadI src)));
9263 effect(KILL cr);
9265 ins_cost(125);
9266 format %{ "orl $dst, $src\t# int" %}
9267 opcode(0x0B);
9268 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9269 ins_pipe(ialu_reg_mem);
9270 %}
9272 // Or Memory with Register
9273 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9274 %{
9275 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9276 effect(KILL cr);
9278 ins_cost(150);
9279 format %{ "orl $dst, $src\t# int" %}
9280 opcode(0x09); /* Opcode 09 /r */
9281 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9282 ins_pipe(ialu_mem_reg);
9283 %}
9285 // Or Memory with Immediate
9286 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9287 %{
9288 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9289 effect(KILL cr);
9291 ins_cost(125);
9292 format %{ "orl $dst, $src\t# int" %}
9293 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9294 ins_encode(REX_mem(dst), OpcSE(src),
9295 RM_opc_mem(secondary, dst), Con8or32(src));
9296 ins_pipe(ialu_mem_imm);
9297 %}
9299 // Xor Instructions
9300 // Xor Register with Register
9301 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9302 %{
9303 match(Set dst (XorI dst src));
9304 effect(KILL cr);
9306 format %{ "xorl $dst, $src\t# int" %}
9307 opcode(0x33);
9308 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9309 ins_pipe(ialu_reg_reg);
9310 %}
9312 // Xor Register with Immediate -1
9313 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9314 match(Set dst (XorI dst imm));
9316 format %{ "not $dst" %}
9317 ins_encode %{
9318 __ notl($dst$$Register);
9319 %}
9320 ins_pipe(ialu_reg);
9321 %}
9323 // Xor Register with Immediate
9324 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9325 %{
9326 match(Set dst (XorI dst src));
9327 effect(KILL cr);
9329 format %{ "xorl $dst, $src\t# int" %}
9330 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9331 ins_encode(OpcSErm(dst, src), Con8or32(src));
9332 ins_pipe(ialu_reg);
9333 %}
9335 // Xor Register with Memory
9336 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9337 %{
9338 match(Set dst (XorI dst (LoadI src)));
9339 effect(KILL cr);
9341 ins_cost(125);
9342 format %{ "xorl $dst, $src\t# int" %}
9343 opcode(0x33);
9344 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9345 ins_pipe(ialu_reg_mem);
9346 %}
9348 // Xor Memory with Register
9349 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9350 %{
9351 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9352 effect(KILL cr);
9354 ins_cost(150);
9355 format %{ "xorl $dst, $src\t# int" %}
9356 opcode(0x31); /* Opcode 31 /r */
9357 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9358 ins_pipe(ialu_mem_reg);
9359 %}
9361 // Xor Memory with Immediate
9362 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9363 %{
9364 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9365 effect(KILL cr);
9367 ins_cost(125);
9368 format %{ "xorl $dst, $src\t# int" %}
9369 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9370 ins_encode(REX_mem(dst), OpcSE(src),
9371 RM_opc_mem(secondary, dst), Con8or32(src));
9372 ins_pipe(ialu_mem_imm);
9373 %}
9376 // Long Logical Instructions
9378 // And Instructions
9379 // And Register with Register
9380 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9381 %{
9382 match(Set dst (AndL dst src));
9383 effect(KILL cr);
9385 format %{ "andq $dst, $src\t# long" %}
9386 opcode(0x23);
9387 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9388 ins_pipe(ialu_reg_reg);
9389 %}
9391 // And Register with Immediate 255
9392 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9393 %{
9394 match(Set dst (AndL dst src));
9396 format %{ "movzbq $dst, $src\t# long & 0xFF" %}
9397 opcode(0x0F, 0xB6);
9398 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9399 ins_pipe(ialu_reg);
9400 %}
9402 // And Register with Immediate 65535
9403 instruct andL_rReg_imm65535(rRegI dst, immL_65535 src)
9404 %{
9405 match(Set dst (AndL dst src));
9407 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9408 opcode(0x0F, 0xB7);
9409 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9410 ins_pipe(ialu_reg);
9411 %}
9413 // And Register with Immediate
9414 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9415 %{
9416 match(Set dst (AndL dst src));
9417 effect(KILL cr);
9419 format %{ "andq $dst, $src\t# long" %}
9420 opcode(0x81, 0x04); /* Opcode 81 /4 */
9421 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9422 ins_pipe(ialu_reg);
9423 %}
9425 // And Register with Memory
9426 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9427 %{
9428 match(Set dst (AndL dst (LoadL src)));
9429 effect(KILL cr);
9431 ins_cost(125);
9432 format %{ "andq $dst, $src\t# long" %}
9433 opcode(0x23);
9434 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9435 ins_pipe(ialu_reg_mem);
9436 %}
9438 // And Memory with Register
9439 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9440 %{
9441 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9442 effect(KILL cr);
9444 ins_cost(150);
9445 format %{ "andq $dst, $src\t# long" %}
9446 opcode(0x21); /* Opcode 21 /r */
9447 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9448 ins_pipe(ialu_mem_reg);
9449 %}
9451 // And Memory with Immediate
9452 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9453 %{
9454 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9455 effect(KILL cr);
9457 ins_cost(125);
9458 format %{ "andq $dst, $src\t# long" %}
9459 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9460 ins_encode(REX_mem_wide(dst), OpcSE(src),
9461 RM_opc_mem(secondary, dst), Con8or32(src));
9462 ins_pipe(ialu_mem_imm);
9463 %}
9465 // Or Instructions
9466 // Or Register with Register
9467 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9468 %{
9469 match(Set dst (OrL dst src));
9470 effect(KILL cr);
9472 format %{ "orq $dst, $src\t# long" %}
9473 opcode(0x0B);
9474 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9475 ins_pipe(ialu_reg_reg);
9476 %}
9478 // Or Register with Immediate
9479 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9480 %{
9481 match(Set dst (OrL dst src));
9482 effect(KILL cr);
9484 format %{ "orq $dst, $src\t# long" %}
9485 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9486 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9487 ins_pipe(ialu_reg);
9488 %}
9490 // Or Register with Memory
9491 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9492 %{
9493 match(Set dst (OrL dst (LoadL src)));
9494 effect(KILL cr);
9496 ins_cost(125);
9497 format %{ "orq $dst, $src\t# long" %}
9498 opcode(0x0B);
9499 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9500 ins_pipe(ialu_reg_mem);
9501 %}
9503 // Or Memory with Register
9504 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9505 %{
9506 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9507 effect(KILL cr);
9509 ins_cost(150);
9510 format %{ "orq $dst, $src\t# long" %}
9511 opcode(0x09); /* Opcode 09 /r */
9512 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9513 ins_pipe(ialu_mem_reg);
9514 %}
9516 // Or Memory with Immediate
9517 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9518 %{
9519 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9520 effect(KILL cr);
9522 ins_cost(125);
9523 format %{ "orq $dst, $src\t# long" %}
9524 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9525 ins_encode(REX_mem_wide(dst), OpcSE(src),
9526 RM_opc_mem(secondary, dst), Con8or32(src));
9527 ins_pipe(ialu_mem_imm);
9528 %}
9530 // Xor Instructions
9531 // Xor Register with Register
9532 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9533 %{
9534 match(Set dst (XorL dst src));
9535 effect(KILL cr);
9537 format %{ "xorq $dst, $src\t# long" %}
9538 opcode(0x33);
9539 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9540 ins_pipe(ialu_reg_reg);
9541 %}
9543 // Xor Register with Immediate -1
9544 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9545 match(Set dst (XorL dst imm));
9547 format %{ "notq $dst" %}
9548 ins_encode %{
9549 __ notq($dst$$Register);
9550 %}
9551 ins_pipe(ialu_reg);
9552 %}
9554 // Xor Register with Immediate
9555 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9556 %{
9557 match(Set dst (XorL dst src));
9558 effect(KILL cr);
9560 format %{ "xorq $dst, $src\t# long" %}
9561 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9562 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9563 ins_pipe(ialu_reg);
9564 %}
9566 // Xor Register with Memory
9567 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9568 %{
9569 match(Set dst (XorL dst (LoadL src)));
9570 effect(KILL cr);
9572 ins_cost(125);
9573 format %{ "xorq $dst, $src\t# long" %}
9574 opcode(0x33);
9575 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9576 ins_pipe(ialu_reg_mem);
9577 %}
9579 // Xor Memory with Register
9580 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9581 %{
9582 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9583 effect(KILL cr);
9585 ins_cost(150);
9586 format %{ "xorq $dst, $src\t# long" %}
9587 opcode(0x31); /* Opcode 31 /r */
9588 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9589 ins_pipe(ialu_mem_reg);
9590 %}
9592 // Xor Memory with Immediate
9593 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9594 %{
9595 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9596 effect(KILL cr);
9598 ins_cost(125);
9599 format %{ "xorq $dst, $src\t# long" %}
9600 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9601 ins_encode(REX_mem_wide(dst), OpcSE(src),
9602 RM_opc_mem(secondary, dst), Con8or32(src));
9603 ins_pipe(ialu_mem_imm);
9604 %}
9606 // Convert Int to Boolean
9607 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9608 %{
9609 match(Set dst (Conv2B src));
9610 effect(KILL cr);
9612 format %{ "testl $src, $src\t# ci2b\n\t"
9613 "setnz $dst\n\t"
9614 "movzbl $dst, $dst" %}
9615 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9616 setNZ_reg(dst),
9617 REX_reg_breg(dst, dst), // movzbl
9618 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9619 ins_pipe(pipe_slow); // XXX
9620 %}
9622 // Convert Pointer to Boolean
9623 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9624 %{
9625 match(Set dst (Conv2B src));
9626 effect(KILL cr);
9628 format %{ "testq $src, $src\t# cp2b\n\t"
9629 "setnz $dst\n\t"
9630 "movzbl $dst, $dst" %}
9631 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9632 setNZ_reg(dst),
9633 REX_reg_breg(dst, dst), // movzbl
9634 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9635 ins_pipe(pipe_slow); // XXX
9636 %}
9638 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9639 %{
9640 match(Set dst (CmpLTMask p q));
9641 effect(KILL cr);
9643 ins_cost(400); // XXX
9644 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9645 "setlt $dst\n\t"
9646 "movzbl $dst, $dst\n\t"
9647 "negl $dst" %}
9648 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9649 setLT_reg(dst),
9650 REX_reg_breg(dst, dst), // movzbl
9651 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9652 neg_reg(dst));
9653 ins_pipe(pipe_slow);
9654 %}
9656 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9657 %{
9658 match(Set dst (CmpLTMask dst zero));
9659 effect(KILL cr);
9661 ins_cost(100); // XXX
9662 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9663 opcode(0xC1, 0x7); /* C1 /7 ib */
9664 ins_encode(reg_opc_imm(dst, 0x1F));
9665 ins_pipe(ialu_reg);
9666 %}
9669 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y,
9670 rRegI tmp,
9671 rFlagsReg cr)
9672 %{
9673 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9674 effect(TEMP tmp, KILL cr);
9676 ins_cost(400); // XXX
9677 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
9678 "sbbl $tmp, $tmp\n\t"
9679 "andl $tmp, $y\n\t"
9680 "addl $p, $tmp" %}
9681 ins_encode(enc_cmpLTP(p, q, y, tmp));
9682 ins_pipe(pipe_cmplt);
9683 %}
9685 /* If I enable this, I encourage spilling in the inner loop of compress.
9686 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr )
9687 %{
9688 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9689 effect( TEMP tmp, KILL cr );
9690 ins_cost(400);
9692 format %{ "SUB $p,$q\n\t"
9693 "SBB RCX,RCX\n\t"
9694 "AND RCX,$y\n\t"
9695 "ADD $p,RCX" %}
9696 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9697 %}
9698 */
9700 //---------- FP Instructions------------------------------------------------
9702 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9703 %{
9704 match(Set cr (CmpF src1 src2));
9706 ins_cost(145);
9707 format %{ "ucomiss $src1, $src2\n\t"
9708 "jnp,s exit\n\t"
9709 "pushfq\t# saw NaN, set CF\n\t"
9710 "andq [rsp], #0xffffff2b\n\t"
9711 "popfq\n"
9712 "exit: nop\t# avoid branch to branch" %}
9713 opcode(0x0F, 0x2E);
9714 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
9715 cmpfp_fixup);
9716 ins_pipe(pipe_slow);
9717 %}
9719 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9720 %{
9721 match(Set cr (CmpF src1 (LoadF src2)));
9723 ins_cost(145);
9724 format %{ "ucomiss $src1, $src2\n\t"
9725 "jnp,s exit\n\t"
9726 "pushfq\t# saw NaN, set CF\n\t"
9727 "andq [rsp], #0xffffff2b\n\t"
9728 "popfq\n"
9729 "exit: nop\t# avoid branch to branch" %}
9730 opcode(0x0F, 0x2E);
9731 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
9732 cmpfp_fixup);
9733 ins_pipe(pipe_slow);
9734 %}
9736 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2)
9737 %{
9738 match(Set cr (CmpF src1 src2));
9740 ins_cost(145);
9741 format %{ "ucomiss $src1, $src2\n\t"
9742 "jnp,s exit\n\t"
9743 "pushfq\t# saw NaN, set CF\n\t"
9744 "andq [rsp], #0xffffff2b\n\t"
9745 "popfq\n"
9746 "exit: nop\t# avoid branch to branch" %}
9747 opcode(0x0F, 0x2E);
9748 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
9749 cmpfp_fixup);
9750 ins_pipe(pipe_slow);
9751 %}
9753 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9754 %{
9755 match(Set cr (CmpD src1 src2));
9757 ins_cost(145);
9758 format %{ "ucomisd $src1, $src2\n\t"
9759 "jnp,s exit\n\t"
9760 "pushfq\t# saw NaN, set CF\n\t"
9761 "andq [rsp], #0xffffff2b\n\t"
9762 "popfq\n"
9763 "exit: nop\t# avoid branch to branch" %}
9764 opcode(0x66, 0x0F, 0x2E);
9765 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
9766 cmpfp_fixup);
9767 ins_pipe(pipe_slow);
9768 %}
9770 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9771 %{
9772 match(Set cr (CmpD src1 (LoadD src2)));
9774 ins_cost(145);
9775 format %{ "ucomisd $src1, $src2\n\t"
9776 "jnp,s exit\n\t"
9777 "pushfq\t# saw NaN, set CF\n\t"
9778 "andq [rsp], #0xffffff2b\n\t"
9779 "popfq\n"
9780 "exit: nop\t# avoid branch to branch" %}
9781 opcode(0x66, 0x0F, 0x2E);
9782 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
9783 cmpfp_fixup);
9784 ins_pipe(pipe_slow);
9785 %}
9787 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2)
9788 %{
9789 match(Set cr (CmpD src1 src2));
9791 ins_cost(145);
9792 format %{ "ucomisd $src1, [$src2]\n\t"
9793 "jnp,s exit\n\t"
9794 "pushfq\t# saw NaN, set CF\n\t"
9795 "andq [rsp], #0xffffff2b\n\t"
9796 "popfq\n"
9797 "exit: nop\t# avoid branch to branch" %}
9798 opcode(0x66, 0x0F, 0x2E);
9799 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
9800 cmpfp_fixup);
9801 ins_pipe(pipe_slow);
9802 %}
9804 // Compare into -1,0,1
9805 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9806 %{
9807 match(Set dst (CmpF3 src1 src2));
9808 effect(KILL cr);
9810 ins_cost(275);
9811 format %{ "ucomiss $src1, $src2\n\t"
9812 "movl $dst, #-1\n\t"
9813 "jp,s done\n\t"
9814 "jb,s done\n\t"
9815 "setne $dst\n\t"
9816 "movzbl $dst, $dst\n"
9817 "done:" %}
9819 opcode(0x0F, 0x2E);
9820 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
9821 cmpfp3(dst));
9822 ins_pipe(pipe_slow);
9823 %}
9825 // Compare into -1,0,1
9826 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9827 %{
9828 match(Set dst (CmpF3 src1 (LoadF src2)));
9829 effect(KILL cr);
9831 ins_cost(275);
9832 format %{ "ucomiss $src1, $src2\n\t"
9833 "movl $dst, #-1\n\t"
9834 "jp,s done\n\t"
9835 "jb,s done\n\t"
9836 "setne $dst\n\t"
9837 "movzbl $dst, $dst\n"
9838 "done:" %}
9840 opcode(0x0F, 0x2E);
9841 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
9842 cmpfp3(dst));
9843 ins_pipe(pipe_slow);
9844 %}
9846 // Compare into -1,0,1
9847 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr)
9848 %{
9849 match(Set dst (CmpF3 src1 src2));
9850 effect(KILL cr);
9852 ins_cost(275);
9853 format %{ "ucomiss $src1, [$src2]\n\t"
9854 "movl $dst, #-1\n\t"
9855 "jp,s done\n\t"
9856 "jb,s done\n\t"
9857 "setne $dst\n\t"
9858 "movzbl $dst, $dst\n"
9859 "done:" %}
9861 opcode(0x0F, 0x2E);
9862 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
9863 cmpfp3(dst));
9864 ins_pipe(pipe_slow);
9865 %}
9867 // Compare into -1,0,1
9868 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9869 %{
9870 match(Set dst (CmpD3 src1 src2));
9871 effect(KILL cr);
9873 ins_cost(275);
9874 format %{ "ucomisd $src1, $src2\n\t"
9875 "movl $dst, #-1\n\t"
9876 "jp,s done\n\t"
9877 "jb,s done\n\t"
9878 "setne $dst\n\t"
9879 "movzbl $dst, $dst\n"
9880 "done:" %}
9882 opcode(0x66, 0x0F, 0x2E);
9883 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
9884 cmpfp3(dst));
9885 ins_pipe(pipe_slow);
9886 %}
9888 // Compare into -1,0,1
9889 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9890 %{
9891 match(Set dst (CmpD3 src1 (LoadD src2)));
9892 effect(KILL cr);
9894 ins_cost(275);
9895 format %{ "ucomisd $src1, $src2\n\t"
9896 "movl $dst, #-1\n\t"
9897 "jp,s done\n\t"
9898 "jb,s done\n\t"
9899 "setne $dst\n\t"
9900 "movzbl $dst, $dst\n"
9901 "done:" %}
9903 opcode(0x66, 0x0F, 0x2E);
9904 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
9905 cmpfp3(dst));
9906 ins_pipe(pipe_slow);
9907 %}
9909 // Compare into -1,0,1
9910 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr)
9911 %{
9912 match(Set dst (CmpD3 src1 src2));
9913 effect(KILL cr);
9915 ins_cost(275);
9916 format %{ "ucomisd $src1, [$src2]\n\t"
9917 "movl $dst, #-1\n\t"
9918 "jp,s done\n\t"
9919 "jb,s done\n\t"
9920 "setne $dst\n\t"
9921 "movzbl $dst, $dst\n"
9922 "done:" %}
9924 opcode(0x66, 0x0F, 0x2E);
9925 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
9926 cmpfp3(dst));
9927 ins_pipe(pipe_slow);
9928 %}
9930 instruct addF_reg(regF dst, regF src)
9931 %{
9932 match(Set dst (AddF dst src));
9934 format %{ "addss $dst, $src" %}
9935 ins_cost(150); // XXX
9936 opcode(0xF3, 0x0F, 0x58);
9937 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9938 ins_pipe(pipe_slow);
9939 %}
9941 instruct addF_mem(regF dst, memory src)
9942 %{
9943 match(Set dst (AddF dst (LoadF src)));
9945 format %{ "addss $dst, $src" %}
9946 ins_cost(150); // XXX
9947 opcode(0xF3, 0x0F, 0x58);
9948 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9949 ins_pipe(pipe_slow);
9950 %}
9952 instruct addF_imm(regF dst, immF src)
9953 %{
9954 match(Set dst (AddF dst src));
9956 format %{ "addss $dst, [$src]" %}
9957 ins_cost(150); // XXX
9958 opcode(0xF3, 0x0F, 0x58);
9959 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
9960 ins_pipe(pipe_slow);
9961 %}
9963 instruct addD_reg(regD dst, regD src)
9964 %{
9965 match(Set dst (AddD dst src));
9967 format %{ "addsd $dst, $src" %}
9968 ins_cost(150); // XXX
9969 opcode(0xF2, 0x0F, 0x58);
9970 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9971 ins_pipe(pipe_slow);
9972 %}
9974 instruct addD_mem(regD dst, memory src)
9975 %{
9976 match(Set dst (AddD dst (LoadD src)));
9978 format %{ "addsd $dst, $src" %}
9979 ins_cost(150); // XXX
9980 opcode(0xF2, 0x0F, 0x58);
9981 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9982 ins_pipe(pipe_slow);
9983 %}
9985 instruct addD_imm(regD dst, immD src)
9986 %{
9987 match(Set dst (AddD dst src));
9989 format %{ "addsd $dst, [$src]" %}
9990 ins_cost(150); // XXX
9991 opcode(0xF2, 0x0F, 0x58);
9992 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
9993 ins_pipe(pipe_slow);
9994 %}
9996 instruct subF_reg(regF dst, regF src)
9997 %{
9998 match(Set dst (SubF dst src));
10000 format %{ "subss $dst, $src" %}
10001 ins_cost(150); // XXX
10002 opcode(0xF3, 0x0F, 0x5C);
10003 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10004 ins_pipe(pipe_slow);
10005 %}
10007 instruct subF_mem(regF dst, memory src)
10008 %{
10009 match(Set dst (SubF dst (LoadF src)));
10011 format %{ "subss $dst, $src" %}
10012 ins_cost(150); // XXX
10013 opcode(0xF3, 0x0F, 0x5C);
10014 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10015 ins_pipe(pipe_slow);
10016 %}
10018 instruct subF_imm(regF dst, immF src)
10019 %{
10020 match(Set dst (SubF dst src));
10022 format %{ "subss $dst, [$src]" %}
10023 ins_cost(150); // XXX
10024 opcode(0xF3, 0x0F, 0x5C);
10025 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10026 ins_pipe(pipe_slow);
10027 %}
10029 instruct subD_reg(regD dst, regD src)
10030 %{
10031 match(Set dst (SubD dst src));
10033 format %{ "subsd $dst, $src" %}
10034 ins_cost(150); // XXX
10035 opcode(0xF2, 0x0F, 0x5C);
10036 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10037 ins_pipe(pipe_slow);
10038 %}
10040 instruct subD_mem(regD dst, memory src)
10041 %{
10042 match(Set dst (SubD dst (LoadD src)));
10044 format %{ "subsd $dst, $src" %}
10045 ins_cost(150); // XXX
10046 opcode(0xF2, 0x0F, 0x5C);
10047 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10048 ins_pipe(pipe_slow);
10049 %}
10051 instruct subD_imm(regD dst, immD src)
10052 %{
10053 match(Set dst (SubD dst src));
10055 format %{ "subsd $dst, [$src]" %}
10056 ins_cost(150); // XXX
10057 opcode(0xF2, 0x0F, 0x5C);
10058 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10059 ins_pipe(pipe_slow);
10060 %}
10062 instruct mulF_reg(regF dst, regF src)
10063 %{
10064 match(Set dst (MulF dst src));
10066 format %{ "mulss $dst, $src" %}
10067 ins_cost(150); // XXX
10068 opcode(0xF3, 0x0F, 0x59);
10069 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10070 ins_pipe(pipe_slow);
10071 %}
10073 instruct mulF_mem(regF dst, memory src)
10074 %{
10075 match(Set dst (MulF dst (LoadF src)));
10077 format %{ "mulss $dst, $src" %}
10078 ins_cost(150); // XXX
10079 opcode(0xF3, 0x0F, 0x59);
10080 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10081 ins_pipe(pipe_slow);
10082 %}
10084 instruct mulF_imm(regF dst, immF src)
10085 %{
10086 match(Set dst (MulF dst src));
10088 format %{ "mulss $dst, [$src]" %}
10089 ins_cost(150); // XXX
10090 opcode(0xF3, 0x0F, 0x59);
10091 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10092 ins_pipe(pipe_slow);
10093 %}
10095 instruct mulD_reg(regD dst, regD src)
10096 %{
10097 match(Set dst (MulD dst src));
10099 format %{ "mulsd $dst, $src" %}
10100 ins_cost(150); // XXX
10101 opcode(0xF2, 0x0F, 0x59);
10102 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10103 ins_pipe(pipe_slow);
10104 %}
10106 instruct mulD_mem(regD dst, memory src)
10107 %{
10108 match(Set dst (MulD dst (LoadD src)));
10110 format %{ "mulsd $dst, $src" %}
10111 ins_cost(150); // XXX
10112 opcode(0xF2, 0x0F, 0x59);
10113 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10114 ins_pipe(pipe_slow);
10115 %}
10117 instruct mulD_imm(regD dst, immD src)
10118 %{
10119 match(Set dst (MulD dst src));
10121 format %{ "mulsd $dst, [$src]" %}
10122 ins_cost(150); // XXX
10123 opcode(0xF2, 0x0F, 0x59);
10124 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10125 ins_pipe(pipe_slow);
10126 %}
10128 instruct divF_reg(regF dst, regF src)
10129 %{
10130 match(Set dst (DivF dst src));
10132 format %{ "divss $dst, $src" %}
10133 ins_cost(150); // XXX
10134 opcode(0xF3, 0x0F, 0x5E);
10135 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10136 ins_pipe(pipe_slow);
10137 %}
10139 instruct divF_mem(regF dst, memory src)
10140 %{
10141 match(Set dst (DivF dst (LoadF src)));
10143 format %{ "divss $dst, $src" %}
10144 ins_cost(150); // XXX
10145 opcode(0xF3, 0x0F, 0x5E);
10146 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10147 ins_pipe(pipe_slow);
10148 %}
10150 instruct divF_imm(regF dst, immF src)
10151 %{
10152 match(Set dst (DivF dst src));
10154 format %{ "divss $dst, [$src]" %}
10155 ins_cost(150); // XXX
10156 opcode(0xF3, 0x0F, 0x5E);
10157 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10158 ins_pipe(pipe_slow);
10159 %}
10161 instruct divD_reg(regD dst, regD src)
10162 %{
10163 match(Set dst (DivD dst src));
10165 format %{ "divsd $dst, $src" %}
10166 ins_cost(150); // XXX
10167 opcode(0xF2, 0x0F, 0x5E);
10168 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10169 ins_pipe(pipe_slow);
10170 %}
10172 instruct divD_mem(regD dst, memory src)
10173 %{
10174 match(Set dst (DivD dst (LoadD src)));
10176 format %{ "divsd $dst, $src" %}
10177 ins_cost(150); // XXX
10178 opcode(0xF2, 0x0F, 0x5E);
10179 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10180 ins_pipe(pipe_slow);
10181 %}
10183 instruct divD_imm(regD dst, immD src)
10184 %{
10185 match(Set dst (DivD dst src));
10187 format %{ "divsd $dst, [$src]" %}
10188 ins_cost(150); // XXX
10189 opcode(0xF2, 0x0F, 0x5E);
10190 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10191 ins_pipe(pipe_slow);
10192 %}
10194 instruct sqrtF_reg(regF dst, regF src)
10195 %{
10196 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10198 format %{ "sqrtss $dst, $src" %}
10199 ins_cost(150); // XXX
10200 opcode(0xF3, 0x0F, 0x51);
10201 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10202 ins_pipe(pipe_slow);
10203 %}
10205 instruct sqrtF_mem(regF dst, memory src)
10206 %{
10207 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
10209 format %{ "sqrtss $dst, $src" %}
10210 ins_cost(150); // XXX
10211 opcode(0xF3, 0x0F, 0x51);
10212 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10213 ins_pipe(pipe_slow);
10214 %}
10216 instruct sqrtF_imm(regF dst, immF src)
10217 %{
10218 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10220 format %{ "sqrtss $dst, [$src]" %}
10221 ins_cost(150); // XXX
10222 opcode(0xF3, 0x0F, 0x51);
10223 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10224 ins_pipe(pipe_slow);
10225 %}
10227 instruct sqrtD_reg(regD dst, regD src)
10228 %{
10229 match(Set dst (SqrtD src));
10231 format %{ "sqrtsd $dst, $src" %}
10232 ins_cost(150); // XXX
10233 opcode(0xF2, 0x0F, 0x51);
10234 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10235 ins_pipe(pipe_slow);
10236 %}
10238 instruct sqrtD_mem(regD dst, memory src)
10239 %{
10240 match(Set dst (SqrtD (LoadD src)));
10242 format %{ "sqrtsd $dst, $src" %}
10243 ins_cost(150); // XXX
10244 opcode(0xF2, 0x0F, 0x51);
10245 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10246 ins_pipe(pipe_slow);
10247 %}
10249 instruct sqrtD_imm(regD dst, immD src)
10250 %{
10251 match(Set dst (SqrtD src));
10253 format %{ "sqrtsd $dst, [$src]" %}
10254 ins_cost(150); // XXX
10255 opcode(0xF2, 0x0F, 0x51);
10256 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10257 ins_pipe(pipe_slow);
10258 %}
10260 instruct absF_reg(regF dst)
10261 %{
10262 match(Set dst (AbsF dst));
10264 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
10265 ins_encode(absF_encoding(dst));
10266 ins_pipe(pipe_slow);
10267 %}
10269 instruct absD_reg(regD dst)
10270 %{
10271 match(Set dst (AbsD dst));
10273 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
10274 "# abs double by sign masking" %}
10275 ins_encode(absD_encoding(dst));
10276 ins_pipe(pipe_slow);
10277 %}
10279 instruct negF_reg(regF dst)
10280 %{
10281 match(Set dst (NegF dst));
10283 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
10284 ins_encode(negF_encoding(dst));
10285 ins_pipe(pipe_slow);
10286 %}
10288 instruct negD_reg(regD dst)
10289 %{
10290 match(Set dst (NegD dst));
10292 format %{ "xorpd $dst, [0x8000000000000000]\t"
10293 "# neg double by sign flipping" %}
10294 ins_encode(negD_encoding(dst));
10295 ins_pipe(pipe_slow);
10296 %}
10298 // -----------Trig and Trancendental Instructions------------------------------
10299 instruct cosD_reg(regD dst) %{
10300 match(Set dst (CosD dst));
10302 format %{ "dcos $dst\n\t" %}
10303 opcode(0xD9, 0xFF);
10304 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10305 ins_pipe( pipe_slow );
10306 %}
10308 instruct sinD_reg(regD dst) %{
10309 match(Set dst (SinD dst));
10311 format %{ "dsin $dst\n\t" %}
10312 opcode(0xD9, 0xFE);
10313 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10314 ins_pipe( pipe_slow );
10315 %}
10317 instruct tanD_reg(regD dst) %{
10318 match(Set dst (TanD dst));
10320 format %{ "dtan $dst\n\t" %}
10321 ins_encode( Push_SrcXD(dst),
10322 Opcode(0xD9), Opcode(0xF2), //fptan
10323 Opcode(0xDD), Opcode(0xD8), //fstp st
10324 Push_ResultXD(dst) );
10325 ins_pipe( pipe_slow );
10326 %}
10328 instruct log10D_reg(regD dst) %{
10329 // The source and result Double operands in XMM registers
10330 match(Set dst (Log10D dst));
10331 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10332 // fyl2x ; compute log_10(2) * log_2(x)
10333 format %{ "fldlg2\t\t\t#Log10\n\t"
10334 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
10335 %}
10336 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
10337 Push_SrcXD(dst),
10338 Opcode(0xD9), Opcode(0xF1), // fyl2x
10339 Push_ResultXD(dst));
10341 ins_pipe( pipe_slow );
10342 %}
10344 instruct logD_reg(regD dst) %{
10345 // The source and result Double operands in XMM registers
10346 match(Set dst (LogD dst));
10347 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10348 // fyl2x ; compute log_e(2) * log_2(x)
10349 format %{ "fldln2\t\t\t#Log_e\n\t"
10350 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
10351 %}
10352 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10353 Push_SrcXD(dst),
10354 Opcode(0xD9), Opcode(0xF1), // fyl2x
10355 Push_ResultXD(dst));
10356 ins_pipe( pipe_slow );
10357 %}
10361 //----------Arithmetic Conversion Instructions---------------------------------
10363 instruct roundFloat_nop(regF dst)
10364 %{
10365 match(Set dst (RoundFloat dst));
10367 ins_cost(0);
10368 ins_encode();
10369 ins_pipe(empty);
10370 %}
10372 instruct roundDouble_nop(regD dst)
10373 %{
10374 match(Set dst (RoundDouble dst));
10376 ins_cost(0);
10377 ins_encode();
10378 ins_pipe(empty);
10379 %}
10381 instruct convF2D_reg_reg(regD dst, regF src)
10382 %{
10383 match(Set dst (ConvF2D src));
10385 format %{ "cvtss2sd $dst, $src" %}
10386 opcode(0xF3, 0x0F, 0x5A);
10387 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10388 ins_pipe(pipe_slow); // XXX
10389 %}
10391 instruct convF2D_reg_mem(regD dst, memory src)
10392 %{
10393 match(Set dst (ConvF2D (LoadF src)));
10395 format %{ "cvtss2sd $dst, $src" %}
10396 opcode(0xF3, 0x0F, 0x5A);
10397 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10398 ins_pipe(pipe_slow); // XXX
10399 %}
10401 instruct convD2F_reg_reg(regF dst, regD src)
10402 %{
10403 match(Set dst (ConvD2F src));
10405 format %{ "cvtsd2ss $dst, $src" %}
10406 opcode(0xF2, 0x0F, 0x5A);
10407 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10408 ins_pipe(pipe_slow); // XXX
10409 %}
10411 instruct convD2F_reg_mem(regF dst, memory src)
10412 %{
10413 match(Set dst (ConvD2F (LoadD src)));
10415 format %{ "cvtsd2ss $dst, $src" %}
10416 opcode(0xF2, 0x0F, 0x5A);
10417 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10418 ins_pipe(pipe_slow); // XXX
10419 %}
10421 // XXX do mem variants
10422 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10423 %{
10424 match(Set dst (ConvF2I src));
10425 effect(KILL cr);
10427 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10428 "cmpl $dst, #0x80000000\n\t"
10429 "jne,s done\n\t"
10430 "subq rsp, #8\n\t"
10431 "movss [rsp], $src\n\t"
10432 "call f2i_fixup\n\t"
10433 "popq $dst\n"
10434 "done: "%}
10435 opcode(0xF3, 0x0F, 0x2C);
10436 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
10437 f2i_fixup(dst, src));
10438 ins_pipe(pipe_slow);
10439 %}
10441 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10442 %{
10443 match(Set dst (ConvF2L src));
10444 effect(KILL cr);
10446 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10447 "cmpq $dst, [0x8000000000000000]\n\t"
10448 "jne,s done\n\t"
10449 "subq rsp, #8\n\t"
10450 "movss [rsp], $src\n\t"
10451 "call f2l_fixup\n\t"
10452 "popq $dst\n"
10453 "done: "%}
10454 opcode(0xF3, 0x0F, 0x2C);
10455 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
10456 f2l_fixup(dst, src));
10457 ins_pipe(pipe_slow);
10458 %}
10460 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10461 %{
10462 match(Set dst (ConvD2I src));
10463 effect(KILL cr);
10465 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10466 "cmpl $dst, #0x80000000\n\t"
10467 "jne,s done\n\t"
10468 "subq rsp, #8\n\t"
10469 "movsd [rsp], $src\n\t"
10470 "call d2i_fixup\n\t"
10471 "popq $dst\n"
10472 "done: "%}
10473 opcode(0xF2, 0x0F, 0x2C);
10474 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
10475 d2i_fixup(dst, src));
10476 ins_pipe(pipe_slow);
10477 %}
10479 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10480 %{
10481 match(Set dst (ConvD2L src));
10482 effect(KILL cr);
10484 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10485 "cmpq $dst, [0x8000000000000000]\n\t"
10486 "jne,s done\n\t"
10487 "subq rsp, #8\n\t"
10488 "movsd [rsp], $src\n\t"
10489 "call d2l_fixup\n\t"
10490 "popq $dst\n"
10491 "done: "%}
10492 opcode(0xF2, 0x0F, 0x2C);
10493 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
10494 d2l_fixup(dst, src));
10495 ins_pipe(pipe_slow);
10496 %}
10498 instruct convI2F_reg_reg(regF dst, rRegI src)
10499 %{
10500 predicate(!UseXmmI2F);
10501 match(Set dst (ConvI2F src));
10503 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10504 opcode(0xF3, 0x0F, 0x2A);
10505 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10506 ins_pipe(pipe_slow); // XXX
10507 %}
10509 instruct convI2F_reg_mem(regF dst, memory src)
10510 %{
10511 match(Set dst (ConvI2F (LoadI src)));
10513 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10514 opcode(0xF3, 0x0F, 0x2A);
10515 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10516 ins_pipe(pipe_slow); // XXX
10517 %}
10519 instruct convI2D_reg_reg(regD dst, rRegI src)
10520 %{
10521 predicate(!UseXmmI2D);
10522 match(Set dst (ConvI2D src));
10524 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10525 opcode(0xF2, 0x0F, 0x2A);
10526 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10527 ins_pipe(pipe_slow); // XXX
10528 %}
10530 instruct convI2D_reg_mem(regD dst, memory src)
10531 %{
10532 match(Set dst (ConvI2D (LoadI src)));
10534 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10535 opcode(0xF2, 0x0F, 0x2A);
10536 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10537 ins_pipe(pipe_slow); // XXX
10538 %}
10540 instruct convXI2F_reg(regF dst, rRegI src)
10541 %{
10542 predicate(UseXmmI2F);
10543 match(Set dst (ConvI2F src));
10545 format %{ "movdl $dst, $src\n\t"
10546 "cvtdq2psl $dst, $dst\t# i2f" %}
10547 ins_encode %{
10548 __ movdl($dst$$XMMRegister, $src$$Register);
10549 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10550 %}
10551 ins_pipe(pipe_slow); // XXX
10552 %}
10554 instruct convXI2D_reg(regD dst, rRegI src)
10555 %{
10556 predicate(UseXmmI2D);
10557 match(Set dst (ConvI2D src));
10559 format %{ "movdl $dst, $src\n\t"
10560 "cvtdq2pdl $dst, $dst\t# i2d" %}
10561 ins_encode %{
10562 __ movdl($dst$$XMMRegister, $src$$Register);
10563 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10564 %}
10565 ins_pipe(pipe_slow); // XXX
10566 %}
10568 instruct convL2F_reg_reg(regF dst, rRegL src)
10569 %{
10570 match(Set dst (ConvL2F src));
10572 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10573 opcode(0xF3, 0x0F, 0x2A);
10574 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
10575 ins_pipe(pipe_slow); // XXX
10576 %}
10578 instruct convL2F_reg_mem(regF dst, memory src)
10579 %{
10580 match(Set dst (ConvL2F (LoadL src)));
10582 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10583 opcode(0xF3, 0x0F, 0x2A);
10584 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
10585 ins_pipe(pipe_slow); // XXX
10586 %}
10588 instruct convL2D_reg_reg(regD dst, rRegL src)
10589 %{
10590 match(Set dst (ConvL2D src));
10592 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10593 opcode(0xF2, 0x0F, 0x2A);
10594 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
10595 ins_pipe(pipe_slow); // XXX
10596 %}
10598 instruct convL2D_reg_mem(regD dst, memory src)
10599 %{
10600 match(Set dst (ConvL2D (LoadL src)));
10602 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10603 opcode(0xF2, 0x0F, 0x2A);
10604 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
10605 ins_pipe(pipe_slow); // XXX
10606 %}
10608 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10609 %{
10610 match(Set dst (ConvI2L src));
10612 ins_cost(125);
10613 format %{ "movslq $dst, $src\t# i2l" %}
10614 opcode(0x63); // needs REX.W
10615 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10616 ins_pipe(ialu_reg_reg);
10617 %}
10619 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10620 // %{
10621 // match(Set dst (ConvI2L src));
10622 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10623 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10624 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10625 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10626 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10627 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10629 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10630 // ins_encode(enc_copy(dst, src));
10631 // // opcode(0x63); // needs REX.W
10632 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10633 // ins_pipe(ialu_reg_reg);
10634 // %}
10636 instruct convI2L_reg_mem(rRegL dst, memory src)
10637 %{
10638 match(Set dst (ConvI2L (LoadI src)));
10640 format %{ "movslq $dst, $src\t# i2l" %}
10641 opcode(0x63); // needs REX.W
10642 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst,src));
10643 ins_pipe(ialu_reg_mem);
10644 %}
10646 // Zero-extend convert int to long
10647 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10648 %{
10649 match(Set dst (AndL (ConvI2L src) mask));
10651 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10652 ins_encode(enc_copy(dst, src));
10653 ins_pipe(ialu_reg_reg);
10654 %}
10656 // Zero-extend convert int to long
10657 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10658 %{
10659 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10661 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10662 opcode(0x8B);
10663 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
10664 ins_pipe(ialu_reg_mem);
10665 %}
10667 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10668 %{
10669 match(Set dst (AndL src mask));
10671 format %{ "movl $dst, $src\t# zero-extend long" %}
10672 ins_encode(enc_copy_always(dst, src));
10673 ins_pipe(ialu_reg_reg);
10674 %}
10676 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10677 %{
10678 match(Set dst (ConvL2I src));
10680 format %{ "movl $dst, $src\t# l2i" %}
10681 ins_encode(enc_copy_always(dst, src));
10682 ins_pipe(ialu_reg_reg);
10683 %}
10686 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10687 match(Set dst (MoveF2I src));
10688 effect(DEF dst, USE src);
10690 ins_cost(125);
10691 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10692 opcode(0x8B);
10693 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
10694 ins_pipe(ialu_reg_mem);
10695 %}
10697 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10698 match(Set dst (MoveI2F src));
10699 effect(DEF dst, USE src);
10701 ins_cost(125);
10702 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10703 opcode(0xF3, 0x0F, 0x10);
10704 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10705 ins_pipe(pipe_slow);
10706 %}
10708 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10709 match(Set dst (MoveD2L src));
10710 effect(DEF dst, USE src);
10712 ins_cost(125);
10713 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10714 opcode(0x8B);
10715 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10716 ins_pipe(ialu_reg_mem);
10717 %}
10719 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10720 predicate(!UseXmmLoadAndClearUpper);
10721 match(Set dst (MoveL2D src));
10722 effect(DEF dst, USE src);
10724 ins_cost(125);
10725 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10726 opcode(0x66, 0x0F, 0x12);
10727 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10728 ins_pipe(pipe_slow);
10729 %}
10731 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10732 predicate(UseXmmLoadAndClearUpper);
10733 match(Set dst (MoveL2D src));
10734 effect(DEF dst, USE src);
10736 ins_cost(125);
10737 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10738 opcode(0xF2, 0x0F, 0x10);
10739 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10740 ins_pipe(pipe_slow);
10741 %}
10744 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10745 match(Set dst (MoveF2I src));
10746 effect(DEF dst, USE src);
10748 ins_cost(95); // XXX
10749 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10750 opcode(0xF3, 0x0F, 0x11);
10751 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
10752 ins_pipe(pipe_slow);
10753 %}
10755 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10756 match(Set dst (MoveI2F src));
10757 effect(DEF dst, USE src);
10759 ins_cost(100);
10760 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10761 opcode(0x89);
10762 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
10763 ins_pipe( ialu_mem_reg );
10764 %}
10766 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10767 match(Set dst (MoveD2L src));
10768 effect(DEF dst, USE src);
10770 ins_cost(95); // XXX
10771 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10772 opcode(0xF2, 0x0F, 0x11);
10773 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
10774 ins_pipe(pipe_slow);
10775 %}
10777 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10778 match(Set dst (MoveL2D src));
10779 effect(DEF dst, USE src);
10781 ins_cost(100);
10782 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10783 opcode(0x89);
10784 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10785 ins_pipe(ialu_mem_reg);
10786 %}
10788 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10789 match(Set dst (MoveF2I src));
10790 effect(DEF dst, USE src);
10791 ins_cost(85);
10792 format %{ "movd $dst,$src\t# MoveF2I" %}
10793 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %}
10794 ins_pipe( pipe_slow );
10795 %}
10797 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10798 match(Set dst (MoveD2L src));
10799 effect(DEF dst, USE src);
10800 ins_cost(85);
10801 format %{ "movd $dst,$src\t# MoveD2L" %}
10802 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %}
10803 ins_pipe( pipe_slow );
10804 %}
10806 // The next instructions have long latency and use Int unit. Set high cost.
10807 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10808 match(Set dst (MoveI2F src));
10809 effect(DEF dst, USE src);
10810 ins_cost(300);
10811 format %{ "movd $dst,$src\t# MoveI2F" %}
10812 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %}
10813 ins_pipe( pipe_slow );
10814 %}
10816 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10817 match(Set dst (MoveL2D src));
10818 effect(DEF dst, USE src);
10819 ins_cost(300);
10820 format %{ "movd $dst,$src\t# MoveL2D" %}
10821 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %}
10822 ins_pipe( pipe_slow );
10823 %}
10825 // Replicate scalar to packed byte (1 byte) values in xmm
10826 instruct Repl8B_reg(regD dst, regD src) %{
10827 match(Set dst (Replicate8B src));
10828 format %{ "MOVDQA $dst,$src\n\t"
10829 "PUNPCKLBW $dst,$dst\n\t"
10830 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10831 ins_encode( pshufd_8x8(dst, src));
10832 ins_pipe( pipe_slow );
10833 %}
10835 // Replicate scalar to packed byte (1 byte) values in xmm
10836 instruct Repl8B_rRegI(regD dst, rRegI src) %{
10837 match(Set dst (Replicate8B src));
10838 format %{ "MOVD $dst,$src\n\t"
10839 "PUNPCKLBW $dst,$dst\n\t"
10840 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10841 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
10842 ins_pipe( pipe_slow );
10843 %}
10845 // Replicate scalar zero to packed byte (1 byte) values in xmm
10846 instruct Repl8B_immI0(regD dst, immI0 zero) %{
10847 match(Set dst (Replicate8B zero));
10848 format %{ "PXOR $dst,$dst\t! replicate8B" %}
10849 ins_encode( pxor(dst, dst));
10850 ins_pipe( fpu_reg_reg );
10851 %}
10853 // Replicate scalar to packed shore (2 byte) values in xmm
10854 instruct Repl4S_reg(regD dst, regD src) %{
10855 match(Set dst (Replicate4S src));
10856 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
10857 ins_encode( pshufd_4x16(dst, src));
10858 ins_pipe( fpu_reg_reg );
10859 %}
10861 // Replicate scalar to packed shore (2 byte) values in xmm
10862 instruct Repl4S_rRegI(regD dst, rRegI src) %{
10863 match(Set dst (Replicate4S src));
10864 format %{ "MOVD $dst,$src\n\t"
10865 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
10866 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
10867 ins_pipe( fpu_reg_reg );
10868 %}
10870 // Replicate scalar zero to packed short (2 byte) values in xmm
10871 instruct Repl4S_immI0(regD dst, immI0 zero) %{
10872 match(Set dst (Replicate4S zero));
10873 format %{ "PXOR $dst,$dst\t! replicate4S" %}
10874 ins_encode( pxor(dst, dst));
10875 ins_pipe( fpu_reg_reg );
10876 %}
10878 // Replicate scalar to packed char (2 byte) values in xmm
10879 instruct Repl4C_reg(regD dst, regD src) %{
10880 match(Set dst (Replicate4C src));
10881 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
10882 ins_encode( pshufd_4x16(dst, src));
10883 ins_pipe( fpu_reg_reg );
10884 %}
10886 // Replicate scalar to packed char (2 byte) values in xmm
10887 instruct Repl4C_rRegI(regD dst, rRegI src) %{
10888 match(Set dst (Replicate4C src));
10889 format %{ "MOVD $dst,$src\n\t"
10890 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
10891 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
10892 ins_pipe( fpu_reg_reg );
10893 %}
10895 // Replicate scalar zero to packed char (2 byte) values in xmm
10896 instruct Repl4C_immI0(regD dst, immI0 zero) %{
10897 match(Set dst (Replicate4C zero));
10898 format %{ "PXOR $dst,$dst\t! replicate4C" %}
10899 ins_encode( pxor(dst, dst));
10900 ins_pipe( fpu_reg_reg );
10901 %}
10903 // Replicate scalar to packed integer (4 byte) values in xmm
10904 instruct Repl2I_reg(regD dst, regD src) %{
10905 match(Set dst (Replicate2I src));
10906 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
10907 ins_encode( pshufd(dst, src, 0x00));
10908 ins_pipe( fpu_reg_reg );
10909 %}
10911 // Replicate scalar to packed integer (4 byte) values in xmm
10912 instruct Repl2I_rRegI(regD dst, rRegI src) %{
10913 match(Set dst (Replicate2I src));
10914 format %{ "MOVD $dst,$src\n\t"
10915 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
10916 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
10917 ins_pipe( fpu_reg_reg );
10918 %}
10920 // Replicate scalar zero to packed integer (2 byte) values in xmm
10921 instruct Repl2I_immI0(regD dst, immI0 zero) %{
10922 match(Set dst (Replicate2I zero));
10923 format %{ "PXOR $dst,$dst\t! replicate2I" %}
10924 ins_encode( pxor(dst, dst));
10925 ins_pipe( fpu_reg_reg );
10926 %}
10928 // Replicate scalar to packed single precision floating point values in xmm
10929 instruct Repl2F_reg(regD dst, regD src) %{
10930 match(Set dst (Replicate2F src));
10931 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10932 ins_encode( pshufd(dst, src, 0xe0));
10933 ins_pipe( fpu_reg_reg );
10934 %}
10936 // Replicate scalar to packed single precision floating point values in xmm
10937 instruct Repl2F_regF(regD dst, regF src) %{
10938 match(Set dst (Replicate2F src));
10939 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10940 ins_encode( pshufd(dst, src, 0xe0));
10941 ins_pipe( fpu_reg_reg );
10942 %}
10944 // Replicate scalar to packed single precision floating point values in xmm
10945 instruct Repl2F_immF0(regD dst, immF0 zero) %{
10946 match(Set dst (Replicate2F zero));
10947 format %{ "PXOR $dst,$dst\t! replicate2F" %}
10948 ins_encode( pxor(dst, dst));
10949 ins_pipe( fpu_reg_reg );
10950 %}
10953 // =======================================================================
10954 // fast clearing of an array
10955 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10956 rFlagsReg cr)
10957 %{
10958 match(Set dummy (ClearArray cnt base));
10959 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10961 format %{ "xorl rax, rax\t# ClearArray:\n\t"
10962 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10963 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
10964 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
10965 ins_pipe(pipe_slow);
10966 %}
10968 instruct string_compare(rdi_RegP str1, rsi_RegP str2, rax_RegI tmp1,
10969 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr)
10970 %{
10971 match(Set result (StrComp str1 str2));
10972 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
10973 //ins_cost(300);
10975 format %{ "String Compare $str1, $str2 -> $result // XXX KILL RAX, RBX" %}
10976 ins_encode( enc_String_Compare() );
10977 ins_pipe( pipe_slow );
10978 %}
10980 // fast array equals
10981 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1,
10982 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) %{
10983 match(Set result (AryEq ary1 ary2));
10984 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr);
10985 //ins_cost(300);
10987 format %{ "Array Equals $ary1,$ary2 -> $result // KILL RAX, RBX" %}
10988 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) );
10989 ins_pipe( pipe_slow );
10990 %}
10992 //----------Control Flow Instructions------------------------------------------
10993 // Signed compare Instructions
10995 // XXX more variants!!
10996 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10997 %{
10998 match(Set cr (CmpI op1 op2));
10999 effect(DEF cr, USE op1, USE op2);
11001 format %{ "cmpl $op1, $op2" %}
11002 opcode(0x3B); /* Opcode 3B /r */
11003 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11004 ins_pipe(ialu_cr_reg_reg);
11005 %}
11007 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11008 %{
11009 match(Set cr (CmpI op1 op2));
11011 format %{ "cmpl $op1, $op2" %}
11012 opcode(0x81, 0x07); /* Opcode 81 /7 */
11013 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11014 ins_pipe(ialu_cr_reg_imm);
11015 %}
11017 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11018 %{
11019 match(Set cr (CmpI op1 (LoadI op2)));
11021 ins_cost(500); // XXX
11022 format %{ "cmpl $op1, $op2" %}
11023 opcode(0x3B); /* Opcode 3B /r */
11024 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11025 ins_pipe(ialu_cr_reg_mem);
11026 %}
11028 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11029 %{
11030 match(Set cr (CmpI src zero));
11032 format %{ "testl $src, $src" %}
11033 opcode(0x85);
11034 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11035 ins_pipe(ialu_cr_reg_imm);
11036 %}
11038 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11039 %{
11040 match(Set cr (CmpI (AndI src con) zero));
11042 format %{ "testl $src, $con" %}
11043 opcode(0xF7, 0x00);
11044 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11045 ins_pipe(ialu_cr_reg_imm);
11046 %}
11048 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11049 %{
11050 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11052 format %{ "testl $src, $mem" %}
11053 opcode(0x85);
11054 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11055 ins_pipe(ialu_cr_reg_mem);
11056 %}
11058 // Unsigned compare Instructions; really, same as signed except they
11059 // produce an rFlagsRegU instead of rFlagsReg.
11060 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11061 %{
11062 match(Set cr (CmpU op1 op2));
11064 format %{ "cmpl $op1, $op2\t# unsigned" %}
11065 opcode(0x3B); /* Opcode 3B /r */
11066 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11067 ins_pipe(ialu_cr_reg_reg);
11068 %}
11070 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11071 %{
11072 match(Set cr (CmpU op1 op2));
11074 format %{ "cmpl $op1, $op2\t# unsigned" %}
11075 opcode(0x81,0x07); /* Opcode 81 /7 */
11076 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11077 ins_pipe(ialu_cr_reg_imm);
11078 %}
11080 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11081 %{
11082 match(Set cr (CmpU op1 (LoadI op2)));
11084 ins_cost(500); // XXX
11085 format %{ "cmpl $op1, $op2\t# unsigned" %}
11086 opcode(0x3B); /* Opcode 3B /r */
11087 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11088 ins_pipe(ialu_cr_reg_mem);
11089 %}
11091 // // // Cisc-spilled version of cmpU_rReg
11092 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11093 // //%{
11094 // // match(Set cr (CmpU (LoadI op1) op2));
11095 // //
11096 // // format %{ "CMPu $op1,$op2" %}
11097 // // ins_cost(500);
11098 // // opcode(0x39); /* Opcode 39 /r */
11099 // // ins_encode( OpcP, reg_mem( op1, op2) );
11100 // //%}
11102 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11103 %{
11104 match(Set cr (CmpU src zero));
11106 format %{ "testl $src, $src\t# unsigned" %}
11107 opcode(0x85);
11108 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11109 ins_pipe(ialu_cr_reg_imm);
11110 %}
11112 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11113 %{
11114 match(Set cr (CmpP op1 op2));
11116 format %{ "cmpq $op1, $op2\t# ptr" %}
11117 opcode(0x3B); /* Opcode 3B /r */
11118 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11119 ins_pipe(ialu_cr_reg_reg);
11120 %}
11122 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11123 %{
11124 match(Set cr (CmpP op1 (LoadP op2)));
11126 ins_cost(500); // XXX
11127 format %{ "cmpq $op1, $op2\t# ptr" %}
11128 opcode(0x3B); /* Opcode 3B /r */
11129 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11130 ins_pipe(ialu_cr_reg_mem);
11131 %}
11133 // // // Cisc-spilled version of cmpP_rReg
11134 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11135 // //%{
11136 // // match(Set cr (CmpP (LoadP op1) op2));
11137 // //
11138 // // format %{ "CMPu $op1,$op2" %}
11139 // // ins_cost(500);
11140 // // opcode(0x39); /* Opcode 39 /r */
11141 // // ins_encode( OpcP, reg_mem( op1, op2) );
11142 // //%}
11144 // XXX this is generalized by compP_rReg_mem???
11145 // Compare raw pointer (used in out-of-heap check).
11146 // Only works because non-oop pointers must be raw pointers
11147 // and raw pointers have no anti-dependencies.
11148 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11149 %{
11150 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
11151 match(Set cr (CmpP op1 (LoadP op2)));
11153 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11154 opcode(0x3B); /* Opcode 3B /r */
11155 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11156 ins_pipe(ialu_cr_reg_mem);
11157 %}
11159 // This will generate a signed flags result. This should be OK since
11160 // any compare to a zero should be eq/neq.
11161 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11162 %{
11163 match(Set cr (CmpP src zero));
11165 format %{ "testq $src, $src\t# ptr" %}
11166 opcode(0x85);
11167 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11168 ins_pipe(ialu_cr_reg_imm);
11169 %}
11171 // This will generate a signed flags result. This should be OK since
11172 // any compare to a zero should be eq/neq.
11173 instruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero)
11174 %{
11175 match(Set cr (CmpP (LoadP op) zero));
11177 ins_cost(500); // XXX
11178 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11179 opcode(0xF7); /* Opcode F7 /0 */
11180 ins_encode(REX_mem_wide(op),
11181 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11182 ins_pipe(ialu_cr_reg_imm);
11183 %}
11186 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11187 %{
11188 match(Set cr (CmpN op1 op2));
11190 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11191 ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %}
11192 ins_pipe(ialu_cr_reg_reg);
11193 %}
11195 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11196 %{
11197 match(Set cr (CmpN src (LoadN mem)));
11199 ins_cost(500); // XXX
11200 format %{ "cmpl $src, mem\t# compressed ptr" %}
11201 ins_encode %{
11202 Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
11203 __ cmpl(as_Register($src$$reg), adr);
11204 %}
11205 ins_pipe(ialu_cr_reg_mem);
11206 %}
11208 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11209 match(Set cr (CmpN src zero));
11211 format %{ "testl $src, $src\t# compressed ptr" %}
11212 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11213 ins_pipe(ialu_cr_reg_imm);
11214 %}
11216 instruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero)
11217 %{
11218 match(Set cr (CmpN (LoadN mem) zero));
11220 ins_cost(500); // XXX
11221 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11222 ins_encode %{
11223 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
11224 __ cmpl(addr, (int)0xFFFFFFFF);
11225 %}
11226 ins_pipe(ialu_cr_reg_mem);
11227 %}
11229 // Yanked all unsigned pointer compare operations.
11230 // Pointer compares are done with CmpP which is already unsigned.
11232 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11233 %{
11234 match(Set cr (CmpL op1 op2));
11236 format %{ "cmpq $op1, $op2" %}
11237 opcode(0x3B); /* Opcode 3B /r */
11238 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11239 ins_pipe(ialu_cr_reg_reg);
11240 %}
11242 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11243 %{
11244 match(Set cr (CmpL op1 op2));
11246 format %{ "cmpq $op1, $op2" %}
11247 opcode(0x81, 0x07); /* Opcode 81 /7 */
11248 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11249 ins_pipe(ialu_cr_reg_imm);
11250 %}
11252 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11253 %{
11254 match(Set cr (CmpL op1 (LoadL op2)));
11256 ins_cost(500); // XXX
11257 format %{ "cmpq $op1, $op2" %}
11258 opcode(0x3B); /* Opcode 3B /r */
11259 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11260 ins_pipe(ialu_cr_reg_mem);
11261 %}
11263 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11264 %{
11265 match(Set cr (CmpL src zero));
11267 format %{ "testq $src, $src" %}
11268 opcode(0x85);
11269 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11270 ins_pipe(ialu_cr_reg_imm);
11271 %}
11273 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11274 %{
11275 match(Set cr (CmpL (AndL src con) zero));
11277 format %{ "testq $src, $con\t# long" %}
11278 opcode(0xF7, 0x00);
11279 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11280 ins_pipe(ialu_cr_reg_imm);
11281 %}
11283 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11284 %{
11285 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11287 format %{ "testq $src, $mem" %}
11288 opcode(0x85);
11289 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11290 ins_pipe(ialu_cr_reg_mem);
11291 %}
11293 // Manifest a CmpL result in an integer register. Very painful.
11294 // This is the test to avoid.
11295 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11296 %{
11297 match(Set dst (CmpL3 src1 src2));
11298 effect(KILL flags);
11300 ins_cost(275); // XXX
11301 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11302 "movl $dst, -1\n\t"
11303 "jl,s done\n\t"
11304 "setne $dst\n\t"
11305 "movzbl $dst, $dst\n\t"
11306 "done:" %}
11307 ins_encode(cmpl3_flag(src1, src2, dst));
11308 ins_pipe(pipe_slow);
11309 %}
11311 //----------Max and Min--------------------------------------------------------
11312 // Min Instructions
11314 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11315 %{
11316 effect(USE_DEF dst, USE src, USE cr);
11318 format %{ "cmovlgt $dst, $src\t# min" %}
11319 opcode(0x0F, 0x4F);
11320 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11321 ins_pipe(pipe_cmov_reg);
11322 %}
11325 instruct minI_rReg(rRegI dst, rRegI src)
11326 %{
11327 match(Set dst (MinI dst src));
11329 ins_cost(200);
11330 expand %{
11331 rFlagsReg cr;
11332 compI_rReg(cr, dst, src);
11333 cmovI_reg_g(dst, src, cr);
11334 %}
11335 %}
11337 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11338 %{
11339 effect(USE_DEF dst, USE src, USE cr);
11341 format %{ "cmovllt $dst, $src\t# max" %}
11342 opcode(0x0F, 0x4C);
11343 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11344 ins_pipe(pipe_cmov_reg);
11345 %}
11348 instruct maxI_rReg(rRegI dst, rRegI src)
11349 %{
11350 match(Set dst (MaxI dst src));
11352 ins_cost(200);
11353 expand %{
11354 rFlagsReg cr;
11355 compI_rReg(cr, dst, src);
11356 cmovI_reg_l(dst, src, cr);
11357 %}
11358 %}
11360 // ============================================================================
11361 // Branch Instructions
11363 // Jump Direct - Label defines a relative address from JMP+1
11364 instruct jmpDir(label labl)
11365 %{
11366 match(Goto);
11367 effect(USE labl);
11369 ins_cost(300);
11370 format %{ "jmp $labl" %}
11371 size(5);
11372 opcode(0xE9);
11373 ins_encode(OpcP, Lbl(labl));
11374 ins_pipe(pipe_jmp);
11375 ins_pc_relative(1);
11376 %}
11378 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11379 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11380 %{
11381 match(If cop cr);
11382 effect(USE labl);
11384 ins_cost(300);
11385 format %{ "j$cop $labl" %}
11386 size(6);
11387 opcode(0x0F, 0x80);
11388 ins_encode(Jcc(cop, labl));
11389 ins_pipe(pipe_jcc);
11390 ins_pc_relative(1);
11391 %}
11393 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11394 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11395 %{
11396 match(CountedLoopEnd cop cr);
11397 effect(USE labl);
11399 ins_cost(300);
11400 format %{ "j$cop $labl\t# loop end" %}
11401 size(6);
11402 opcode(0x0F, 0x80);
11403 ins_encode(Jcc(cop, labl));
11404 ins_pipe(pipe_jcc);
11405 ins_pc_relative(1);
11406 %}
11408 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11409 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl)
11410 %{
11411 match(CountedLoopEnd cop cmp);
11412 effect(USE labl);
11414 ins_cost(300);
11415 format %{ "j$cop,u $labl\t# loop end" %}
11416 size(6);
11417 opcode(0x0F, 0x80);
11418 ins_encode(Jcc(cop, labl));
11419 ins_pipe(pipe_jcc);
11420 ins_pc_relative(1);
11421 %}
11423 // Jump Direct Conditional - using unsigned comparison
11424 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl)
11425 %{
11426 match(If cop cmp);
11427 effect(USE labl);
11429 ins_cost(300);
11430 format %{ "j$cop,u $labl" %}
11431 size(6);
11432 opcode(0x0F, 0x80);
11433 ins_encode(Jcc(cop, labl));
11434 ins_pipe(pipe_jcc);
11435 ins_pc_relative(1);
11436 %}
11438 // ============================================================================
11439 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11440 // superklass array for an instance of the superklass. Set a hidden
11441 // internal cache on a hit (cache is checked with exposed code in
11442 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11443 // encoding ALSO sets flags.
11445 instruct partialSubtypeCheck(rdi_RegP result,
11446 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11447 rFlagsReg cr)
11448 %{
11449 match(Set result (PartialSubtypeCheck sub super));
11450 effect(KILL rcx, KILL cr);
11452 ins_cost(1100); // slightly larger than the next version
11453 format %{ "cmpq rax, rsi\n\t"
11454 "jeq,s hit\n\t"
11455 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
11456 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11457 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11458 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11459 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11460 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
11461 "hit:\n\t"
11462 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11463 "miss:\t" %}
11465 opcode(0x1); // Force a XOR of RDI
11466 ins_encode(enc_PartialSubtypeCheck());
11467 ins_pipe(pipe_slow);
11468 %}
11470 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11471 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11472 immP0 zero,
11473 rdi_RegP result)
11474 %{
11475 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11476 predicate(!UseCompressedOops); // decoding oop kills condition codes
11477 effect(KILL rcx, KILL result);
11479 ins_cost(1000);
11480 format %{ "cmpq rax, rsi\n\t"
11481 "jeq,s miss\t# Actually a hit; we are done.\n\t"
11482 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
11483 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11484 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11485 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11486 "jne,s miss\t\t# Missed: flags nz\n\t"
11487 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
11488 "miss:\t" %}
11490 opcode(0x0); // No need to XOR RDI
11491 ins_encode(enc_PartialSubtypeCheck());
11492 ins_pipe(pipe_slow);
11493 %}
11495 // ============================================================================
11496 // Branch Instructions -- short offset versions
11497 //
11498 // These instructions are used to replace jumps of a long offset (the default
11499 // match) with jumps of a shorter offset. These instructions are all tagged
11500 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11501 // match rules in general matching. Instead, the ADLC generates a conversion
11502 // method in the MachNode which can be used to do in-place replacement of the
11503 // long variant with the shorter variant. The compiler will determine if a
11504 // branch can be taken by the is_short_branch_offset() predicate in the machine
11505 // specific code section of the file.
11507 // Jump Direct - Label defines a relative address from JMP+1
11508 instruct jmpDir_short(label labl)
11509 %{
11510 match(Goto);
11511 effect(USE labl);
11513 ins_cost(300);
11514 format %{ "jmp,s $labl" %}
11515 size(2);
11516 opcode(0xEB);
11517 ins_encode(OpcP, LblShort(labl));
11518 ins_pipe(pipe_jmp);
11519 ins_pc_relative(1);
11520 ins_short_branch(1);
11521 %}
11523 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11524 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl)
11525 %{
11526 match(If cop cr);
11527 effect(USE labl);
11529 ins_cost(300);
11530 format %{ "j$cop,s $labl" %}
11531 size(2);
11532 opcode(0x70);
11533 ins_encode(JccShort(cop, labl));
11534 ins_pipe(pipe_jcc);
11535 ins_pc_relative(1);
11536 ins_short_branch(1);
11537 %}
11539 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11540 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl)
11541 %{
11542 match(CountedLoopEnd cop cr);
11543 effect(USE labl);
11545 ins_cost(300);
11546 format %{ "j$cop,s $labl" %}
11547 size(2);
11548 opcode(0x70);
11549 ins_encode(JccShort(cop, labl));
11550 ins_pipe(pipe_jcc);
11551 ins_pc_relative(1);
11552 ins_short_branch(1);
11553 %}
11555 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11556 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl)
11557 %{
11558 match(CountedLoopEnd cop cmp);
11559 effect(USE labl);
11561 ins_cost(300);
11562 format %{ "j$cop,us $labl" %}
11563 size(2);
11564 opcode(0x70);
11565 ins_encode(JccShort(cop, labl));
11566 ins_pipe(pipe_jcc);
11567 ins_pc_relative(1);
11568 ins_short_branch(1);
11569 %}
11571 // Jump Direct Conditional - using unsigned comparison
11572 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl)
11573 %{
11574 match(If cop cmp);
11575 effect(USE labl);
11577 ins_cost(300);
11578 format %{ "j$cop,us $labl" %}
11579 size(2);
11580 opcode(0x70);
11581 ins_encode(JccShort(cop, labl));
11582 ins_pipe(pipe_jcc);
11583 ins_pc_relative(1);
11584 ins_short_branch(1);
11585 %}
11587 // ============================================================================
11588 // inlined locking and unlocking
11590 instruct cmpFastLock(rFlagsReg cr,
11591 rRegP object, rRegP box, rax_RegI tmp, rRegP scr)
11592 %{
11593 match(Set cr (FastLock object box));
11594 effect(TEMP tmp, TEMP scr);
11596 ins_cost(300);
11597 format %{ "fastlock $object,$box,$tmp,$scr" %}
11598 ins_encode(Fast_Lock(object, box, tmp, scr));
11599 ins_pipe(pipe_slow);
11600 ins_pc_relative(1);
11601 %}
11603 instruct cmpFastUnlock(rFlagsReg cr,
11604 rRegP object, rax_RegP box, rRegP tmp)
11605 %{
11606 match(Set cr (FastUnlock object box));
11607 effect(TEMP tmp);
11609 ins_cost(300);
11610 format %{ "fastunlock $object, $box, $tmp" %}
11611 ins_encode(Fast_Unlock(object, box, tmp));
11612 ins_pipe(pipe_slow);
11613 ins_pc_relative(1);
11614 %}
11617 // ============================================================================
11618 // Safepoint Instructions
11619 instruct safePoint_poll(rFlagsReg cr)
11620 %{
11621 match(SafePoint);
11622 effect(KILL cr);
11624 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11625 "# Safepoint: poll for GC" %}
11626 size(6); // Opcode + ModRM + Disp32 == 6 bytes
11627 ins_cost(125);
11628 ins_encode(enc_safepoint_poll);
11629 ins_pipe(ialu_reg_mem);
11630 %}
11632 // ============================================================================
11633 // Procedure Call/Return Instructions
11634 // Call Java Static Instruction
11635 // Note: If this code changes, the corresponding ret_addr_offset() and
11636 // compute_padding() functions will have to be adjusted.
11637 instruct CallStaticJavaDirect(method meth)
11638 %{
11639 match(CallStaticJava);
11640 effect(USE meth);
11642 ins_cost(300);
11643 format %{ "call,static " %}
11644 opcode(0xE8); /* E8 cd */
11645 ins_encode(Java_Static_Call(meth), call_epilog);
11646 ins_pipe(pipe_slow);
11647 ins_pc_relative(1);
11648 ins_alignment(4);
11649 %}
11651 // Call Java Dynamic Instruction
11652 // Note: If this code changes, the corresponding ret_addr_offset() and
11653 // compute_padding() functions will have to be adjusted.
11654 instruct CallDynamicJavaDirect(method meth)
11655 %{
11656 match(CallDynamicJava);
11657 effect(USE meth);
11659 ins_cost(300);
11660 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11661 "call,dynamic " %}
11662 opcode(0xE8); /* E8 cd */
11663 ins_encode(Java_Dynamic_Call(meth), call_epilog);
11664 ins_pipe(pipe_slow);
11665 ins_pc_relative(1);
11666 ins_alignment(4);
11667 %}
11669 // Call Runtime Instruction
11670 instruct CallRuntimeDirect(method meth)
11671 %{
11672 match(CallRuntime);
11673 effect(USE meth);
11675 ins_cost(300);
11676 format %{ "call,runtime " %}
11677 opcode(0xE8); /* E8 cd */
11678 ins_encode(Java_To_Runtime(meth));
11679 ins_pipe(pipe_slow);
11680 ins_pc_relative(1);
11681 %}
11683 // Call runtime without safepoint
11684 instruct CallLeafDirect(method meth)
11685 %{
11686 match(CallLeaf);
11687 effect(USE meth);
11689 ins_cost(300);
11690 format %{ "call_leaf,runtime " %}
11691 opcode(0xE8); /* E8 cd */
11692 ins_encode(Java_To_Runtime(meth));
11693 ins_pipe(pipe_slow);
11694 ins_pc_relative(1);
11695 %}
11697 // Call runtime without safepoint
11698 instruct CallLeafNoFPDirect(method meth)
11699 %{
11700 match(CallLeafNoFP);
11701 effect(USE meth);
11703 ins_cost(300);
11704 format %{ "call_leaf_nofp,runtime " %}
11705 opcode(0xE8); /* E8 cd */
11706 ins_encode(Java_To_Runtime(meth));
11707 ins_pipe(pipe_slow);
11708 ins_pc_relative(1);
11709 %}
11711 // Return Instruction
11712 // Remove the return address & jump to it.
11713 // Notice: We always emit a nop after a ret to make sure there is room
11714 // for safepoint patching
11715 instruct Ret()
11716 %{
11717 match(Return);
11719 format %{ "ret" %}
11720 opcode(0xC3);
11721 ins_encode(OpcP);
11722 ins_pipe(pipe_jmp);
11723 %}
11725 // Tail Call; Jump from runtime stub to Java code.
11726 // Also known as an 'interprocedural jump'.
11727 // Target of jump will eventually return to caller.
11728 // TailJump below removes the return address.
11729 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11730 %{
11731 match(TailCall jump_target method_oop);
11733 ins_cost(300);
11734 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11735 opcode(0xFF, 0x4); /* Opcode FF /4 */
11736 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11737 ins_pipe(pipe_jmp);
11738 %}
11740 // Tail Jump; remove the return address; jump to target.
11741 // TailCall above leaves the return address around.
11742 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11743 %{
11744 match(TailJump jump_target ex_oop);
11746 ins_cost(300);
11747 format %{ "popq rdx\t# pop return address\n\t"
11748 "jmp $jump_target" %}
11749 opcode(0xFF, 0x4); /* Opcode FF /4 */
11750 ins_encode(Opcode(0x5a), // popq rdx
11751 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11752 ins_pipe(pipe_jmp);
11753 %}
11755 // Create exception oop: created by stack-crawling runtime code.
11756 // Created exception is now available to this handler, and is setup
11757 // just prior to jumping to this handler. No code emitted.
11758 instruct CreateException(rax_RegP ex_oop)
11759 %{
11760 match(Set ex_oop (CreateEx));
11762 size(0);
11763 // use the following format syntax
11764 format %{ "# exception oop is in rax; no code emitted" %}
11765 ins_encode();
11766 ins_pipe(empty);
11767 %}
11769 // Rethrow exception:
11770 // The exception oop will come in the first argument position.
11771 // Then JUMP (not call) to the rethrow stub code.
11772 instruct RethrowException()
11773 %{
11774 match(Rethrow);
11776 // use the following format syntax
11777 format %{ "jmp rethrow_stub" %}
11778 ins_encode(enc_rethrow);
11779 ins_pipe(pipe_jmp);
11780 %}
11783 //----------PEEPHOLE RULES-----------------------------------------------------
11784 // These must follow all instruction definitions as they use the names
11785 // defined in the instructions definitions.
11786 //
11787 // peepmatch ( root_instr_name [precerding_instruction]* );
11788 //
11789 // peepconstraint %{
11790 // (instruction_number.operand_name relational_op instruction_number.operand_name
11791 // [, ...] );
11792 // // instruction numbers are zero-based using left to right order in peepmatch
11793 //
11794 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11795 // // provide an instruction_number.operand_name for each operand that appears
11796 // // in the replacement instruction's match rule
11797 //
11798 // ---------VM FLAGS---------------------------------------------------------
11799 //
11800 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11801 //
11802 // Each peephole rule is given an identifying number starting with zero and
11803 // increasing by one in the order seen by the parser. An individual peephole
11804 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11805 // on the command-line.
11806 //
11807 // ---------CURRENT LIMITATIONS----------------------------------------------
11808 //
11809 // Only match adjacent instructions in same basic block
11810 // Only equality constraints
11811 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11812 // Only one replacement instruction
11813 //
11814 // ---------EXAMPLE----------------------------------------------------------
11815 //
11816 // // pertinent parts of existing instructions in architecture description
11817 // instruct movI(rRegI dst, rRegI src)
11818 // %{
11819 // match(Set dst (CopyI src));
11820 // %}
11821 //
11822 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11823 // %{
11824 // match(Set dst (AddI dst src));
11825 // effect(KILL cr);
11826 // %}
11827 //
11828 // // Change (inc mov) to lea
11829 // peephole %{
11830 // // increment preceeded by register-register move
11831 // peepmatch ( incI_rReg movI );
11832 // // require that the destination register of the increment
11833 // // match the destination register of the move
11834 // peepconstraint ( 0.dst == 1.dst );
11835 // // construct a replacement instruction that sets
11836 // // the destination to ( move's source register + one )
11837 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11838 // %}
11839 //
11841 // Implementation no longer uses movX instructions since
11842 // machine-independent system no longer uses CopyX nodes.
11843 //
11844 // peephole
11845 // %{
11846 // peepmatch (incI_rReg movI);
11847 // peepconstraint (0.dst == 1.dst);
11848 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11849 // %}
11851 // peephole
11852 // %{
11853 // peepmatch (decI_rReg movI);
11854 // peepconstraint (0.dst == 1.dst);
11855 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11856 // %}
11858 // peephole
11859 // %{
11860 // peepmatch (addI_rReg_imm movI);
11861 // peepconstraint (0.dst == 1.dst);
11862 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11863 // %}
11865 // peephole
11866 // %{
11867 // peepmatch (incL_rReg movL);
11868 // peepconstraint (0.dst == 1.dst);
11869 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11870 // %}
11872 // peephole
11873 // %{
11874 // peepmatch (decL_rReg movL);
11875 // peepconstraint (0.dst == 1.dst);
11876 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11877 // %}
11879 // peephole
11880 // %{
11881 // peepmatch (addL_rReg_imm movL);
11882 // peepconstraint (0.dst == 1.dst);
11883 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11884 // %}
11886 // peephole
11887 // %{
11888 // peepmatch (addP_rReg_imm movP);
11889 // peepconstraint (0.dst == 1.dst);
11890 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11891 // %}
11893 // // Change load of spilled value to only a spill
11894 // instruct storeI(memory mem, rRegI src)
11895 // %{
11896 // match(Set mem (StoreI mem src));
11897 // %}
11898 //
11899 // instruct loadI(rRegI dst, memory mem)
11900 // %{
11901 // match(Set dst (LoadI mem));
11902 // %}
11903 //
11905 peephole
11906 %{
11907 peepmatch (loadI storeI);
11908 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11909 peepreplace (storeI(1.mem 1.mem 1.src));
11910 %}
11912 peephole
11913 %{
11914 peepmatch (loadL storeL);
11915 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11916 peepreplace (storeL(1.mem 1.mem 1.src));
11917 %}
11919 //----------SMARTSPILL RULES---------------------------------------------------
11920 // These must follow all instruction definitions as they use the names
11921 // defined in the instructions definitions.
