Fri, 21 Jun 2013 15:56:24 -0700
Merge
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "opto/vectornode.hpp"
39 #include "runtime/atomic.hpp"
40 #include "runtime/os.hpp"
41 #ifdef TARGET_ARCH_MODEL_x86_32
42 # include "adfiles/ad_x86_32.hpp"
43 #endif
44 #ifdef TARGET_ARCH_MODEL_x86_64
45 # include "adfiles/ad_x86_64.hpp"
46 #endif
47 #ifdef TARGET_ARCH_MODEL_sparc
48 # include "adfiles/ad_sparc.hpp"
49 #endif
50 #ifdef TARGET_ARCH_MODEL_zero
51 # include "adfiles/ad_zero.hpp"
52 #endif
53 #ifdef TARGET_ARCH_MODEL_arm
54 # include "adfiles/ad_arm.hpp"
55 #endif
56 #ifdef TARGET_ARCH_MODEL_ppc_32
57 # include "adfiles/ad_ppc_32.hpp"
58 #endif
59 #ifdef TARGET_ARCH_MODEL_ppc_64
60 # include "adfiles/ad_ppc_64.hpp"
61 #endif
63 OptoReg::Name OptoReg::c_frame_pointer;
65 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
66 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
67 RegMask Matcher::STACK_ONLY_mask;
68 RegMask Matcher::c_frame_ptr_mask;
69 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
70 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
72 //---------------------------Matcher-------------------------------------------
73 Matcher::Matcher( Node_List &proj_list ) :
74 PhaseTransform( Phase::Ins_Select ),
75 #ifdef ASSERT
76 _old2new_map(C->comp_arena()),
77 _new2old_map(C->comp_arena()),
78 #endif
79 _shared_nodes(C->comp_arena()),
80 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
81 _swallowed(swallowed),
82 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
83 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
84 _must_clone(must_clone), _proj_list(proj_list),
85 _register_save_policy(register_save_policy),
86 _c_reg_save_policy(c_reg_save_policy),
87 _register_save_type(register_save_type),
88 _ruleName(ruleName),
89 _allocation_started(false),
90 _states_arena(Chunk::medium_size),
91 _visited(&_states_arena),
92 _shared(&_states_arena),
93 _dontcare(&_states_arena) {
94 C->set_matcher(this);
96 idealreg2spillmask [Op_RegI] = NULL;
97 idealreg2spillmask [Op_RegN] = NULL;
98 idealreg2spillmask [Op_RegL] = NULL;
99 idealreg2spillmask [Op_RegF] = NULL;
100 idealreg2spillmask [Op_RegD] = NULL;
101 idealreg2spillmask [Op_RegP] = NULL;
102 idealreg2spillmask [Op_VecS] = NULL;
103 idealreg2spillmask [Op_VecD] = NULL;
104 idealreg2spillmask [Op_VecX] = NULL;
105 idealreg2spillmask [Op_VecY] = NULL;
107 idealreg2debugmask [Op_RegI] = NULL;
108 idealreg2debugmask [Op_RegN] = NULL;
109 idealreg2debugmask [Op_RegL] = NULL;
110 idealreg2debugmask [Op_RegF] = NULL;
111 idealreg2debugmask [Op_RegD] = NULL;
112 idealreg2debugmask [Op_RegP] = NULL;
113 idealreg2debugmask [Op_VecS] = NULL;
114 idealreg2debugmask [Op_VecD] = NULL;
115 idealreg2debugmask [Op_VecX] = NULL;
116 idealreg2debugmask [Op_VecY] = NULL;
118 idealreg2mhdebugmask[Op_RegI] = NULL;
119 idealreg2mhdebugmask[Op_RegN] = NULL;
120 idealreg2mhdebugmask[Op_RegL] = NULL;
121 idealreg2mhdebugmask[Op_RegF] = NULL;
122 idealreg2mhdebugmask[Op_RegD] = NULL;
123 idealreg2mhdebugmask[Op_RegP] = NULL;
124 idealreg2mhdebugmask[Op_VecS] = NULL;
125 idealreg2mhdebugmask[Op_VecD] = NULL;
126 idealreg2mhdebugmask[Op_VecX] = NULL;
127 idealreg2mhdebugmask[Op_VecY] = NULL;
129 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
130 }
132 //------------------------------warp_incoming_stk_arg------------------------
133 // This warps a VMReg into an OptoReg::Name
134 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
135 OptoReg::Name warped;
136 if( reg->is_stack() ) { // Stack slot argument?
137 warped = OptoReg::add(_old_SP, reg->reg2stack() );
138 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
139 if( warped >= _in_arg_limit )
140 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
141 if (!RegMask::can_represent_arg(warped)) {
142 // the compiler cannot represent this method's calling sequence
143 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
144 return OptoReg::Bad;
145 }
146 return warped;
147 }
148 return OptoReg::as_OptoReg(reg);
149 }
151 //---------------------------compute_old_SP------------------------------------
152 OptoReg::Name Compile::compute_old_SP() {
153 int fixed = fixed_slots();
154 int preserve = in_preserve_stack_slots();
155 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
156 }
160 #ifdef ASSERT
161 void Matcher::verify_new_nodes_only(Node* xroot) {
162 // Make sure that the new graph only references new nodes
163 ResourceMark rm;
164 Unique_Node_List worklist;
165 VectorSet visited(Thread::current()->resource_area());
166 worklist.push(xroot);
167 while (worklist.size() > 0) {
168 Node* n = worklist.pop();
169 visited <<= n->_idx;
170 assert(C->node_arena()->contains(n), "dead node");
171 for (uint j = 0; j < n->req(); j++) {
172 Node* in = n->in(j);
173 if (in != NULL) {
174 assert(C->node_arena()->contains(in), "dead node");
175 if (!visited.test(in->_idx)) {
176 worklist.push(in);
177 }
178 }
179 }
180 }
181 }
182 #endif
185 //---------------------------match---------------------------------------------
186 void Matcher::match( ) {
187 if( MaxLabelRootDepth < 100 ) { // Too small?
188 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
189 MaxLabelRootDepth = 100;
190 }
191 // One-time initialization of some register masks.
192 init_spill_mask( C->root()->in(1) );
193 _return_addr_mask = return_addr();
194 #ifdef _LP64
195 // Pointers take 2 slots in 64-bit land
196 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
197 #endif
199 // Map a Java-signature return type into return register-value
200 // machine registers for 0, 1 and 2 returned values.
201 const TypeTuple *range = C->tf()->range();
202 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
203 // Get ideal-register return type
204 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
205 // Get machine return register
206 uint sop = C->start()->Opcode();
207 OptoRegPair regs = return_value(ireg, false);
209 // And mask for same
210 _return_value_mask = RegMask(regs.first());
211 if( OptoReg::is_valid(regs.second()) )
212 _return_value_mask.Insert(regs.second());
213 }
215 // ---------------
216 // Frame Layout
218 // Need the method signature to determine the incoming argument types,
219 // because the types determine which registers the incoming arguments are
220 // in, and this affects the matched code.
221 const TypeTuple *domain = C->tf()->domain();
222 uint argcnt = domain->cnt() - TypeFunc::Parms;
223 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
224 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
225 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
226 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
227 uint i;
228 for( i = 0; i<argcnt; i++ ) {
229 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
230 }
232 // Pass array of ideal registers and length to USER code (from the AD file)
233 // that will convert this to an array of register numbers.
234 const StartNode *start = C->start();
235 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
236 #ifdef ASSERT
237 // Sanity check users' calling convention. Real handy while trying to
238 // get the initial port correct.
239 { for (uint i = 0; i<argcnt; i++) {
240 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
241 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
242 _parm_regs[i].set_bad();
243 continue;
244 }
245 VMReg parm_reg = vm_parm_regs[i].first();
246 assert(parm_reg->is_valid(), "invalid arg?");
247 if (parm_reg->is_reg()) {
248 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
249 assert(can_be_java_arg(opto_parm_reg) ||
250 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
251 opto_parm_reg == inline_cache_reg(),
252 "parameters in register must be preserved by runtime stubs");
253 }
254 for (uint j = 0; j < i; j++) {
255 assert(parm_reg != vm_parm_regs[j].first(),
256 "calling conv. must produce distinct regs");
257 }
258 }
259 }
260 #endif
262 // Do some initial frame layout.
264 // Compute the old incoming SP (may be called FP) as
265 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
266 _old_SP = C->compute_old_SP();
267 assert( is_even(_old_SP), "must be even" );
269 // Compute highest incoming stack argument as
270 // _old_SP + out_preserve_stack_slots + incoming argument size.
271 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
272 assert( is_even(_in_arg_limit), "out_preserve must be even" );
273 for( i = 0; i < argcnt; i++ ) {
274 // Permit args to have no register
275 _calling_convention_mask[i].Clear();
276 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
277 continue;
278 }
279 // calling_convention returns stack arguments as a count of
280 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
281 // the allocators point of view, taking into account all the
282 // preserve area, locks & pad2.
284 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
285 if( OptoReg::is_valid(reg1))
286 _calling_convention_mask[i].Insert(reg1);
288 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
289 if( OptoReg::is_valid(reg2))
290 _calling_convention_mask[i].Insert(reg2);
292 // Saved biased stack-slot register number
293 _parm_regs[i].set_pair(reg2, reg1);
294 }
296 // Finally, make sure the incoming arguments take up an even number of
297 // words, in case the arguments or locals need to contain doubleword stack
298 // slots. The rest of the system assumes that stack slot pairs (in
299 // particular, in the spill area) which look aligned will in fact be
300 // aligned relative to the stack pointer in the target machine. Double
301 // stack slots will always be allocated aligned.
302 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
304 // Compute highest outgoing stack argument as
305 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
306 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
307 assert( is_even(_out_arg_limit), "out_preserve must be even" );
309 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
310 // the compiler cannot represent this method's calling sequence
311 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
312 }
314 if (C->failing()) return; // bailed out on incoming arg failure
316 // ---------------
317 // Collect roots of matcher trees. Every node for which
318 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
319 // can be a valid interior of some tree.
320 find_shared( C->root() );
321 find_shared( C->top() );
323 C->print_method(PHASE_BEFORE_MATCHING);
325 // Create new ideal node ConP #NULL even if it does exist in old space
326 // to avoid false sharing if the corresponding mach node is not used.
327 // The corresponding mach node is only used in rare cases for derived
328 // pointers.
329 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
331 // Swap out to old-space; emptying new-space
332 Arena *old = C->node_arena()->move_contents(C->old_arena());
334 // Save debug and profile information for nodes in old space:
335 _old_node_note_array = C->node_note_array();
336 if (_old_node_note_array != NULL) {
337 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
338 (C->comp_arena(), _old_node_note_array->length(),
339 0, NULL));
340 }
342 // Pre-size the new_node table to avoid the need for range checks.
343 grow_new_node_array(C->unique());
345 // Reset node counter so MachNodes start with _idx at 0
346 int nodes = C->unique(); // save value
347 C->set_unique(0);
348 C->reset_dead_node_list();
350 // Recursively match trees from old space into new space.
351 // Correct leaves of new-space Nodes; they point to old-space.
352 _visited.Clear(); // Clear visit bits for xform call
353 C->set_cached_top_node(xform( C->top(), nodes ));
354 if (!C->failing()) {
355 Node* xroot = xform( C->root(), 1 );
356 if (xroot == NULL) {
357 Matcher::soft_match_failure(); // recursive matching process failed
358 C->record_method_not_compilable("instruction match failed");
359 } else {
360 // During matching shared constants were attached to C->root()
361 // because xroot wasn't available yet, so transfer the uses to
362 // the xroot.
363 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
364 Node* n = C->root()->fast_out(j);
365 if (C->node_arena()->contains(n)) {
366 assert(n->in(0) == C->root(), "should be control user");
367 n->set_req(0, xroot);
368 --j;
369 --jmax;
370 }
371 }
373 // Generate new mach node for ConP #NULL
374 assert(new_ideal_null != NULL, "sanity");
375 _mach_null = match_tree(new_ideal_null);
376 // Don't set control, it will confuse GCM since there are no uses.
377 // The control will be set when this node is used first time
378 // in find_base_for_derived().
379 assert(_mach_null != NULL, "");
381 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
383 #ifdef ASSERT
384 verify_new_nodes_only(xroot);
385 #endif
386 }
387 }
388 if (C->top() == NULL || C->root() == NULL) {
389 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
390 }
391 if (C->failing()) {
392 // delete old;
393 old->destruct_contents();
394 return;
395 }
396 assert( C->top(), "" );
397 assert( C->root(), "" );
398 validate_null_checks();
400 // Now smoke old-space
401 NOT_DEBUG( old->destruct_contents() );
403 // ------------------------
404 // Set up save-on-entry registers
405 Fixup_Save_On_Entry( );
406 }
409 //------------------------------Fixup_Save_On_Entry----------------------------
410 // The stated purpose of this routine is to take care of save-on-entry
411 // registers. However, the overall goal of the Match phase is to convert into
412 // machine-specific instructions which have RegMasks to guide allocation.
413 // So what this procedure really does is put a valid RegMask on each input
414 // to the machine-specific variations of all Return, TailCall and Halt
415 // instructions. It also adds edgs to define the save-on-entry values (and of
416 // course gives them a mask).
418 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
419 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
420 // Do all the pre-defined register masks
421 rms[TypeFunc::Control ] = RegMask::Empty;
422 rms[TypeFunc::I_O ] = RegMask::Empty;
423 rms[TypeFunc::Memory ] = RegMask::Empty;
424 rms[TypeFunc::ReturnAdr] = ret_adr;
425 rms[TypeFunc::FramePtr ] = fp;
426 return rms;
427 }
429 //---------------------------init_first_stack_mask-----------------------------
430 // Create the initial stack mask used by values spilling to the stack.
431 // Disallow any debug info in outgoing argument areas by setting the
432 // initial mask accordingly.
433 void Matcher::init_first_stack_mask() {
435 // Allocate storage for spill masks as masks for the appropriate load type.
436 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
438 idealreg2spillmask [Op_RegN] = &rms[0];
439 idealreg2spillmask [Op_RegI] = &rms[1];
440 idealreg2spillmask [Op_RegL] = &rms[2];
441 idealreg2spillmask [Op_RegF] = &rms[3];
442 idealreg2spillmask [Op_RegD] = &rms[4];
443 idealreg2spillmask [Op_RegP] = &rms[5];
445 idealreg2debugmask [Op_RegN] = &rms[6];
446 idealreg2debugmask [Op_RegI] = &rms[7];
447 idealreg2debugmask [Op_RegL] = &rms[8];
448 idealreg2debugmask [Op_RegF] = &rms[9];
449 idealreg2debugmask [Op_RegD] = &rms[10];
450 idealreg2debugmask [Op_RegP] = &rms[11];
452 idealreg2mhdebugmask[Op_RegN] = &rms[12];
453 idealreg2mhdebugmask[Op_RegI] = &rms[13];
454 idealreg2mhdebugmask[Op_RegL] = &rms[14];
455 idealreg2mhdebugmask[Op_RegF] = &rms[15];
456 idealreg2mhdebugmask[Op_RegD] = &rms[16];
457 idealreg2mhdebugmask[Op_RegP] = &rms[17];
459 idealreg2spillmask [Op_VecS] = &rms[18];
460 idealreg2spillmask [Op_VecD] = &rms[19];
461 idealreg2spillmask [Op_VecX] = &rms[20];
462 idealreg2spillmask [Op_VecY] = &rms[21];
464 OptoReg::Name i;
466 // At first, start with the empty mask
467 C->FIRST_STACK_mask().Clear();
469 // Add in the incoming argument area
470 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
471 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
472 C->FIRST_STACK_mask().Insert(i);
474 // Add in all bits past the outgoing argument area
475 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
476 "must be able to represent all call arguments in reg mask");
477 init = _out_arg_limit;
478 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
479 C->FIRST_STACK_mask().Insert(i);
481 // Finally, set the "infinite stack" bit.
482 C->FIRST_STACK_mask().set_AllStack();
484 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
485 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
486 // Keep spill masks aligned.
487 aligned_stack_mask.clear_to_pairs();
488 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
490 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
491 #ifdef _LP64
492 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
493 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
494 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
495 #else
496 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
497 #endif
498 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
499 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
500 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
501 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
502 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
503 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
504 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
505 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
507 if (Matcher::vector_size_supported(T_BYTE,4)) {
508 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
509 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
510 }
511 if (Matcher::vector_size_supported(T_FLOAT,2)) {
512 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
513 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
514 }
515 if (Matcher::vector_size_supported(T_FLOAT,4)) {
516 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
517 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
518 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
519 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
520 }
521 if (Matcher::vector_size_supported(T_FLOAT,8)) {
522 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
523 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
524 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
525 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
526 }
527 if (UseFPUForSpilling) {
528 // This mask logic assumes that the spill operations are
529 // symmetric and that the registers involved are the same size.
530 // On sparc for instance we may have to use 64 bit moves will
531 // kill 2 registers when used with F0-F31.
532 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
533 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
534 #ifdef _LP64
535 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
536 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
537 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
538 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
539 #else
540 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
541 #ifdef ARM
542 // ARM has support for moving 64bit values between a pair of
543 // integer registers and a double register
544 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
545 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
546 #endif
547 #endif
548 }
550 // Make up debug masks. Any spill slot plus callee-save registers.
551 // Caller-save registers are assumed to be trashable by the various
552 // inline-cache fixup routines.
553 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
554 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
555 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
556 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
557 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
558 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
560 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
561 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
562 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
563 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
564 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
565 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
567 // Prevent stub compilations from attempting to reference
568 // callee-saved registers from debug info
569 bool exclude_soe = !Compile::current()->is_method_compilation();
571 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
572 // registers the caller has to save do not work
573 if( _register_save_policy[i] == 'C' ||
574 _register_save_policy[i] == 'A' ||
575 (_register_save_policy[i] == 'E' && exclude_soe) ) {
576 idealreg2debugmask [Op_RegN]->Remove(i);
577 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
578 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
579 idealreg2debugmask [Op_RegF]->Remove(i); // masks
580 idealreg2debugmask [Op_RegD]->Remove(i);
581 idealreg2debugmask [Op_RegP]->Remove(i);
583 idealreg2mhdebugmask[Op_RegN]->Remove(i);
584 idealreg2mhdebugmask[Op_RegI]->Remove(i);
585 idealreg2mhdebugmask[Op_RegL]->Remove(i);
586 idealreg2mhdebugmask[Op_RegF]->Remove(i);
587 idealreg2mhdebugmask[Op_RegD]->Remove(i);
588 idealreg2mhdebugmask[Op_RegP]->Remove(i);
589 }
590 }
592 // Subtract the register we use to save the SP for MethodHandle
593 // invokes to from the debug mask.
594 const RegMask save_mask = method_handle_invoke_SP_save_mask();
595 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
596 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
597 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
598 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
599 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
600 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
601 }
603 //---------------------------is_save_on_entry----------------------------------
604 bool Matcher::is_save_on_entry( int reg ) {
605 return
606 _register_save_policy[reg] == 'E' ||
607 _register_save_policy[reg] == 'A' || // Save-on-entry register?
608 // Also save argument registers in the trampolining stubs
609 (C->save_argument_registers() && is_spillable_arg(reg));
610 }
612 //---------------------------Fixup_Save_On_Entry-------------------------------
613 void Matcher::Fixup_Save_On_Entry( ) {
614 init_first_stack_mask();
616 Node *root = C->root(); // Short name for root
617 // Count number of save-on-entry registers.
618 uint soe_cnt = number_of_saved_registers();
619 uint i;
621 // Find the procedure Start Node
622 StartNode *start = C->start();
623 assert( start, "Expect a start node" );
625 // Save argument registers in the trampolining stubs
626 if( C->save_argument_registers() )
627 for( i = 0; i < _last_Mach_Reg; i++ )
628 if( is_spillable_arg(i) )
629 soe_cnt++;
631 // Input RegMask array shared by all Returns.
632 // The type for doubles and longs has a count of 2, but
633 // there is only 1 returned value
634 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
635 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
636 // Returns have 0 or 1 returned values depending on call signature.
637 // Return register is specified by return_value in the AD file.
638 if (ret_edge_cnt > TypeFunc::Parms)
639 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
641 // Input RegMask array shared by all Rethrows.
642 uint reth_edge_cnt = TypeFunc::Parms+1;
643 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
644 // Rethrow takes exception oop only, but in the argument 0 slot.
645 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
646 #ifdef _LP64
647 // Need two slots for ptrs in 64-bit land
648 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
649 #endif
651 // Input RegMask array shared by all TailCalls
652 uint tail_call_edge_cnt = TypeFunc::Parms+2;
653 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
655 // Input RegMask array shared by all TailJumps
656 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
657 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
659 // TailCalls have 2 returned values (target & moop), whose masks come
660 // from the usual MachNode/MachOper mechanism. Find a sample
661 // TailCall to extract these masks and put the correct masks into
662 // the tail_call_rms array.
663 for( i=1; i < root->req(); i++ ) {
664 MachReturnNode *m = root->in(i)->as_MachReturn();
665 if( m->ideal_Opcode() == Op_TailCall ) {
666 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
667 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
668 break;
669 }
670 }
672 // TailJumps have 2 returned values (target & ex_oop), whose masks come
673 // from the usual MachNode/MachOper mechanism. Find a sample
674 // TailJump to extract these masks and put the correct masks into
675 // the tail_jump_rms array.
676 for( i=1; i < root->req(); i++ ) {
677 MachReturnNode *m = root->in(i)->as_MachReturn();
678 if( m->ideal_Opcode() == Op_TailJump ) {
679 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
680 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
681 break;
682 }
683 }
685 // Input RegMask array shared by all Halts
686 uint halt_edge_cnt = TypeFunc::Parms;
687 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
689 // Capture the return input masks into each exit flavor
690 for( i=1; i < root->req(); i++ ) {
691 MachReturnNode *exit = root->in(i)->as_MachReturn();
692 switch( exit->ideal_Opcode() ) {
693 case Op_Return : exit->_in_rms = ret_rms; break;
694 case Op_Rethrow : exit->_in_rms = reth_rms; break;
695 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
696 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
697 case Op_Halt : exit->_in_rms = halt_rms; break;
698 default : ShouldNotReachHere();
699 }
700 }
702 // Next unused projection number from Start.
703 int proj_cnt = C->tf()->domain()->cnt();
705 // Do all the save-on-entry registers. Make projections from Start for
706 // them, and give them a use at the exit points. To the allocator, they
707 // look like incoming register arguments.
708 for( i = 0; i < _last_Mach_Reg; i++ ) {
709 if( is_save_on_entry(i) ) {
711 // Add the save-on-entry to the mask array
712 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
713 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
714 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
715 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
716 // Halts need the SOE registers, but only in the stack as debug info.
717 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
718 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
720 Node *mproj;
722 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
723 // into a single RegD.
724 if( (i&1) == 0 &&
725 _register_save_type[i ] == Op_RegF &&
726 _register_save_type[i+1] == Op_RegF &&
727 is_save_on_entry(i+1) ) {
728 // Add other bit for double
729 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
730 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
731 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
732 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
733 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
734 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
735 proj_cnt += 2; // Skip 2 for doubles
736 }
737 else if( (i&1) == 1 && // Else check for high half of double
738 _register_save_type[i-1] == Op_RegF &&
739 _register_save_type[i ] == Op_RegF &&
740 is_save_on_entry(i-1) ) {
741 ret_rms [ ret_edge_cnt] = RegMask::Empty;
742 reth_rms [ reth_edge_cnt] = RegMask::Empty;
743 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
744 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
745 halt_rms [ halt_edge_cnt] = RegMask::Empty;
746 mproj = C->top();
747 }
748 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
749 // into a single RegL.
750 else if( (i&1) == 0 &&
751 _register_save_type[i ] == Op_RegI &&
752 _register_save_type[i+1] == Op_RegI &&
753 is_save_on_entry(i+1) ) {
754 // Add other bit for long
755 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
756 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
757 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
758 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
759 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
760 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
761 proj_cnt += 2; // Skip 2 for longs
762 }
763 else if( (i&1) == 1 && // Else check for high half of long
764 _register_save_type[i-1] == Op_RegI &&
765 _register_save_type[i ] == Op_RegI &&
766 is_save_on_entry(i-1) ) {
767 ret_rms [ ret_edge_cnt] = RegMask::Empty;
768 reth_rms [ reth_edge_cnt] = RegMask::Empty;
769 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
770 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
771 halt_rms [ halt_edge_cnt] = RegMask::Empty;
772 mproj = C->top();
773 } else {
774 // Make a projection for it off the Start
775 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
776 }
778 ret_edge_cnt ++;
779 reth_edge_cnt ++;
780 tail_call_edge_cnt ++;
781 tail_jump_edge_cnt ++;
782 halt_edge_cnt ++;
784 // Add a use of the SOE register to all exit paths
785 for( uint j=1; j < root->req(); j++ )
786 root->in(j)->add_req(mproj);
787 } // End of if a save-on-entry register
788 } // End of for all machine registers
789 }
791 //------------------------------init_spill_mask--------------------------------
792 void Matcher::init_spill_mask( Node *ret ) {
793 if( idealreg2regmask[Op_RegI] ) return; // One time only init
795 OptoReg::c_frame_pointer = c_frame_pointer();
796 c_frame_ptr_mask = c_frame_pointer();
797 #ifdef _LP64
798 // pointers are twice as big
799 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
800 #endif
802 // Start at OptoReg::stack0()
803 STACK_ONLY_mask.Clear();
804 OptoReg::Name init = OptoReg::stack2reg(0);
805 // STACK_ONLY_mask is all stack bits
806 OptoReg::Name i;
807 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
808 STACK_ONLY_mask.Insert(i);
809 // Also set the "infinite stack" bit.
810 STACK_ONLY_mask.set_AllStack();
812 // Copy the register names over into the shared world
813 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
814 // SharedInfo::regName[i] = regName[i];
815 // Handy RegMasks per machine register
816 mreg2regmask[i].Insert(i);
817 }
819 // Grab the Frame Pointer
820 Node *fp = ret->in(TypeFunc::FramePtr);
821 Node *mem = ret->in(TypeFunc::Memory);
822 const TypePtr* atp = TypePtr::BOTTOM;
823 // Share frame pointer while making spill ops
824 set_shared(fp);
826 // Compute generic short-offset Loads
827 #ifdef _LP64
828 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
829 #endif
830 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp));
831 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp));
832 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp));
833 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp));
834 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
835 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
836 spillD != NULL && spillP != NULL, "");
838 // Get the ADLC notion of the right regmask, for each basic type.
839 #ifdef _LP64
840 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
841 #endif
842 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
843 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
844 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
845 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
846 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
848 // Vector regmasks.
849 if (Matcher::vector_size_supported(T_BYTE,4)) {
850 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
851 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
852 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
853 }
854 if (Matcher::vector_size_supported(T_FLOAT,2)) {
855 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
856 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
857 }
858 if (Matcher::vector_size_supported(T_FLOAT,4)) {
859 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
860 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
861 }
862 if (Matcher::vector_size_supported(T_FLOAT,8)) {
863 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
864 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
865 }
866 }
868 #ifdef ASSERT
869 static void match_alias_type(Compile* C, Node* n, Node* m) {
870 if (!VerifyAliases) return; // do not go looking for trouble by default
871 const TypePtr* nat = n->adr_type();
872 const TypePtr* mat = m->adr_type();
873 int nidx = C->get_alias_index(nat);
874 int midx = C->get_alias_index(mat);
875 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
876 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
877 for (uint i = 1; i < n->req(); i++) {
878 Node* n1 = n->in(i);
879 const TypePtr* n1at = n1->adr_type();
880 if (n1at != NULL) {
881 nat = n1at;
882 nidx = C->get_alias_index(n1at);
883 }
884 }
885 }
886 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
887 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
888 switch (n->Opcode()) {
889 case Op_PrefetchRead:
890 case Op_PrefetchWrite:
891 case Op_PrefetchAllocation:
892 nidx = Compile::AliasIdxRaw;
893 nat = TypeRawPtr::BOTTOM;
894 break;
895 }
896 }
897 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
898 switch (n->Opcode()) {
899 case Op_ClearArray:
900 midx = Compile::AliasIdxRaw;
901 mat = TypeRawPtr::BOTTOM;
902 break;
903 }
904 }
905 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
906 switch (n->Opcode()) {
907 case Op_Return:
908 case Op_Rethrow:
909 case Op_Halt:
910 case Op_TailCall:
911 case Op_TailJump:
912 nidx = Compile::AliasIdxBot;
913 nat = TypePtr::BOTTOM;
914 break;
915 }
916 }
917 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
918 switch (n->Opcode()) {
919 case Op_StrComp:
920 case Op_StrEquals:
921 case Op_StrIndexOf:
922 case Op_AryEq:
923 case Op_MemBarVolatile:
924 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
925 case Op_EncodeISOArray:
926 nidx = Compile::AliasIdxTop;
927 nat = NULL;
928 break;
929 }
930 }
931 if (nidx != midx) {
932 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
933 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
934 n->dump();
935 m->dump();
936 }
937 assert(C->subsume_loads() && C->must_alias(nat, midx),
938 "must not lose alias info when matching");
939 }
940 }
941 #endif
944 //------------------------------MStack-----------------------------------------
945 // State and MStack class used in xform() and find_shared() iterative methods.
946 enum Node_State { Pre_Visit, // node has to be pre-visited
947 Visit, // visit node
948 Post_Visit, // post-visit node
949 Alt_Post_Visit // alternative post-visit path
950 };
952 class MStack: public Node_Stack {
953 public:
954 MStack(int size) : Node_Stack(size) { }
956 void push(Node *n, Node_State ns) {
957 Node_Stack::push(n, (uint)ns);
958 }
959 void push(Node *n, Node_State ns, Node *parent, int indx) {
960 ++_inode_top;
961 if ((_inode_top + 1) >= _inode_max) grow();
962 _inode_top->node = parent;
963 _inode_top->indx = (uint)indx;
964 ++_inode_top;
965 _inode_top->node = n;
966 _inode_top->indx = (uint)ns;
967 }
968 Node *parent() {
969 pop();
970 return node();
971 }
972 Node_State state() const {
973 return (Node_State)index();
974 }
975 void set_state(Node_State ns) {
976 set_index((uint)ns);
977 }
978 };
981 //------------------------------xform------------------------------------------
982 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
983 // Node in new-space. Given a new-space Node, recursively walk his children.
984 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
985 Node *Matcher::xform( Node *n, int max_stack ) {
986 // Use one stack to keep both: child's node/state and parent's node/index
987 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
988 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
990 while (mstack.is_nonempty()) {
991 n = mstack.node(); // Leave node on stack
992 Node_State nstate = mstack.state();
993 if (nstate == Visit) {
994 mstack.set_state(Post_Visit);
995 Node *oldn = n;
996 // Old-space or new-space check
997 if (!C->node_arena()->contains(n)) {
998 // Old space!
999 Node* m;
1000 if (has_new_node(n)) { // Not yet Label/Reduced
1001 m = new_node(n);
1002 } else {
1003 if (!is_dontcare(n)) { // Matcher can match this guy
1004 // Calls match special. They match alone with no children.
1005 // Their children, the incoming arguments, match normally.
1006 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1007 if (C->failing()) return NULL;
1008 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1009 } else { // Nothing the matcher cares about
1010 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1011 // Convert to machine-dependent projection
1012 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1013 #ifdef ASSERT
1014 _new2old_map.map(m->_idx, n);
1015 #endif
1016 if (m->in(0) != NULL) // m might be top
1017 collect_null_checks(m, n);
1018 } else { // Else just a regular 'ol guy
1019 m = n->clone(); // So just clone into new-space
1020 #ifdef ASSERT
1021 _new2old_map.map(m->_idx, n);
1022 #endif
1023 // Def-Use edges will be added incrementally as Uses
1024 // of this node are matched.
1025 assert(m->outcnt() == 0, "no Uses of this clone yet");
1026 }
1027 }
1029 set_new_node(n, m); // Map old to new
1030 if (_old_node_note_array != NULL) {
1031 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1032 n->_idx);
1033 C->set_node_notes_at(m->_idx, nn);
1034 }
1035 debug_only(match_alias_type(C, n, m));
1036 }
1037 n = m; // n is now a new-space node
1038 mstack.set_node(n);
1039 }
1041 // New space!
1042 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1044 int i;
1045 // Put precedence edges on stack first (match them last).
1046 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1047 Node *m = oldn->in(i);
1048 if (m == NULL) break;
1049 // set -1 to call add_prec() instead of set_req() during Step1
1050 mstack.push(m, Visit, n, -1);
1051 }
1053 // For constant debug info, I'd rather have unmatched constants.
1054 int cnt = n->req();
1055 JVMState* jvms = n->jvms();
1056 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1058 // Now do only debug info. Clone constants rather than matching.
1059 // Constants are represented directly in the debug info without
1060 // the need for executable machine instructions.
1061 // Monitor boxes are also represented directly.
1062 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1063 Node *m = n->in(i); // Get input
1064 int op = m->Opcode();
1065 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1066 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1067 op == Op_ConF || op == Op_ConD || op == Op_ConL
1068 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1069 ) {
1070 m = m->clone();
1071 #ifdef ASSERT
1072 _new2old_map.map(m->_idx, n);
1073 #endif
1074 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1075 mstack.push(m->in(0), Visit, m, 0);
1076 } else {
1077 mstack.push(m, Visit, n, i);
1078 }
1079 }
1081 // And now walk his children, and convert his inputs to new-space.
1082 for( ; i >= 0; --i ) { // For all normal inputs do
1083 Node *m = n->in(i); // Get input
1084 if(m != NULL)
1085 mstack.push(m, Visit, n, i);
1086 }
1088 }
1089 else if (nstate == Post_Visit) {
1090 // Set xformed input
1091 Node *p = mstack.parent();
1092 if (p != NULL) { // root doesn't have parent
1093 int i = (int)mstack.index();
1094 if (i >= 0)
1095 p->set_req(i, n); // required input
1096 else if (i == -1)
1097 p->add_prec(n); // precedence input
1098 else
1099 ShouldNotReachHere();
1100 }
1101 mstack.pop(); // remove processed node from stack
1102 }
1103 else {
1104 ShouldNotReachHere();
1105 }
1106 } // while (mstack.is_nonempty())
1107 return n; // Return new-space Node
1108 }
1110 //------------------------------warp_outgoing_stk_arg------------------------
1111 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1112 // Convert outgoing argument location to a pre-biased stack offset
1113 if (reg->is_stack()) {
1114 OptoReg::Name warped = reg->reg2stack();
1115 // Adjust the stack slot offset to be the register number used
1116 // by the allocator.
1117 warped = OptoReg::add(begin_out_arg_area, warped);
1118 // Keep track of the largest numbered stack slot used for an arg.
1119 // Largest used slot per call-site indicates the amount of stack
1120 // that is killed by the call.
1121 if( warped >= out_arg_limit_per_call )
1122 out_arg_limit_per_call = OptoReg::add(warped,1);
1123 if (!RegMask::can_represent_arg(warped)) {
1124 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1125 return OptoReg::Bad;
1126 }
1127 return warped;
1128 }
1129 return OptoReg::as_OptoReg(reg);
1130 }
1133 //------------------------------match_sfpt-------------------------------------
1134 // Helper function to match call instructions. Calls match special.
1135 // They match alone with no children. Their children, the incoming
1136 // arguments, match normally.
1137 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1138 MachSafePointNode *msfpt = NULL;
1139 MachCallNode *mcall = NULL;
1140 uint cnt;
1141 // Split out case for SafePoint vs Call
1142 CallNode *call;
1143 const TypeTuple *domain;
1144 ciMethod* method = NULL;
1145 bool is_method_handle_invoke = false; // for special kill effects
1146 if( sfpt->is_Call() ) {
1147 call = sfpt->as_Call();
1148 domain = call->tf()->domain();
1149 cnt = domain->cnt();
1151 // Match just the call, nothing else
1152 MachNode *m = match_tree(call);
1153 if (C->failing()) return NULL;
1154 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1156 // Copy data from the Ideal SafePoint to the machine version
1157 mcall = m->as_MachCall();
1159 mcall->set_tf( call->tf());
1160 mcall->set_entry_point(call->entry_point());
1161 mcall->set_cnt( call->cnt());
1163 if( mcall->is_MachCallJava() ) {
1164 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1165 const CallJavaNode *call_java = call->as_CallJava();
1166 method = call_java->method();
1167 mcall_java->_method = method;
1168 mcall_java->_bci = call_java->_bci;
1169 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1170 is_method_handle_invoke = call_java->is_method_handle_invoke();
1171 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1172 if (is_method_handle_invoke) {
1173 C->set_has_method_handle_invokes(true);
1174 }
1175 if( mcall_java->is_MachCallStaticJava() )
1176 mcall_java->as_MachCallStaticJava()->_name =
1177 call_java->as_CallStaticJava()->_name;
1178 if( mcall_java->is_MachCallDynamicJava() )
1179 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1180 call_java->as_CallDynamicJava()->_vtable_index;
1181 }
1182 else if( mcall->is_MachCallRuntime() ) {
1183 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1184 }
1185 msfpt = mcall;
1186 }
1187 // This is a non-call safepoint
1188 else {
1189 call = NULL;
1190 domain = NULL;
1191 MachNode *mn = match_tree(sfpt);
1192 if (C->failing()) return NULL;
1193 msfpt = mn->as_MachSafePoint();
1194 cnt = TypeFunc::Parms;
1195 }
1197 // Advertise the correct memory effects (for anti-dependence computation).
1198 msfpt->set_adr_type(sfpt->adr_type());
1200 // Allocate a private array of RegMasks. These RegMasks are not shared.
1201 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1202 // Empty them all.
1203 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1205 // Do all the pre-defined non-Empty register masks
1206 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1207 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1209 // Place first outgoing argument can possibly be put.
1210 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1211 assert( is_even(begin_out_arg_area), "" );
1212 // Compute max outgoing register number per call site.
1213 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1214 // Calls to C may hammer extra stack slots above and beyond any arguments.
1215 // These are usually backing store for register arguments for varargs.
1216 if( call != NULL && call->is_CallRuntime() )
1217 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1220 // Do the normal argument list (parameters) register masks
1221 int argcnt = cnt - TypeFunc::Parms;
1222 if( argcnt > 0 ) { // Skip it all if we have no args
1223 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1224 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1225 int i;
1226 for( i = 0; i < argcnt; i++ ) {
1227 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1228 }
1229 // V-call to pick proper calling convention
1230 call->calling_convention( sig_bt, parm_regs, argcnt );
1232 #ifdef ASSERT
1233 // Sanity check users' calling convention. Really handy during
1234 // the initial porting effort. Fairly expensive otherwise.
1235 { for (int i = 0; i<argcnt; i++) {
1236 if( !parm_regs[i].first()->is_valid() &&
1237 !parm_regs[i].second()->is_valid() ) continue;
1238 VMReg reg1 = parm_regs[i].first();
1239 VMReg reg2 = parm_regs[i].second();
1240 for (int j = 0; j < i; j++) {
1241 if( !parm_regs[j].first()->is_valid() &&
1242 !parm_regs[j].second()->is_valid() ) continue;
1243 VMReg reg3 = parm_regs[j].first();
1244 VMReg reg4 = parm_regs[j].second();
1245 if( !reg1->is_valid() ) {
1246 assert( !reg2->is_valid(), "valid halvsies" );
1247 } else if( !reg3->is_valid() ) {
1248 assert( !reg4->is_valid(), "valid halvsies" );
1249 } else {
1250 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1251 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1252 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1253 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1254 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1255 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1256 }
1257 }
1258 }
1259 }
1260 #endif
1262 // Visit each argument. Compute its outgoing register mask.
1263 // Return results now can have 2 bits returned.
1264 // Compute max over all outgoing arguments both per call-site
1265 // and over the entire method.
1266 for( i = 0; i < argcnt; i++ ) {
1267 // Address of incoming argument mask to fill in
1268 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1269 if( !parm_regs[i].first()->is_valid() &&
1270 !parm_regs[i].second()->is_valid() ) {
1271 continue; // Avoid Halves
1272 }
1273 // Grab first register, adjust stack slots and insert in mask.
1274 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1275 if (OptoReg::is_valid(reg1))
1276 rm->Insert( reg1 );
1277 // Grab second register (if any), adjust stack slots and insert in mask.
1278 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1279 if (OptoReg::is_valid(reg2))
1280 rm->Insert( reg2 );
1281 } // End of for all arguments
1283 // Compute number of stack slots needed to restore stack in case of
1284 // Pascal-style argument popping.
1285 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1286 }
1288 // Compute the max stack slot killed by any call. These will not be
1289 // available for debug info, and will be used to adjust FIRST_STACK_mask
1290 // after all call sites have been visited.
1291 if( _out_arg_limit < out_arg_limit_per_call)
1292 _out_arg_limit = out_arg_limit_per_call;
1294 if (mcall) {
1295 // Kill the outgoing argument area, including any non-argument holes and
1296 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1297 // Since the max-per-method covers the max-per-call-site and debug info
1298 // is excluded on the max-per-method basis, debug info cannot land in
1299 // this killed area.
1300 uint r_cnt = mcall->tf()->range()->cnt();
1301 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1302 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1303 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1304 } else {
1305 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1306 proj->_rout.Insert(OptoReg::Name(i));
1307 }
1308 if( proj->_rout.is_NotEmpty() )
1309 _proj_list.push(proj);
1310 }
1311 // Transfer the safepoint information from the call to the mcall
1312 // Move the JVMState list
1313 msfpt->set_jvms(sfpt->jvms());
1314 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1315 jvms->set_map(sfpt);
1316 }
1318 // Debug inputs begin just after the last incoming parameter
1319 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1320 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1322 // Move the OopMap
1323 msfpt->_oop_map = sfpt->_oop_map;
1325 // Registers killed by the call are set in the local scheduling pass
1326 // of Global Code Motion.
1327 return msfpt;
1328 }
1330 //---------------------------match_tree----------------------------------------
1331 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1332 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1333 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1334 // a Load's result RegMask for memoization in idealreg2regmask[]
1335 MachNode *Matcher::match_tree( const Node *n ) {
1336 assert( n->Opcode() != Op_Phi, "cannot match" );
1337 assert( !n->is_block_start(), "cannot match" );
1338 // Set the mark for all locally allocated State objects.
1339 // When this call returns, the _states_arena arena will be reset
1340 // freeing all State objects.
1341 ResourceMark rm( &_states_arena );
1343 LabelRootDepth = 0;
1345 // StoreNodes require their Memory input to match any LoadNodes
1346 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1347 #ifdef ASSERT
1348 Node* save_mem_node = _mem_node;
1349 _mem_node = n->is_Store() ? (Node*)n : NULL;
1350 #endif
1351 // State object for root node of match tree
1352 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1353 State *s = new (&_states_arena) State;
1354 s->_kids[0] = NULL;
1355 s->_kids[1] = NULL;
1356 s->_leaf = (Node*)n;
1357 // Label the input tree, allocating labels from top-level arena
1358 Label_Root( n, s, n->in(0), mem );
1359 if (C->failing()) return NULL;
1361 // The minimum cost match for the whole tree is found at the root State
1362 uint mincost = max_juint;
1363 uint cost = max_juint;
1364 uint i;
1365 for( i = 0; i < NUM_OPERANDS; i++ ) {
1366 if( s->valid(i) && // valid entry and
1367 s->_cost[i] < cost && // low cost and
1368 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1369 cost = s->_cost[mincost=i];
1370 }
1371 if (mincost == max_juint) {
1372 #ifndef PRODUCT
1373 tty->print("No matching rule for:");
1374 s->dump();
1375 #endif
1376 Matcher::soft_match_failure();
1377 return NULL;
1378 }
1379 // Reduce input tree based upon the state labels to machine Nodes
1380 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1381 #ifdef ASSERT
1382 _old2new_map.map(n->_idx, m);
1383 _new2old_map.map(m->_idx, (Node*)n);
1384 #endif
1386 // Add any Matcher-ignored edges
1387 uint cnt = n->req();
1388 uint start = 1;
1389 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1390 if( n->is_AddP() ) {
1391 assert( mem == (Node*)1, "" );
1392 start = AddPNode::Base+1;
1393 }
1394 for( i = start; i < cnt; i++ ) {
1395 if( !n->match_edge(i) ) {
1396 if( i < m->req() )
1397 m->ins_req( i, n->in(i) );
1398 else
1399 m->add_req( n->in(i) );
1400 }
1401 }
1403 debug_only( _mem_node = save_mem_node; )
1404 return m;
1405 }
1408 //------------------------------match_into_reg---------------------------------
1409 // Choose to either match this Node in a register or part of the current
1410 // match tree. Return true for requiring a register and false for matching
1411 // as part of the current match tree.
1412 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1414 const Type *t = m->bottom_type();
1416 if (t->singleton()) {
1417 // Never force constants into registers. Allow them to match as
1418 // constants or registers. Copies of the same value will share
1419 // the same register. See find_shared_node.
1420 return false;
1421 } else { // Not a constant
1422 // Stop recursion if they have different Controls.
1423 Node* m_control = m->in(0);
1424 // Control of load's memory can post-dominates load's control.
1425 // So use it since load can't float above its memory.
1426 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1427 if (control && m_control && control != m_control && control != mem_control) {
1429 // Actually, we can live with the most conservative control we
1430 // find, if it post-dominates the others. This allows us to
1431 // pick up load/op/store trees where the load can float a little
1432 // above the store.
1433 Node *x = control;
1434 const uint max_scan = 6; // Arbitrary scan cutoff
1435 uint j;
1436 for (j=0; j<max_scan; j++) {
1437 if (x->is_Region()) // Bail out at merge points
1438 return true;
1439 x = x->in(0);
1440 if (x == m_control) // Does 'control' post-dominate
1441 break; // m->in(0)? If so, we can use it
1442 if (x == mem_control) // Does 'control' post-dominate
1443 break; // mem_control? If so, we can use it
1444 }
1445 if (j == max_scan) // No post-domination before scan end?
1446 return true; // Then break the match tree up
1447 }
1448 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1449 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1450 // These are commonly used in address expressions and can
1451 // efficiently fold into them on X64 in some cases.
1452 return false;
1453 }
1454 }
1456 // Not forceable cloning. If shared, put it into a register.
1457 return shared;
1458 }
1461 //------------------------------Instruction Selection--------------------------
1462 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1463 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1464 // things the Matcher does not match (e.g., Memory), and things with different
1465 // Controls (hence forced into different blocks). We pass in the Control
1466 // selected for this entire State tree.
1468 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1469 // Store and the Load must have identical Memories (as well as identical
1470 // pointers). Since the Matcher does not have anything for Memory (and
1471 // does not handle DAGs), I have to match the Memory input myself. If the
1472 // Tree root is a Store, I require all Loads to have the identical memory.
1473 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1474 // Since Label_Root is a recursive function, its possible that we might run
1475 // out of stack space. See bugs 6272980 & 6227033 for more info.
1476 LabelRootDepth++;
1477 if (LabelRootDepth > MaxLabelRootDepth) {
1478 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1479 return NULL;
1480 }
1481 uint care = 0; // Edges matcher cares about
1482 uint cnt = n->req();
1483 uint i = 0;
1485 // Examine children for memory state
1486 // Can only subsume a child into your match-tree if that child's memory state
1487 // is not modified along the path to another input.
1488 // It is unsafe even if the other inputs are separate roots.
1489 Node *input_mem = NULL;
1490 for( i = 1; i < cnt; i++ ) {
1491 if( !n->match_edge(i) ) continue;
1492 Node *m = n->in(i); // Get ith input
1493 assert( m, "expect non-null children" );
1494 if( m->is_Load() ) {
1495 if( input_mem == NULL ) {
1496 input_mem = m->in(MemNode::Memory);
1497 } else if( input_mem != m->in(MemNode::Memory) ) {
1498 input_mem = NodeSentinel;
1499 }
1500 }
1501 }
1503 for( i = 1; i < cnt; i++ ){// For my children
1504 if( !n->match_edge(i) ) continue;
1505 Node *m = n->in(i); // Get ith input
1506 // Allocate states out of a private arena
1507 State *s = new (&_states_arena) State;
1508 svec->_kids[care++] = s;
1509 assert( care <= 2, "binary only for now" );
1511 // Recursively label the State tree.
1512 s->_kids[0] = NULL;
1513 s->_kids[1] = NULL;
1514 s->_leaf = m;
1516 // Check for leaves of the State Tree; things that cannot be a part of
1517 // the current tree. If it finds any, that value is matched as a
1518 // register operand. If not, then the normal matching is used.
1519 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1520 //
1521 // Stop recursion if this is LoadNode and the root of this tree is a
1522 // StoreNode and the load & store have different memories.
1523 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1524 // Can NOT include the match of a subtree when its memory state
1525 // is used by any of the other subtrees
1526 (input_mem == NodeSentinel) ) {
1527 #ifndef PRODUCT
1528 // Print when we exclude matching due to different memory states at input-loads
1529 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1530 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1531 tty->print_cr("invalid input_mem");
1532 }
1533 #endif
1534 // Switch to a register-only opcode; this value must be in a register
1535 // and cannot be subsumed as part of a larger instruction.
1536 s->DFA( m->ideal_reg(), m );
1538 } else {
1539 // If match tree has no control and we do, adopt it for entire tree
1540 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1541 control = m->in(0); // Pick up control
1542 // Else match as a normal part of the match tree.
1543 control = Label_Root(m,s,control,mem);
1544 if (C->failing()) return NULL;
1545 }
1546 }
1549 // Call DFA to match this node, and return
1550 svec->DFA( n->Opcode(), n );
1552 #ifdef ASSERT
1553 uint x;
1554 for( x = 0; x < _LAST_MACH_OPER; x++ )
1555 if( svec->valid(x) )
1556 break;
1558 if (x >= _LAST_MACH_OPER) {
1559 n->dump();
1560 svec->dump();
1561 assert( false, "bad AD file" );
1562 }
1563 #endif
1564 return control;
1565 }
1568 // Con nodes reduced using the same rule can share their MachNode
1569 // which reduces the number of copies of a constant in the final
1570 // program. The register allocator is free to split uses later to
1571 // split live ranges.
1572 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1573 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1575 // See if this Con has already been reduced using this rule.
1576 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1577 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1578 if (last != NULL && rule == last->rule()) {
1579 // Don't expect control change for DecodeN
1580 if (leaf->is_DecodeNarrowPtr())
1581 return last;
1582 // Get the new space root.
1583 Node* xroot = new_node(C->root());
1584 if (xroot == NULL) {
1585 // This shouldn't happen give the order of matching.
1586 return NULL;
1587 }
1589 // Shared constants need to have their control be root so they
1590 // can be scheduled properly.
1591 Node* control = last->in(0);
1592 if (control != xroot) {
1593 if (control == NULL || control == C->root()) {
1594 last->set_req(0, xroot);
1595 } else {
1596 assert(false, "unexpected control");
1597 return NULL;
1598 }
1599 }
1600 return last;
1601 }
1602 return NULL;
1603 }
1606 //------------------------------ReduceInst-------------------------------------
1607 // Reduce a State tree (with given Control) into a tree of MachNodes.
1608 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1609 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1610 // Each MachNode has a number of complicated MachOper operands; each
1611 // MachOper also covers a further tree of Ideal Nodes.
1613 // The root of the Ideal match tree is always an instruction, so we enter
1614 // the recursion here. After building the MachNode, we need to recurse
1615 // the tree checking for these cases:
1616 // (1) Child is an instruction -
1617 // Build the instruction (recursively), add it as an edge.
1618 // Build a simple operand (register) to hold the result of the instruction.
1619 // (2) Child is an interior part of an instruction -
1620 // Skip over it (do nothing)
1621 // (3) Child is the start of a operand -
1622 // Build the operand, place it inside the instruction
1623 // Call ReduceOper.
1624 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1625 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1627 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1628 if (shared_node != NULL) {
1629 return shared_node;
1630 }
1632 // Build the object to represent this state & prepare for recursive calls
1633 MachNode *mach = s->MachNodeGenerator( rule, C );
1634 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1635 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1636 Node *leaf = s->_leaf;
1637 // Check for instruction or instruction chain rule
1638 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1639 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1640 "duplicating node that's already been matched");
1641 // Instruction
1642 mach->add_req( leaf->in(0) ); // Set initial control
1643 // Reduce interior of complex instruction
1644 ReduceInst_Interior( s, rule, mem, mach, 1 );
1645 } else {
1646 // Instruction chain rules are data-dependent on their inputs
1647 mach->add_req(0); // Set initial control to none
1648 ReduceInst_Chain_Rule( s, rule, mem, mach );
1649 }
1651 // If a Memory was used, insert a Memory edge
1652 if( mem != (Node*)1 ) {
1653 mach->ins_req(MemNode::Memory,mem);
1654 #ifdef ASSERT
1655 // Verify adr type after matching memory operation
1656 const MachOper* oper = mach->memory_operand();
1657 if (oper != NULL && oper != (MachOper*)-1) {
1658 // It has a unique memory operand. Find corresponding ideal mem node.
1659 Node* m = NULL;
1660 if (leaf->is_Mem()) {
1661 m = leaf;
1662 } else {
1663 m = _mem_node;
1664 assert(m != NULL && m->is_Mem(), "expecting memory node");
1665 }
1666 const Type* mach_at = mach->adr_type();
1667 // DecodeN node consumed by an address may have different type
1668 // then its input. Don't compare types for such case.
1669 if (m->adr_type() != mach_at &&
1670 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1671 m->in(MemNode::Address)->is_AddP() &&
1672 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1673 m->in(MemNode::Address)->is_AddP() &&
1674 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1675 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1676 mach_at = m->adr_type();
1677 }
1678 if (m->adr_type() != mach_at) {
1679 m->dump();
1680 tty->print_cr("mach:");
1681 mach->dump(1);
1682 }
1683 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1684 }
1685 #endif
1686 }
1688 // If the _leaf is an AddP, insert the base edge
1689 if( leaf->is_AddP() )
1690 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1692 uint num_proj = _proj_list.size();
1694 // Perform any 1-to-many expansions required
1695 MachNode *ex = mach->Expand(s,_proj_list, mem);
1696 if( ex != mach ) {
1697 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1698 if( ex->in(1)->is_Con() )
1699 ex->in(1)->set_req(0, C->root());
1700 // Remove old node from the graph
1701 for( uint i=0; i<mach->req(); i++ ) {
1702 mach->set_req(i,NULL);
1703 }
1704 #ifdef ASSERT
1705 _new2old_map.map(ex->_idx, s->_leaf);
1706 #endif
1707 }
1709 // PhaseChaitin::fixup_spills will sometimes generate spill code
1710 // via the matcher. By the time, nodes have been wired into the CFG,
1711 // and any further nodes generated by expand rules will be left hanging
1712 // in space, and will not get emitted as output code. Catch this.
1713 // Also, catch any new register allocation constraints ("projections")
1714 // generated belatedly during spill code generation.
1715 if (_allocation_started) {
1716 guarantee(ex == mach, "no expand rules during spill generation");
1717 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1718 }
1720 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1721 // Record the con for sharing
1722 _shared_nodes.map(leaf->_idx, ex);
1723 }
1725 return ex;
1726 }
1728 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1729 // 'op' is what I am expecting to receive
1730 int op = _leftOp[rule];
1731 // Operand type to catch childs result
1732 // This is what my child will give me.
1733 int opnd_class_instance = s->_rule[op];
1734 // Choose between operand class or not.
1735 // This is what I will receive.
1736 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1737 // New rule for child. Chase operand classes to get the actual rule.
1738 int newrule = s->_rule[catch_op];
1740 if( newrule < NUM_OPERANDS ) {
1741 // Chain from operand or operand class, may be output of shared node
1742 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1743 "Bad AD file: Instruction chain rule must chain from operand");
1744 // Insert operand into array of operands for this instruction
1745 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1747 ReduceOper( s, newrule, mem, mach );
1748 } else {
1749 // Chain from the result of an instruction
1750 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1751 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1752 Node *mem1 = (Node*)1;
1753 debug_only(Node *save_mem_node = _mem_node;)
1754 mach->add_req( ReduceInst(s, newrule, mem1) );
1755 debug_only(_mem_node = save_mem_node;)
1756 }
1757 return;
1758 }
1761 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1762 if( s->_leaf->is_Load() ) {
1763 Node *mem2 = s->_leaf->in(MemNode::Memory);
1764 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1765 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1766 mem = mem2;
1767 }
1768 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1769 if( mach->in(0) == NULL )
1770 mach->set_req(0, s->_leaf->in(0));
1771 }
1773 // Now recursively walk the state tree & add operand list.
1774 for( uint i=0; i<2; i++ ) { // binary tree
1775 State *newstate = s->_kids[i];
1776 if( newstate == NULL ) break; // Might only have 1 child
1777 // 'op' is what I am expecting to receive
1778 int op;
1779 if( i == 0 ) {
1780 op = _leftOp[rule];
1781 } else {
1782 op = _rightOp[rule];
1783 }
1784 // Operand type to catch childs result
1785 // This is what my child will give me.
1786 int opnd_class_instance = newstate->_rule[op];
1787 // Choose between operand class or not.
1788 // This is what I will receive.
1789 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1790 // New rule for child. Chase operand classes to get the actual rule.
1791 int newrule = newstate->_rule[catch_op];
1793 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1794 // Operand/operandClass
1795 // Insert operand into array of operands for this instruction
1796 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1797 ReduceOper( newstate, newrule, mem, mach );
1799 } else { // Child is internal operand or new instruction
1800 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1801 // internal operand --> call ReduceInst_Interior
1802 // Interior of complex instruction. Do nothing but recurse.
1803 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1804 } else {
1805 // instruction --> call build operand( ) to catch result
1806 // --> ReduceInst( newrule )
1807 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1808 Node *mem1 = (Node*)1;
1809 debug_only(Node *save_mem_node = _mem_node;)
1810 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1811 debug_only(_mem_node = save_mem_node;)
1812 }
1813 }
1814 assert( mach->_opnds[num_opnds-1], "" );
1815 }
1816 return num_opnds;
1817 }
1819 // This routine walks the interior of possible complex operands.
1820 // At each point we check our children in the match tree:
1821 // (1) No children -
1822 // We are a leaf; add _leaf field as an input to the MachNode
1823 // (2) Child is an internal operand -
1824 // Skip over it ( do nothing )
1825 // (3) Child is an instruction -
1826 // Call ReduceInst recursively and
1827 // and instruction as an input to the MachNode
1828 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1829 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1830 State *kid = s->_kids[0];
1831 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1833 // Leaf? And not subsumed?
1834 if( kid == NULL && !_swallowed[rule] ) {
1835 mach->add_req( s->_leaf ); // Add leaf pointer
1836 return; // Bail out
1837 }
1839 if( s->_leaf->is_Load() ) {
1840 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1841 mem = s->_leaf->in(MemNode::Memory);
1842 debug_only(_mem_node = s->_leaf;)
1843 }
1844 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1845 if( !mach->in(0) )
1846 mach->set_req(0,s->_leaf->in(0));
1847 else {
1848 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1849 }
1850 }
1852 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1853 int newrule;
1854 if( i == 0)
1855 newrule = kid->_rule[_leftOp[rule]];
1856 else
1857 newrule = kid->_rule[_rightOp[rule]];
1859 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1860 // Internal operand; recurse but do nothing else
1861 ReduceOper( kid, newrule, mem, mach );
1863 } else { // Child is a new instruction
1864 // Reduce the instruction, and add a direct pointer from this
1865 // machine instruction to the newly reduced one.
1866 Node *mem1 = (Node*)1;
1867 debug_only(Node *save_mem_node = _mem_node;)
1868 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1869 debug_only(_mem_node = save_mem_node;)
1870 }
1871 }
1872 }
1875 // -------------------------------------------------------------------------
1876 // Java-Java calling convention
1877 // (what you use when Java calls Java)
1879 //------------------------------find_receiver----------------------------------
1880 // For a given signature, return the OptoReg for parameter 0.
1881 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1882 VMRegPair regs;
1883 BasicType sig_bt = T_OBJECT;
1884 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1885 // Return argument 0 register. In the LP64 build pointers
1886 // take 2 registers, but the VM wants only the 'main' name.
1887 return OptoReg::as_OptoReg(regs.first());
1888 }
1890 // A method-klass-holder may be passed in the inline_cache_reg
1891 // and then expanded into the inline_cache_reg and a method_oop register
1892 // defined in ad_<arch>.cpp
1895 //------------------------------find_shared------------------------------------
1896 // Set bits if Node is shared or otherwise a root
1897 void Matcher::find_shared( Node *n ) {
1898 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1899 MStack mstack(C->unique() * 2);
1900 // Mark nodes as address_visited if they are inputs to an address expression
1901 VectorSet address_visited(Thread::current()->resource_area());
1902 mstack.push(n, Visit); // Don't need to pre-visit root node
1903 while (mstack.is_nonempty()) {
1904 n = mstack.node(); // Leave node on stack
1905 Node_State nstate = mstack.state();
1906 uint nop = n->Opcode();
1907 if (nstate == Pre_Visit) {
1908 if (address_visited.test(n->_idx)) { // Visited in address already?
1909 // Flag as visited and shared now.
1910 set_visited(n);
1911 }
1912 if (is_visited(n)) { // Visited already?
1913 // Node is shared and has no reason to clone. Flag it as shared.
1914 // This causes it to match into a register for the sharing.
1915 set_shared(n); // Flag as shared and
1916 mstack.pop(); // remove node from stack
1917 continue;
1918 }
1919 nstate = Visit; // Not already visited; so visit now
1920 }
1921 if (nstate == Visit) {
1922 mstack.set_state(Post_Visit);
1923 set_visited(n); // Flag as visited now
1924 bool mem_op = false;
1926 switch( nop ) { // Handle some opcodes special
1927 case Op_Phi: // Treat Phis as shared roots
1928 case Op_Parm:
1929 case Op_Proj: // All handled specially during matching
1930 case Op_SafePointScalarObject:
1931 set_shared(n);
1932 set_dontcare(n);
1933 break;
1934 case Op_If:
1935 case Op_CountedLoopEnd:
1936 mstack.set_state(Alt_Post_Visit); // Alternative way
1937 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1938 // with matching cmp/branch in 1 instruction. The Matcher needs the
1939 // Bool and CmpX side-by-side, because it can only get at constants
1940 // that are at the leaves of Match trees, and the Bool's condition acts
1941 // as a constant here.
1942 mstack.push(n->in(1), Visit); // Clone the Bool
1943 mstack.push(n->in(0), Pre_Visit); // Visit control input
1944 continue; // while (mstack.is_nonempty())
1945 case Op_ConvI2D: // These forms efficiently match with a prior
1946 case Op_ConvI2F: // Load but not a following Store
1947 if( n->in(1)->is_Load() && // Prior load
1948 n->outcnt() == 1 && // Not already shared
1949 n->unique_out()->is_Store() ) // Following store
1950 set_shared(n); // Force it to be a root
1951 break;
1952 case Op_ReverseBytesI:
1953 case Op_ReverseBytesL:
1954 if( n->in(1)->is_Load() && // Prior load
1955 n->outcnt() == 1 ) // Not already shared
1956 set_shared(n); // Force it to be a root
1957 break;
1958 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1959 case Op_IfFalse:
1960 case Op_IfTrue:
1961 case Op_MachProj:
1962 case Op_MergeMem:
1963 case Op_Catch:
1964 case Op_CatchProj:
1965 case Op_CProj:
1966 case Op_JumpProj:
1967 case Op_JProj:
1968 case Op_NeverBranch:
1969 set_dontcare(n);
1970 break;
1971 case Op_Jump:
1972 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
1973 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1974 continue; // while (mstack.is_nonempty())
1975 case Op_StrComp:
1976 case Op_StrEquals:
1977 case Op_StrIndexOf:
1978 case Op_AryEq:
1979 case Op_EncodeISOArray:
1980 set_shared(n); // Force result into register (it will be anyways)
1981 break;
1982 case Op_ConP: { // Convert pointers above the centerline to NUL
1983 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1984 const TypePtr* tp = tn->type()->is_ptr();
1985 if (tp->_ptr == TypePtr::AnyNull) {
1986 tn->set_type(TypePtr::NULL_PTR);
1987 }
1988 break;
1989 }
1990 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1991 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1992 const TypePtr* tp = tn->type()->make_ptr();
1993 if (tp && tp->_ptr == TypePtr::AnyNull) {
1994 tn->set_type(TypeNarrowOop::NULL_PTR);
1995 }
1996 break;
1997 }
1998 case Op_Binary: // These are introduced in the Post_Visit state.
1999 ShouldNotReachHere();
2000 break;
2001 case Op_ClearArray:
2002 case Op_SafePoint:
2003 mem_op = true;
2004 break;
2005 default:
2006 if( n->is_Store() ) {
2007 // Do match stores, despite no ideal reg
2008 mem_op = true;
2009 break;
2010 }
2011 if( n->is_Mem() ) { // Loads and LoadStores
2012 mem_op = true;
2013 // Loads must be root of match tree due to prior load conflict
2014 if( C->subsume_loads() == false )
2015 set_shared(n);
2016 }
2017 // Fall into default case
2018 if( !n->ideal_reg() )
2019 set_dontcare(n); // Unmatchable Nodes
2020 } // end_switch
2022 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2023 Node *m = n->in(i); // Get ith input
2024 if (m == NULL) continue; // Ignore NULLs
2025 uint mop = m->Opcode();
2027 // Must clone all producers of flags, or we will not match correctly.
2028 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2029 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2030 // are also there, so we may match a float-branch to int-flags and
2031 // expect the allocator to haul the flags from the int-side to the
2032 // fp-side. No can do.
2033 if( _must_clone[mop] ) {
2034 mstack.push(m, Visit);
2035 continue; // for(int i = ...)
2036 }
2038 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2039 // Bases used in addresses must be shared but since
2040 // they are shared through a DecodeN they may appear
2041 // to have a single use so force sharing here.
2042 set_shared(m->in(AddPNode::Base)->in(1));
2043 }
2045 // Clone addressing expressions as they are "free" in memory access instructions
2046 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2047 // Some inputs for address expression are not put on stack
2048 // to avoid marking them as shared and forcing them into register
2049 // if they are used only in address expressions.
2050 // But they should be marked as shared if there are other uses
2051 // besides address expressions.
2053 Node *off = m->in(AddPNode::Offset);
2054 if( off->is_Con() &&
2055 // When there are other uses besides address expressions
2056 // put it on stack and mark as shared.
2057 !is_visited(m) ) {
2058 address_visited.test_set(m->_idx); // Flag as address_visited
2059 Node *adr = m->in(AddPNode::Address);
2061 // Intel, ARM and friends can handle 2 adds in addressing mode
2062 if( clone_shift_expressions && adr->is_AddP() &&
2063 // AtomicAdd is not an addressing expression.
2064 // Cheap to find it by looking for screwy base.
2065 !adr->in(AddPNode::Base)->is_top() &&
2066 // Are there other uses besides address expressions?
2067 !is_visited(adr) ) {
2068 address_visited.set(adr->_idx); // Flag as address_visited
2069 Node *shift = adr->in(AddPNode::Offset);
2070 // Check for shift by small constant as well
2071 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2072 shift->in(2)->get_int() <= 3 &&
2073 // Are there other uses besides address expressions?
2074 !is_visited(shift) ) {
2075 address_visited.set(shift->_idx); // Flag as address_visited
2076 mstack.push(shift->in(2), Visit);
2077 Node *conv = shift->in(1);
2078 #ifdef _LP64
2079 // Allow Matcher to match the rule which bypass
2080 // ConvI2L operation for an array index on LP64
2081 // if the index value is positive.
2082 if( conv->Opcode() == Op_ConvI2L &&
2083 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2084 // Are there other uses besides address expressions?
2085 !is_visited(conv) ) {
2086 address_visited.set(conv->_idx); // Flag as address_visited
2087 mstack.push(conv->in(1), Pre_Visit);
2088 } else
2089 #endif
2090 mstack.push(conv, Pre_Visit);
2091 } else {
2092 mstack.push(shift, Pre_Visit);
2093 }
2094 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2095 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2096 } else { // Sparc, Alpha, PPC and friends
2097 mstack.push(adr, Pre_Visit);
2098 }
2100 // Clone X+offset as it also folds into most addressing expressions
2101 mstack.push(off, Visit);
2102 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2103 continue; // for(int i = ...)
2104 } // if( off->is_Con() )
2105 } // if( mem_op &&
2106 mstack.push(m, Pre_Visit);
2107 } // for(int i = ...)
2108 }
2109 else if (nstate == Alt_Post_Visit) {
2110 mstack.pop(); // Remove node from stack
2111 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2112 // shared and all users of the Bool need to move the Cmp in parallel.
2113 // This leaves both the Bool and the If pointing at the Cmp. To
2114 // prevent the Matcher from trying to Match the Cmp along both paths
2115 // BoolNode::match_edge always returns a zero.
2117 // We reorder the Op_If in a pre-order manner, so we can visit without
2118 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2119 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2120 }
2121 else if (nstate == Post_Visit) {
2122 mstack.pop(); // Remove node from stack
2124 // Now hack a few special opcodes
2125 switch( n->Opcode() ) { // Handle some opcodes special
2126 case Op_StorePConditional:
2127 case Op_StoreIConditional:
2128 case Op_StoreLConditional:
2129 case Op_CompareAndSwapI:
2130 case Op_CompareAndSwapL:
2131 case Op_CompareAndSwapP:
2132 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2133 Node *newval = n->in(MemNode::ValueIn );
2134 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2135 Node *pair = new (C) BinaryNode( oldval, newval );
2136 n->set_req(MemNode::ValueIn,pair);
2137 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2138 break;
2139 }
2140 case Op_CMoveD: // Convert trinary to binary-tree
2141 case Op_CMoveF:
2142 case Op_CMoveI:
2143 case Op_CMoveL:
2144 case Op_CMoveN:
2145 case Op_CMoveP: {
2146 // Restructure into a binary tree for Matching. It's possible that
2147 // we could move this code up next to the graph reshaping for IfNodes
2148 // or vice-versa, but I do not want to debug this for Ladybird.
2149 // 10/2/2000 CNC.
2150 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1));
2151 n->set_req(1,pair1);
2152 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3));
2153 n->set_req(2,pair2);
2154 n->del_req(3);
2155 break;
2156 }
2157 case Op_LoopLimit: {
2158 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2));
2159 n->set_req(1,pair1);
2160 n->set_req(2,n->in(3));
2161 n->del_req(3);
2162 break;
2163 }
2164 case Op_StrEquals: {
2165 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2166 n->set_req(2,pair1);
2167 n->set_req(3,n->in(4));
2168 n->del_req(4);
2169 break;
2170 }
2171 case Op_StrComp:
2172 case Op_StrIndexOf: {
2173 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2174 n->set_req(2,pair1);
2175 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5));
2176 n->set_req(3,pair2);
2177 n->del_req(5);
2178 n->del_req(4);
2179 break;
2180 }
2181 case Op_EncodeISOArray: {
2182 // Restructure into a binary tree for Matching.
2183 Node* pair = new (C) BinaryNode(n->in(3), n->in(4));
2184 n->set_req(3, pair);
2185 n->del_req(4);
2186 break;
2187 }
2188 default:
2189 break;
2190 }
2191 }
2192 else {
2193 ShouldNotReachHere();
2194 }
2195 } // end of while (mstack.is_nonempty())
2196 }
2198 #ifdef ASSERT
2199 // machine-independent root to machine-dependent root
2200 void Matcher::dump_old2new_map() {
2201 _old2new_map.dump();
2202 }
2203 #endif
2205 //---------------------------collect_null_checks-------------------------------
2206 // Find null checks in the ideal graph; write a machine-specific node for
2207 // it. Used by later implicit-null-check handling. Actually collects
2208 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2209 // value being tested.
2210 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2211 Node *iff = proj->in(0);
2212 if( iff->Opcode() == Op_If ) {
2213 // During matching If's have Bool & Cmp side-by-side
2214 BoolNode *b = iff->in(1)->as_Bool();
2215 Node *cmp = iff->in(2);
2216 int opc = cmp->Opcode();
2217 if (opc != Op_CmpP && opc != Op_CmpN) return;
2219 const Type* ct = cmp->in(2)->bottom_type();
2220 if (ct == TypePtr::NULL_PTR ||
2221 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2223 bool push_it = false;
2224 if( proj->Opcode() == Op_IfTrue ) {
2225 extern int all_null_checks_found;
2226 all_null_checks_found++;
2227 if( b->_test._test == BoolTest::ne ) {
2228 push_it = true;
2229 }
2230 } else {
2231 assert( proj->Opcode() == Op_IfFalse, "" );
2232 if( b->_test._test == BoolTest::eq ) {
2233 push_it = true;
2234 }
2235 }
2236 if( push_it ) {
2237 _null_check_tests.push(proj);
2238 Node* val = cmp->in(1);
2239 #ifdef _LP64
2240 if (val->bottom_type()->isa_narrowoop() &&
2241 !Matcher::narrow_oop_use_complex_address()) {
2242 //
2243 // Look for DecodeN node which should be pinned to orig_proj.
2244 // On platforms (Sparc) which can not handle 2 adds
2245 // in addressing mode we have to keep a DecodeN node and
2246 // use it to do implicit NULL check in address.
2247 //
2248 // DecodeN node was pinned to non-null path (orig_proj) during
2249 // CastPP transformation in final_graph_reshaping_impl().
2250 //
2251 uint cnt = orig_proj->outcnt();
2252 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2253 Node* d = orig_proj->raw_out(i);
2254 if (d->is_DecodeN() && d->in(1) == val) {
2255 val = d;
2256 val->set_req(0, NULL); // Unpin now.
2257 // Mark this as special case to distinguish from
2258 // a regular case: CmpP(DecodeN, NULL).
2259 val = (Node*)(((intptr_t)val) | 1);
2260 break;
2261 }
2262 }
2263 }
2264 #endif
2265 _null_check_tests.push(val);
2266 }
2267 }
2268 }
2269 }
2271 //---------------------------validate_null_checks------------------------------
2272 // Its possible that the value being NULL checked is not the root of a match
2273 // tree. If so, I cannot use the value in an implicit null check.
2274 void Matcher::validate_null_checks( ) {
2275 uint cnt = _null_check_tests.size();
2276 for( uint i=0; i < cnt; i+=2 ) {
2277 Node *test = _null_check_tests[i];
2278 Node *val = _null_check_tests[i+1];
2279 bool is_decoden = ((intptr_t)val) & 1;
2280 val = (Node*)(((intptr_t)val) & ~1);
2281 if (has_new_node(val)) {
2282 Node* new_val = new_node(val);
2283 if (is_decoden) {
2284 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2285 // Note: new_val may have a control edge if
2286 // the original ideal node DecodeN was matched before
2287 // it was unpinned in Matcher::collect_null_checks().
2288 // Unpin the mach node and mark it.
2289 new_val->set_req(0, NULL);
2290 new_val = (Node*)(((intptr_t)new_val) | 1);
2291 }
2292 // Is a match-tree root, so replace with the matched value
2293 _null_check_tests.map(i+1, new_val);
2294 } else {
2295 // Yank from candidate list
2296 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2297 _null_check_tests.map(i,_null_check_tests[--cnt]);
2298 _null_check_tests.pop();
2299 _null_check_tests.pop();
2300 i-=2;
2301 }
2302 }
2303 }
2305 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2306 // atomic instruction acting as a store_load barrier without any
2307 // intervening volatile load, and thus we don't need a barrier here.
2308 // We retain the Node to act as a compiler ordering barrier.
2309 bool Matcher::post_store_load_barrier(const Node *vmb) {
2310 Compile *C = Compile::current();
2311 assert( vmb->is_MemBar(), "" );
2312 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2313 const MemBarNode *mem = (const MemBarNode*)vmb;
2315 // Get the Proj node, ctrl, that can be used to iterate forward
2316 Node *ctrl = NULL;
2317 DUIterator_Fast imax, i = mem->fast_outs(imax);
2318 while( true ) {
2319 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2320 assert( ctrl->is_Proj(), "only projections here" );
2321 ProjNode *proj = (ProjNode*)ctrl;
2322 if( proj->_con == TypeFunc::Control &&
2323 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2324 break;
2325 i++;
2326 }
2328 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2329 Node *x = ctrl->fast_out(j);
2330 int xop = x->Opcode();
2332 // We don't need current barrier if we see another or a lock
2333 // before seeing volatile load.
2334 //
2335 // Op_Fastunlock previously appeared in the Op_* list below.
2336 // With the advent of 1-0 lock operations we're no longer guaranteed
2337 // that a monitor exit operation contains a serializing instruction.
2339 if (xop == Op_MemBarVolatile ||
2340 xop == Op_FastLock ||
2341 xop == Op_CompareAndSwapL ||
2342 xop == Op_CompareAndSwapP ||
2343 xop == Op_CompareAndSwapN ||
2344 xop == Op_CompareAndSwapI)
2345 return true;
2347 if (x->is_MemBar()) {
2348 // We must retain this membar if there is an upcoming volatile
2349 // load, which will be preceded by acquire membar.
2350 if (xop == Op_MemBarAcquire)
2351 return false;
2352 // For other kinds of barriers, check by pretending we
2353 // are them, and seeing if we can be removed.
2354 else
2355 return post_store_load_barrier((const MemBarNode*)x);
2356 }
2358 // Delicate code to detect case of an upcoming fastlock block
2359 if( x->is_If() && x->req() > 1 &&
2360 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2361 Node *iff = x;
2362 Node *bol = iff->in(1);
2363 // The iff might be some random subclass of If or bol might be Con-Top
2364 if (!bol->is_Bool()) return false;
2365 assert( bol->req() > 1, "" );
2366 return (bol->in(1)->Opcode() == Op_FastUnlock);
2367 }
2368 // probably not necessary to check for these
2369 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2370 return false;
2371 }
2372 return false;
2373 }
2375 //=============================================================================
2376 //---------------------------State---------------------------------------------
2377 State::State(void) {
2378 #ifdef ASSERT
2379 _id = 0;
2380 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2381 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2382 //memset(_cost, -1, sizeof(_cost));
2383 //memset(_rule, -1, sizeof(_rule));
2384 #endif
2385 memset(_valid, 0, sizeof(_valid));
2386 }
2388 #ifdef ASSERT
2389 State::~State() {
2390 _id = 99;
2391 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2392 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2393 memset(_cost, -3, sizeof(_cost));
2394 memset(_rule, -3, sizeof(_rule));
2395 }
2396 #endif
2398 #ifndef PRODUCT
2399 //---------------------------dump----------------------------------------------
2400 void State::dump() {
2401 tty->print("\n");
2402 dump(0);
2403 }
2405 void State::dump(int depth) {
2406 for( int j = 0; j < depth; j++ )
2407 tty->print(" ");
2408 tty->print("--N: ");
2409 _leaf->dump();
2410 uint i;
2411 for( i = 0; i < _LAST_MACH_OPER; i++ )
2412 // Check for valid entry
2413 if( valid(i) ) {
2414 for( int j = 0; j < depth; j++ )
2415 tty->print(" ");
2416 assert(_cost[i] != max_juint, "cost must be a valid value");
2417 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2418 tty->print_cr("%s %d %s",
2419 ruleName[i], _cost[i], ruleName[_rule[i]] );
2420 }
2421 tty->print_cr("");
2423 for( i=0; i<2; i++ )
2424 if( _kids[i] )
2425 _kids[i]->dump(depth+1);
2426 }
2427 #endif