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src/cpu/ppc/vm/assembler_ppc.hpp@b384ba33c9a0
src/cpu/ppc/vm/assembler_ppc.hpp
Thu, 17 Jul 2014 15:40:04 -0700
- author
- kvn
- date
- Thu, 17 Jul 2014 15:40:04 -0700
- changeset 7132
- b384ba33c9a0
- parent 6538
- 56e7f5560e60
- child 7222
- f6bde7889409
- permissions
- -rw-r--r--
8050942: PPC64: implement template interpreter for ppc64le
Reviewed-by: kvn, goetz
Contributed-by: asmundak@google.com
1 /*
2 * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2013 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP
27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP
29 #include "asm/register.hpp"
31 // Address is an abstraction used to represent a memory location
32 // as used in assembler instructions.
33 // PPC instructions grok either baseReg + indexReg or baseReg + disp.
34 // So far we do not use this as simplification by this class is low
35 // on PPC with its simple addressing mode. Use RegisterOrConstant to
36 // represent an offset.
37 class Address VALUE_OBJ_CLASS_SPEC {
38 };
40 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
41 private:
42 address _address;
43 RelocationHolder _rspec;
45 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
46 switch (rtype) {
47 case relocInfo::external_word_type:
48 return external_word_Relocation::spec(addr);
49 case relocInfo::internal_word_type:
50 return internal_word_Relocation::spec(addr);
51 case relocInfo::opt_virtual_call_type:
52 return opt_virtual_call_Relocation::spec();
53 case relocInfo::static_call_type:
54 return static_call_Relocation::spec();
55 case relocInfo::runtime_call_type:
56 return runtime_call_Relocation::spec();
57 case relocInfo::none:
58 return RelocationHolder();
59 default:
60 ShouldNotReachHere();
61 return RelocationHolder();
62 }
63 }
65 protected:
66 // creation
67 AddressLiteral() : _address(NULL), _rspec(NULL) {}
69 public:
70 AddressLiteral(address addr, RelocationHolder const& rspec)
71 : _address(addr),
72 _rspec(rspec) {}
74 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
75 : _address((address) addr),
76 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
78 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
79 : _address((address) addr),
80 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
82 intptr_t value() const { return (intptr_t) _address; }
84 const RelocationHolder& rspec() const { return _rspec; }
85 };
87 // Argument is an abstraction used to represent an outgoing
88 // actual argument or an incoming formal parameter, whether
89 // it resides in memory or in a register, in a manner consistent
90 // with the PPC Application Binary Interface, or ABI. This is
91 // often referred to as the native or C calling convention.
93 class Argument VALUE_OBJ_CLASS_SPEC {
94 private:
95 int _number; // The number of the argument.
96 public:
97 enum {
98 // Only 8 registers may contain integer parameters.
99 n_register_parameters = 8,
100 // Can have up to 8 floating registers.
101 n_float_register_parameters = 8,
103 // PPC C calling conventions.
104 // The first eight arguments are passed in int regs if they are int.
105 n_int_register_parameters_c = 8,
106 // The first thirteen float arguments are passed in float regs.
107 n_float_register_parameters_c = 13,
108 // Only the first 8 parameters are not placed on the stack. Aix disassembly
109 // shows that xlC places all float args after argument 8 on the stack AND
110 // in a register. This is not documented, but we follow this convention, too.
111 n_regs_not_on_stack_c = 8,
112 };
113 // creation
114 Argument(int number) : _number(number) {}
116 int number() const { return _number; }
118 // Locating register-based arguments:
119 bool is_register() const { return _number < n_register_parameters; }
121 Register as_register() const {
122 assert(is_register(), "must be a register argument");
123 return as_Register(number() + R3_ARG1->encoding());
124 }
125 };
127 #if !defined(ABI_ELFv2)
128 // A ppc64 function descriptor.
129 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC {
130 private:
131 address _entry;
132 address _toc;
133 address _env;
135 public:
136 inline address entry() const { return _entry; }
137 inline address toc() const { return _toc; }
138 inline address env() const { return _env; }
140 inline void set_entry(address entry) { _entry = entry; }
141 inline void set_toc( address toc) { _toc = toc; }
142 inline void set_env( address env) { _env = env; }
144 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
145 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); }
146 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); }
148 // Friend functions can be called without loading toc and env.
149 enum {
150 friend_toc = 0xcafe,
151 friend_env = 0xc0de
152 };
154 inline bool is_friend_function() const {
155 return (toc() == (address) friend_toc) && (env() == (address) friend_env);
156 }
158 // Constructor for stack-allocated instances.
159 FunctionDescriptor() {
160 _entry = (address) 0xbad;
161 _toc = (address) 0xbad;
162 _env = (address) 0xbad;
163 }
164 };
165 #endif
167 class Assembler : public AbstractAssembler {
168 protected:
169 // Displacement routines
170 static void print_instruction(int inst);
171 static int patched_branch(int dest_pos, int inst, int inst_pos);
172 static int branch_destination(int inst, int pos);
174 friend class AbstractAssembler;
176 // Code patchers need various routines like inv_wdisp()
177 friend class NativeInstruction;
178 friend class NativeGeneralJump;
179 friend class Relocation;
181 public:
183 enum shifts {
184 XO_21_29_SHIFT = 2,
185 XO_21_30_SHIFT = 1,
186 XO_27_29_SHIFT = 2,
187 XO_30_31_SHIFT = 0,
188 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15
189 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20
190 RS_SHIFT = 21u, // RS field in bits 21 -- 25
191 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31
192 };
194 enum opcdxos_masks {
195 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
196 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
197 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
198 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
199 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
200 // trap instructions
201 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
202 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT),
203 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
204 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
205 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
206 STD_OPCODE_MASK = LD_OPCODE_MASK,
207 STDU_OPCODE_MASK = STD_OPCODE_MASK,
208 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
209 STDUX_OPCODE_MASK = STDX_OPCODE_MASK,
210 STW_OPCODE_MASK = (63u << OPCODE_SHIFT),
211 STWU_OPCODE_MASK = STW_OPCODE_MASK,
212 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
213 STWUX_OPCODE_MASK = STWX_OPCODE_MASK,
214 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT),
215 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT),
216 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
217 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
218 };
220 enum opcdxos {
221 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1),
222 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1),
223 ADDI_OPCODE = (14u << OPCODE_SHIFT),
224 ADDIS_OPCODE = (15u << OPCODE_SHIFT),
225 ADDIC__OPCODE = (13u << OPCODE_SHIFT),
226 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1),
227 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1),
228 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1),
229 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1),
230 SUBFIC_OPCODE = (8u << OPCODE_SHIFT),
231 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
232 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
233 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
234 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
235 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
236 MULLI_OPCODE = (7u << OPCODE_SHIFT),
237 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1),
238 ANDI_OPCODE = (28u << OPCODE_SHIFT),
239 ANDIS_OPCODE = (29u << OPCODE_SHIFT),
240 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1),
241 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1),
242 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1),
243 ORI_OPCODE = (24u << OPCODE_SHIFT),
244 ORIS_OPCODE = (25u << OPCODE_SHIFT),
245 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1),
246 XORI_OPCODE = (26u << OPCODE_SHIFT),
247 XORIS_OPCODE = (27u << OPCODE_SHIFT),
249 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
251 RLWINM_OPCODE = (21u << OPCODE_SHIFT),
252 CLRRWI_OPCODE = RLWINM_OPCODE,
253 CLRLWI_OPCODE = RLWINM_OPCODE,
255 RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
257 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
258 SLWI_OPCODE = RLWINM_OPCODE,
259 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
260 SRWI_OPCODE = RLWINM_OPCODE,
261 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
262 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
264 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
265 CMPI_OPCODE = (11u << OPCODE_SHIFT),
266 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
267 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
269 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
271 MTLR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT),
272 MFLR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT),
274 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
275 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
276 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
278 // condition register logic instructions
279 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
280 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
281 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
282 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
283 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
284 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
285 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
286 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
288 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
289 BXX_OPCODE = (18u << OPCODE_SHIFT),
290 BCXX_OPCODE = (16u << OPCODE_SHIFT),
292 // CTR-related opcodes
293 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
294 MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
295 MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
298 LWZ_OPCODE = (32u << OPCODE_SHIFT),
299 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
300 LWZU_OPCODE = (33u << OPCODE_SHIFT),
301 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1),
303 LHA_OPCODE = (42u << OPCODE_SHIFT),
304 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
305 LHAU_OPCODE = (43u << OPCODE_SHIFT),
307 LHZ_OPCODE = (40u << OPCODE_SHIFT),
308 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
309 LHZU_OPCODE = (41u << OPCODE_SHIFT),
310 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1),
312 LBZ_OPCODE = (34u << OPCODE_SHIFT),
313 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
314 LBZU_OPCODE = (35u << OPCODE_SHIFT),
316 STW_OPCODE = (36u << OPCODE_SHIFT),
317 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
318 STWU_OPCODE = (37u << OPCODE_SHIFT),
319 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
321 STH_OPCODE = (44u << OPCODE_SHIFT),
322 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
323 STHU_OPCODE = (45u << OPCODE_SHIFT),
325 STB_OPCODE = (38u << OPCODE_SHIFT),
326 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
327 STBU_OPCODE = (39u << OPCODE_SHIFT),
329 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
330 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
331 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM
333 // 32 bit opcode encodings
335 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM
336 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
338 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM
340 // 64 bit opcode encodings
342 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
343 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
344 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM
346 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
347 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
348 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
349 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
351 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM
352 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
353 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
354 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
356 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
358 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
359 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
360 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
362 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
363 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
364 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
365 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
367 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
368 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
369 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
372 // opcodes only used for floating arithmetic
373 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
374 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
375 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
376 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
377 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
378 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
379 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
380 // on Power7. Do not use.
381 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
382 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
383 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
384 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
385 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
386 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
387 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
388 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1),
389 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1),
390 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1),
391 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1),
392 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1),
393 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1),
395 // PPC64-internal FPU conversion opcodes
396 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1),
397 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1),
398 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1),
399 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1),
400 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1),
401 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1),
402 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1),
404 // WARNING: using fmadd results in a non-compliant vm. Some floating
405 // point tck tests will fail.
406 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
407 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
408 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
409 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
410 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
411 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
412 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
413 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
415 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1),
416 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1),
417 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1),
418 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1),
419 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
420 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
422 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
423 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
424 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
425 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
426 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
427 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
429 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
430 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
432 // Vector instruction support for >= Power6
433 // Vector Storage Access
434 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
435 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
436 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
437 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
438 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
439 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
440 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
441 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
442 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
443 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
444 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
445 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
447 // Vector Permute and Formatting
448 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
449 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
450 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
451 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
452 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
453 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
454 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
455 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
456 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
457 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
458 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
459 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
460 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
461 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
462 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
464 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
465 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
466 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
467 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
468 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
469 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
471 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
472 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
473 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
474 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
475 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
476 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
478 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
479 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
481 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
482 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
483 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
484 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
485 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
487 // Vector Integer
488 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
489 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
490 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
491 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
492 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
493 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
494 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
495 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
496 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
497 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
498 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ),
499 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ),
500 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ),
501 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ),
502 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ),
503 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ),
504 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ),
505 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ),
506 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ),
507 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ),
509 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ),
510 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ),
511 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ),
512 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ),
513 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ),
514 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ),
515 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ),
516 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ),
517 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ),
518 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ),
519 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ),
520 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ),
521 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ),
522 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ),
523 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ),
524 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ),
525 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ),
527 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ),
528 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ),
529 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ),
530 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ),
531 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ),
533 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ),
534 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ),
535 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ),
536 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ),
537 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ),
538 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ),
540 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ),
541 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ),
542 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ),
543 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ),
544 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ),
545 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ),
546 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ),
547 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ),
548 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ),
549 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ),
550 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ),
551 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ),
553 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ),
554 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ),
555 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ),
556 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ),
557 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ),
558 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ),
559 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ),
560 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ),
561 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ),
563 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ),
564 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ),
565 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ),
566 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ),
567 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ),
568 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ),
569 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ),
570 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ),
571 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ),
572 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ),
573 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ),
574 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ),
575 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ),
576 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ),
577 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ),
578 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ),
579 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ),
581 // Vector Floating-Point
582 // not implemented yet
584 // Vector Status and Control
585 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
586 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
588 // Icache and dcache related instructions
589 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
590 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
591 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
592 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
594 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
595 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
596 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
598 // Instruction synchronization
599 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
600 // Memory barriers
601 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
602 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
604 // Trap instructions
605 TDI_OPCODE = (2u << OPCODE_SHIFT),
606 TWI_OPCODE = (3u << OPCODE_SHIFT),
607 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
608 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
610 // Atomics.
611 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
612 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
613 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
614 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
616 };
618 // Trap instructions TO bits
619 enum trap_to_bits {
620 // single bits
621 traptoLessThanSigned = 1 << 4, // 0, left end
622 traptoGreaterThanSigned = 1 << 3,
623 traptoEqual = 1 << 2,
624 traptoLessThanUnsigned = 1 << 1,
625 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
627 // compound ones
628 traptoUnconditional = (traptoLessThanSigned |
629 traptoGreaterThanSigned |
630 traptoEqual |
631 traptoLessThanUnsigned |
632 traptoGreaterThanUnsigned)
633 };
635 // Branch hints BH field
636 enum branch_hint_bh {
637 // bclr cases:
638 bhintbhBCLRisReturn = 0,
639 bhintbhBCLRisNotReturnButSame = 1,
640 bhintbhBCLRisNotPredictable = 3,
642 // bcctr cases:
643 bhintbhBCCTRisNotReturnButSame = 0,
644 bhintbhBCCTRisNotPredictable = 3
645 };
647 // Branch prediction hints AT field
648 enum branch_hint_at {
649 bhintatNoHint = 0, // at=00
650 bhintatIsNotTaken = 2, // at=10
651 bhintatIsTaken = 3 // at=11
652 };
654 // Branch prediction hints
655 enum branch_hint_concept {
656 // Use the same encoding as branch_hint_at to simply code.
657 bhintNoHint = bhintatNoHint,
658 bhintIsNotTaken = bhintatIsNotTaken,
659 bhintIsTaken = bhintatIsTaken
660 };
662 // Used in BO field of branch instruction.
663 enum branch_condition {
664 bcondCRbiIs0 = 4, // bo=001at
665 bcondCRbiIs1 = 12, // bo=011at
666 bcondAlways = 20 // bo=10100
667 };
669 // Branch condition with combined prediction hints.
670 enum branch_condition_with_hint {
671 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint,
672 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
673 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken,
674 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint,
675 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
676 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken,
677 };
679 // Elemental Memory Barriers (>=Power 8)
680 enum Elemental_Membar_mask_bits {
681 StoreStore = 1 << 0,
682 StoreLoad = 1 << 1,
683 LoadStore = 1 << 2,
684 LoadLoad = 1 << 3
685 };
687 // Branch prediction hints.
688 inline static int add_bhint_to_boint(const int bhint, const int boint) {
689 switch (boint) {
690 case bcondCRbiIs0:
691 case bcondCRbiIs1:
692 // branch_hint and branch_hint_at have same encodings
693 assert( (int)bhintNoHint == (int)bhintatNoHint
694 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
695 && (int)bhintIsTaken == (int)bhintatIsTaken,
696 "wrong encodings");
697 assert((bhint & 0x03) == bhint, "wrong encodings");
698 return (boint & ~0x03) | bhint;
699 case bcondAlways:
700 // no branch_hint
701 return boint;
702 default:
703 ShouldNotReachHere();
704 return 0;
705 }
706 }
708 // Extract bcond from boint.
709 inline static int inv_boint_bcond(const int boint) {
710 int r_bcond = boint & ~0x03;
711 assert(r_bcond == bcondCRbiIs0 ||
712 r_bcond == bcondCRbiIs1 ||
713 r_bcond == bcondAlways,
714 "bad branch condition");
715 return r_bcond;
716 }
718 // Extract bhint from boint.
719 inline static int inv_boint_bhint(const int boint) {
720 int r_bhint = boint & 0x03;
721 assert(r_bhint == bhintatNoHint ||
722 r_bhint == bhintatIsNotTaken ||
723 r_bhint == bhintatIsTaken,
724 "bad branch hint");
725 return r_bhint;
726 }
728 // Calculate opposite of given bcond.
729 inline static int opposite_bcond(const int bcond) {
730 switch (bcond) {
731 case bcondCRbiIs0:
732 return bcondCRbiIs1;
733 case bcondCRbiIs1:
734 return bcondCRbiIs0;
735 default:
736 ShouldNotReachHere();
737 return 0;
738 }
739 }
741 // Calculate opposite of given bhint.
742 inline static int opposite_bhint(const int bhint) {
743 switch (bhint) {
744 case bhintatNoHint:
745 return bhintatNoHint;
746 case bhintatIsNotTaken:
747 return bhintatIsTaken;
748 case bhintatIsTaken:
749 return bhintatIsNotTaken;
750 default:
751 ShouldNotReachHere();
752 return 0;
753 }
754 }
756 // PPC branch instructions
757 enum ppcops {
758 b_op = 18,
759 bc_op = 16,
760 bcr_op = 19
761 };
763 enum Condition {
764 negative = 0,
765 less = 0,
766 positive = 1,
767 greater = 1,
768 zero = 2,
769 equal = 2,
770 summary_overflow = 3,
771 };
773 public:
774 // Helper functions for groups of instructions
776 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
778 // instruction must start at passed address
779 static int instr_len(unsigned char *instr) { return BytesPerInstWord; }
781 // instruction must be left-justified in argument
782 static int instr_len(unsigned long instr) { return BytesPerInstWord; }
784 // longest instructions
785 static int instr_maxlen() { return BytesPerInstWord; }
787 // Test if x is within signed immediate range for nbits.
788 static bool is_simm(int x, unsigned int nbits) {
789 assert(0 < nbits && nbits < 32, "out of bounds");
790 const int min = -( ((int)1) << nbits-1 );
791 const int maxplus1 = ( ((int)1) << nbits-1 );
792 return min <= x && x < maxplus1;
793 }
795 static bool is_simm(jlong x, unsigned int nbits) {
796 assert(0 < nbits && nbits < 64, "out of bounds");
797 const jlong min = -( ((jlong)1) << nbits-1 );
798 const jlong maxplus1 = ( ((jlong)1) << nbits-1 );
799 return min <= x && x < maxplus1;
800 }
802 // Test if x is within unsigned immediate range for nbits
803 static bool is_uimm(int x, unsigned int nbits) {
804 assert(0 < nbits && nbits < 32, "out of bounds");
805 const int maxplus1 = ( ((int)1) << nbits );
806 return 0 <= x && x < maxplus1;
807 }
809 static bool is_uimm(jlong x, unsigned int nbits) {
810 assert(0 < nbits && nbits < 64, "out of bounds");
811 const jlong maxplus1 = ( ((jlong)1) << nbits );
812 return 0 <= x && x < maxplus1;
813 }
815 protected:
816 // helpers
818 // X is supposed to fit in a field "nbits" wide
819 // and be sign-extended. Check the range.
820 static void assert_signed_range(intptr_t x, int nbits) {
821 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
822 "value out of range");
823 }
825 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
826 assert((x & 3) == 0, "not word aligned");
827 assert_signed_range(x, nbits + 2);
828 }
830 static void assert_unsigned_const(int x, int nbits) {
831 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
832 }
834 static int fmask(juint hi_bit, juint lo_bit) {
835 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
836 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
837 }
839 // inverse of u_field
840 static int inv_u_field(int x, int hi_bit, int lo_bit) {
841 juint r = juint(x) >> lo_bit;
842 r &= fmask(hi_bit, lo_bit);
843 return int(r);
844 }
846 // signed version: extract from field and sign-extend
847 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
848 x = x << (31-hi_bit);
849 x = x >> (31-hi_bit+lo_bit);
850 return x;
851 }
853 static int u_field(int x, int hi_bit, int lo_bit) {
854 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
855 int r = x << lo_bit;
856 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
857 return r;
858 }
860 // Same as u_field for signed values
861 static int s_field(int x, int hi_bit, int lo_bit) {
862 int nbits = hi_bit - lo_bit + 1;
863 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
864 "value out of range");
865 x &= fmask(hi_bit, lo_bit);
866 int r = x << lo_bit;
867 return r;
868 }
870 // inv_op for ppc instructions
871 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
873 // Determine target address from li, bd field of branch instruction.
874 static intptr_t inv_li_field(int x) {
875 intptr_t r = inv_s_field_ppc(x, 25, 2);
876 r = (r << 2);
877 return r;
878 }
879 static intptr_t inv_bd_field(int x, intptr_t pos) {
880 intptr_t r = inv_s_field_ppc(x, 15, 2);
881 r = (r << 2) + pos;
882 return r;
883 }
885 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
886 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
887 // Extract instruction fields from instruction words.
888 public:
889 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); }
890 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); }
891 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); }
892 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
893 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); }
894 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
895 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
896 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; }
897 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); }
898 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); }
899 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); }
900 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); }
901 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
902 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }
904 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
905 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
907 // instruction fields
908 static int aa( int x) { return opp_u_field(x, 30, 30); }
909 static int ba( int x) { return opp_u_field(x, 15, 11); }
910 static int bb( int x) { return opp_u_field(x, 20, 16); }
911 static int bc( int x) { return opp_u_field(x, 25, 21); }
912 static int bd( int x) { return opp_s_field(x, 29, 16); }
913 static int bf( ConditionRegister cr) { return bf(cr->encoding()); }
914 static int bf( int x) { return opp_u_field(x, 8, 6); }
915 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); }
916 static int bfa( int x) { return opp_u_field(x, 13, 11); }
917 static int bh( int x) { return opp_u_field(x, 20, 19); }
918 static int bi( int x) { return opp_u_field(x, 15, 11); }
919 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
920 static int bo( int x) { return opp_u_field(x, 10, 6); }
921 static int bt( int x) { return opp_u_field(x, 10, 6); }
922 static int d1( int x) { return opp_s_field(x, 31, 16); }
923 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
924 static int eh( int x) { return opp_u_field(x, 31, 31); }
925 static int flm( int x) { return opp_u_field(x, 14, 7); }
926 static int fra( FloatRegister r) { return fra(r->encoding());}
927 static int frb( FloatRegister r) { return frb(r->encoding());}
928 static int frc( FloatRegister r) { return frc(r->encoding());}
929 static int frs( FloatRegister r) { return frs(r->encoding());}
930 static int frt( FloatRegister r) { return frt(r->encoding());}
931 static int fra( int x) { return opp_u_field(x, 15, 11); }
932 static int frb( int x) { return opp_u_field(x, 20, 16); }
933 static int frc( int x) { return opp_u_field(x, 25, 21); }
934 static int frs( int x) { return opp_u_field(x, 10, 6); }
935 static int frt( int x) { return opp_u_field(x, 10, 6); }
936 static int fxm( int x) { return opp_u_field(x, 19, 12); }
937 static int l10( int x) { return opp_u_field(x, 10, 10); }
938 static int l15( int x) { return opp_u_field(x, 15, 15); }
939 static int l910( int x) { return opp_u_field(x, 10, 9); }
940 static int e1215( int x) { return opp_u_field(x, 15, 12); }
941 static int lev( int x) { return opp_u_field(x, 26, 20); }
942 static int li( int x) { return opp_s_field(x, 29, 6); }
943 static int lk( int x) { return opp_u_field(x, 31, 31); }
944 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
945 static int me2630( int x) { return opp_u_field(x, 30, 26); }
946 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
947 static int me2126( int x) { return mb2126(x); }
948 static int nb( int x) { return opp_u_field(x, 20, 16); }
949 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
950 static int oe( int x) { return opp_u_field(x, 21, 21); }
951 static int ra( Register r) { return ra(r->encoding()); }
952 static int ra( int x) { return opp_u_field(x, 15, 11); }
953 static int rb( Register r) { return rb(r->encoding()); }
954 static int rb( int x) { return opp_u_field(x, 20, 16); }
955 static int rc( int x) { return opp_u_field(x, 31, 31); }
956 static int rs( Register r) { return rs(r->encoding()); }
957 static int rs( int x) { return opp_u_field(x, 10, 6); }
958 // we don't want to use R0 in memory accesses, because it has value `0' then
959 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
960 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); }
962 // register r is target
963 static int rt( Register r) { return rs(r); }
964 static int rt( int x) { return rs(x); }
965 static int rta( Register r) { return ra(r); }
966 static int rta0mem( Register r) { rta(r); return ra0mem(r); }
968 static int sh1620( int x) { return opp_u_field(x, 20, 16); }
969 static int sh30( int x) { return opp_u_field(x, 30, 30); }
970 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
971 static int si( int x) { return opp_s_field(x, 31, 16); }
972 static int spr( int x) { return opp_u_field(x, 20, 11); }
973 static int sr( int x) { return opp_u_field(x, 15, 12); }
974 static int tbr( int x) { return opp_u_field(x, 20, 11); }
975 static int th( int x) { return opp_u_field(x, 10, 7); }
976 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
977 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
978 static int to( int x) { return opp_u_field(x, 10, 6); }
979 static int u( int x) { return opp_u_field(x, 19, 16); }
980 static int ui( int x) { return opp_u_field(x, 31, 16); }
982 // Support vector instructions for >= Power6.
983 static int vra( int x) { return opp_u_field(x, 15, 11); }
984 static int vrb( int x) { return opp_u_field(x, 20, 16); }
985 static int vrc( int x) { return opp_u_field(x, 25, 21); }
986 static int vrs( int x) { return opp_u_field(x, 10, 6); }
987 static int vrt( int x) { return opp_u_field(x, 10, 6); }
989 static int vra( VectorRegister r) { return vra(r->encoding());}
990 static int vrb( VectorRegister r) { return vrb(r->encoding());}
991 static int vrc( VectorRegister r) { return vrc(r->encoding());}
992 static int vrs( VectorRegister r) { return vrs(r->encoding());}
993 static int vrt( VectorRegister r) { return vrt(r->encoding());}
995 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
996 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
997 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
998 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
1000 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
1001 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
1002 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
1003 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1004 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1005 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1006 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1008 protected:
1009 // Compute relative address for branch.
1010 static intptr_t disp(intptr_t x, intptr_t off) {
1011 int xx = x - off;
1012 xx = xx >> 2;
1013 return xx;
1014 }
1016 public:
1017 // signed immediate, in low bits, nbits long
1018 static int simm(int x, int nbits) {
1019 assert_signed_range(x, nbits);
1020 return x & ((1 << nbits) - 1);
1021 }
1023 // unsigned immediate, in low bits, nbits long
1024 static int uimm(int x, int nbits) {
1025 assert_unsigned_const(x, nbits);
1026 return x & ((1 << nbits) - 1);
1027 }
1029 static void set_imm(int* instr, short s) {
1030 // imm is always in the lower 16 bits of the instruction,
1031 // so this is endian-neutral. Same for the get_imm below.
1032 uint32_t w = *(uint32_t *)instr;
1033 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
1034 }
1036 static int get_imm(address a, int instruction_number) {
1037 return (short)((int *)a)[instruction_number];
1038 }
1040 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); }
1041 static inline int lo16_unsigned(int x) { return x & 0xffff; }
1043 protected:
1045 // Extract the top 32 bits in a 64 bit word.
1046 static int32_t hi32(int64_t x) {
1047 int32_t r = int32_t((uint64_t)x >> 32);
1048 return r;
1049 }
1051 public:
1053 static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1054 return ((addr + (a - 1)) & ~(a - 1));
1055 }
1057 static inline bool is_aligned(unsigned int addr, unsigned int a) {
1058 return (0 == addr % a);
1059 }
1061 void flush() {
1062 AbstractAssembler::flush();
1063 }
1065 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
1066 inline void emit_data(int);
1067 inline void emit_data(int, RelocationHolder const&);
1068 inline void emit_data(int, relocInfo::relocType rtype);
1070 // Emit an address.
1071 inline address emit_addr(const address addr = NULL);
1073 #if !defined(ABI_ELFv2)
1074 // Emit a function descriptor with the specified entry point, TOC,
1075 // and ENV. If the entry point is NULL, the descriptor will point
1076 // just past the descriptor.
1077 // Use values from friend functions as defaults.
1078 inline address emit_fd(address entry = NULL,
1079 address toc = (address) FunctionDescriptor::friend_toc,
1080 address env = (address) FunctionDescriptor::friend_env);
1081 #endif
1083 /////////////////////////////////////////////////////////////////////////////////////
1084 // PPC instructions
1085 /////////////////////////////////////////////////////////////////////////////////////
1087 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1088 // immediates. The normal instruction encoders enforce that r0 is not
1089 // passed to them. Use either extended mnemonics encoders or the special ra0
1090 // versions.
1092 // Issue an illegal instruction.
1093 inline void illtrap();
1094 static inline bool is_illtrap(int x);
1096 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1097 inline void addi( Register d, Register a, int si16);
1098 inline void addis(Register d, Register a, int si16);
1099 private:
1100 inline void addi_r0ok( Register d, Register a, int si16);
1101 inline void addis_r0ok(Register d, Register a, int si16);
1102 public:
1103 inline void addic_( Register d, Register a, int si16);
1104 inline void subfic( Register d, Register a, int si16);
1105 inline void add( Register d, Register a, Register b);
1106 inline void add_( Register d, Register a, Register b);
1107 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec.
1108 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability.
1109 inline void subf_( Register d, Register a, Register b);
1110 inline void addc( Register d, Register a, Register b);
1111 inline void addc_( Register d, Register a, Register b);
1112 inline void subfc( Register d, Register a, Register b);
1113 inline void subfc_( Register d, Register a, Register b);
1114 inline void adde( Register d, Register a, Register b);
1115 inline void adde_( Register d, Register a, Register b);
1116 inline void subfe( Register d, Register a, Register b);
1117 inline void subfe_( Register d, Register a, Register b);
1118 inline void neg( Register d, Register a);
1119 inline void neg_( Register d, Register a);
1120 inline void mulli( Register d, Register a, int si16);
1121 inline void mulld( Register d, Register a, Register b);
1122 inline void mulld_( Register d, Register a, Register b);
1123 inline void mullw( Register d, Register a, Register b);
1124 inline void mullw_( Register d, Register a, Register b);
1125 inline void mulhw( Register d, Register a, Register b);
1126 inline void mulhw_( Register d, Register a, Register b);
1127 inline void mulhd( Register d, Register a, Register b);
1128 inline void mulhd_( Register d, Register a, Register b);
1129 inline void mulhdu( Register d, Register a, Register b);
1130 inline void mulhdu_(Register d, Register a, Register b);
1131 inline void divd( Register d, Register a, Register b);
1132 inline void divd_( Register d, Register a, Register b);
1133 inline void divw( Register d, Register a, Register b);
1134 inline void divw_( Register d, Register a, Register b);
1136 // extended mnemonics
1137 inline void li( Register d, int si16);
1138 inline void lis( Register d, int si16);
1139 inline void addir(Register d, int si16, Register a);
1141 static bool is_addi(int x) {
1142 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1143 }
1144 static bool is_addis(int x) {
1145 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1146 }
1147 static bool is_bxx(int x) {
1148 return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1149 }
1150 static bool is_b(int x) {
1151 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1152 }
1153 static bool is_bl(int x) {
1154 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1155 }
1156 static bool is_bcxx(int x) {
1157 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1158 }
1159 static bool is_bxx_or_bcxx(int x) {
1160 return is_bxx(x) || is_bcxx(x);
1161 }
1162 static bool is_bctrl(int x) {
1163 return x == 0x4e800421;
1164 }
1165 static bool is_bctr(int x) {
1166 return x == 0x4e800420;
1167 }
1168 static bool is_bclr(int x) {
1169 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1170 }
1171 static bool is_li(int x) {
1172 return is_addi(x) && inv_ra_field(x)==0;
1173 }
1174 static bool is_lis(int x) {
1175 return is_addis(x) && inv_ra_field(x)==0;
1176 }
1177 static bool is_mtctr(int x) {
1178 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1179 }
1180 static bool is_ld(int x) {
1181 return LD_OPCODE == (x & LD_OPCODE_MASK);
1182 }
1183 static bool is_std(int x) {
1184 return STD_OPCODE == (x & STD_OPCODE_MASK);
1185 }
1186 static bool is_stdu(int x) {
1187 return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1188 }
1189 static bool is_stdx(int x) {
1190 return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1191 }
1192 static bool is_stdux(int x) {
1193 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1194 }
1195 static bool is_stwx(int x) {
1196 return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1197 }
1198 static bool is_stwux(int x) {
1199 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1200 }
1201 static bool is_stw(int x) {
1202 return STW_OPCODE == (x & STW_OPCODE_MASK);
1203 }
1204 static bool is_stwu(int x) {
1205 return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1206 }
1207 static bool is_ori(int x) {
1208 return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1209 };
1210 static bool is_oris(int x) {
1211 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1212 };
1213 static bool is_rldicr(int x) {
1214 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1215 };
1216 static bool is_nop(int x) {
1217 return x == 0x60000000;
1218 }
1219 // endgroup opcode for Power6
1220 static bool is_endgroup(int x) {
1221 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1222 }
1225 private:
1226 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1227 inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1228 inline void cmp( ConditionRegister bf, int l, Register a, Register b);
1229 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1230 inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1232 public:
1233 // extended mnemonics of Compare Instructions
1234 inline void cmpwi( ConditionRegister crx, Register a, int si16);
1235 inline void cmpdi( ConditionRegister crx, Register a, int si16);
1236 inline void cmpw( ConditionRegister crx, Register a, Register b);
1237 inline void cmpd( ConditionRegister crx, Register a, Register b);
1238 inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1239 inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1240 inline void cmplw( ConditionRegister crx, Register a, Register b);
1241 inline void cmpld( ConditionRegister crx, Register a, Register b);
1243 inline void isel( Register d, Register a, Register b, int bc);
1244 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1245 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1246 // Set d = 0 if (cr.cc) equals 1, otherwise b.
1247 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1249 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1250 void andi( Register a, Register s, int ui16); // optimized version
1251 inline void andi_( Register a, Register s, int ui16);
1252 inline void andis_( Register a, Register s, int ui16);
1253 inline void ori( Register a, Register s, int ui16);
1254 inline void oris( Register a, Register s, int ui16);
1255 inline void xori( Register a, Register s, int ui16);
1256 inline void xoris( Register a, Register s, int ui16);
1257 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
1258 inline void and_( Register a, Register s, Register b);
1259 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1260 // SMT-priority change instruction (see SMT instructions below).
1261 inline void or_unchecked(Register a, Register s, Register b);
1262 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
1263 inline void or_( Register a, Register s, Register b);
1264 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword
1265 inline void xor_( Register a, Register s, Register b);
1266 inline void nand( Register a, Register s, Register b);
1267 inline void nand_( Register a, Register s, Register b);
1268 inline void nor( Register a, Register s, Register b);
1269 inline void nor_( Register a, Register s, Register b);
1270 inline void andc( Register a, Register s, Register b);
1271 inline void andc_( Register a, Register s, Register b);
1272 inline void orc( Register a, Register s, Register b);
1273 inline void orc_( Register a, Register s, Register b);
1274 inline void extsb( Register a, Register s);
1275 inline void extsh( Register a, Register s);
1276 inline void extsw( Register a, Register s);
1278 // extended mnemonics
1279 inline void nop();
1280 // NOP for FP and BR units (different versions to allow them to be in one group)
1281 inline void fpnop0();
1282 inline void fpnop1();
1283 inline void brnop0();
1284 inline void brnop1();
1285 inline void brnop2();
1287 inline void mr( Register d, Register s);
1288 inline void ori_opt( Register d, int ui16);
1289 inline void oris_opt(Register d, int ui16);
1291 // endgroup opcode for Power6
1292 inline void endgroup();
1294 // count instructions
1295 inline void cntlzw( Register a, Register s);
1296 inline void cntlzw_( Register a, Register s);
1297 inline void cntlzd( Register a, Register s);
1298 inline void cntlzd_( Register a, Register s);
1300 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1301 inline void sld( Register a, Register s, Register b);
1302 inline void sld_( Register a, Register s, Register b);
1303 inline void slw( Register a, Register s, Register b);
1304 inline void slw_( Register a, Register s, Register b);
1305 inline void srd( Register a, Register s, Register b);
1306 inline void srd_( Register a, Register s, Register b);
1307 inline void srw( Register a, Register s, Register b);
1308 inline void srw_( Register a, Register s, Register b);
1309 inline void srad( Register a, Register s, Register b);
1310 inline void srad_( Register a, Register s, Register b);
1311 inline void sraw( Register a, Register s, Register b);
1312 inline void sraw_( Register a, Register s, Register b);
1313 inline void sradi( Register a, Register s, int sh6);
1314 inline void sradi_( Register a, Register s, int sh6);
1315 inline void srawi( Register a, Register s, int sh5);
1316 inline void srawi_( Register a, Register s, int sh5);
1318 // extended mnemonics for Shift Instructions
1319 inline void sldi( Register a, Register s, int sh6);
1320 inline void sldi_( Register a, Register s, int sh6);
1321 inline void slwi( Register a, Register s, int sh5);
1322 inline void slwi_( Register a, Register s, int sh5);
1323 inline void srdi( Register a, Register s, int sh6);
1324 inline void srdi_( Register a, Register s, int sh6);
1325 inline void srwi( Register a, Register s, int sh5);
1326 inline void srwi_( Register a, Register s, int sh5);
1328 inline void clrrdi( Register a, Register s, int ui6);
1329 inline void clrrdi_( Register a, Register s, int ui6);
1330 inline void clrldi( Register a, Register s, int ui6);
1331 inline void clrldi_( Register a, Register s, int ui6);
1332 inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1333 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1334 inline void extrdi( Register a, Register s, int n, int b);
1335 // testbit with condition register
1336 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1338 // rotate instructions
1339 inline void rotldi( Register a, Register s, int n);
1340 inline void rotrdi( Register a, Register s, int n);
1341 inline void rotlwi( Register a, Register s, int n);
1342 inline void rotrwi( Register a, Register s, int n);
1344 // Rotate Instructions
1345 inline void rldic( Register a, Register s, int sh6, int mb6);
1346 inline void rldic_( Register a, Register s, int sh6, int mb6);
1347 inline void rldicr( Register a, Register s, int sh6, int mb6);
1348 inline void rldicr_( Register a, Register s, int sh6, int mb6);
1349 inline void rldicl( Register a, Register s, int sh6, int mb6);
1350 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1351 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1352 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1353 inline void rldimi( Register a, Register s, int sh6, int mb6);
1354 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1355 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1356 inline void insrdi( Register a, Register s, int n, int b);
1357 inline void insrwi( Register a, Register s, int n, int b);
1359 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1360 // 4 bytes
1361 inline void lwzx( Register d, Register s1, Register s2);
1362 inline void lwz( Register d, int si16, Register s1);
1363 inline void lwzu( Register d, int si16, Register s1);
1365 // 4 bytes
1366 inline void lwax( Register d, Register s1, Register s2);
1367 inline void lwa( Register d, int si16, Register s1);
1369 // 4 bytes reversed
1370 inline void lwbrx( Register d, Register s1, Register s2);
1372 // 2 bytes
1373 inline void lhzx( Register d, Register s1, Register s2);
1374 inline void lhz( Register d, int si16, Register s1);
1375 inline void lhzu( Register d, int si16, Register s1);
1377 // 2 bytes reversed
1378 inline void lhbrx( Register d, Register s1, Register s2);
1380 // 2 bytes
1381 inline void lhax( Register d, Register s1, Register s2);
1382 inline void lha( Register d, int si16, Register s1);
1383 inline void lhau( Register d, int si16, Register s1);
1385 // 1 byte
1386 inline void lbzx( Register d, Register s1, Register s2);
1387 inline void lbz( Register d, int si16, Register s1);
1388 inline void lbzu( Register d, int si16, Register s1);
1390 // 8 bytes
1391 inline void ldx( Register d, Register s1, Register s2);
1392 inline void ld( Register d, int si16, Register s1);
1393 inline void ldu( Register d, int si16, Register s1);
1395 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
1396 inline void stwx( Register d, Register s1, Register s2);
1397 inline void stw( Register d, int si16, Register s1);
1398 inline void stwu( Register d, int si16, Register s1);
1400 inline void sthx( Register d, Register s1, Register s2);
1401 inline void sth( Register d, int si16, Register s1);
1402 inline void sthu( Register d, int si16, Register s1);
1404 inline void stbx( Register d, Register s1, Register s2);
1405 inline void stb( Register d, int si16, Register s1);
1406 inline void stbu( Register d, int si16, Register s1);
1408 inline void stdx( Register d, Register s1, Register s2);
1409 inline void std( Register d, int si16, Register s1);
1410 inline void stdu( Register d, int si16, Register s1);
1411 inline void stdux(Register s, Register a, Register b);
1413 // PPC 1, section 3.3.13 Move To/From System Register Instructions
1414 inline void mtlr( Register s1);
1415 inline void mflr( Register d);
1416 inline void mtctr(Register s1);
1417 inline void mfctr(Register d);
1418 inline void mtcrf(int fxm, Register s);
1419 inline void mfcr( Register d);
1420 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1421 inline void mtcr( Register s);
1423 // PPC 1, section 2.4.1 Branch Instructions
1424 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1425 inline void b( Label& L);
1426 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1427 inline void bl( Label& L);
1428 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1429 inline void bc( int boint, int biint, Label& L);
1430 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1431 inline void bcl(int boint, int biint, Label& L);
1433 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1434 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1435 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1436 relocInfo::relocType rt = relocInfo::none);
1437 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1438 relocInfo::relocType rt = relocInfo::none);
1440 // helper function for b, bcxx
1441 inline bool is_within_range_of_b(address a, address pc);
1442 inline bool is_within_range_of_bcxx(address a, address pc);
1444 // get the destination of a bxx branch (b, bl, ba, bla)
1445 static inline address bxx_destination(address baddr);
1446 static inline address bxx_destination(int instr, address pc);
1447 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1449 // extended mnemonics for branch instructions
1450 inline void blt(ConditionRegister crx, Label& L);
1451 inline void bgt(ConditionRegister crx, Label& L);
1452 inline void beq(ConditionRegister crx, Label& L);
1453 inline void bso(ConditionRegister crx, Label& L);
1454 inline void bge(ConditionRegister crx, Label& L);
1455 inline void ble(ConditionRegister crx, Label& L);
1456 inline void bne(ConditionRegister crx, Label& L);
1457 inline void bns(ConditionRegister crx, Label& L);
1459 // Branch instructions with static prediction hints.
1460 inline void blt_predict_taken( ConditionRegister crx, Label& L);
1461 inline void bgt_predict_taken( ConditionRegister crx, Label& L);
1462 inline void beq_predict_taken( ConditionRegister crx, Label& L);
1463 inline void bso_predict_taken( ConditionRegister crx, Label& L);
1464 inline void bge_predict_taken( ConditionRegister crx, Label& L);
1465 inline void ble_predict_taken( ConditionRegister crx, Label& L);
1466 inline void bne_predict_taken( ConditionRegister crx, Label& L);
1467 inline void bns_predict_taken( ConditionRegister crx, Label& L);
1468 inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1469 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1470 inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1471 inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1472 inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1473 inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1474 inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1475 inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1477 // for use in conjunction with testbitdi:
1478 inline void btrue( ConditionRegister crx, Label& L);
1479 inline void bfalse(ConditionRegister crx, Label& L);
1481 inline void bltl(ConditionRegister crx, Label& L);
1482 inline void bgtl(ConditionRegister crx, Label& L);
1483 inline void beql(ConditionRegister crx, Label& L);
1484 inline void bsol(ConditionRegister crx, Label& L);
1485 inline void bgel(ConditionRegister crx, Label& L);
1486 inline void blel(ConditionRegister crx, Label& L);
1487 inline void bnel(ConditionRegister crx, Label& L);
1488 inline void bnsl(ConditionRegister crx, Label& L);
1490 // extended mnemonics for Branch Instructions via LR
1491 // We use `blr' for returns.
1492 inline void blr(relocInfo::relocType rt = relocInfo::none);
1494 // extended mnemonics for Branch Instructions with CTR
1495 // bdnz means `decrement CTR and jump to L if CTR is not zero'
1496 inline void bdnz(Label& L);
1497 // Decrement and branch if result is zero.
1498 inline void bdz(Label& L);
1499 // we use `bctr[l]' for jumps/calls in function descriptor glue
1500 // code, e.g. calls to runtime functions
1501 inline void bctr( relocInfo::relocType rt = relocInfo::none);
1502 inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1503 // conditional jumps/branches via CTR
1504 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1505 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1506 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1507 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1509 // condition register logic instructions
1510 inline void crand( int d, int s1, int s2);
1511 inline void crnand(int d, int s1, int s2);
1512 inline void cror( int d, int s1, int s2);
1513 inline void crxor( int d, int s1, int s2);
1514 inline void crnor( int d, int s1, int s2);
1515 inline void creqv( int d, int s1, int s2);
1516 inline void crandc(int d, int s1, int s2);
1517 inline void crorc( int d, int s1, int s2);
1519 // icache and dcache related instructions
1520 inline void icbi( Register s1, Register s2);
1521 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1522 inline void dcbz( Register s1, Register s2);
1523 inline void dcbst( Register s1, Register s2);
1524 inline void dcbf( Register s1, Register s2);
1526 enum ct_cache_specification {
1527 ct_primary_cache = 0,
1528 ct_secondary_cache = 2
1529 };
1530 // dcache read hint
1531 inline void dcbt( Register s1, Register s2);
1532 inline void dcbtct( Register s1, Register s2, int ct);
1533 inline void dcbtds( Register s1, Register s2, int ds);
1534 // dcache write hint
1535 inline void dcbtst( Register s1, Register s2);
1536 inline void dcbtstct(Register s1, Register s2, int ct);
1538 // machine barrier instructions:
1539 //
1540 // - sync two-way memory barrier, aka fence
1541 // - lwsync orders Store|Store,
1542 // Load|Store,
1543 // Load|Load,
1544 // but not Store|Load
1545 // - eieio orders memory accesses for device memory (only)
1546 // - isync invalidates speculatively executed instructions
1547 // From the Power ISA 2.06 documentation:
1548 // "[...] an isync instruction prevents the execution of
1549 // instructions following the isync until instructions
1550 // preceding the isync have completed, [...]"
1551 // From IBM's AIX assembler reference:
1552 // "The isync [...] instructions causes the processor to
1553 // refetch any instructions that might have been fetched
1554 // prior to the isync instruction. The instruction isync
1555 // causes the processor to wait for all previous instructions
1556 // to complete. Then any instructions already fetched are
1557 // discarded and instruction processing continues in the
1558 // environment established by the previous instructions."
1559 //
1560 // semantic barrier instructions:
1561 // (as defined in orderAccess.hpp)
1562 //
1563 // - release orders Store|Store, (maps to lwsync)
1564 // Load|Store
1565 // - acquire orders Load|Store, (maps to lwsync)
1566 // Load|Load
1567 // - fence orders Store|Store, (maps to sync)
1568 // Load|Store,
1569 // Load|Load,
1570 // Store|Load
1571 //
1572 private:
1573 inline void sync(int l);
1574 public:
1575 inline void sync();
1576 inline void lwsync();
1577 inline void ptesync();
1578 inline void eieio();
1579 inline void isync();
1580 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1582 // atomics
1583 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1584 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1585 inline bool lxarx_hint_exclusive_access();
1586 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1587 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1588 inline void stwcx_( Register s, Register a, Register b);
1589 inline void stdcx_( Register s, Register a, Register b);
1591 // Instructions for adjusting thread priority for simultaneous
1592 // multithreading (SMT) on Power5.
1593 private:
1594 inline void smt_prio_very_low();
1595 inline void smt_prio_medium_high();
1596 inline void smt_prio_high();
1598 public:
1599 inline void smt_prio_low();
1600 inline void smt_prio_medium_low();
1601 inline void smt_prio_medium();
1603 // trap instructions
1604 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1605 // NOT FOR DIRECT USE!!
1606 protected:
1607 inline void tdi_unchecked(int tobits, Register a, int si16);
1608 inline void twi_unchecked(int tobits, Register a, int si16);
1609 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1610 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1611 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP
1612 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP
1614 static bool is_tdi(int x, int tobits, int ra, int si16) {
1615 return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
1616 && (tobits == inv_to_field(x))
1617 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1618 && (si16 == inv_si_field(x));
1619 }
1621 static bool is_twi(int x, int tobits, int ra, int si16) {
1622 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1623 && (tobits == inv_to_field(x))
1624 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1625 && (si16 == inv_si_field(x));
1626 }
1628 static bool is_twi(int x, int tobits, int ra) {
1629 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1630 && (tobits == inv_to_field(x))
1631 && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
1632 }
1634 static bool is_td(int x, int tobits, int ra, int rb) {
1635 return (TD_OPCODE == (x & TD_OPCODE_MASK))
1636 && (tobits == inv_to_field(x))
1637 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1638 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1639 }
1641 static bool is_tw(int x, int tobits, int ra, int rb) {
1642 return (TW_OPCODE == (x & TW_OPCODE_MASK))
1643 && (tobits == inv_to_field(x))
1644 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1645 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1646 }
1648 public:
1649 // PPC floating point instructions
1650 // PPC 1, section 4.6.2 Floating-Point Load Instructions
1651 inline void lfs( FloatRegister d, int si16, Register a);
1652 inline void lfsu( FloatRegister d, int si16, Register a);
1653 inline void lfsx( FloatRegister d, Register a, Register b);
1654 inline void lfd( FloatRegister d, int si16, Register a);
1655 inline void lfdu( FloatRegister d, int si16, Register a);
1656 inline void lfdx( FloatRegister d, Register a, Register b);
1658 // PPC 1, section 4.6.3 Floating-Point Store Instructions
1659 inline void stfs( FloatRegister s, int si16, Register a);
1660 inline void stfsu( FloatRegister s, int si16, Register a);
1661 inline void stfsx( FloatRegister s, Register a, Register b);
1662 inline void stfd( FloatRegister s, int si16, Register a);
1663 inline void stfdu( FloatRegister s, int si16, Register a);
1664 inline void stfdx( FloatRegister s, Register a, Register b);
1666 // PPC 1, section 4.6.4 Floating-Point Move Instructions
1667 inline void fmr( FloatRegister d, FloatRegister b);
1668 inline void fmr_( FloatRegister d, FloatRegister b);
1670 // inline void mffgpr( FloatRegister d, Register b);
1671 // inline void mftgpr( Register d, FloatRegister b);
1672 inline void cmpb( Register a, Register s, Register b);
1673 inline void popcntb(Register a, Register s);
1674 inline void popcntw(Register a, Register s);
1675 inline void popcntd(Register a, Register s);
1677 inline void fneg( FloatRegister d, FloatRegister b);
1678 inline void fneg_( FloatRegister d, FloatRegister b);
1679 inline void fabs( FloatRegister d, FloatRegister b);
1680 inline void fabs_( FloatRegister d, FloatRegister b);
1681 inline void fnabs( FloatRegister d, FloatRegister b);
1682 inline void fnabs_(FloatRegister d, FloatRegister b);
1684 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
1685 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b);
1686 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
1687 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
1688 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
1689 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b);
1690 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
1691 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
1692 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
1693 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c);
1694 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
1695 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
1696 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
1697 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b);
1698 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
1699 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
1700 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
1702 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
1703 inline void frsp( FloatRegister d, FloatRegister b);
1704 inline void fctid( FloatRegister d, FloatRegister b);
1705 inline void fctidz(FloatRegister d, FloatRegister b);
1706 inline void fctiw( FloatRegister d, FloatRegister b);
1707 inline void fctiwz(FloatRegister d, FloatRegister b);
1708 inline void fcfid( FloatRegister d, FloatRegister b);
1709 inline void fcfids(FloatRegister d, FloatRegister b);
1711 // PPC 1, section 4.6.7 Floating-Point Compare Instructions
1712 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
1714 inline void fsqrt( FloatRegister d, FloatRegister b);
1715 inline void fsqrts(FloatRegister d, FloatRegister b);
1717 // Vector instructions for >= Power6.
1718 inline void lvebx( VectorRegister d, Register s1, Register s2);
1719 inline void lvehx( VectorRegister d, Register s1, Register s2);
1720 inline void lvewx( VectorRegister d, Register s1, Register s2);
1721 inline void lvx( VectorRegister d, Register s1, Register s2);
1722 inline void lvxl( VectorRegister d, Register s1, Register s2);
1723 inline void stvebx( VectorRegister d, Register s1, Register s2);
1724 inline void stvehx( VectorRegister d, Register s1, Register s2);
1725 inline void stvewx( VectorRegister d, Register s1, Register s2);
1726 inline void stvx( VectorRegister d, Register s1, Register s2);
1727 inline void stvxl( VectorRegister d, Register s1, Register s2);
1728 inline void lvsl( VectorRegister d, Register s1, Register s2);
1729 inline void lvsr( VectorRegister d, Register s1, Register s2);
1730 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b);
1731 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b);
1732 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b);
1733 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b);
1734 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b);
1735 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b);
1736 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b);
1737 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b);
1738 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
1739 inline void vupkhpx( VectorRegister d, VectorRegister b);
1740 inline void vupkhsb( VectorRegister d, VectorRegister b);
1741 inline void vupkhsh( VectorRegister d, VectorRegister b);
1742 inline void vupklpx( VectorRegister d, VectorRegister b);
1743 inline void vupklsb( VectorRegister d, VectorRegister b);
1744 inline void vupklsh( VectorRegister d, VectorRegister b);
1745 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
1746 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
1747 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
1748 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
1749 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
1750 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
1751 inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
1752 inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
1753 inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
1754 inline void vspltisb( VectorRegister d, int si5);
1755 inline void vspltish( VectorRegister d, int si5);
1756 inline void vspltisw( VectorRegister d, int si5);
1757 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1758 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1759 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
1760 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4);
1761 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
1762 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
1763 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
1764 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1765 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
1766 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1767 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
1768 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
1769 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
1770 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
1771 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
1772 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
1773 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
1774 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1775 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
1776 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1777 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b);
1778 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b);
1779 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b);
1780 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b);
1781 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b);
1782 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b);
1783 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b);
1784 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b);
1785 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b);
1786 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b);
1787 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b);
1788 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b);
1789 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b);
1790 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b);
1791 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b);
1792 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1793 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
1794 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1795 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1796 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1797 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1798 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1799 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1800 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1801 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b);
1802 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
1803 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
1804 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
1805 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
1806 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b);
1807 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b);
1808 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b);
1809 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b);
1810 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b);
1811 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b);
1812 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b);
1813 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b);
1814 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b);
1815 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b);
1816 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b);
1817 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b);
1818 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b);
1819 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b);
1820 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b);
1821 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b);
1822 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b);
1823 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b);
1824 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
1825 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
1826 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
1827 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
1828 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
1829 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
1830 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
1831 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
1832 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
1833 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
1834 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
1835 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
1836 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
1837 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
1838 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
1839 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
1840 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
1841 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
1842 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b);
1843 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
1844 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
1845 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
1846 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
1847 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
1848 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
1849 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
1850 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
1851 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
1852 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
1853 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
1854 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
1855 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
1856 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
1857 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
1858 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1859 // Vector Floating-Point not implemented yet
1860 inline void mtvscr( VectorRegister b);
1861 inline void mfvscr( VectorRegister d);
1863 // The following encoders use r0 as second operand. These instructions
1864 // read r0 as '0'.
1865 inline void lwzx( Register d, Register s2);
1866 inline void lwz( Register d, int si16);
1867 inline void lwax( Register d, Register s2);
1868 inline void lwa( Register d, int si16);
1869 inline void lwbrx(Register d, Register s2);
1870 inline void lhzx( Register d, Register s2);
1871 inline void lhz( Register d, int si16);
1872 inline void lhax( Register d, Register s2);
1873 inline void lha( Register d, int si16);
1874 inline void lhbrx(Register d, Register s2);
1875 inline void lbzx( Register d, Register s2);
1876 inline void lbz( Register d, int si16);
1877 inline void ldx( Register d, Register s2);
1878 inline void ld( Register d, int si16);
1879 inline void stwx( Register d, Register s2);
1880 inline void stw( Register d, int si16);
1881 inline void sthx( Register d, Register s2);
1882 inline void sth( Register d, int si16);
1883 inline void stbx( Register d, Register s2);
1884 inline void stb( Register d, int si16);
1885 inline void stdx( Register d, Register s2);
1886 inline void std( Register d, int si16);
1888 // PPC 2, section 3.2.1 Instruction Cache Instructions
1889 inline void icbi( Register s2);
1890 // PPC 2, section 3.2.2 Data Cache Instructions
1891 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
1892 inline void dcbz( Register s2);
1893 inline void dcbst( Register s2);
1894 inline void dcbf( Register s2);
1895 // dcache read hint
1896 inline void dcbt( Register s2);
1897 inline void dcbtct( Register s2, int ct);
1898 inline void dcbtds( Register s2, int ds);
1899 // dcache write hint
1900 inline void dcbtst( Register s2);
1901 inline void dcbtstct(Register s2, int ct);
1903 // Atomics: use ra0mem to disallow R0 as base.
1904 inline void lwarx_unchecked(Register d, Register b, int eh1);
1905 inline void ldarx_unchecked(Register d, Register b, int eh1);
1906 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
1907 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
1908 inline void stwcx_(Register s, Register b);
1909 inline void stdcx_(Register s, Register b);
1910 inline void lfs( FloatRegister d, int si16);
1911 inline void lfsx( FloatRegister d, Register b);
1912 inline void lfd( FloatRegister d, int si16);
1913 inline void lfdx( FloatRegister d, Register b);
1914 inline void stfs( FloatRegister s, int si16);
1915 inline void stfsx( FloatRegister s, Register b);
1916 inline void stfd( FloatRegister s, int si16);
1917 inline void stfdx( FloatRegister s, Register b);
1918 inline void lvebx( VectorRegister d, Register s2);
1919 inline void lvehx( VectorRegister d, Register s2);
1920 inline void lvewx( VectorRegister d, Register s2);
1921 inline void lvx( VectorRegister d, Register s2);
1922 inline void lvxl( VectorRegister d, Register s2);
1923 inline void stvebx(VectorRegister d, Register s2);
1924 inline void stvehx(VectorRegister d, Register s2);
1925 inline void stvewx(VectorRegister d, Register s2);
1926 inline void stvx( VectorRegister d, Register s2);
1927 inline void stvxl( VectorRegister d, Register s2);
1928 inline void lvsl( VectorRegister d, Register s2);
1929 inline void lvsr( VectorRegister d, Register s2);
1931 // RegisterOrConstant versions.
1932 // These emitters choose between the versions using two registers and
1933 // those with register and immediate, depending on the content of roc.
1934 // If the constant is not encodable as immediate, instructions to
1935 // load the constant are emitted beforehand. Store instructions need a
1936 // tmp reg if the constant is not encodable as immediate.
1937 // Size unpredictable.
1938 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg);
1939 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
1940 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1941 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
1942 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1943 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1944 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1945 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1946 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1947 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1948 void add( Register d, RegisterOrConstant roc, Register s1);
1949 void subf(Register d, RegisterOrConstant roc, Register s1);
1950 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
1953 // Emit several instructions to load a 64 bit constant. This issues a fixed
1954 // instruction pattern so that the constant can be patched later on.
1955 enum {
1956 load_const_size = 5 * BytesPerInstWord
1957 };
1958 void load_const(Register d, long a, Register tmp = noreg);
1959 inline void load_const(Register d, void* a, Register tmp = noreg);
1960 inline void load_const(Register d, Label& L, Register tmp = noreg);
1961 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
1963 // Load a 64 bit constant, optimized, not identifyable.
1964 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
1965 // 16 bit immediate offset. This is useful if the offset can be encoded in
1966 // a succeeding instruction.
1967 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false);
1968 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
1969 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
1970 }
1972 // Creation
1973 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1974 #ifdef CHECK_DELAY
1975 delay_state = no_delay;
1976 #endif
1977 }
1979 // Testing
1980 #ifndef PRODUCT
1981 void test_asm();
1982 #endif
1983 };
1986 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP
