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src/cpu/x86/vm/vm_version_x86.cpp@b1bc1af04c6e
src/cpu/x86/vm/vm_version_x86.cpp
Tue, 05 Aug 2014 15:02:10 -0700
- author
- kvn
- date
- Tue, 05 Aug 2014 15:02:10 -0700
- changeset 7025
- b1bc1af04c6e
- parent 6680
- 78bbf4d43a14
- child 7027
- b20a35eae442
- permissions
- -rw-r--r--
8052081: Optimize generated by C2 code for Intel's Atom processor
Summary: Allow to execute vectorization and crc32 optimization on Atom. Enable UseFPUForSpilling by default on x86.
Reviewed-by: roland
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/stubCodeGenerator.hpp"
31 #include "vm_version_x86.hpp"
32 #ifdef TARGET_OS_FAMILY_linux
33 # include "os_linux.inline.hpp"
34 #endif
35 #ifdef TARGET_OS_FAMILY_solaris
36 # include "os_solaris.inline.hpp"
37 #endif
38 #ifdef TARGET_OS_FAMILY_windows
39 # include "os_windows.inline.hpp"
40 #endif
41 #ifdef TARGET_OS_FAMILY_bsd
42 # include "os_bsd.inline.hpp"
43 #endif
46 int VM_Version::_cpu;
47 int VM_Version::_model;
48 int VM_Version::_stepping;
49 int VM_Version::_cpuFeatures;
50 const char* VM_Version::_features_str = "";
51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
53 // Address of instruction which causes SEGV
54 address VM_Version::_cpuinfo_segv_addr = 0;
55 // Address of instruction after the one which causes SEGV
56 address VM_Version::_cpuinfo_cont_addr = 0;
58 static BufferBlob* stub_blob;
59 static const int stub_size = 600;
61 extern "C" {
62 typedef void (*get_cpu_info_stub_t)(void*);
63 }
64 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
67 class VM_Version_StubGenerator: public StubCodeGenerator {
68 public:
70 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
72 address generate_get_cpu_info() {
73 // Flags to test CPU type.
74 const uint32_t HS_EFL_AC = 0x40000;
75 const uint32_t HS_EFL_ID = 0x200000;
76 // Values for when we don't have a CPUID instruction.
77 const int CPU_FAMILY_SHIFT = 8;
78 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
79 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
81 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
82 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
84 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
85 # define __ _masm->
87 address start = __ pc();
89 //
90 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
91 //
92 // LP64: rcx and rdx are first and second argument registers on windows
94 __ push(rbp);
95 #ifdef _LP64
96 __ mov(rbp, c_rarg0); // cpuid_info address
97 #else
98 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
99 #endif
100 __ push(rbx);
101 __ push(rsi);
102 __ pushf(); // preserve rbx, and flags
103 __ pop(rax);
104 __ push(rax);
105 __ mov(rcx, rax);
106 //
107 // if we are unable to change the AC flag, we have a 386
108 //
109 __ xorl(rax, HS_EFL_AC);
110 __ push(rax);
111 __ popf();
112 __ pushf();
113 __ pop(rax);
114 __ cmpptr(rax, rcx);
115 __ jccb(Assembler::notEqual, detect_486);
117 __ movl(rax, CPU_FAMILY_386);
118 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
119 __ jmp(done);
121 //
122 // If we are unable to change the ID flag, we have a 486 which does
123 // not support the "cpuid" instruction.
124 //
125 __ bind(detect_486);
126 __ mov(rax, rcx);
127 __ xorl(rax, HS_EFL_ID);
128 __ push(rax);
129 __ popf();
130 __ pushf();
131 __ pop(rax);
132 __ cmpptr(rcx, rax);
133 __ jccb(Assembler::notEqual, detect_586);
135 __ bind(cpu486);
136 __ movl(rax, CPU_FAMILY_486);
137 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
138 __ jmp(done);
140 //
141 // At this point, we have a chip which supports the "cpuid" instruction
142 //
143 __ bind(detect_586);
144 __ xorl(rax, rax);
145 __ cpuid();
146 __ orl(rax, rax);
147 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
148 // value of at least 1, we give up and
149 // assume a 486
150 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
151 __ movl(Address(rsi, 0), rax);
152 __ movl(Address(rsi, 4), rbx);
153 __ movl(Address(rsi, 8), rcx);
154 __ movl(Address(rsi,12), rdx);
156 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
157 __ jccb(Assembler::belowEqual, std_cpuid4);
159 //
160 // cpuid(0xB) Processor Topology
161 //
162 __ movl(rax, 0xb);
163 __ xorl(rcx, rcx); // Threads level
164 __ cpuid();
166 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
167 __ movl(Address(rsi, 0), rax);
168 __ movl(Address(rsi, 4), rbx);
169 __ movl(Address(rsi, 8), rcx);
170 __ movl(Address(rsi,12), rdx);
172 __ movl(rax, 0xb);
173 __ movl(rcx, 1); // Cores level
174 __ cpuid();
175 __ push(rax);
176 __ andl(rax, 0x1f); // Determine if valid topology level
177 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
178 __ andl(rax, 0xffff);
179 __ pop(rax);
180 __ jccb(Assembler::equal, std_cpuid4);
182 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
183 __ movl(Address(rsi, 0), rax);
184 __ movl(Address(rsi, 4), rbx);
185 __ movl(Address(rsi, 8), rcx);
186 __ movl(Address(rsi,12), rdx);
188 __ movl(rax, 0xb);
189 __ movl(rcx, 2); // Packages level
190 __ cpuid();
191 __ push(rax);
192 __ andl(rax, 0x1f); // Determine if valid topology level
193 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
194 __ andl(rax, 0xffff);
195 __ pop(rax);
196 __ jccb(Assembler::equal, std_cpuid4);
198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
199 __ movl(Address(rsi, 0), rax);
200 __ movl(Address(rsi, 4), rbx);
201 __ movl(Address(rsi, 8), rcx);
202 __ movl(Address(rsi,12), rdx);
204 //
205 // cpuid(0x4) Deterministic cache params
206 //
207 __ bind(std_cpuid4);
208 __ movl(rax, 4);
209 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
210 __ jccb(Assembler::greater, std_cpuid1);
212 __ xorl(rcx, rcx); // L1 cache
213 __ cpuid();
214 __ push(rax);
215 __ andl(rax, 0x1f); // Determine if valid cache parameters used
216 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
217 __ pop(rax);
218 __ jccb(Assembler::equal, std_cpuid1);
220 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
221 __ movl(Address(rsi, 0), rax);
222 __ movl(Address(rsi, 4), rbx);
223 __ movl(Address(rsi, 8), rcx);
224 __ movl(Address(rsi,12), rdx);
226 //
227 // Standard cpuid(0x1)
228 //
229 __ bind(std_cpuid1);
230 __ movl(rax, 1);
231 __ cpuid();
232 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
233 __ movl(Address(rsi, 0), rax);
234 __ movl(Address(rsi, 4), rbx);
235 __ movl(Address(rsi, 8), rcx);
236 __ movl(Address(rsi,12), rdx);
238 //
239 // Check if OS has enabled XGETBV instruction to access XCR0
240 // (OSXSAVE feature flag) and CPU supports AVX
241 //
242 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
243 __ cmpl(rcx, 0x18000000);
244 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
246 //
247 // XCR0, XFEATURE_ENABLED_MASK register
248 //
249 __ xorl(rcx, rcx); // zero for XCR0 register
250 __ xgetbv();
251 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
252 __ movl(Address(rsi, 0), rax);
253 __ movl(Address(rsi, 4), rdx);
255 __ andl(rax, 0x6); // xcr0 bits sse | ymm
256 __ cmpl(rax, 0x6);
257 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
259 //
260 // Some OSs have a bug when upper 128bits of YMM
261 // registers are not restored after a signal processing.
262 // Generate SEGV here (reference through NULL)
263 // and check upper YMM bits after it.
264 //
265 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
266 intx saved_useavx = UseAVX;
267 intx saved_usesse = UseSSE;
268 UseAVX = 1;
269 UseSSE = 2;
271 // load value into all 32 bytes of ymm7 register
272 __ movl(rcx, VM_Version::ymm_test_value());
274 __ movdl(xmm0, rcx);
275 __ pshufd(xmm0, xmm0, 0x00);
276 __ vinsertf128h(xmm0, xmm0, xmm0);
277 __ vmovdqu(xmm7, xmm0);
278 #ifdef _LP64
279 __ vmovdqu(xmm8, xmm0);
280 __ vmovdqu(xmm15, xmm0);
281 #endif
283 __ xorl(rsi, rsi);
284 VM_Version::set_cpuinfo_segv_addr( __ pc() );
285 // Generate SEGV
286 __ movl(rax, Address(rsi, 0));
288 VM_Version::set_cpuinfo_cont_addr( __ pc() );
289 // Returns here after signal. Save xmm0 to check it later.
290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
291 __ vmovdqu(Address(rsi, 0), xmm0);
292 __ vmovdqu(Address(rsi, 32), xmm7);
293 #ifdef _LP64
294 __ vmovdqu(Address(rsi, 64), xmm8);
295 __ vmovdqu(Address(rsi, 96), xmm15);
296 #endif
298 VM_Version::clean_cpuFeatures();
299 UseAVX = saved_useavx;
300 UseSSE = saved_usesse;
302 //
303 // cpuid(0x7) Structured Extended Features
304 //
305 __ bind(sef_cpuid);
306 __ movl(rax, 7);
307 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
308 __ jccb(Assembler::greater, ext_cpuid);
310 __ xorl(rcx, rcx);
311 __ cpuid();
312 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
313 __ movl(Address(rsi, 0), rax);
314 __ movl(Address(rsi, 4), rbx);
316 //
317 // Extended cpuid(0x80000000)
318 //
319 __ bind(ext_cpuid);
320 __ movl(rax, 0x80000000);
321 __ cpuid();
322 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
323 __ jcc(Assembler::belowEqual, done);
324 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
325 __ jccb(Assembler::belowEqual, ext_cpuid1);
326 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
327 __ jccb(Assembler::belowEqual, ext_cpuid5);
328 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
329 __ jccb(Assembler::belowEqual, ext_cpuid7);
330 //
331 // Extended cpuid(0x80000008)
332 //
333 __ movl(rax, 0x80000008);
334 __ cpuid();
335 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
336 __ movl(Address(rsi, 0), rax);
337 __ movl(Address(rsi, 4), rbx);
338 __ movl(Address(rsi, 8), rcx);
339 __ movl(Address(rsi,12), rdx);
341 //
342 // Extended cpuid(0x80000007)
343 //
344 __ bind(ext_cpuid7);
345 __ movl(rax, 0x80000007);
346 __ cpuid();
347 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
348 __ movl(Address(rsi, 0), rax);
349 __ movl(Address(rsi, 4), rbx);
350 __ movl(Address(rsi, 8), rcx);
351 __ movl(Address(rsi,12), rdx);
353 //
354 // Extended cpuid(0x80000005)
355 //
356 __ bind(ext_cpuid5);
357 __ movl(rax, 0x80000005);
358 __ cpuid();
359 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
360 __ movl(Address(rsi, 0), rax);
361 __ movl(Address(rsi, 4), rbx);
362 __ movl(Address(rsi, 8), rcx);
363 __ movl(Address(rsi,12), rdx);
365 //
366 // Extended cpuid(0x80000001)
367 //
368 __ bind(ext_cpuid1);
369 __ movl(rax, 0x80000001);
370 __ cpuid();
371 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
372 __ movl(Address(rsi, 0), rax);
373 __ movl(Address(rsi, 4), rbx);
374 __ movl(Address(rsi, 8), rcx);
375 __ movl(Address(rsi,12), rdx);
377 //
378 // return
379 //
380 __ bind(done);
381 __ popf();
382 __ pop(rsi);
383 __ pop(rbx);
384 __ pop(rbp);
385 __ ret(0);
387 # undef __
389 return start;
390 };
391 };
394 void VM_Version::get_cpu_info_wrapper() {
395 get_cpu_info_stub(&_cpuid_info);
396 }
398 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED
399 #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f()
400 #endif
402 void VM_Version::get_processor_features() {
404 _cpu = 4; // 486 by default
405 _model = 0;
406 _stepping = 0;
407 _cpuFeatures = 0;
408 _logical_processors_per_package = 1;
410 if (!Use486InstrsOnly) {
411 // Get raw processor info
413 // Some platforms (like Win*) need a wrapper around here
414 // in order to properly handle SEGV for YMM registers test.
415 CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper);
417 assert_is_initialized();
418 _cpu = extended_cpu_family();
419 _model = extended_cpu_model();
420 _stepping = cpu_stepping();
422 if (cpu_family() > 4) { // it supports CPUID
423 _cpuFeatures = feature_flags();
424 // Logical processors are only available on P4s and above,
425 // and only if hyperthreading is available.
426 _logical_processors_per_package = logical_processor_count();
427 }
428 }
430 _supports_cx8 = supports_cmpxchg8();
431 // xchg and xadd instructions
432 _supports_atomic_getset4 = true;
433 _supports_atomic_getadd4 = true;
434 LP64_ONLY(_supports_atomic_getset8 = true);
435 LP64_ONLY(_supports_atomic_getadd8 = true);
437 #ifdef _LP64
438 // OS should support SSE for x64 and hardware should support at least SSE2.
439 if (!VM_Version::supports_sse2()) {
440 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
441 }
442 // in 64 bit the use of SSE2 is the minimum
443 if (UseSSE < 2) UseSSE = 2;
444 #endif
446 #ifdef AMD64
447 // flush_icache_stub have to be generated first.
448 // That is why Icache line size is hard coded in ICache class,
449 // see icache_x86.hpp. It is also the reason why we can't use
450 // clflush instruction in 32-bit VM since it could be running
451 // on CPU which does not support it.
452 //
453 // The only thing we can do is to verify that flushed
454 // ICache::line_size has correct value.
455 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
456 // clflush_size is size in quadwords (8 bytes).
457 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
458 #endif
460 // If the OS doesn't support SSE, we can't use this feature even if the HW does
461 if (!os::supports_sse())
462 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
464 if (UseSSE < 4) {
465 _cpuFeatures &= ~CPU_SSE4_1;
466 _cpuFeatures &= ~CPU_SSE4_2;
467 }
469 if (UseSSE < 3) {
470 _cpuFeatures &= ~CPU_SSE3;
471 _cpuFeatures &= ~CPU_SSSE3;
472 _cpuFeatures &= ~CPU_SSE4A;
473 }
475 if (UseSSE < 2)
476 _cpuFeatures &= ~CPU_SSE2;
478 if (UseSSE < 1)
479 _cpuFeatures &= ~CPU_SSE;
481 if (UseAVX < 2)
482 _cpuFeatures &= ~CPU_AVX2;
484 if (UseAVX < 1)
485 _cpuFeatures &= ~CPU_AVX;
487 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
488 _cpuFeatures &= ~CPU_AES;
490 if (logical_processors_per_package() == 1) {
491 // HT processor could be installed on a system which doesn't support HT.
492 _cpuFeatures &= ~CPU_HT;
493 }
495 char buf[256];
496 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
497 cores_per_cpu(), threads_per_core(),
498 cpu_family(), _model, _stepping,
499 (supports_cmov() ? ", cmov" : ""),
500 (supports_cmpxchg8() ? ", cx8" : ""),
501 (supports_fxsr() ? ", fxsr" : ""),
502 (supports_mmx() ? ", mmx" : ""),
503 (supports_sse() ? ", sse" : ""),
504 (supports_sse2() ? ", sse2" : ""),
505 (supports_sse3() ? ", sse3" : ""),
506 (supports_ssse3()? ", ssse3": ""),
507 (supports_sse4_1() ? ", sse4.1" : ""),
508 (supports_sse4_2() ? ", sse4.2" : ""),
509 (supports_popcnt() ? ", popcnt" : ""),
510 (supports_avx() ? ", avx" : ""),
511 (supports_avx2() ? ", avx2" : ""),
512 (supports_aes() ? ", aes" : ""),
513 (supports_clmul() ? ", clmul" : ""),
514 (supports_erms() ? ", erms" : ""),
515 (supports_rtm() ? ", rtm" : ""),
516 (supports_mmx_ext() ? ", mmxext" : ""),
517 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
518 (supports_lzcnt() ? ", lzcnt": ""),
519 (supports_sse4a() ? ", sse4a": ""),
520 (supports_ht() ? ", ht": ""),
521 (supports_tsc() ? ", tsc": ""),
522 (supports_tscinv_bit() ? ", tscinvbit": ""),
523 (supports_tscinv() ? ", tscinv": ""),
524 (supports_bmi1() ? ", bmi1" : ""),
525 (supports_bmi2() ? ", bmi2" : ""));
526 _features_str = strdup(buf);
528 // UseSSE is set to the smaller of what hardware supports and what
529 // the command line requires. I.e., you cannot set UseSSE to 2 on
530 // older Pentiums which do not support it.
531 if (UseSSE > 4) UseSSE=4;
532 if (UseSSE < 0) UseSSE=0;
533 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
534 UseSSE = MIN2((intx)3,UseSSE);
535 if (!supports_sse3()) // Drop to 2 if no SSE3 support
536 UseSSE = MIN2((intx)2,UseSSE);
537 if (!supports_sse2()) // Drop to 1 if no SSE2 support
538 UseSSE = MIN2((intx)1,UseSSE);
539 if (!supports_sse ()) // Drop to 0 if no SSE support
540 UseSSE = 0;
542 if (UseAVX > 2) UseAVX=2;
543 if (UseAVX < 0) UseAVX=0;
544 if (!supports_avx2()) // Drop to 1 if no AVX2 support
545 UseAVX = MIN2((intx)1,UseAVX);
546 if (!supports_avx ()) // Drop to 0 if no AVX support
547 UseAVX = 0;
549 // Use AES instructions if available.
550 if (supports_aes()) {
551 if (FLAG_IS_DEFAULT(UseAES)) {
552 UseAES = true;
553 }
554 } else if (UseAES) {
555 if (!FLAG_IS_DEFAULT(UseAES))
556 warning("AES instructions are not available on this CPU");
557 FLAG_SET_DEFAULT(UseAES, false);
558 }
560 // Use CLMUL instructions if available.
561 if (supports_clmul()) {
562 if (FLAG_IS_DEFAULT(UseCLMUL)) {
563 UseCLMUL = true;
564 }
565 } else if (UseCLMUL) {
566 if (!FLAG_IS_DEFAULT(UseCLMUL))
567 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
568 FLAG_SET_DEFAULT(UseCLMUL, false);
569 }
571 if (UseCLMUL && (UseSSE > 2)) {
572 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
573 UseCRC32Intrinsics = true;
574 }
575 } else if (UseCRC32Intrinsics) {
576 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
577 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
578 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
579 }
581 // The AES intrinsic stubs require AES instruction support (of course)
582 // but also require sse3 mode for instructions it use.
583 if (UseAES && (UseSSE > 2)) {
584 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
585 UseAESIntrinsics = true;
586 }
587 } else if (UseAESIntrinsics) {
588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
589 warning("AES intrinsics are not available on this CPU");
590 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
591 }
593 // Adjust RTM (Restricted Transactional Memory) flags
594 if (!supports_rtm() && UseRTMLocking) {
595 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
596 // setting during arguments processing. See use_biased_locking().
597 // VM_Version_init() is executed after UseBiasedLocking is used
598 // in Thread::allocate().
599 vm_exit_during_initialization("RTM instructions are not available on this CPU");
600 }
602 #if INCLUDE_RTM_OPT
603 if (UseRTMLocking) {
604 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
605 // RTM locking should be used only for applications with
606 // high lock contention. For now we do not use it by default.
607 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
608 }
609 if (!is_power_of_2(RTMTotalCountIncrRate)) {
610 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
611 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
612 }
613 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
614 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
615 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
616 }
617 } else { // !UseRTMLocking
618 if (UseRTMForStackLocks) {
619 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
620 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
621 }
622 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
623 }
624 if (UseRTMDeopt) {
625 FLAG_SET_DEFAULT(UseRTMDeopt, false);
626 }
627 if (PrintPreciseRTMLockingStatistics) {
628 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
629 }
630 }
631 #else
632 if (UseRTMLocking) {
633 // Only C2 does RTM locking optimization.
634 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
635 // setting during arguments processing. See use_biased_locking().
636 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
637 }
638 #endif
640 #ifdef COMPILER2
641 if (UseFPUForSpilling) {
642 if (UseSSE < 2) {
643 // Only supported with SSE2+
644 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
645 }
646 }
647 if (MaxVectorSize > 0) {
648 if (!is_power_of_2(MaxVectorSize)) {
649 warning("MaxVectorSize must be a power of 2");
650 FLAG_SET_DEFAULT(MaxVectorSize, 32);
651 }
652 if (MaxVectorSize > 32) {
653 FLAG_SET_DEFAULT(MaxVectorSize, 32);
654 }
655 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
656 // 32 bytes vectors (in YMM) are only supported with AVX+
657 FLAG_SET_DEFAULT(MaxVectorSize, 16);
658 }
659 if (UseSSE < 2) {
660 // Vectors (in XMM) are only supported with SSE2+
661 FLAG_SET_DEFAULT(MaxVectorSize, 0);
662 }
663 #ifdef ASSERT
664 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
665 tty->print_cr("State of YMM registers after signal handle:");
666 int nreg = 2 LP64_ONLY(+2);
667 const char* ymm_name[4] = {"0", "7", "8", "15"};
668 for (int i = 0; i < nreg; i++) {
669 tty->print("YMM%s:", ymm_name[i]);
670 for (int j = 7; j >=0; j--) {
671 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
672 }
673 tty->cr();
674 }
675 }
676 #endif
677 }
678 #endif
680 // On new cpus instructions which update whole XMM register should be used
681 // to prevent partial register stall due to dependencies on high half.
682 //
683 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
684 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
685 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
686 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
688 if( is_amd() ) { // AMD cpus specific settings
689 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
690 // Use it on new AMD cpus starting from Opteron.
691 UseAddressNop = true;
692 }
693 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
694 // Use it on new AMD cpus starting from Opteron.
695 UseNewLongLShift = true;
696 }
697 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
698 if( supports_sse4a() ) {
699 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
700 } else {
701 UseXmmLoadAndClearUpper = false;
702 }
703 }
704 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
705 if( supports_sse4a() ) {
706 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
707 } else {
708 UseXmmRegToRegMoveAll = false;
709 }
710 }
711 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
712 if( supports_sse4a() ) {
713 UseXmmI2F = true;
714 } else {
715 UseXmmI2F = false;
716 }
717 }
718 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
719 if( supports_sse4a() ) {
720 UseXmmI2D = true;
721 } else {
722 UseXmmI2D = false;
723 }
724 }
725 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
726 if( supports_sse4_2() && UseSSE >= 4 ) {
727 UseSSE42Intrinsics = true;
728 }
729 }
731 // some defaults for AMD family 15h
732 if ( cpu_family() == 0x15 ) {
733 // On family 15h processors default is no sw prefetch
734 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
735 AllocatePrefetchStyle = 0;
736 }
737 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
738 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
739 AllocatePrefetchInstr = 3;
740 }
741 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
742 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
743 UseXMMForArrayCopy = true;
744 }
745 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
746 UseUnalignedLoadStores = true;
747 }
748 }
750 #ifdef COMPILER2
751 if (MaxVectorSize > 16) {
752 // Limit vectors size to 16 bytes on current AMD cpus.
753 FLAG_SET_DEFAULT(MaxVectorSize, 16);
754 }
755 #endif // COMPILER2
756 }
758 if( is_intel() ) { // Intel cpus specific settings
759 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
760 UseStoreImmI16 = false; // don't use it on Intel cpus
761 }
762 if( cpu_family() == 6 || cpu_family() == 15 ) {
763 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
764 // Use it on all Intel cpus starting from PentiumPro
765 UseAddressNop = true;
766 }
767 }
768 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
769 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
770 }
771 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
772 if( supports_sse3() ) {
773 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
774 } else {
775 UseXmmRegToRegMoveAll = false;
776 }
777 }
778 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
779 #ifdef COMPILER2
780 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
781 // For new Intel cpus do the next optimization:
782 // don't align the beginning of a loop if there are enough instructions
783 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
784 // in current fetch line (OptoLoopAlignment) or the padding
785 // is big (> MaxLoopPad).
786 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
787 // generated NOP instructions. 11 is the largest size of one
788 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
789 MaxLoopPad = 11;
790 }
791 #endif // COMPILER2
792 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
793 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
794 }
795 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
796 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
797 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
798 }
799 }
800 if (supports_sse4_2() && UseSSE >= 4) {
801 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
802 UseSSE42Intrinsics = true;
803 }
804 }
805 }
806 if ((cpu_family() == 0x06) &&
807 ((extended_cpu_model() == 0x36) || // Centerton
808 (extended_cpu_model() == 0x37) || // Silvermont
809 (extended_cpu_model() == 0x4D))) {
810 #ifdef COMPILER2
811 if (FLAG_IS_DEFAULT(OptoScheduling)) {
812 OptoScheduling = true;
813 }
814 #endif
815 if (supports_sse4_2()) { // Silvermont
816 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
817 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
818 }
819 }
820 }
821 }
823 // Use count leading zeros count instruction if available.
824 if (supports_lzcnt()) {
825 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
826 UseCountLeadingZerosInstruction = true;
827 }
828 } else if (UseCountLeadingZerosInstruction) {
829 warning("lzcnt instruction is not available on this CPU");
830 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
831 }
833 if (supports_bmi1()) {
834 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
835 UseBMI1Instructions = true;
836 }
837 } else if (UseBMI1Instructions) {
838 warning("BMI1 instructions are not available on this CPU");
839 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
840 }
842 // Use count trailing zeros instruction if available
843 if (supports_bmi1()) {
844 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
845 UseCountTrailingZerosInstruction = UseBMI1Instructions;
846 }
847 } else if (UseCountTrailingZerosInstruction) {
848 warning("tzcnt instruction is not available on this CPU");
849 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
850 }
852 // Use population count instruction if available.
853 if (supports_popcnt()) {
854 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
855 UsePopCountInstruction = true;
856 }
857 } else if (UsePopCountInstruction) {
858 warning("POPCNT instruction is not available on this CPU");
859 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
860 }
862 // Use fast-string operations if available.
863 if (supports_erms()) {
864 if (FLAG_IS_DEFAULT(UseFastStosb)) {
865 UseFastStosb = true;
866 }
867 } else if (UseFastStosb) {
868 warning("fast-string operations are not available on this CPU");
869 FLAG_SET_DEFAULT(UseFastStosb, false);
870 }
872 #ifdef COMPILER2
873 if (FLAG_IS_DEFAULT(AlignVector)) {
874 // Modern processors allow misaligned memory operations for vectors.
875 AlignVector = !UseUnalignedLoadStores;
876 }
877 #endif // COMPILER2
879 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
880 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
882 // set valid Prefetch instruction
883 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
884 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
885 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
886 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
888 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
889 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
890 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
891 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
893 // Allocation prefetch settings
894 intx cache_line_size = prefetch_data_size();
895 if( cache_line_size > AllocatePrefetchStepSize )
896 AllocatePrefetchStepSize = cache_line_size;
898 assert(AllocatePrefetchLines > 0, "invalid value");
899 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
900 AllocatePrefetchLines = 3;
901 assert(AllocateInstancePrefetchLines > 0, "invalid value");
902 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
903 AllocateInstancePrefetchLines = 1;
905 AllocatePrefetchDistance = allocate_prefetch_distance();
906 AllocatePrefetchStyle = allocate_prefetch_style();
908 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
909 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
910 #ifdef _LP64
911 AllocatePrefetchDistance = 384;
912 #else
913 AllocatePrefetchDistance = 320;
914 #endif
915 }
916 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
917 AllocatePrefetchDistance = 192;
918 AllocatePrefetchLines = 4;
919 }
920 #ifdef COMPILER2
921 if (supports_sse4_2()) {
922 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
923 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
924 }
925 }
926 #endif
927 }
928 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
930 #ifdef _LP64
931 // Prefetch settings
932 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
933 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
934 PrefetchFieldsAhead = prefetch_fields_ahead();
935 #endif
937 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
938 (cache_line_size > ContendedPaddingWidth))
939 ContendedPaddingWidth = cache_line_size;
941 #ifndef PRODUCT
942 if (PrintMiscellaneous && Verbose) {
943 tty->print_cr("Logical CPUs per core: %u",
944 logical_processors_per_package());
945 tty->print("UseSSE=%d", (int) UseSSE);
946 if (UseAVX > 0) {
947 tty->print(" UseAVX=%d", (int) UseAVX);
948 }
949 if (UseAES) {
950 tty->print(" UseAES=1");
951 }
952 #ifdef COMPILER2
953 if (MaxVectorSize > 0) {
954 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize);
955 }
956 #endif
957 tty->cr();
958 tty->print("Allocation");
959 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
960 tty->print_cr(": no prefetching");
961 } else {
962 tty->print(" prefetching: ");
963 if (UseSSE == 0 && supports_3dnow_prefetch()) {
964 tty->print("PREFETCHW");
965 } else if (UseSSE >= 1) {
966 if (AllocatePrefetchInstr == 0) {
967 tty->print("PREFETCHNTA");
968 } else if (AllocatePrefetchInstr == 1) {
969 tty->print("PREFETCHT0");
970 } else if (AllocatePrefetchInstr == 2) {
971 tty->print("PREFETCHT2");
972 } else if (AllocatePrefetchInstr == 3) {
973 tty->print("PREFETCHW");
974 }
975 }
976 if (AllocatePrefetchLines > 1) {
977 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
978 } else {
979 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
980 }
981 }
983 if (PrefetchCopyIntervalInBytes > 0) {
984 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
985 }
986 if (PrefetchScanIntervalInBytes > 0) {
987 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
988 }
989 if (PrefetchFieldsAhead > 0) {
990 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
991 }
992 if (ContendedPaddingWidth > 0) {
993 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
994 }
995 }
996 #endif // !PRODUCT
997 }
999 bool VM_Version::use_biased_locking() {
1000 #if INCLUDE_RTM_OPT
1001 // RTM locking is most useful when there is high lock contention and
1002 // low data contention. With high lock contention the lock is usually
1003 // inflated and biased locking is not suitable for that case.
1004 // RTM locking code requires that biased locking is off.
1005 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1006 // because it is used by Thread::allocate() which is called before
1007 // VM_Version::initialize().
1008 if (UseRTMLocking && UseBiasedLocking) {
1009 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1010 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1011 } else {
1012 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1013 UseBiasedLocking = false;
1014 }
1015 }
1016 #endif
1017 return UseBiasedLocking;
1018 }
1020 void VM_Version::initialize() {
1021 ResourceMark rm;
1022 // Making this stub must be FIRST use of assembler
1024 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1025 if (stub_blob == NULL) {
1026 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1027 }
1028 CodeBuffer c(stub_blob);
1029 VM_Version_StubGenerator g(&c);
1030 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1031 g.generate_get_cpu_info());
1033 get_processor_features();
1034 }
