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src/cpu/x86/vm/assembler_x86.cpp@ae065c367d93
src/cpu/x86/vm/assembler_x86.cpp
Tue, 02 Nov 2010 09:00:37 -0700
- author
- kvn
- date
- Tue, 02 Nov 2010 09:00:37 -0700
- changeset 2269
- ae065c367d93
- parent 2201
- d55217dc206f
- child 2275
- 2fe998383789
- permissions
- -rw-r--r--
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
Summary: Use hardware DIV instruction for long division by constant when it is faster than code with multiply.
Reviewed-by: never
1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "incls/_precompiled.incl"
26 #include "incls/_assembler_x86.cpp.incl"
28 // Implementation of AddressLiteral
30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
31 _is_lval = false;
32 _target = target;
33 switch (rtype) {
34 case relocInfo::oop_type:
35 // Oops are a special case. Normally they would be their own section
36 // but in cases like icBuffer they are literals in the code stream that
37 // we don't have a section for. We use none so that we get a literal address
38 // which is always patchable.
39 break;
40 case relocInfo::external_word_type:
41 _rspec = external_word_Relocation::spec(target);
42 break;
43 case relocInfo::internal_word_type:
44 _rspec = internal_word_Relocation::spec(target);
45 break;
46 case relocInfo::opt_virtual_call_type:
47 _rspec = opt_virtual_call_Relocation::spec();
48 break;
49 case relocInfo::static_call_type:
50 _rspec = static_call_Relocation::spec();
51 break;
52 case relocInfo::runtime_call_type:
53 _rspec = runtime_call_Relocation::spec();
54 break;
55 case relocInfo::poll_type:
56 case relocInfo::poll_return_type:
57 _rspec = Relocation::spec_simple(rtype);
58 break;
59 case relocInfo::none:
60 break;
61 default:
62 ShouldNotReachHere();
63 break;
64 }
65 }
67 // Implementation of Address
69 #ifdef _LP64
71 Address Address::make_array(ArrayAddress adr) {
72 // Not implementable on 64bit machines
73 // Should have been handled higher up the call chain.
74 ShouldNotReachHere();
75 return Address();
76 }
78 // exceedingly dangerous constructor
79 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
80 _base = noreg;
81 _index = noreg;
82 _scale = no_scale;
83 _disp = disp;
84 switch (rtype) {
85 case relocInfo::external_word_type:
86 _rspec = external_word_Relocation::spec(loc);
87 break;
88 case relocInfo::internal_word_type:
89 _rspec = internal_word_Relocation::spec(loc);
90 break;
91 case relocInfo::runtime_call_type:
92 // HMM
93 _rspec = runtime_call_Relocation::spec();
94 break;
95 case relocInfo::poll_type:
96 case relocInfo::poll_return_type:
97 _rspec = Relocation::spec_simple(rtype);
98 break;
99 case relocInfo::none:
100 break;
101 default:
102 ShouldNotReachHere();
103 }
104 }
105 #else // LP64
107 Address Address::make_array(ArrayAddress adr) {
108 AddressLiteral base = adr.base();
109 Address index = adr.index();
110 assert(index._disp == 0, "must not have disp"); // maybe it can?
111 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
112 array._rspec = base._rspec;
113 return array;
114 }
116 // exceedingly dangerous constructor
117 Address::Address(address loc, RelocationHolder spec) {
118 _base = noreg;
119 _index = noreg;
120 _scale = no_scale;
121 _disp = (intptr_t) loc;
122 _rspec = spec;
123 }
125 #endif // _LP64
129 // Convert the raw encoding form into the form expected by the constructor for
130 // Address. An index of 4 (rsp) corresponds to having no index, so convert
131 // that to noreg for the Address constructor.
132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
133 RelocationHolder rspec;
134 if (disp_is_oop) {
135 rspec = Relocation::spec_simple(relocInfo::oop_type);
136 }
137 bool valid_index = index != rsp->encoding();
138 if (valid_index) {
139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
140 madr._rspec = rspec;
141 return madr;
142 } else {
143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
144 madr._rspec = rspec;
145 return madr;
146 }
147 }
149 // Implementation of Assembler
151 int AbstractAssembler::code_fill_byte() {
152 return (u_char)'\xF4'; // hlt
153 }
155 // make this go away someday
156 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
157 if (rtype == relocInfo::none)
158 emit_long(data);
159 else emit_data(data, Relocation::spec_simple(rtype), format);
160 }
162 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
163 assert(imm_operand == 0, "default format must be immediate in this file");
164 assert(inst_mark() != NULL, "must be inside InstructionMark");
165 if (rspec.type() != relocInfo::none) {
166 #ifdef ASSERT
167 check_relocation(rspec, format);
168 #endif
169 // Do not use AbstractAssembler::relocate, which is not intended for
170 // embedded words. Instead, relocate to the enclosing instruction.
172 // hack. call32 is too wide for mask so use disp32
173 if (format == call32_operand)
174 code_section()->relocate(inst_mark(), rspec, disp32_operand);
175 else
176 code_section()->relocate(inst_mark(), rspec, format);
177 }
178 emit_long(data);
179 }
181 static int encode(Register r) {
182 int enc = r->encoding();
183 if (enc >= 8) {
184 enc -= 8;
185 }
186 return enc;
187 }
189 static int encode(XMMRegister r) {
190 int enc = r->encoding();
191 if (enc >= 8) {
192 enc -= 8;
193 }
194 return enc;
195 }
197 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
198 assert(dst->has_byte_register(), "must have byte register");
199 assert(isByte(op1) && isByte(op2), "wrong opcode");
200 assert(isByte(imm8), "not a byte");
201 assert((op1 & 0x01) == 0, "should be 8bit operation");
202 emit_byte(op1);
203 emit_byte(op2 | encode(dst));
204 emit_byte(imm8);
205 }
208 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
209 assert(isByte(op1) && isByte(op2), "wrong opcode");
210 assert((op1 & 0x01) == 1, "should be 32bit operation");
211 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
212 if (is8bit(imm32)) {
213 emit_byte(op1 | 0x02); // set sign bit
214 emit_byte(op2 | encode(dst));
215 emit_byte(imm32 & 0xFF);
216 } else {
217 emit_byte(op1);
218 emit_byte(op2 | encode(dst));
219 emit_long(imm32);
220 }
221 }
223 // immediate-to-memory forms
224 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
225 assert((op1 & 0x01) == 1, "should be 32bit operation");
226 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
227 if (is8bit(imm32)) {
228 emit_byte(op1 | 0x02); // set sign bit
229 emit_operand(rm, adr, 1);
230 emit_byte(imm32 & 0xFF);
231 } else {
232 emit_byte(op1);
233 emit_operand(rm, adr, 4);
234 emit_long(imm32);
235 }
236 }
238 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
239 LP64_ONLY(ShouldNotReachHere());
240 assert(isByte(op1) && isByte(op2), "wrong opcode");
241 assert((op1 & 0x01) == 1, "should be 32bit operation");
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
243 InstructionMark im(this);
244 emit_byte(op1);
245 emit_byte(op2 | encode(dst));
246 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
247 }
250 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
251 assert(isByte(op1) && isByte(op2), "wrong opcode");
252 emit_byte(op1);
253 emit_byte(op2 | encode(dst) << 3 | encode(src));
254 }
257 void Assembler::emit_operand(Register reg, Register base, Register index,
258 Address::ScaleFactor scale, int disp,
259 RelocationHolder const& rspec,
260 int rip_relative_correction) {
261 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
263 // Encode the registers as needed in the fields they are used in
265 int regenc = encode(reg) << 3;
266 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
267 int baseenc = base->is_valid() ? encode(base) : 0;
269 if (base->is_valid()) {
270 if (index->is_valid()) {
271 assert(scale != Address::no_scale, "inconsistent address");
272 // [base + index*scale + disp]
273 if (disp == 0 && rtype == relocInfo::none &&
274 base != rbp LP64_ONLY(&& base != r13)) {
275 // [base + index*scale]
276 // [00 reg 100][ss index base]
277 assert(index != rsp, "illegal addressing mode");
278 emit_byte(0x04 | regenc);
279 emit_byte(scale << 6 | indexenc | baseenc);
280 } else if (is8bit(disp) && rtype == relocInfo::none) {
281 // [base + index*scale + imm8]
282 // [01 reg 100][ss index base] imm8
283 assert(index != rsp, "illegal addressing mode");
284 emit_byte(0x44 | regenc);
285 emit_byte(scale << 6 | indexenc | baseenc);
286 emit_byte(disp & 0xFF);
287 } else {
288 // [base + index*scale + disp32]
289 // [10 reg 100][ss index base] disp32
290 assert(index != rsp, "illegal addressing mode");
291 emit_byte(0x84 | regenc);
292 emit_byte(scale << 6 | indexenc | baseenc);
293 emit_data(disp, rspec, disp32_operand);
294 }
295 } else if (base == rsp LP64_ONLY(|| base == r12)) {
296 // [rsp + disp]
297 if (disp == 0 && rtype == relocInfo::none) {
298 // [rsp]
299 // [00 reg 100][00 100 100]
300 emit_byte(0x04 | regenc);
301 emit_byte(0x24);
302 } else if (is8bit(disp) && rtype == relocInfo::none) {
303 // [rsp + imm8]
304 // [01 reg 100][00 100 100] disp8
305 emit_byte(0x44 | regenc);
306 emit_byte(0x24);
307 emit_byte(disp & 0xFF);
308 } else {
309 // [rsp + imm32]
310 // [10 reg 100][00 100 100] disp32
311 emit_byte(0x84 | regenc);
312 emit_byte(0x24);
313 emit_data(disp, rspec, disp32_operand);
314 }
315 } else {
316 // [base + disp]
317 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
318 if (disp == 0 && rtype == relocInfo::none &&
319 base != rbp LP64_ONLY(&& base != r13)) {
320 // [base]
321 // [00 reg base]
322 emit_byte(0x00 | regenc | baseenc);
323 } else if (is8bit(disp) && rtype == relocInfo::none) {
324 // [base + disp8]
325 // [01 reg base] disp8
326 emit_byte(0x40 | regenc | baseenc);
327 emit_byte(disp & 0xFF);
328 } else {
329 // [base + disp32]
330 // [10 reg base] disp32
331 emit_byte(0x80 | regenc | baseenc);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 }
335 } else {
336 if (index->is_valid()) {
337 assert(scale != Address::no_scale, "inconsistent address");
338 // [index*scale + disp]
339 // [00 reg 100][ss index 101] disp32
340 assert(index != rsp, "illegal addressing mode");
341 emit_byte(0x04 | regenc);
342 emit_byte(scale << 6 | indexenc | 0x05);
343 emit_data(disp, rspec, disp32_operand);
344 } else if (rtype != relocInfo::none ) {
345 // [disp] (64bit) RIP-RELATIVE (32bit) abs
346 // [00 000 101] disp32
348 emit_byte(0x05 | regenc);
349 // Note that the RIP-rel. correction applies to the generated
350 // disp field, but _not_ to the target address in the rspec.
352 // disp was created by converting the target address minus the pc
353 // at the start of the instruction. That needs more correction here.
354 // intptr_t disp = target - next_ip;
355 assert(inst_mark() != NULL, "must be inside InstructionMark");
356 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
357 int64_t adjusted = disp;
358 // Do rip-rel adjustment for 64bit
359 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
360 assert(is_simm32(adjusted),
361 "must be 32bit offset (RIP relative address)");
362 emit_data((int32_t) adjusted, rspec, disp32_operand);
364 } else {
365 // 32bit never did this, did everything as the rip-rel/disp code above
366 // [disp] ABSOLUTE
367 // [00 reg 100][00 100 101] disp32
368 emit_byte(0x04 | regenc);
369 emit_byte(0x25);
370 emit_data(disp, rspec, disp32_operand);
371 }
372 }
373 }
375 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
376 Address::ScaleFactor scale, int disp,
377 RelocationHolder const& rspec) {
378 emit_operand((Register)reg, base, index, scale, disp, rspec);
379 }
381 // Secret local extension to Assembler::WhichOperand:
382 #define end_pc_operand (_WhichOperand_limit)
384 address Assembler::locate_operand(address inst, WhichOperand which) {
385 // Decode the given instruction, and return the address of
386 // an embedded 32-bit operand word.
388 // If "which" is disp32_operand, selects the displacement portion
389 // of an effective address specifier.
390 // If "which" is imm64_operand, selects the trailing immediate constant.
391 // If "which" is call32_operand, selects the displacement of a call or jump.
392 // Caller is responsible for ensuring that there is such an operand,
393 // and that it is 32/64 bits wide.
395 // If "which" is end_pc_operand, find the end of the instruction.
397 address ip = inst;
398 bool is_64bit = false;
400 debug_only(bool has_disp32 = false);
401 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
403 again_after_prefix:
404 switch (0xFF & *ip++) {
406 // These convenience macros generate groups of "case" labels for the switch.
407 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
408 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
409 case (x)+4: case (x)+5: case (x)+6: case (x)+7
410 #define REP16(x) REP8((x)+0): \
411 case REP8((x)+8)
413 case CS_segment:
414 case SS_segment:
415 case DS_segment:
416 case ES_segment:
417 case FS_segment:
418 case GS_segment:
419 // Seems dubious
420 LP64_ONLY(assert(false, "shouldn't have that prefix"));
421 assert(ip == inst+1, "only one prefix allowed");
422 goto again_after_prefix;
424 case 0x67:
425 case REX:
426 case REX_B:
427 case REX_X:
428 case REX_XB:
429 case REX_R:
430 case REX_RB:
431 case REX_RX:
432 case REX_RXB:
433 NOT_LP64(assert(false, "64bit prefixes"));
434 goto again_after_prefix;
436 case REX_W:
437 case REX_WB:
438 case REX_WX:
439 case REX_WXB:
440 case REX_WR:
441 case REX_WRB:
442 case REX_WRX:
443 case REX_WRXB:
444 NOT_LP64(assert(false, "64bit prefixes"));
445 is_64bit = true;
446 goto again_after_prefix;
448 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
449 case 0x88: // movb a, r
450 case 0x89: // movl a, r
451 case 0x8A: // movb r, a
452 case 0x8B: // movl r, a
453 case 0x8F: // popl a
454 debug_only(has_disp32 = true);
455 break;
457 case 0x68: // pushq #32
458 if (which == end_pc_operand) {
459 return ip + 4;
460 }
461 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
462 return ip; // not produced by emit_operand
464 case 0x66: // movw ... (size prefix)
465 again_after_size_prefix2:
466 switch (0xFF & *ip++) {
467 case REX:
468 case REX_B:
469 case REX_X:
470 case REX_XB:
471 case REX_R:
472 case REX_RB:
473 case REX_RX:
474 case REX_RXB:
475 case REX_W:
476 case REX_WB:
477 case REX_WX:
478 case REX_WXB:
479 case REX_WR:
480 case REX_WRB:
481 case REX_WRX:
482 case REX_WRXB:
483 NOT_LP64(assert(false, "64bit prefix found"));
484 goto again_after_size_prefix2;
485 case 0x8B: // movw r, a
486 case 0x89: // movw a, r
487 debug_only(has_disp32 = true);
488 break;
489 case 0xC7: // movw a, #16
490 debug_only(has_disp32 = true);
491 tail_size = 2; // the imm16
492 break;
493 case 0x0F: // several SSE/SSE2 variants
494 ip--; // reparse the 0x0F
495 goto again_after_prefix;
496 default:
497 ShouldNotReachHere();
498 }
499 break;
501 case REP8(0xB8): // movl/q r, #32/#64(oop?)
502 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
503 // these asserts are somewhat nonsensical
504 #ifndef _LP64
505 assert(which == imm_operand || which == disp32_operand, "");
506 #else
507 assert((which == call32_operand || which == imm_operand) && is_64bit ||
508 which == narrow_oop_operand && !is_64bit, "");
509 #endif // _LP64
510 return ip;
512 case 0x69: // imul r, a, #32
513 case 0xC7: // movl a, #32(oop?)
514 tail_size = 4;
515 debug_only(has_disp32 = true); // has both kinds of operands!
516 break;
518 case 0x0F: // movx..., etc.
519 switch (0xFF & *ip++) {
520 case 0x12: // movlps
521 case 0x28: // movaps
522 case 0x2E: // ucomiss
523 case 0x2F: // comiss
524 case 0x54: // andps
525 case 0x55: // andnps
526 case 0x56: // orps
527 case 0x57: // xorps
528 case 0x6E: // movd
529 case 0x7E: // movd
530 case 0xAE: // ldmxcsr a
531 // 64bit side says it these have both operands but that doesn't
532 // appear to be true
533 debug_only(has_disp32 = true);
534 break;
536 case 0xAD: // shrd r, a, %cl
537 case 0xAF: // imul r, a
538 case 0xBE: // movsbl r, a (movsxb)
539 case 0xBF: // movswl r, a (movsxw)
540 case 0xB6: // movzbl r, a (movzxb)
541 case 0xB7: // movzwl r, a (movzxw)
542 case REP16(0x40): // cmovl cc, r, a
543 case 0xB0: // cmpxchgb
544 case 0xB1: // cmpxchg
545 case 0xC1: // xaddl
546 case 0xC7: // cmpxchg8
547 case REP16(0x90): // setcc a
548 debug_only(has_disp32 = true);
549 // fall out of the switch to decode the address
550 break;
552 case 0xAC: // shrd r, a, #8
553 debug_only(has_disp32 = true);
554 tail_size = 1; // the imm8
555 break;
557 case REP16(0x80): // jcc rdisp32
558 if (which == end_pc_operand) return ip + 4;
559 assert(which == call32_operand, "jcc has no disp32 or imm");
560 return ip;
561 default:
562 ShouldNotReachHere();
563 }
564 break;
566 case 0x81: // addl a, #32; addl r, #32
567 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
568 // on 32bit in the case of cmpl, the imm might be an oop
569 tail_size = 4;
570 debug_only(has_disp32 = true); // has both kinds of operands!
571 break;
573 case 0x83: // addl a, #8; addl r, #8
574 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
575 debug_only(has_disp32 = true); // has both kinds of operands!
576 tail_size = 1;
577 break;
579 case 0x9B:
580 switch (0xFF & *ip++) {
581 case 0xD9: // fnstcw a
582 debug_only(has_disp32 = true);
583 break;
584 default:
585 ShouldNotReachHere();
586 }
587 break;
589 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
590 case REP4(0x10): // adc...
591 case REP4(0x20): // and...
592 case REP4(0x30): // xor...
593 case REP4(0x08): // or...
594 case REP4(0x18): // sbb...
595 case REP4(0x28): // sub...
596 case 0xF7: // mull a
597 case 0x8D: // lea r, a
598 case 0x87: // xchg r, a
599 case REP4(0x38): // cmp...
600 case 0x85: // test r, a
601 debug_only(has_disp32 = true); // has both kinds of operands!
602 break;
604 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
605 case 0xC6: // movb a, #8
606 case 0x80: // cmpb a, #8
607 case 0x6B: // imul r, a, #8
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 tail_size = 1; // the imm8
610 break;
612 case 0xE8: // call rdisp32
613 case 0xE9: // jmp rdisp32
614 if (which == end_pc_operand) return ip + 4;
615 assert(which == call32_operand, "call has no disp32 or imm");
616 return ip;
618 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
619 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
620 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
621 case 0xDD: // fld_d a; fst_d a; fstp_d a
622 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
623 case 0xDF: // fild_d a; fistp_d a
624 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
625 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
626 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
627 debug_only(has_disp32 = true);
628 break;
630 case 0xF0: // Lock
631 assert(os::is_MP(), "only on MP");
632 goto again_after_prefix;
634 case 0xF3: // For SSE
635 case 0xF2: // For SSE2
636 switch (0xFF & *ip++) {
637 case REX:
638 case REX_B:
639 case REX_X:
640 case REX_XB:
641 case REX_R:
642 case REX_RB:
643 case REX_RX:
644 case REX_RXB:
645 case REX_W:
646 case REX_WB:
647 case REX_WX:
648 case REX_WXB:
649 case REX_WR:
650 case REX_WRB:
651 case REX_WRX:
652 case REX_WRXB:
653 NOT_LP64(assert(false, "found 64bit prefix"));
654 ip++;
655 default:
656 ip++;
657 }
658 debug_only(has_disp32 = true); // has both kinds of operands!
659 break;
661 default:
662 ShouldNotReachHere();
664 #undef REP8
665 #undef REP16
666 }
668 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
669 #ifdef _LP64
670 assert(which != imm_operand, "instruction is not a movq reg, imm64");
671 #else
672 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
673 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
674 #endif // LP64
675 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
677 // parse the output of emit_operand
678 int op2 = 0xFF & *ip++;
679 int base = op2 & 0x07;
680 int op3 = -1;
681 const int b100 = 4;
682 const int b101 = 5;
683 if (base == b100 && (op2 >> 6) != 3) {
684 op3 = 0xFF & *ip++;
685 base = op3 & 0x07; // refetch the base
686 }
687 // now ip points at the disp (if any)
689 switch (op2 >> 6) {
690 case 0:
691 // [00 reg 100][ss index base]
692 // [00 reg 100][00 100 esp]
693 // [00 reg base]
694 // [00 reg 100][ss index 101][disp32]
695 // [00 reg 101] [disp32]
697 if (base == b101) {
698 if (which == disp32_operand)
699 return ip; // caller wants the disp32
700 ip += 4; // skip the disp32
701 }
702 break;
704 case 1:
705 // [01 reg 100][ss index base][disp8]
706 // [01 reg 100][00 100 esp][disp8]
707 // [01 reg base] [disp8]
708 ip += 1; // skip the disp8
709 break;
711 case 2:
712 // [10 reg 100][ss index base][disp32]
713 // [10 reg 100][00 100 esp][disp32]
714 // [10 reg base] [disp32]
715 if (which == disp32_operand)
716 return ip; // caller wants the disp32
717 ip += 4; // skip the disp32
718 break;
720 case 3:
721 // [11 reg base] (not a memory addressing mode)
722 break;
723 }
725 if (which == end_pc_operand) {
726 return ip + tail_size;
727 }
729 #ifdef _LP64
730 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
731 #else
732 assert(which == imm_operand, "instruction has only an imm field");
733 #endif // LP64
734 return ip;
735 }
737 address Assembler::locate_next_instruction(address inst) {
738 // Secretly share code with locate_operand:
739 return locate_operand(inst, end_pc_operand);
740 }
743 #ifdef ASSERT
744 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
745 address inst = inst_mark();
746 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
747 address opnd;
749 Relocation* r = rspec.reloc();
750 if (r->type() == relocInfo::none) {
751 return;
752 } else if (r->is_call() || format == call32_operand) {
753 // assert(format == imm32_operand, "cannot specify a nonzero format");
754 opnd = locate_operand(inst, call32_operand);
755 } else if (r->is_data()) {
756 assert(format == imm_operand || format == disp32_operand
757 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
758 opnd = locate_operand(inst, (WhichOperand)format);
759 } else {
760 assert(format == imm_operand, "cannot specify a format");
761 return;
762 }
763 assert(opnd == pc(), "must put operand where relocs can find it");
764 }
765 #endif // ASSERT
767 void Assembler::emit_operand32(Register reg, Address adr) {
768 assert(reg->encoding() < 8, "no extended registers");
769 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
770 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
771 adr._rspec);
772 }
774 void Assembler::emit_operand(Register reg, Address adr,
775 int rip_relative_correction) {
776 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
777 adr._rspec,
778 rip_relative_correction);
779 }
781 void Assembler::emit_operand(XMMRegister reg, Address adr) {
782 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
783 adr._rspec);
784 }
786 // MMX operations
787 void Assembler::emit_operand(MMXRegister reg, Address adr) {
788 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
789 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
790 }
792 // work around gcc (3.2.1-7a) bug
793 void Assembler::emit_operand(Address adr, MMXRegister reg) {
794 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
795 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
796 }
799 void Assembler::emit_farith(int b1, int b2, int i) {
800 assert(isByte(b1) && isByte(b2), "wrong opcode");
801 assert(0 <= i && i < 8, "illegal stack offset");
802 emit_byte(b1);
803 emit_byte(b2 + i);
804 }
807 // Now the Assembler instruction (identical for 32/64 bits)
809 void Assembler::adcl(Register dst, int32_t imm32) {
810 prefix(dst);
811 emit_arith(0x81, 0xD0, dst, imm32);
812 }
814 void Assembler::adcl(Register dst, Address src) {
815 InstructionMark im(this);
816 prefix(src, dst);
817 emit_byte(0x13);
818 emit_operand(dst, src);
819 }
821 void Assembler::adcl(Register dst, Register src) {
822 (void) prefix_and_encode(dst->encoding(), src->encoding());
823 emit_arith(0x13, 0xC0, dst, src);
824 }
826 void Assembler::addl(Address dst, int32_t imm32) {
827 InstructionMark im(this);
828 prefix(dst);
829 emit_arith_operand(0x81, rax, dst, imm32);
830 }
832 void Assembler::addl(Address dst, Register src) {
833 InstructionMark im(this);
834 prefix(dst, src);
835 emit_byte(0x01);
836 emit_operand(src, dst);
837 }
839 void Assembler::addl(Register dst, int32_t imm32) {
840 prefix(dst);
841 emit_arith(0x81, 0xC0, dst, imm32);
842 }
844 void Assembler::addl(Register dst, Address src) {
845 InstructionMark im(this);
846 prefix(src, dst);
847 emit_byte(0x03);
848 emit_operand(dst, src);
849 }
851 void Assembler::addl(Register dst, Register src) {
852 (void) prefix_and_encode(dst->encoding(), src->encoding());
853 emit_arith(0x03, 0xC0, dst, src);
854 }
856 void Assembler::addr_nop_4() {
857 // 4 bytes: NOP DWORD PTR [EAX+0]
858 emit_byte(0x0F);
859 emit_byte(0x1F);
860 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
861 emit_byte(0); // 8-bits offset (1 byte)
862 }
864 void Assembler::addr_nop_5() {
865 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
866 emit_byte(0x0F);
867 emit_byte(0x1F);
868 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
869 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
870 emit_byte(0); // 8-bits offset (1 byte)
871 }
873 void Assembler::addr_nop_7() {
874 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
875 emit_byte(0x0F);
876 emit_byte(0x1F);
877 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
878 emit_long(0); // 32-bits offset (4 bytes)
879 }
881 void Assembler::addr_nop_8() {
882 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
883 emit_byte(0x0F);
884 emit_byte(0x1F);
885 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
886 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
887 emit_long(0); // 32-bits offset (4 bytes)
888 }
890 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
891 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
892 emit_byte(0xF2);
893 int encode = prefix_and_encode(dst->encoding(), src->encoding());
894 emit_byte(0x0F);
895 emit_byte(0x58);
896 emit_byte(0xC0 | encode);
897 }
899 void Assembler::addsd(XMMRegister dst, Address src) {
900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
901 InstructionMark im(this);
902 emit_byte(0xF2);
903 prefix(src, dst);
904 emit_byte(0x0F);
905 emit_byte(0x58);
906 emit_operand(dst, src);
907 }
909 void Assembler::addss(XMMRegister dst, XMMRegister src) {
910 NOT_LP64(assert(VM_Version::supports_sse(), ""));
911 emit_byte(0xF3);
912 int encode = prefix_and_encode(dst->encoding(), src->encoding());
913 emit_byte(0x0F);
914 emit_byte(0x58);
915 emit_byte(0xC0 | encode);
916 }
918 void Assembler::addss(XMMRegister dst, Address src) {
919 NOT_LP64(assert(VM_Version::supports_sse(), ""));
920 InstructionMark im(this);
921 emit_byte(0xF3);
922 prefix(src, dst);
923 emit_byte(0x0F);
924 emit_byte(0x58);
925 emit_operand(dst, src);
926 }
928 void Assembler::andl(Register dst, int32_t imm32) {
929 prefix(dst);
930 emit_arith(0x81, 0xE0, dst, imm32);
931 }
933 void Assembler::andl(Register dst, Address src) {
934 InstructionMark im(this);
935 prefix(src, dst);
936 emit_byte(0x23);
937 emit_operand(dst, src);
938 }
940 void Assembler::andl(Register dst, Register src) {
941 (void) prefix_and_encode(dst->encoding(), src->encoding());
942 emit_arith(0x23, 0xC0, dst, src);
943 }
945 void Assembler::andpd(XMMRegister dst, Address src) {
946 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
947 InstructionMark im(this);
948 emit_byte(0x66);
949 prefix(src, dst);
950 emit_byte(0x0F);
951 emit_byte(0x54);
952 emit_operand(dst, src);
953 }
955 void Assembler::bsfl(Register dst, Register src) {
956 int encode = prefix_and_encode(dst->encoding(), src->encoding());
957 emit_byte(0x0F);
958 emit_byte(0xBC);
959 emit_byte(0xC0 | encode);
960 }
962 void Assembler::bsrl(Register dst, Register src) {
963 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
964 int encode = prefix_and_encode(dst->encoding(), src->encoding());
965 emit_byte(0x0F);
966 emit_byte(0xBD);
967 emit_byte(0xC0 | encode);
968 }
970 void Assembler::bswapl(Register reg) { // bswap
971 int encode = prefix_and_encode(reg->encoding());
972 emit_byte(0x0F);
973 emit_byte(0xC8 | encode);
974 }
976 void Assembler::call(Label& L, relocInfo::relocType rtype) {
977 // suspect disp32 is always good
978 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
980 if (L.is_bound()) {
981 const int long_size = 5;
982 int offs = (int)( target(L) - pc() );
983 assert(offs <= 0, "assembler error");
984 InstructionMark im(this);
985 // 1110 1000 #32-bit disp
986 emit_byte(0xE8);
987 emit_data(offs - long_size, rtype, operand);
988 } else {
989 InstructionMark im(this);
990 // 1110 1000 #32-bit disp
991 L.add_patch_at(code(), locator());
993 emit_byte(0xE8);
994 emit_data(int(0), rtype, operand);
995 }
996 }
998 void Assembler::call(Register dst) {
999 // This was originally using a 32bit register encoding
1000 // and surely we want 64bit!
1001 // this is a 32bit encoding but in 64bit mode the default
1002 // operand size is 64bit so there is no need for the
1003 // wide prefix. So prefix only happens if we use the
1004 // new registers. Much like push/pop.
1005 int x = offset();
1006 // this may be true but dbx disassembles it as if it
1007 // were 32bits...
1008 // int encode = prefix_and_encode(dst->encoding());
1009 // if (offset() != x) assert(dst->encoding() >= 8, "what?");
1010 int encode = prefixq_and_encode(dst->encoding());
1012 emit_byte(0xFF);
1013 emit_byte(0xD0 | encode);
1014 }
1017 void Assembler::call(Address adr) {
1018 InstructionMark im(this);
1019 prefix(adr);
1020 emit_byte(0xFF);
1021 emit_operand(rdx, adr);
1022 }
1024 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1025 assert(entry != NULL, "call most probably wrong");
1026 InstructionMark im(this);
1027 emit_byte(0xE8);
1028 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
1029 assert(is_simm32(disp), "must be 32bit offset (call2)");
1030 // Technically, should use call32_operand, but this format is
1031 // implied by the fact that we're emitting a call instruction.
1033 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1034 emit_data((int) disp, rspec, operand);
1035 }
1037 void Assembler::cdql() {
1038 emit_byte(0x99);
1039 }
1041 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1042 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1043 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1044 emit_byte(0x0F);
1045 emit_byte(0x40 | cc);
1046 emit_byte(0xC0 | encode);
1047 }
1050 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1051 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1052 prefix(src, dst);
1053 emit_byte(0x0F);
1054 emit_byte(0x40 | cc);
1055 emit_operand(dst, src);
1056 }
1058 void Assembler::cmpb(Address dst, int imm8) {
1059 InstructionMark im(this);
1060 prefix(dst);
1061 emit_byte(0x80);
1062 emit_operand(rdi, dst, 1);
1063 emit_byte(imm8);
1064 }
1066 void Assembler::cmpl(Address dst, int32_t imm32) {
1067 InstructionMark im(this);
1068 prefix(dst);
1069 emit_byte(0x81);
1070 emit_operand(rdi, dst, 4);
1071 emit_long(imm32);
1072 }
1074 void Assembler::cmpl(Register dst, int32_t imm32) {
1075 prefix(dst);
1076 emit_arith(0x81, 0xF8, dst, imm32);
1077 }
1079 void Assembler::cmpl(Register dst, Register src) {
1080 (void) prefix_and_encode(dst->encoding(), src->encoding());
1081 emit_arith(0x3B, 0xC0, dst, src);
1082 }
1085 void Assembler::cmpl(Register dst, Address src) {
1086 InstructionMark im(this);
1087 prefix(src, dst);
1088 emit_byte(0x3B);
1089 emit_operand(dst, src);
1090 }
1092 void Assembler::cmpw(Address dst, int imm16) {
1093 InstructionMark im(this);
1094 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1095 emit_byte(0x66);
1096 emit_byte(0x81);
1097 emit_operand(rdi, dst, 2);
1098 emit_word(imm16);
1099 }
1101 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1102 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1103 // The ZF is set if the compared values were equal, and cleared otherwise.
1104 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1105 if (Atomics & 2) {
1106 // caveat: no instructionmark, so this isn't relocatable.
1107 // Emit a synthetic, non-atomic, CAS equivalent.
1108 // Beware. The synthetic form sets all ICCs, not just ZF.
1109 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1110 cmpl(rax, adr);
1111 movl(rax, adr);
1112 if (reg != rax) {
1113 Label L ;
1114 jcc(Assembler::notEqual, L);
1115 movl(adr, reg);
1116 bind(L);
1117 }
1118 } else {
1119 InstructionMark im(this);
1120 prefix(adr, reg);
1121 emit_byte(0x0F);
1122 emit_byte(0xB1);
1123 emit_operand(reg, adr);
1124 }
1125 }
1127 void Assembler::comisd(XMMRegister dst, Address src) {
1128 // NOTE: dbx seems to decode this as comiss even though the
1129 // 0x66 is there. Strangly ucomisd comes out correct
1130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1131 emit_byte(0x66);
1132 comiss(dst, src);
1133 }
1135 void Assembler::comiss(XMMRegister dst, Address src) {
1136 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1138 InstructionMark im(this);
1139 prefix(src, dst);
1140 emit_byte(0x0F);
1141 emit_byte(0x2F);
1142 emit_operand(dst, src);
1143 }
1145 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1146 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1147 emit_byte(0xF3);
1148 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1149 emit_byte(0x0F);
1150 emit_byte(0xE6);
1151 emit_byte(0xC0 | encode);
1152 }
1154 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1155 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1156 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1157 emit_byte(0x0F);
1158 emit_byte(0x5B);
1159 emit_byte(0xC0 | encode);
1160 }
1162 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1164 emit_byte(0xF2);
1165 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1166 emit_byte(0x0F);
1167 emit_byte(0x5A);
1168 emit_byte(0xC0 | encode);
1169 }
1171 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1172 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1173 emit_byte(0xF2);
1174 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1175 emit_byte(0x0F);
1176 emit_byte(0x2A);
1177 emit_byte(0xC0 | encode);
1178 }
1180 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1181 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1182 emit_byte(0xF3);
1183 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1184 emit_byte(0x0F);
1185 emit_byte(0x2A);
1186 emit_byte(0xC0 | encode);
1187 }
1189 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1190 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1191 emit_byte(0xF3);
1192 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1193 emit_byte(0x0F);
1194 emit_byte(0x5A);
1195 emit_byte(0xC0 | encode);
1196 }
1198 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1200 emit_byte(0xF2);
1201 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1202 emit_byte(0x0F);
1203 emit_byte(0x2C);
1204 emit_byte(0xC0 | encode);
1205 }
1207 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1208 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1209 emit_byte(0xF3);
1210 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1211 emit_byte(0x0F);
1212 emit_byte(0x2C);
1213 emit_byte(0xC0 | encode);
1214 }
1216 void Assembler::decl(Address dst) {
1217 // Don't use it directly. Use MacroAssembler::decrement() instead.
1218 InstructionMark im(this);
1219 prefix(dst);
1220 emit_byte(0xFF);
1221 emit_operand(rcx, dst);
1222 }
1224 void Assembler::divsd(XMMRegister dst, Address src) {
1225 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1226 InstructionMark im(this);
1227 emit_byte(0xF2);
1228 prefix(src, dst);
1229 emit_byte(0x0F);
1230 emit_byte(0x5E);
1231 emit_operand(dst, src);
1232 }
1234 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1236 emit_byte(0xF2);
1237 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1238 emit_byte(0x0F);
1239 emit_byte(0x5E);
1240 emit_byte(0xC0 | encode);
1241 }
1243 void Assembler::divss(XMMRegister dst, Address src) {
1244 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1245 InstructionMark im(this);
1246 emit_byte(0xF3);
1247 prefix(src, dst);
1248 emit_byte(0x0F);
1249 emit_byte(0x5E);
1250 emit_operand(dst, src);
1251 }
1253 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1254 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1255 emit_byte(0xF3);
1256 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1257 emit_byte(0x0F);
1258 emit_byte(0x5E);
1259 emit_byte(0xC0 | encode);
1260 }
1262 void Assembler::emms() {
1263 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1264 emit_byte(0x0F);
1265 emit_byte(0x77);
1266 }
1268 void Assembler::hlt() {
1269 emit_byte(0xF4);
1270 }
1272 void Assembler::idivl(Register src) {
1273 int encode = prefix_and_encode(src->encoding());
1274 emit_byte(0xF7);
1275 emit_byte(0xF8 | encode);
1276 }
1278 void Assembler::imull(Register dst, Register src) {
1279 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1280 emit_byte(0x0F);
1281 emit_byte(0xAF);
1282 emit_byte(0xC0 | encode);
1283 }
1286 void Assembler::imull(Register dst, Register src, int value) {
1287 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1288 if (is8bit(value)) {
1289 emit_byte(0x6B);
1290 emit_byte(0xC0 | encode);
1291 emit_byte(value & 0xFF);
1292 } else {
1293 emit_byte(0x69);
1294 emit_byte(0xC0 | encode);
1295 emit_long(value);
1296 }
1297 }
1299 void Assembler::incl(Address dst) {
1300 // Don't use it directly. Use MacroAssembler::increment() instead.
1301 InstructionMark im(this);
1302 prefix(dst);
1303 emit_byte(0xFF);
1304 emit_operand(rax, dst);
1305 }
1307 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
1308 InstructionMark im(this);
1309 relocate(rtype);
1310 assert((0 <= cc) && (cc < 16), "illegal cc");
1311 if (L.is_bound()) {
1312 address dst = target(L);
1313 assert(dst != NULL, "jcc most probably wrong");
1315 const int short_size = 2;
1316 const int long_size = 6;
1317 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
1318 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1319 // 0111 tttn #8-bit disp
1320 emit_byte(0x70 | cc);
1321 emit_byte((offs - short_size) & 0xFF);
1322 } else {
1323 // 0000 1111 1000 tttn #32-bit disp
1324 assert(is_simm32(offs - long_size),
1325 "must be 32bit offset (call4)");
1326 emit_byte(0x0F);
1327 emit_byte(0x80 | cc);
1328 emit_long(offs - long_size);
1329 }
1330 } else {
1331 // Note: could eliminate cond. jumps to this jump if condition
1332 // is the same however, seems to be rather unlikely case.
1333 // Note: use jccb() if label to be bound is very close to get
1334 // an 8-bit displacement
1335 L.add_patch_at(code(), locator());
1336 emit_byte(0x0F);
1337 emit_byte(0x80 | cc);
1338 emit_long(0);
1339 }
1340 }
1342 void Assembler::jccb(Condition cc, Label& L) {
1343 if (L.is_bound()) {
1344 const int short_size = 2;
1345 address entry = target(L);
1346 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
1347 "Dispacement too large for a short jmp");
1348 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1349 // 0111 tttn #8-bit disp
1350 emit_byte(0x70 | cc);
1351 emit_byte((offs - short_size) & 0xFF);
1352 } else {
1353 InstructionMark im(this);
1354 L.add_patch_at(code(), locator());
1355 emit_byte(0x70 | cc);
1356 emit_byte(0);
1357 }
1358 }
1360 void Assembler::jmp(Address adr) {
1361 InstructionMark im(this);
1362 prefix(adr);
1363 emit_byte(0xFF);
1364 emit_operand(rsp, adr);
1365 }
1367 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
1368 if (L.is_bound()) {
1369 address entry = target(L);
1370 assert(entry != NULL, "jmp most probably wrong");
1371 InstructionMark im(this);
1372 const int short_size = 2;
1373 const int long_size = 5;
1374 intptr_t offs = entry - _code_pos;
1375 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1376 emit_byte(0xEB);
1377 emit_byte((offs - short_size) & 0xFF);
1378 } else {
1379 emit_byte(0xE9);
1380 emit_long(offs - long_size);
1381 }
1382 } else {
1383 // By default, forward jumps are always 32-bit displacements, since
1384 // we can't yet know where the label will be bound. If you're sure that
1385 // the forward jump will not run beyond 256 bytes, use jmpb to
1386 // force an 8-bit displacement.
1387 InstructionMark im(this);
1388 relocate(rtype);
1389 L.add_patch_at(code(), locator());
1390 emit_byte(0xE9);
1391 emit_long(0);
1392 }
1393 }
1395 void Assembler::jmp(Register entry) {
1396 int encode = prefix_and_encode(entry->encoding());
1397 emit_byte(0xFF);
1398 emit_byte(0xE0 | encode);
1399 }
1401 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1402 InstructionMark im(this);
1403 emit_byte(0xE9);
1404 assert(dest != NULL, "must have a target");
1405 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1406 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1407 emit_data(disp, rspec.reloc(), call32_operand);
1408 }
1410 void Assembler::jmpb(Label& L) {
1411 if (L.is_bound()) {
1412 const int short_size = 2;
1413 address entry = target(L);
1414 assert(is8bit((entry - _code_pos) + short_size),
1415 "Dispacement too large for a short jmp");
1416 assert(entry != NULL, "jmp most probably wrong");
1417 intptr_t offs = entry - _code_pos;
1418 emit_byte(0xEB);
1419 emit_byte((offs - short_size) & 0xFF);
1420 } else {
1421 InstructionMark im(this);
1422 L.add_patch_at(code(), locator());
1423 emit_byte(0xEB);
1424 emit_byte(0);
1425 }
1426 }
1428 void Assembler::ldmxcsr( Address src) {
1429 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1430 InstructionMark im(this);
1431 prefix(src);
1432 emit_byte(0x0F);
1433 emit_byte(0xAE);
1434 emit_operand(as_Register(2), src);
1435 }
1437 void Assembler::leal(Register dst, Address src) {
1438 InstructionMark im(this);
1439 #ifdef _LP64
1440 emit_byte(0x67); // addr32
1441 prefix(src, dst);
1442 #endif // LP64
1443 emit_byte(0x8D);
1444 emit_operand(dst, src);
1445 }
1447 void Assembler::lock() {
1448 if (Atomics & 1) {
1449 // Emit either nothing, a NOP, or a NOP: prefix
1450 emit_byte(0x90) ;
1451 } else {
1452 emit_byte(0xF0);
1453 }
1454 }
1456 void Assembler::lzcntl(Register dst, Register src) {
1457 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1458 emit_byte(0xF3);
1459 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1460 emit_byte(0x0F);
1461 emit_byte(0xBD);
1462 emit_byte(0xC0 | encode);
1463 }
1465 // Emit mfence instruction
1466 void Assembler::mfence() {
1467 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1468 emit_byte( 0x0F );
1469 emit_byte( 0xAE );
1470 emit_byte( 0xF0 );
1471 }
1473 void Assembler::mov(Register dst, Register src) {
1474 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1475 }
1477 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1478 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1479 int dstenc = dst->encoding();
1480 int srcenc = src->encoding();
1481 emit_byte(0x66);
1482 if (dstenc < 8) {
1483 if (srcenc >= 8) {
1484 prefix(REX_B);
1485 srcenc -= 8;
1486 }
1487 } else {
1488 if (srcenc < 8) {
1489 prefix(REX_R);
1490 } else {
1491 prefix(REX_RB);
1492 srcenc -= 8;
1493 }
1494 dstenc -= 8;
1495 }
1496 emit_byte(0x0F);
1497 emit_byte(0x28);
1498 emit_byte(0xC0 | dstenc << 3 | srcenc);
1499 }
1501 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1502 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1503 int dstenc = dst->encoding();
1504 int srcenc = src->encoding();
1505 if (dstenc < 8) {
1506 if (srcenc >= 8) {
1507 prefix(REX_B);
1508 srcenc -= 8;
1509 }
1510 } else {
1511 if (srcenc < 8) {
1512 prefix(REX_R);
1513 } else {
1514 prefix(REX_RB);
1515 srcenc -= 8;
1516 }
1517 dstenc -= 8;
1518 }
1519 emit_byte(0x0F);
1520 emit_byte(0x28);
1521 emit_byte(0xC0 | dstenc << 3 | srcenc);
1522 }
1524 void Assembler::movb(Register dst, Address src) {
1525 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1526 InstructionMark im(this);
1527 prefix(src, dst, true);
1528 emit_byte(0x8A);
1529 emit_operand(dst, src);
1530 }
1533 void Assembler::movb(Address dst, int imm8) {
1534 InstructionMark im(this);
1535 prefix(dst);
1536 emit_byte(0xC6);
1537 emit_operand(rax, dst, 1);
1538 emit_byte(imm8);
1539 }
1542 void Assembler::movb(Address dst, Register src) {
1543 assert(src->has_byte_register(), "must have byte register");
1544 InstructionMark im(this);
1545 prefix(dst, src, true);
1546 emit_byte(0x88);
1547 emit_operand(src, dst);
1548 }
1550 void Assembler::movdl(XMMRegister dst, Register src) {
1551 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1552 emit_byte(0x66);
1553 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1554 emit_byte(0x0F);
1555 emit_byte(0x6E);
1556 emit_byte(0xC0 | encode);
1557 }
1559 void Assembler::movdl(Register dst, XMMRegister src) {
1560 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1561 emit_byte(0x66);
1562 // swap src/dst to get correct prefix
1563 int encode = prefix_and_encode(src->encoding(), dst->encoding());
1564 emit_byte(0x0F);
1565 emit_byte(0x7E);
1566 emit_byte(0xC0 | encode);
1567 }
1569 void Assembler::movdqa(XMMRegister dst, Address src) {
1570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1571 InstructionMark im(this);
1572 emit_byte(0x66);
1573 prefix(src, dst);
1574 emit_byte(0x0F);
1575 emit_byte(0x6F);
1576 emit_operand(dst, src);
1577 }
1579 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1580 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1581 emit_byte(0x66);
1582 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1583 emit_byte(0x0F);
1584 emit_byte(0x6F);
1585 emit_byte(0xC0 | encode);
1586 }
1588 void Assembler::movdqa(Address dst, XMMRegister src) {
1589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1590 InstructionMark im(this);
1591 emit_byte(0x66);
1592 prefix(dst, src);
1593 emit_byte(0x0F);
1594 emit_byte(0x7F);
1595 emit_operand(src, dst);
1596 }
1598 void Assembler::movdqu(XMMRegister dst, Address src) {
1599 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1600 InstructionMark im(this);
1601 emit_byte(0xF3);
1602 prefix(src, dst);
1603 emit_byte(0x0F);
1604 emit_byte(0x6F);
1605 emit_operand(dst, src);
1606 }
1608 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1610 emit_byte(0xF3);
1611 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1612 emit_byte(0x0F);
1613 emit_byte(0x6F);
1614 emit_byte(0xC0 | encode);
1615 }
1617 void Assembler::movdqu(Address dst, XMMRegister src) {
1618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1619 InstructionMark im(this);
1620 emit_byte(0xF3);
1621 prefix(dst, src);
1622 emit_byte(0x0F);
1623 emit_byte(0x7F);
1624 emit_operand(src, dst);
1625 }
1627 // Uses zero extension on 64bit
1629 void Assembler::movl(Register dst, int32_t imm32) {
1630 int encode = prefix_and_encode(dst->encoding());
1631 emit_byte(0xB8 | encode);
1632 emit_long(imm32);
1633 }
1635 void Assembler::movl(Register dst, Register src) {
1636 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1637 emit_byte(0x8B);
1638 emit_byte(0xC0 | encode);
1639 }
1641 void Assembler::movl(Register dst, Address src) {
1642 InstructionMark im(this);
1643 prefix(src, dst);
1644 emit_byte(0x8B);
1645 emit_operand(dst, src);
1646 }
1648 void Assembler::movl(Address dst, int32_t imm32) {
1649 InstructionMark im(this);
1650 prefix(dst);
1651 emit_byte(0xC7);
1652 emit_operand(rax, dst, 4);
1653 emit_long(imm32);
1654 }
1656 void Assembler::movl(Address dst, Register src) {
1657 InstructionMark im(this);
1658 prefix(dst, src);
1659 emit_byte(0x89);
1660 emit_operand(src, dst);
1661 }
1663 // New cpus require to use movsd and movss to avoid partial register stall
1664 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1665 // The selection is done in MacroAssembler::movdbl() and movflt().
1666 void Assembler::movlpd(XMMRegister dst, Address src) {
1667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1668 InstructionMark im(this);
1669 emit_byte(0x66);
1670 prefix(src, dst);
1671 emit_byte(0x0F);
1672 emit_byte(0x12);
1673 emit_operand(dst, src);
1674 }
1676 void Assembler::movq( MMXRegister dst, Address src ) {
1677 assert( VM_Version::supports_mmx(), "" );
1678 emit_byte(0x0F);
1679 emit_byte(0x6F);
1680 emit_operand(dst, src);
1681 }
1683 void Assembler::movq( Address dst, MMXRegister src ) {
1684 assert( VM_Version::supports_mmx(), "" );
1685 emit_byte(0x0F);
1686 emit_byte(0x7F);
1687 // workaround gcc (3.2.1-7a) bug
1688 // In that version of gcc with only an emit_operand(MMX, Address)
1689 // gcc will tail jump and try and reverse the parameters completely
1690 // obliterating dst in the process. By having a version available
1691 // that doesn't need to swap the args at the tail jump the bug is
1692 // avoided.
1693 emit_operand(dst, src);
1694 }
1696 void Assembler::movq(XMMRegister dst, Address src) {
1697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1698 InstructionMark im(this);
1699 emit_byte(0xF3);
1700 prefix(src, dst);
1701 emit_byte(0x0F);
1702 emit_byte(0x7E);
1703 emit_operand(dst, src);
1704 }
1706 void Assembler::movq(Address dst, XMMRegister src) {
1707 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1708 InstructionMark im(this);
1709 emit_byte(0x66);
1710 prefix(dst, src);
1711 emit_byte(0x0F);
1712 emit_byte(0xD6);
1713 emit_operand(src, dst);
1714 }
1716 void Assembler::movsbl(Register dst, Address src) { // movsxb
1717 InstructionMark im(this);
1718 prefix(src, dst);
1719 emit_byte(0x0F);
1720 emit_byte(0xBE);
1721 emit_operand(dst, src);
1722 }
1724 void Assembler::movsbl(Register dst, Register src) { // movsxb
1725 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1726 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1727 emit_byte(0x0F);
1728 emit_byte(0xBE);
1729 emit_byte(0xC0 | encode);
1730 }
1732 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1734 emit_byte(0xF2);
1735 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1736 emit_byte(0x0F);
1737 emit_byte(0x10);
1738 emit_byte(0xC0 | encode);
1739 }
1741 void Assembler::movsd(XMMRegister dst, Address src) {
1742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1743 InstructionMark im(this);
1744 emit_byte(0xF2);
1745 prefix(src, dst);
1746 emit_byte(0x0F);
1747 emit_byte(0x10);
1748 emit_operand(dst, src);
1749 }
1751 void Assembler::movsd(Address dst, XMMRegister src) {
1752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1753 InstructionMark im(this);
1754 emit_byte(0xF2);
1755 prefix(dst, src);
1756 emit_byte(0x0F);
1757 emit_byte(0x11);
1758 emit_operand(src, dst);
1759 }
1761 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1762 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1763 emit_byte(0xF3);
1764 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1765 emit_byte(0x0F);
1766 emit_byte(0x10);
1767 emit_byte(0xC0 | encode);
1768 }
1770 void Assembler::movss(XMMRegister dst, Address src) {
1771 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1772 InstructionMark im(this);
1773 emit_byte(0xF3);
1774 prefix(src, dst);
1775 emit_byte(0x0F);
1776 emit_byte(0x10);
1777 emit_operand(dst, src);
1778 }
1780 void Assembler::movss(Address dst, XMMRegister src) {
1781 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1782 InstructionMark im(this);
1783 emit_byte(0xF3);
1784 prefix(dst, src);
1785 emit_byte(0x0F);
1786 emit_byte(0x11);
1787 emit_operand(src, dst);
1788 }
1790 void Assembler::movswl(Register dst, Address src) { // movsxw
1791 InstructionMark im(this);
1792 prefix(src, dst);
1793 emit_byte(0x0F);
1794 emit_byte(0xBF);
1795 emit_operand(dst, src);
1796 }
1798 void Assembler::movswl(Register dst, Register src) { // movsxw
1799 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1800 emit_byte(0x0F);
1801 emit_byte(0xBF);
1802 emit_byte(0xC0 | encode);
1803 }
1805 void Assembler::movw(Address dst, int imm16) {
1806 InstructionMark im(this);
1808 emit_byte(0x66); // switch to 16-bit mode
1809 prefix(dst);
1810 emit_byte(0xC7);
1811 emit_operand(rax, dst, 2);
1812 emit_word(imm16);
1813 }
1815 void Assembler::movw(Register dst, Address src) {
1816 InstructionMark im(this);
1817 emit_byte(0x66);
1818 prefix(src, dst);
1819 emit_byte(0x8B);
1820 emit_operand(dst, src);
1821 }
1823 void Assembler::movw(Address dst, Register src) {
1824 InstructionMark im(this);
1825 emit_byte(0x66);
1826 prefix(dst, src);
1827 emit_byte(0x89);
1828 emit_operand(src, dst);
1829 }
1831 void Assembler::movzbl(Register dst, Address src) { // movzxb
1832 InstructionMark im(this);
1833 prefix(src, dst);
1834 emit_byte(0x0F);
1835 emit_byte(0xB6);
1836 emit_operand(dst, src);
1837 }
1839 void Assembler::movzbl(Register dst, Register src) { // movzxb
1840 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1841 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1842 emit_byte(0x0F);
1843 emit_byte(0xB6);
1844 emit_byte(0xC0 | encode);
1845 }
1847 void Assembler::movzwl(Register dst, Address src) { // movzxw
1848 InstructionMark im(this);
1849 prefix(src, dst);
1850 emit_byte(0x0F);
1851 emit_byte(0xB7);
1852 emit_operand(dst, src);
1853 }
1855 void Assembler::movzwl(Register dst, Register src) { // movzxw
1856 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1857 emit_byte(0x0F);
1858 emit_byte(0xB7);
1859 emit_byte(0xC0 | encode);
1860 }
1862 void Assembler::mull(Address src) {
1863 InstructionMark im(this);
1864 prefix(src);
1865 emit_byte(0xF7);
1866 emit_operand(rsp, src);
1867 }
1869 void Assembler::mull(Register src) {
1870 int encode = prefix_and_encode(src->encoding());
1871 emit_byte(0xF7);
1872 emit_byte(0xE0 | encode);
1873 }
1875 void Assembler::mulsd(XMMRegister dst, Address src) {
1876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1877 InstructionMark im(this);
1878 emit_byte(0xF2);
1879 prefix(src, dst);
1880 emit_byte(0x0F);
1881 emit_byte(0x59);
1882 emit_operand(dst, src);
1883 }
1885 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1886 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1887 emit_byte(0xF2);
1888 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1889 emit_byte(0x0F);
1890 emit_byte(0x59);
1891 emit_byte(0xC0 | encode);
1892 }
1894 void Assembler::mulss(XMMRegister dst, Address src) {
1895 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1896 InstructionMark im(this);
1897 emit_byte(0xF3);
1898 prefix(src, dst);
1899 emit_byte(0x0F);
1900 emit_byte(0x59);
1901 emit_operand(dst, src);
1902 }
1904 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1905 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1906 emit_byte(0xF3);
1907 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1908 emit_byte(0x0F);
1909 emit_byte(0x59);
1910 emit_byte(0xC0 | encode);
1911 }
1913 void Assembler::negl(Register dst) {
1914 int encode = prefix_and_encode(dst->encoding());
1915 emit_byte(0xF7);
1916 emit_byte(0xD8 | encode);
1917 }
1919 void Assembler::nop(int i) {
1920 #ifdef ASSERT
1921 assert(i > 0, " ");
1922 // The fancy nops aren't currently recognized by debuggers making it a
1923 // pain to disassemble code while debugging. If asserts are on clearly
1924 // speed is not an issue so simply use the single byte traditional nop
1925 // to do alignment.
1927 for (; i > 0 ; i--) emit_byte(0x90);
1928 return;
1930 #endif // ASSERT
1932 if (UseAddressNop && VM_Version::is_intel()) {
1933 //
1934 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1935 // 1: 0x90
1936 // 2: 0x66 0x90
1937 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1938 // 4: 0x0F 0x1F 0x40 0x00
1939 // 5: 0x0F 0x1F 0x44 0x00 0x00
1940 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1941 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1942 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1943 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1944 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1945 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1947 // The rest coding is Intel specific - don't use consecutive address nops
1949 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1950 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1951 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1952 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1954 while(i >= 15) {
1955 // For Intel don't generate consecutive addess nops (mix with regular nops)
1956 i -= 15;
1957 emit_byte(0x66); // size prefix
1958 emit_byte(0x66); // size prefix
1959 emit_byte(0x66); // size prefix
1960 addr_nop_8();
1961 emit_byte(0x66); // size prefix
1962 emit_byte(0x66); // size prefix
1963 emit_byte(0x66); // size prefix
1964 emit_byte(0x90); // nop
1965 }
1966 switch (i) {
1967 case 14:
1968 emit_byte(0x66); // size prefix
1969 case 13:
1970 emit_byte(0x66); // size prefix
1971 case 12:
1972 addr_nop_8();
1973 emit_byte(0x66); // size prefix
1974 emit_byte(0x66); // size prefix
1975 emit_byte(0x66); // size prefix
1976 emit_byte(0x90); // nop
1977 break;
1978 case 11:
1979 emit_byte(0x66); // size prefix
1980 case 10:
1981 emit_byte(0x66); // size prefix
1982 case 9:
1983 emit_byte(0x66); // size prefix
1984 case 8:
1985 addr_nop_8();
1986 break;
1987 case 7:
1988 addr_nop_7();
1989 break;
1990 case 6:
1991 emit_byte(0x66); // size prefix
1992 case 5:
1993 addr_nop_5();
1994 break;
1995 case 4:
1996 addr_nop_4();
1997 break;
1998 case 3:
1999 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2000 emit_byte(0x66); // size prefix
2001 case 2:
2002 emit_byte(0x66); // size prefix
2003 case 1:
2004 emit_byte(0x90); // nop
2005 break;
2006 default:
2007 assert(i == 0, " ");
2008 }
2009 return;
2010 }
2011 if (UseAddressNop && VM_Version::is_amd()) {
2012 //
2013 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2014 // 1: 0x90
2015 // 2: 0x66 0x90
2016 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2017 // 4: 0x0F 0x1F 0x40 0x00
2018 // 5: 0x0F 0x1F 0x44 0x00 0x00
2019 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2020 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2021 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2022 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2023 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2024 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2026 // The rest coding is AMD specific - use consecutive address nops
2028 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2029 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2030 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2031 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2032 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2033 // Size prefixes (0x66) are added for larger sizes
2035 while(i >= 22) {
2036 i -= 11;
2037 emit_byte(0x66); // size prefix
2038 emit_byte(0x66); // size prefix
2039 emit_byte(0x66); // size prefix
2040 addr_nop_8();
2041 }
2042 // Generate first nop for size between 21-12
2043 switch (i) {
2044 case 21:
2045 i -= 1;
2046 emit_byte(0x66); // size prefix
2047 case 20:
2048 case 19:
2049 i -= 1;
2050 emit_byte(0x66); // size prefix
2051 case 18:
2052 case 17:
2053 i -= 1;
2054 emit_byte(0x66); // size prefix
2055 case 16:
2056 case 15:
2057 i -= 8;
2058 addr_nop_8();
2059 break;
2060 case 14:
2061 case 13:
2062 i -= 7;
2063 addr_nop_7();
2064 break;
2065 case 12:
2066 i -= 6;
2067 emit_byte(0x66); // size prefix
2068 addr_nop_5();
2069 break;
2070 default:
2071 assert(i < 12, " ");
2072 }
2074 // Generate second nop for size between 11-1
2075 switch (i) {
2076 case 11:
2077 emit_byte(0x66); // size prefix
2078 case 10:
2079 emit_byte(0x66); // size prefix
2080 case 9:
2081 emit_byte(0x66); // size prefix
2082 case 8:
2083 addr_nop_8();
2084 break;
2085 case 7:
2086 addr_nop_7();
2087 break;
2088 case 6:
2089 emit_byte(0x66); // size prefix
2090 case 5:
2091 addr_nop_5();
2092 break;
2093 case 4:
2094 addr_nop_4();
2095 break;
2096 case 3:
2097 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2098 emit_byte(0x66); // size prefix
2099 case 2:
2100 emit_byte(0x66); // size prefix
2101 case 1:
2102 emit_byte(0x90); // nop
2103 break;
2104 default:
2105 assert(i == 0, " ");
2106 }
2107 return;
2108 }
2110 // Using nops with size prefixes "0x66 0x90".
2111 // From AMD Optimization Guide:
2112 // 1: 0x90
2113 // 2: 0x66 0x90
2114 // 3: 0x66 0x66 0x90
2115 // 4: 0x66 0x66 0x66 0x90
2116 // 5: 0x66 0x66 0x90 0x66 0x90
2117 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2118 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2119 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2120 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2121 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2122 //
2123 while(i > 12) {
2124 i -= 4;
2125 emit_byte(0x66); // size prefix
2126 emit_byte(0x66);
2127 emit_byte(0x66);
2128 emit_byte(0x90); // nop
2129 }
2130 // 1 - 12 nops
2131 if(i > 8) {
2132 if(i > 9) {
2133 i -= 1;
2134 emit_byte(0x66);
2135 }
2136 i -= 3;
2137 emit_byte(0x66);
2138 emit_byte(0x66);
2139 emit_byte(0x90);
2140 }
2141 // 1 - 8 nops
2142 if(i > 4) {
2143 if(i > 6) {
2144 i -= 1;
2145 emit_byte(0x66);
2146 }
2147 i -= 3;
2148 emit_byte(0x66);
2149 emit_byte(0x66);
2150 emit_byte(0x90);
2151 }
2152 switch (i) {
2153 case 4:
2154 emit_byte(0x66);
2155 case 3:
2156 emit_byte(0x66);
2157 case 2:
2158 emit_byte(0x66);
2159 case 1:
2160 emit_byte(0x90);
2161 break;
2162 default:
2163 assert(i == 0, " ");
2164 }
2165 }
2167 void Assembler::notl(Register dst) {
2168 int encode = prefix_and_encode(dst->encoding());
2169 emit_byte(0xF7);
2170 emit_byte(0xD0 | encode );
2171 }
2173 void Assembler::orl(Address dst, int32_t imm32) {
2174 InstructionMark im(this);
2175 prefix(dst);
2176 emit_byte(0x81);
2177 emit_operand(rcx, dst, 4);
2178 emit_long(imm32);
2179 }
2181 void Assembler::orl(Register dst, int32_t imm32) {
2182 prefix(dst);
2183 emit_arith(0x81, 0xC8, dst, imm32);
2184 }
2187 void Assembler::orl(Register dst, Address src) {
2188 InstructionMark im(this);
2189 prefix(src, dst);
2190 emit_byte(0x0B);
2191 emit_operand(dst, src);
2192 }
2195 void Assembler::orl(Register dst, Register src) {
2196 (void) prefix_and_encode(dst->encoding(), src->encoding());
2197 emit_arith(0x0B, 0xC0, dst, src);
2198 }
2200 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2201 assert(VM_Version::supports_sse4_2(), "");
2203 InstructionMark im(this);
2204 emit_byte(0x66);
2205 prefix(src, dst);
2206 emit_byte(0x0F);
2207 emit_byte(0x3A);
2208 emit_byte(0x61);
2209 emit_operand(dst, src);
2210 emit_byte(imm8);
2211 }
2213 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2214 assert(VM_Version::supports_sse4_2(), "");
2216 emit_byte(0x66);
2217 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2218 emit_byte(0x0F);
2219 emit_byte(0x3A);
2220 emit_byte(0x61);
2221 emit_byte(0xC0 | encode);
2222 emit_byte(imm8);
2223 }
2225 // generic
2226 void Assembler::pop(Register dst) {
2227 int encode = prefix_and_encode(dst->encoding());
2228 emit_byte(0x58 | encode);
2229 }
2231 void Assembler::popcntl(Register dst, Address src) {
2232 assert(VM_Version::supports_popcnt(), "must support");
2233 InstructionMark im(this);
2234 emit_byte(0xF3);
2235 prefix(src, dst);
2236 emit_byte(0x0F);
2237 emit_byte(0xB8);
2238 emit_operand(dst, src);
2239 }
2241 void Assembler::popcntl(Register dst, Register src) {
2242 assert(VM_Version::supports_popcnt(), "must support");
2243 emit_byte(0xF3);
2244 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2245 emit_byte(0x0F);
2246 emit_byte(0xB8);
2247 emit_byte(0xC0 | encode);
2248 }
2250 void Assembler::popf() {
2251 emit_byte(0x9D);
2252 }
2254 #ifndef _LP64 // no 32bit push/pop on amd64
2255 void Assembler::popl(Address dst) {
2256 // NOTE: this will adjust stack by 8byte on 64bits
2257 InstructionMark im(this);
2258 prefix(dst);
2259 emit_byte(0x8F);
2260 emit_operand(rax, dst);
2261 }
2262 #endif
2264 void Assembler::prefetch_prefix(Address src) {
2265 prefix(src);
2266 emit_byte(0x0F);
2267 }
2269 void Assembler::prefetchnta(Address src) {
2270 NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
2271 InstructionMark im(this);
2272 prefetch_prefix(src);
2273 emit_byte(0x18);
2274 emit_operand(rax, src); // 0, src
2275 }
2277 void Assembler::prefetchr(Address src) {
2278 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2279 InstructionMark im(this);
2280 prefetch_prefix(src);
2281 emit_byte(0x0D);
2282 emit_operand(rax, src); // 0, src
2283 }
2285 void Assembler::prefetcht0(Address src) {
2286 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2287 InstructionMark im(this);
2288 prefetch_prefix(src);
2289 emit_byte(0x18);
2290 emit_operand(rcx, src); // 1, src
2291 }
2293 void Assembler::prefetcht1(Address src) {
2294 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2295 InstructionMark im(this);
2296 prefetch_prefix(src);
2297 emit_byte(0x18);
2298 emit_operand(rdx, src); // 2, src
2299 }
2301 void Assembler::prefetcht2(Address src) {
2302 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2303 InstructionMark im(this);
2304 prefetch_prefix(src);
2305 emit_byte(0x18);
2306 emit_operand(rbx, src); // 3, src
2307 }
2309 void Assembler::prefetchw(Address src) {
2310 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
2311 InstructionMark im(this);
2312 prefetch_prefix(src);
2313 emit_byte(0x0D);
2314 emit_operand(rcx, src); // 1, src
2315 }
2317 void Assembler::prefix(Prefix p) {
2318 a_byte(p);
2319 }
2321 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2322 assert(isByte(mode), "invalid value");
2323 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2325 emit_byte(0x66);
2326 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2327 emit_byte(0x0F);
2328 emit_byte(0x70);
2329 emit_byte(0xC0 | encode);
2330 emit_byte(mode & 0xFF);
2332 }
2334 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2335 assert(isByte(mode), "invalid value");
2336 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2338 InstructionMark im(this);
2339 emit_byte(0x66);
2340 prefix(src, dst);
2341 emit_byte(0x0F);
2342 emit_byte(0x70);
2343 emit_operand(dst, src);
2344 emit_byte(mode & 0xFF);
2345 }
2347 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2348 assert(isByte(mode), "invalid value");
2349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2351 emit_byte(0xF2);
2352 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2353 emit_byte(0x0F);
2354 emit_byte(0x70);
2355 emit_byte(0xC0 | encode);
2356 emit_byte(mode & 0xFF);
2357 }
2359 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2360 assert(isByte(mode), "invalid value");
2361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2363 InstructionMark im(this);
2364 emit_byte(0xF2);
2365 prefix(src, dst); // QQ new
2366 emit_byte(0x0F);
2367 emit_byte(0x70);
2368 emit_operand(dst, src);
2369 emit_byte(mode & 0xFF);
2370 }
2372 void Assembler::psrlq(XMMRegister dst, int shift) {
2373 // HMM Table D-1 says sse2 or mmx
2374 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2376 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
2377 emit_byte(0x66);
2378 emit_byte(0x0F);
2379 emit_byte(0x73);
2380 emit_byte(0xC0 | encode);
2381 emit_byte(shift);
2382 }
2384 void Assembler::ptest(XMMRegister dst, Address src) {
2385 assert(VM_Version::supports_sse4_1(), "");
2387 InstructionMark im(this);
2388 emit_byte(0x66);
2389 prefix(src, dst);
2390 emit_byte(0x0F);
2391 emit_byte(0x38);
2392 emit_byte(0x17);
2393 emit_operand(dst, src);
2394 }
2396 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2397 assert(VM_Version::supports_sse4_1(), "");
2399 emit_byte(0x66);
2400 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2401 emit_byte(0x0F);
2402 emit_byte(0x38);
2403 emit_byte(0x17);
2404 emit_byte(0xC0 | encode);
2405 }
2407 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2408 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2409 emit_byte(0x66);
2410 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2411 emit_byte(0x0F);
2412 emit_byte(0x60);
2413 emit_byte(0xC0 | encode);
2414 }
2416 void Assembler::push(int32_t imm32) {
2417 // in 64bits we push 64bits onto the stack but only
2418 // take a 32bit immediate
2419 emit_byte(0x68);
2420 emit_long(imm32);
2421 }
2423 void Assembler::push(Register src) {
2424 int encode = prefix_and_encode(src->encoding());
2426 emit_byte(0x50 | encode);
2427 }
2429 void Assembler::pushf() {
2430 emit_byte(0x9C);
2431 }
2433 #ifndef _LP64 // no 32bit push/pop on amd64
2434 void Assembler::pushl(Address src) {
2435 // Note this will push 64bit on 64bit
2436 InstructionMark im(this);
2437 prefix(src);
2438 emit_byte(0xFF);
2439 emit_operand(rsi, src);
2440 }
2441 #endif
2443 void Assembler::pxor(XMMRegister dst, Address src) {
2444 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2445 InstructionMark im(this);
2446 emit_byte(0x66);
2447 prefix(src, dst);
2448 emit_byte(0x0F);
2449 emit_byte(0xEF);
2450 emit_operand(dst, src);
2451 }
2453 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2454 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2455 InstructionMark im(this);
2456 emit_byte(0x66);
2457 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2458 emit_byte(0x0F);
2459 emit_byte(0xEF);
2460 emit_byte(0xC0 | encode);
2461 }
2463 void Assembler::rcll(Register dst, int imm8) {
2464 assert(isShiftCount(imm8), "illegal shift count");
2465 int encode = prefix_and_encode(dst->encoding());
2466 if (imm8 == 1) {
2467 emit_byte(0xD1);
2468 emit_byte(0xD0 | encode);
2469 } else {
2470 emit_byte(0xC1);
2471 emit_byte(0xD0 | encode);
2472 emit_byte(imm8);
2473 }
2474 }
2476 // copies data from [esi] to [edi] using rcx pointer sized words
2477 // generic
2478 void Assembler::rep_mov() {
2479 emit_byte(0xF3);
2480 // MOVSQ
2481 LP64_ONLY(prefix(REX_W));
2482 emit_byte(0xA5);
2483 }
2485 // sets rcx pointer sized words with rax, value at [edi]
2486 // generic
2487 void Assembler::rep_set() { // rep_set
2488 emit_byte(0xF3);
2489 // STOSQ
2490 LP64_ONLY(prefix(REX_W));
2491 emit_byte(0xAB);
2492 }
2494 // scans rcx pointer sized words at [edi] for occurance of rax,
2495 // generic
2496 void Assembler::repne_scan() { // repne_scan
2497 emit_byte(0xF2);
2498 // SCASQ
2499 LP64_ONLY(prefix(REX_W));
2500 emit_byte(0xAF);
2501 }
2503 #ifdef _LP64
2504 // scans rcx 4 byte words at [edi] for occurance of rax,
2505 // generic
2506 void Assembler::repne_scanl() { // repne_scan
2507 emit_byte(0xF2);
2508 // SCASL
2509 emit_byte(0xAF);
2510 }
2511 #endif
2513 void Assembler::ret(int imm16) {
2514 if (imm16 == 0) {
2515 emit_byte(0xC3);
2516 } else {
2517 emit_byte(0xC2);
2518 emit_word(imm16);
2519 }
2520 }
2522 void Assembler::sahf() {
2523 #ifdef _LP64
2524 // Not supported in 64bit mode
2525 ShouldNotReachHere();
2526 #endif
2527 emit_byte(0x9E);
2528 }
2530 void Assembler::sarl(Register dst, int imm8) {
2531 int encode = prefix_and_encode(dst->encoding());
2532 assert(isShiftCount(imm8), "illegal shift count");
2533 if (imm8 == 1) {
2534 emit_byte(0xD1);
2535 emit_byte(0xF8 | encode);
2536 } else {
2537 emit_byte(0xC1);
2538 emit_byte(0xF8 | encode);
2539 emit_byte(imm8);
2540 }
2541 }
2543 void Assembler::sarl(Register dst) {
2544 int encode = prefix_and_encode(dst->encoding());
2545 emit_byte(0xD3);
2546 emit_byte(0xF8 | encode);
2547 }
2549 void Assembler::sbbl(Address dst, int32_t imm32) {
2550 InstructionMark im(this);
2551 prefix(dst);
2552 emit_arith_operand(0x81, rbx, dst, imm32);
2553 }
2555 void Assembler::sbbl(Register dst, int32_t imm32) {
2556 prefix(dst);
2557 emit_arith(0x81, 0xD8, dst, imm32);
2558 }
2561 void Assembler::sbbl(Register dst, Address src) {
2562 InstructionMark im(this);
2563 prefix(src, dst);
2564 emit_byte(0x1B);
2565 emit_operand(dst, src);
2566 }
2568 void Assembler::sbbl(Register dst, Register src) {
2569 (void) prefix_and_encode(dst->encoding(), src->encoding());
2570 emit_arith(0x1B, 0xC0, dst, src);
2571 }
2573 void Assembler::setb(Condition cc, Register dst) {
2574 assert(0 <= cc && cc < 16, "illegal cc");
2575 int encode = prefix_and_encode(dst->encoding(), true);
2576 emit_byte(0x0F);
2577 emit_byte(0x90 | cc);
2578 emit_byte(0xC0 | encode);
2579 }
2581 void Assembler::shll(Register dst, int imm8) {
2582 assert(isShiftCount(imm8), "illegal shift count");
2583 int encode = prefix_and_encode(dst->encoding());
2584 if (imm8 == 1 ) {
2585 emit_byte(0xD1);
2586 emit_byte(0xE0 | encode);
2587 } else {
2588 emit_byte(0xC1);
2589 emit_byte(0xE0 | encode);
2590 emit_byte(imm8);
2591 }
2592 }
2594 void Assembler::shll(Register dst) {
2595 int encode = prefix_and_encode(dst->encoding());
2596 emit_byte(0xD3);
2597 emit_byte(0xE0 | encode);
2598 }
2600 void Assembler::shrl(Register dst, int imm8) {
2601 assert(isShiftCount(imm8), "illegal shift count");
2602 int encode = prefix_and_encode(dst->encoding());
2603 emit_byte(0xC1);
2604 emit_byte(0xE8 | encode);
2605 emit_byte(imm8);
2606 }
2608 void Assembler::shrl(Register dst) {
2609 int encode = prefix_and_encode(dst->encoding());
2610 emit_byte(0xD3);
2611 emit_byte(0xE8 | encode);
2612 }
2614 // copies a single word from [esi] to [edi]
2615 void Assembler::smovl() {
2616 emit_byte(0xA5);
2617 }
2619 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2620 // HMM Table D-1 says sse2
2621 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2622 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2623 emit_byte(0xF2);
2624 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2625 emit_byte(0x0F);
2626 emit_byte(0x51);
2627 emit_byte(0xC0 | encode);
2628 }
2630 void Assembler::stmxcsr( Address dst) {
2631 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2632 InstructionMark im(this);
2633 prefix(dst);
2634 emit_byte(0x0F);
2635 emit_byte(0xAE);
2636 emit_operand(as_Register(3), dst);
2637 }
2639 void Assembler::subl(Address dst, int32_t imm32) {
2640 InstructionMark im(this);
2641 prefix(dst);
2642 if (is8bit(imm32)) {
2643 emit_byte(0x83);
2644 emit_operand(rbp, dst, 1);
2645 emit_byte(imm32 & 0xFF);
2646 } else {
2647 emit_byte(0x81);
2648 emit_operand(rbp, dst, 4);
2649 emit_long(imm32);
2650 }
2651 }
2653 void Assembler::subl(Register dst, int32_t imm32) {
2654 prefix(dst);
2655 emit_arith(0x81, 0xE8, dst, imm32);
2656 }
2658 void Assembler::subl(Address dst, Register src) {
2659 InstructionMark im(this);
2660 prefix(dst, src);
2661 emit_byte(0x29);
2662 emit_operand(src, dst);
2663 }
2665 void Assembler::subl(Register dst, Address src) {
2666 InstructionMark im(this);
2667 prefix(src, dst);
2668 emit_byte(0x2B);
2669 emit_operand(dst, src);
2670 }
2672 void Assembler::subl(Register dst, Register src) {
2673 (void) prefix_and_encode(dst->encoding(), src->encoding());
2674 emit_arith(0x2B, 0xC0, dst, src);
2675 }
2677 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2679 emit_byte(0xF2);
2680 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2681 emit_byte(0x0F);
2682 emit_byte(0x5C);
2683 emit_byte(0xC0 | encode);
2684 }
2686 void Assembler::subsd(XMMRegister dst, Address src) {
2687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2688 InstructionMark im(this);
2689 emit_byte(0xF2);
2690 prefix(src, dst);
2691 emit_byte(0x0F);
2692 emit_byte(0x5C);
2693 emit_operand(dst, src);
2694 }
2696 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2697 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2698 emit_byte(0xF3);
2699 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2700 emit_byte(0x0F);
2701 emit_byte(0x5C);
2702 emit_byte(0xC0 | encode);
2703 }
2705 void Assembler::subss(XMMRegister dst, Address src) {
2706 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2707 InstructionMark im(this);
2708 emit_byte(0xF3);
2709 prefix(src, dst);
2710 emit_byte(0x0F);
2711 emit_byte(0x5C);
2712 emit_operand(dst, src);
2713 }
2715 void Assembler::testb(Register dst, int imm8) {
2716 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2717 (void) prefix_and_encode(dst->encoding(), true);
2718 emit_arith_b(0xF6, 0xC0, dst, imm8);
2719 }
2721 void Assembler::testl(Register dst, int32_t imm32) {
2722 // not using emit_arith because test
2723 // doesn't support sign-extension of
2724 // 8bit operands
2725 int encode = dst->encoding();
2726 if (encode == 0) {
2727 emit_byte(0xA9);
2728 } else {
2729 encode = prefix_and_encode(encode);
2730 emit_byte(0xF7);
2731 emit_byte(0xC0 | encode);
2732 }
2733 emit_long(imm32);
2734 }
2736 void Assembler::testl(Register dst, Register src) {
2737 (void) prefix_and_encode(dst->encoding(), src->encoding());
2738 emit_arith(0x85, 0xC0, dst, src);
2739 }
2741 void Assembler::testl(Register dst, Address src) {
2742 InstructionMark im(this);
2743 prefix(src, dst);
2744 emit_byte(0x85);
2745 emit_operand(dst, src);
2746 }
2748 void Assembler::ucomisd(XMMRegister dst, Address src) {
2749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2750 emit_byte(0x66);
2751 ucomiss(dst, src);
2752 }
2754 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2756 emit_byte(0x66);
2757 ucomiss(dst, src);
2758 }
2760 void Assembler::ucomiss(XMMRegister dst, Address src) {
2761 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2763 InstructionMark im(this);
2764 prefix(src, dst);
2765 emit_byte(0x0F);
2766 emit_byte(0x2E);
2767 emit_operand(dst, src);
2768 }
2770 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2771 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2772 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2773 emit_byte(0x0F);
2774 emit_byte(0x2E);
2775 emit_byte(0xC0 | encode);
2776 }
2779 void Assembler::xaddl(Address dst, Register src) {
2780 InstructionMark im(this);
2781 prefix(dst, src);
2782 emit_byte(0x0F);
2783 emit_byte(0xC1);
2784 emit_operand(src, dst);
2785 }
2787 void Assembler::xchgl(Register dst, Address src) { // xchg
2788 InstructionMark im(this);
2789 prefix(src, dst);
2790 emit_byte(0x87);
2791 emit_operand(dst, src);
2792 }
2794 void Assembler::xchgl(Register dst, Register src) {
2795 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2796 emit_byte(0x87);
2797 emit_byte(0xc0 | encode);
2798 }
2800 void Assembler::xorl(Register dst, int32_t imm32) {
2801 prefix(dst);
2802 emit_arith(0x81, 0xF0, dst, imm32);
2803 }
2805 void Assembler::xorl(Register dst, Address src) {
2806 InstructionMark im(this);
2807 prefix(src, dst);
2808 emit_byte(0x33);
2809 emit_operand(dst, src);
2810 }
2812 void Assembler::xorl(Register dst, Register src) {
2813 (void) prefix_and_encode(dst->encoding(), src->encoding());
2814 emit_arith(0x33, 0xC0, dst, src);
2815 }
2817 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2819 emit_byte(0x66);
2820 xorps(dst, src);
2821 }
2823 void Assembler::xorpd(XMMRegister dst, Address src) {
2824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2825 InstructionMark im(this);
2826 emit_byte(0x66);
2827 prefix(src, dst);
2828 emit_byte(0x0F);
2829 emit_byte(0x57);
2830 emit_operand(dst, src);
2831 }
2834 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2836 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2837 emit_byte(0x0F);
2838 emit_byte(0x57);
2839 emit_byte(0xC0 | encode);
2840 }
2842 void Assembler::xorps(XMMRegister dst, Address src) {
2843 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2844 InstructionMark im(this);
2845 prefix(src, dst);
2846 emit_byte(0x0F);
2847 emit_byte(0x57);
2848 emit_operand(dst, src);
2849 }
2851 #ifndef _LP64
2852 // 32bit only pieces of the assembler
2854 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
2855 // NO PREFIX AS NEVER 64BIT
2856 InstructionMark im(this);
2857 emit_byte(0x81);
2858 emit_byte(0xF8 | src1->encoding());
2859 emit_data(imm32, rspec, 0);
2860 }
2862 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
2863 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
2864 InstructionMark im(this);
2865 emit_byte(0x81);
2866 emit_operand(rdi, src1);
2867 emit_data(imm32, rspec, 0);
2868 }
2870 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
2871 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
2872 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
2873 void Assembler::cmpxchg8(Address adr) {
2874 InstructionMark im(this);
2875 emit_byte(0x0F);
2876 emit_byte(0xc7);
2877 emit_operand(rcx, adr);
2878 }
2880 void Assembler::decl(Register dst) {
2881 // Don't use it directly. Use MacroAssembler::decrementl() instead.
2882 emit_byte(0x48 | dst->encoding());
2883 }
2885 #endif // _LP64
2887 // 64bit typically doesn't use the x87 but needs to for the trig funcs
2889 void Assembler::fabs() {
2890 emit_byte(0xD9);
2891 emit_byte(0xE1);
2892 }
2894 void Assembler::fadd(int i) {
2895 emit_farith(0xD8, 0xC0, i);
2896 }
2898 void Assembler::fadd_d(Address src) {
2899 InstructionMark im(this);
2900 emit_byte(0xDC);
2901 emit_operand32(rax, src);
2902 }
2904 void Assembler::fadd_s(Address src) {
2905 InstructionMark im(this);
2906 emit_byte(0xD8);
2907 emit_operand32(rax, src);
2908 }
2910 void Assembler::fadda(int i) {
2911 emit_farith(0xDC, 0xC0, i);
2912 }
2914 void Assembler::faddp(int i) {
2915 emit_farith(0xDE, 0xC0, i);
2916 }
2918 void Assembler::fchs() {
2919 emit_byte(0xD9);
2920 emit_byte(0xE0);
2921 }
2923 void Assembler::fcom(int i) {
2924 emit_farith(0xD8, 0xD0, i);
2925 }
2927 void Assembler::fcomp(int i) {
2928 emit_farith(0xD8, 0xD8, i);
2929 }
2931 void Assembler::fcomp_d(Address src) {
2932 InstructionMark im(this);
2933 emit_byte(0xDC);
2934 emit_operand32(rbx, src);
2935 }
2937 void Assembler::fcomp_s(Address src) {
2938 InstructionMark im(this);
2939 emit_byte(0xD8);
2940 emit_operand32(rbx, src);
2941 }
2943 void Assembler::fcompp() {
2944 emit_byte(0xDE);
2945 emit_byte(0xD9);
2946 }
2948 void Assembler::fcos() {
2949 emit_byte(0xD9);
2950 emit_byte(0xFF);
2951 }
2953 void Assembler::fdecstp() {
2954 emit_byte(0xD9);
2955 emit_byte(0xF6);
2956 }
2958 void Assembler::fdiv(int i) {
2959 emit_farith(0xD8, 0xF0, i);
2960 }
2962 void Assembler::fdiv_d(Address src) {
2963 InstructionMark im(this);
2964 emit_byte(0xDC);
2965 emit_operand32(rsi, src);
2966 }
2968 void Assembler::fdiv_s(Address src) {
2969 InstructionMark im(this);
2970 emit_byte(0xD8);
2971 emit_operand32(rsi, src);
2972 }
2974 void Assembler::fdiva(int i) {
2975 emit_farith(0xDC, 0xF8, i);
2976 }
2978 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
2979 // is erroneous for some of the floating-point instructions below.
2981 void Assembler::fdivp(int i) {
2982 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
2983 }
2985 void Assembler::fdivr(int i) {
2986 emit_farith(0xD8, 0xF8, i);
2987 }
2989 void Assembler::fdivr_d(Address src) {
2990 InstructionMark im(this);
2991 emit_byte(0xDC);
2992 emit_operand32(rdi, src);
2993 }
2995 void Assembler::fdivr_s(Address src) {
2996 InstructionMark im(this);
2997 emit_byte(0xD8);
2998 emit_operand32(rdi, src);
2999 }
3001 void Assembler::fdivra(int i) {
3002 emit_farith(0xDC, 0xF0, i);
3003 }
3005 void Assembler::fdivrp(int i) {
3006 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3007 }
3009 void Assembler::ffree(int i) {
3010 emit_farith(0xDD, 0xC0, i);
3011 }
3013 void Assembler::fild_d(Address adr) {
3014 InstructionMark im(this);
3015 emit_byte(0xDF);
3016 emit_operand32(rbp, adr);
3017 }
3019 void Assembler::fild_s(Address adr) {
3020 InstructionMark im(this);
3021 emit_byte(0xDB);
3022 emit_operand32(rax, adr);
3023 }
3025 void Assembler::fincstp() {
3026 emit_byte(0xD9);
3027 emit_byte(0xF7);
3028 }
3030 void Assembler::finit() {
3031 emit_byte(0x9B);
3032 emit_byte(0xDB);
3033 emit_byte(0xE3);
3034 }
3036 void Assembler::fist_s(Address adr) {
3037 InstructionMark im(this);
3038 emit_byte(0xDB);
3039 emit_operand32(rdx, adr);
3040 }
3042 void Assembler::fistp_d(Address adr) {
3043 InstructionMark im(this);
3044 emit_byte(0xDF);
3045 emit_operand32(rdi, adr);
3046 }
3048 void Assembler::fistp_s(Address adr) {
3049 InstructionMark im(this);
3050 emit_byte(0xDB);
3051 emit_operand32(rbx, adr);
3052 }
3054 void Assembler::fld1() {
3055 emit_byte(0xD9);
3056 emit_byte(0xE8);
3057 }
3059 void Assembler::fld_d(Address adr) {
3060 InstructionMark im(this);
3061 emit_byte(0xDD);
3062 emit_operand32(rax, adr);
3063 }
3065 void Assembler::fld_s(Address adr) {
3066 InstructionMark im(this);
3067 emit_byte(0xD9);
3068 emit_operand32(rax, adr);
3069 }
3072 void Assembler::fld_s(int index) {
3073 emit_farith(0xD9, 0xC0, index);
3074 }
3076 void Assembler::fld_x(Address adr) {
3077 InstructionMark im(this);
3078 emit_byte(0xDB);
3079 emit_operand32(rbp, adr);
3080 }
3082 void Assembler::fldcw(Address src) {
3083 InstructionMark im(this);
3084 emit_byte(0xd9);
3085 emit_operand32(rbp, src);
3086 }
3088 void Assembler::fldenv(Address src) {
3089 InstructionMark im(this);
3090 emit_byte(0xD9);
3091 emit_operand32(rsp, src);
3092 }
3094 void Assembler::fldlg2() {
3095 emit_byte(0xD9);
3096 emit_byte(0xEC);
3097 }
3099 void Assembler::fldln2() {
3100 emit_byte(0xD9);
3101 emit_byte(0xED);
3102 }
3104 void Assembler::fldz() {
3105 emit_byte(0xD9);
3106 emit_byte(0xEE);
3107 }
3109 void Assembler::flog() {
3110 fldln2();
3111 fxch();
3112 fyl2x();
3113 }
3115 void Assembler::flog10() {
3116 fldlg2();
3117 fxch();
3118 fyl2x();
3119 }
3121 void Assembler::fmul(int i) {
3122 emit_farith(0xD8, 0xC8, i);
3123 }
3125 void Assembler::fmul_d(Address src) {
3126 InstructionMark im(this);
3127 emit_byte(0xDC);
3128 emit_operand32(rcx, src);
3129 }
3131 void Assembler::fmul_s(Address src) {
3132 InstructionMark im(this);
3133 emit_byte(0xD8);
3134 emit_operand32(rcx, src);
3135 }
3137 void Assembler::fmula(int i) {
3138 emit_farith(0xDC, 0xC8, i);
3139 }
3141 void Assembler::fmulp(int i) {
3142 emit_farith(0xDE, 0xC8, i);
3143 }
3145 void Assembler::fnsave(Address dst) {
3146 InstructionMark im(this);
3147 emit_byte(0xDD);
3148 emit_operand32(rsi, dst);
3149 }
3151 void Assembler::fnstcw(Address src) {
3152 InstructionMark im(this);
3153 emit_byte(0x9B);
3154 emit_byte(0xD9);
3155 emit_operand32(rdi, src);
3156 }
3158 void Assembler::fnstsw_ax() {
3159 emit_byte(0xdF);
3160 emit_byte(0xE0);
3161 }
3163 void Assembler::fprem() {
3164 emit_byte(0xD9);
3165 emit_byte(0xF8);
3166 }
3168 void Assembler::fprem1() {
3169 emit_byte(0xD9);
3170 emit_byte(0xF5);
3171 }
3173 void Assembler::frstor(Address src) {
3174 InstructionMark im(this);
3175 emit_byte(0xDD);
3176 emit_operand32(rsp, src);
3177 }
3179 void Assembler::fsin() {
3180 emit_byte(0xD9);
3181 emit_byte(0xFE);
3182 }
3184 void Assembler::fsqrt() {
3185 emit_byte(0xD9);
3186 emit_byte(0xFA);
3187 }
3189 void Assembler::fst_d(Address adr) {
3190 InstructionMark im(this);
3191 emit_byte(0xDD);
3192 emit_operand32(rdx, adr);
3193 }
3195 void Assembler::fst_s(Address adr) {
3196 InstructionMark im(this);
3197 emit_byte(0xD9);
3198 emit_operand32(rdx, adr);
3199 }
3201 void Assembler::fstp_d(Address adr) {
3202 InstructionMark im(this);
3203 emit_byte(0xDD);
3204 emit_operand32(rbx, adr);
3205 }
3207 void Assembler::fstp_d(int index) {
3208 emit_farith(0xDD, 0xD8, index);
3209 }
3211 void Assembler::fstp_s(Address adr) {
3212 InstructionMark im(this);
3213 emit_byte(0xD9);
3214 emit_operand32(rbx, adr);
3215 }
3217 void Assembler::fstp_x(Address adr) {
3218 InstructionMark im(this);
3219 emit_byte(0xDB);
3220 emit_operand32(rdi, adr);
3221 }
3223 void Assembler::fsub(int i) {
3224 emit_farith(0xD8, 0xE0, i);
3225 }
3227 void Assembler::fsub_d(Address src) {
3228 InstructionMark im(this);
3229 emit_byte(0xDC);
3230 emit_operand32(rsp, src);
3231 }
3233 void Assembler::fsub_s(Address src) {
3234 InstructionMark im(this);
3235 emit_byte(0xD8);
3236 emit_operand32(rsp, src);
3237 }
3239 void Assembler::fsuba(int i) {
3240 emit_farith(0xDC, 0xE8, i);
3241 }
3243 void Assembler::fsubp(int i) {
3244 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
3245 }
3247 void Assembler::fsubr(int i) {
3248 emit_farith(0xD8, 0xE8, i);
3249 }
3251 void Assembler::fsubr_d(Address src) {
3252 InstructionMark im(this);
3253 emit_byte(0xDC);
3254 emit_operand32(rbp, src);
3255 }
3257 void Assembler::fsubr_s(Address src) {
3258 InstructionMark im(this);
3259 emit_byte(0xD8);
3260 emit_operand32(rbp, src);
3261 }
3263 void Assembler::fsubra(int i) {
3264 emit_farith(0xDC, 0xE0, i);
3265 }
3267 void Assembler::fsubrp(int i) {
3268 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
3269 }
3271 void Assembler::ftan() {
3272 emit_byte(0xD9);
3273 emit_byte(0xF2);
3274 emit_byte(0xDD);
3275 emit_byte(0xD8);
3276 }
3278 void Assembler::ftst() {
3279 emit_byte(0xD9);
3280 emit_byte(0xE4);
3281 }
3283 void Assembler::fucomi(int i) {
3284 // make sure the instruction is supported (introduced for P6, together with cmov)
3285 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3286 emit_farith(0xDB, 0xE8, i);
3287 }
3289 void Assembler::fucomip(int i) {
3290 // make sure the instruction is supported (introduced for P6, together with cmov)
3291 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3292 emit_farith(0xDF, 0xE8, i);
3293 }
3295 void Assembler::fwait() {
3296 emit_byte(0x9B);
3297 }
3299 void Assembler::fxch(int i) {
3300 emit_farith(0xD9, 0xC8, i);
3301 }
3303 void Assembler::fyl2x() {
3304 emit_byte(0xD9);
3305 emit_byte(0xF1);
3306 }
3309 #ifndef _LP64
3311 void Assembler::incl(Register dst) {
3312 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3313 emit_byte(0x40 | dst->encoding());
3314 }
3316 void Assembler::lea(Register dst, Address src) {
3317 leal(dst, src);
3318 }
3320 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3321 InstructionMark im(this);
3322 emit_byte(0xC7);
3323 emit_operand(rax, dst);
3324 emit_data((int)imm32, rspec, 0);
3325 }
3327 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3328 InstructionMark im(this);
3329 int encode = prefix_and_encode(dst->encoding());
3330 emit_byte(0xB8 | encode);
3331 emit_data((int)imm32, rspec, 0);
3332 }
3334 void Assembler::popa() { // 32bit
3335 emit_byte(0x61);
3336 }
3338 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
3339 InstructionMark im(this);
3340 emit_byte(0x68);
3341 emit_data(imm32, rspec, 0);
3342 }
3344 void Assembler::pusha() { // 32bit
3345 emit_byte(0x60);
3346 }
3348 void Assembler::set_byte_if_not_zero(Register dst) {
3349 emit_byte(0x0F);
3350 emit_byte(0x95);
3351 emit_byte(0xE0 | dst->encoding());
3352 }
3354 void Assembler::shldl(Register dst, Register src) {
3355 emit_byte(0x0F);
3356 emit_byte(0xA5);
3357 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3358 }
3360 void Assembler::shrdl(Register dst, Register src) {
3361 emit_byte(0x0F);
3362 emit_byte(0xAD);
3363 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3364 }
3366 #else // LP64
3368 void Assembler::set_byte_if_not_zero(Register dst) {
3369 int enc = prefix_and_encode(dst->encoding(), true);
3370 emit_byte(0x0F);
3371 emit_byte(0x95);
3372 emit_byte(0xE0 | enc);
3373 }
3375 // 64bit only pieces of the assembler
3376 // This should only be used by 64bit instructions that can use rip-relative
3377 // it cannot be used by instructions that want an immediate value.
3379 bool Assembler::reachable(AddressLiteral adr) {
3380 int64_t disp;
3381 // None will force a 64bit literal to the code stream. Likely a placeholder
3382 // for something that will be patched later and we need to certain it will
3383 // always be reachable.
3384 if (adr.reloc() == relocInfo::none) {
3385 return false;
3386 }
3387 if (adr.reloc() == relocInfo::internal_word_type) {
3388 // This should be rip relative and easily reachable.
3389 return true;
3390 }
3391 if (adr.reloc() == relocInfo::virtual_call_type ||
3392 adr.reloc() == relocInfo::opt_virtual_call_type ||
3393 adr.reloc() == relocInfo::static_call_type ||
3394 adr.reloc() == relocInfo::static_stub_type ) {
3395 // This should be rip relative within the code cache and easily
3396 // reachable until we get huge code caches. (At which point
3397 // ic code is going to have issues).
3398 return true;
3399 }
3400 if (adr.reloc() != relocInfo::external_word_type &&
3401 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
3402 adr.reloc() != relocInfo::poll_type && // relocs to identify them
3403 adr.reloc() != relocInfo::runtime_call_type ) {
3404 return false;
3405 }
3407 // Stress the correction code
3408 if (ForceUnreachable) {
3409 // Must be runtimecall reloc, see if it is in the codecache
3410 // Flipping stuff in the codecache to be unreachable causes issues
3411 // with things like inline caches where the additional instructions
3412 // are not handled.
3413 if (CodeCache::find_blob(adr._target) == NULL) {
3414 return false;
3415 }
3416 }
3417 // For external_word_type/runtime_call_type if it is reachable from where we
3418 // are now (possibly a temp buffer) and where we might end up
3419 // anywhere in the codeCache then we are always reachable.
3420 // This would have to change if we ever save/restore shared code
3421 // to be more pessimistic.
3423 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
3424 if (!is_simm32(disp)) return false;
3425 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
3426 if (!is_simm32(disp)) return false;
3428 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
3430 // Because rip relative is a disp + address_of_next_instruction and we
3431 // don't know the value of address_of_next_instruction we apply a fudge factor
3432 // to make sure we will be ok no matter the size of the instruction we get placed into.
3433 // We don't have to fudge the checks above here because they are already worst case.
3435 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
3436 // + 4 because better safe than sorry.
3437 const int fudge = 12 + 4;
3438 if (disp < 0) {
3439 disp -= fudge;
3440 } else {
3441 disp += fudge;
3442 }
3443 return is_simm32(disp);
3444 }
3446 void Assembler::emit_data64(jlong data,
3447 relocInfo::relocType rtype,
3448 int format) {
3449 if (rtype == relocInfo::none) {
3450 emit_long64(data);
3451 } else {
3452 emit_data64(data, Relocation::spec_simple(rtype), format);
3453 }
3454 }
3456 void Assembler::emit_data64(jlong data,
3457 RelocationHolder const& rspec,
3458 int format) {
3459 assert(imm_operand == 0, "default format must be immediate in this file");
3460 assert(imm_operand == format, "must be immediate");
3461 assert(inst_mark() != NULL, "must be inside InstructionMark");
3462 // Do not use AbstractAssembler::relocate, which is not intended for
3463 // embedded words. Instead, relocate to the enclosing instruction.
3464 code_section()->relocate(inst_mark(), rspec, format);
3465 #ifdef ASSERT
3466 check_relocation(rspec, format);
3467 #endif
3468 emit_long64(data);
3469 }
3471 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
3472 if (reg_enc >= 8) {
3473 prefix(REX_B);
3474 reg_enc -= 8;
3475 } else if (byteinst && reg_enc >= 4) {
3476 prefix(REX);
3477 }
3478 return reg_enc;
3479 }
3481 int Assembler::prefixq_and_encode(int reg_enc) {
3482 if (reg_enc < 8) {
3483 prefix(REX_W);
3484 } else {
3485 prefix(REX_WB);
3486 reg_enc -= 8;
3487 }
3488 return reg_enc;
3489 }
3491 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
3492 if (dst_enc < 8) {
3493 if (src_enc >= 8) {
3494 prefix(REX_B);
3495 src_enc -= 8;
3496 } else if (byteinst && src_enc >= 4) {
3497 prefix(REX);
3498 }
3499 } else {
3500 if (src_enc < 8) {
3501 prefix(REX_R);
3502 } else {
3503 prefix(REX_RB);
3504 src_enc -= 8;
3505 }
3506 dst_enc -= 8;
3507 }
3508 return dst_enc << 3 | src_enc;
3509 }
3511 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
3512 if (dst_enc < 8) {
3513 if (src_enc < 8) {
3514 prefix(REX_W);
3515 } else {
3516 prefix(REX_WB);
3517 src_enc -= 8;
3518 }
3519 } else {
3520 if (src_enc < 8) {
3521 prefix(REX_WR);
3522 } else {
3523 prefix(REX_WRB);
3524 src_enc -= 8;
3525 }
3526 dst_enc -= 8;
3527 }
3528 return dst_enc << 3 | src_enc;
3529 }
3531 void Assembler::prefix(Register reg) {
3532 if (reg->encoding() >= 8) {
3533 prefix(REX_B);
3534 }
3535 }
3537 void Assembler::prefix(Address adr) {
3538 if (adr.base_needs_rex()) {
3539 if (adr.index_needs_rex()) {
3540 prefix(REX_XB);
3541 } else {
3542 prefix(REX_B);
3543 }
3544 } else {
3545 if (adr.index_needs_rex()) {
3546 prefix(REX_X);
3547 }
3548 }
3549 }
3551 void Assembler::prefixq(Address adr) {
3552 if (adr.base_needs_rex()) {
3553 if (adr.index_needs_rex()) {
3554 prefix(REX_WXB);
3555 } else {
3556 prefix(REX_WB);
3557 }
3558 } else {
3559 if (adr.index_needs_rex()) {
3560 prefix(REX_WX);
3561 } else {
3562 prefix(REX_W);
3563 }
3564 }
3565 }
3568 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
3569 if (reg->encoding() < 8) {
3570 if (adr.base_needs_rex()) {
3571 if (adr.index_needs_rex()) {
3572 prefix(REX_XB);
3573 } else {
3574 prefix(REX_B);
3575 }
3576 } else {
3577 if (adr.index_needs_rex()) {
3578 prefix(REX_X);
3579 } else if (reg->encoding() >= 4 ) {
3580 prefix(REX);
3581 }
3582 }
3583 } else {
3584 if (adr.base_needs_rex()) {
3585 if (adr.index_needs_rex()) {
3586 prefix(REX_RXB);
3587 } else {
3588 prefix(REX_RB);
3589 }
3590 } else {
3591 if (adr.index_needs_rex()) {
3592 prefix(REX_RX);
3593 } else {
3594 prefix(REX_R);
3595 }
3596 }
3597 }
3598 }
3600 void Assembler::prefixq(Address adr, Register src) {
3601 if (src->encoding() < 8) {
3602 if (adr.base_needs_rex()) {
3603 if (adr.index_needs_rex()) {
3604 prefix(REX_WXB);
3605 } else {
3606 prefix(REX_WB);
3607 }
3608 } else {
3609 if (adr.index_needs_rex()) {
3610 prefix(REX_WX);
3611 } else {
3612 prefix(REX_W);
3613 }
3614 }
3615 } else {
3616 if (adr.base_needs_rex()) {
3617 if (adr.index_needs_rex()) {
3618 prefix(REX_WRXB);
3619 } else {
3620 prefix(REX_WRB);
3621 }
3622 } else {
3623 if (adr.index_needs_rex()) {
3624 prefix(REX_WRX);
3625 } else {
3626 prefix(REX_WR);
3627 }
3628 }
3629 }
3630 }
3632 void Assembler::prefix(Address adr, XMMRegister reg) {
3633 if (reg->encoding() < 8) {
3634 if (adr.base_needs_rex()) {
3635 if (adr.index_needs_rex()) {
3636 prefix(REX_XB);
3637 } else {
3638 prefix(REX_B);
3639 }
3640 } else {
3641 if (adr.index_needs_rex()) {
3642 prefix(REX_X);
3643 }
3644 }
3645 } else {
3646 if (adr.base_needs_rex()) {
3647 if (adr.index_needs_rex()) {
3648 prefix(REX_RXB);
3649 } else {
3650 prefix(REX_RB);
3651 }
3652 } else {
3653 if (adr.index_needs_rex()) {
3654 prefix(REX_RX);
3655 } else {
3656 prefix(REX_R);
3657 }
3658 }
3659 }
3660 }
3662 void Assembler::adcq(Register dst, int32_t imm32) {
3663 (void) prefixq_and_encode(dst->encoding());
3664 emit_arith(0x81, 0xD0, dst, imm32);
3665 }
3667 void Assembler::adcq(Register dst, Address src) {
3668 InstructionMark im(this);
3669 prefixq(src, dst);
3670 emit_byte(0x13);
3671 emit_operand(dst, src);
3672 }
3674 void Assembler::adcq(Register dst, Register src) {
3675 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3676 emit_arith(0x13, 0xC0, dst, src);
3677 }
3679 void Assembler::addq(Address dst, int32_t imm32) {
3680 InstructionMark im(this);
3681 prefixq(dst);
3682 emit_arith_operand(0x81, rax, dst,imm32);
3683 }
3685 void Assembler::addq(Address dst, Register src) {
3686 InstructionMark im(this);
3687 prefixq(dst, src);
3688 emit_byte(0x01);
3689 emit_operand(src, dst);
3690 }
3692 void Assembler::addq(Register dst, int32_t imm32) {
3693 (void) prefixq_and_encode(dst->encoding());
3694 emit_arith(0x81, 0xC0, dst, imm32);
3695 }
3697 void Assembler::addq(Register dst, Address src) {
3698 InstructionMark im(this);
3699 prefixq(src, dst);
3700 emit_byte(0x03);
3701 emit_operand(dst, src);
3702 }
3704 void Assembler::addq(Register dst, Register src) {
3705 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3706 emit_arith(0x03, 0xC0, dst, src);
3707 }
3709 void Assembler::andq(Register dst, int32_t imm32) {
3710 (void) prefixq_and_encode(dst->encoding());
3711 emit_arith(0x81, 0xE0, dst, imm32);
3712 }
3714 void Assembler::andq(Register dst, Address src) {
3715 InstructionMark im(this);
3716 prefixq(src, dst);
3717 emit_byte(0x23);
3718 emit_operand(dst, src);
3719 }
3721 void Assembler::andq(Register dst, Register src) {
3722 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3723 emit_arith(0x23, 0xC0, dst, src);
3724 }
3726 void Assembler::bsfq(Register dst, Register src) {
3727 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3728 emit_byte(0x0F);
3729 emit_byte(0xBC);
3730 emit_byte(0xC0 | encode);
3731 }
3733 void Assembler::bsrq(Register dst, Register src) {
3734 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
3735 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3736 emit_byte(0x0F);
3737 emit_byte(0xBD);
3738 emit_byte(0xC0 | encode);
3739 }
3741 void Assembler::bswapq(Register reg) {
3742 int encode = prefixq_and_encode(reg->encoding());
3743 emit_byte(0x0F);
3744 emit_byte(0xC8 | encode);
3745 }
3747 void Assembler::cdqq() {
3748 prefix(REX_W);
3749 emit_byte(0x99);
3750 }
3752 void Assembler::clflush(Address adr) {
3753 prefix(adr);
3754 emit_byte(0x0F);
3755 emit_byte(0xAE);
3756 emit_operand(rdi, adr);
3757 }
3759 void Assembler::cmovq(Condition cc, Register dst, Register src) {
3760 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3761 emit_byte(0x0F);
3762 emit_byte(0x40 | cc);
3763 emit_byte(0xC0 | encode);
3764 }
3766 void Assembler::cmovq(Condition cc, Register dst, Address src) {
3767 InstructionMark im(this);
3768 prefixq(src, dst);
3769 emit_byte(0x0F);
3770 emit_byte(0x40 | cc);
3771 emit_operand(dst, src);
3772 }
3774 void Assembler::cmpq(Address dst, int32_t imm32) {
3775 InstructionMark im(this);
3776 prefixq(dst);
3777 emit_byte(0x81);
3778 emit_operand(rdi, dst, 4);
3779 emit_long(imm32);
3780 }
3782 void Assembler::cmpq(Register dst, int32_t imm32) {
3783 (void) prefixq_and_encode(dst->encoding());
3784 emit_arith(0x81, 0xF8, dst, imm32);
3785 }
3787 void Assembler::cmpq(Address dst, Register src) {
3788 InstructionMark im(this);
3789 prefixq(dst, src);
3790 emit_byte(0x3B);
3791 emit_operand(src, dst);
3792 }
3794 void Assembler::cmpq(Register dst, Register src) {
3795 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3796 emit_arith(0x3B, 0xC0, dst, src);
3797 }
3799 void Assembler::cmpq(Register dst, Address src) {
3800 InstructionMark im(this);
3801 prefixq(src, dst);
3802 emit_byte(0x3B);
3803 emit_operand(dst, src);
3804 }
3806 void Assembler::cmpxchgq(Register reg, Address adr) {
3807 InstructionMark im(this);
3808 prefixq(adr, reg);
3809 emit_byte(0x0F);
3810 emit_byte(0xB1);
3811 emit_operand(reg, adr);
3812 }
3814 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
3815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3816 emit_byte(0xF2);
3817 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3818 emit_byte(0x0F);
3819 emit_byte(0x2A);
3820 emit_byte(0xC0 | encode);
3821 }
3823 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
3824 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3825 emit_byte(0xF3);
3826 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3827 emit_byte(0x0F);
3828 emit_byte(0x2A);
3829 emit_byte(0xC0 | encode);
3830 }
3832 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
3833 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3834 emit_byte(0xF2);
3835 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3836 emit_byte(0x0F);
3837 emit_byte(0x2C);
3838 emit_byte(0xC0 | encode);
3839 }
3841 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
3842 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3843 emit_byte(0xF3);
3844 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3845 emit_byte(0x0F);
3846 emit_byte(0x2C);
3847 emit_byte(0xC0 | encode);
3848 }
3850 void Assembler::decl(Register dst) {
3851 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3852 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
3853 int encode = prefix_and_encode(dst->encoding());
3854 emit_byte(0xFF);
3855 emit_byte(0xC8 | encode);
3856 }
3858 void Assembler::decq(Register dst) {
3859 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3860 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3861 int encode = prefixq_and_encode(dst->encoding());
3862 emit_byte(0xFF);
3863 emit_byte(0xC8 | encode);
3864 }
3866 void Assembler::decq(Address dst) {
3867 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3868 InstructionMark im(this);
3869 prefixq(dst);
3870 emit_byte(0xFF);
3871 emit_operand(rcx, dst);
3872 }
3874 void Assembler::fxrstor(Address src) {
3875 prefixq(src);
3876 emit_byte(0x0F);
3877 emit_byte(0xAE);
3878 emit_operand(as_Register(1), src);
3879 }
3881 void Assembler::fxsave(Address dst) {
3882 prefixq(dst);
3883 emit_byte(0x0F);
3884 emit_byte(0xAE);
3885 emit_operand(as_Register(0), dst);
3886 }
3888 void Assembler::idivq(Register src) {
3889 int encode = prefixq_and_encode(src->encoding());
3890 emit_byte(0xF7);
3891 emit_byte(0xF8 | encode);
3892 }
3894 void Assembler::imulq(Register dst, Register src) {
3895 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3896 emit_byte(0x0F);
3897 emit_byte(0xAF);
3898 emit_byte(0xC0 | encode);
3899 }
3901 void Assembler::imulq(Register dst, Register src, int value) {
3902 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3903 if (is8bit(value)) {
3904 emit_byte(0x6B);
3905 emit_byte(0xC0 | encode);
3906 emit_byte(value & 0xFF);
3907 } else {
3908 emit_byte(0x69);
3909 emit_byte(0xC0 | encode);
3910 emit_long(value);
3911 }
3912 }
3914 void Assembler::incl(Register dst) {
3915 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3916 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3917 int encode = prefix_and_encode(dst->encoding());
3918 emit_byte(0xFF);
3919 emit_byte(0xC0 | encode);
3920 }
3922 void Assembler::incq(Register dst) {
3923 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3924 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3925 int encode = prefixq_and_encode(dst->encoding());
3926 emit_byte(0xFF);
3927 emit_byte(0xC0 | encode);
3928 }
3930 void Assembler::incq(Address dst) {
3931 // Don't use it directly. Use MacroAssembler::incrementq() instead.
3932 InstructionMark im(this);
3933 prefixq(dst);
3934 emit_byte(0xFF);
3935 emit_operand(rax, dst);
3936 }
3938 void Assembler::lea(Register dst, Address src) {
3939 leaq(dst, src);
3940 }
3942 void Assembler::leaq(Register dst, Address src) {
3943 InstructionMark im(this);
3944 prefixq(src, dst);
3945 emit_byte(0x8D);
3946 emit_operand(dst, src);
3947 }
3949 void Assembler::mov64(Register dst, int64_t imm64) {
3950 InstructionMark im(this);
3951 int encode = prefixq_and_encode(dst->encoding());
3952 emit_byte(0xB8 | encode);
3953 emit_long64(imm64);
3954 }
3956 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
3957 InstructionMark im(this);
3958 int encode = prefixq_and_encode(dst->encoding());
3959 emit_byte(0xB8 | encode);
3960 emit_data64(imm64, rspec);
3961 }
3963 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3964 InstructionMark im(this);
3965 int encode = prefix_and_encode(dst->encoding());
3966 emit_byte(0xB8 | encode);
3967 emit_data((int)imm32, rspec, narrow_oop_operand);
3968 }
3970 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3971 InstructionMark im(this);
3972 prefix(dst);
3973 emit_byte(0xC7);
3974 emit_operand(rax, dst, 4);
3975 emit_data((int)imm32, rspec, narrow_oop_operand);
3976 }
3978 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3979 InstructionMark im(this);
3980 int encode = prefix_and_encode(src1->encoding());
3981 emit_byte(0x81);
3982 emit_byte(0xF8 | encode);
3983 emit_data((int)imm32, rspec, narrow_oop_operand);
3984 }
3986 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3987 InstructionMark im(this);
3988 prefix(src1);
3989 emit_byte(0x81);
3990 emit_operand(rax, src1, 4);
3991 emit_data((int)imm32, rspec, narrow_oop_operand);
3992 }
3994 void Assembler::lzcntq(Register dst, Register src) {
3995 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
3996 emit_byte(0xF3);
3997 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3998 emit_byte(0x0F);
3999 emit_byte(0xBD);
4000 emit_byte(0xC0 | encode);
4001 }
4003 void Assembler::movdq(XMMRegister dst, Register src) {
4004 // table D-1 says MMX/SSE2
4005 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4006 emit_byte(0x66);
4007 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4008 emit_byte(0x0F);
4009 emit_byte(0x6E);
4010 emit_byte(0xC0 | encode);
4011 }
4013 void Assembler::movdq(Register dst, XMMRegister src) {
4014 // table D-1 says MMX/SSE2
4015 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4016 emit_byte(0x66);
4017 // swap src/dst to get correct prefix
4018 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
4019 emit_byte(0x0F);
4020 emit_byte(0x7E);
4021 emit_byte(0xC0 | encode);
4022 }
4024 void Assembler::movq(Register dst, Register src) {
4025 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4026 emit_byte(0x8B);
4027 emit_byte(0xC0 | encode);
4028 }
4030 void Assembler::movq(Register dst, Address src) {
4031 InstructionMark im(this);
4032 prefixq(src, dst);
4033 emit_byte(0x8B);
4034 emit_operand(dst, src);
4035 }
4037 void Assembler::movq(Address dst, Register src) {
4038 InstructionMark im(this);
4039 prefixq(dst, src);
4040 emit_byte(0x89);
4041 emit_operand(src, dst);
4042 }
4044 void Assembler::movsbq(Register dst, Address src) {
4045 InstructionMark im(this);
4046 prefixq(src, dst);
4047 emit_byte(0x0F);
4048 emit_byte(0xBE);
4049 emit_operand(dst, src);
4050 }
4052 void Assembler::movsbq(Register dst, Register src) {
4053 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4054 emit_byte(0x0F);
4055 emit_byte(0xBE);
4056 emit_byte(0xC0 | encode);
4057 }
4059 void Assembler::movslq(Register dst, int32_t imm32) {
4060 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
4061 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
4062 // as a result we shouldn't use until tested at runtime...
4063 ShouldNotReachHere();
4064 InstructionMark im(this);
4065 int encode = prefixq_and_encode(dst->encoding());
4066 emit_byte(0xC7 | encode);
4067 emit_long(imm32);
4068 }
4070 void Assembler::movslq(Address dst, int32_t imm32) {
4071 assert(is_simm32(imm32), "lost bits");
4072 InstructionMark im(this);
4073 prefixq(dst);
4074 emit_byte(0xC7);
4075 emit_operand(rax, dst, 4);
4076 emit_long(imm32);
4077 }
4079 void Assembler::movslq(Register dst, Address src) {
4080 InstructionMark im(this);
4081 prefixq(src, dst);
4082 emit_byte(0x63);
4083 emit_operand(dst, src);
4084 }
4086 void Assembler::movslq(Register dst, Register src) {
4087 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4088 emit_byte(0x63);
4089 emit_byte(0xC0 | encode);
4090 }
4092 void Assembler::movswq(Register dst, Address src) {
4093 InstructionMark im(this);
4094 prefixq(src, dst);
4095 emit_byte(0x0F);
4096 emit_byte(0xBF);
4097 emit_operand(dst, src);
4098 }
4100 void Assembler::movswq(Register dst, Register src) {
4101 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4102 emit_byte(0x0F);
4103 emit_byte(0xBF);
4104 emit_byte(0xC0 | encode);
4105 }
4107 void Assembler::movzbq(Register dst, Address src) {
4108 InstructionMark im(this);
4109 prefixq(src, dst);
4110 emit_byte(0x0F);
4111 emit_byte(0xB6);
4112 emit_operand(dst, src);
4113 }
4115 void Assembler::movzbq(Register dst, Register src) {
4116 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4117 emit_byte(0x0F);
4118 emit_byte(0xB6);
4119 emit_byte(0xC0 | encode);
4120 }
4122 void Assembler::movzwq(Register dst, Address src) {
4123 InstructionMark im(this);
4124 prefixq(src, dst);
4125 emit_byte(0x0F);
4126 emit_byte(0xB7);
4127 emit_operand(dst, src);
4128 }
4130 void Assembler::movzwq(Register dst, Register src) {
4131 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4132 emit_byte(0x0F);
4133 emit_byte(0xB7);
4134 emit_byte(0xC0 | encode);
4135 }
4137 void Assembler::negq(Register dst) {
4138 int encode = prefixq_and_encode(dst->encoding());
4139 emit_byte(0xF7);
4140 emit_byte(0xD8 | encode);
4141 }
4143 void Assembler::notq(Register dst) {
4144 int encode = prefixq_and_encode(dst->encoding());
4145 emit_byte(0xF7);
4146 emit_byte(0xD0 | encode);
4147 }
4149 void Assembler::orq(Address dst, int32_t imm32) {
4150 InstructionMark im(this);
4151 prefixq(dst);
4152 emit_byte(0x81);
4153 emit_operand(rcx, dst, 4);
4154 emit_long(imm32);
4155 }
4157 void Assembler::orq(Register dst, int32_t imm32) {
4158 (void) prefixq_and_encode(dst->encoding());
4159 emit_arith(0x81, 0xC8, dst, imm32);
4160 }
4162 void Assembler::orq(Register dst, Address src) {
4163 InstructionMark im(this);
4164 prefixq(src, dst);
4165 emit_byte(0x0B);
4166 emit_operand(dst, src);
4167 }
4169 void Assembler::orq(Register dst, Register src) {
4170 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4171 emit_arith(0x0B, 0xC0, dst, src);
4172 }
4174 void Assembler::popa() { // 64bit
4175 movq(r15, Address(rsp, 0));
4176 movq(r14, Address(rsp, wordSize));
4177 movq(r13, Address(rsp, 2 * wordSize));
4178 movq(r12, Address(rsp, 3 * wordSize));
4179 movq(r11, Address(rsp, 4 * wordSize));
4180 movq(r10, Address(rsp, 5 * wordSize));
4181 movq(r9, Address(rsp, 6 * wordSize));
4182 movq(r8, Address(rsp, 7 * wordSize));
4183 movq(rdi, Address(rsp, 8 * wordSize));
4184 movq(rsi, Address(rsp, 9 * wordSize));
4185 movq(rbp, Address(rsp, 10 * wordSize));
4186 // skip rsp
4187 movq(rbx, Address(rsp, 12 * wordSize));
4188 movq(rdx, Address(rsp, 13 * wordSize));
4189 movq(rcx, Address(rsp, 14 * wordSize));
4190 movq(rax, Address(rsp, 15 * wordSize));
4192 addq(rsp, 16 * wordSize);
4193 }
4195 void Assembler::popcntq(Register dst, Address src) {
4196 assert(VM_Version::supports_popcnt(), "must support");
4197 InstructionMark im(this);
4198 emit_byte(0xF3);
4199 prefixq(src, dst);
4200 emit_byte(0x0F);
4201 emit_byte(0xB8);
4202 emit_operand(dst, src);
4203 }
4205 void Assembler::popcntq(Register dst, Register src) {
4206 assert(VM_Version::supports_popcnt(), "must support");
4207 emit_byte(0xF3);
4208 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4209 emit_byte(0x0F);
4210 emit_byte(0xB8);
4211 emit_byte(0xC0 | encode);
4212 }
4214 void Assembler::popq(Address dst) {
4215 InstructionMark im(this);
4216 prefixq(dst);
4217 emit_byte(0x8F);
4218 emit_operand(rax, dst);
4219 }
4221 void Assembler::pusha() { // 64bit
4222 // we have to store original rsp. ABI says that 128 bytes
4223 // below rsp are local scratch.
4224 movq(Address(rsp, -5 * wordSize), rsp);
4226 subq(rsp, 16 * wordSize);
4228 movq(Address(rsp, 15 * wordSize), rax);
4229 movq(Address(rsp, 14 * wordSize), rcx);
4230 movq(Address(rsp, 13 * wordSize), rdx);
4231 movq(Address(rsp, 12 * wordSize), rbx);
4232 // skip rsp
4233 movq(Address(rsp, 10 * wordSize), rbp);
4234 movq(Address(rsp, 9 * wordSize), rsi);
4235 movq(Address(rsp, 8 * wordSize), rdi);
4236 movq(Address(rsp, 7 * wordSize), r8);
4237 movq(Address(rsp, 6 * wordSize), r9);
4238 movq(Address(rsp, 5 * wordSize), r10);
4239 movq(Address(rsp, 4 * wordSize), r11);
4240 movq(Address(rsp, 3 * wordSize), r12);
4241 movq(Address(rsp, 2 * wordSize), r13);
4242 movq(Address(rsp, wordSize), r14);
4243 movq(Address(rsp, 0), r15);
4244 }
4246 void Assembler::pushq(Address src) {
4247 InstructionMark im(this);
4248 prefixq(src);
4249 emit_byte(0xFF);
4250 emit_operand(rsi, src);
4251 }
4253 void Assembler::rclq(Register dst, int imm8) {
4254 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4255 int encode = prefixq_and_encode(dst->encoding());
4256 if (imm8 == 1) {
4257 emit_byte(0xD1);
4258 emit_byte(0xD0 | encode);
4259 } else {
4260 emit_byte(0xC1);
4261 emit_byte(0xD0 | encode);
4262 emit_byte(imm8);
4263 }
4264 }
4265 void Assembler::sarq(Register dst, int imm8) {
4266 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4267 int encode = prefixq_and_encode(dst->encoding());
4268 if (imm8 == 1) {
4269 emit_byte(0xD1);
4270 emit_byte(0xF8 | encode);
4271 } else {
4272 emit_byte(0xC1);
4273 emit_byte(0xF8 | encode);
4274 emit_byte(imm8);
4275 }
4276 }
4278 void Assembler::sarq(Register dst) {
4279 int encode = prefixq_and_encode(dst->encoding());
4280 emit_byte(0xD3);
4281 emit_byte(0xF8 | encode);
4282 }
4283 void Assembler::sbbq(Address dst, int32_t imm32) {
4284 InstructionMark im(this);
4285 prefixq(dst);
4286 emit_arith_operand(0x81, rbx, dst, imm32);
4287 }
4289 void Assembler::sbbq(Register dst, int32_t imm32) {
4290 (void) prefixq_and_encode(dst->encoding());
4291 emit_arith(0x81, 0xD8, dst, imm32);
4292 }
4294 void Assembler::sbbq(Register dst, Address src) {
4295 InstructionMark im(this);
4296 prefixq(src, dst);
4297 emit_byte(0x1B);
4298 emit_operand(dst, src);
4299 }
4301 void Assembler::sbbq(Register dst, Register src) {
4302 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4303 emit_arith(0x1B, 0xC0, dst, src);
4304 }
4306 void Assembler::shlq(Register dst, int imm8) {
4307 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4308 int encode = prefixq_and_encode(dst->encoding());
4309 if (imm8 == 1) {
4310 emit_byte(0xD1);
4311 emit_byte(0xE0 | encode);
4312 } else {
4313 emit_byte(0xC1);
4314 emit_byte(0xE0 | encode);
4315 emit_byte(imm8);
4316 }
4317 }
4319 void Assembler::shlq(Register dst) {
4320 int encode = prefixq_and_encode(dst->encoding());
4321 emit_byte(0xD3);
4322 emit_byte(0xE0 | encode);
4323 }
4325 void Assembler::shrq(Register dst, int imm8) {
4326 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4327 int encode = prefixq_and_encode(dst->encoding());
4328 emit_byte(0xC1);
4329 emit_byte(0xE8 | encode);
4330 emit_byte(imm8);
4331 }
4333 void Assembler::shrq(Register dst) {
4334 int encode = prefixq_and_encode(dst->encoding());
4335 emit_byte(0xD3);
4336 emit_byte(0xE8 | encode);
4337 }
4339 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4340 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4341 InstructionMark im(this);
4342 emit_byte(0xF2);
4343 prefix(src, dst);
4344 emit_byte(0x0F);
4345 emit_byte(0x51);
4346 emit_operand(dst, src);
4347 }
4349 void Assembler::subq(Address dst, int32_t imm32) {
4350 InstructionMark im(this);
4351 prefixq(dst);
4352 if (is8bit(imm32)) {
4353 emit_byte(0x83);
4354 emit_operand(rbp, dst, 1);
4355 emit_byte(imm32 & 0xFF);
4356 } else {
4357 emit_byte(0x81);
4358 emit_operand(rbp, dst, 4);
4359 emit_long(imm32);
4360 }
4361 }
4363 void Assembler::subq(Register dst, int32_t imm32) {
4364 (void) prefixq_and_encode(dst->encoding());
4365 emit_arith(0x81, 0xE8, dst, imm32);
4366 }
4368 void Assembler::subq(Address dst, Register src) {
4369 InstructionMark im(this);
4370 prefixq(dst, src);
4371 emit_byte(0x29);
4372 emit_operand(src, dst);
4373 }
4375 void Assembler::subq(Register dst, Address src) {
4376 InstructionMark im(this);
4377 prefixq(src, dst);
4378 emit_byte(0x2B);
4379 emit_operand(dst, src);
4380 }
4382 void Assembler::subq(Register dst, Register src) {
4383 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4384 emit_arith(0x2B, 0xC0, dst, src);
4385 }
4387 void Assembler::testq(Register dst, int32_t imm32) {
4388 // not using emit_arith because test
4389 // doesn't support sign-extension of
4390 // 8bit operands
4391 int encode = dst->encoding();
4392 if (encode == 0) {
4393 prefix(REX_W);
4394 emit_byte(0xA9);
4395 } else {
4396 encode = prefixq_and_encode(encode);
4397 emit_byte(0xF7);
4398 emit_byte(0xC0 | encode);
4399 }
4400 emit_long(imm32);
4401 }
4403 void Assembler::testq(Register dst, Register src) {
4404 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4405 emit_arith(0x85, 0xC0, dst, src);
4406 }
4408 void Assembler::xaddq(Address dst, Register src) {
4409 InstructionMark im(this);
4410 prefixq(dst, src);
4411 emit_byte(0x0F);
4412 emit_byte(0xC1);
4413 emit_operand(src, dst);
4414 }
4416 void Assembler::xchgq(Register dst, Address src) {
4417 InstructionMark im(this);
4418 prefixq(src, dst);
4419 emit_byte(0x87);
4420 emit_operand(dst, src);
4421 }
4423 void Assembler::xchgq(Register dst, Register src) {
4424 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4425 emit_byte(0x87);
4426 emit_byte(0xc0 | encode);
4427 }
4429 void Assembler::xorq(Register dst, Register src) {
4430 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4431 emit_arith(0x33, 0xC0, dst, src);
4432 }
4434 void Assembler::xorq(Register dst, Address src) {
4435 InstructionMark im(this);
4436 prefixq(src, dst);
4437 emit_byte(0x33);
4438 emit_operand(dst, src);
4439 }
4441 #endif // !LP64
4443 static Assembler::Condition reverse[] = {
4444 Assembler::noOverflow /* overflow = 0x0 */ ,
4445 Assembler::overflow /* noOverflow = 0x1 */ ,
4446 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
4447 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
4448 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
4449 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
4450 Assembler::above /* belowEqual = 0x6 */ ,
4451 Assembler::belowEqual /* above = 0x7 */ ,
4452 Assembler::positive /* negative = 0x8 */ ,
4453 Assembler::negative /* positive = 0x9 */ ,
4454 Assembler::noParity /* parity = 0xa */ ,
4455 Assembler::parity /* noParity = 0xb */ ,
4456 Assembler::greaterEqual /* less = 0xc */ ,
4457 Assembler::less /* greaterEqual = 0xd */ ,
4458 Assembler::greater /* lessEqual = 0xe */ ,
4459 Assembler::lessEqual /* greater = 0xf, */
4461 };
4464 // Implementation of MacroAssembler
4466 // First all the versions that have distinct versions depending on 32/64 bit
4467 // Unless the difference is trivial (1 line or so).
4469 #ifndef _LP64
4471 // 32bit versions
4473 Address MacroAssembler::as_Address(AddressLiteral adr) {
4474 return Address(adr.target(), adr.rspec());
4475 }
4477 Address MacroAssembler::as_Address(ArrayAddress adr) {
4478 return Address::make_array(adr);
4479 }
4481 int MacroAssembler::biased_locking_enter(Register lock_reg,
4482 Register obj_reg,
4483 Register swap_reg,
4484 Register tmp_reg,
4485 bool swap_reg_contains_mark,
4486 Label& done,
4487 Label* slow_case,
4488 BiasedLockingCounters* counters) {
4489 assert(UseBiasedLocking, "why call this otherwise?");
4490 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4491 assert_different_registers(lock_reg, obj_reg, swap_reg);
4493 if (PrintBiasedLockingStatistics && counters == NULL)
4494 counters = BiasedLocking::counters();
4496 bool need_tmp_reg = false;
4497 if (tmp_reg == noreg) {
4498 need_tmp_reg = true;
4499 tmp_reg = lock_reg;
4500 } else {
4501 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4502 }
4503 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4504 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4505 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4506 Address saved_mark_addr(lock_reg, 0);
4508 // Biased locking
4509 // See whether the lock is currently biased toward our thread and
4510 // whether the epoch is still valid
4511 // Note that the runtime guarantees sufficient alignment of JavaThread
4512 // pointers to allow age to be placed into low bits
4513 // First check to see whether biasing is even enabled for this object
4514 Label cas_label;
4515 int null_check_offset = -1;
4516 if (!swap_reg_contains_mark) {
4517 null_check_offset = offset();
4518 movl(swap_reg, mark_addr);
4519 }
4520 if (need_tmp_reg) {
4521 push(tmp_reg);
4522 }
4523 movl(tmp_reg, swap_reg);
4524 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4525 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4526 if (need_tmp_reg) {
4527 pop(tmp_reg);
4528 }
4529 jcc(Assembler::notEqual, cas_label);
4530 // The bias pattern is present in the object's header. Need to check
4531 // whether the bias owner and the epoch are both still current.
4532 // Note that because there is no current thread register on x86 we
4533 // need to store off the mark word we read out of the object to
4534 // avoid reloading it and needing to recheck invariants below. This
4535 // store is unfortunate but it makes the overall code shorter and
4536 // simpler.
4537 movl(saved_mark_addr, swap_reg);
4538 if (need_tmp_reg) {
4539 push(tmp_reg);
4540 }
4541 get_thread(tmp_reg);
4542 xorl(swap_reg, tmp_reg);
4543 if (swap_reg_contains_mark) {
4544 null_check_offset = offset();
4545 }
4546 movl(tmp_reg, klass_addr);
4547 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4548 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4549 if (need_tmp_reg) {
4550 pop(tmp_reg);
4551 }
4552 if (counters != NULL) {
4553 cond_inc32(Assembler::zero,
4554 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4555 }
4556 jcc(Assembler::equal, done);
4558 Label try_revoke_bias;
4559 Label try_rebias;
4561 // At this point we know that the header has the bias pattern and
4562 // that we are not the bias owner in the current epoch. We need to
4563 // figure out more details about the state of the header in order to
4564 // know what operations can be legally performed on the object's
4565 // header.
4567 // If the low three bits in the xor result aren't clear, that means
4568 // the prototype header is no longer biased and we have to revoke
4569 // the bias on this object.
4570 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4571 jcc(Assembler::notZero, try_revoke_bias);
4573 // Biasing is still enabled for this data type. See whether the
4574 // epoch of the current bias is still valid, meaning that the epoch
4575 // bits of the mark word are equal to the epoch bits of the
4576 // prototype header. (Note that the prototype header's epoch bits
4577 // only change at a safepoint.) If not, attempt to rebias the object
4578 // toward the current thread. Note that we must be absolutely sure
4579 // that the current epoch is invalid in order to do this because
4580 // otherwise the manipulations it performs on the mark word are
4581 // illegal.
4582 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4583 jcc(Assembler::notZero, try_rebias);
4585 // The epoch of the current bias is still valid but we know nothing
4586 // about the owner; it might be set or it might be clear. Try to
4587 // acquire the bias of the object using an atomic operation. If this
4588 // fails we will go in to the runtime to revoke the object's bias.
4589 // Note that we first construct the presumed unbiased header so we
4590 // don't accidentally blow away another thread's valid bias.
4591 movl(swap_reg, saved_mark_addr);
4592 andl(swap_reg,
4593 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
4594 if (need_tmp_reg) {
4595 push(tmp_reg);
4596 }
4597 get_thread(tmp_reg);
4598 orl(tmp_reg, swap_reg);
4599 if (os::is_MP()) {
4600 lock();
4601 }
4602 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4603 if (need_tmp_reg) {
4604 pop(tmp_reg);
4605 }
4606 // If the biasing toward our thread failed, this means that
4607 // another thread succeeded in biasing it toward itself and we
4608 // need to revoke that bias. The revocation will occur in the
4609 // interpreter runtime in the slow case.
4610 if (counters != NULL) {
4611 cond_inc32(Assembler::zero,
4612 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
4613 }
4614 if (slow_case != NULL) {
4615 jcc(Assembler::notZero, *slow_case);
4616 }
4617 jmp(done);
4619 bind(try_rebias);
4620 // At this point we know the epoch has expired, meaning that the
4621 // current "bias owner", if any, is actually invalid. Under these
4622 // circumstances _only_, we are allowed to use the current header's
4623 // value as the comparison value when doing the cas to acquire the
4624 // bias in the current epoch. In other words, we allow transfer of
4625 // the bias from one thread to another directly in this situation.
4626 //
4627 // FIXME: due to a lack of registers we currently blow away the age
4628 // bits in this situation. Should attempt to preserve them.
4629 if (need_tmp_reg) {
4630 push(tmp_reg);
4631 }
4632 get_thread(tmp_reg);
4633 movl(swap_reg, klass_addr);
4634 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4635 movl(swap_reg, saved_mark_addr);
4636 if (os::is_MP()) {
4637 lock();
4638 }
4639 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4640 if (need_tmp_reg) {
4641 pop(tmp_reg);
4642 }
4643 // If the biasing toward our thread failed, then another thread
4644 // succeeded in biasing it toward itself and we need to revoke that
4645 // bias. The revocation will occur in the runtime in the slow case.
4646 if (counters != NULL) {
4647 cond_inc32(Assembler::zero,
4648 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
4649 }
4650 if (slow_case != NULL) {
4651 jcc(Assembler::notZero, *slow_case);
4652 }
4653 jmp(done);
4655 bind(try_revoke_bias);
4656 // The prototype mark in the klass doesn't have the bias bit set any
4657 // more, indicating that objects of this data type are not supposed
4658 // to be biased any more. We are going to try to reset the mark of
4659 // this object to the prototype value and fall through to the
4660 // CAS-based locking scheme. Note that if our CAS fails, it means
4661 // that another thread raced us for the privilege of revoking the
4662 // bias of this particular object, so it's okay to continue in the
4663 // normal locking code.
4664 //
4665 // FIXME: due to a lack of registers we currently blow away the age
4666 // bits in this situation. Should attempt to preserve them.
4667 movl(swap_reg, saved_mark_addr);
4668 if (need_tmp_reg) {
4669 push(tmp_reg);
4670 }
4671 movl(tmp_reg, klass_addr);
4672 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4673 if (os::is_MP()) {
4674 lock();
4675 }
4676 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4677 if (need_tmp_reg) {
4678 pop(tmp_reg);
4679 }
4680 // Fall through to the normal CAS-based lock, because no matter what
4681 // the result of the above CAS, some thread must have succeeded in
4682 // removing the bias bit from the object's header.
4683 if (counters != NULL) {
4684 cond_inc32(Assembler::zero,
4685 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
4686 }
4688 bind(cas_label);
4690 return null_check_offset;
4691 }
4692 void MacroAssembler::call_VM_leaf_base(address entry_point,
4693 int number_of_arguments) {
4694 call(RuntimeAddress(entry_point));
4695 increment(rsp, number_of_arguments * wordSize);
4696 }
4698 void MacroAssembler::cmpoop(Address src1, jobject obj) {
4699 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4700 }
4702 void MacroAssembler::cmpoop(Register src1, jobject obj) {
4703 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4704 }
4706 void MacroAssembler::extend_sign(Register hi, Register lo) {
4707 // According to Intel Doc. AP-526, "Integer Divide", p.18.
4708 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
4709 cdql();
4710 } else {
4711 movl(hi, lo);
4712 sarl(hi, 31);
4713 }
4714 }
4716 void MacroAssembler::fat_nop() {
4717 // A 5 byte nop that is safe for patching (see patch_verified_entry)
4718 emit_byte(0x26); // es:
4719 emit_byte(0x2e); // cs:
4720 emit_byte(0x64); // fs:
4721 emit_byte(0x65); // gs:
4722 emit_byte(0x90);
4723 }
4725 void MacroAssembler::jC2(Register tmp, Label& L) {
4726 // set parity bit if FPU flag C2 is set (via rax)
4727 save_rax(tmp);
4728 fwait(); fnstsw_ax();
4729 sahf();
4730 restore_rax(tmp);
4731 // branch
4732 jcc(Assembler::parity, L);
4733 }
4735 void MacroAssembler::jnC2(Register tmp, Label& L) {
4736 // set parity bit if FPU flag C2 is set (via rax)
4737 save_rax(tmp);
4738 fwait(); fnstsw_ax();
4739 sahf();
4740 restore_rax(tmp);
4741 // branch
4742 jcc(Assembler::noParity, L);
4743 }
4745 // 32bit can do a case table jump in one instruction but we no longer allow the base
4746 // to be installed in the Address class
4747 void MacroAssembler::jump(ArrayAddress entry) {
4748 jmp(as_Address(entry));
4749 }
4751 // Note: y_lo will be destroyed
4752 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
4753 // Long compare for Java (semantics as described in JVM spec.)
4754 Label high, low, done;
4756 cmpl(x_hi, y_hi);
4757 jcc(Assembler::less, low);
4758 jcc(Assembler::greater, high);
4759 // x_hi is the return register
4760 xorl(x_hi, x_hi);
4761 cmpl(x_lo, y_lo);
4762 jcc(Assembler::below, low);
4763 jcc(Assembler::equal, done);
4765 bind(high);
4766 xorl(x_hi, x_hi);
4767 increment(x_hi);
4768 jmp(done);
4770 bind(low);
4771 xorl(x_hi, x_hi);
4772 decrementl(x_hi);
4774 bind(done);
4775 }
4777 void MacroAssembler::lea(Register dst, AddressLiteral src) {
4778 mov_literal32(dst, (int32_t)src.target(), src.rspec());
4779 }
4781 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
4782 // leal(dst, as_Address(adr));
4783 // see note in movl as to why we must use a move
4784 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
4785 }
4787 void MacroAssembler::leave() {
4788 mov(rsp, rbp);
4789 pop(rbp);
4790 }
4792 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
4793 // Multiplication of two Java long values stored on the stack
4794 // as illustrated below. Result is in rdx:rax.
4795 //
4796 // rsp ---> [ ?? ] \ \
4797 // .... | y_rsp_offset |
4798 // [ y_lo ] / (in bytes) | x_rsp_offset
4799 // [ y_hi ] | (in bytes)
4800 // .... |
4801 // [ x_lo ] /
4802 // [ x_hi ]
4803 // ....
4804 //
4805 // Basic idea: lo(result) = lo(x_lo * y_lo)
4806 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
4807 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
4808 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
4809 Label quick;
4810 // load x_hi, y_hi and check if quick
4811 // multiplication is possible
4812 movl(rbx, x_hi);
4813 movl(rcx, y_hi);
4814 movl(rax, rbx);
4815 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
4816 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
4817 // do full multiplication
4818 // 1st step
4819 mull(y_lo); // x_hi * y_lo
4820 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
4821 // 2nd step
4822 movl(rax, x_lo);
4823 mull(rcx); // x_lo * y_hi
4824 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
4825 // 3rd step
4826 bind(quick); // note: rbx, = 0 if quick multiply!
4827 movl(rax, x_lo);
4828 mull(y_lo); // x_lo * y_lo
4829 addl(rdx, rbx); // correct hi(x_lo * y_lo)
4830 }
4832 void MacroAssembler::lneg(Register hi, Register lo) {
4833 negl(lo);
4834 adcl(hi, 0);
4835 negl(hi);
4836 }
4838 void MacroAssembler::lshl(Register hi, Register lo) {
4839 // Java shift left long support (semantics as described in JVM spec., p.305)
4840 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
4841 // shift value is in rcx !
4842 assert(hi != rcx, "must not use rcx");
4843 assert(lo != rcx, "must not use rcx");
4844 const Register s = rcx; // shift count
4845 const int n = BitsPerWord;
4846 Label L;
4847 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4848 cmpl(s, n); // if (s < n)
4849 jcc(Assembler::less, L); // else (s >= n)
4850 movl(hi, lo); // x := x << n
4851 xorl(lo, lo);
4852 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4853 bind(L); // s (mod n) < n
4854 shldl(hi, lo); // x := x << s
4855 shll(lo);
4856 }
4859 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
4860 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
4861 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
4862 assert(hi != rcx, "must not use rcx");
4863 assert(lo != rcx, "must not use rcx");
4864 const Register s = rcx; // shift count
4865 const int n = BitsPerWord;
4866 Label L;
4867 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4868 cmpl(s, n); // if (s < n)
4869 jcc(Assembler::less, L); // else (s >= n)
4870 movl(lo, hi); // x := x >> n
4871 if (sign_extension) sarl(hi, 31);
4872 else xorl(hi, hi);
4873 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4874 bind(L); // s (mod n) < n
4875 shrdl(lo, hi); // x := x >> s
4876 if (sign_extension) sarl(hi);
4877 else shrl(hi);
4878 }
4880 void MacroAssembler::movoop(Register dst, jobject obj) {
4881 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4882 }
4884 void MacroAssembler::movoop(Address dst, jobject obj) {
4885 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4886 }
4888 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
4889 if (src.is_lval()) {
4890 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
4891 } else {
4892 movl(dst, as_Address(src));
4893 }
4894 }
4896 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
4897 movl(as_Address(dst), src);
4898 }
4900 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
4901 movl(dst, as_Address(src));
4902 }
4904 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
4905 void MacroAssembler::movptr(Address dst, intptr_t src) {
4906 movl(dst, src);
4907 }
4910 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
4911 movsd(dst, as_Address(src));
4912 }
4914 void MacroAssembler::pop_callee_saved_registers() {
4915 pop(rcx);
4916 pop(rdx);
4917 pop(rdi);
4918 pop(rsi);
4919 }
4921 void MacroAssembler::pop_fTOS() {
4922 fld_d(Address(rsp, 0));
4923 addl(rsp, 2 * wordSize);
4924 }
4926 void MacroAssembler::push_callee_saved_registers() {
4927 push(rsi);
4928 push(rdi);
4929 push(rdx);
4930 push(rcx);
4931 }
4933 void MacroAssembler::push_fTOS() {
4934 subl(rsp, 2 * wordSize);
4935 fstp_d(Address(rsp, 0));
4936 }
4939 void MacroAssembler::pushoop(jobject obj) {
4940 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
4941 }
4944 void MacroAssembler::pushptr(AddressLiteral src) {
4945 if (src.is_lval()) {
4946 push_literal32((int32_t)src.target(), src.rspec());
4947 } else {
4948 pushl(as_Address(src));
4949 }
4950 }
4952 void MacroAssembler::set_word_if_not_zero(Register dst) {
4953 xorl(dst, dst);
4954 set_byte_if_not_zero(dst);
4955 }
4957 static void pass_arg0(MacroAssembler* masm, Register arg) {
4958 masm->push(arg);
4959 }
4961 static void pass_arg1(MacroAssembler* masm, Register arg) {
4962 masm->push(arg);
4963 }
4965 static void pass_arg2(MacroAssembler* masm, Register arg) {
4966 masm->push(arg);
4967 }
4969 static void pass_arg3(MacroAssembler* masm, Register arg) {
4970 masm->push(arg);
4971 }
4973 #ifndef PRODUCT
4974 extern "C" void findpc(intptr_t x);
4975 #endif
4977 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
4978 // In order to get locks to work, we need to fake a in_VM state
4979 JavaThread* thread = JavaThread::current();
4980 JavaThreadState saved_state = thread->thread_state();
4981 thread->set_thread_state(_thread_in_vm);
4982 if (ShowMessageBoxOnError) {
4983 JavaThread* thread = JavaThread::current();
4984 JavaThreadState saved_state = thread->thread_state();
4985 thread->set_thread_state(_thread_in_vm);
4986 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
4987 ttyLocker ttyl;
4988 BytecodeCounter::print();
4989 }
4990 // To see where a verify_oop failed, get $ebx+40/X for this frame.
4991 // This is the value of eip which points to where verify_oop will return.
4992 if (os::message_box(msg, "Execution stopped, print registers?")) {
4993 ttyLocker ttyl;
4994 tty->print_cr("eip = 0x%08x", eip);
4995 #ifndef PRODUCT
4996 if ((WizardMode || Verbose) && PrintMiscellaneous) {
4997 tty->cr();
4998 findpc(eip);
4999 tty->cr();
5000 }
5001 #endif
5002 tty->print_cr("rax = 0x%08x", rax);
5003 tty->print_cr("rbx = 0x%08x", rbx);
5004 tty->print_cr("rcx = 0x%08x", rcx);
5005 tty->print_cr("rdx = 0x%08x", rdx);
5006 tty->print_cr("rdi = 0x%08x", rdi);
5007 tty->print_cr("rsi = 0x%08x", rsi);
5008 tty->print_cr("rbp = 0x%08x", rbp);
5009 tty->print_cr("rsp = 0x%08x", rsp);
5010 BREAKPOINT;
5011 assert(false, "start up GDB");
5012 }
5013 } else {
5014 ttyLocker ttyl;
5015 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
5016 assert(false, "DEBUG MESSAGE");
5017 }
5018 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5019 }
5021 void MacroAssembler::stop(const char* msg) {
5022 ExternalAddress message((address)msg);
5023 // push address of message
5024 pushptr(message.addr());
5025 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5026 pusha(); // push registers
5027 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
5028 hlt();
5029 }
5031 void MacroAssembler::warn(const char* msg) {
5032 push_CPU_state();
5034 ExternalAddress message((address) msg);
5035 // push address of message
5036 pushptr(message.addr());
5038 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
5039 addl(rsp, wordSize); // discard argument
5040 pop_CPU_state();
5041 }
5043 #else // _LP64
5045 // 64 bit versions
5047 Address MacroAssembler::as_Address(AddressLiteral adr) {
5048 // amd64 always does this as a pc-rel
5049 // we can be absolute or disp based on the instruction type
5050 // jmp/call are displacements others are absolute
5051 assert(!adr.is_lval(), "must be rval");
5052 assert(reachable(adr), "must be");
5053 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
5055 }
5057 Address MacroAssembler::as_Address(ArrayAddress adr) {
5058 AddressLiteral base = adr.base();
5059 lea(rscratch1, base);
5060 Address index = adr.index();
5061 assert(index._disp == 0, "must not have disp"); // maybe it can?
5062 Address array(rscratch1, index._index, index._scale, index._disp);
5063 return array;
5064 }
5066 int MacroAssembler::biased_locking_enter(Register lock_reg,
5067 Register obj_reg,
5068 Register swap_reg,
5069 Register tmp_reg,
5070 bool swap_reg_contains_mark,
5071 Label& done,
5072 Label* slow_case,
5073 BiasedLockingCounters* counters) {
5074 assert(UseBiasedLocking, "why call this otherwise?");
5075 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
5076 assert(tmp_reg != noreg, "tmp_reg must be supplied");
5077 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5078 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5079 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5080 Address saved_mark_addr(lock_reg, 0);
5082 if (PrintBiasedLockingStatistics && counters == NULL)
5083 counters = BiasedLocking::counters();
5085 // Biased locking
5086 // See whether the lock is currently biased toward our thread and
5087 // whether the epoch is still valid
5088 // Note that the runtime guarantees sufficient alignment of JavaThread
5089 // pointers to allow age to be placed into low bits
5090 // First check to see whether biasing is even enabled for this object
5091 Label cas_label;
5092 int null_check_offset = -1;
5093 if (!swap_reg_contains_mark) {
5094 null_check_offset = offset();
5095 movq(swap_reg, mark_addr);
5096 }
5097 movq(tmp_reg, swap_reg);
5098 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5099 cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
5100 jcc(Assembler::notEqual, cas_label);
5101 // The bias pattern is present in the object's header. Need to check
5102 // whether the bias owner and the epoch are both still current.
5103 load_prototype_header(tmp_reg, obj_reg);
5104 orq(tmp_reg, r15_thread);
5105 xorq(tmp_reg, swap_reg);
5106 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
5107 if (counters != NULL) {
5108 cond_inc32(Assembler::zero,
5109 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5110 }
5111 jcc(Assembler::equal, done);
5113 Label try_revoke_bias;
5114 Label try_rebias;
5116 // At this point we know that the header has the bias pattern and
5117 // that we are not the bias owner in the current epoch. We need to
5118 // figure out more details about the state of the header in order to
5119 // know what operations can be legally performed on the object's
5120 // header.
5122 // If the low three bits in the xor result aren't clear, that means
5123 // the prototype header is no longer biased and we have to revoke
5124 // the bias on this object.
5125 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5126 jcc(Assembler::notZero, try_revoke_bias);
5128 // Biasing is still enabled for this data type. See whether the
5129 // epoch of the current bias is still valid, meaning that the epoch
5130 // bits of the mark word are equal to the epoch bits of the
5131 // prototype header. (Note that the prototype header's epoch bits
5132 // only change at a safepoint.) If not, attempt to rebias the object
5133 // toward the current thread. Note that we must be absolutely sure
5134 // that the current epoch is invalid in order to do this because
5135 // otherwise the manipulations it performs on the mark word are
5136 // illegal.
5137 testq(tmp_reg, markOopDesc::epoch_mask_in_place);
5138 jcc(Assembler::notZero, try_rebias);
5140 // The epoch of the current bias is still valid but we know nothing
5141 // about the owner; it might be set or it might be clear. Try to
5142 // acquire the bias of the object using an atomic operation. If this
5143 // fails we will go in to the runtime to revoke the object's bias.
5144 // Note that we first construct the presumed unbiased header so we
5145 // don't accidentally blow away another thread's valid bias.
5146 andq(swap_reg,
5147 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5148 movq(tmp_reg, swap_reg);
5149 orq(tmp_reg, r15_thread);
5150 if (os::is_MP()) {
5151 lock();
5152 }
5153 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5154 // If the biasing toward our thread failed, this means that
5155 // another thread succeeded in biasing it toward itself and we
5156 // need to revoke that bias. The revocation will occur in the
5157 // interpreter runtime in the slow case.
5158 if (counters != NULL) {
5159 cond_inc32(Assembler::zero,
5160 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5161 }
5162 if (slow_case != NULL) {
5163 jcc(Assembler::notZero, *slow_case);
5164 }
5165 jmp(done);
5167 bind(try_rebias);
5168 // At this point we know the epoch has expired, meaning that the
5169 // current "bias owner", if any, is actually invalid. Under these
5170 // circumstances _only_, we are allowed to use the current header's
5171 // value as the comparison value when doing the cas to acquire the
5172 // bias in the current epoch. In other words, we allow transfer of
5173 // the bias from one thread to another directly in this situation.
5174 //
5175 // FIXME: due to a lack of registers we currently blow away the age
5176 // bits in this situation. Should attempt to preserve them.
5177 load_prototype_header(tmp_reg, obj_reg);
5178 orq(tmp_reg, r15_thread);
5179 if (os::is_MP()) {
5180 lock();
5181 }
5182 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5183 // If the biasing toward our thread failed, then another thread
5184 // succeeded in biasing it toward itself and we need to revoke that
5185 // bias. The revocation will occur in the runtime in the slow case.
5186 if (counters != NULL) {
5187 cond_inc32(Assembler::zero,
5188 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
5189 }
5190 if (slow_case != NULL) {
5191 jcc(Assembler::notZero, *slow_case);
5192 }
5193 jmp(done);
5195 bind(try_revoke_bias);
5196 // The prototype mark in the klass doesn't have the bias bit set any
5197 // more, indicating that objects of this data type are not supposed
5198 // to be biased any more. We are going to try to reset the mark of
5199 // this object to the prototype value and fall through to the
5200 // CAS-based locking scheme. Note that if our CAS fails, it means
5201 // that another thread raced us for the privilege of revoking the
5202 // bias of this particular object, so it's okay to continue in the
5203 // normal locking code.
5204 //
5205 // FIXME: due to a lack of registers we currently blow away the age
5206 // bits in this situation. Should attempt to preserve them.
5207 load_prototype_header(tmp_reg, obj_reg);
5208 if (os::is_MP()) {
5209 lock();
5210 }
5211 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5212 // Fall through to the normal CAS-based lock, because no matter what
5213 // the result of the above CAS, some thread must have succeeded in
5214 // removing the bias bit from the object's header.
5215 if (counters != NULL) {
5216 cond_inc32(Assembler::zero,
5217 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
5218 }
5220 bind(cas_label);
5222 return null_check_offset;
5223 }
5225 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
5226 Label L, E;
5228 #ifdef _WIN64
5229 // Windows always allocates space for it's register args
5230 assert(num_args <= 4, "only register arguments supported");
5231 subq(rsp, frame::arg_reg_save_area_bytes);
5232 #endif
5234 // Align stack if necessary
5235 testl(rsp, 15);
5236 jcc(Assembler::zero, L);
5238 subq(rsp, 8);
5239 {
5240 call(RuntimeAddress(entry_point));
5241 }
5242 addq(rsp, 8);
5243 jmp(E);
5245 bind(L);
5246 {
5247 call(RuntimeAddress(entry_point));
5248 }
5250 bind(E);
5252 #ifdef _WIN64
5253 // restore stack pointer
5254 addq(rsp, frame::arg_reg_save_area_bytes);
5255 #endif
5257 }
5259 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
5260 assert(!src2.is_lval(), "should use cmpptr");
5262 if (reachable(src2)) {
5263 cmpq(src1, as_Address(src2));
5264 } else {
5265 lea(rscratch1, src2);
5266 Assembler::cmpq(src1, Address(rscratch1, 0));
5267 }
5268 }
5270 int MacroAssembler::corrected_idivq(Register reg) {
5271 // Full implementation of Java ldiv and lrem; checks for special
5272 // case as described in JVM spec., p.243 & p.271. The function
5273 // returns the (pc) offset of the idivl instruction - may be needed
5274 // for implicit exceptions.
5275 //
5276 // normal case special case
5277 //
5278 // input : rax: dividend min_long
5279 // reg: divisor (may not be eax/edx) -1
5280 //
5281 // output: rax: quotient (= rax idiv reg) min_long
5282 // rdx: remainder (= rax irem reg) 0
5283 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
5284 static const int64_t min_long = 0x8000000000000000;
5285 Label normal_case, special_case;
5287 // check for special case
5288 cmp64(rax, ExternalAddress((address) &min_long));
5289 jcc(Assembler::notEqual, normal_case);
5290 xorl(rdx, rdx); // prepare rdx for possible special case (where
5291 // remainder = 0)
5292 cmpq(reg, -1);
5293 jcc(Assembler::equal, special_case);
5295 // handle normal case
5296 bind(normal_case);
5297 cdqq();
5298 int idivq_offset = offset();
5299 idivq(reg);
5301 // normal and special case exit
5302 bind(special_case);
5304 return idivq_offset;
5305 }
5307 void MacroAssembler::decrementq(Register reg, int value) {
5308 if (value == min_jint) { subq(reg, value); return; }
5309 if (value < 0) { incrementq(reg, -value); return; }
5310 if (value == 0) { ; return; }
5311 if (value == 1 && UseIncDec) { decq(reg) ; return; }
5312 /* else */ { subq(reg, value) ; return; }
5313 }
5315 void MacroAssembler::decrementq(Address dst, int value) {
5316 if (value == min_jint) { subq(dst, value); return; }
5317 if (value < 0) { incrementq(dst, -value); return; }
5318 if (value == 0) { ; return; }
5319 if (value == 1 && UseIncDec) { decq(dst) ; return; }
5320 /* else */ { subq(dst, value) ; return; }
5321 }
5323 void MacroAssembler::fat_nop() {
5324 // A 5 byte nop that is safe for patching (see patch_verified_entry)
5325 // Recommened sequence from 'Software Optimization Guide for the AMD
5326 // Hammer Processor'
5327 emit_byte(0x66);
5328 emit_byte(0x66);
5329 emit_byte(0x90);
5330 emit_byte(0x66);
5331 emit_byte(0x90);
5332 }
5334 void MacroAssembler::incrementq(Register reg, int value) {
5335 if (value == min_jint) { addq(reg, value); return; }
5336 if (value < 0) { decrementq(reg, -value); return; }
5337 if (value == 0) { ; return; }
5338 if (value == 1 && UseIncDec) { incq(reg) ; return; }
5339 /* else */ { addq(reg, value) ; return; }
5340 }
5342 void MacroAssembler::incrementq(Address dst, int value) {
5343 if (value == min_jint) { addq(dst, value); return; }
5344 if (value < 0) { decrementq(dst, -value); return; }
5345 if (value == 0) { ; return; }
5346 if (value == 1 && UseIncDec) { incq(dst) ; return; }
5347 /* else */ { addq(dst, value) ; return; }
5348 }
5350 // 32bit can do a case table jump in one instruction but we no longer allow the base
5351 // to be installed in the Address class
5352 void MacroAssembler::jump(ArrayAddress entry) {
5353 lea(rscratch1, entry.base());
5354 Address dispatch = entry.index();
5355 assert(dispatch._base == noreg, "must be");
5356 dispatch._base = rscratch1;
5357 jmp(dispatch);
5358 }
5360 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5361 ShouldNotReachHere(); // 64bit doesn't use two regs
5362 cmpq(x_lo, y_lo);
5363 }
5365 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5366 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5367 }
5369 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5370 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
5371 movptr(dst, rscratch1);
5372 }
5374 void MacroAssembler::leave() {
5375 // %%% is this really better? Why not on 32bit too?
5376 emit_byte(0xC9); // LEAVE
5377 }
5379 void MacroAssembler::lneg(Register hi, Register lo) {
5380 ShouldNotReachHere(); // 64bit doesn't use two regs
5381 negq(lo);
5382 }
5384 void MacroAssembler::movoop(Register dst, jobject obj) {
5385 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5386 }
5388 void MacroAssembler::movoop(Address dst, jobject obj) {
5389 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5390 movq(dst, rscratch1);
5391 }
5393 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5394 if (src.is_lval()) {
5395 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5396 } else {
5397 if (reachable(src)) {
5398 movq(dst, as_Address(src));
5399 } else {
5400 lea(rscratch1, src);
5401 movq(dst, Address(rscratch1,0));
5402 }
5403 }
5404 }
5406 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5407 movq(as_Address(dst), src);
5408 }
5410 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5411 movq(dst, as_Address(src));
5412 }
5414 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5415 void MacroAssembler::movptr(Address dst, intptr_t src) {
5416 mov64(rscratch1, src);
5417 movq(dst, rscratch1);
5418 }
5420 // These are mostly for initializing NULL
5421 void MacroAssembler::movptr(Address dst, int32_t src) {
5422 movslq(dst, src);
5423 }
5425 void MacroAssembler::movptr(Register dst, int32_t src) {
5426 mov64(dst, (intptr_t)src);
5427 }
5429 void MacroAssembler::pushoop(jobject obj) {
5430 movoop(rscratch1, obj);
5431 push(rscratch1);
5432 }
5434 void MacroAssembler::pushptr(AddressLiteral src) {
5435 lea(rscratch1, src);
5436 if (src.is_lval()) {
5437 push(rscratch1);
5438 } else {
5439 pushq(Address(rscratch1, 0));
5440 }
5441 }
5443 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
5444 bool clear_pc) {
5445 // we must set sp to zero to clear frame
5446 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
5447 // must clear fp, so that compiled frames are not confused; it is
5448 // possible that we need it only for debugging
5449 if (clear_fp) {
5450 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
5451 }
5453 if (clear_pc) {
5454 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
5455 }
5456 }
5458 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
5459 Register last_java_fp,
5460 address last_java_pc) {
5461 // determine last_java_sp register
5462 if (!last_java_sp->is_valid()) {
5463 last_java_sp = rsp;
5464 }
5466 // last_java_fp is optional
5467 if (last_java_fp->is_valid()) {
5468 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
5469 last_java_fp);
5470 }
5472 // last_java_pc is optional
5473 if (last_java_pc != NULL) {
5474 Address java_pc(r15_thread,
5475 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
5476 lea(rscratch1, InternalAddress(last_java_pc));
5477 movptr(java_pc, rscratch1);
5478 }
5480 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
5481 }
5483 static void pass_arg0(MacroAssembler* masm, Register arg) {
5484 if (c_rarg0 != arg ) {
5485 masm->mov(c_rarg0, arg);
5486 }
5487 }
5489 static void pass_arg1(MacroAssembler* masm, Register arg) {
5490 if (c_rarg1 != arg ) {
5491 masm->mov(c_rarg1, arg);
5492 }
5493 }
5495 static void pass_arg2(MacroAssembler* masm, Register arg) {
5496 if (c_rarg2 != arg ) {
5497 masm->mov(c_rarg2, arg);
5498 }
5499 }
5501 static void pass_arg3(MacroAssembler* masm, Register arg) {
5502 if (c_rarg3 != arg ) {
5503 masm->mov(c_rarg3, arg);
5504 }
5505 }
5507 void MacroAssembler::stop(const char* msg) {
5508 address rip = pc();
5509 pusha(); // get regs on stack
5510 lea(c_rarg0, ExternalAddress((address) msg));
5511 lea(c_rarg1, InternalAddress(rip));
5512 movq(c_rarg2, rsp); // pass pointer to regs array
5513 andq(rsp, -16); // align stack as required by ABI
5514 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
5515 hlt();
5516 }
5518 void MacroAssembler::warn(const char* msg) {
5519 push(r12);
5520 movq(r12, rsp);
5521 andq(rsp, -16); // align stack as required by push_CPU_state and call
5523 push_CPU_state(); // keeps alignment at 16 bytes
5524 lea(c_rarg0, ExternalAddress((address) msg));
5525 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
5526 pop_CPU_state();
5528 movq(rsp, r12);
5529 pop(r12);
5530 }
5532 #ifndef PRODUCT
5533 extern "C" void findpc(intptr_t x);
5534 #endif
5536 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
5537 // In order to get locks to work, we need to fake a in_VM state
5538 if (ShowMessageBoxOnError ) {
5539 JavaThread* thread = JavaThread::current();
5540 JavaThreadState saved_state = thread->thread_state();
5541 thread->set_thread_state(_thread_in_vm);
5542 #ifndef PRODUCT
5543 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5544 ttyLocker ttyl;
5545 BytecodeCounter::print();
5546 }
5547 #endif
5548 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5549 // XXX correct this offset for amd64
5550 // This is the value of eip which points to where verify_oop will return.
5551 if (os::message_box(msg, "Execution stopped, print registers?")) {
5552 ttyLocker ttyl;
5553 tty->print_cr("rip = 0x%016lx", pc);
5554 #ifndef PRODUCT
5555 tty->cr();
5556 findpc(pc);
5557 tty->cr();
5558 #endif
5559 tty->print_cr("rax = 0x%016lx", regs[15]);
5560 tty->print_cr("rbx = 0x%016lx", regs[12]);
5561 tty->print_cr("rcx = 0x%016lx", regs[14]);
5562 tty->print_cr("rdx = 0x%016lx", regs[13]);
5563 tty->print_cr("rdi = 0x%016lx", regs[8]);
5564 tty->print_cr("rsi = 0x%016lx", regs[9]);
5565 tty->print_cr("rbp = 0x%016lx", regs[10]);
5566 tty->print_cr("rsp = 0x%016lx", regs[11]);
5567 tty->print_cr("r8 = 0x%016lx", regs[7]);
5568 tty->print_cr("r9 = 0x%016lx", regs[6]);
5569 tty->print_cr("r10 = 0x%016lx", regs[5]);
5570 tty->print_cr("r11 = 0x%016lx", regs[4]);
5571 tty->print_cr("r12 = 0x%016lx", regs[3]);
5572 tty->print_cr("r13 = 0x%016lx", regs[2]);
5573 tty->print_cr("r14 = 0x%016lx", regs[1]);
5574 tty->print_cr("r15 = 0x%016lx", regs[0]);
5575 BREAKPOINT;
5576 }
5577 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5578 } else {
5579 ttyLocker ttyl;
5580 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
5581 msg);
5582 }
5583 }
5585 #endif // _LP64
5587 // Now versions that are common to 32/64 bit
5589 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5590 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5591 }
5593 void MacroAssembler::addptr(Register dst, Register src) {
5594 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5595 }
5597 void MacroAssembler::addptr(Address dst, Register src) {
5598 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5599 }
5601 void MacroAssembler::align(int modulus) {
5602 if (offset() % modulus != 0) {
5603 nop(modulus - (offset() % modulus));
5604 }
5605 }
5607 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5608 if (reachable(src)) {
5609 andpd(dst, as_Address(src));
5610 } else {
5611 lea(rscratch1, src);
5612 andpd(dst, Address(rscratch1, 0));
5613 }
5614 }
5616 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5617 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5618 }
5620 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
5621 pushf();
5622 if (os::is_MP())
5623 lock();
5624 incrementl(counter_addr);
5625 popf();
5626 }
5628 // Writes to stack successive pages until offset reached to check for
5629 // stack overflow + shadow pages. This clobbers tmp.
5630 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5631 movptr(tmp, rsp);
5632 // Bang stack for total size given plus shadow page size.
5633 // Bang one page at a time because large size can bang beyond yellow and
5634 // red zones.
5635 Label loop;
5636 bind(loop);
5637 movl(Address(tmp, (-os::vm_page_size())), size );
5638 subptr(tmp, os::vm_page_size());
5639 subl(size, os::vm_page_size());
5640 jcc(Assembler::greater, loop);
5642 // Bang down shadow pages too.
5643 // The -1 because we already subtracted 1 page.
5644 for (int i = 0; i< StackShadowPages-1; i++) {
5645 // this could be any sized move but this is can be a debugging crumb
5646 // so the bigger the better.
5647 movptr(Address(tmp, (-i*os::vm_page_size())), size );
5648 }
5649 }
5651 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
5652 assert(UseBiasedLocking, "why call this otherwise?");
5654 // Check for biased locking unlock case, which is a no-op
5655 // Note: we do not have to check the thread ID for two reasons.
5656 // First, the interpreter checks for IllegalMonitorStateException at
5657 // a higher level. Second, if the bias was revoked while we held the
5658 // lock, the object could not be rebiased toward another thread, so
5659 // the bias bit would be clear.
5660 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
5661 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
5662 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
5663 jcc(Assembler::equal, done);
5664 }
5666 void MacroAssembler::c2bool(Register x) {
5667 // implements x == 0 ? 0 : 1
5668 // note: must only look at least-significant byte of x
5669 // since C-style booleans are stored in one byte
5670 // only! (was bug)
5671 andl(x, 0xFF);
5672 setb(Assembler::notZero, x);
5673 }
5675 // Wouldn't need if AddressLiteral version had new name
5676 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
5677 Assembler::call(L, rtype);
5678 }
5680 void MacroAssembler::call(Register entry) {
5681 Assembler::call(entry);
5682 }
5684 void MacroAssembler::call(AddressLiteral entry) {
5685 if (reachable(entry)) {
5686 Assembler::call_literal(entry.target(), entry.rspec());
5687 } else {
5688 lea(rscratch1, entry);
5689 Assembler::call(rscratch1);
5690 }
5691 }
5693 // Implementation of call_VM versions
5695 void MacroAssembler::call_VM(Register oop_result,
5696 address entry_point,
5697 bool check_exceptions) {
5698 Label C, E;
5699 call(C, relocInfo::none);
5700 jmp(E);
5702 bind(C);
5703 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
5704 ret(0);
5706 bind(E);
5707 }
5709 void MacroAssembler::call_VM(Register oop_result,
5710 address entry_point,
5711 Register arg_1,
5712 bool check_exceptions) {
5713 Label C, E;
5714 call(C, relocInfo::none);
5715 jmp(E);
5717 bind(C);
5718 pass_arg1(this, arg_1);
5719 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
5720 ret(0);
5722 bind(E);
5723 }
5725 void MacroAssembler::call_VM(Register oop_result,
5726 address entry_point,
5727 Register arg_1,
5728 Register arg_2,
5729 bool check_exceptions) {
5730 Label C, E;
5731 call(C, relocInfo::none);
5732 jmp(E);
5734 bind(C);
5736 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5738 pass_arg2(this, arg_2);
5739 pass_arg1(this, arg_1);
5740 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
5741 ret(0);
5743 bind(E);
5744 }
5746 void MacroAssembler::call_VM(Register oop_result,
5747 address entry_point,
5748 Register arg_1,
5749 Register arg_2,
5750 Register arg_3,
5751 bool check_exceptions) {
5752 Label C, E;
5753 call(C, relocInfo::none);
5754 jmp(E);
5756 bind(C);
5758 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5759 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5760 pass_arg3(this, arg_3);
5762 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5763 pass_arg2(this, arg_2);
5765 pass_arg1(this, arg_1);
5766 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
5767 ret(0);
5769 bind(E);
5770 }
5772 void MacroAssembler::call_VM(Register oop_result,
5773 Register last_java_sp,
5774 address entry_point,
5775 int number_of_arguments,
5776 bool check_exceptions) {
5777 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
5778 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
5779 }
5781 void MacroAssembler::call_VM(Register oop_result,
5782 Register last_java_sp,
5783 address entry_point,
5784 Register arg_1,
5785 bool check_exceptions) {
5786 pass_arg1(this, arg_1);
5787 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
5788 }
5790 void MacroAssembler::call_VM(Register oop_result,
5791 Register last_java_sp,
5792 address entry_point,
5793 Register arg_1,
5794 Register arg_2,
5795 bool check_exceptions) {
5797 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5798 pass_arg2(this, arg_2);
5799 pass_arg1(this, arg_1);
5800 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
5801 }
5803 void MacroAssembler::call_VM(Register oop_result,
5804 Register last_java_sp,
5805 address entry_point,
5806 Register arg_1,
5807 Register arg_2,
5808 Register arg_3,
5809 bool check_exceptions) {
5810 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5811 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5812 pass_arg3(this, arg_3);
5813 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5814 pass_arg2(this, arg_2);
5815 pass_arg1(this, arg_1);
5816 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
5817 }
5819 void MacroAssembler::call_VM_base(Register oop_result,
5820 Register java_thread,
5821 Register last_java_sp,
5822 address entry_point,
5823 int number_of_arguments,
5824 bool check_exceptions) {
5825 // determine java_thread register
5826 if (!java_thread->is_valid()) {
5827 #ifdef _LP64
5828 java_thread = r15_thread;
5829 #else
5830 java_thread = rdi;
5831 get_thread(java_thread);
5832 #endif // LP64
5833 }
5834 // determine last_java_sp register
5835 if (!last_java_sp->is_valid()) {
5836 last_java_sp = rsp;
5837 }
5838 // debugging support
5839 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
5840 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
5841 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
5842 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
5844 // push java thread (becomes first argument of C function)
5846 NOT_LP64(push(java_thread); number_of_arguments++);
5847 LP64_ONLY(mov(c_rarg0, r15_thread));
5849 // set last Java frame before call
5850 assert(last_java_sp != rbp, "can't use ebp/rbp");
5852 // Only interpreter should have to set fp
5853 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
5855 // do the call, remove parameters
5856 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
5858 // restore the thread (cannot use the pushed argument since arguments
5859 // may be overwritten by C code generated by an optimizing compiler);
5860 // however can use the register value directly if it is callee saved.
5861 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
5862 // rdi & rsi (also r15) are callee saved -> nothing to do
5863 #ifdef ASSERT
5864 guarantee(java_thread != rax, "change this code");
5865 push(rax);
5866 { Label L;
5867 get_thread(rax);
5868 cmpptr(java_thread, rax);
5869 jcc(Assembler::equal, L);
5870 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
5871 bind(L);
5872 }
5873 pop(rax);
5874 #endif
5875 } else {
5876 get_thread(java_thread);
5877 }
5878 // reset last Java frame
5879 // Only interpreter should have to clear fp
5880 reset_last_Java_frame(java_thread, true, false);
5882 #ifndef CC_INTERP
5883 // C++ interp handles this in the interpreter
5884 check_and_handle_popframe(java_thread);
5885 check_and_handle_earlyret(java_thread);
5886 #endif /* CC_INTERP */
5888 if (check_exceptions) {
5889 // check for pending exceptions (java_thread is set upon return)
5890 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
5891 #ifndef _LP64
5892 jump_cc(Assembler::notEqual,
5893 RuntimeAddress(StubRoutines::forward_exception_entry()));
5894 #else
5895 // This used to conditionally jump to forward_exception however it is
5896 // possible if we relocate that the branch will not reach. So we must jump
5897 // around so we can always reach
5899 Label ok;
5900 jcc(Assembler::equal, ok);
5901 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
5902 bind(ok);
5903 #endif // LP64
5904 }
5906 // get oop result if there is one and reset the value in the thread
5907 if (oop_result->is_valid()) {
5908 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
5909 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
5910 verify_oop(oop_result, "broken oop in call_VM_base");
5911 }
5912 }
5914 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
5916 // Calculate the value for last_Java_sp
5917 // somewhat subtle. call_VM does an intermediate call
5918 // which places a return address on the stack just under the
5919 // stack pointer as the user finsihed with it. This allows
5920 // use to retrieve last_Java_pc from last_Java_sp[-1].
5921 // On 32bit we then have to push additional args on the stack to accomplish
5922 // the actual requested call. On 64bit call_VM only can use register args
5923 // so the only extra space is the return address that call_VM created.
5924 // This hopefully explains the calculations here.
5926 #ifdef _LP64
5927 // We've pushed one address, correct last_Java_sp
5928 lea(rax, Address(rsp, wordSize));
5929 #else
5930 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
5931 #endif // LP64
5933 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
5935 }
5937 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
5938 call_VM_leaf_base(entry_point, number_of_arguments);
5939 }
5941 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
5942 pass_arg0(this, arg_0);
5943 call_VM_leaf(entry_point, 1);
5944 }
5946 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
5948 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5949 pass_arg1(this, arg_1);
5950 pass_arg0(this, arg_0);
5951 call_VM_leaf(entry_point, 2);
5952 }
5954 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
5955 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
5956 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5957 pass_arg2(this, arg_2);
5958 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
5959 pass_arg1(this, arg_1);
5960 pass_arg0(this, arg_0);
5961 call_VM_leaf(entry_point, 3);
5962 }
5964 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
5965 }
5967 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
5968 }
5970 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
5971 if (reachable(src1)) {
5972 cmpl(as_Address(src1), imm);
5973 } else {
5974 lea(rscratch1, src1);
5975 cmpl(Address(rscratch1, 0), imm);
5976 }
5977 }
5979 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
5980 assert(!src2.is_lval(), "use cmpptr");
5981 if (reachable(src2)) {
5982 cmpl(src1, as_Address(src2));
5983 } else {
5984 lea(rscratch1, src2);
5985 cmpl(src1, Address(rscratch1, 0));
5986 }
5987 }
5989 void MacroAssembler::cmp32(Register src1, int32_t imm) {
5990 Assembler::cmpl(src1, imm);
5991 }
5993 void MacroAssembler::cmp32(Register src1, Address src2) {
5994 Assembler::cmpl(src1, src2);
5995 }
5997 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
5998 ucomisd(opr1, opr2);
6000 Label L;
6001 if (unordered_is_less) {
6002 movl(dst, -1);
6003 jcc(Assembler::parity, L);
6004 jcc(Assembler::below , L);
6005 movl(dst, 0);
6006 jcc(Assembler::equal , L);
6007 increment(dst);
6008 } else { // unordered is greater
6009 movl(dst, 1);
6010 jcc(Assembler::parity, L);
6011 jcc(Assembler::above , L);
6012 movl(dst, 0);
6013 jcc(Assembler::equal , L);
6014 decrementl(dst);
6015 }
6016 bind(L);
6017 }
6019 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6020 ucomiss(opr1, opr2);
6022 Label L;
6023 if (unordered_is_less) {
6024 movl(dst, -1);
6025 jcc(Assembler::parity, L);
6026 jcc(Assembler::below , L);
6027 movl(dst, 0);
6028 jcc(Assembler::equal , L);
6029 increment(dst);
6030 } else { // unordered is greater
6031 movl(dst, 1);
6032 jcc(Assembler::parity, L);
6033 jcc(Assembler::above , L);
6034 movl(dst, 0);
6035 jcc(Assembler::equal , L);
6036 decrementl(dst);
6037 }
6038 bind(L);
6039 }
6042 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
6043 if (reachable(src1)) {
6044 cmpb(as_Address(src1), imm);
6045 } else {
6046 lea(rscratch1, src1);
6047 cmpb(Address(rscratch1, 0), imm);
6048 }
6049 }
6051 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
6052 #ifdef _LP64
6053 if (src2.is_lval()) {
6054 movptr(rscratch1, src2);
6055 Assembler::cmpq(src1, rscratch1);
6056 } else if (reachable(src2)) {
6057 cmpq(src1, as_Address(src2));
6058 } else {
6059 lea(rscratch1, src2);
6060 Assembler::cmpq(src1, Address(rscratch1, 0));
6061 }
6062 #else
6063 if (src2.is_lval()) {
6064 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6065 } else {
6066 cmpl(src1, as_Address(src2));
6067 }
6068 #endif // _LP64
6069 }
6071 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
6072 assert(src2.is_lval(), "not a mem-mem compare");
6073 #ifdef _LP64
6074 // moves src2's literal address
6075 movptr(rscratch1, src2);
6076 Assembler::cmpq(src1, rscratch1);
6077 #else
6078 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6079 #endif // _LP64
6080 }
6082 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6083 if (reachable(adr)) {
6084 if (os::is_MP())
6085 lock();
6086 cmpxchgptr(reg, as_Address(adr));
6087 } else {
6088 lea(rscratch1, adr);
6089 if (os::is_MP())
6090 lock();
6091 cmpxchgptr(reg, Address(rscratch1, 0));
6092 }
6093 }
6095 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6096 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6097 }
6099 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6100 if (reachable(src)) {
6101 comisd(dst, as_Address(src));
6102 } else {
6103 lea(rscratch1, src);
6104 comisd(dst, Address(rscratch1, 0));
6105 }
6106 }
6108 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6109 if (reachable(src)) {
6110 comiss(dst, as_Address(src));
6111 } else {
6112 lea(rscratch1, src);
6113 comiss(dst, Address(rscratch1, 0));
6114 }
6115 }
6118 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6119 Condition negated_cond = negate_condition(cond);
6120 Label L;
6121 jcc(negated_cond, L);
6122 atomic_incl(counter_addr);
6123 bind(L);
6124 }
6126 int MacroAssembler::corrected_idivl(Register reg) {
6127 // Full implementation of Java idiv and irem; checks for
6128 // special case as described in JVM spec., p.243 & p.271.
6129 // The function returns the (pc) offset of the idivl
6130 // instruction - may be needed for implicit exceptions.
6131 //
6132 // normal case special case
6133 //
6134 // input : rax,: dividend min_int
6135 // reg: divisor (may not be rax,/rdx) -1
6136 //
6137 // output: rax,: quotient (= rax, idiv reg) min_int
6138 // rdx: remainder (= rax, irem reg) 0
6139 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
6140 const int min_int = 0x80000000;
6141 Label normal_case, special_case;
6143 // check for special case
6144 cmpl(rax, min_int);
6145 jcc(Assembler::notEqual, normal_case);
6146 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
6147 cmpl(reg, -1);
6148 jcc(Assembler::equal, special_case);
6150 // handle normal case
6151 bind(normal_case);
6152 cdql();
6153 int idivl_offset = offset();
6154 idivl(reg);
6156 // normal and special case exit
6157 bind(special_case);
6159 return idivl_offset;
6160 }
6164 void MacroAssembler::decrementl(Register reg, int value) {
6165 if (value == min_jint) {subl(reg, value) ; return; }
6166 if (value < 0) { incrementl(reg, -value); return; }
6167 if (value == 0) { ; return; }
6168 if (value == 1 && UseIncDec) { decl(reg) ; return; }
6169 /* else */ { subl(reg, value) ; return; }
6170 }
6172 void MacroAssembler::decrementl(Address dst, int value) {
6173 if (value == min_jint) {subl(dst, value) ; return; }
6174 if (value < 0) { incrementl(dst, -value); return; }
6175 if (value == 0) { ; return; }
6176 if (value == 1 && UseIncDec) { decl(dst) ; return; }
6177 /* else */ { subl(dst, value) ; return; }
6178 }
6180 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6181 assert (shift_value > 0, "illegal shift value");
6182 Label _is_positive;
6183 testl (reg, reg);
6184 jcc (Assembler::positive, _is_positive);
6185 int offset = (1 << shift_value) - 1 ;
6187 if (offset == 1) {
6188 incrementl(reg);
6189 } else {
6190 addl(reg, offset);
6191 }
6193 bind (_is_positive);
6194 sarl(reg, shift_value);
6195 }
6197 // !defined(COMPILER2) is because of stupid core builds
6198 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6199 void MacroAssembler::empty_FPU_stack() {
6200 if (VM_Version::supports_mmx()) {
6201 emms();
6202 } else {
6203 for (int i = 8; i-- > 0; ) ffree(i);
6204 }
6205 }
6206 #endif // !LP64 || C1 || !C2
6209 // Defines obj, preserves var_size_in_bytes
6210 void MacroAssembler::eden_allocate(Register obj,
6211 Register var_size_in_bytes,
6212 int con_size_in_bytes,
6213 Register t1,
6214 Label& slow_case) {
6215 assert(obj == rax, "obj must be in rax, for cmpxchg");
6216 assert_different_registers(obj, var_size_in_bytes, t1);
6217 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
6218 jmp(slow_case);
6219 } else {
6220 Register end = t1;
6221 Label retry;
6222 bind(retry);
6223 ExternalAddress heap_top((address) Universe::heap()->top_addr());
6224 movptr(obj, heap_top);
6225 if (var_size_in_bytes == noreg) {
6226 lea(end, Address(obj, con_size_in_bytes));
6227 } else {
6228 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
6229 }
6230 // if end < obj then we wrapped around => object too long => slow case
6231 cmpptr(end, obj);
6232 jcc(Assembler::below, slow_case);
6233 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
6234 jcc(Assembler::above, slow_case);
6235 // Compare obj with the top addr, and if still equal, store the new top addr in
6236 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
6237 // it otherwise. Use lock prefix for atomicity on MPs.
6238 locked_cmpxchgptr(end, heap_top);
6239 jcc(Assembler::notEqual, retry);
6240 }
6241 }
6243 void MacroAssembler::enter() {
6244 push(rbp);
6245 mov(rbp, rsp);
6246 }
6248 void MacroAssembler::fcmp(Register tmp) {
6249 fcmp(tmp, 1, true, true);
6250 }
6252 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
6253 assert(!pop_right || pop_left, "usage error");
6254 if (VM_Version::supports_cmov()) {
6255 assert(tmp == noreg, "unneeded temp");
6256 if (pop_left) {
6257 fucomip(index);
6258 } else {
6259 fucomi(index);
6260 }
6261 if (pop_right) {
6262 fpop();
6263 }
6264 } else {
6265 assert(tmp != noreg, "need temp");
6266 if (pop_left) {
6267 if (pop_right) {
6268 fcompp();
6269 } else {
6270 fcomp(index);
6271 }
6272 } else {
6273 fcom(index);
6274 }
6275 // convert FPU condition into eflags condition via rax,
6276 save_rax(tmp);
6277 fwait(); fnstsw_ax();
6278 sahf();
6279 restore_rax(tmp);
6280 }
6281 // condition codes set as follows:
6282 //
6283 // CF (corresponds to C0) if x < y
6284 // PF (corresponds to C2) if unordered
6285 // ZF (corresponds to C3) if x = y
6286 }
6288 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
6289 fcmp2int(dst, unordered_is_less, 1, true, true);
6290 }
6292 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
6293 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
6294 Label L;
6295 if (unordered_is_less) {
6296 movl(dst, -1);
6297 jcc(Assembler::parity, L);
6298 jcc(Assembler::below , L);
6299 movl(dst, 0);
6300 jcc(Assembler::equal , L);
6301 increment(dst);
6302 } else { // unordered is greater
6303 movl(dst, 1);
6304 jcc(Assembler::parity, L);
6305 jcc(Assembler::above , L);
6306 movl(dst, 0);
6307 jcc(Assembler::equal , L);
6308 decrementl(dst);
6309 }
6310 bind(L);
6311 }
6313 void MacroAssembler::fld_d(AddressLiteral src) {
6314 fld_d(as_Address(src));
6315 }
6317 void MacroAssembler::fld_s(AddressLiteral src) {
6318 fld_s(as_Address(src));
6319 }
6321 void MacroAssembler::fld_x(AddressLiteral src) {
6322 Assembler::fld_x(as_Address(src));
6323 }
6325 void MacroAssembler::fldcw(AddressLiteral src) {
6326 Assembler::fldcw(as_Address(src));
6327 }
6329 void MacroAssembler::fpop() {
6330 ffree();
6331 fincstp();
6332 }
6334 void MacroAssembler::fremr(Register tmp) {
6335 save_rax(tmp);
6336 { Label L;
6337 bind(L);
6338 fprem();
6339 fwait(); fnstsw_ax();
6340 #ifdef _LP64
6341 testl(rax, 0x400);
6342 jcc(Assembler::notEqual, L);
6343 #else
6344 sahf();
6345 jcc(Assembler::parity, L);
6346 #endif // _LP64
6347 }
6348 restore_rax(tmp);
6349 // Result is in ST0.
6350 // Note: fxch & fpop to get rid of ST1
6351 // (otherwise FPU stack could overflow eventually)
6352 fxch(1);
6353 fpop();
6354 }
6357 void MacroAssembler::incrementl(AddressLiteral dst) {
6358 if (reachable(dst)) {
6359 incrementl(as_Address(dst));
6360 } else {
6361 lea(rscratch1, dst);
6362 incrementl(Address(rscratch1, 0));
6363 }
6364 }
6366 void MacroAssembler::incrementl(ArrayAddress dst) {
6367 incrementl(as_Address(dst));
6368 }
6370 void MacroAssembler::incrementl(Register reg, int value) {
6371 if (value == min_jint) {addl(reg, value) ; return; }
6372 if (value < 0) { decrementl(reg, -value); return; }
6373 if (value == 0) { ; return; }
6374 if (value == 1 && UseIncDec) { incl(reg) ; return; }
6375 /* else */ { addl(reg, value) ; return; }
6376 }
6378 void MacroAssembler::incrementl(Address dst, int value) {
6379 if (value == min_jint) {addl(dst, value) ; return; }
6380 if (value < 0) { decrementl(dst, -value); return; }
6381 if (value == 0) { ; return; }
6382 if (value == 1 && UseIncDec) { incl(dst) ; return; }
6383 /* else */ { addl(dst, value) ; return; }
6384 }
6386 void MacroAssembler::jump(AddressLiteral dst) {
6387 if (reachable(dst)) {
6388 jmp_literal(dst.target(), dst.rspec());
6389 } else {
6390 lea(rscratch1, dst);
6391 jmp(rscratch1);
6392 }
6393 }
6395 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
6396 if (reachable(dst)) {
6397 InstructionMark im(this);
6398 relocate(dst.reloc());
6399 const int short_size = 2;
6400 const int long_size = 6;
6401 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
6402 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
6403 // 0111 tttn #8-bit disp
6404 emit_byte(0x70 | cc);
6405 emit_byte((offs - short_size) & 0xFF);
6406 } else {
6407 // 0000 1111 1000 tttn #32-bit disp
6408 emit_byte(0x0F);
6409 emit_byte(0x80 | cc);
6410 emit_long(offs - long_size);
6411 }
6412 } else {
6413 #ifdef ASSERT
6414 warning("reversing conditional branch");
6415 #endif /* ASSERT */
6416 Label skip;
6417 jccb(reverse[cc], skip);
6418 lea(rscratch1, dst);
6419 Assembler::jmp(rscratch1);
6420 bind(skip);
6421 }
6422 }
6424 void MacroAssembler::ldmxcsr(AddressLiteral src) {
6425 if (reachable(src)) {
6426 Assembler::ldmxcsr(as_Address(src));
6427 } else {
6428 lea(rscratch1, src);
6429 Assembler::ldmxcsr(Address(rscratch1, 0));
6430 }
6431 }
6433 int MacroAssembler::load_signed_byte(Register dst, Address src) {
6434 int off;
6435 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6436 off = offset();
6437 movsbl(dst, src); // movsxb
6438 } else {
6439 off = load_unsigned_byte(dst, src);
6440 shll(dst, 24);
6441 sarl(dst, 24);
6442 }
6443 return off;
6444 }
6446 // Note: load_signed_short used to be called load_signed_word.
6447 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
6448 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
6449 // The term "word" in HotSpot means a 32- or 64-bit machine word.
6450 int MacroAssembler::load_signed_short(Register dst, Address src) {
6451 int off;
6452 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6453 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
6454 // version but this is what 64bit has always done. This seems to imply
6455 // that users are only using 32bits worth.
6456 off = offset();
6457 movswl(dst, src); // movsxw
6458 } else {
6459 off = load_unsigned_short(dst, src);
6460 shll(dst, 16);
6461 sarl(dst, 16);
6462 }
6463 return off;
6464 }
6466 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
6467 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6468 // and "3.9 Partial Register Penalties", p. 22).
6469 int off;
6470 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
6471 off = offset();
6472 movzbl(dst, src); // movzxb
6473 } else {
6474 xorl(dst, dst);
6475 off = offset();
6476 movb(dst, src);
6477 }
6478 return off;
6479 }
6481 // Note: load_unsigned_short used to be called load_unsigned_word.
6482 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
6483 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6484 // and "3.9 Partial Register Penalties", p. 22).
6485 int off;
6486 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
6487 off = offset();
6488 movzwl(dst, src); // movzxw
6489 } else {
6490 xorl(dst, dst);
6491 off = offset();
6492 movw(dst, src);
6493 }
6494 return off;
6495 }
6497 void MacroAssembler::load_sized_value(Register dst, Address src,
6498 size_t size_in_bytes, bool is_signed) {
6499 switch (size_in_bytes) {
6500 #ifndef _LP64
6501 // For case 8, caller is responsible for manually loading
6502 // the second word into another register.
6503 case 8: movl(dst, src); break;
6504 #else
6505 case 8: movq(dst, src); break;
6506 #endif
6507 case 4: movl(dst, src); break;
6508 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
6509 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
6510 default: ShouldNotReachHere();
6511 }
6512 }
6514 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
6515 if (reachable(dst)) {
6516 movl(as_Address(dst), src);
6517 } else {
6518 lea(rscratch1, dst);
6519 movl(Address(rscratch1, 0), src);
6520 }
6521 }
6523 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
6524 if (reachable(src)) {
6525 movl(dst, as_Address(src));
6526 } else {
6527 lea(rscratch1, src);
6528 movl(dst, Address(rscratch1, 0));
6529 }
6530 }
6532 // C++ bool manipulation
6534 void MacroAssembler::movbool(Register dst, Address src) {
6535 if(sizeof(bool) == 1)
6536 movb(dst, src);
6537 else if(sizeof(bool) == 2)
6538 movw(dst, src);
6539 else if(sizeof(bool) == 4)
6540 movl(dst, src);
6541 else
6542 // unsupported
6543 ShouldNotReachHere();
6544 }
6546 void MacroAssembler::movbool(Address dst, bool boolconst) {
6547 if(sizeof(bool) == 1)
6548 movb(dst, (int) boolconst);
6549 else if(sizeof(bool) == 2)
6550 movw(dst, (int) boolconst);
6551 else if(sizeof(bool) == 4)
6552 movl(dst, (int) boolconst);
6553 else
6554 // unsupported
6555 ShouldNotReachHere();
6556 }
6558 void MacroAssembler::movbool(Address dst, Register src) {
6559 if(sizeof(bool) == 1)
6560 movb(dst, src);
6561 else if(sizeof(bool) == 2)
6562 movw(dst, src);
6563 else if(sizeof(bool) == 4)
6564 movl(dst, src);
6565 else
6566 // unsupported
6567 ShouldNotReachHere();
6568 }
6570 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
6571 movb(as_Address(dst), src);
6572 }
6574 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
6575 if (reachable(src)) {
6576 if (UseXmmLoadAndClearUpper) {
6577 movsd (dst, as_Address(src));
6578 } else {
6579 movlpd(dst, as_Address(src));
6580 }
6581 } else {
6582 lea(rscratch1, src);
6583 if (UseXmmLoadAndClearUpper) {
6584 movsd (dst, Address(rscratch1, 0));
6585 } else {
6586 movlpd(dst, Address(rscratch1, 0));
6587 }
6588 }
6589 }
6591 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
6592 if (reachable(src)) {
6593 movss(dst, as_Address(src));
6594 } else {
6595 lea(rscratch1, src);
6596 movss(dst, Address(rscratch1, 0));
6597 }
6598 }
6600 void MacroAssembler::movptr(Register dst, Register src) {
6601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6602 }
6604 void MacroAssembler::movptr(Register dst, Address src) {
6605 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6606 }
6608 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
6609 void MacroAssembler::movptr(Register dst, intptr_t src) {
6610 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
6611 }
6613 void MacroAssembler::movptr(Address dst, Register src) {
6614 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6615 }
6617 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
6618 if (reachable(src)) {
6619 movss(dst, as_Address(src));
6620 } else {
6621 lea(rscratch1, src);
6622 movss(dst, Address(rscratch1, 0));
6623 }
6624 }
6626 void MacroAssembler::null_check(Register reg, int offset) {
6627 if (needs_explicit_null_check(offset)) {
6628 // provoke OS NULL exception if reg = NULL by
6629 // accessing M[reg] w/o changing any (non-CC) registers
6630 // NOTE: cmpl is plenty here to provoke a segv
6631 cmpptr(rax, Address(reg, 0));
6632 // Note: should probably use testl(rax, Address(reg, 0));
6633 // may be shorter code (however, this version of
6634 // testl needs to be implemented first)
6635 } else {
6636 // nothing to do, (later) access of M[reg + offset]
6637 // will provoke OS NULL exception if reg = NULL
6638 }
6639 }
6641 void MacroAssembler::os_breakpoint() {
6642 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
6643 // (e.g., MSVC can't call ps() otherwise)
6644 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
6645 }
6647 void MacroAssembler::pop_CPU_state() {
6648 pop_FPU_state();
6649 pop_IU_state();
6650 }
6652 void MacroAssembler::pop_FPU_state() {
6653 NOT_LP64(frstor(Address(rsp, 0));)
6654 LP64_ONLY(fxrstor(Address(rsp, 0));)
6655 addptr(rsp, FPUStateSizeInWords * wordSize);
6656 }
6658 void MacroAssembler::pop_IU_state() {
6659 popa();
6660 LP64_ONLY(addq(rsp, 8));
6661 popf();
6662 }
6664 // Save Integer and Float state
6665 // Warning: Stack must be 16 byte aligned (64bit)
6666 void MacroAssembler::push_CPU_state() {
6667 push_IU_state();
6668 push_FPU_state();
6669 }
6671 void MacroAssembler::push_FPU_state() {
6672 subptr(rsp, FPUStateSizeInWords * wordSize);
6673 #ifndef _LP64
6674 fnsave(Address(rsp, 0));
6675 fwait();
6676 #else
6677 fxsave(Address(rsp, 0));
6678 #endif // LP64
6679 }
6681 void MacroAssembler::push_IU_state() {
6682 // Push flags first because pusha kills them
6683 pushf();
6684 // Make sure rsp stays 16-byte aligned
6685 LP64_ONLY(subq(rsp, 8));
6686 pusha();
6687 }
6689 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
6690 // determine java_thread register
6691 if (!java_thread->is_valid()) {
6692 java_thread = rdi;
6693 get_thread(java_thread);
6694 }
6695 // we must set sp to zero to clear frame
6696 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
6697 if (clear_fp) {
6698 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
6699 }
6701 if (clear_pc)
6702 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
6704 }
6706 void MacroAssembler::restore_rax(Register tmp) {
6707 if (tmp == noreg) pop(rax);
6708 else if (tmp != rax) mov(rax, tmp);
6709 }
6711 void MacroAssembler::round_to(Register reg, int modulus) {
6712 addptr(reg, modulus - 1);
6713 andptr(reg, -modulus);
6714 }
6716 void MacroAssembler::save_rax(Register tmp) {
6717 if (tmp == noreg) push(rax);
6718 else if (tmp != rax) mov(tmp, rax);
6719 }
6721 // Write serialization page so VM thread can do a pseudo remote membar.
6722 // We use the current thread pointer to calculate a thread specific
6723 // offset to write to within the page. This minimizes bus traffic
6724 // due to cache line collision.
6725 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
6726 movl(tmp, thread);
6727 shrl(tmp, os::get_serialize_page_shift_count());
6728 andl(tmp, (os::vm_page_size() - sizeof(int)));
6730 Address index(noreg, tmp, Address::times_1);
6731 ExternalAddress page(os::get_memory_serialize_page());
6733 // Size of store must match masking code above
6734 movl(as_Address(ArrayAddress(page, index)), tmp);
6735 }
6737 // Calls to C land
6738 //
6739 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
6740 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
6741 // has to be reset to 0. This is required to allow proper stack traversal.
6742 void MacroAssembler::set_last_Java_frame(Register java_thread,
6743 Register last_java_sp,
6744 Register last_java_fp,
6745 address last_java_pc) {
6746 // determine java_thread register
6747 if (!java_thread->is_valid()) {
6748 java_thread = rdi;
6749 get_thread(java_thread);
6750 }
6751 // determine last_java_sp register
6752 if (!last_java_sp->is_valid()) {
6753 last_java_sp = rsp;
6754 }
6756 // last_java_fp is optional
6758 if (last_java_fp->is_valid()) {
6759 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
6760 }
6762 // last_java_pc is optional
6764 if (last_java_pc != NULL) {
6765 lea(Address(java_thread,
6766 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
6767 InternalAddress(last_java_pc));
6769 }
6770 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
6771 }
6773 void MacroAssembler::shlptr(Register dst, int imm8) {
6774 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
6775 }
6777 void MacroAssembler::shrptr(Register dst, int imm8) {
6778 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
6779 }
6781 void MacroAssembler::sign_extend_byte(Register reg) {
6782 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
6783 movsbl(reg, reg); // movsxb
6784 } else {
6785 shll(reg, 24);
6786 sarl(reg, 24);
6787 }
6788 }
6790 void MacroAssembler::sign_extend_short(Register reg) {
6791 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6792 movswl(reg, reg); // movsxw
6793 } else {
6794 shll(reg, 16);
6795 sarl(reg, 16);
6796 }
6797 }
6799 //////////////////////////////////////////////////////////////////////////////////
6800 #ifndef SERIALGC
6802 void MacroAssembler::g1_write_barrier_pre(Register obj,
6803 #ifndef _LP64
6804 Register thread,
6805 #endif
6806 Register tmp,
6807 Register tmp2,
6808 bool tosca_live) {
6809 LP64_ONLY(Register thread = r15_thread;)
6810 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6811 PtrQueue::byte_offset_of_active()));
6813 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6814 PtrQueue::byte_offset_of_index()));
6815 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
6816 PtrQueue::byte_offset_of_buf()));
6819 Label done;
6820 Label runtime;
6822 // if (!marking_in_progress) goto done;
6823 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
6824 cmpl(in_progress, 0);
6825 } else {
6826 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
6827 cmpb(in_progress, 0);
6828 }
6829 jcc(Assembler::equal, done);
6831 // if (x.f == NULL) goto done;
6832 #ifdef _LP64
6833 load_heap_oop(tmp2, Address(obj, 0));
6834 #else
6835 movptr(tmp2, Address(obj, 0));
6836 #endif
6837 cmpptr(tmp2, (int32_t) NULL_WORD);
6838 jcc(Assembler::equal, done);
6840 // Can we store original value in the thread's buffer?
6842 #ifdef _LP64
6843 movslq(tmp, index);
6844 cmpq(tmp, 0);
6845 #else
6846 cmpl(index, 0);
6847 #endif
6848 jcc(Assembler::equal, runtime);
6849 #ifdef _LP64
6850 subq(tmp, wordSize);
6851 movl(index, tmp);
6852 addq(tmp, buffer);
6853 #else
6854 subl(index, wordSize);
6855 movl(tmp, buffer);
6856 addl(tmp, index);
6857 #endif
6858 movptr(Address(tmp, 0), tmp2);
6859 jmp(done);
6860 bind(runtime);
6861 // save the live input values
6862 if(tosca_live) push(rax);
6863 push(obj);
6864 #ifdef _LP64
6865 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread);
6866 #else
6867 push(thread);
6868 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread);
6869 pop(thread);
6870 #endif
6871 pop(obj);
6872 if(tosca_live) pop(rax);
6873 bind(done);
6875 }
6877 void MacroAssembler::g1_write_barrier_post(Register store_addr,
6878 Register new_val,
6879 #ifndef _LP64
6880 Register thread,
6881 #endif
6882 Register tmp,
6883 Register tmp2) {
6885 LP64_ONLY(Register thread = r15_thread;)
6886 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6887 PtrQueue::byte_offset_of_index()));
6888 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
6889 PtrQueue::byte_offset_of_buf()));
6890 BarrierSet* bs = Universe::heap()->barrier_set();
6891 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
6892 Label done;
6893 Label runtime;
6895 // Does store cross heap regions?
6897 movptr(tmp, store_addr);
6898 xorptr(tmp, new_val);
6899 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
6900 jcc(Assembler::equal, done);
6902 // crosses regions, storing NULL?
6904 cmpptr(new_val, (int32_t) NULL_WORD);
6905 jcc(Assembler::equal, done);
6907 // storing region crossing non-NULL, is card already dirty?
6909 ExternalAddress cardtable((address) ct->byte_map_base);
6910 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
6911 #ifdef _LP64
6912 const Register card_addr = tmp;
6914 movq(card_addr, store_addr);
6915 shrq(card_addr, CardTableModRefBS::card_shift);
6917 lea(tmp2, cardtable);
6919 // get the address of the card
6920 addq(card_addr, tmp2);
6921 #else
6922 const Register card_index = tmp;
6924 movl(card_index, store_addr);
6925 shrl(card_index, CardTableModRefBS::card_shift);
6927 Address index(noreg, card_index, Address::times_1);
6928 const Register card_addr = tmp;
6929 lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
6930 #endif
6931 cmpb(Address(card_addr, 0), 0);
6932 jcc(Assembler::equal, done);
6934 // storing a region crossing, non-NULL oop, card is clean.
6935 // dirty card and log.
6937 movb(Address(card_addr, 0), 0);
6939 cmpl(queue_index, 0);
6940 jcc(Assembler::equal, runtime);
6941 subl(queue_index, wordSize);
6942 movptr(tmp2, buffer);
6943 #ifdef _LP64
6944 movslq(rscratch1, queue_index);
6945 addq(tmp2, rscratch1);
6946 movq(Address(tmp2, 0), card_addr);
6947 #else
6948 addl(tmp2, queue_index);
6949 movl(Address(tmp2, 0), card_index);
6950 #endif
6951 jmp(done);
6953 bind(runtime);
6954 // save the live input values
6955 push(store_addr);
6956 push(new_val);
6957 #ifdef _LP64
6958 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
6959 #else
6960 push(thread);
6961 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
6962 pop(thread);
6963 #endif
6964 pop(new_val);
6965 pop(store_addr);
6967 bind(done);
6969 }
6971 #endif // SERIALGC
6972 //////////////////////////////////////////////////////////////////////////////////
6975 void MacroAssembler::store_check(Register obj) {
6976 // Does a store check for the oop in register obj. The content of
6977 // register obj is destroyed afterwards.
6978 store_check_part_1(obj);
6979 store_check_part_2(obj);
6980 }
6982 void MacroAssembler::store_check(Register obj, Address dst) {
6983 store_check(obj);
6984 }
6987 // split the store check operation so that other instructions can be scheduled inbetween
6988 void MacroAssembler::store_check_part_1(Register obj) {
6989 BarrierSet* bs = Universe::heap()->barrier_set();
6990 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
6991 shrptr(obj, CardTableModRefBS::card_shift);
6992 }
6994 void MacroAssembler::store_check_part_2(Register obj) {
6995 BarrierSet* bs = Universe::heap()->barrier_set();
6996 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
6997 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
6998 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
7000 // The calculation for byte_map_base is as follows:
7001 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
7002 // So this essentially converts an address to a displacement and
7003 // it will never need to be relocated. On 64bit however the value may be too
7004 // large for a 32bit displacement
7006 intptr_t disp = (intptr_t) ct->byte_map_base;
7007 if (is_simm32(disp)) {
7008 Address cardtable(noreg, obj, Address::times_1, disp);
7009 movb(cardtable, 0);
7010 } else {
7011 // By doing it as an ExternalAddress disp could be converted to a rip-relative
7012 // displacement and done in a single instruction given favorable mapping and
7013 // a smarter version of as_Address. Worst case it is two instructions which
7014 // is no worse off then loading disp into a register and doing as a simple
7015 // Address() as above.
7016 // We can't do as ExternalAddress as the only style since if disp == 0 we'll
7017 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
7018 // in some cases we'll get a single instruction version.
7020 ExternalAddress cardtable((address)disp);
7021 Address index(noreg, obj, Address::times_1);
7022 movb(as_Address(ArrayAddress(cardtable, index)), 0);
7023 }
7024 }
7026 void MacroAssembler::subptr(Register dst, int32_t imm32) {
7027 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
7028 }
7030 void MacroAssembler::subptr(Register dst, Register src) {
7031 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
7032 }
7034 void MacroAssembler::test32(Register src1, AddressLiteral src2) {
7035 // src2 must be rval
7037 if (reachable(src2)) {
7038 testl(src1, as_Address(src2));
7039 } else {
7040 lea(rscratch1, src2);
7041 testl(src1, Address(rscratch1, 0));
7042 }
7043 }
7045 // C++ bool manipulation
7046 void MacroAssembler::testbool(Register dst) {
7047 if(sizeof(bool) == 1)
7048 testb(dst, 0xff);
7049 else if(sizeof(bool) == 2) {
7050 // testw implementation needed for two byte bools
7051 ShouldNotReachHere();
7052 } else if(sizeof(bool) == 4)
7053 testl(dst, dst);
7054 else
7055 // unsupported
7056 ShouldNotReachHere();
7057 }
7059 void MacroAssembler::testptr(Register dst, Register src) {
7060 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
7061 }
7063 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
7064 void MacroAssembler::tlab_allocate(Register obj,
7065 Register var_size_in_bytes,
7066 int con_size_in_bytes,
7067 Register t1,
7068 Register t2,
7069 Label& slow_case) {
7070 assert_different_registers(obj, t1, t2);
7071 assert_different_registers(obj, var_size_in_bytes, t1);
7072 Register end = t2;
7073 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
7075 verify_tlab();
7077 NOT_LP64(get_thread(thread));
7079 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
7080 if (var_size_in_bytes == noreg) {
7081 lea(end, Address(obj, con_size_in_bytes));
7082 } else {
7083 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
7084 }
7085 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
7086 jcc(Assembler::above, slow_case);
7088 // update the tlab top pointer
7089 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
7091 // recover var_size_in_bytes if necessary
7092 if (var_size_in_bytes == end) {
7093 subptr(var_size_in_bytes, obj);
7094 }
7095 verify_tlab();
7096 }
7098 // Preserves rbx, and rdx.
7099 void MacroAssembler::tlab_refill(Label& retry,
7100 Label& try_eden,
7101 Label& slow_case) {
7102 Register top = rax;
7103 Register t1 = rcx;
7104 Register t2 = rsi;
7105 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
7106 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
7107 Label do_refill, discard_tlab;
7109 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
7110 // No allocation in the shared eden.
7111 jmp(slow_case);
7112 }
7114 NOT_LP64(get_thread(thread_reg));
7116 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7117 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7119 // calculate amount of free space
7120 subptr(t1, top);
7121 shrptr(t1, LogHeapWordSize);
7123 // Retain tlab and allocate object in shared space if
7124 // the amount free in the tlab is too large to discard.
7125 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
7126 jcc(Assembler::lessEqual, discard_tlab);
7128 // Retain
7129 // %%% yuck as movptr...
7130 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
7131 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
7132 if (TLABStats) {
7133 // increment number of slow_allocations
7134 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
7135 }
7136 jmp(try_eden);
7138 bind(discard_tlab);
7139 if (TLABStats) {
7140 // increment number of refills
7141 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
7142 // accumulate wastage -- t1 is amount free in tlab
7143 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
7144 }
7146 // if tlab is currently allocated (top or end != null) then
7147 // fill [top, end + alignment_reserve) with array object
7148 testptr (top, top);
7149 jcc(Assembler::zero, do_refill);
7151 // set up the mark word
7152 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
7153 // set the length to the remaining space
7154 subptr(t1, typeArrayOopDesc::header_size(T_INT));
7155 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
7156 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
7157 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
7158 // set klass to intArrayKlass
7159 // dubious reloc why not an oop reloc?
7160 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
7161 // store klass last. concurrent gcs assumes klass length is valid if
7162 // klass field is not null.
7163 store_klass(top, t1);
7165 // refill the tlab with an eden allocation
7166 bind(do_refill);
7167 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7168 shlptr(t1, LogHeapWordSize);
7169 // add object_size ??
7170 eden_allocate(top, t1, 0, t2, slow_case);
7172 // Check that t1 was preserved in eden_allocate.
7173 #ifdef ASSERT
7174 if (UseTLAB) {
7175 Label ok;
7176 Register tsize = rsi;
7177 assert_different_registers(tsize, thread_reg, t1);
7178 push(tsize);
7179 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7180 shlptr(tsize, LogHeapWordSize);
7181 cmpptr(t1, tsize);
7182 jcc(Assembler::equal, ok);
7183 stop("assert(t1 != tlab size)");
7184 should_not_reach_here();
7186 bind(ok);
7187 pop(tsize);
7188 }
7189 #endif
7190 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
7191 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
7192 addptr(top, t1);
7193 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
7194 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
7195 verify_tlab();
7196 jmp(retry);
7197 }
7199 static const double pi_4 = 0.7853981633974483;
7201 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
7202 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
7203 // was attempted in this code; unfortunately it appears that the
7204 // switch to 80-bit precision and back causes this to be
7205 // unprofitable compared with simply performing a runtime call if
7206 // the argument is out of the (-pi/4, pi/4) range.
7208 Register tmp = noreg;
7209 if (!VM_Version::supports_cmov()) {
7210 // fcmp needs a temporary so preserve rbx,
7211 tmp = rbx;
7212 push(tmp);
7213 }
7215 Label slow_case, done;
7217 ExternalAddress pi4_adr = (address)&pi_4;
7218 if (reachable(pi4_adr)) {
7219 // x ?<= pi/4
7220 fld_d(pi4_adr);
7221 fld_s(1); // Stack: X PI/4 X
7222 fabs(); // Stack: |X| PI/4 X
7223 fcmp(tmp);
7224 jcc(Assembler::above, slow_case);
7226 // fastest case: -pi/4 <= x <= pi/4
7227 switch(trig) {
7228 case 's':
7229 fsin();
7230 break;
7231 case 'c':
7232 fcos();
7233 break;
7234 case 't':
7235 ftan();
7236 break;
7237 default:
7238 assert(false, "bad intrinsic");
7239 break;
7240 }
7241 jmp(done);
7242 }
7244 // slow case: runtime call
7245 bind(slow_case);
7246 // Preserve registers across runtime call
7247 pusha();
7248 int incoming_argument_and_return_value_offset = -1;
7249 if (num_fpu_regs_in_use > 1) {
7250 // Must preserve all other FPU regs (could alternatively convert
7251 // SharedRuntime::dsin and dcos into assembly routines known not to trash
7252 // FPU state, but can not trust C compiler)
7253 NEEDS_CLEANUP;
7254 // NOTE that in this case we also push the incoming argument to
7255 // the stack and restore it later; we also use this stack slot to
7256 // hold the return value from dsin or dcos.
7257 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7258 subptr(rsp, sizeof(jdouble));
7259 fstp_d(Address(rsp, 0));
7260 }
7261 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
7262 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
7263 }
7264 subptr(rsp, sizeof(jdouble));
7265 fstp_d(Address(rsp, 0));
7266 #ifdef _LP64
7267 movdbl(xmm0, Address(rsp, 0));
7268 #endif // _LP64
7270 // NOTE: we must not use call_VM_leaf here because that requires a
7271 // complete interpreter frame in debug mode -- same bug as 4387334
7272 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
7273 // do proper 64bit abi
7275 NEEDS_CLEANUP;
7276 // Need to add stack banging before this runtime call if it needs to
7277 // be taken; however, there is no generic stack banging routine at
7278 // the MacroAssembler level
7279 switch(trig) {
7280 case 's':
7281 {
7282 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
7283 }
7284 break;
7285 case 'c':
7286 {
7287 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
7288 }
7289 break;
7290 case 't':
7291 {
7292 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
7293 }
7294 break;
7295 default:
7296 assert(false, "bad intrinsic");
7297 break;
7298 }
7299 #ifdef _LP64
7300 movsd(Address(rsp, 0), xmm0);
7301 fld_d(Address(rsp, 0));
7302 #endif // _LP64
7303 addptr(rsp, sizeof(jdouble));
7304 if (num_fpu_regs_in_use > 1) {
7305 // Must save return value to stack and then restore entire FPU stack
7306 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
7307 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7308 fld_d(Address(rsp, 0));
7309 addptr(rsp, sizeof(jdouble));
7310 }
7311 }
7312 popa();
7314 // Come here with result in F-TOS
7315 bind(done);
7317 if (tmp != noreg) {
7318 pop(tmp);
7319 }
7320 }
7323 // Look up the method for a megamorphic invokeinterface call.
7324 // The target method is determined by <intf_klass, itable_index>.
7325 // The receiver klass is in recv_klass.
7326 // On success, the result will be in method_result, and execution falls through.
7327 // On failure, execution transfers to the given label.
7328 void MacroAssembler::lookup_interface_method(Register recv_klass,
7329 Register intf_klass,
7330 RegisterOrConstant itable_index,
7331 Register method_result,
7332 Register scan_temp,
7333 Label& L_no_such_interface) {
7334 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
7335 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
7336 "caller must use same register for non-constant itable index as for method");
7338 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
7339 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
7340 int itentry_off = itableMethodEntry::method_offset_in_bytes();
7341 int scan_step = itableOffsetEntry::size() * wordSize;
7342 int vte_size = vtableEntry::size() * wordSize;
7343 Address::ScaleFactor times_vte_scale = Address::times_ptr;
7344 assert(vte_size == wordSize, "else adjust times_vte_scale");
7346 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize));
7348 // %%% Could store the aligned, prescaled offset in the klassoop.
7349 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
7350 if (HeapWordsPerLong > 1) {
7351 // Round up to align_object_offset boundary
7352 // see code for instanceKlass::start_of_itable!
7353 round_to(scan_temp, BytesPerLong);
7354 }
7356 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
7357 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
7358 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
7360 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
7361 // if (scan->interface() == intf) {
7362 // result = (klass + scan->offset() + itable_index);
7363 // }
7364 // }
7365 Label search, found_method;
7367 for (int peel = 1; peel >= 0; peel--) {
7368 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
7369 cmpptr(intf_klass, method_result);
7371 if (peel) {
7372 jccb(Assembler::equal, found_method);
7373 } else {
7374 jccb(Assembler::notEqual, search);
7375 // (invert the test to fall through to found_method...)
7376 }
7378 if (!peel) break;
7380 bind(search);
7382 // Check that the previous entry is non-null. A null entry means that
7383 // the receiver class doesn't implement the interface, and wasn't the
7384 // same as when the caller was compiled.
7385 testptr(method_result, method_result);
7386 jcc(Assembler::zero, L_no_such_interface);
7387 addptr(scan_temp, scan_step);
7388 }
7390 bind(found_method);
7392 // Got a hit.
7393 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
7394 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
7395 }
7398 void MacroAssembler::check_klass_subtype(Register sub_klass,
7399 Register super_klass,
7400 Register temp_reg,
7401 Label& L_success) {
7402 Label L_failure;
7403 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
7404 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
7405 bind(L_failure);
7406 }
7409 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
7410 Register super_klass,
7411 Register temp_reg,
7412 Label* L_success,
7413 Label* L_failure,
7414 Label* L_slow_path,
7415 RegisterOrConstant super_check_offset) {
7416 assert_different_registers(sub_klass, super_klass, temp_reg);
7417 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
7418 if (super_check_offset.is_register()) {
7419 assert_different_registers(sub_klass, super_klass,
7420 super_check_offset.as_register());
7421 } else if (must_load_sco) {
7422 assert(temp_reg != noreg, "supply either a temp or a register offset");
7423 }
7425 Label L_fallthrough;
7426 int label_nulls = 0;
7427 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7428 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7429 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
7430 assert(label_nulls <= 1, "at most one NULL in the batch");
7432 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7433 Klass::secondary_super_cache_offset_in_bytes());
7434 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
7435 Klass::super_check_offset_offset_in_bytes());
7436 Address super_check_offset_addr(super_klass, sco_offset);
7438 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
7439 // range of a jccb. If this routine grows larger, reconsider at
7440 // least some of these.
7441 #define local_jcc(assembler_cond, label) \
7442 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
7443 else jcc( assembler_cond, label) /*omit semi*/
7445 // Hacked jmp, which may only be used just before L_fallthrough.
7446 #define final_jmp(label) \
7447 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
7448 else jmp(label) /*omit semi*/
7450 // If the pointers are equal, we are done (e.g., String[] elements).
7451 // This self-check enables sharing of secondary supertype arrays among
7452 // non-primary types such as array-of-interface. Otherwise, each such
7453 // type would need its own customized SSA.
7454 // We move this check to the front of the fast path because many
7455 // type checks are in fact trivially successful in this manner,
7456 // so we get a nicely predicted branch right at the start of the check.
7457 cmpptr(sub_klass, super_klass);
7458 local_jcc(Assembler::equal, *L_success);
7460 // Check the supertype display:
7461 if (must_load_sco) {
7462 // Positive movl does right thing on LP64.
7463 movl(temp_reg, super_check_offset_addr);
7464 super_check_offset = RegisterOrConstant(temp_reg);
7465 }
7466 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
7467 cmpptr(super_klass, super_check_addr); // load displayed supertype
7469 // This check has worked decisively for primary supers.
7470 // Secondary supers are sought in the super_cache ('super_cache_addr').
7471 // (Secondary supers are interfaces and very deeply nested subtypes.)
7472 // This works in the same check above because of a tricky aliasing
7473 // between the super_cache and the primary super display elements.
7474 // (The 'super_check_addr' can address either, as the case requires.)
7475 // Note that the cache is updated below if it does not help us find
7476 // what we need immediately.
7477 // So if it was a primary super, we can just fail immediately.
7478 // Otherwise, it's the slow path for us (no success at this point).
7480 if (super_check_offset.is_register()) {
7481 local_jcc(Assembler::equal, *L_success);
7482 cmpl(super_check_offset.as_register(), sc_offset);
7483 if (L_failure == &L_fallthrough) {
7484 local_jcc(Assembler::equal, *L_slow_path);
7485 } else {
7486 local_jcc(Assembler::notEqual, *L_failure);
7487 final_jmp(*L_slow_path);
7488 }
7489 } else if (super_check_offset.as_constant() == sc_offset) {
7490 // Need a slow path; fast failure is impossible.
7491 if (L_slow_path == &L_fallthrough) {
7492 local_jcc(Assembler::equal, *L_success);
7493 } else {
7494 local_jcc(Assembler::notEqual, *L_slow_path);
7495 final_jmp(*L_success);
7496 }
7497 } else {
7498 // No slow path; it's a fast decision.
7499 if (L_failure == &L_fallthrough) {
7500 local_jcc(Assembler::equal, *L_success);
7501 } else {
7502 local_jcc(Assembler::notEqual, *L_failure);
7503 final_jmp(*L_success);
7504 }
7505 }
7507 bind(L_fallthrough);
7509 #undef local_jcc
7510 #undef final_jmp
7511 }
7514 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
7515 Register super_klass,
7516 Register temp_reg,
7517 Register temp2_reg,
7518 Label* L_success,
7519 Label* L_failure,
7520 bool set_cond_codes) {
7521 assert_different_registers(sub_klass, super_klass, temp_reg);
7522 if (temp2_reg != noreg)
7523 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
7524 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
7526 Label L_fallthrough;
7527 int label_nulls = 0;
7528 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7529 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7530 assert(label_nulls <= 1, "at most one NULL in the batch");
7532 // a couple of useful fields in sub_klass:
7533 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
7534 Klass::secondary_supers_offset_in_bytes());
7535 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7536 Klass::secondary_super_cache_offset_in_bytes());
7537 Address secondary_supers_addr(sub_klass, ss_offset);
7538 Address super_cache_addr( sub_klass, sc_offset);
7540 // Do a linear scan of the secondary super-klass chain.
7541 // This code is rarely used, so simplicity is a virtue here.
7542 // The repne_scan instruction uses fixed registers, which we must spill.
7543 // Don't worry too much about pre-existing connections with the input regs.
7545 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
7546 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
7548 // Get super_klass value into rax (even if it was in rdi or rcx).
7549 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
7550 if (super_klass != rax || UseCompressedOops) {
7551 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
7552 mov(rax, super_klass);
7553 }
7554 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
7555 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
7557 #ifndef PRODUCT
7558 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
7559 ExternalAddress pst_counter_addr((address) pst_counter);
7560 NOT_LP64( incrementl(pst_counter_addr) );
7561 LP64_ONLY( lea(rcx, pst_counter_addr) );
7562 LP64_ONLY( incrementl(Address(rcx, 0)) );
7563 #endif //PRODUCT
7565 // We will consult the secondary-super array.
7566 movptr(rdi, secondary_supers_addr);
7567 // Load the array length. (Positive movl does right thing on LP64.)
7568 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
7569 // Skip to start of data.
7570 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
7572 // Scan RCX words at [RDI] for an occurrence of RAX.
7573 // Set NZ/Z based on last compare.
7574 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
7575 // not change flags (only scas instruction which is repeated sets flags).
7576 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
7577 #ifdef _LP64
7578 // This part is tricky, as values in supers array could be 32 or 64 bit wide
7579 // and we store values in objArrays always encoded, thus we need to encode
7580 // the value of rax before repne. Note that rax is dead after the repne.
7581 if (UseCompressedOops) {
7582 encode_heap_oop_not_null(rax); // Changes flags.
7583 // The superclass is never null; it would be a basic system error if a null
7584 // pointer were to sneak in here. Note that we have already loaded the
7585 // Klass::super_check_offset from the super_klass in the fast path,
7586 // so if there is a null in that register, we are already in the afterlife.
7587 testl(rax,rax); // Set Z = 0
7588 repne_scanl();
7589 } else
7590 #endif // _LP64
7591 {
7592 testptr(rax,rax); // Set Z = 0
7593 repne_scan();
7594 }
7595 // Unspill the temp. registers:
7596 if (pushed_rdi) pop(rdi);
7597 if (pushed_rcx) pop(rcx);
7598 if (pushed_rax) pop(rax);
7600 if (set_cond_codes) {
7601 // Special hack for the AD files: rdi is guaranteed non-zero.
7602 assert(!pushed_rdi, "rdi must be left non-NULL");
7603 // Also, the condition codes are properly set Z/NZ on succeed/failure.
7604 }
7606 if (L_failure == &L_fallthrough)
7607 jccb(Assembler::notEqual, *L_failure);
7608 else jcc(Assembler::notEqual, *L_failure);
7610 // Success. Cache the super we found and proceed in triumph.
7611 movptr(super_cache_addr, super_klass);
7613 if (L_success != &L_fallthrough) {
7614 jmp(*L_success);
7615 }
7617 #undef IS_A_TEMP
7619 bind(L_fallthrough);
7620 }
7623 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7624 ucomisd(dst, as_Address(src));
7625 }
7627 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7628 ucomiss(dst, as_Address(src));
7629 }
7631 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7632 if (reachable(src)) {
7633 xorpd(dst, as_Address(src));
7634 } else {
7635 lea(rscratch1, src);
7636 xorpd(dst, Address(rscratch1, 0));
7637 }
7638 }
7640 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7641 if (reachable(src)) {
7642 xorps(dst, as_Address(src));
7643 } else {
7644 lea(rscratch1, src);
7645 xorps(dst, Address(rscratch1, 0));
7646 }
7647 }
7649 void MacroAssembler::verify_oop(Register reg, const char* s) {
7650 if (!VerifyOops) return;
7652 // Pass register number to verify_oop_subroutine
7653 char* b = new char[strlen(s) + 50];
7654 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
7655 #ifdef _LP64
7656 push(rscratch1); // save r10, trashed by movptr()
7657 #endif
7658 push(rax); // save rax,
7659 push(reg); // pass register argument
7660 ExternalAddress buffer((address) b);
7661 // avoid using pushptr, as it modifies scratch registers
7662 // and our contract is not to modify anything
7663 movptr(rax, buffer.addr());
7664 push(rax);
7665 // call indirectly to solve generation ordering problem
7666 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7667 call(rax);
7668 // Caller pops the arguments (oop, message) and restores rax, r10
7669 }
7672 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
7673 Register tmp,
7674 int offset) {
7675 intptr_t value = *delayed_value_addr;
7676 if (value != 0)
7677 return RegisterOrConstant(value + offset);
7679 // load indirectly to solve generation ordering problem
7680 movptr(tmp, ExternalAddress((address) delayed_value_addr));
7682 #ifdef ASSERT
7683 { Label L;
7684 testptr(tmp, tmp);
7685 if (WizardMode) {
7686 jcc(Assembler::notZero, L);
7687 char* buf = new char[40];
7688 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
7689 stop(buf);
7690 } else {
7691 jccb(Assembler::notZero, L);
7692 hlt();
7693 }
7694 bind(L);
7695 }
7696 #endif
7698 if (offset != 0)
7699 addptr(tmp, offset);
7701 return RegisterOrConstant(tmp);
7702 }
7705 // registers on entry:
7706 // - rax ('check' register): required MethodType
7707 // - rcx: method handle
7708 // - rdx, rsi, or ?: killable temp
7709 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
7710 Register temp_reg,
7711 Label& wrong_method_type) {
7712 Address type_addr(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg));
7713 // compare method type against that of the receiver
7714 if (UseCompressedOops) {
7715 load_heap_oop(temp_reg, type_addr);
7716 cmpptr(mtype_reg, temp_reg);
7717 } else {
7718 cmpptr(mtype_reg, type_addr);
7719 }
7720 jcc(Assembler::notEqual, wrong_method_type);
7721 }
7724 // A method handle has a "vmslots" field which gives the size of its
7725 // argument list in JVM stack slots. This field is either located directly
7726 // in every method handle, or else is indirectly accessed through the
7727 // method handle's MethodType. This macro hides the distinction.
7728 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
7729 Register temp_reg) {
7730 assert_different_registers(vmslots_reg, mh_reg, temp_reg);
7731 // load mh.type.form.vmslots
7732 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) {
7733 // hoist vmslots into every mh to avoid dependent load chain
7734 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg)));
7735 } else {
7736 Register temp2_reg = vmslots_reg;
7737 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)));
7738 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg)));
7739 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)));
7740 }
7741 }
7744 // registers on entry:
7745 // - rcx: method handle
7746 // - rdx: killable temp (interpreted only)
7747 // - rax: killable temp (compiled only)
7748 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) {
7749 assert(mh_reg == rcx, "caller must put MH object in rcx");
7750 assert_different_registers(mh_reg, temp_reg);
7752 // pick out the interpreted side of the handler
7753 // NOTE: vmentry is not an oop!
7754 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg)));
7756 // off we go...
7757 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes()));
7759 // for the various stubs which take control at this point,
7760 // see MethodHandles::generate_method_handle_stub
7761 }
7764 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
7765 int extra_slot_offset) {
7766 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
7767 int stackElementSize = Interpreter::stackElementSize;
7768 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
7769 #ifdef ASSERT
7770 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
7771 assert(offset1 - offset == stackElementSize, "correct arithmetic");
7772 #endif
7773 Register scale_reg = noreg;
7774 Address::ScaleFactor scale_factor = Address::no_scale;
7775 if (arg_slot.is_constant()) {
7776 offset += arg_slot.as_constant() * stackElementSize;
7777 } else {
7778 scale_reg = arg_slot.as_register();
7779 scale_factor = Address::times(stackElementSize);
7780 }
7781 offset += wordSize; // return PC is on stack
7782 return Address(rsp, scale_reg, scale_factor, offset);
7783 }
7786 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
7787 if (!VerifyOops) return;
7789 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
7790 // Pass register number to verify_oop_subroutine
7791 char* b = new char[strlen(s) + 50];
7792 sprintf(b, "verify_oop_addr: %s", s);
7794 #ifdef _LP64
7795 push(rscratch1); // save r10, trashed by movptr()
7796 #endif
7797 push(rax); // save rax,
7798 // addr may contain rsp so we will have to adjust it based on the push
7799 // we just did
7800 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
7801 // stores rax into addr which is backwards of what was intended.
7802 if (addr.uses(rsp)) {
7803 lea(rax, addr);
7804 pushptr(Address(rax, BytesPerWord));
7805 } else {
7806 pushptr(addr);
7807 }
7809 ExternalAddress buffer((address) b);
7810 // pass msg argument
7811 // avoid using pushptr, as it modifies scratch registers
7812 // and our contract is not to modify anything
7813 movptr(rax, buffer.addr());
7814 push(rax);
7816 // call indirectly to solve generation ordering problem
7817 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7818 call(rax);
7819 // Caller pops the arguments (addr, message) and restores rax, r10.
7820 }
7822 void MacroAssembler::verify_tlab() {
7823 #ifdef ASSERT
7824 if (UseTLAB && VerifyOops) {
7825 Label next, ok;
7826 Register t1 = rsi;
7827 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
7829 push(t1);
7830 NOT_LP64(push(thread_reg));
7831 NOT_LP64(get_thread(thread_reg));
7833 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7834 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
7835 jcc(Assembler::aboveEqual, next);
7836 stop("assert(top >= start)");
7837 should_not_reach_here();
7839 bind(next);
7840 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7841 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7842 jcc(Assembler::aboveEqual, ok);
7843 stop("assert(top <= end)");
7844 should_not_reach_here();
7846 bind(ok);
7847 NOT_LP64(pop(thread_reg));
7848 pop(t1);
7849 }
7850 #endif
7851 }
7853 class ControlWord {
7854 public:
7855 int32_t _value;
7857 int rounding_control() const { return (_value >> 10) & 3 ; }
7858 int precision_control() const { return (_value >> 8) & 3 ; }
7859 bool precision() const { return ((_value >> 5) & 1) != 0; }
7860 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7861 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7862 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7863 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7864 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7866 void print() const {
7867 // rounding control
7868 const char* rc;
7869 switch (rounding_control()) {
7870 case 0: rc = "round near"; break;
7871 case 1: rc = "round down"; break;
7872 case 2: rc = "round up "; break;
7873 case 3: rc = "chop "; break;
7874 };
7875 // precision control
7876 const char* pc;
7877 switch (precision_control()) {
7878 case 0: pc = "24 bits "; break;
7879 case 1: pc = "reserved"; break;
7880 case 2: pc = "53 bits "; break;
7881 case 3: pc = "64 bits "; break;
7882 };
7883 // flags
7884 char f[9];
7885 f[0] = ' ';
7886 f[1] = ' ';
7887 f[2] = (precision ()) ? 'P' : 'p';
7888 f[3] = (underflow ()) ? 'U' : 'u';
7889 f[4] = (overflow ()) ? 'O' : 'o';
7890 f[5] = (zero_divide ()) ? 'Z' : 'z';
7891 f[6] = (denormalized()) ? 'D' : 'd';
7892 f[7] = (invalid ()) ? 'I' : 'i';
7893 f[8] = '\x0';
7894 // output
7895 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
7896 }
7898 };
7900 class StatusWord {
7901 public:
7902 int32_t _value;
7904 bool busy() const { return ((_value >> 15) & 1) != 0; }
7905 bool C3() const { return ((_value >> 14) & 1) != 0; }
7906 bool C2() const { return ((_value >> 10) & 1) != 0; }
7907 bool C1() const { return ((_value >> 9) & 1) != 0; }
7908 bool C0() const { return ((_value >> 8) & 1) != 0; }
7909 int top() const { return (_value >> 11) & 7 ; }
7910 bool error_status() const { return ((_value >> 7) & 1) != 0; }
7911 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
7912 bool precision() const { return ((_value >> 5) & 1) != 0; }
7913 bool underflow() const { return ((_value >> 4) & 1) != 0; }
7914 bool overflow() const { return ((_value >> 3) & 1) != 0; }
7915 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
7916 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
7917 bool invalid() const { return ((_value >> 0) & 1) != 0; }
7919 void print() const {
7920 // condition codes
7921 char c[5];
7922 c[0] = (C3()) ? '3' : '-';
7923 c[1] = (C2()) ? '2' : '-';
7924 c[2] = (C1()) ? '1' : '-';
7925 c[3] = (C0()) ? '0' : '-';
7926 c[4] = '\x0';
7927 // flags
7928 char f[9];
7929 f[0] = (error_status()) ? 'E' : '-';
7930 f[1] = (stack_fault ()) ? 'S' : '-';
7931 f[2] = (precision ()) ? 'P' : '-';
7932 f[3] = (underflow ()) ? 'U' : '-';
7933 f[4] = (overflow ()) ? 'O' : '-';
7934 f[5] = (zero_divide ()) ? 'Z' : '-';
7935 f[6] = (denormalized()) ? 'D' : '-';
7936 f[7] = (invalid ()) ? 'I' : '-';
7937 f[8] = '\x0';
7938 // output
7939 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
7940 }
7942 };
7944 class TagWord {
7945 public:
7946 int32_t _value;
7948 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
7950 void print() const {
7951 printf("%04x", _value & 0xFFFF);
7952 }
7954 };
7956 class FPU_Register {
7957 public:
7958 int32_t _m0;
7959 int32_t _m1;
7960 int16_t _ex;
7962 bool is_indefinite() const {
7963 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
7964 }
7966 void print() const {
7967 char sign = (_ex < 0) ? '-' : '+';
7968 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
7969 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
7970 };
7972 };
7974 class FPU_State {
7975 public:
7976 enum {
7977 register_size = 10,
7978 number_of_registers = 8,
7979 register_mask = 7
7980 };
7982 ControlWord _control_word;
7983 StatusWord _status_word;
7984 TagWord _tag_word;
7985 int32_t _error_offset;
7986 int32_t _error_selector;
7987 int32_t _data_offset;
7988 int32_t _data_selector;
7989 int8_t _register[register_size * number_of_registers];
7991 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
7992 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
7994 const char* tag_as_string(int tag) const {
7995 switch (tag) {
7996 case 0: return "valid";
7997 case 1: return "zero";
7998 case 2: return "special";
7999 case 3: return "empty";
8000 }
8001 ShouldNotReachHere();
8002 return NULL;
8003 }
8005 void print() const {
8006 // print computation registers
8007 { int t = _status_word.top();
8008 for (int i = 0; i < number_of_registers; i++) {
8009 int j = (i - t) & register_mask;
8010 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
8011 st(j)->print();
8012 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
8013 }
8014 }
8015 printf("\n");
8016 // print control registers
8017 printf("ctrl = "); _control_word.print(); printf("\n");
8018 printf("stat = "); _status_word .print(); printf("\n");
8019 printf("tags = "); _tag_word .print(); printf("\n");
8020 }
8022 };
8024 class Flag_Register {
8025 public:
8026 int32_t _value;
8028 bool overflow() const { return ((_value >> 11) & 1) != 0; }
8029 bool direction() const { return ((_value >> 10) & 1) != 0; }
8030 bool sign() const { return ((_value >> 7) & 1) != 0; }
8031 bool zero() const { return ((_value >> 6) & 1) != 0; }
8032 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
8033 bool parity() const { return ((_value >> 2) & 1) != 0; }
8034 bool carry() const { return ((_value >> 0) & 1) != 0; }
8036 void print() const {
8037 // flags
8038 char f[8];
8039 f[0] = (overflow ()) ? 'O' : '-';
8040 f[1] = (direction ()) ? 'D' : '-';
8041 f[2] = (sign ()) ? 'S' : '-';
8042 f[3] = (zero ()) ? 'Z' : '-';
8043 f[4] = (auxiliary_carry()) ? 'A' : '-';
8044 f[5] = (parity ()) ? 'P' : '-';
8045 f[6] = (carry ()) ? 'C' : '-';
8046 f[7] = '\x0';
8047 // output
8048 printf("%08x flags = %s", _value, f);
8049 }
8051 };
8053 class IU_Register {
8054 public:
8055 int32_t _value;
8057 void print() const {
8058 printf("%08x %11d", _value, _value);
8059 }
8061 };
8063 class IU_State {
8064 public:
8065 Flag_Register _eflags;
8066 IU_Register _rdi;
8067 IU_Register _rsi;
8068 IU_Register _rbp;
8069 IU_Register _rsp;
8070 IU_Register _rbx;
8071 IU_Register _rdx;
8072 IU_Register _rcx;
8073 IU_Register _rax;
8075 void print() const {
8076 // computation registers
8077 printf("rax, = "); _rax.print(); printf("\n");
8078 printf("rbx, = "); _rbx.print(); printf("\n");
8079 printf("rcx = "); _rcx.print(); printf("\n");
8080 printf("rdx = "); _rdx.print(); printf("\n");
8081 printf("rdi = "); _rdi.print(); printf("\n");
8082 printf("rsi = "); _rsi.print(); printf("\n");
8083 printf("rbp, = "); _rbp.print(); printf("\n");
8084 printf("rsp = "); _rsp.print(); printf("\n");
8085 printf("\n");
8086 // control registers
8087 printf("flgs = "); _eflags.print(); printf("\n");
8088 }
8089 };
8092 class CPU_State {
8093 public:
8094 FPU_State _fpu_state;
8095 IU_State _iu_state;
8097 void print() const {
8098 printf("--------------------------------------------------\n");
8099 _iu_state .print();
8100 printf("\n");
8101 _fpu_state.print();
8102 printf("--------------------------------------------------\n");
8103 }
8105 };
8108 static void _print_CPU_state(CPU_State* state) {
8109 state->print();
8110 };
8113 void MacroAssembler::print_CPU_state() {
8114 push_CPU_state();
8115 push(rsp); // pass CPU state
8116 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
8117 addptr(rsp, wordSize); // discard argument
8118 pop_CPU_state();
8119 }
8122 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
8123 static int counter = 0;
8124 FPU_State* fs = &state->_fpu_state;
8125 counter++;
8126 // For leaf calls, only verify that the top few elements remain empty.
8127 // We only need 1 empty at the top for C2 code.
8128 if( stack_depth < 0 ) {
8129 if( fs->tag_for_st(7) != 3 ) {
8130 printf("FPR7 not empty\n");
8131 state->print();
8132 assert(false, "error");
8133 return false;
8134 }
8135 return true; // All other stack states do not matter
8136 }
8138 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
8139 "bad FPU control word");
8141 // compute stack depth
8142 int i = 0;
8143 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
8144 int d = i;
8145 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
8146 // verify findings
8147 if (i != FPU_State::number_of_registers) {
8148 // stack not contiguous
8149 printf("%s: stack not contiguous at ST%d\n", s, i);
8150 state->print();
8151 assert(false, "error");
8152 return false;
8153 }
8154 // check if computed stack depth corresponds to expected stack depth
8155 if (stack_depth < 0) {
8156 // expected stack depth is -stack_depth or less
8157 if (d > -stack_depth) {
8158 // too many elements on the stack
8159 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
8160 state->print();
8161 assert(false, "error");
8162 return false;
8163 }
8164 } else {
8165 // expected stack depth is stack_depth
8166 if (d != stack_depth) {
8167 // wrong stack depth
8168 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
8169 state->print();
8170 assert(false, "error");
8171 return false;
8172 }
8173 }
8174 // everything is cool
8175 return true;
8176 }
8179 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
8180 if (!VerifyFPU) return;
8181 push_CPU_state();
8182 push(rsp); // pass CPU state
8183 ExternalAddress msg((address) s);
8184 // pass message string s
8185 pushptr(msg.addr());
8186 push(stack_depth); // pass stack depth
8187 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
8188 addptr(rsp, 3 * wordSize); // discard arguments
8189 // check for error
8190 { Label L;
8191 testl(rax, rax);
8192 jcc(Assembler::notZero, L);
8193 int3(); // break if error condition
8194 bind(L);
8195 }
8196 pop_CPU_state();
8197 }
8199 void MacroAssembler::load_klass(Register dst, Register src) {
8200 #ifdef _LP64
8201 if (UseCompressedOops) {
8202 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8203 decode_heap_oop_not_null(dst);
8204 } else
8205 #endif
8206 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8207 }
8209 void MacroAssembler::load_prototype_header(Register dst, Register src) {
8210 #ifdef _LP64
8211 if (UseCompressedOops) {
8212 assert (Universe::heap() != NULL, "java heap should be initialized");
8213 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8214 if (Universe::narrow_oop_shift() != 0) {
8215 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8216 if (LogMinObjAlignmentInBytes == Address::times_8) {
8217 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8218 } else {
8219 // OK to use shift since we don't need to preserve flags.
8220 shlq(dst, LogMinObjAlignmentInBytes);
8221 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8222 }
8223 } else {
8224 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8225 }
8226 } else
8227 #endif
8228 {
8229 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8230 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8231 }
8232 }
8234 void MacroAssembler::store_klass(Register dst, Register src) {
8235 #ifdef _LP64
8236 if (UseCompressedOops) {
8237 encode_heap_oop_not_null(src);
8238 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8239 } else
8240 #endif
8241 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8242 }
8244 void MacroAssembler::load_heap_oop(Register dst, Address src) {
8245 #ifdef _LP64
8246 if (UseCompressedOops) {
8247 movl(dst, src);
8248 decode_heap_oop(dst);
8249 } else
8250 #endif
8251 movptr(dst, src);
8252 }
8254 void MacroAssembler::store_heap_oop(Address dst, Register src) {
8255 #ifdef _LP64
8256 if (UseCompressedOops) {
8257 assert(!dst.uses(src), "not enough registers");
8258 encode_heap_oop(src);
8259 movl(dst, src);
8260 } else
8261 #endif
8262 movptr(dst, src);
8263 }
8265 // Used for storing NULLs.
8266 void MacroAssembler::store_heap_oop_null(Address dst) {
8267 #ifdef _LP64
8268 if (UseCompressedOops) {
8269 movl(dst, (int32_t)NULL_WORD);
8270 } else {
8271 movslq(dst, (int32_t)NULL_WORD);
8272 }
8273 #else
8274 movl(dst, (int32_t)NULL_WORD);
8275 #endif
8276 }
8278 #ifdef _LP64
8279 void MacroAssembler::store_klass_gap(Register dst, Register src) {
8280 if (UseCompressedOops) {
8281 // Store to klass gap in destination
8282 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
8283 }
8284 }
8286 #ifdef ASSERT
8287 void MacroAssembler::verify_heapbase(const char* msg) {
8288 assert (UseCompressedOops, "should be compressed");
8289 assert (Universe::heap() != NULL, "java heap should be initialized");
8290 if (CheckCompressedOops) {
8291 Label ok;
8292 push(rscratch1); // cmpptr trashes rscratch1
8293 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8294 jcc(Assembler::equal, ok);
8295 stop(msg);
8296 bind(ok);
8297 pop(rscratch1);
8298 }
8299 }
8300 #endif
8302 // Algorithm must match oop.inline.hpp encode_heap_oop.
8303 void MacroAssembler::encode_heap_oop(Register r) {
8304 #ifdef ASSERT
8305 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
8306 #endif
8307 verify_oop(r, "broken oop in encode_heap_oop");
8308 if (Universe::narrow_oop_base() == NULL) {
8309 if (Universe::narrow_oop_shift() != 0) {
8310 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8311 shrq(r, LogMinObjAlignmentInBytes);
8312 }
8313 return;
8314 }
8315 testq(r, r);
8316 cmovq(Assembler::equal, r, r12_heapbase);
8317 subq(r, r12_heapbase);
8318 shrq(r, LogMinObjAlignmentInBytes);
8319 }
8321 void MacroAssembler::encode_heap_oop_not_null(Register r) {
8322 #ifdef ASSERT
8323 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
8324 if (CheckCompressedOops) {
8325 Label ok;
8326 testq(r, r);
8327 jcc(Assembler::notEqual, ok);
8328 stop("null oop passed to encode_heap_oop_not_null");
8329 bind(ok);
8330 }
8331 #endif
8332 verify_oop(r, "broken oop in encode_heap_oop_not_null");
8333 if (Universe::narrow_oop_base() != NULL) {
8334 subq(r, r12_heapbase);
8335 }
8336 if (Universe::narrow_oop_shift() != 0) {
8337 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8338 shrq(r, LogMinObjAlignmentInBytes);
8339 }
8340 }
8342 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
8343 #ifdef ASSERT
8344 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
8345 if (CheckCompressedOops) {
8346 Label ok;
8347 testq(src, src);
8348 jcc(Assembler::notEqual, ok);
8349 stop("null oop passed to encode_heap_oop_not_null2");
8350 bind(ok);
8351 }
8352 #endif
8353 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
8354 if (dst != src) {
8355 movq(dst, src);
8356 }
8357 if (Universe::narrow_oop_base() != NULL) {
8358 subq(dst, r12_heapbase);
8359 }
8360 if (Universe::narrow_oop_shift() != 0) {
8361 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8362 shrq(dst, LogMinObjAlignmentInBytes);
8363 }
8364 }
8366 void MacroAssembler::decode_heap_oop(Register r) {
8367 #ifdef ASSERT
8368 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
8369 #endif
8370 if (Universe::narrow_oop_base() == NULL) {
8371 if (Universe::narrow_oop_shift() != 0) {
8372 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8373 shlq(r, LogMinObjAlignmentInBytes);
8374 }
8375 } else {
8376 Label done;
8377 shlq(r, LogMinObjAlignmentInBytes);
8378 jccb(Assembler::equal, done);
8379 addq(r, r12_heapbase);
8380 bind(done);
8381 }
8382 verify_oop(r, "broken oop in decode_heap_oop");
8383 }
8385 void MacroAssembler::decode_heap_oop_not_null(Register r) {
8386 // Note: it will change flags
8387 assert (UseCompressedOops, "should only be used for compressed headers");
8388 assert (Universe::heap() != NULL, "java heap should be initialized");
8389 // Cannot assert, unverified entry point counts instructions (see .ad file)
8390 // vtableStubs also counts instructions in pd_code_size_limit.
8391 // Also do not verify_oop as this is called by verify_oop.
8392 if (Universe::narrow_oop_shift() != 0) {
8393 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8394 shlq(r, LogMinObjAlignmentInBytes);
8395 if (Universe::narrow_oop_base() != NULL) {
8396 addq(r, r12_heapbase);
8397 }
8398 } else {
8399 assert (Universe::narrow_oop_base() == NULL, "sanity");
8400 }
8401 }
8403 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
8404 // Note: it will change flags
8405 assert (UseCompressedOops, "should only be used for compressed headers");
8406 assert (Universe::heap() != NULL, "java heap should be initialized");
8407 // Cannot assert, unverified entry point counts instructions (see .ad file)
8408 // vtableStubs also counts instructions in pd_code_size_limit.
8409 // Also do not verify_oop as this is called by verify_oop.
8410 if (Universe::narrow_oop_shift() != 0) {
8411 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8412 if (LogMinObjAlignmentInBytes == Address::times_8) {
8413 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
8414 } else {
8415 if (dst != src) {
8416 movq(dst, src);
8417 }
8418 shlq(dst, LogMinObjAlignmentInBytes);
8419 if (Universe::narrow_oop_base() != NULL) {
8420 addq(dst, r12_heapbase);
8421 }
8422 }
8423 } else {
8424 assert (Universe::narrow_oop_base() == NULL, "sanity");
8425 if (dst != src) {
8426 movq(dst, src);
8427 }
8428 }
8429 }
8431 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
8432 assert (UseCompressedOops, "should only be used for compressed headers");
8433 assert (Universe::heap() != NULL, "java heap should be initialized");
8434 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8435 int oop_index = oop_recorder()->find_index(obj);
8436 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8437 mov_narrow_oop(dst, oop_index, rspec);
8438 }
8440 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
8441 assert (UseCompressedOops, "should only be used for compressed headers");
8442 assert (Universe::heap() != NULL, "java heap should be initialized");
8443 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8444 int oop_index = oop_recorder()->find_index(obj);
8445 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8446 mov_narrow_oop(dst, oop_index, rspec);
8447 }
8449 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
8450 assert (UseCompressedOops, "should only be used for compressed headers");
8451 assert (Universe::heap() != NULL, "java heap should be initialized");
8452 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8453 int oop_index = oop_recorder()->find_index(obj);
8454 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8455 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8456 }
8458 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
8459 assert (UseCompressedOops, "should only be used for compressed headers");
8460 assert (Universe::heap() != NULL, "java heap should be initialized");
8461 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8462 int oop_index = oop_recorder()->find_index(obj);
8463 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8464 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8465 }
8467 void MacroAssembler::reinit_heapbase() {
8468 if (UseCompressedOops) {
8469 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8470 }
8471 }
8472 #endif // _LP64
8474 // IndexOf substring.
8475 void MacroAssembler::string_indexof(Register str1, Register str2,
8476 Register cnt1, Register cnt2, Register result,
8477 XMMRegister vec, Register tmp) {
8478 assert(UseSSE42Intrinsics, "SSE4.2 is required");
8480 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
8481 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP;
8483 push(str1); // string addr
8484 push(str2); // substr addr
8485 push(cnt2); // substr count
8486 jmpb(PREP_FOR_SCAN);
8488 // Substr count saved at sp
8489 // Substr saved at sp+1*wordSize
8490 // String saved at sp+2*wordSize
8492 // Reload substr for rescan
8493 bind(RELOAD_SUBSTR);
8494 movl(cnt2, Address(rsp, 0));
8495 movptr(str2, Address(rsp, wordSize));
8496 // We came here after the beginninig of the substring was
8497 // matched but the rest of it was not so we need to search
8498 // again. Start from the next element after the previous match.
8499 subptr(str1, result); // Restore counter
8500 shrl(str1, 1);
8501 addl(cnt1, str1);
8502 decrementl(cnt1);
8503 lea(str1, Address(result, 2)); // Reload string
8505 // Load substr
8506 bind(PREP_FOR_SCAN);
8507 movdqu(vec, Address(str2, 0));
8508 addl(cnt1, 8); // prime the loop
8509 subptr(str1, 16);
8511 // Scan string for substr in 16-byte vectors
8512 bind(SCAN_TO_SUBSTR);
8513 subl(cnt1, 8);
8514 addptr(str1, 16);
8516 // pcmpestri
8517 // inputs:
8518 // xmm - substring
8519 // rax - substring length (elements count)
8520 // mem - scaned string
8521 // rdx - string length (elements count)
8522 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
8523 // outputs:
8524 // rcx - matched index in string
8525 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
8527 pcmpestri(vec, Address(str1, 0), 0x0d);
8528 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
8529 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
8531 // Fallthrough: found a potential substr
8533 // Make sure string is still long enough
8534 subl(cnt1, tmp);
8535 cmpl(cnt1, cnt2);
8536 jccb(Assembler::negative, RET_NOT_FOUND);
8537 // Compute start addr of substr
8538 lea(str1, Address(str1, tmp, Address::times_2));
8539 movptr(result, str1); // save
8541 // Compare potential substr
8542 addl(cnt1, 8); // prime the loop
8543 addl(cnt2, 8);
8544 subptr(str1, 16);
8545 subptr(str2, 16);
8547 // Scan 16-byte vectors of string and substr
8548 bind(SCAN_SUBSTR);
8549 subl(cnt1, 8);
8550 subl(cnt2, 8);
8551 addptr(str1, 16);
8552 addptr(str2, 16);
8553 movdqu(vec, Address(str2, 0));
8554 pcmpestri(vec, Address(str1, 0), 0x0d);
8555 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
8556 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
8558 // Compute substr offset
8559 subptr(result, Address(rsp, 2*wordSize));
8560 shrl(result, 1); // index
8561 jmpb(CLEANUP);
8563 bind(RET_NOT_FOUND);
8564 movl(result, -1);
8566 bind(CLEANUP);
8567 addptr(rsp, 3*wordSize);
8568 }
8570 // Compare strings.
8571 void MacroAssembler::string_compare(Register str1, Register str2,
8572 Register cnt1, Register cnt2, Register result,
8573 XMMRegister vec1, XMMRegister vec2) {
8574 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
8576 // Compute the minimum of the string lengths and the
8577 // difference of the string lengths (stack).
8578 // Do the conditional move stuff
8579 movl(result, cnt1);
8580 subl(cnt1, cnt2);
8581 push(cnt1);
8582 if (VM_Version::supports_cmov()) {
8583 cmovl(Assembler::lessEqual, cnt2, result);
8584 } else {
8585 Label GT_LABEL;
8586 jccb(Assembler::greater, GT_LABEL);
8587 movl(cnt2, result);
8588 bind(GT_LABEL);
8589 }
8591 // Is the minimum length zero?
8592 testl(cnt2, cnt2);
8593 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8595 // Load first characters
8596 load_unsigned_short(result, Address(str1, 0));
8597 load_unsigned_short(cnt1, Address(str2, 0));
8599 // Compare first characters
8600 subl(result, cnt1);
8601 jcc(Assembler::notZero, POP_LABEL);
8602 decrementl(cnt2);
8603 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8605 {
8606 // Check after comparing first character to see if strings are equivalent
8607 Label LSkip2;
8608 // Check if the strings start at same location
8609 cmpptr(str1, str2);
8610 jccb(Assembler::notEqual, LSkip2);
8612 // Check if the length difference is zero (from stack)
8613 cmpl(Address(rsp, 0), 0x0);
8614 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
8616 // Strings might not be equivalent
8617 bind(LSkip2);
8618 }
8620 // Advance to next character
8621 addptr(str1, 2);
8622 addptr(str2, 2);
8624 if (UseSSE42Intrinsics) {
8625 // With SSE4.2, use double quad vector compare
8626 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8627 // Setup to compare 16-byte vectors
8628 movl(cnt1, cnt2);
8629 andl(cnt2, 0xfffffff8); // cnt2 holds the vector count
8630 andl(cnt1, 0x00000007); // cnt1 holds the tail count
8631 testl(cnt2, cnt2);
8632 jccb(Assembler::zero, COMPARE_TAIL);
8634 lea(str2, Address(str2, cnt2, Address::times_2));
8635 lea(str1, Address(str1, cnt2, Address::times_2));
8636 negptr(cnt2);
8638 bind(COMPARE_VECTORS);
8639 movdqu(vec1, Address(str1, cnt2, Address::times_2));
8640 movdqu(vec2, Address(str2, cnt2, Address::times_2));
8641 pxor(vec1, vec2);
8642 ptest(vec1, vec1);
8643 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
8644 addptr(cnt2, 8);
8645 jcc(Assembler::notZero, COMPARE_VECTORS);
8646 jmpb(COMPARE_TAIL);
8648 // Mismatched characters in the vectors
8649 bind(VECTOR_NOT_EQUAL);
8650 lea(str1, Address(str1, cnt2, Address::times_2));
8651 lea(str2, Address(str2, cnt2, Address::times_2));
8652 movl(cnt1, 8);
8654 // Compare tail (< 8 chars), or rescan last vectors to
8655 // find 1st mismatched characters
8656 bind(COMPARE_TAIL);
8657 testl(cnt1, cnt1);
8658 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8659 movl(cnt2, cnt1);
8660 // Fallthru to tail compare
8661 }
8663 // Shift str2 and str1 to the end of the arrays, negate min
8664 lea(str1, Address(str1, cnt2, Address::times_2, 0));
8665 lea(str2, Address(str2, cnt2, Address::times_2, 0));
8666 negptr(cnt2);
8668 // Compare the rest of the characters
8669 bind(WHILE_HEAD_LABEL);
8670 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, 0));
8671 load_unsigned_short(cnt1, Address(str2, cnt2, Address::times_2, 0));
8672 subl(result, cnt1);
8673 jccb(Assembler::notZero, POP_LABEL);
8674 increment(cnt2);
8675 jcc(Assembler::notZero, WHILE_HEAD_LABEL);
8677 // Strings are equal up to min length. Return the length difference.
8678 bind(LENGTH_DIFF_LABEL);
8679 pop(result);
8680 jmpb(DONE_LABEL);
8682 // Discard the stored length difference
8683 bind(POP_LABEL);
8684 addptr(rsp, wordSize);
8686 // That's it
8687 bind(DONE_LABEL);
8688 }
8690 // Compare char[] arrays aligned to 4 bytes or substrings.
8691 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8692 Register limit, Register result, Register chr,
8693 XMMRegister vec1, XMMRegister vec2) {
8694 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
8696 int length_offset = arrayOopDesc::length_offset_in_bytes();
8697 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
8699 // Check the input args
8700 cmpptr(ary1, ary2);
8701 jcc(Assembler::equal, TRUE_LABEL);
8703 if (is_array_equ) {
8704 // Need additional checks for arrays_equals.
8705 testptr(ary1, ary1);
8706 jcc(Assembler::zero, FALSE_LABEL);
8707 testptr(ary2, ary2);
8708 jcc(Assembler::zero, FALSE_LABEL);
8710 // Check the lengths
8711 movl(limit, Address(ary1, length_offset));
8712 cmpl(limit, Address(ary2, length_offset));
8713 jcc(Assembler::notEqual, FALSE_LABEL);
8714 }
8716 // count == 0
8717 testl(limit, limit);
8718 jcc(Assembler::zero, TRUE_LABEL);
8720 if (is_array_equ) {
8721 // Load array address
8722 lea(ary1, Address(ary1, base_offset));
8723 lea(ary2, Address(ary2, base_offset));
8724 }
8726 shll(limit, 1); // byte count != 0
8727 movl(result, limit); // copy
8729 if (UseSSE42Intrinsics) {
8730 // With SSE4.2, use double quad vector compare
8731 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8732 // Compare 16-byte vectors
8733 andl(result, 0x0000000e); // tail count (in bytes)
8734 andl(limit, 0xfffffff0); // vector count (in bytes)
8735 jccb(Assembler::zero, COMPARE_TAIL);
8737 lea(ary1, Address(ary1, limit, Address::times_1));
8738 lea(ary2, Address(ary2, limit, Address::times_1));
8739 negptr(limit);
8741 bind(COMPARE_WIDE_VECTORS);
8742 movdqu(vec1, Address(ary1, limit, Address::times_1));
8743 movdqu(vec2, Address(ary2, limit, Address::times_1));
8744 pxor(vec1, vec2);
8745 ptest(vec1, vec1);
8746 jccb(Assembler::notZero, FALSE_LABEL);
8747 addptr(limit, 16);
8748 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8750 bind(COMPARE_TAIL); // limit is zero
8751 movl(limit, result);
8752 // Fallthru to tail compare
8753 }
8755 // Compare 4-byte vectors
8756 andl(limit, 0xfffffffc); // vector count (in bytes)
8757 jccb(Assembler::zero, COMPARE_CHAR);
8759 lea(ary1, Address(ary1, limit, Address::times_1));
8760 lea(ary2, Address(ary2, limit, Address::times_1));
8761 negptr(limit);
8763 bind(COMPARE_VECTORS);
8764 movl(chr, Address(ary1, limit, Address::times_1));
8765 cmpl(chr, Address(ary2, limit, Address::times_1));
8766 jccb(Assembler::notEqual, FALSE_LABEL);
8767 addptr(limit, 4);
8768 jcc(Assembler::notZero, COMPARE_VECTORS);
8770 // Compare trailing char (final 2 bytes), if any
8771 bind(COMPARE_CHAR);
8772 testl(result, 0x2); // tail char
8773 jccb(Assembler::zero, TRUE_LABEL);
8774 load_unsigned_short(chr, Address(ary1, 0));
8775 load_unsigned_short(limit, Address(ary2, 0));
8776 cmpl(chr, limit);
8777 jccb(Assembler::notEqual, FALSE_LABEL);
8779 bind(TRUE_LABEL);
8780 movl(result, 1); // return true
8781 jmpb(DONE);
8783 bind(FALSE_LABEL);
8784 xorl(result, result); // return false
8786 // That's it
8787 bind(DONE);
8788 }
8790 #ifdef PRODUCT
8791 #define BLOCK_COMMENT(str) /* nothing */
8792 #else
8793 #define BLOCK_COMMENT(str) block_comment(str)
8794 #endif
8796 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
8797 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8798 Register to, Register value, Register count,
8799 Register rtmp, XMMRegister xtmp) {
8800 assert_different_registers(to, value, count, rtmp);
8801 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8802 Label L_fill_2_bytes, L_fill_4_bytes;
8804 int shift = -1;
8805 switch (t) {
8806 case T_BYTE:
8807 shift = 2;
8808 break;
8809 case T_SHORT:
8810 shift = 1;
8811 break;
8812 case T_INT:
8813 shift = 0;
8814 break;
8815 default: ShouldNotReachHere();
8816 }
8818 if (t == T_BYTE) {
8819 andl(value, 0xff);
8820 movl(rtmp, value);
8821 shll(rtmp, 8);
8822 orl(value, rtmp);
8823 }
8824 if (t == T_SHORT) {
8825 andl(value, 0xffff);
8826 }
8827 if (t == T_BYTE || t == T_SHORT) {
8828 movl(rtmp, value);
8829 shll(rtmp, 16);
8830 orl(value, rtmp);
8831 }
8833 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8834 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8835 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8836 // align source address at 4 bytes address boundary
8837 if (t == T_BYTE) {
8838 // One byte misalignment happens only for byte arrays
8839 testptr(to, 1);
8840 jccb(Assembler::zero, L_skip_align1);
8841 movb(Address(to, 0), value);
8842 increment(to);
8843 decrement(count);
8844 BIND(L_skip_align1);
8845 }
8846 // Two bytes misalignment happens only for byte and short (char) arrays
8847 testptr(to, 2);
8848 jccb(Assembler::zero, L_skip_align2);
8849 movw(Address(to, 0), value);
8850 addptr(to, 2);
8851 subl(count, 1<<(shift-1));
8852 BIND(L_skip_align2);
8853 }
8854 if (UseSSE < 2) {
8855 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8856 // Fill 32-byte chunks
8857 subl(count, 8 << shift);
8858 jcc(Assembler::less, L_check_fill_8_bytes);
8859 align(16);
8861 BIND(L_fill_32_bytes_loop);
8863 for (int i = 0; i < 32; i += 4) {
8864 movl(Address(to, i), value);
8865 }
8867 addptr(to, 32);
8868 subl(count, 8 << shift);
8869 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8870 BIND(L_check_fill_8_bytes);
8871 addl(count, 8 << shift);
8872 jccb(Assembler::zero, L_exit);
8873 jmpb(L_fill_8_bytes);
8875 //
8876 // length is too short, just fill qwords
8877 //
8878 BIND(L_fill_8_bytes_loop);
8879 movl(Address(to, 0), value);
8880 movl(Address(to, 4), value);
8881 addptr(to, 8);
8882 BIND(L_fill_8_bytes);
8883 subl(count, 1 << (shift + 1));
8884 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8885 // fall through to fill 4 bytes
8886 } else {
8887 Label L_fill_32_bytes;
8888 if (!UseUnalignedLoadStores) {
8889 // align to 8 bytes, we know we are 4 byte aligned to start
8890 testptr(to, 4);
8891 jccb(Assembler::zero, L_fill_32_bytes);
8892 movl(Address(to, 0), value);
8893 addptr(to, 4);
8894 subl(count, 1<<shift);
8895 }
8896 BIND(L_fill_32_bytes);
8897 {
8898 assert( UseSSE >= 2, "supported cpu only" );
8899 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8900 // Fill 32-byte chunks
8901 movdl(xtmp, value);
8902 pshufd(xtmp, xtmp, 0);
8904 subl(count, 8 << shift);
8905 jcc(Assembler::less, L_check_fill_8_bytes);
8906 align(16);
8908 BIND(L_fill_32_bytes_loop);
8910 if (UseUnalignedLoadStores) {
8911 movdqu(Address(to, 0), xtmp);
8912 movdqu(Address(to, 16), xtmp);
8913 } else {
8914 movq(Address(to, 0), xtmp);
8915 movq(Address(to, 8), xtmp);
8916 movq(Address(to, 16), xtmp);
8917 movq(Address(to, 24), xtmp);
8918 }
8920 addptr(to, 32);
8921 subl(count, 8 << shift);
8922 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8923 BIND(L_check_fill_8_bytes);
8924 addl(count, 8 << shift);
8925 jccb(Assembler::zero, L_exit);
8926 jmpb(L_fill_8_bytes);
8928 //
8929 // length is too short, just fill qwords
8930 //
8931 BIND(L_fill_8_bytes_loop);
8932 movq(Address(to, 0), xtmp);
8933 addptr(to, 8);
8934 BIND(L_fill_8_bytes);
8935 subl(count, 1 << (shift + 1));
8936 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8937 }
8938 }
8939 // fill trailing 4 bytes
8940 BIND(L_fill_4_bytes);
8941 testl(count, 1<<shift);
8942 jccb(Assembler::zero, L_fill_2_bytes);
8943 movl(Address(to, 0), value);
8944 if (t == T_BYTE || t == T_SHORT) {
8945 addptr(to, 4);
8946 BIND(L_fill_2_bytes);
8947 // fill trailing 2 bytes
8948 testl(count, 1<<(shift-1));
8949 jccb(Assembler::zero, L_fill_byte);
8950 movw(Address(to, 0), value);
8951 if (t == T_BYTE) {
8952 addptr(to, 2);
8953 BIND(L_fill_byte);
8954 // fill trailing byte
8955 testl(count, 1);
8956 jccb(Assembler::zero, L_exit);
8957 movb(Address(to, 0), value);
8958 } else {
8959 BIND(L_fill_byte);
8960 }
8961 } else {
8962 BIND(L_fill_2_bytes);
8963 }
8964 BIND(L_exit);
8965 }
8966 #undef BIND
8967 #undef BLOCK_COMMENT
8970 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8971 switch (cond) {
8972 // Note some conditions are synonyms for others
8973 case Assembler::zero: return Assembler::notZero;
8974 case Assembler::notZero: return Assembler::zero;
8975 case Assembler::less: return Assembler::greaterEqual;
8976 case Assembler::lessEqual: return Assembler::greater;
8977 case Assembler::greater: return Assembler::lessEqual;
8978 case Assembler::greaterEqual: return Assembler::less;
8979 case Assembler::below: return Assembler::aboveEqual;
8980 case Assembler::belowEqual: return Assembler::above;
8981 case Assembler::above: return Assembler::belowEqual;
8982 case Assembler::aboveEqual: return Assembler::below;
8983 case Assembler::overflow: return Assembler::noOverflow;
8984 case Assembler::noOverflow: return Assembler::overflow;
8985 case Assembler::negative: return Assembler::positive;
8986 case Assembler::positive: return Assembler::negative;
8987 case Assembler::parity: return Assembler::noParity;
8988 case Assembler::noParity: return Assembler::parity;
8989 }
8990 ShouldNotReachHere(); return Assembler::overflow;
8991 }
8993 SkipIfEqual::SkipIfEqual(
8994 MacroAssembler* masm, const bool* flag_addr, bool value) {
8995 _masm = masm;
8996 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8997 _masm->jcc(Assembler::equal, _label);
8998 }
9000 SkipIfEqual::~SkipIfEqual() {
9001 _masm->bind(_label);
9002 }
