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src/cpu/mips/vm/mips_64.ad@a7aab745eaa6
src/cpu/mips/vm/mips_64.ad
Thu, 03 Aug 2017 16:06:12 +0800
- author
- fujie
- date
- Thu, 03 Aug 2017 16:06:12 +0800
- changeset 426
- a7aab745eaa6
- parent 422
- 8b711b193083
- child 427
- 540fea2596f7
- permissions
- -rw-r--r--
[C2] Add branchConL_regL_immL & jmpLoopEnd_reg_immI for mips.
1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 // GodSon3 Architecture Description File
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // archtecture.
33 // format:
34 // reg_def name (call convention, c-call convention, ideal type, encoding);
35 // call convention :
36 // NS = No-Save
37 // SOC = Save-On-Call
38 // SOE = Save-On-Entry
39 // AS = Always-Save
40 // ideal type :
41 // see opto/opcodes.hpp for more info
42 // reg_class name (reg, ...);
43 // alloc_class name (reg, ...);
44 register %{
46 // General Registers
47 // Integer Registers
48 reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
49 reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
50 reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
51 reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
52 reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
53 reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
54 reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
55 reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
56 reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
57 reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
58 reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
59 reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
60 reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
61 reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
62 reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
63 reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
64 reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
65 reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
66 reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
67 reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
68 reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
69 reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
70 reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
71 reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
72 reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
73 reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
74 reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
75 reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
76 reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
77 reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
78 reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
79 reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
80 reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
81 reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
82 reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
83 reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
84 reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
85 reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
86 reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
87 reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
88 reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
89 reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
90 reg_def S5_H (SOC, SOE, Op_RegI, 21, S5->as_VMReg()->next());
91 reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
92 reg_def S6_H (SOC, SOE, Op_RegI, 22, S6->as_VMReg()->next());
93 reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
94 reg_def S7_H (SOC, SOE, Op_RegI, 23, S7->as_VMReg()->next());
95 reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
96 reg_def T8_H (SOC, SOC, Op_RegI, 24, T8->as_VMReg()->next());
97 reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
98 reg_def T9_H (SOC, SOC, Op_RegI, 25, T9->as_VMReg()->next());
100 // Special Registers
101 reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
102 reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
103 reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
104 reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
105 reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
106 reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
107 reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
108 reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
109 reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
110 reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
112 // Floating registers.
113 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
114 reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next());
115 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
116 reg_def F1_H ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()->next());
117 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
118 reg_def F2_H ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()->next());
119 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
120 reg_def F3_H ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()->next());
121 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
122 reg_def F4_H ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()->next());
123 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
124 reg_def F5_H ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()->next());
125 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
126 reg_def F6_H ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()->next());
127 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
128 reg_def F7_H ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()->next());
129 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
130 reg_def F8_H ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()->next());
131 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
132 reg_def F9_H ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()->next());
133 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
134 reg_def F10_H ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()->next());
135 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
136 reg_def F11_H ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()->next());
137 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
138 reg_def F12_H ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()->next());
139 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
140 reg_def F13_H ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()->next());
141 reg_def F14 ( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
142 reg_def F14_H ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()->next());
143 reg_def F15 ( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
144 reg_def F15_H ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()->next());
145 reg_def F16 ( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
146 reg_def F16_H ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()->next());
147 reg_def F17 ( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
148 reg_def F17_H ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()->next());
149 reg_def F18 ( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
150 reg_def F18_H ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()->next());
151 reg_def F19 ( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
152 reg_def F19_H ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()->next());
153 reg_def F20 ( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
154 reg_def F20_H ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()->next());
155 reg_def F21 ( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
156 reg_def F21_H ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()->next());
157 reg_def F22 ( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
158 reg_def F22_H ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()->next());
159 reg_def F23 ( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
160 reg_def F23_H ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()->next());
161 reg_def F24 ( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
162 reg_def F24_H ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()->next());
163 reg_def F25 ( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
164 reg_def F25_H ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()->next());
165 reg_def F26 ( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
166 reg_def F26_H ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()->next());
167 reg_def F27 ( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
168 reg_def F27_H ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()->next());
169 reg_def F28 ( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
170 reg_def F28_H ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()->next());
171 reg_def F29 ( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
172 reg_def F29_H ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()->next());
173 reg_def F30 ( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
174 reg_def F30_H ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()->next());
175 reg_def F31 ( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
176 reg_def F31_H ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()->next());
179 // ----------------------------
180 // Special Registers
181 // Condition Codes Flag Registers
182 reg_def MIPS_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg());
183 //S6 is used for get_thread(S6)
184 //S5 is uesd for heapbase of compressed oop
185 alloc_class chunk0(
186 S7, S7_H,
187 S0, S0_H,
188 S1, S1_H,
189 S2, S2_H,
190 S4, S4_H,
191 S5, S5_H,
192 S6, S6_H,
193 S3, S3_H,
194 T2, T2_H,
195 T3, T3_H,
196 T8, T8_H,
197 T9, T9_H,
198 T1, T1_H, // inline_cache_reg
199 V1, V1_H,
200 A7, A7_H,
201 A6, A6_H,
202 A5, A5_H,
203 A4, A4_H,
204 V0, V0_H,
205 A3, A3_H,
206 A2, A2_H,
207 A1, A1_H,
208 A0, A0_H,
209 T0, T0_H,
210 GP, GP_H
211 RA, RA_H,
212 SP, SP_H, // stack_pointer
213 FP, FP_H // frame_pointer
214 );
216 alloc_class chunk1( F0, F0_H,
217 F1, F1_H,
218 F2, F2_H,
219 F3, F3_H,
220 F4, F4_H,
221 F5, F5_H,
222 F6, F6_H,
223 F7, F7_H,
224 F8, F8_H,
225 F9, F9_H,
226 F10, F10_H,
227 F11, F11_H,
228 F20, F20_H,
229 F21, F21_H,
230 F22, F22_H,
231 F23, F23_H,
232 F24, F24_H,
233 F25, F25_H,
234 F26, F26_H,
235 F27, F27_H,
236 F28, F28_H,
237 F19, F19_H,
238 F18, F18_H,
239 F17, F17_H,
240 F16, F16_H,
241 F15, F15_H,
242 F14, F14_H,
243 F13, F13_H,
244 F12, F12_H,
245 F29, F29_H,
246 F30, F30_H,
247 F31, F31_H);
249 alloc_class chunk2(MIPS_FLAG);
251 reg_class s_reg( S0, S1, S2, S3, S4, S5, S6, S7 );
252 reg_class s0_reg( S0 );
253 reg_class s1_reg( S1 );
254 reg_class s2_reg( S2 );
255 reg_class s3_reg( S3 );
256 reg_class s4_reg( S4 );
257 reg_class s5_reg( S5 );
258 reg_class s6_reg( S6 );
259 reg_class s7_reg( S7 );
261 reg_class t_reg( T0, T1, T2, T3, T8, T9 );
262 reg_class t0_reg( T0 );
263 reg_class t1_reg( T1 );
264 reg_class t2_reg( T2 );
265 reg_class t3_reg( T3 );
266 reg_class t8_reg( T8 );
267 reg_class t9_reg( T9 );
269 reg_class a_reg( A0, A1, A2, A3, A4, A5, A6, A7 );
270 reg_class a0_reg( A0 );
271 reg_class a1_reg( A1 );
272 reg_class a2_reg( A2 );
273 reg_class a3_reg( A3 );
274 reg_class a4_reg( A4 );
275 reg_class a5_reg( A5 );
276 reg_class a6_reg( A6 );
277 reg_class a7_reg( A7 );
279 reg_class v0_reg( V0 );
280 reg_class v1_reg( V1 );
282 reg_class sp_reg( SP, SP_H );
283 reg_class fp_reg( FP, FP_H );
285 reg_class mips_flags(MIPS_FLAG);
287 reg_class v0_long_reg( V0, V0_H );
288 reg_class v1_long_reg( V1, V1_H );
289 reg_class a0_long_reg( A0, A0_H );
290 reg_class a1_long_reg( A1, A1_H );
291 reg_class a2_long_reg( A2, A2_H );
292 reg_class a3_long_reg( A3, A3_H );
293 reg_class a4_long_reg( A4, A4_H );
294 reg_class a5_long_reg( A5, A5_H );
295 reg_class a6_long_reg( A6, A6_H );
296 reg_class a7_long_reg( A7, A7_H );
297 reg_class t0_long_reg( T0, T0_H );
298 reg_class t1_long_reg( T1, T1_H );
299 reg_class t2_long_reg( T2, T2_H );
300 reg_class t3_long_reg( T3, T3_H );
301 reg_class t8_long_reg( T8, T8_H );
302 reg_class t9_long_reg( T9, T9_H );
303 reg_class s0_long_reg( S0, S0_H );
304 reg_class s1_long_reg( S1, S1_H );
305 reg_class s2_long_reg( S2, S2_H );
306 reg_class s3_long_reg( S3, S3_H );
307 reg_class s4_long_reg( S4, S4_H );
308 reg_class s5_long_reg( S5, S5_H );
309 reg_class s6_long_reg( S6, S6_H );
310 reg_class s7_long_reg( S7, S7_H );
312 reg_class int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, A7, A6, A5, A4, V0, A3, A2, A1, A0, T0 );
314 reg_class no_Ax_int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, V0, T0 );
316 reg_class p_reg(
317 S7, S7_H,
318 S0, S0_H,
319 S1, S1_H,
320 S2, S2_H,
321 S4, S4_H,
322 S3, S3_H,
323 T8, T8_H,
324 T2, T2_H,
325 T3, T3_H,
326 T1, T1_H,
327 A7, A7_H,
328 A6, A6_H,
329 A5, A5_H,
330 A4, A4_H,
331 A3, A3_H,
332 A2, A2_H,
333 A1, A1_H,
334 A0, A0_H,
335 T0, T0_H
336 );
338 reg_class no_T8_p_reg(
339 S7, S7_H,
340 S0, S0_H,
341 S1, S1_H,
342 S2, S2_H,
343 S4, S4_H,
344 S3, S3_H,
345 T2, T2_H,
346 T3, T3_H,
347 T1, T1_H,
348 A7, A7_H,
349 A6, A6_H,
350 A5, A5_H,
351 A4, A4_H,
352 A3, A3_H,
353 A2, A2_H,
354 A1, A1_H,
355 A0, A0_H,
356 T0, T0_H
357 );
359 reg_class long_reg(
360 S7, S7_H,
361 S0, S0_H,
362 S1, S1_H,
363 S2, S2_H,
364 S4, S4_H,
365 S3, S3_H,
366 T8, T8_H,
367 T2, T2_H,
368 T3, T3_H,
369 T1, T1_H,
370 A7, A7_H,
371 A6, A6_H,
372 A5, A5_H,
373 A4, A4_H,
374 A3, A3_H,
375 A2, A2_H,
376 A1, A1_H,
377 A0, A0_H,
378 T0, T0_H
379 );
382 // Floating point registers.
383 // 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
384 // 2016/12/1 aoqi: F31 are not used as temporary registers in D2I
385 reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F31);
386 reg_class dbl_reg( F0, F0_H,
387 F1, F1_H,
388 F2, F2_H,
389 F3, F3_H,
390 F4, F4_H,
391 F5, F5_H,
392 F6, F6_H,
393 F7, F7_H,
394 F8, F8_H,
395 F9, F9_H,
396 F10, F10_H,
397 F11, F11_H,
398 F12, F12_H,
399 F13, F13_H,
400 F14, F14_H,
401 F15, F15_H,
402 F16, F16_H,
403 F17, F17_H,
404 F18, F18_H,
405 F19, F19_H,
406 F20, F20_H,
407 F21, F21_H,
408 F22, F22_H,
409 F23, F23_H,
410 F24, F24_H,
411 F25, F25_H,
412 F26, F26_H,
413 F27, F27_H,
414 F28, F28_H,
415 F29, F29_H,
416 F31, F31_H);
418 reg_class flt_arg0( F12 );
419 reg_class dbl_arg0( F12, F12_H );
420 reg_class dbl_arg1( F14, F14_H );
422 %}
424 //----------DEFINITION BLOCK---------------------------------------------------
425 // Define name --> value mappings to inform the ADLC of an integer valued name
426 // Current support includes integer values in the range [0, 0x7FFFFFFF]
427 // Format:
428 // int_def <name> ( <int_value>, <expression>);
429 // Generated Code in ad_<arch>.hpp
430 // #define <name> (<expression>)
431 // // value == <int_value>
432 // Generated code in ad_<arch>.cpp adlc_verification()
433 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
434 //
435 definitions %{
436 int_def DEFAULT_COST ( 100, 100);
437 int_def HUGE_COST (1000000, 1000000);
439 // Memory refs are twice as expensive as run-of-the-mill.
440 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
442 // Branches are even more expensive.
443 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
444 // we use jr instruction to construct call, so more expensive
445 // by yjl 2/28/2006
446 int_def CALL_COST ( 500, DEFAULT_COST * 5);
447 /*
448 int_def EQUAL ( 1, 1 );
449 int_def NOT_EQUAL ( 2, 2 );
450 int_def GREATER ( 3, 3 );
451 int_def GREATER_EQUAL ( 4, 4 );
452 int_def LESS ( 5, 5 );
453 int_def LESS_EQUAL ( 6, 6 );
454 */
455 %}
459 //----------SOURCE BLOCK-------------------------------------------------------
460 // This is a block of C++ code which provides values, functions, and
461 // definitions necessary in the rest of the architecture description
463 source_hpp %{
464 // Header information of the source block.
465 // Method declarations/definitions which are used outside
466 // the ad-scope can conveniently be defined here.
467 //
468 // To keep related declarations/definitions/uses close together,
469 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
471 class CallStubImpl {
473 //--------------------------------------------------------------
474 //---< Used for optimization in Compile::shorten_branches >---
475 //--------------------------------------------------------------
477 public:
478 // Size of call trampoline stub.
479 static uint size_call_trampoline() {
480 return 0; // no call trampolines on this platform
481 }
483 // number of relocations needed by a call trampoline stub
484 static uint reloc_call_trampoline() {
485 return 0; // no call trampolines on this platform
486 }
487 };
489 class HandlerImpl {
491 public:
493 static int emit_exception_handler(CodeBuffer &cbuf);
494 static int emit_deopt_handler(CodeBuffer& cbuf);
496 static uint size_exception_handler() {
497 // NativeCall instruction size is the same as NativeJump.
498 // exception handler starts out as jump and can be patched to
499 // a call be deoptimization. (4932387)
500 // Note that this value is also credited (in output.cpp) to
501 // the size of the code section.
502 // return NativeJump::instruction_size;
503 int size = NativeCall::instruction_size;
504 return round_to(size, 16);
505 }
507 #ifdef _LP64
508 static uint size_deopt_handler() {
509 int size = NativeCall::instruction_size;
510 return round_to(size, 16);
511 }
512 #else
513 static uint size_deopt_handler() {
514 // NativeCall instruction size is the same as NativeJump.
515 // exception handler starts out as jump and can be patched to
516 // a call be deoptimization. (4932387)
517 // Note that this value is also credited (in output.cpp) to
518 // the size of the code section.
519 return 5 + NativeJump::instruction_size; // pushl(); jmp;
520 }
521 #endif
522 };
524 %} // end source_hpp
526 source %{
528 #define NO_INDEX 0
529 #define RELOC_IMM64 Assembler::imm_operand
530 #define RELOC_DISP32 Assembler::disp32_operand
533 #define __ _masm.
536 // Emit exception handler code.
537 // Stuff framesize into a register and call a VM stub routine.
538 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
539 // Note that the code buffer's insts_mark is always relative to insts.
540 // That's why we must use the macroassembler to generate a handler.
541 MacroAssembler _masm(&cbuf);
542 address base =
543 __ start_a_stub(size_exception_handler());
544 if (base == NULL) return 0; // CodeBuffer::expand failed
545 int offset = __ offset();
547 __ block_comment("; emit_exception_handler");
549 cbuf.set_insts_mark();
550 __ relocate(relocInfo::runtime_call_type);
551 __ patchable_jump((address)OptoRuntime::exception_blob()->entry_point());
552 __ align(16);
553 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
554 __ end_a_stub();
555 return offset;
556 }
558 // Emit deopt handler code.
559 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
560 // Note that the code buffer's insts_mark is always relative to insts.
561 // That's why we must use the macroassembler to generate a handler.
562 MacroAssembler _masm(&cbuf);
563 address base =
564 __ start_a_stub(size_deopt_handler());
566 // FIXME
567 if (base == NULL) return 0; // CodeBuffer::expand failed
568 int offset = __ offset();
570 __ block_comment("; emit_deopt_handler");
572 cbuf.set_insts_mark();
573 __ relocate(relocInfo::runtime_call_type);
574 __ patchable_call(SharedRuntime::deopt_blob()->unpack());
575 __ align(16);
576 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
577 __ end_a_stub();
578 return offset;
579 }
582 const bool Matcher::match_rule_supported(int opcode) {
583 if (!has_match_rule(opcode))
584 return false;
586 switch (opcode) {
587 //Op_CountLeadingZerosI Op_CountLeadingZerosL can be deleted, all MIPS CPUs support clz & dclz.
588 case Op_CountLeadingZerosI:
589 case Op_CountLeadingZerosL:
590 if (!UseCountLeadingZerosInstruction)
591 return false;
592 break;
593 case Op_CountTrailingZerosI:
594 case Op_CountTrailingZerosL:
595 if (!UseCountTrailingZerosInstruction)
596 return false;
597 break;
598 }
600 return true; // Per default match rules are supported.
601 }
603 //FIXME
604 // emit call stub, compiled java to interpreter
605 void emit_java_to_interp(CodeBuffer &cbuf ) {
606 // Stub is fixed up when the corresponding call is converted from calling
607 // compiled code to calling interpreted code.
608 // mov rbx,0
609 // jmp -1
611 address mark = cbuf.insts_mark(); // get mark within main instrs section
613 // Note that the code buffer's insts_mark is always relative to insts.
614 // That's why we must use the macroassembler to generate a stub.
615 MacroAssembler _masm(&cbuf);
617 address base =
618 __ start_a_stub(Compile::MAX_stubs_size);
619 if (base == NULL) return; // CodeBuffer::expand failed
620 // static stub relocation stores the instruction address of the call
622 __ relocate(static_stub_Relocation::spec(mark), 0);
624 // static stub relocation also tags the methodOop in the code-stream.
625 __ patchable_set48(S3, (long)0);
626 // This is recognized as unresolved by relocs/nativeInst/ic code
628 __ relocate(relocInfo::runtime_call_type);
630 cbuf.set_insts_mark();
631 address call_pc = (address)-1;
632 __ patchable_jump(call_pc);
633 __ align(16);
634 __ end_a_stub();
635 // Update current stubs pointer and restore code_end.
636 }
638 // size of call stub, compiled java to interpretor
639 uint size_java_to_interp() {
640 int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size
641 return round_to(size, 16);
642 }
644 // relocation entries for call stub, compiled java to interpreter
645 uint reloc_java_to_interp() {
646 return 16; // in emit_java_to_interp + in Java_Static_Call
647 }
649 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
650 if( Assembler::is_simm16(offset) ) return true;
651 else {
652 assert(false, "Not implemented yet !" );
653 Unimplemented();
654 }
655 }
658 // No additional cost for CMOVL.
659 const int Matcher::long_cmove_cost() { return 0; }
661 // No CMOVF/CMOVD with SSE2
662 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
664 // Does the CPU require late expand (see block.cpp for description of late expand)?
665 const bool Matcher::require_postalloc_expand = false;
667 // Should the Matcher clone shifts on addressing modes, expecting them
668 // to be subsumed into complex addressing expressions or compute them
669 // into registers? True for Intel but false for most RISCs
670 const bool Matcher::clone_shift_expressions = false;
672 // Do we need to mask the count passed to shift instructions or does
673 // the cpu only look at the lower 5/6 bits anyway?
674 const bool Matcher::need_masked_shift_count = false;
676 bool Matcher::narrow_oop_use_complex_address() {
677 NOT_LP64(ShouldNotCallThis());
678 assert(UseCompressedOops, "only for compressed oops code");
679 return false;
680 }
682 bool Matcher::narrow_klass_use_complex_address() {
683 NOT_LP64(ShouldNotCallThis());
684 assert(UseCompressedClassPointers, "only for compressed klass code");
685 return false;
686 }
688 // This is UltraSparc specific, true just means we have fast l2f conversion
689 const bool Matcher::convL2FSupported(void) {
690 return true;
691 }
693 // Max vector size in bytes. 0 if not supported.
694 const int Matcher::vector_width_in_bytes(BasicType bt) {
695 if (MaxVectorSize == 0)
696 return 0;
697 assert(MaxVectorSize == 8, "");
698 return 8;
699 }
701 // Vector ideal reg
702 const int Matcher::vector_ideal_reg(int size) {
703 assert(MaxVectorSize == 8, "");
704 switch(size) {
705 case 8: return Op_VecD;
706 }
707 ShouldNotReachHere();
708 return 0;
709 }
711 // Only lowest bits of xmm reg are used for vector shift count.
712 const int Matcher::vector_shift_count_ideal_reg(int size) {
713 fatal("vector shift is not supported");
714 return Node::NotAMachineReg;
715 }
717 // Limits on vector size (number of elements) loaded into vector.
718 const int Matcher::max_vector_size(const BasicType bt) {
719 assert(is_java_primitive(bt), "only primitive type vectors");
720 return vector_width_in_bytes(bt)/type2aelembytes(bt);
721 }
723 const int Matcher::min_vector_size(const BasicType bt) {
724 return max_vector_size(bt); // Same as max.
725 }
727 // MIPS supports misaligned vectors store/load? FIXME
728 const bool Matcher::misaligned_vectors_ok() {
729 return false;
730 //return !AlignVector; // can be changed by flag
731 }
733 // Register for DIVI projection of divmodI
734 RegMask Matcher::divI_proj_mask() {
735 ShouldNotReachHere();
736 return RegMask();
737 }
739 // Register for MODI projection of divmodI
740 RegMask Matcher::modI_proj_mask() {
741 ShouldNotReachHere();
742 return RegMask();
743 }
745 // Register for DIVL projection of divmodL
746 RegMask Matcher::divL_proj_mask() {
747 ShouldNotReachHere();
748 return RegMask();
749 }
751 int Matcher::regnum_to_fpu_offset(int regnum) {
752 return regnum - 32; // The FP registers are in the second chunk
753 }
756 const bool Matcher::isSimpleConstant64(jlong value) {
757 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
758 return true;
759 }
762 // Return whether or not this register is ever used as an argument. This
763 // function is used on startup to build the trampoline stubs in generateOptoStub.
764 // Registers not mentioned will be killed by the VM call in the trampoline, and
765 // arguments in those registers not be available to the callee.
766 bool Matcher::can_be_java_arg( int reg ) {
767 /* Refer to: [sharedRuntime_mips_64.cpp] SharedRuntime::java_calling_convention() */
768 if ( reg == T0_num || reg == T0_H_num
769 || reg == A0_num || reg == A0_H_num
770 || reg == A1_num || reg == A1_H_num
771 || reg == A2_num || reg == A2_H_num
772 || reg == A3_num || reg == A3_H_num
773 || reg == A4_num || reg == A4_H_num
774 || reg == A5_num || reg == A5_H_num
775 || reg == A6_num || reg == A6_H_num
776 || reg == A7_num || reg == A7_H_num )
777 return true;
779 if ( reg == F12_num || reg == F12_H_num
780 || reg == F13_num || reg == F13_H_num
781 || reg == F14_num || reg == F14_H_num
782 || reg == F15_num || reg == F15_H_num
783 || reg == F16_num || reg == F16_H_num
784 || reg == F17_num || reg == F17_H_num
785 || reg == F18_num || reg == F18_H_num
786 || reg == F19_num || reg == F19_H_num )
787 return true;
789 return false;
790 }
792 bool Matcher::is_spillable_arg( int reg ) {
793 return can_be_java_arg(reg);
794 }
796 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
797 return false;
798 }
800 // Register for MODL projection of divmodL
801 RegMask Matcher::modL_proj_mask() {
802 ShouldNotReachHere();
803 return RegMask();
804 }
806 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
807 return FP_REG_mask();
808 }
810 // MIPS doesn't support AES intrinsics
811 const bool Matcher::pass_original_key_for_aes() {
812 return false;
813 }
815 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
816 //lui
817 //ori
818 //dsll
819 //ori
821 //jalr
822 //nop
824 return round_to(current_offset, alignment_required()) - current_offset;
825 }
827 int CallLeafDirectNode::compute_padding(int current_offset) const {
828 //lui
829 //ori
830 //dsll
831 //ori
833 //jalr
834 //nop
836 return round_to(current_offset, alignment_required()) - current_offset;
837 }
839 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
840 //lui
841 //ori
842 //dsll
843 //ori
845 //jalr
846 //nop
848 return round_to(current_offset, alignment_required()) - current_offset;
849 }
851 // If CPU can load and store mis-aligned doubles directly then no fixup is
852 // needed. Else we split the double into 2 integer pieces and move it
853 // piece-by-piece. Only happens when passing doubles into C code as the
854 // Java calling convention forces doubles to be aligned.
855 const bool Matcher::misaligned_doubles_ok = false;
856 // Do floats take an entire double register or just half?
857 //const bool Matcher::float_in_double = true;
858 bool Matcher::float_in_double() { return false; }
859 // Threshold size for cleararray.
860 const int Matcher::init_array_short_size = 8 * BytesPerLong;
861 // Do ints take an entire long register or just half?
862 const bool Matcher::int_in_long = true;
863 // Is it better to copy float constants, or load them directly from memory?
864 // Intel can load a float constant from a direct address, requiring no
865 // extra registers. Most RISCs will have to materialize an address into a
866 // register first, so they would do better to copy the constant from stack.
867 const bool Matcher::rematerialize_float_constants = false;
868 // Advertise here if the CPU requires explicit rounding operations
869 // to implement the UseStrictFP mode.
870 const bool Matcher::strict_fp_requires_explicit_rounding = false;
871 // The ecx parameter to rep stos for the ClearArray node is in dwords.
872 const bool Matcher::init_array_count_is_in_bytes = false;
875 // Indicate if the safepoint node needs the polling page as an input.
876 // Since MIPS doesn't have absolute addressing, it needs.
877 bool SafePointNode::needs_polling_address_input() {
878 return false;
879 }
881 // !!!!! Special hack to get all type of calls to specify the byte offset
882 // from the start of the call to the point where the return address
883 // will point.
884 int MachCallStaticJavaNode::ret_addr_offset() {
885 //lui
886 //ori
887 //nop
888 //nop
889 //jalr
890 //nop
891 return 24;
892 }
894 int MachCallDynamicJavaNode::ret_addr_offset() {
895 //lui IC_Klass,
896 //ori IC_Klass,
897 //dsll IC_Klass
898 //ori IC_Klass
900 //lui T9
901 //ori T9
902 //nop
903 //nop
904 //jalr T9
905 //nop
906 return 4 * 4 + 4 * 6;
907 }
909 //=============================================================================
911 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
912 enum RC { rc_bad, rc_int, rc_float, rc_stack };
913 static enum RC rc_class( OptoReg::Name reg ) {
914 if( !OptoReg::is_valid(reg) ) return rc_bad;
915 if (OptoReg::is_stack(reg)) return rc_stack;
916 VMReg r = OptoReg::as_VMReg(reg);
917 if (r->is_Register()) return rc_int;
918 assert(r->is_FloatRegister(), "must be");
919 return rc_float;
920 }
922 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
923 // Get registers to move
924 OptoReg::Name src_second = ra_->get_reg_second(in(1));
925 OptoReg::Name src_first = ra_->get_reg_first(in(1));
926 OptoReg::Name dst_second = ra_->get_reg_second(this );
927 OptoReg::Name dst_first = ra_->get_reg_first(this );
929 enum RC src_second_rc = rc_class(src_second);
930 enum RC src_first_rc = rc_class(src_first);
931 enum RC dst_second_rc = rc_class(dst_second);
932 enum RC dst_first_rc = rc_class(dst_first);
934 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
936 // Generate spill code!
937 int size = 0;
939 if( src_first == dst_first && src_second == dst_second )
940 return 0; // Self copy, no move
942 if (src_first_rc == rc_stack) {
943 // mem ->
944 if (dst_first_rc == rc_stack) {
945 // mem -> mem
946 assert(src_second != dst_first, "overlap");
947 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
948 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
949 // 64-bit
950 int src_offset = ra_->reg2offset(src_first);
951 int dst_offset = ra_->reg2offset(dst_first);
952 if (cbuf) {
953 MacroAssembler _masm(cbuf);
954 __ ld(AT, Address(SP, src_offset));
955 __ sd(AT, Address(SP, dst_offset));
956 #ifndef PRODUCT
957 } else {
958 if(!do_size){
959 if (size != 0) st->print("\n\t");
960 st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
961 "sd AT, [SP + #%d]",
962 src_offset, dst_offset);
963 }
964 #endif
965 }
966 size += 8;
967 } else {
968 // 32-bit
969 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
970 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
971 // No pushl/popl, so:
972 int src_offset = ra_->reg2offset(src_first);
973 int dst_offset = ra_->reg2offset(dst_first);
974 if (cbuf) {
975 MacroAssembler _masm(cbuf);
976 __ lw(AT, Address(SP, src_offset));
977 __ sw(AT, Address(SP, dst_offset));
978 #ifndef PRODUCT
979 } else {
980 if(!do_size){
981 if (size != 0) st->print("\n\t");
982 st->print("lw AT, [SP + #%d] spill 2\n\t"
983 "sw AT, [SP + #%d]\n\t",
984 src_offset, dst_offset);
985 }
986 #endif
987 }
988 size += 8;
989 }
990 return size;
991 } else if (dst_first_rc == rc_int) {
992 // mem -> gpr
993 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
994 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
995 // 64-bit
996 int offset = ra_->reg2offset(src_first);
997 if (cbuf) {
998 MacroAssembler _masm(cbuf);
999 __ ld(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1000 #ifndef PRODUCT
1001 } else {
1002 if(!do_size){
1003 if (size != 0) st->print("\n\t");
1004 st->print("ld %s, [SP + #%d]\t# spill 3",
1005 Matcher::regName[dst_first],
1006 offset);
1007 }
1008 #endif
1009 }
1010 size += 4;
1011 } else {
1012 // 32-bit
1013 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1014 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1015 int offset = ra_->reg2offset(src_first);
1016 if (cbuf) {
1017 MacroAssembler _masm(cbuf);
1018 if (this->ideal_reg() == Op_RegI)
1019 __ lw(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1020 else
1021 __ lwu(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1022 #ifndef PRODUCT
1023 } else {
1024 if(!do_size){
1025 if (size != 0) st->print("\n\t");
1026 if (this->ideal_reg() == Op_RegI)
1027 st->print("lw %s, [SP + #%d]\t# spill 4",
1028 Matcher::regName[dst_first],
1029 offset);
1030 else
1031 st->print("lwu %s, [SP + #%d]\t# spill 5",
1032 Matcher::regName[dst_first],
1033 offset);
1034 }
1035 #endif
1036 }
1037 size += 4;
1038 }
1039 return size;
1040 } else if (dst_first_rc == rc_float) {
1041 // mem-> xmm
1042 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1043 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1044 // 64-bit
1045 int offset = ra_->reg2offset(src_first);
1046 if (cbuf) {
1047 MacroAssembler _masm(cbuf);
1048 __ ldc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1049 #ifndef PRODUCT
1050 } else {
1051 if(!do_size){
1052 if (size != 0) st->print("\n\t");
1053 st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1054 Matcher::regName[dst_first],
1055 offset);
1056 }
1057 #endif
1058 }
1059 size += 4;
1060 } else {
1061 // 32-bit
1062 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1063 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1064 int offset = ra_->reg2offset(src_first);
1065 if (cbuf) {
1066 MacroAssembler _masm(cbuf);
1067 __ lwc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1068 #ifndef PRODUCT
1069 } else {
1070 if(!do_size){
1071 if (size != 0) st->print("\n\t");
1072 st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1073 Matcher::regName[dst_first],
1074 offset);
1075 }
1076 #endif
1077 }
1078 size += 4;
1079 }
1080 return size;
1081 }
1082 } else if (src_first_rc == rc_int) {
1083 // gpr ->
1084 if (dst_first_rc == rc_stack) {
1085 // gpr -> mem
1086 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1087 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1088 // 64-bit
1089 int offset = ra_->reg2offset(dst_first);
1090 if (cbuf) {
1091 MacroAssembler _masm(cbuf);
1092 __ sd(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1093 #ifndef PRODUCT
1094 } else {
1095 if(!do_size){
1096 if (size != 0) st->print("\n\t");
1097 st->print("sd %s, [SP + #%d] # spill 8",
1098 Matcher::regName[src_first],
1099 offset);
1100 }
1101 #endif
1102 }
1103 size += 4;
1104 } else {
1105 // 32-bit
1106 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1107 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1108 int offset = ra_->reg2offset(dst_first);
1109 if (cbuf) {
1110 MacroAssembler _masm(cbuf);
1111 __ sw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1112 #ifndef PRODUCT
1113 } else {
1114 if(!do_size){
1115 if (size != 0) st->print("\n\t");
1116 st->print("sw %s, [SP + #%d]\t# spill 9",
1117 Matcher::regName[src_first], offset);
1118 }
1119 #endif
1120 }
1121 size += 4;
1122 }
1123 return size;
1124 } else if (dst_first_rc == rc_int) {
1125 // gpr -> gpr
1126 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1127 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1128 // 64-bit
1129 if (cbuf) {
1130 MacroAssembler _masm(cbuf);
1131 __ move(as_Register(Matcher::_regEncode[dst_first]),
1132 as_Register(Matcher::_regEncode[src_first]));
1133 #ifndef PRODUCT
1134 } else {
1135 if(!do_size){
1136 if (size != 0) st->print("\n\t");
1137 st->print("move(64bit) %s <-- %s\t# spill 10",
1138 Matcher::regName[dst_first],
1139 Matcher::regName[src_first]);
1140 }
1141 #endif
1142 }
1143 size += 4;
1144 return size;
1145 } else {
1146 // 32-bit
1147 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1148 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1149 if (cbuf) {
1150 MacroAssembler _masm(cbuf);
1151 if (this->ideal_reg() == Op_RegI)
1152 __ move_u32(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1153 else
1154 __ daddu(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
1156 #ifndef PRODUCT
1157 } else {
1158 if(!do_size){
1159 if (size != 0) st->print("\n\t");
1160 st->print("move(32-bit) %s <-- %s\t# spill 11",
1161 Matcher::regName[dst_first],
1162 Matcher::regName[src_first]);
1163 }
1164 #endif
1165 }
1166 size += 4;
1167 return size;
1168 }
1169 } else if (dst_first_rc == rc_float) {
1170 // gpr -> xmm
1171 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1172 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1173 // 64-bit
1174 if (cbuf) {
1175 MacroAssembler _masm(cbuf);
1176 __ dmtc1(as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]));
1177 #ifndef PRODUCT
1178 } else {
1179 if(!do_size){
1180 if (size != 0) st->print("\n\t");
1181 st->print("dmtc1 %s, %s\t# spill 12",
1182 Matcher::regName[dst_first],
1183 Matcher::regName[src_first]);
1184 }
1185 #endif
1186 }
1187 size += 4;
1188 } else {
1189 // 32-bit
1190 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1191 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1192 if (cbuf) {
1193 MacroAssembler _masm(cbuf);
1194 __ mtc1( as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]) );
1195 #ifndef PRODUCT
1196 } else {
1197 if(!do_size){
1198 if (size != 0) st->print("\n\t");
1199 st->print("mtc1 %s, %s\t# spill 13",
1200 Matcher::regName[dst_first],
1201 Matcher::regName[src_first]);
1202 }
1203 #endif
1204 }
1205 size += 4;
1206 }
1207 return size;
1208 }
1209 } else if (src_first_rc == rc_float) {
1210 // xmm ->
1211 if (dst_first_rc == rc_stack) {
1212 // xmm -> mem
1213 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1214 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1215 // 64-bit
1216 int offset = ra_->reg2offset(dst_first);
1217 if (cbuf) {
1218 MacroAssembler _masm(cbuf);
1219 __ sdc1( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
1220 #ifndef PRODUCT
1221 } else {
1222 if(!do_size){
1223 if (size != 0) st->print("\n\t");
1224 st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1225 Matcher::regName[src_first],
1226 offset);
1227 }
1228 #endif
1229 }
1230 size += 4;
1231 } else {
1232 // 32-bit
1233 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1234 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1235 int offset = ra_->reg2offset(dst_first);
1236 if (cbuf) {
1237 MacroAssembler _masm(cbuf);
1238 __ swc1(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
1239 #ifndef PRODUCT
1240 } else {
1241 if(!do_size){
1242 if (size != 0) st->print("\n\t");
1243 st->print("swc1 %s, [SP + #%d]\t# spill 15",
1244 Matcher::regName[src_first],
1245 offset);
1246 }
1247 #endif
1248 }
1249 size += 4;
1250 }
1251 return size;
1252 } else if (dst_first_rc == rc_int) {
1253 // xmm -> gpr
1254 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1255 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1256 // 64-bit
1257 if (cbuf) {
1258 MacroAssembler _masm(cbuf);
1259 __ dmfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1260 #ifndef PRODUCT
1261 } else {
1262 if(!do_size){
1263 if (size != 0) st->print("\n\t");
1264 st->print("dmfc1 %s, %s\t# spill 16",
1265 Matcher::regName[dst_first],
1266 Matcher::regName[src_first]);
1267 }
1268 #endif
1269 }
1270 size += 4;
1271 } else {
1272 // 32-bit
1273 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1274 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1275 if (cbuf) {
1276 MacroAssembler _masm(cbuf);
1277 __ mfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1278 #ifndef PRODUCT
1279 } else {
1280 if(!do_size){
1281 if (size != 0) st->print("\n\t");
1282 st->print("mfc1 %s, %s\t# spill 17",
1283 Matcher::regName[dst_first],
1284 Matcher::regName[src_first]);
1285 }
1286 #endif
1287 }
1288 size += 4;
1289 }
1290 return size;
1291 } else if (dst_first_rc == rc_float) {
1292 // xmm -> xmm
1293 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1294 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1295 // 64-bit
1296 if (cbuf) {
1297 MacroAssembler _masm(cbuf);
1298 __ mov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1299 #ifndef PRODUCT
1300 } else {
1301 if(!do_size){
1302 if (size != 0) st->print("\n\t");
1303 st->print("mov_d %s <-- %s\t# spill 18",
1304 Matcher::regName[dst_first],
1305 Matcher::regName[src_first]);
1306 }
1307 #endif
1308 }
1309 size += 4;
1310 } else {
1311 // 32-bit
1312 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1313 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1314 if (cbuf) {
1315 MacroAssembler _masm(cbuf);
1316 __ mov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1317 #ifndef PRODUCT
1318 } else {
1319 if(!do_size){
1320 if (size != 0) st->print("\n\t");
1321 st->print("mov_s %s <-- %s\t# spill 19",
1322 Matcher::regName[dst_first],
1323 Matcher::regName[src_first]);
1324 }
1325 #endif
1326 }
1327 size += 4;
1328 }
1329 return size;
1330 }
1331 }
1333 assert(0," foo ");
1334 Unimplemented();
1335 return size;
1337 }
1339 #ifndef PRODUCT
1340 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1341 implementation( NULL, ra_, false, st );
1342 }
1343 #endif
1345 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1346 implementation( &cbuf, ra_, false, NULL );
1347 }
1349 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1350 return implementation( NULL, ra_, true, NULL );
1351 }
1353 //=============================================================================
1354 #
1356 #ifndef PRODUCT
1357 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
1358 st->print("INT3");
1359 }
1360 #endif
1362 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
1363 MacroAssembler _masm(&cbuf);
1364 __ int3();
1365 }
1367 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
1368 return MachNode::size(ra_);
1369 }
1372 //=============================================================================
1373 #ifndef PRODUCT
1374 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1375 Compile *C = ra_->C;
1376 int framesize = C->frame_size_in_bytes();
1378 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1380 st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1381 st->cr(); st->print("\t");
1382 if (UseLoongsonISA) {
1383 st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1384 } else {
1385 st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1386 st->cr(); st->print("\t");
1387 st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1388 }
1390 if( do_polling() && C->is_method_compilation() ) {
1391 st->print("Poll Safepoint # MachEpilogNode");
1392 }
1393 }
1394 #endif
1396 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1397 Compile *C = ra_->C;
1398 MacroAssembler _masm(&cbuf);
1399 int framesize = C->frame_size_in_bytes();
1401 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1403 __ daddiu(SP, SP, framesize);
1405 if (UseLoongsonISA) {
1406 __ gslq(RA, FP, SP, -wordSize*2);
1407 } else {
1408 __ ld(RA, SP, -wordSize );
1409 __ ld(FP, SP, -wordSize*2 );
1410 }
1412 if( do_polling() && C->is_method_compilation() ) {
1413 __ set64(AT, (long)os::get_polling_page());
1414 __ relocate(relocInfo::poll_return_type);
1415 __ lw(AT, AT, 0);
1416 }
1417 }
1419 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1420 return MachNode::size(ra_); // too many variables; just compute it the hard way fujie debug
1421 }
1423 int MachEpilogNode::reloc() const {
1424 return 0; // a large enough number
1425 }
1427 const Pipeline * MachEpilogNode::pipeline() const {
1428 return MachNode::pipeline_class();
1429 }
1431 int MachEpilogNode::safepoint_offset() const { return 0; }
1433 //=============================================================================
1435 #ifndef PRODUCT
1436 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1437 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1438 int reg = ra_->get_reg_first(this);
1439 st->print("ADDI %s, SP, %d @BoxLockNode",Matcher::regName[reg],offset);
1440 }
1441 #endif
1444 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1445 return 4;
1446 }
1448 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1449 MacroAssembler _masm(&cbuf);
1450 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1451 int reg = ra_->get_encode(this);
1453 __ addi(as_Register(reg), SP, offset);
1454 /*
1455 if( offset >= 128 ) {
1456 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1457 emit_rm(cbuf, 0x2, reg, 0x04);
1458 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1459 emit_d32(cbuf, offset);
1460 }
1461 else {
1462 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1463 emit_rm(cbuf, 0x1, reg, 0x04);
1464 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1465 emit_d8(cbuf, offset);
1466 }
1467 */
1468 }
1471 //static int sizeof_FFree_Float_Stack_All = -1;
1473 int MachCallRuntimeNode::ret_addr_offset() {
1474 //lui
1475 //ori
1476 //dsll
1477 //ori
1478 //jalr
1479 //nop
1480 assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()");
1481 return NativeCall::instruction_size;
1482 // return 16;
1483 }
1489 //=============================================================================
1490 #ifndef PRODUCT
1491 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1492 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1493 }
1494 #endif
1496 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1497 MacroAssembler _masm(&cbuf);
1498 int i = 0;
1499 for(i = 0; i < _count; i++)
1500 __ nop();
1501 }
1503 uint MachNopNode::size(PhaseRegAlloc *) const {
1504 return 4 * _count;
1505 }
1506 const Pipeline* MachNopNode::pipeline() const {
1507 return MachNode::pipeline_class();
1508 }
1510 //=============================================================================
1512 //=============================================================================
1513 #ifndef PRODUCT
1514 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1515 st->print_cr("load_klass(T9, T0)");
1516 st->print_cr("\tbeq(T9, iCache, L)");
1517 st->print_cr("\tnop");
1518 st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)");
1519 st->print_cr("\tnop");
1520 st->print_cr("\tnop");
1521 st->print_cr(" L:");
1522 }
1523 #endif
1526 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1527 MacroAssembler _masm(&cbuf);
1528 #ifdef ASSERT
1529 //uint code_size = cbuf.code_size();
1530 #endif
1531 int ic_reg = Matcher::inline_cache_reg_encode();
1532 Label L;
1533 Register receiver = T0;
1534 Register iCache = as_Register(ic_reg);
1535 __ load_klass(T9, receiver);
1536 __ beq(T9, iCache, L);
1537 __ nop();
1539 __ relocate(relocInfo::runtime_call_type);
1540 __ patchable_jump((address)SharedRuntime::get_ic_miss_stub());
1542 /* WARNING these NOPs are critical so that verified entry point is properly
1543 * 8 bytes aligned for patching by NativeJump::patch_verified_entry() */
1544 __ align(CodeEntryAlignment);
1545 __ bind(L);
1546 }
1548 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1549 return MachNode::size(ra_);
1550 }
1554 //=============================================================================
1556 const RegMask& MachConstantBaseNode::_out_RegMask = P_REG_mask();
1558 int Compile::ConstantTable::calculate_table_base_offset() const {
1559 return 0; // absolute addressing, no offset
1560 }
1562 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1563 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1564 ShouldNotReachHere();
1565 }
1567 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1568 Compile* C = ra_->C;
1569 Compile::ConstantTable& constant_table = C->constant_table();
1570 MacroAssembler _masm(&cbuf);
1572 Register Rtoc = as_Register(ra_->get_encode(this));
1573 CodeSection* consts_section = __ code()->consts();
1574 int consts_size = consts_section->align_at_start(consts_section->size());
1575 assert(constant_table.size() == consts_size, "must be equal");
1577 if (consts_section->size()) {
1578 // Materialize the constant table base.
1579 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1580 // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1581 __ relocate(relocInfo::internal_pc_type);
1582 __ patchable_set48(Rtoc, (long)baseaddr);
1583 }
1584 }
1586 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1587 // patchable_set48 (4 insts)
1588 return 4 * 4;
1589 }
1591 #ifndef PRODUCT
1592 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1593 Register r = as_Register(ra_->get_encode(this));
1594 st->print("patchable_set48 %s, &constanttable (constant table base) @ MachConstantBaseNode", r->name());
1595 }
1596 #endif
1599 //=============================================================================
1600 #ifndef PRODUCT
1601 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1602 Compile* C = ra_->C;
1604 int framesize = C->frame_size_in_bytes();
1605 int bangsize = C->bang_size_in_bytes();
1606 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1608 // Calls to C2R adapters often do not accept exceptional returns.
1609 // We require that their callers must bang for them. But be careful, because
1610 // some VM calls (such as call site linkage) can use several kilobytes of
1611 // stack. But the stack safety zone should account for that.
1612 // See bugs 4446381, 4468289, 4497237.
1613 if (C->need_stack_bang(bangsize)) {
1614 st->print_cr("# stack bang"); st->print("\t");
1615 }
1616 if (UseLoongsonISA) {
1617 st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1618 } else {
1619 st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize);
1620 st->print("sd FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1621 }
1622 st->print("daddiu FP, SP, -%d \n\t", wordSize*2);
1623 st->print("daddiu SP, SP, -%d \t",framesize);
1624 }
1625 #endif
1628 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1629 Compile* C = ra_->C;
1630 MacroAssembler _masm(&cbuf);
1632 int framesize = C->frame_size_in_bytes();
1633 int bangsize = C->bang_size_in_bytes();
1635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1637 if (C->need_stack_bang(bangsize)) {
1638 __ generate_stack_overflow_check(bangsize);
1639 }
1641 if (UseLoongsonISA) {
1642 __ gssq(RA, FP, SP, -wordSize*2);
1643 } else {
1644 __ sd(RA, SP, -wordSize);
1645 __ sd(FP, SP, -wordSize*2);
1646 }
1647 __ daddiu(FP, SP, -wordSize*2);
1648 __ daddiu(SP, SP, -framesize);
1649 __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
1650 __ nop();
1652 C->set_frame_complete(cbuf.insts_size());
1653 if (C->has_mach_constant_base_node()) {
1654 // NOTE: We set the table base offset here because users might be
1655 // emitted before MachConstantBaseNode.
1656 Compile::ConstantTable& constant_table = C->constant_table();
1657 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1658 }
1660 }
1663 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1664 return MachNode::size(ra_); // too many variables; just compute it the hard way
1665 }
1667 int MachPrologNode::reloc() const {
1668 return 0; // a large enough number
1669 }
1671 %}
1673 //----------ENCODING BLOCK-----------------------------------------------------
1674 // This block specifies the encoding classes used by the compiler to output
1675 // byte streams. Encoding classes generate functions which are called by
1676 // Machine Instruction Nodes in order to generate the bit encoding of the
1677 // instruction. Operands specify their base encoding interface with the
1678 // interface keyword. There are currently supported four interfaces,
1679 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1680 // operand to generate a function which returns its register number when
1681 // queried. CONST_INTER causes an operand to generate a function which
1682 // returns the value of the constant when queried. MEMORY_INTER causes an
1683 // operand to generate four functions which return the Base Register, the
1684 // Index Register, the Scale Value, and the Offset Value of the operand when
1685 // queried. COND_INTER causes an operand to generate six functions which
1686 // return the encoding code (ie - encoding bits for the instruction)
1687 // associated with each basic boolean condition for a conditional instruction.
1688 // Instructions specify two basic values for encoding. They use the
1689 // ins_encode keyword to specify their encoding class (which must be one of
1690 // the class names specified in the encoding block), and they use the
1691 // opcode keyword to specify, in order, their primary, secondary, and
1692 // tertiary opcode. Only the opcode sections which a particular instruction
1693 // needs for encoding need to be specified.
1694 encode %{
1696 //Load byte signed
1697 enc_class load_B_enc (mRegI dst, memory mem) %{
1698 MacroAssembler _masm(&cbuf);
1699 int dst = $dst$$reg;
1700 int base = $mem$$base;
1701 int index = $mem$$index;
1702 int scale = $mem$$scale;
1703 int disp = $mem$$disp;
1705 if( index != 0 ) {
1706 if( Assembler::is_simm16(disp) ) {
1707 if( UseLoongsonISA ) {
1708 if (scale == 0) {
1709 __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1710 } else {
1711 __ dsll(AT, as_Register(index), scale);
1712 __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1713 }
1714 } else {
1715 if (scale == 0) {
1716 __ addu(AT, as_Register(base), as_Register(index));
1717 } else {
1718 __ dsll(AT, as_Register(index), scale);
1719 __ addu(AT, as_Register(base), AT);
1720 }
1721 __ lb(as_Register(dst), AT, disp);
1722 }
1723 } else {
1724 if (scale == 0) {
1725 __ addu(AT, as_Register(base), as_Register(index));
1726 } else {
1727 __ dsll(AT, as_Register(index), scale);
1728 __ addu(AT, as_Register(base), AT);
1729 }
1730 __ move(T9, disp);
1731 if( UseLoongsonISA ) {
1732 __ gslbx(as_Register(dst), AT, T9, 0);
1733 } else {
1734 __ addu(AT, AT, T9);
1735 __ lb(as_Register(dst), AT, 0);
1736 }
1737 }
1738 } else {
1739 if( Assembler::is_simm16(disp) ) {
1740 __ lb(as_Register(dst), as_Register(base), disp);
1741 } else {
1742 __ move(T9, disp);
1743 if( UseLoongsonISA ) {
1744 __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1745 } else {
1746 __ addu(AT, as_Register(base), T9);
1747 __ lb(as_Register(dst), AT, 0);
1748 }
1749 }
1750 }
1751 %}
1753 //Load byte unsigned
1754 enc_class load_UB_enc (mRegI dst, memory mem) %{
1755 MacroAssembler _masm(&cbuf);
1756 int dst = $dst$$reg;
1757 int base = $mem$$base;
1758 int index = $mem$$index;
1759 int scale = $mem$$scale;
1760 int disp = $mem$$disp;
1762 if( index != 0 ) {
1763 if (scale == 0) {
1764 __ daddu(AT, as_Register(base), as_Register(index));
1765 } else {
1766 __ dsll(AT, as_Register(index), scale);
1767 __ daddu(AT, as_Register(base), AT);
1768 }
1769 if( Assembler::is_simm16(disp) ) {
1770 __ lbu(as_Register(dst), AT, disp);
1771 } else {
1772 __ move(T9, disp);
1773 __ daddu(AT, AT, T9);
1774 __ lbu(as_Register(dst), AT, 0);
1775 }
1776 } else {
1777 if( Assembler::is_simm16(disp) ) {
1778 __ lbu(as_Register(dst), as_Register(base), disp);
1779 } else {
1780 __ move(T9, disp);
1781 __ daddu(AT, as_Register(base), T9);
1782 __ lbu(as_Register(dst), AT, 0);
1783 }
1784 }
1785 %}
1787 enc_class store_B_reg_enc (memory mem, mRegI src) %{
1788 MacroAssembler _masm(&cbuf);
1789 int src = $src$$reg;
1790 int base = $mem$$base;
1791 int index = $mem$$index;
1792 int scale = $mem$$scale;
1793 int disp = $mem$$disp;
1795 if( index != 0 ) {
1796 if (scale == 0) {
1797 if( Assembler::is_simm(disp, 8) ) {
1798 if (UseLoongsonISA) {
1799 __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1800 } else {
1801 __ addu(AT, as_Register(base), as_Register(index));
1802 __ sb(as_Register(src), AT, disp);
1803 }
1804 } else if( Assembler::is_simm16(disp) ) {
1805 __ addu(AT, as_Register(base), as_Register(index));
1806 __ sb(as_Register(src), AT, disp);
1807 } else {
1808 __ addu(AT, as_Register(base), as_Register(index));
1809 __ move(T9, disp);
1810 if (UseLoongsonISA) {
1811 __ gssbx(as_Register(src), AT, T9, 0);
1812 } else {
1813 __ addu(AT, AT, T9);
1814 __ sb(as_Register(src), AT, 0);
1815 }
1816 }
1817 } else {
1818 __ dsll(AT, as_Register(index), scale);
1819 if( Assembler::is_simm(disp, 8) ) {
1820 if (UseLoongsonISA) {
1821 __ gssbx(as_Register(src), AT, as_Register(base), disp);
1822 } else {
1823 __ addu(AT, as_Register(base), AT);
1824 __ sb(as_Register(src), AT, disp);
1825 }
1826 } else if( Assembler::is_simm16(disp) ) {
1827 __ addu(AT, as_Register(base), AT);
1828 __ sb(as_Register(src), AT, disp);
1829 } else {
1830 __ addu(AT, as_Register(base), AT);
1831 __ move(T9, disp);
1832 if (UseLoongsonISA) {
1833 __ gssbx(as_Register(src), AT, T9, 0);
1834 } else {
1835 __ addu(AT, AT, T9);
1836 __ sb(as_Register(src), AT, 0);
1837 }
1838 }
1839 }
1840 } else {
1841 if( Assembler::is_simm16(disp) ) {
1842 __ sb(as_Register(src), as_Register(base), disp);
1843 } else {
1844 __ move(T9, disp);
1845 if (UseLoongsonISA) {
1846 __ gssbx(as_Register(src), as_Register(base), T9, 0);
1847 } else {
1848 __ addu(AT, as_Register(base), T9);
1849 __ sb(as_Register(src), AT, 0);
1850 }
1851 }
1852 }
1853 %}
1855 enc_class store_B_immI_enc (memory mem, immI8 src) %{
1856 MacroAssembler _masm(&cbuf);
1857 int base = $mem$$base;
1858 int index = $mem$$index;
1859 int scale = $mem$$scale;
1860 int disp = $mem$$disp;
1861 int value = $src$$constant;
1863 if( index != 0 ) {
1864 if (!UseLoongsonISA) {
1865 if (scale == 0) {
1866 __ daddu(AT, as_Register(base), as_Register(index));
1867 } else {
1868 __ dsll(AT, as_Register(index), scale);
1869 __ daddu(AT, as_Register(base), AT);
1870 }
1871 if( Assembler::is_simm16(disp) ) {
1872 if (value == 0) {
1873 __ sb(R0, AT, disp);
1874 } else {
1875 __ move(T9, value);
1876 __ sb(T9, AT, disp);
1877 }
1878 } else {
1879 if (value == 0) {
1880 __ move(T9, disp);
1881 __ daddu(AT, AT, T9);
1882 __ sb(R0, AT, 0);
1883 } else {
1884 __ move(T9, disp);
1885 __ daddu(AT, AT, T9);
1886 __ move(T9, value);
1887 __ sb(T9, AT, 0);
1888 }
1889 }
1890 } else {
1892 if (scale == 0) {
1893 if( Assembler::is_simm(disp, 8) ) {
1894 if (value == 0) {
1895 __ gssbx(R0, as_Register(base), as_Register(index), disp);
1896 } else {
1897 __ move(T9, value);
1898 __ gssbx(T9, as_Register(base), as_Register(index), disp);
1899 }
1900 } else if( Assembler::is_simm16(disp) ) {
1901 __ daddu(AT, as_Register(base), as_Register(index));
1902 if (value == 0) {
1903 __ sb(R0, AT, disp);
1904 } else {
1905 __ move(T9, value);
1906 __ sb(T9, AT, disp);
1907 }
1908 } else {
1909 if (value == 0) {
1910 __ daddu(AT, as_Register(base), as_Register(index));
1911 __ move(T9, disp);
1912 __ gssbx(R0, AT, T9, 0);
1913 } else {
1914 __ move(AT, disp);
1915 __ move(T9, value);
1916 __ daddu(AT, as_Register(base), AT);
1917 __ gssbx(T9, AT, as_Register(index), 0);
1918 }
1919 }
1921 } else {
1923 if( Assembler::is_simm(disp, 8) ) {
1924 __ dsll(AT, as_Register(index), scale);
1925 if (value == 0) {
1926 __ gssbx(R0, as_Register(base), AT, disp);
1927 } else {
1928 __ move(T9, value);
1929 __ gssbx(T9, as_Register(base), AT, disp);
1930 }
1931 } else if( Assembler::is_simm16(disp) ) {
1932 __ dsll(AT, as_Register(index), scale);
1933 __ daddu(AT, as_Register(base), AT);
1934 if (value == 0) {
1935 __ sb(R0, AT, disp);
1936 } else {
1937 __ move(T9, value);
1938 __ sb(T9, AT, disp);
1939 }
1940 } else {
1941 __ dsll(AT, as_Register(index), scale);
1942 if (value == 0) {
1943 __ daddu(AT, as_Register(base), AT);
1944 __ move(T9, disp);
1945 __ gssbx(R0, AT, T9, 0);
1946 } else {
1947 __ move(T9, disp);
1948 __ daddu(AT, AT, T9);
1949 __ move(T9, value);
1950 __ gssbx(T9, as_Register(base), AT, 0);
1951 }
1952 }
1953 }
1954 }
1955 } else {
1956 if( Assembler::is_simm16(disp) ) {
1957 if (value == 0) {
1958 __ sb(R0, as_Register(base), disp);
1959 } else {
1960 __ move(AT, value);
1961 __ sb(AT, as_Register(base), disp);
1962 }
1963 } else {
1964 if (value == 0) {
1965 __ move(T9, disp);
1966 if (UseLoongsonISA) {
1967 __ gssbx(R0, as_Register(base), T9, 0);
1968 } else {
1969 __ daddu(AT, as_Register(base), T9);
1970 __ sb(R0, AT, 0);
1971 }
1972 } else {
1973 __ move(T9, disp);
1974 if (UseLoongsonISA) {
1975 __ move(AT, value);
1976 __ gssbx(AT, as_Register(base), T9, 0);
1977 } else {
1978 __ daddu(AT, as_Register(base), T9);
1979 __ move(T9, value);
1980 __ sb(T9, AT, 0);
1981 }
1982 }
1983 }
1984 }
1985 %}
1988 enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
1989 MacroAssembler _masm(&cbuf);
1990 int base = $mem$$base;
1991 int index = $mem$$index;
1992 int scale = $mem$$scale;
1993 int disp = $mem$$disp;
1994 int value = $src$$constant;
1996 if( index != 0 ) {
1997 if ( UseLoongsonISA ) {
1998 if ( Assembler::is_simm(disp,8) ) {
1999 if ( scale == 0 ) {
2000 if ( value == 0 ) {
2001 __ gssbx(R0, as_Register(base), as_Register(index), disp);
2002 } else {
2003 __ move(AT, value);
2004 __ gssbx(AT, as_Register(base), as_Register(index), disp);
2005 }
2006 } else {
2007 __ dsll(AT, as_Register(index), scale);
2008 if ( value == 0 ) {
2009 __ gssbx(R0, as_Register(base), AT, disp);
2010 } else {
2011 __ move(T9, value);
2012 __ gssbx(T9, as_Register(base), AT, disp);
2013 }
2014 }
2015 } else if ( Assembler::is_simm16(disp) ) {
2016 if ( scale == 0 ) {
2017 __ daddu(AT, as_Register(base), as_Register(index));
2018 if ( value == 0 ){
2019 __ sb(R0, AT, disp);
2020 } else {
2021 __ move(T9, value);
2022 __ sb(T9, AT, disp);
2023 }
2024 } else {
2025 __ dsll(AT, as_Register(index), scale);
2026 __ daddu(AT, as_Register(base), AT);
2027 if ( value == 0 ) {
2028 __ sb(R0, AT, disp);
2029 } else {
2030 __ move(T9, value);
2031 __ sb(T9, AT, disp);
2032 }
2033 }
2034 } else {
2035 if ( scale == 0 ) {
2036 __ move(AT, disp);
2037 __ daddu(AT, as_Register(index), AT);
2038 if ( value == 0 ) {
2039 __ gssbx(R0, as_Register(base), AT, 0);
2040 } else {
2041 __ move(T9, value);
2042 __ gssbx(T9, as_Register(base), AT, 0);
2043 }
2044 } else {
2045 __ dsll(AT, as_Register(index), scale);
2046 __ move(T9, disp);
2047 __ daddu(AT, AT, T9);
2048 if ( value == 0 ) {
2049 __ gssbx(R0, as_Register(base), AT, 0);
2050 } else {
2051 __ move(T9, value);
2052 __ gssbx(T9, as_Register(base), AT, 0);
2053 }
2054 }
2055 }
2056 } else { //not use loongson isa
2057 if (scale == 0) {
2058 __ daddu(AT, as_Register(base), as_Register(index));
2059 } else {
2060 __ dsll(AT, as_Register(index), scale);
2061 __ daddu(AT, as_Register(base), AT);
2062 }
2063 if( Assembler::is_simm16(disp) ) {
2064 if (value == 0) {
2065 __ sb(R0, AT, disp);
2066 } else {
2067 __ move(T9, value);
2068 __ sb(T9, AT, disp);
2069 }
2070 } else {
2071 if (value == 0) {
2072 __ move(T9, disp);
2073 __ daddu(AT, AT, T9);
2074 __ sb(R0, AT, 0);
2075 } else {
2076 __ move(T9, disp);
2077 __ daddu(AT, AT, T9);
2078 __ move(T9, value);
2079 __ sb(T9, AT, 0);
2080 }
2081 }
2082 }
2083 } else {
2084 if ( UseLoongsonISA ){
2085 if ( Assembler::is_simm16(disp) ){
2086 if ( value == 0 ) {
2087 __ sb(R0, as_Register(base), disp);
2088 } else {
2089 __ move(AT, value);
2090 __ sb(AT, as_Register(base), disp);
2091 }
2092 } else {
2093 __ move(AT, disp);
2094 if ( value == 0 ) {
2095 __ gssbx(R0, as_Register(base), AT, 0);
2096 } else {
2097 __ move(T9, value);
2098 __ gssbx(T9, as_Register(base), AT, 0);
2099 }
2100 }
2101 } else {
2102 if( Assembler::is_simm16(disp) ) {
2103 if (value == 0) {
2104 __ sb(R0, as_Register(base), disp);
2105 } else {
2106 __ move(AT, value);
2107 __ sb(AT, as_Register(base), disp);
2108 }
2109 } else {
2110 if (value == 0) {
2111 __ move(T9, disp);
2112 __ daddu(AT, as_Register(base), T9);
2113 __ sb(R0, AT, 0);
2114 } else {
2115 __ move(T9, disp);
2116 __ daddu(AT, as_Register(base), T9);
2117 __ move(T9, value);
2118 __ sb(T9, AT, 0);
2119 }
2120 }
2121 }
2122 }
2124 __ sync();
2125 %}
2127 // Load Short (16bit signed)
2128 enc_class load_S_enc (mRegI dst, memory mem) %{
2129 MacroAssembler _masm(&cbuf);
2130 int dst = $dst$$reg;
2131 int base = $mem$$base;
2132 int index = $mem$$index;
2133 int scale = $mem$$scale;
2134 int disp = $mem$$disp;
2136 if( index != 0 ) {
2137 if ( UseLoongsonISA ) {
2138 if ( Assembler::is_simm(disp, 8) ) {
2139 if (scale == 0) {
2140 __ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
2141 } else {
2142 __ dsll(AT, as_Register(index), scale);
2143 __ gslhx(as_Register(dst), as_Register(base), AT, disp);
2144 }
2145 } else if ( Assembler::is_simm16(disp) ) {
2146 if (scale == 0) {
2147 __ daddu(AT, as_Register(base), as_Register(index));
2148 __ lh(as_Register(dst), AT, disp);
2149 } else {
2150 __ dsll(AT, as_Register(index), scale);
2151 __ daddu(AT, as_Register(base), AT);
2152 __ lh(as_Register(dst), AT, disp);
2153 }
2154 } else {
2155 if (scale == 0) {
2156 __ move(AT, disp);
2157 __ daddu(AT, as_Register(index), AT);
2158 __ gslhx(as_Register(dst), as_Register(base), AT, 0);
2159 } else {
2160 __ dsll(AT, as_Register(index), scale);
2161 __ move(T9, disp);
2162 __ daddu(AT, AT, T9);
2163 __ gslhx(as_Register(dst), as_Register(base), AT, 0);
2164 }
2165 }
2166 } else { // not use loongson isa
2167 if (scale == 0) {
2168 __ daddu(AT, as_Register(base), as_Register(index));
2169 } else {
2170 __ dsll(AT, as_Register(index), scale);
2171 __ daddu(AT, as_Register(base), AT);
2172 }
2173 if( Assembler::is_simm16(disp) ) {
2174 __ lh(as_Register(dst), AT, disp);
2175 } else {
2176 __ move(T9, disp);
2177 __ daddu(AT, AT, T9);
2178 __ lh(as_Register(dst), AT, 0);
2179 }
2180 }
2181 } else { // index is 0
2182 if ( UseLoongsonISA ) {
2183 if ( Assembler::is_simm16(disp) ) {
2184 __ lh(as_Register(dst), as_Register(base), disp);
2185 } else {
2186 __ move(T9, disp);
2187 __ gslhx(as_Register(dst), as_Register(base), T9, 0);
2188 }
2189 } else { //not use loongson isa
2190 if( Assembler::is_simm16(disp) ) {
2191 __ lh(as_Register(dst), as_Register(base), disp);
2192 } else {
2193 __ move(T9, disp);
2194 __ daddu(AT, as_Register(base), T9);
2195 __ lh(as_Register(dst), AT, 0);
2196 }
2197 }
2198 }
2199 %}
2201 // Load Char (16bit unsigned)
2202 enc_class load_C_enc (mRegI dst, memory mem) %{
2203 MacroAssembler _masm(&cbuf);
2204 int dst = $dst$$reg;
2205 int base = $mem$$base;
2206 int index = $mem$$index;
2207 int scale = $mem$$scale;
2208 int disp = $mem$$disp;
2210 if( index != 0 ) {
2211 if (scale == 0) {
2212 __ daddu(AT, as_Register(base), as_Register(index));
2213 } else {
2214 __ dsll(AT, as_Register(index), scale);
2215 __ daddu(AT, as_Register(base), AT);
2216 }
2217 if( Assembler::is_simm16(disp) ) {
2218 __ lhu(as_Register(dst), AT, disp);
2219 } else {
2220 __ move(T9, disp);
2221 __ addu(AT, AT, T9);
2222 __ lhu(as_Register(dst), AT, 0);
2223 }
2224 } else {
2225 if( Assembler::is_simm16(disp) ) {
2226 __ lhu(as_Register(dst), as_Register(base), disp);
2227 } else {
2228 __ move(T9, disp);
2229 __ daddu(AT, as_Register(base), T9);
2230 __ lhu(as_Register(dst), AT, 0);
2231 }
2232 }
2233 %}
2235 // Store Char (16bit unsigned)
2236 enc_class store_C_reg_enc (memory mem, mRegI src) %{
2237 MacroAssembler _masm(&cbuf);
2238 int src = $src$$reg;
2239 int base = $mem$$base;
2240 int index = $mem$$index;
2241 int scale = $mem$$scale;
2242 int disp = $mem$$disp;
2244 if( index != 0 ) {
2245 if( Assembler::is_simm16(disp) ) {
2246 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2247 if (scale == 0) {
2248 __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
2249 } else {
2250 __ dsll(AT, as_Register(index), scale);
2251 __ gsshx(as_Register(src), as_Register(base), AT, disp);
2252 }
2253 } else {
2254 if (scale == 0) {
2255 __ addu(AT, as_Register(base), as_Register(index));
2256 } else {
2257 __ dsll(AT, as_Register(index), scale);
2258 __ addu(AT, as_Register(base), AT);
2259 }
2260 __ sh(as_Register(src), AT, disp);
2261 }
2262 } else {
2263 if (scale == 0) {
2264 __ addu(AT, as_Register(base), as_Register(index));
2265 } else {
2266 __ dsll(AT, as_Register(index), scale);
2267 __ addu(AT, as_Register(base), AT);
2268 }
2269 __ move(T9, disp);
2270 if( UseLoongsonISA ) {
2271 __ gsshx(as_Register(src), AT, T9, 0);
2272 } else {
2273 __ addu(AT, AT, T9);
2274 __ sh(as_Register(src), AT, 0);
2275 }
2276 }
2277 } else {
2278 if( Assembler::is_simm16(disp) ) {
2279 __ sh(as_Register(src), as_Register(base), disp);
2280 } else {
2281 __ move(T9, disp);
2282 if( UseLoongsonISA ) {
2283 __ gsshx(as_Register(src), as_Register(base), T9, 0);
2284 } else {
2285 __ addu(AT, as_Register(base), T9);
2286 __ sh(as_Register(src), AT, 0);
2287 }
2288 }
2289 }
2290 %}
2292 enc_class store_C0_enc (memory mem) %{
2293 MacroAssembler _masm(&cbuf);
2294 int base = $mem$$base;
2295 int index = $mem$$index;
2296 int scale = $mem$$scale;
2297 int disp = $mem$$disp;
2299 if( index != 0 ) {
2300 if( Assembler::is_simm16(disp) ) {
2301 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2302 if (scale == 0) {
2303 __ gsshx(R0, as_Register(base), as_Register(index), disp);
2304 } else {
2305 __ dsll(AT, as_Register(index), scale);
2306 __ gsshx(R0, as_Register(base), AT, disp);
2307 }
2308 } else {
2309 if (scale == 0) {
2310 __ addu(AT, as_Register(base), as_Register(index));
2311 } else {
2312 __ dsll(AT, as_Register(index), scale);
2313 __ addu(AT, as_Register(base), AT);
2314 }
2315 __ sh(R0, AT, disp);
2316 }
2317 } else {
2318 if (scale == 0) {
2319 __ addu(AT, as_Register(base), as_Register(index));
2320 } else {
2321 __ dsll(AT, as_Register(index), scale);
2322 __ addu(AT, as_Register(base), AT);
2323 }
2324 __ move(T9, disp);
2325 if( UseLoongsonISA ) {
2326 __ gsshx(R0, AT, T9, 0);
2327 } else {
2328 __ addu(AT, AT, T9);
2329 __ sh(R0, AT, 0);
2330 }
2331 }
2332 } else {
2333 if( Assembler::is_simm16(disp) ) {
2334 __ sh(R0, as_Register(base), disp);
2335 } else {
2336 __ move(T9, disp);
2337 if( UseLoongsonISA ) {
2338 __ gsshx(R0, as_Register(base), T9, 0);
2339 } else {
2340 __ addu(AT, as_Register(base), T9);
2341 __ sh(R0, AT, 0);
2342 }
2343 }
2344 }
2345 %}
2347 enc_class load_I_enc (mRegI dst, memory mem) %{
2348 MacroAssembler _masm(&cbuf);
2349 int dst = $dst$$reg;
2350 int base = $mem$$base;
2351 int index = $mem$$index;
2352 int scale = $mem$$scale;
2353 int disp = $mem$$disp;
2355 if( index != 0 ) {
2356 if( Assembler::is_simm16(disp) ) {
2357 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2358 if (scale == 0) {
2359 __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
2360 } else {
2361 __ dsll(AT, as_Register(index), scale);
2362 __ gslwx(as_Register(dst), as_Register(base), AT, disp);
2363 }
2364 } else {
2365 if (scale == 0) {
2366 __ addu(AT, as_Register(base), as_Register(index));
2367 } else {
2368 __ dsll(AT, as_Register(index), scale);
2369 __ addu(AT, as_Register(base), AT);
2370 }
2371 __ lw(as_Register(dst), AT, disp);
2372 }
2373 } else {
2374 if (scale == 0) {
2375 __ addu(AT, as_Register(base), as_Register(index));
2376 } else {
2377 __ dsll(AT, as_Register(index), scale);
2378 __ addu(AT, as_Register(base), AT);
2379 }
2380 __ move(T9, disp);
2381 if( UseLoongsonISA ) {
2382 __ gslwx(as_Register(dst), AT, T9, 0);
2383 } else {
2384 __ addu(AT, AT, T9);
2385 __ lw(as_Register(dst), AT, 0);
2386 }
2387 }
2388 } else {
2389 if( Assembler::is_simm16(disp) ) {
2390 __ lw(as_Register(dst), as_Register(base), disp);
2391 } else {
2392 __ move(T9, disp);
2393 if( UseLoongsonISA ) {
2394 __ gslwx(as_Register(dst), as_Register(base), T9, 0);
2395 } else {
2396 __ addu(AT, as_Register(base), T9);
2397 __ lw(as_Register(dst), AT, 0);
2398 }
2399 }
2400 }
2401 %}
2403 enc_class store_I_reg_enc (memory mem, mRegI src) %{
2404 MacroAssembler _masm(&cbuf);
2405 int src = $src$$reg;
2406 int base = $mem$$base;
2407 int index = $mem$$index;
2408 int scale = $mem$$scale;
2409 int disp = $mem$$disp;
2411 if( index != 0 ) {
2412 if( Assembler::is_simm16(disp) ) {
2413 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2414 if (scale == 0) {
2415 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
2416 } else {
2417 __ dsll(AT, as_Register(index), scale);
2418 __ gsswx(as_Register(src), as_Register(base), AT, disp);
2419 }
2420 } else {
2421 if (scale == 0) {
2422 __ addu(AT, as_Register(base), as_Register(index));
2423 } else {
2424 __ dsll(AT, as_Register(index), scale);
2425 __ addu(AT, as_Register(base), AT);
2426 }
2427 __ sw(as_Register(src), AT, disp);
2428 }
2429 } else {
2430 if (scale == 0) {
2431 __ addu(AT, as_Register(base), as_Register(index));
2432 } else {
2433 __ dsll(AT, as_Register(index), scale);
2434 __ addu(AT, as_Register(base), AT);
2435 }
2436 __ move(T9, disp);
2437 if( UseLoongsonISA ) {
2438 __ gsswx(as_Register(src), AT, T9, 0);
2439 } else {
2440 __ addu(AT, AT, T9);
2441 __ sw(as_Register(src), AT, 0);
2442 }
2443 }
2444 } else {
2445 if( Assembler::is_simm16(disp) ) {
2446 __ sw(as_Register(src), as_Register(base), disp);
2447 } else {
2448 __ move(T9, disp);
2449 if( UseLoongsonISA ) {
2450 __ gsswx(as_Register(src), as_Register(base), T9, 0);
2451 } else {
2452 __ addu(AT, as_Register(base), T9);
2453 __ sw(as_Register(src), AT, 0);
2454 }
2455 }
2456 }
2457 %}
2459 enc_class store_I_immI_enc (memory mem, immI src) %{
2460 MacroAssembler _masm(&cbuf);
2461 int base = $mem$$base;
2462 int index = $mem$$index;
2463 int scale = $mem$$scale;
2464 int disp = $mem$$disp;
2465 int value = $src$$constant;
2467 if( index != 0 ) {
2468 if ( UseLoongsonISA ) {
2469 if ( Assembler::is_simm(disp, 8) ) {
2470 if ( scale == 0 ) {
2471 if ( value == 0 ) {
2472 __ gsswx(R0, as_Register(base), as_Register(index), disp);
2473 } else {
2474 __ move(T9, value);
2475 __ gsswx(T9, as_Register(base), as_Register(index), disp);
2476 }
2477 } else {
2478 __ dsll(AT, as_Register(index), scale);
2479 if ( value == 0 ) {
2480 __ gsswx(R0, as_Register(base), AT, disp);
2481 } else {
2482 __ move(T9, value);
2483 __ gsswx(T9, as_Register(base), AT, disp);
2484 }
2485 }
2486 } else if ( Assembler::is_simm16(disp) ) {
2487 if ( scale == 0 ) {
2488 __ daddu(AT, as_Register(base), as_Register(index));
2489 if ( value == 0 ) {
2490 __ sw(R0, AT, disp);
2491 } else {
2492 __ move(T9, value);
2493 __ sw(T9, AT, disp);
2494 }
2495 } else {
2496 __ dsll(AT, as_Register(index), scale);
2497 __ daddu(AT, as_Register(base), AT);
2498 if ( value == 0 ) {
2499 __ sw(R0, AT, disp);
2500 } else {
2501 __ move(T9, value);
2502 __ sw(T9, AT, disp);
2503 }
2504 }
2505 } else {
2506 if ( scale == 0 ) {
2507 __ move(T9, disp);
2508 __ daddu(AT, as_Register(index), T9);
2509 if ( value ==0 ) {
2510 __ gsswx(R0, as_Register(base), AT, 0);
2511 } else {
2512 __ move(T9, value);
2513 __ gsswx(T9, as_Register(base), AT, 0);
2514 }
2515 } else {
2516 __ dsll(AT, as_Register(index), scale);
2517 __ move(T9, disp);
2518 __ daddu(AT, AT, T9);
2519 if ( value == 0 ) {
2520 __ gsswx(R0, as_Register(base), AT, 0);
2521 } else {
2522 __ move(T9, value);
2523 __ gsswx(T9, as_Register(base), AT, 0);
2524 }
2525 }
2526 }
2527 } else { //not use loongson isa
2528 if (scale == 0) {
2529 __ daddu(AT, as_Register(base), as_Register(index));
2530 } else {
2531 __ dsll(AT, as_Register(index), scale);
2532 __ daddu(AT, as_Register(base), AT);
2533 }
2534 if( Assembler::is_simm16(disp) ) {
2535 if (value == 0) {
2536 __ sw(R0, AT, disp);
2537 } else {
2538 __ move(T9, value);
2539 __ sw(T9, AT, disp);
2540 }
2541 } else {
2542 if (value == 0) {
2543 __ move(T9, disp);
2544 __ daddu(AT, AT, T9);
2545 __ sw(R0, AT, 0);
2546 } else {
2547 __ move(T9, disp);
2548 __ daddu(AT, AT, T9);
2549 __ move(T9, value);
2550 __ sw(T9, AT, 0);
2551 }
2552 }
2553 }
2554 } else {
2555 if ( UseLoongsonISA ) {
2556 if ( Assembler::is_simm16(disp) ) {
2557 if ( value == 0 ) {
2558 __ sw(R0, as_Register(base), disp);
2559 } else {
2560 __ move(AT, value);
2561 __ sw(AT, as_Register(base), disp);
2562 }
2563 } else {
2564 __ move(T9, disp);
2565 if ( value == 0 ) {
2566 __ gsswx(R0, as_Register(base), T9, 0);
2567 } else {
2568 __ move(AT, value);
2569 __ gsswx(AT, as_Register(base), T9, 0);
2570 }
2571 }
2572 } else {
2573 if( Assembler::is_simm16(disp) ) {
2574 if (value == 0) {
2575 __ sw(R0, as_Register(base), disp);
2576 } else {
2577 __ move(AT, value);
2578 __ sw(AT, as_Register(base), disp);
2579 }
2580 } else {
2581 if (value == 0) {
2582 __ move(T9, disp);
2583 __ daddu(AT, as_Register(base), T9);
2584 __ sw(R0, AT, 0);
2585 } else {
2586 __ move(T9, disp);
2587 __ daddu(AT, as_Register(base), T9);
2588 __ move(T9, value);
2589 __ sw(T9, AT, 0);
2590 }
2591 }
2592 }
2593 }
2594 %}
2596 enc_class load_N_enc (mRegN dst, memory mem) %{
2597 MacroAssembler _masm(&cbuf);
2598 int dst = $dst$$reg;
2599 int base = $mem$$base;
2600 int index = $mem$$index;
2601 int scale = $mem$$scale;
2602 int disp = $mem$$disp;
2603 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2604 assert(disp_reloc == relocInfo::none, "cannot have disp");
2606 if( index != 0 ) {
2607 if (scale == 0) {
2608 __ daddu(AT, as_Register(base), as_Register(index));
2609 } else {
2610 __ dsll(AT, as_Register(index), scale);
2611 __ daddu(AT, as_Register(base), AT);
2612 }
2613 if( Assembler::is_simm16(disp) ) {
2614 __ lwu(as_Register(dst), AT, disp);
2615 } else {
2616 __ set64(T9, disp);
2617 __ daddu(AT, AT, T9);
2618 __ lwu(as_Register(dst), AT, 0);
2619 }
2620 } else {
2621 if( Assembler::is_simm16(disp) ) {
2622 __ lwu(as_Register(dst), as_Register(base), disp);
2623 } else {
2624 __ set64(T9, disp);
2625 __ daddu(AT, as_Register(base), T9);
2626 __ lwu(as_Register(dst), AT, 0);
2627 }
2628 }
2630 %}
2633 enc_class load_P_enc (mRegP dst, memory mem) %{
2634 MacroAssembler _masm(&cbuf);
2635 int dst = $dst$$reg;
2636 int base = $mem$$base;
2637 int index = $mem$$index;
2638 int scale = $mem$$scale;
2639 int disp = $mem$$disp;
2640 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2641 assert(disp_reloc == relocInfo::none, "cannot have disp");
2643 if( index != 0 ) {
2644 if ( UseLoongsonISA ) {
2645 if ( Assembler::is_simm(disp, 8) ) {
2646 if ( scale != 0 ) {
2647 __ dsll(AT, as_Register(index), scale);
2648 __ gsldx(as_Register(dst), as_Register(base), AT, disp);
2649 } else {
2650 __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
2651 }
2652 } else if ( Assembler::is_simm16(disp) ){
2653 if ( scale != 0 ) {
2654 __ dsll(AT, as_Register(index), scale);
2655 __ daddu(AT, AT, as_Register(base));
2656 } else {
2657 __ daddu(AT, as_Register(index), as_Register(base));
2658 }
2659 __ ld(as_Register(dst), AT, disp);
2660 } else {
2661 if ( scale != 0 ) {
2662 __ dsll(AT, as_Register(index), scale);
2663 __ move(T9, disp);
2664 __ daddu(AT, AT, T9);
2665 } else {
2666 __ move(T9, disp);
2667 __ daddu(AT, as_Register(index), T9);
2668 }
2669 __ gsldx(as_Register(dst), as_Register(base), AT, 0);
2670 }
2671 } else { //not use loongson isa
2672 if (scale == 0) {
2673 __ daddu(AT, as_Register(base), as_Register(index));
2674 } else {
2675 __ dsll(AT, as_Register(index), scale);
2676 __ daddu(AT, as_Register(base), AT);
2677 }
2678 if( Assembler::is_simm16(disp) ) {
2679 __ ld(as_Register(dst), AT, disp);
2680 } else {
2681 __ set64(T9, disp);
2682 __ daddu(AT, AT, T9);
2683 __ ld(as_Register(dst), AT, 0);
2684 }
2685 }
2686 } else {
2687 if ( UseLoongsonISA ) {
2688 if ( Assembler::is_simm16(disp) ){
2689 __ ld(as_Register(dst), as_Register(base), disp);
2690 } else {
2691 __ set64(T9, disp);
2692 __ gsldx(as_Register(dst), as_Register(base), T9, 0);
2693 }
2694 } else { //not use loongson isa
2695 if( Assembler::is_simm16(disp) ) {
2696 __ ld(as_Register(dst), as_Register(base), disp);
2697 } else {
2698 __ set64(T9, disp);
2699 __ daddu(AT, as_Register(base), T9);
2700 __ ld(as_Register(dst), AT, 0);
2701 }
2702 }
2703 }
2704 // if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
2705 %}
2707 enc_class store_P_reg_enc (memory mem, mRegP src) %{
2708 MacroAssembler _masm(&cbuf);
2709 int src = $src$$reg;
2710 int base = $mem$$base;
2711 int index = $mem$$index;
2712 int scale = $mem$$scale;
2713 int disp = $mem$$disp;
2715 if( index != 0 ) {
2716 if ( UseLoongsonISA ){
2717 if ( Assembler::is_simm(disp, 8) ) {
2718 if ( scale == 0 ) {
2719 __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
2720 } else {
2721 __ dsll(AT, as_Register(index), scale);
2722 __ gssdx(as_Register(src), as_Register(base), AT, disp);
2723 }
2724 } else if ( Assembler::is_simm16(disp) ) {
2725 if ( scale == 0 ) {
2726 __ daddu(AT, as_Register(base), as_Register(index));
2727 } else {
2728 __ dsll(AT, as_Register(index), scale);
2729 __ daddu(AT, as_Register(base), AT);
2730 }
2731 __ sd(as_Register(src), AT, disp);
2732 } else {
2733 if ( scale == 0 ) {
2734 __ move(T9, disp);
2735 __ daddu(AT, as_Register(index), T9);
2736 } else {
2737 __ dsll(AT, as_Register(index), scale);
2738 __ move(T9, disp);
2739 __ daddu(AT, AT, T9);
2740 }
2741 __ gssdx(as_Register(src), as_Register(base), AT, 0);
2742 }
2743 } else { //not use loongson isa
2744 if (scale == 0) {
2745 __ daddu(AT, as_Register(base), as_Register(index));
2746 } else {
2747 __ dsll(AT, as_Register(index), scale);
2748 __ daddu(AT, as_Register(base), AT);
2749 }
2750 if( Assembler::is_simm16(disp) ) {
2751 __ sd(as_Register(src), AT, disp);
2752 } else {
2753 __ move(T9, disp);
2754 __ daddu(AT, AT, T9);
2755 __ sd(as_Register(src), AT, 0);
2756 }
2757 }
2758 } else {
2759 if ( UseLoongsonISA ) {
2760 if ( Assembler::is_simm16(disp) ) {
2761 __ sd(as_Register(src), as_Register(base), disp);
2762 } else {
2763 __ move(T9, disp);
2764 __ gssdx(as_Register(src), as_Register(base), T9, 0);
2765 }
2766 } else {
2767 if( Assembler::is_simm16(disp) ) {
2768 __ sd(as_Register(src), as_Register(base), disp);
2769 } else {
2770 __ move(T9, disp);
2771 __ daddu(AT, as_Register(base), T9);
2772 __ sd(as_Register(src), AT, 0);
2773 }
2774 }
2775 }
2776 %}
2778 enc_class store_N_reg_enc (memory mem, mRegN src) %{
2779 MacroAssembler _masm(&cbuf);
2780 int src = $src$$reg;
2781 int base = $mem$$base;
2782 int index = $mem$$index;
2783 int scale = $mem$$scale;
2784 int disp = $mem$$disp;
2786 if( index != 0 ) {
2787 if ( UseLoongsonISA ){
2788 if ( Assembler::is_simm(disp, 8) ) {
2789 if ( scale == 0 ) {
2790 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
2791 } else {
2792 __ dsll(AT, as_Register(index), scale);
2793 __ gsswx(as_Register(src), as_Register(base), AT, disp);
2794 }
2795 } else if ( Assembler::is_simm16(disp) ) {
2796 if ( scale == 0 ) {
2797 __ daddu(AT, as_Register(base), as_Register(index));
2798 } else {
2799 __ dsll(AT, as_Register(index), scale);
2800 __ daddu(AT, as_Register(base), AT);
2801 }
2802 __ sw(as_Register(src), AT, disp);
2803 } else {
2804 if ( scale == 0 ) {
2805 __ move(T9, disp);
2806 __ daddu(AT, as_Register(index), T9);
2807 } else {
2808 __ dsll(AT, as_Register(index), scale);
2809 __ move(T9, disp);
2810 __ daddu(AT, AT, T9);
2811 }
2812 __ gsswx(as_Register(src), as_Register(base), AT, 0);
2813 }
2814 } else { //not use loongson isa
2815 if (scale == 0) {
2816 __ daddu(AT, as_Register(base), as_Register(index));
2817 } else {
2818 __ dsll(AT, as_Register(index), scale);
2819 __ daddu(AT, as_Register(base), AT);
2820 }
2821 if( Assembler::is_simm16(disp) ) {
2822 __ sw(as_Register(src), AT, disp);
2823 } else {
2824 __ move(T9, disp);
2825 __ daddu(AT, AT, T9);
2826 __ sw(as_Register(src), AT, 0);
2827 }
2828 }
2829 } else {
2830 if ( UseLoongsonISA ) {
2831 if ( Assembler::is_simm16(disp) ) {
2832 __ sw(as_Register(src), as_Register(base), disp);
2833 } else {
2834 __ move(T9, disp);
2835 __ gsswx(as_Register(src), as_Register(base), T9, 0);
2836 }
2837 } else {
2838 if( Assembler::is_simm16(disp) ) {
2839 __ sw(as_Register(src), as_Register(base), disp);
2840 } else {
2841 __ move(T9, disp);
2842 __ daddu(AT, as_Register(base), T9);
2843 __ sw(as_Register(src), AT, 0);
2844 }
2845 }
2846 }
2847 %}
2849 enc_class store_P_immP0_enc (memory mem) %{
2850 MacroAssembler _masm(&cbuf);
2851 int base = $mem$$base;
2852 int index = $mem$$index;
2853 int scale = $mem$$scale;
2854 int disp = $mem$$disp;
2856 if( index != 0 ) {
2857 if (scale == 0) {
2858 if( Assembler::is_simm16(disp) ) {
2859 if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
2860 __ gssdx(R0, as_Register(base), as_Register(index), disp);
2861 } else {
2862 __ daddu(AT, as_Register(base), as_Register(index));
2863 __ sd(R0, AT, disp);
2864 }
2865 } else {
2866 __ daddu(AT, as_Register(base), as_Register(index));
2867 __ move(T9, disp);
2868 if(UseLoongsonISA) {
2869 __ gssdx(R0, AT, T9, 0);
2870 } else {
2871 __ daddu(AT, AT, T9);
2872 __ sd(R0, AT, 0);
2873 }
2874 }
2875 } else {
2876 __ dsll(AT, as_Register(index), scale);
2877 if( Assembler::is_simm16(disp) ) {
2878 if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
2879 __ gssdx(R0, as_Register(base), AT, disp);
2880 } else {
2881 __ daddu(AT, as_Register(base), AT);
2882 __ sd(R0, AT, disp);
2883 }
2884 } else {
2885 __ daddu(AT, as_Register(base), AT);
2886 __ move(T9, disp);
2887 if (UseLoongsonISA) {
2888 __ gssdx(R0, AT, T9, 0);
2889 } else {
2890 __ daddu(AT, AT, T9);
2891 __ sd(R0, AT, 0);
2892 }
2893 }
2894 }
2895 } else {
2896 if( Assembler::is_simm16(disp) ) {
2897 __ sd(R0, as_Register(base), disp);
2898 } else {
2899 __ move(T9, disp);
2900 if (UseLoongsonISA) {
2901 __ gssdx(R0, as_Register(base), T9, 0);
2902 } else {
2903 __ daddu(AT, as_Register(base), T9);
2904 __ sd(R0, AT, 0);
2905 }
2906 }
2907 }
2908 %}
2910 enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
2911 MacroAssembler _masm(&cbuf);
2912 int base = $mem$$base;
2913 int index = $mem$$index;
2914 int scale = $mem$$scale;
2915 int disp = $mem$$disp;
2917 if(index!=0){
2918 if (scale == 0) {
2919 __ daddu(AT, as_Register(base), as_Register(index));
2920 } else {
2921 __ dsll(AT, as_Register(index), scale);
2922 __ daddu(AT, as_Register(base), AT);
2923 }
2925 if( Assembler::is_simm16(disp) ) {
2926 __ sw(R0, AT, disp);
2927 } else {
2928 __ move(T9, disp);
2929 __ daddu(AT, AT, T9);
2930 __ sw(R0, AT, 0);
2931 }
2932 }
2933 else {
2934 if( Assembler::is_simm16(disp) ) {
2935 __ sw(R0, as_Register(base), disp);
2936 } else {
2937 __ move(T9, disp);
2938 __ daddu(AT, as_Register(base), T9);
2939 __ sw(R0, AT, 0);
2940 }
2941 }
2942 %}
2944 enc_class load_L_enc (mRegL dst, memory mem) %{
2945 MacroAssembler _masm(&cbuf);
2946 int base = $mem$$base;
2947 int index = $mem$$index;
2948 int scale = $mem$$scale;
2949 int disp = $mem$$disp;
2950 Register dst_reg = as_Register($dst$$reg);
2952 // For implicit null check
2953 __ lb(AT, as_Register(base), 0);
2955 if( index != 0 ) {
2956 if (scale == 0) {
2957 __ daddu(AT, as_Register(base), as_Register(index));
2958 } else {
2959 __ dsll(AT, as_Register(index), scale);
2960 __ daddu(AT, as_Register(base), AT);
2961 }
2962 if( Assembler::is_simm16(disp) ) {
2963 __ ld(dst_reg, AT, disp);
2964 } else {
2965 __ move(T9, disp);
2966 __ daddu(AT, AT, T9);
2967 __ ld(dst_reg, AT, 0);
2968 }
2969 } else {
2970 if( Assembler::is_simm16(disp) ) {
2971 __ ld(dst_reg, as_Register(base), disp);
2972 } else {
2973 __ move(T9, disp);
2974 __ daddu(AT, as_Register(base), T9);
2975 __ ld(dst_reg, AT, 0);
2976 }
2977 }
2978 %}
2980 enc_class store_L_reg_enc (memory mem, mRegL src) %{
2981 MacroAssembler _masm(&cbuf);
2982 int base = $mem$$base;
2983 int index = $mem$$index;
2984 int scale = $mem$$scale;
2985 int disp = $mem$$disp;
2986 Register src_reg = as_Register($src$$reg);
2988 if( index != 0 ) {
2989 if (scale == 0) {
2990 __ daddu(AT, as_Register(base), as_Register(index));
2991 } else {
2992 __ dsll(AT, as_Register(index), scale);
2993 __ daddu(AT, as_Register(base), AT);
2994 }
2995 if( Assembler::is_simm16(disp) ) {
2996 __ sd(src_reg, AT, disp);
2997 } else {
2998 __ move(T9, disp);
2999 __ daddu(AT, AT, T9);
3000 __ sd(src_reg, AT, 0);
3001 }
3002 } else {
3003 if( Assembler::is_simm16(disp) ) {
3004 __ sd(src_reg, as_Register(base), disp);
3005 } else {
3006 __ move(T9, disp);
3007 __ daddu(AT, as_Register(base), T9);
3008 __ sd(src_reg, AT, 0);
3009 }
3010 }
3011 %}
3013 enc_class store_L_immL0_enc (memory mem, immL0 src) %{
3014 MacroAssembler _masm(&cbuf);
3015 int base = $mem$$base;
3016 int index = $mem$$index;
3017 int scale = $mem$$scale;
3018 int disp = $mem$$disp;
3020 if( index != 0 ) {
3021 // For implicit null check
3022 __ lb(AT, as_Register(base), 0);
3024 if (scale == 0) {
3025 __ daddu(AT, as_Register(base), as_Register(index));
3026 } else {
3027 __ dsll(AT, as_Register(index), scale);
3028 __ daddu(AT, as_Register(base), AT);
3029 }
3030 if( Assembler::is_simm16(disp) ) {
3031 __ sd(R0, AT, disp);
3032 } else {
3033 __ move(T9, disp);
3034 __ addu(AT, AT, T9);
3035 __ sd(R0, AT, 0);
3036 }
3037 } else {
3038 if( Assembler::is_simm16(disp) ) {
3039 __ sd(R0, as_Register(base), disp);
3040 } else {
3041 __ move(T9, disp);
3042 __ addu(AT, as_Register(base), T9);
3043 __ sd(R0, AT, 0);
3044 }
3045 }
3046 %}
3048 enc_class store_L_immL_enc (memory mem, immL src) %{
3049 MacroAssembler _masm(&cbuf);
3050 int base = $mem$$base;
3051 int index = $mem$$index;
3052 int scale = $mem$$scale;
3053 int disp = $mem$$disp;
3054 long imm = $src$$constant;
3056 if( index != 0 ) {
3057 if (scale == 0) {
3058 __ daddu(AT, as_Register(base), as_Register(index));
3059 } else {
3060 __ dsll(AT, as_Register(index), scale);
3061 __ daddu(AT, as_Register(base), AT);
3062 }
3063 if( Assembler::is_simm16(disp) ) {
3064 __ set64(T9, imm);
3065 __ sd(T9, AT, disp);
3066 } else {
3067 __ move(T9, disp);
3068 __ addu(AT, AT, T9);
3069 __ set64(T9, imm);
3070 __ sd(T9, AT, 0);
3071 }
3072 } else {
3073 if( Assembler::is_simm16(disp) ) {
3074 __ move(AT, as_Register(base));
3075 __ set64(T9, imm);
3076 __ sd(T9, AT, disp);
3077 } else {
3078 __ move(T9, disp);
3079 __ addu(AT, as_Register(base), T9);
3080 __ set64(T9, imm);
3081 __ sd(T9, AT, 0);
3082 }
3083 }
3084 %}
3086 enc_class load_F_enc (regF dst, memory mem) %{
3087 MacroAssembler _masm(&cbuf);
3088 int base = $mem$$base;
3089 int index = $mem$$index;
3090 int scale = $mem$$scale;
3091 int disp = $mem$$disp;
3092 FloatRegister dst = $dst$$FloatRegister;
3094 if( index != 0 ) {
3095 if( Assembler::is_simm16(disp) ) {
3096 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3097 if (scale == 0) {
3098 __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
3099 } else {
3100 __ dsll(AT, as_Register(index), scale);
3101 __ gslwxc1(dst, as_Register(base), AT, disp);
3102 }
3103 } else {
3104 if (scale == 0) {
3105 __ daddu(AT, as_Register(base), as_Register(index));
3106 } else {
3107 __ dsll(AT, as_Register(index), scale);
3108 __ daddu(AT, as_Register(base), AT);
3109 }
3110 __ lwc1(dst, AT, disp);
3111 }
3112 } else {
3113 if (scale == 0) {
3114 __ daddu(AT, as_Register(base), as_Register(index));
3115 } else {
3116 __ dsll(AT, as_Register(index), scale);
3117 __ daddu(AT, as_Register(base), AT);
3118 }
3119 __ move(T9, disp);
3120 if( UseLoongsonISA ) {
3121 __ gslwxc1(dst, AT, T9, 0);
3122 } else {
3123 __ daddu(AT, AT, T9);
3124 __ lwc1(dst, AT, 0);
3125 }
3126 }
3127 } else {
3128 if( Assembler::is_simm16(disp) ) {
3129 __ lwc1(dst, as_Register(base), disp);
3130 } else {
3131 __ move(T9, disp);
3132 if( UseLoongsonISA ) {
3133 __ gslwxc1(dst, as_Register(base), T9, 0);
3134 } else {
3135 __ daddu(AT, as_Register(base), T9);
3136 __ lwc1(dst, AT, 0);
3137 }
3138 }
3139 }
3140 %}
3142 enc_class store_F_reg_enc (memory mem, regF src) %{
3143 MacroAssembler _masm(&cbuf);
3144 int base = $mem$$base;
3145 int index = $mem$$index;
3146 int scale = $mem$$scale;
3147 int disp = $mem$$disp;
3148 FloatRegister src = $src$$FloatRegister;
3150 if( index != 0 ) {
3151 if( Assembler::is_simm16(disp) ) {
3152 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3153 if (scale == 0) {
3154 __ gsswxc1(src, as_Register(base), as_Register(index), disp);
3155 } else {
3156 __ dsll(AT, as_Register(index), scale);
3157 __ gsswxc1(src, as_Register(base), AT, disp);
3158 }
3159 } else {
3160 if (scale == 0) {
3161 __ daddu(AT, as_Register(base), as_Register(index));
3162 } else {
3163 __ dsll(AT, as_Register(index), scale);
3164 __ daddu(AT, as_Register(base), AT);
3165 }
3166 __ swc1(src, AT, disp);
3167 }
3168 } else {
3169 if (scale == 0) {
3170 __ daddu(AT, as_Register(base), as_Register(index));
3171 } else {
3172 __ dsll(AT, as_Register(index), scale);
3173 __ daddu(AT, as_Register(base), AT);
3174 }
3175 __ move(T9, disp);
3176 if( UseLoongsonISA ) {
3177 __ gsswxc1(src, AT, T9, 0);
3178 } else {
3179 __ daddu(AT, AT, T9);
3180 __ swc1(src, AT, 0);
3181 }
3182 }
3183 } else {
3184 if( Assembler::is_simm16(disp) ) {
3185 __ swc1(src, as_Register(base), disp);
3186 } else {
3187 __ move(T9, disp);
3188 if( UseLoongsonISA ) {
3189 __ gsswxc1(src, as_Register(base), T9, 0);
3190 } else {
3191 __ daddu(AT, as_Register(base), T9);
3192 __ swc1(src, AT, 0);
3193 }
3194 }
3195 }
3196 %}
3198 enc_class load_D_enc (regD dst, memory mem) %{
3199 MacroAssembler _masm(&cbuf);
3200 int base = $mem$$base;
3201 int index = $mem$$index;
3202 int scale = $mem$$scale;
3203 int disp = $mem$$disp;
3204 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3206 if( index != 0 ) {
3207 if( Assembler::is_simm16(disp) ) {
3208 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3209 if (scale == 0) {
3210 __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
3211 } else {
3212 __ dsll(AT, as_Register(index), scale);
3213 __ gsldxc1(dst_reg, as_Register(base), AT, disp);
3214 }
3215 } else {
3216 if (scale == 0) {
3217 __ daddu(AT, as_Register(base), as_Register(index));
3218 } else {
3219 __ dsll(AT, as_Register(index), scale);
3220 __ daddu(AT, as_Register(base), AT);
3221 }
3222 __ ldc1(dst_reg, AT, disp);
3223 }
3224 } else {
3225 if (scale == 0) {
3226 __ daddu(AT, as_Register(base), as_Register(index));
3227 } else {
3228 __ dsll(AT, as_Register(index), scale);
3229 __ daddu(AT, as_Register(base), AT);
3230 }
3231 __ move(T9, disp);
3232 if( UseLoongsonISA ) {
3233 __ gsldxc1(dst_reg, AT, T9, 0);
3234 } else {
3235 __ addu(AT, AT, T9);
3236 __ ldc1(dst_reg, AT, 0);
3237 }
3238 }
3239 } else {
3240 if( Assembler::is_simm16(disp) ) {
3241 __ ldc1(dst_reg, as_Register(base), disp);
3242 } else {
3243 __ move(T9, disp);
3244 if( UseLoongsonISA ) {
3245 __ gsldxc1(dst_reg, as_Register(base), T9, 0);
3246 } else {
3247 __ addu(AT, as_Register(base), T9);
3248 __ ldc1(dst_reg, AT, 0);
3249 }
3250 }
3251 }
3252 %}
3254 enc_class store_D_reg_enc (memory mem, regD src) %{
3255 MacroAssembler _masm(&cbuf);
3256 int base = $mem$$base;
3257 int index = $mem$$index;
3258 int scale = $mem$$scale;
3259 int disp = $mem$$disp;
3260 FloatRegister src_reg = as_FloatRegister($src$$reg);
3262 if( index != 0 ) {
3263 if( Assembler::is_simm16(disp) ) {
3264 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3265 if (scale == 0) {
3266 __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
3267 } else {
3268 __ dsll(AT, as_Register(index), scale);
3269 __ gssdxc1(src_reg, as_Register(base), AT, disp);
3270 }
3271 } else {
3272 if (scale == 0) {
3273 __ daddu(AT, as_Register(base), as_Register(index));
3274 } else {
3275 __ dsll(AT, as_Register(index), scale);
3276 __ daddu(AT, as_Register(base), AT);
3277 }
3278 __ sdc1(src_reg, AT, disp);
3279 }
3280 } else {
3281 if (scale == 0) {
3282 __ daddu(AT, as_Register(base), as_Register(index));
3283 } else {
3284 __ dsll(AT, as_Register(index), scale);
3285 __ daddu(AT, as_Register(base), AT);
3286 }
3287 __ move(T9, disp);
3288 if( UseLoongsonISA ) {
3289 __ gssdxc1(src_reg, AT, T9, 0);
3290 } else {
3291 __ addu(AT, AT, T9);
3292 __ sdc1(src_reg, AT, 0);
3293 }
3294 }
3295 } else {
3296 if( Assembler::is_simm16(disp) ) {
3297 __ sdc1(src_reg, as_Register(base), disp);
3298 } else {
3299 __ move(T9, disp);
3300 if( UseLoongsonISA ) {
3301 __ gssdxc1(src_reg, as_Register(base), T9, 0);
3302 } else {
3303 __ addu(AT, as_Register(base), T9);
3304 __ sdc1(src_reg, AT, 0);
3305 }
3306 }
3307 }
3308 %}
3310 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
3311 MacroAssembler _masm(&cbuf);
3312 // This is the instruction starting address for relocation info.
3313 __ block_comment("Java_To_Runtime");
3314 cbuf.set_insts_mark();
3315 __ relocate(relocInfo::runtime_call_type);
3317 __ patchable_call((address)$meth$$method);
3318 %}
3320 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
3321 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
3322 // who we intended to call.
3323 MacroAssembler _masm(&cbuf);
3324 cbuf.set_insts_mark();
3326 if ( !_method ) {
3327 __ relocate(relocInfo::runtime_call_type);
3328 } else if(_optimized_virtual) {
3329 __ relocate(relocInfo::opt_virtual_call_type);
3330 } else {
3331 __ relocate(relocInfo::static_call_type);
3332 }
3334 __ patchable_call((address)($meth$$method));
3335 if( _method ) { // Emit stub for static call
3336 emit_java_to_interp(cbuf);
3337 }
3338 %}
3341 /*
3342 * [Ref: LIR_Assembler::ic_call() ]
3343 */
3344 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
3345 MacroAssembler _masm(&cbuf);
3346 __ block_comment("Java_Dynamic_Call");
3347 __ ic_call((address)$meth$$method);
3348 %}
3351 enc_class Set_Flags_After_Fast_Lock_Unlock(FlagsReg cr) %{
3352 Register flags = $cr$$Register;
3353 Label L;
3355 MacroAssembler _masm(&cbuf);
3357 __ addu(flags, R0, R0);
3358 __ beq(AT, R0, L);
3359 __ delayed()->nop();
3360 __ move(flags, 0xFFFFFFFF);
3361 __ bind(L);
3362 %}
3364 enc_class enc_PartialSubtypeCheck(mRegP result, mRegP sub, mRegP super, mRegI tmp) %{
3365 Register result = $result$$Register;
3366 Register sub = $sub$$Register;
3367 Register super = $super$$Register;
3368 Register length = $tmp$$Register;
3369 Register tmp = T9;
3370 Label miss;
3372 /* 2012/9/28 Jin: result may be the same as sub
3373 * 47c B40: # B21 B41 <- B20 Freq: 0.155379
3374 * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
3375 * 4bc mov S2, NULL #@loadConP
3376 * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
3377 */
3378 MacroAssembler _masm(&cbuf);
3379 Label done;
3380 __ check_klass_subtype_slow_path(sub, super, length, tmp,
3381 NULL, &miss,
3382 /*set_cond_codes:*/ true);
3383 /* 2013/7/22 Jin: Refer to X86_64's RDI */
3384 __ move(result, 0);
3385 __ b(done);
3386 __ nop();
3388 __ bind(miss);
3389 __ move(result, 1);
3390 __ bind(done);
3391 %}
3393 %}
3396 //---------MIPS FRAME--------------------------------------------------------------
3397 // Definition of frame structure and management information.
3398 //
3399 // S T A C K L A Y O U T Allocators stack-slot number
3400 // | (to get allocators register number
3401 // G Owned by | | v add SharedInfo::stack0)
3402 // r CALLER | |
3403 // o | +--------+ pad to even-align allocators stack-slot
3404 // w V | pad0 | numbers; owned by CALLER
3405 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3406 // h ^ | in | 5
3407 // | | args | 4 Holes in incoming args owned by SELF
3408 // | | old | | 3
3409 // | | SP-+--------+----> Matcher::_old_SP, even aligned
3410 // v | | ret | 3 return address
3411 // Owned by +--------+
3412 // Self | pad2 | 2 pad to align old SP
3413 // | +--------+ 1
3414 // | | locks | 0
3415 // | +--------+----> SharedInfo::stack0, even aligned
3416 // | | pad1 | 11 pad to align new SP
3417 // | +--------+
3418 // | | | 10
3419 // | | spills | 9 spills
3420 // V | | 8 (pad0 slot for callee)
3421 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3422 // ^ | out | 7
3423 // | | args | 6 Holes in outgoing args owned by CALLEE
3424 // Owned by new | |
3425 // Callee SP-+--------+----> Matcher::_new_SP, even aligned
3426 // | |
3427 //
3428 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3429 // known from SELF's arguments and the Java calling convention.
3430 // Region 6-7 is determined per call site.
3431 // Note 2: If the calling convention leaves holes in the incoming argument
3432 // area, those holes are owned by SELF. Holes in the outgoing area
3433 // are owned by the CALLEE. Holes should not be nessecary in the
3434 // incoming area, as the Java calling convention is completely under
3435 // the control of the AD file. Doubles can be sorted and packed to
3436 // avoid holes. Holes in the outgoing arguments may be nessecary for
3437 // varargs C calling conventions.
3438 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3439 // even aligned with pad0 as needed.
3440 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3441 // region 6-11 is even aligned; it may be padded out more so that
3442 // the region from SP to FP meets the minimum stack alignment.
3443 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3444 // alignment. Region 11, pad1, may be dynamically extended so that
3445 // SP meets the minimum alignment.
3448 frame %{
3450 stack_direction(TOWARDS_LOW);
3452 // These two registers define part of the calling convention
3453 // between compiled code and the interpreter.
3454 // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
3455 // for more information. by yjl 3/16/2006
3457 inline_cache_reg(T1); // Inline Cache Register
3458 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
3459 /*
3460 inline_cache_reg(T1); // Inline Cache Register or methodOop for I2C
3461 interpreter_arg_ptr_reg(A0); // Argument pointer for I2C adapters
3462 */
3464 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3465 cisc_spilling_operand_name(indOffset32);
3467 // Number of stack slots consumed by locking an object
3468 // generate Compile::sync_stack_slots
3469 #ifdef _LP64
3470 sync_stack_slots(2);
3471 #else
3472 sync_stack_slots(1);
3473 #endif
3475 frame_pointer(SP);
3477 // Interpreter stores its frame pointer in a register which is
3478 // stored to the stack by I2CAdaptors.
3479 // I2CAdaptors convert from interpreted java to compiled java.
3481 interpreter_frame_pointer(FP);
3483 // generate Matcher::stack_alignment
3484 stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
3486 // Number of stack slots between incoming argument block and the start of
3487 // a new frame. The PROLOG must add this many slots to the stack. The
3488 // EPILOG must remove this many slots. Intel needs one slot for
3489 // return address.
3490 // generate Matcher::in_preserve_stack_slots
3491 //in_preserve_stack_slots(VerifyStackAtCalls + 2); //Now VerifyStackAtCalls is defined as false ! Leave one stack slot for ra and fp
3492 in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp
3494 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3495 // for calls to C. Supports the var-args backing area for register parms.
3496 varargs_C_out_slots_killed(0);
3498 // The after-PROLOG location of the return address. Location of
3499 // return address specifies a type (REG or STACK) and a number
3500 // representing the register number (i.e. - use a register name) or
3501 // stack slot.
3502 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3503 // Otherwise, it is above the locks and verification slot and alignment word
3504 //return_addr(STACK -1+ round_to(1+VerifyStackAtCalls+Compile::current()->sync()*Compile::current()->sync_stack_slots(),WordsPerLong));
3505 return_addr(REG RA);
3507 // Body of function which returns an integer array locating
3508 // arguments either in registers or in stack slots. Passed an array
3509 // of ideal registers called "sig" and a "length" count. Stack-slot
3510 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3511 // arguments for a CALLEE. Incoming stack arguments are
3512 // automatically biased by the preserve_stack_slots field above.
3515 // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
3516 // StartNode::calling_convention call this. by yjl 3/16/2006
3517 calling_convention %{
3518 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3519 %}
3524 // Body of function which returns an integer array locating
3525 // arguments either in registers or in stack slots. Passed an array
3526 // of ideal registers called "sig" and a "length" count. Stack-slot
3527 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3528 // arguments for a CALLEE. Incoming stack arguments are
3529 // automatically biased by the preserve_stack_slots field above.
3532 // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
3533 c_calling_convention %{
3534 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3535 %}
3538 // Location of C & interpreter return values
3539 // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
3540 // SEE Matcher::match. by yjl 3/16/2006
3541 c_return_value %{
3542 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3543 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3544 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3545 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num };
3546 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3547 %}
3549 // Location of return values
3550 // register(s) contain(s) return value for Op_StartC2I and Op_Start.
3551 // SEE Matcher::match. by yjl 3/16/2006
3553 return_value %{
3554 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3555 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3556 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3557 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num};
3558 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3559 %}
3561 %}
3563 //----------ATTRIBUTES---------------------------------------------------------
3564 //----------Operand Attributes-------------------------------------------------
3565 op_attrib op_cost(0); // Required cost attribute
3567 //----------Instruction Attributes---------------------------------------------
3568 ins_attrib ins_cost(100); // Required cost attribute
3569 ins_attrib ins_size(32); // Required size attribute (in bits)
3570 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3571 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3572 // non-matching short branch variant of some
3573 // long branch?
3574 ins_attrib ins_alignment(4); // Required alignment attribute (must be a power of 2)
3575 // specifies the alignment that some part of the instruction (not
3576 // necessarily the start) requires. If > 1, a compute_padding()
3577 // function must be provided for the instruction
3579 //----------OPERANDS-----------------------------------------------------------
3580 // Operand definitions must precede instruction definitions for correct parsing
3581 // in the ADLC because operands constitute user defined types which are used in
3582 // instruction definitions.
3584 // Vectors
3585 operand vecD() %{
3586 constraint(ALLOC_IN_RC(dbl_reg));
3587 match(VecD);
3589 format %{ %}
3590 interface(REG_INTER);
3591 %}
3593 // Flags register, used as output of compare instructions
3594 operand FlagsReg() %{
3595 constraint(ALLOC_IN_RC(mips_flags));
3596 match(RegFlags);
3598 format %{ "EFLAGS" %}
3599 interface(REG_INTER);
3600 %}
3602 //----------Simple Operands----------------------------------------------------
3603 //TODO: Should we need to define some more special immediate number ?
3604 // Immediate Operands
3605 // Integer Immediate
3606 operand immI() %{
3607 match(ConI);
3608 //TODO: should not match immI8 here LEE
3609 match(immI8);
3611 op_cost(20);
3612 format %{ %}
3613 interface(CONST_INTER);
3614 %}
3616 // Long Immediate 8-bit
3617 operand immL8()
3618 %{
3619 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3620 match(ConL);
3622 op_cost(5);
3623 format %{ %}
3624 interface(CONST_INTER);
3625 %}
3627 // Constant for test vs zero
3628 operand immI0() %{
3629 predicate(n->get_int() == 0);
3630 match(ConI);
3632 op_cost(0);
3633 format %{ %}
3634 interface(CONST_INTER);
3635 %}
3637 // Constant for increment
3638 operand immI1() %{
3639 predicate(n->get_int() == 1);
3640 match(ConI);
3642 op_cost(0);
3643 format %{ %}
3644 interface(CONST_INTER);
3645 %}
3647 // Constant for decrement
3648 operand immI_M1() %{
3649 predicate(n->get_int() == -1);
3650 match(ConI);
3652 op_cost(0);
3653 format %{ %}
3654 interface(CONST_INTER);
3655 %}
3657 operand immI_MaxI() %{
3658 predicate(n->get_int() == 2147483647);
3659 match(ConI);
3661 op_cost(0);
3662 format %{ %}
3663 interface(CONST_INTER);
3664 %}
3666 // Valid scale values for addressing modes
3667 operand immI2() %{
3668 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3669 match(ConI);
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3675 operand immI8() %{
3676 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3677 match(ConI);
3679 op_cost(5);
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3684 operand immI16() %{
3685 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3686 match(ConI);
3688 op_cost(10);
3689 format %{ %}
3690 interface(CONST_INTER);
3691 %}
3693 // Constant for long shifts
3694 operand immI_32() %{
3695 predicate( n->get_int() == 32 );
3696 match(ConI);
3698 op_cost(0);
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3703 operand immI_63() %{
3704 predicate( n->get_int() == 63 );
3705 match(ConI);
3707 op_cost(0);
3708 format %{ %}
3709 interface(CONST_INTER);
3710 %}
3712 operand immI_0_31() %{
3713 predicate( n->get_int() >= 0 && n->get_int() <= 31 );
3714 match(ConI);
3716 op_cost(0);
3717 format %{ %}
3718 interface(CONST_INTER);
3719 %}
3721 // Operand for non-negtive integer mask
3722 operand immI_nonneg_mask() %{
3723 predicate( (n->get_int() >= 0) && (Assembler::is_int_mask(n->get_int()) != -1) );
3724 match(ConI);
3726 op_cost(0);
3727 format %{ %}
3728 interface(CONST_INTER);
3729 %}
3731 operand immI_32_63() %{
3732 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3733 match(ConI);
3734 op_cost(0);
3736 format %{ %}
3737 interface(CONST_INTER);
3738 %}
3740 operand immI16_sub() %{
3741 predicate((-32767 <= n->get_int()) && (n->get_int() <= 32768));
3742 match(ConI);
3744 op_cost(10);
3745 format %{ %}
3746 interface(CONST_INTER);
3747 %}
3749 operand immI_0_32767() %{
3750 predicate( n->get_int() >= 0 && n->get_int() <= 32767 );
3751 match(ConI);
3752 op_cost(0);
3754 format %{ %}
3755 interface(CONST_INTER);
3756 %}
3758 operand immI_0_65535() %{
3759 predicate( n->get_int() >= 0 && n->get_int() <= 65535 );
3760 match(ConI);
3761 op_cost(0);
3763 format %{ %}
3764 interface(CONST_INTER);
3765 %}
3767 operand immI_1() %{
3768 predicate( n->get_int() == 1 );
3769 match(ConI);
3771 op_cost(0);
3772 format %{ %}
3773 interface(CONST_INTER);
3774 %}
3776 operand immI_2() %{
3777 predicate( n->get_int() == 2 );
3778 match(ConI);
3780 op_cost(0);
3781 format %{ %}
3782 interface(CONST_INTER);
3783 %}
3785 operand immI_3() %{
3786 predicate( n->get_int() == 3 );
3787 match(ConI);
3789 op_cost(0);
3790 format %{ %}
3791 interface(CONST_INTER);
3792 %}
3794 operand immI_7() %{
3795 predicate( n->get_int() == 7 );
3796 match(ConI);
3798 format %{ %}
3799 interface(CONST_INTER);
3800 %}
3802 // Immediates for special shifts (sign extend)
3804 // Constants for increment
3805 operand immI_16() %{
3806 predicate( n->get_int() == 16 );
3807 match(ConI);
3809 format %{ %}
3810 interface(CONST_INTER);
3811 %}
3813 operand immI_24() %{
3814 predicate( n->get_int() == 24 );
3815 match(ConI);
3817 format %{ %}
3818 interface(CONST_INTER);
3819 %}
3821 // Constant for byte-wide masking
3822 operand immI_255() %{
3823 predicate( n->get_int() == 255 );
3824 match(ConI);
3826 op_cost(0);
3827 format %{ %}
3828 interface(CONST_INTER);
3829 %}
3831 operand immI_65535() %{
3832 predicate( n->get_int() == 65535 );
3833 match(ConI);
3835 op_cost(5);
3836 format %{ %}
3837 interface(CONST_INTER);
3838 %}
3840 operand immI_65536() %{
3841 predicate( n->get_int() == 65536 );
3842 match(ConI);
3844 op_cost(5);
3845 format %{ %}
3846 interface(CONST_INTER);
3847 %}
3849 operand immI_M65536() %{
3850 predicate( n->get_int() == -65536 );
3851 match(ConI);
3853 op_cost(5);
3854 format %{ %}
3855 interface(CONST_INTER);
3856 %}
3858 // Pointer Immediate
3859 operand immP() %{
3860 match(ConP);
3862 op_cost(10);
3863 format %{ %}
3864 interface(CONST_INTER);
3865 %}
3867 // NULL Pointer Immediate
3868 operand immP0() %{
3869 predicate( n->get_ptr() == 0 );
3870 match(ConP);
3871 op_cost(0);
3873 format %{ %}
3874 interface(CONST_INTER);
3875 %}
3877 // Pointer Immediate: 64-bit
3878 operand immP_set() %{
3879 match(ConP);
3881 op_cost(5);
3882 // formats are generated automatically for constants and base registers
3883 format %{ %}
3884 interface(CONST_INTER);
3885 %}
3887 // Pointer Immediate: 64-bit
3888 operand immP_load() %{
3889 predicate(n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set64(n->get_ptr()) > 3));
3890 match(ConP);
3892 op_cost(5);
3893 // formats are generated automatically for constants and base registers
3894 format %{ %}
3895 interface(CONST_INTER);
3896 %}
3898 // Pointer Immediate: 64-bit
3899 operand immP_no_oop_cheap() %{
3900 predicate(!n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set64(n->get_ptr()) <= 3));
3901 match(ConP);
3903 op_cost(5);
3904 // formats are generated automatically for constants and base registers
3905 format %{ %}
3906 interface(CONST_INTER);
3907 %}
3909 // Pointer for polling page
3910 operand immP_poll() %{
3911 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3912 match(ConP);
3913 op_cost(5);
3915 format %{ %}
3916 interface(CONST_INTER);
3917 %}
3919 // Pointer Immediate
3920 operand immN() %{
3921 match(ConN);
3923 op_cost(10);
3924 format %{ %}
3925 interface(CONST_INTER);
3926 %}
3928 operand immNKlass() %{
3929 match(ConNKlass);
3931 op_cost(10);
3932 format %{ %}
3933 interface(CONST_INTER);
3934 %}
3936 // NULL Pointer Immediate
3937 operand immN0() %{
3938 predicate(n->get_narrowcon() == 0);
3939 match(ConN);
3941 op_cost(5);
3942 format %{ %}
3943 interface(CONST_INTER);
3944 %}
3946 // Long Immediate
3947 operand immL() %{
3948 match(ConL);
3950 op_cost(20);
3951 format %{ %}
3952 interface(CONST_INTER);
3953 %}
3955 // Long Immediate zero
3956 operand immL0() %{
3957 predicate( n->get_long() == 0L );
3958 match(ConL);
3959 op_cost(0);
3961 format %{ %}
3962 interface(CONST_INTER);
3963 %}
3965 operand immL7() %{
3966 predicate( n->get_long() == 7L );
3967 match(ConL);
3968 op_cost(0);
3970 format %{ %}
3971 interface(CONST_INTER);
3972 %}
3974 operand immL_M1() %{
3975 predicate( n->get_long() == -1L );
3976 match(ConL);
3977 op_cost(0);
3979 format %{ %}
3980 interface(CONST_INTER);
3981 %}
3983 // bit 0..2 zero
3984 operand immL_M8() %{
3985 predicate( n->get_long() == -8L );
3986 match(ConL);
3987 op_cost(0);
3989 format %{ %}
3990 interface(CONST_INTER);
3991 %}
3993 // bit 2 zero
3994 operand immL_M5() %{
3995 predicate( n->get_long() == -5L );
3996 match(ConL);
3997 op_cost(0);
3999 format %{ %}
4000 interface(CONST_INTER);
4001 %}
4003 // bit 1..2 zero
4004 operand immL_M7() %{
4005 predicate( n->get_long() == -7L );
4006 match(ConL);
4007 op_cost(0);
4009 format %{ %}
4010 interface(CONST_INTER);
4011 %}
4013 // bit 0..1 zero
4014 operand immL_M4() %{
4015 predicate( n->get_long() == -4L );
4016 match(ConL);
4017 op_cost(0);
4019 format %{ %}
4020 interface(CONST_INTER);
4021 %}
4023 // bit 3..6 zero
4024 operand immL_M121() %{
4025 predicate( n->get_long() == -121L );
4026 match(ConL);
4027 op_cost(0);
4029 format %{ %}
4030 interface(CONST_INTER);
4031 %}
4033 // Long immediate from 0 to 127.
4034 // Used for a shorter form of long mul by 10.
4035 operand immL_127() %{
4036 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4037 match(ConL);
4038 op_cost(0);
4040 format %{ %}
4041 interface(CONST_INTER);
4042 %}
4044 // Operand for non-negtive long mask
4045 operand immL_nonneg_mask() %{
4046 predicate( (n->get_long() >= 0) && (Assembler::is_jlong_mask(n->get_long()) != -1) );
4047 match(ConL);
4049 op_cost(0);
4050 format %{ %}
4051 interface(CONST_INTER);
4052 %}
4054 operand immL_0_65535() %{
4055 predicate( n->get_long() >= 0 && n->get_long() <= 65535 );
4056 match(ConL);
4057 op_cost(0);
4059 format %{ %}
4060 interface(CONST_INTER);
4061 %}
4063 // Long Immediate: cheap (materialize in <= 3 instructions)
4064 operand immL_cheap() %{
4065 predicate(MacroAssembler::insts_for_set64(n->get_long()) <= 3);
4066 match(ConL);
4067 op_cost(0);
4069 format %{ %}
4070 interface(CONST_INTER);
4071 %}
4073 // Long Immediate: expensive (materialize in > 3 instructions)
4074 operand immL_expensive() %{
4075 predicate(MacroAssembler::insts_for_set64(n->get_long()) > 3);
4076 match(ConL);
4077 op_cost(0);
4079 format %{ %}
4080 interface(CONST_INTER);
4081 %}
4083 operand immL16() %{
4084 predicate((-32768 <= n->get_long()) && (n->get_long() <= 32767));
4085 match(ConL);
4087 op_cost(10);
4088 format %{ %}
4089 interface(CONST_INTER);
4090 %}
4092 operand immL16_sub() %{
4093 predicate((-32767 <= n->get_long()) && (n->get_long() <= 32768));
4094 match(ConL);
4096 op_cost(10);
4097 format %{ %}
4098 interface(CONST_INTER);
4099 %}
4101 // Long Immediate: low 32-bit mask
4102 operand immL_32bits() %{
4103 predicate(n->get_long() == 0xFFFFFFFFL);
4104 match(ConL);
4105 op_cost(20);
4107 format %{ %}
4108 interface(CONST_INTER);
4109 %}
4111 // Long Immediate 32-bit signed
4112 operand immL32()
4113 %{
4114 predicate(n->get_long() == (int) (n->get_long()));
4115 match(ConL);
4117 op_cost(15);
4118 format %{ %}
4119 interface(CONST_INTER);
4120 %}
4123 //single-precision floating-point zero
4124 operand immF0() %{
4125 predicate(jint_cast(n->getf()) == 0);
4126 match(ConF);
4128 op_cost(5);
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4133 //single-precision floating-point immediate
4134 operand immF() %{
4135 match(ConF);
4137 op_cost(20);
4138 format %{ %}
4139 interface(CONST_INTER);
4140 %}
4142 //double-precision floating-point zero
4143 operand immD0() %{
4144 predicate(jlong_cast(n->getd()) == 0);
4145 match(ConD);
4147 op_cost(5);
4148 format %{ %}
4149 interface(CONST_INTER);
4150 %}
4152 //double-precision floating-point immediate
4153 operand immD() %{
4154 match(ConD);
4156 op_cost(20);
4157 format %{ %}
4158 interface(CONST_INTER);
4159 %}
4161 // Register Operands
4162 // Integer Register
4163 operand mRegI() %{
4164 constraint(ALLOC_IN_RC(int_reg));
4165 match(RegI);
4167 format %{ %}
4168 interface(REG_INTER);
4169 %}
4171 operand no_Ax_mRegI() %{
4172 constraint(ALLOC_IN_RC(no_Ax_int_reg));
4173 match(RegI);
4174 match(mRegI);
4176 format %{ %}
4177 interface(REG_INTER);
4178 %}
4180 operand mS0RegI() %{
4181 constraint(ALLOC_IN_RC(s0_reg));
4182 match(RegI);
4183 match(mRegI);
4185 format %{ "S0" %}
4186 interface(REG_INTER);
4187 %}
4189 operand mS1RegI() %{
4190 constraint(ALLOC_IN_RC(s1_reg));
4191 match(RegI);
4192 match(mRegI);
4194 format %{ "S1" %}
4195 interface(REG_INTER);
4196 %}
4198 operand mS2RegI() %{
4199 constraint(ALLOC_IN_RC(s2_reg));
4200 match(RegI);
4201 match(mRegI);
4203 format %{ "S2" %}
4204 interface(REG_INTER);
4205 %}
4207 operand mS3RegI() %{
4208 constraint(ALLOC_IN_RC(s3_reg));
4209 match(RegI);
4210 match(mRegI);
4212 format %{ "S3" %}
4213 interface(REG_INTER);
4214 %}
4216 operand mS4RegI() %{
4217 constraint(ALLOC_IN_RC(s4_reg));
4218 match(RegI);
4219 match(mRegI);
4221 format %{ "S4" %}
4222 interface(REG_INTER);
4223 %}
4225 operand mS5RegI() %{
4226 constraint(ALLOC_IN_RC(s5_reg));
4227 match(RegI);
4228 match(mRegI);
4230 format %{ "S5" %}
4231 interface(REG_INTER);
4232 %}
4234 operand mS6RegI() %{
4235 constraint(ALLOC_IN_RC(s6_reg));
4236 match(RegI);
4237 match(mRegI);
4239 format %{ "S6" %}
4240 interface(REG_INTER);
4241 %}
4243 operand mS7RegI() %{
4244 constraint(ALLOC_IN_RC(s7_reg));
4245 match(RegI);
4246 match(mRegI);
4248 format %{ "S7" %}
4249 interface(REG_INTER);
4250 %}
4253 operand mT0RegI() %{
4254 constraint(ALLOC_IN_RC(t0_reg));
4255 match(RegI);
4256 match(mRegI);
4258 format %{ "T0" %}
4259 interface(REG_INTER);
4260 %}
4262 operand mT1RegI() %{
4263 constraint(ALLOC_IN_RC(t1_reg));
4264 match(RegI);
4265 match(mRegI);
4267 format %{ "T1" %}
4268 interface(REG_INTER);
4269 %}
4271 operand mT2RegI() %{
4272 constraint(ALLOC_IN_RC(t2_reg));
4273 match(RegI);
4274 match(mRegI);
4276 format %{ "T2" %}
4277 interface(REG_INTER);
4278 %}
4280 operand mT3RegI() %{
4281 constraint(ALLOC_IN_RC(t3_reg));
4282 match(RegI);
4283 match(mRegI);
4285 format %{ "T3" %}
4286 interface(REG_INTER);
4287 %}
4289 operand mT8RegI() %{
4290 constraint(ALLOC_IN_RC(t8_reg));
4291 match(RegI);
4292 match(mRegI);
4294 format %{ "T8" %}
4295 interface(REG_INTER);
4296 %}
4298 operand mT9RegI() %{
4299 constraint(ALLOC_IN_RC(t9_reg));
4300 match(RegI);
4301 match(mRegI);
4303 format %{ "T9" %}
4304 interface(REG_INTER);
4305 %}
4307 operand mA0RegI() %{
4308 constraint(ALLOC_IN_RC(a0_reg));
4309 match(RegI);
4310 match(mRegI);
4312 format %{ "A0" %}
4313 interface(REG_INTER);
4314 %}
4316 operand mA1RegI() %{
4317 constraint(ALLOC_IN_RC(a1_reg));
4318 match(RegI);
4319 match(mRegI);
4321 format %{ "A1" %}
4322 interface(REG_INTER);
4323 %}
4325 operand mA2RegI() %{
4326 constraint(ALLOC_IN_RC(a2_reg));
4327 match(RegI);
4328 match(mRegI);
4330 format %{ "A2" %}
4331 interface(REG_INTER);
4332 %}
4334 operand mA3RegI() %{
4335 constraint(ALLOC_IN_RC(a3_reg));
4336 match(RegI);
4337 match(mRegI);
4339 format %{ "A3" %}
4340 interface(REG_INTER);
4341 %}
4343 operand mA4RegI() %{
4344 constraint(ALLOC_IN_RC(a4_reg));
4345 match(RegI);
4346 match(mRegI);
4348 format %{ "A4" %}
4349 interface(REG_INTER);
4350 %}
4352 operand mA5RegI() %{
4353 constraint(ALLOC_IN_RC(a5_reg));
4354 match(RegI);
4355 match(mRegI);
4357 format %{ "A5" %}
4358 interface(REG_INTER);
4359 %}
4361 operand mA6RegI() %{
4362 constraint(ALLOC_IN_RC(a6_reg));
4363 match(RegI);
4364 match(mRegI);
4366 format %{ "A6" %}
4367 interface(REG_INTER);
4368 %}
4370 operand mA7RegI() %{
4371 constraint(ALLOC_IN_RC(a7_reg));
4372 match(RegI);
4373 match(mRegI);
4375 format %{ "A7" %}
4376 interface(REG_INTER);
4377 %}
4379 operand mV0RegI() %{
4380 constraint(ALLOC_IN_RC(v0_reg));
4381 match(RegI);
4382 match(mRegI);
4384 format %{ "V0" %}
4385 interface(REG_INTER);
4386 %}
4388 operand mV1RegI() %{
4389 constraint(ALLOC_IN_RC(v1_reg));
4390 match(RegI);
4391 match(mRegI);
4393 format %{ "V1" %}
4394 interface(REG_INTER);
4395 %}
4397 operand mRegN() %{
4398 constraint(ALLOC_IN_RC(int_reg));
4399 match(RegN);
4401 format %{ %}
4402 interface(REG_INTER);
4403 %}
4405 operand t0_RegN() %{
4406 constraint(ALLOC_IN_RC(t0_reg));
4407 match(RegN);
4408 match(mRegN);
4410 format %{ %}
4411 interface(REG_INTER);
4412 %}
4414 operand t1_RegN() %{
4415 constraint(ALLOC_IN_RC(t1_reg));
4416 match(RegN);
4417 match(mRegN);
4419 format %{ %}
4420 interface(REG_INTER);
4421 %}
4423 operand t2_RegN() %{
4424 constraint(ALLOC_IN_RC(t2_reg));
4425 match(RegN);
4426 match(mRegN);
4428 format %{ %}
4429 interface(REG_INTER);
4430 %}
4432 operand t3_RegN() %{
4433 constraint(ALLOC_IN_RC(t3_reg));
4434 match(RegN);
4435 match(mRegN);
4437 format %{ %}
4438 interface(REG_INTER);
4439 %}
4441 operand t8_RegN() %{
4442 constraint(ALLOC_IN_RC(t8_reg));
4443 match(RegN);
4444 match(mRegN);
4446 format %{ %}
4447 interface(REG_INTER);
4448 %}
4450 operand t9_RegN() %{
4451 constraint(ALLOC_IN_RC(t9_reg));
4452 match(RegN);
4453 match(mRegN);
4455 format %{ %}
4456 interface(REG_INTER);
4457 %}
4459 operand a0_RegN() %{
4460 constraint(ALLOC_IN_RC(a0_reg));
4461 match(RegN);
4462 match(mRegN);
4464 format %{ %}
4465 interface(REG_INTER);
4466 %}
4468 operand a1_RegN() %{
4469 constraint(ALLOC_IN_RC(a1_reg));
4470 match(RegN);
4471 match(mRegN);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4477 operand a2_RegN() %{
4478 constraint(ALLOC_IN_RC(a2_reg));
4479 match(RegN);
4480 match(mRegN);
4482 format %{ %}
4483 interface(REG_INTER);
4484 %}
4486 operand a3_RegN() %{
4487 constraint(ALLOC_IN_RC(a3_reg));
4488 match(RegN);
4489 match(mRegN);
4491 format %{ %}
4492 interface(REG_INTER);
4493 %}
4495 operand a4_RegN() %{
4496 constraint(ALLOC_IN_RC(a4_reg));
4497 match(RegN);
4498 match(mRegN);
4500 format %{ %}
4501 interface(REG_INTER);
4502 %}
4504 operand a5_RegN() %{
4505 constraint(ALLOC_IN_RC(a5_reg));
4506 match(RegN);
4507 match(mRegN);
4509 format %{ %}
4510 interface(REG_INTER);
4511 %}
4513 operand a6_RegN() %{
4514 constraint(ALLOC_IN_RC(a6_reg));
4515 match(RegN);
4516 match(mRegN);
4518 format %{ %}
4519 interface(REG_INTER);
4520 %}
4522 operand a7_RegN() %{
4523 constraint(ALLOC_IN_RC(a7_reg));
4524 match(RegN);
4525 match(mRegN);
4527 format %{ %}
4528 interface(REG_INTER);
4529 %}
4531 operand s0_RegN() %{
4532 constraint(ALLOC_IN_RC(s0_reg));
4533 match(RegN);
4534 match(mRegN);
4536 format %{ %}
4537 interface(REG_INTER);
4538 %}
4540 operand s1_RegN() %{
4541 constraint(ALLOC_IN_RC(s1_reg));
4542 match(RegN);
4543 match(mRegN);
4545 format %{ %}
4546 interface(REG_INTER);
4547 %}
4549 operand s2_RegN() %{
4550 constraint(ALLOC_IN_RC(s2_reg));
4551 match(RegN);
4552 match(mRegN);
4554 format %{ %}
4555 interface(REG_INTER);
4556 %}
4558 operand s3_RegN() %{
4559 constraint(ALLOC_IN_RC(s3_reg));
4560 match(RegN);
4561 match(mRegN);
4563 format %{ %}
4564 interface(REG_INTER);
4565 %}
4567 operand s4_RegN() %{
4568 constraint(ALLOC_IN_RC(s4_reg));
4569 match(RegN);
4570 match(mRegN);
4572 format %{ %}
4573 interface(REG_INTER);
4574 %}
4576 operand s5_RegN() %{
4577 constraint(ALLOC_IN_RC(s5_reg));
4578 match(RegN);
4579 match(mRegN);
4581 format %{ %}
4582 interface(REG_INTER);
4583 %}
4585 operand s6_RegN() %{
4586 constraint(ALLOC_IN_RC(s6_reg));
4587 match(RegN);
4588 match(mRegN);
4590 format %{ %}
4591 interface(REG_INTER);
4592 %}
4594 operand s7_RegN() %{
4595 constraint(ALLOC_IN_RC(s7_reg));
4596 match(RegN);
4597 match(mRegN);
4599 format %{ %}
4600 interface(REG_INTER);
4601 %}
4603 operand v0_RegN() %{
4604 constraint(ALLOC_IN_RC(v0_reg));
4605 match(RegN);
4606 match(mRegN);
4608 format %{ %}
4609 interface(REG_INTER);
4610 %}
4612 operand v1_RegN() %{
4613 constraint(ALLOC_IN_RC(v1_reg));
4614 match(RegN);
4615 match(mRegN);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4621 // Pointer Register
4622 operand mRegP() %{
4623 constraint(ALLOC_IN_RC(p_reg));
4624 match(RegP);
4626 format %{ %}
4627 interface(REG_INTER);
4628 %}
4630 operand no_T8_mRegP() %{
4631 constraint(ALLOC_IN_RC(no_T8_p_reg));
4632 match(RegP);
4633 match(mRegP);
4635 format %{ %}
4636 interface(REG_INTER);
4637 %}
4639 operand s0_RegP()
4640 %{
4641 constraint(ALLOC_IN_RC(s0_long_reg));
4642 match(RegP);
4643 match(mRegP);
4644 match(no_T8_mRegP);
4646 format %{ %}
4647 interface(REG_INTER);
4648 %}
4650 operand s1_RegP()
4651 %{
4652 constraint(ALLOC_IN_RC(s1_long_reg));
4653 match(RegP);
4654 match(mRegP);
4655 match(no_T8_mRegP);
4657 format %{ %}
4658 interface(REG_INTER);
4659 %}
4661 operand s2_RegP()
4662 %{
4663 constraint(ALLOC_IN_RC(s2_long_reg));
4664 match(RegP);
4665 match(mRegP);
4666 match(no_T8_mRegP);
4668 format %{ %}
4669 interface(REG_INTER);
4670 %}
4672 operand s3_RegP()
4673 %{
4674 constraint(ALLOC_IN_RC(s3_long_reg));
4675 match(RegP);
4676 match(mRegP);
4677 match(no_T8_mRegP);
4679 format %{ %}
4680 interface(REG_INTER);
4681 %}
4683 operand s4_RegP()
4684 %{
4685 constraint(ALLOC_IN_RC(s4_long_reg));
4686 match(RegP);
4687 match(mRegP);
4688 match(no_T8_mRegP);
4690 format %{ %}
4691 interface(REG_INTER);
4692 %}
4694 operand s5_RegP()
4695 %{
4696 constraint(ALLOC_IN_RC(s5_long_reg));
4697 match(RegP);
4698 match(mRegP);
4699 match(no_T8_mRegP);
4701 format %{ %}
4702 interface(REG_INTER);
4703 %}
4705 operand s6_RegP()
4706 %{
4707 constraint(ALLOC_IN_RC(s6_long_reg));
4708 match(RegP);
4709 match(mRegP);
4710 match(no_T8_mRegP);
4712 format %{ %}
4713 interface(REG_INTER);
4714 %}
4716 operand s7_RegP()
4717 %{
4718 constraint(ALLOC_IN_RC(s7_long_reg));
4719 match(RegP);
4720 match(mRegP);
4721 match(no_T8_mRegP);
4723 format %{ %}
4724 interface(REG_INTER);
4725 %}
4727 operand t0_RegP()
4728 %{
4729 constraint(ALLOC_IN_RC(t0_long_reg));
4730 match(RegP);
4731 match(mRegP);
4732 match(no_T8_mRegP);
4734 format %{ %}
4735 interface(REG_INTER);
4736 %}
4738 operand t1_RegP()
4739 %{
4740 constraint(ALLOC_IN_RC(t1_long_reg));
4741 match(RegP);
4742 match(mRegP);
4743 match(no_T8_mRegP);
4745 format %{ %}
4746 interface(REG_INTER);
4747 %}
4749 operand t2_RegP()
4750 %{
4751 constraint(ALLOC_IN_RC(t2_long_reg));
4752 match(RegP);
4753 match(mRegP);
4754 match(no_T8_mRegP);
4756 format %{ %}
4757 interface(REG_INTER);
4758 %}
4760 operand t3_RegP()
4761 %{
4762 constraint(ALLOC_IN_RC(t3_long_reg));
4763 match(RegP);
4764 match(mRegP);
4765 match(no_T8_mRegP);
4767 format %{ %}
4768 interface(REG_INTER);
4769 %}
4771 operand t8_RegP()
4772 %{
4773 constraint(ALLOC_IN_RC(t8_long_reg));
4774 match(RegP);
4775 match(mRegP);
4777 format %{ %}
4778 interface(REG_INTER);
4779 %}
4781 operand t9_RegP()
4782 %{
4783 constraint(ALLOC_IN_RC(t9_long_reg));
4784 match(RegP);
4785 match(mRegP);
4786 match(no_T8_mRegP);
4788 format %{ %}
4789 interface(REG_INTER);
4790 %}
4792 operand a0_RegP()
4793 %{
4794 constraint(ALLOC_IN_RC(a0_long_reg));
4795 match(RegP);
4796 match(mRegP);
4797 match(no_T8_mRegP);
4799 format %{ %}
4800 interface(REG_INTER);
4801 %}
4803 operand a1_RegP()
4804 %{
4805 constraint(ALLOC_IN_RC(a1_long_reg));
4806 match(RegP);
4807 match(mRegP);
4808 match(no_T8_mRegP);
4810 format %{ %}
4811 interface(REG_INTER);
4812 %}
4814 operand a2_RegP()
4815 %{
4816 constraint(ALLOC_IN_RC(a2_long_reg));
4817 match(RegP);
4818 match(mRegP);
4819 match(no_T8_mRegP);
4821 format %{ %}
4822 interface(REG_INTER);
4823 %}
4825 operand a3_RegP()
4826 %{
4827 constraint(ALLOC_IN_RC(a3_long_reg));
4828 match(RegP);
4829 match(mRegP);
4830 match(no_T8_mRegP);
4832 format %{ %}
4833 interface(REG_INTER);
4834 %}
4836 operand a4_RegP()
4837 %{
4838 constraint(ALLOC_IN_RC(a4_long_reg));
4839 match(RegP);
4840 match(mRegP);
4841 match(no_T8_mRegP);
4843 format %{ %}
4844 interface(REG_INTER);
4845 %}
4848 operand a5_RegP()
4849 %{
4850 constraint(ALLOC_IN_RC(a5_long_reg));
4851 match(RegP);
4852 match(mRegP);
4853 match(no_T8_mRegP);
4855 format %{ %}
4856 interface(REG_INTER);
4857 %}
4859 operand a6_RegP()
4860 %{
4861 constraint(ALLOC_IN_RC(a6_long_reg));
4862 match(RegP);
4863 match(mRegP);
4864 match(no_T8_mRegP);
4866 format %{ %}
4867 interface(REG_INTER);
4868 %}
4870 operand a7_RegP()
4871 %{
4872 constraint(ALLOC_IN_RC(a7_long_reg));
4873 match(RegP);
4874 match(mRegP);
4875 match(no_T8_mRegP);
4877 format %{ %}
4878 interface(REG_INTER);
4879 %}
4881 operand v0_RegP()
4882 %{
4883 constraint(ALLOC_IN_RC(v0_long_reg));
4884 match(RegP);
4885 match(mRegP);
4886 match(no_T8_mRegP);
4888 format %{ %}
4889 interface(REG_INTER);
4890 %}
4892 operand v1_RegP()
4893 %{
4894 constraint(ALLOC_IN_RC(v1_long_reg));
4895 match(RegP);
4896 match(mRegP);
4897 match(no_T8_mRegP);
4899 format %{ %}
4900 interface(REG_INTER);
4901 %}
4903 /*
4904 operand mSPRegP(mRegP reg) %{
4905 constraint(ALLOC_IN_RC(sp_reg));
4906 match(reg);
4908 format %{ "SP" %}
4909 interface(REG_INTER);
4910 %}
4912 operand mFPRegP(mRegP reg) %{
4913 constraint(ALLOC_IN_RC(fp_reg));
4914 match(reg);
4916 format %{ "FP" %}
4917 interface(REG_INTER);
4918 %}
4919 */
4921 operand mRegL() %{
4922 constraint(ALLOC_IN_RC(long_reg));
4923 match(RegL);
4925 format %{ %}
4926 interface(REG_INTER);
4927 %}
4929 operand v0RegL() %{
4930 constraint(ALLOC_IN_RC(v0_long_reg));
4931 match(RegL);
4932 match(mRegL);
4934 format %{ %}
4935 interface(REG_INTER);
4936 %}
4938 operand v1RegL() %{
4939 constraint(ALLOC_IN_RC(v1_long_reg));
4940 match(RegL);
4941 match(mRegL);
4943 format %{ %}
4944 interface(REG_INTER);
4945 %}
4947 operand a0RegL() %{
4948 constraint(ALLOC_IN_RC(a0_long_reg));
4949 match(RegL);
4950 match(mRegL);
4952 format %{ "A0" %}
4953 interface(REG_INTER);
4954 %}
4956 operand a1RegL() %{
4957 constraint(ALLOC_IN_RC(a1_long_reg));
4958 match(RegL);
4959 match(mRegL);
4961 format %{ %}
4962 interface(REG_INTER);
4963 %}
4965 operand a2RegL() %{
4966 constraint(ALLOC_IN_RC(a2_long_reg));
4967 match(RegL);
4968 match(mRegL);
4970 format %{ %}
4971 interface(REG_INTER);
4972 %}
4974 operand a3RegL() %{
4975 constraint(ALLOC_IN_RC(a3_long_reg));
4976 match(RegL);
4977 match(mRegL);
4979 format %{ %}
4980 interface(REG_INTER);
4981 %}
4983 operand t0RegL() %{
4984 constraint(ALLOC_IN_RC(t0_long_reg));
4985 match(RegL);
4986 match(mRegL);
4988 format %{ %}
4989 interface(REG_INTER);
4990 %}
4992 operand t1RegL() %{
4993 constraint(ALLOC_IN_RC(t1_long_reg));
4994 match(RegL);
4995 match(mRegL);
4997 format %{ %}
4998 interface(REG_INTER);
4999 %}
5001 operand t2RegL() %{
5002 constraint(ALLOC_IN_RC(t2_long_reg));
5003 match(RegL);
5004 match(mRegL);
5006 format %{ %}
5007 interface(REG_INTER);
5008 %}
5010 operand t3RegL() %{
5011 constraint(ALLOC_IN_RC(t3_long_reg));
5012 match(RegL);
5013 match(mRegL);
5015 format %{ %}
5016 interface(REG_INTER);
5017 %}
5019 operand t8RegL() %{
5020 constraint(ALLOC_IN_RC(t8_long_reg));
5021 match(RegL);
5022 match(mRegL);
5024 format %{ %}
5025 interface(REG_INTER);
5026 %}
5028 operand a4RegL() %{
5029 constraint(ALLOC_IN_RC(a4_long_reg));
5030 match(RegL);
5031 match(mRegL);
5033 format %{ %}
5034 interface(REG_INTER);
5035 %}
5037 operand a5RegL() %{
5038 constraint(ALLOC_IN_RC(a5_long_reg));
5039 match(RegL);
5040 match(mRegL);
5042 format %{ %}
5043 interface(REG_INTER);
5044 %}
5046 operand a6RegL() %{
5047 constraint(ALLOC_IN_RC(a6_long_reg));
5048 match(RegL);
5049 match(mRegL);
5051 format %{ %}
5052 interface(REG_INTER);
5053 %}
5055 operand a7RegL() %{
5056 constraint(ALLOC_IN_RC(a7_long_reg));
5057 match(RegL);
5058 match(mRegL);
5060 format %{ %}
5061 interface(REG_INTER);
5062 %}
5064 operand s0RegL() %{
5065 constraint(ALLOC_IN_RC(s0_long_reg));
5066 match(RegL);
5067 match(mRegL);
5069 format %{ %}
5070 interface(REG_INTER);
5071 %}
5073 operand s1RegL() %{
5074 constraint(ALLOC_IN_RC(s1_long_reg));
5075 match(RegL);
5076 match(mRegL);
5078 format %{ %}
5079 interface(REG_INTER);
5080 %}
5082 operand s2RegL() %{
5083 constraint(ALLOC_IN_RC(s2_long_reg));
5084 match(RegL);
5085 match(mRegL);
5087 format %{ %}
5088 interface(REG_INTER);
5089 %}
5091 operand s3RegL() %{
5092 constraint(ALLOC_IN_RC(s3_long_reg));
5093 match(RegL);
5094 match(mRegL);
5096 format %{ %}
5097 interface(REG_INTER);
5098 %}
5100 operand s4RegL() %{
5101 constraint(ALLOC_IN_RC(s4_long_reg));
5102 match(RegL);
5103 match(mRegL);
5105 format %{ %}
5106 interface(REG_INTER);
5107 %}
5109 operand s7RegL() %{
5110 constraint(ALLOC_IN_RC(s7_long_reg));
5111 match(RegL);
5112 match(mRegL);
5114 format %{ %}
5115 interface(REG_INTER);
5116 %}
5118 // Floating register operands
5119 operand regF() %{
5120 constraint(ALLOC_IN_RC(flt_reg));
5121 match(RegF);
5123 format %{ %}
5124 interface(REG_INTER);
5125 %}
5127 //Double Precision Floating register operands
5128 operand regD() %{
5129 constraint(ALLOC_IN_RC(dbl_reg));
5130 match(RegD);
5132 format %{ %}
5133 interface(REG_INTER);
5134 %}
5136 //----------Memory Operands----------------------------------------------------
5137 // Indirect Memory Operand
5138 operand indirect(mRegP reg) %{
5139 constraint(ALLOC_IN_RC(p_reg));
5140 match(reg);
5142 format %{ "[$reg] @ indirect" %}
5143 interface(MEMORY_INTER) %{
5144 base($reg);
5145 index(0x0); /* NO_INDEX */
5146 scale(0x0);
5147 disp(0x0);
5148 %}
5149 %}
5151 // Indirect Memory Plus Short Offset Operand
5152 operand indOffset8(mRegP reg, immL8 off)
5153 %{
5154 constraint(ALLOC_IN_RC(p_reg));
5155 match(AddP reg off);
5157 op_cost(10);
5158 format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
5159 interface(MEMORY_INTER) %{
5160 base($reg);
5161 index(0x0); /* NO_INDEX */
5162 scale(0x0);
5163 disp($off);
5164 %}
5165 %}
5167 // Indirect Memory Times Scale Plus Index Register
5168 operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale)
5169 %{
5170 constraint(ALLOC_IN_RC(p_reg));
5171 match(AddP reg (LShiftL lreg scale));
5173 op_cost(10);
5174 format %{"[$reg + $lreg << $scale] @ indIndexScale" %}
5175 interface(MEMORY_INTER) %{
5176 base($reg);
5177 index($lreg);
5178 scale($scale);
5179 disp(0x0);
5180 %}
5181 %}
5184 // [base + index + offset]
5185 operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
5186 %{
5187 constraint(ALLOC_IN_RC(p_reg));
5188 op_cost(5);
5189 match(AddP (AddP base index) off);
5191 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %}
5192 interface(MEMORY_INTER) %{
5193 base($base);
5194 index($index);
5195 scale(0x0);
5196 disp($off);
5197 %}
5198 %}
5200 // [base + index + offset]
5201 operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
5202 %{
5203 constraint(ALLOC_IN_RC(p_reg));
5204 op_cost(5);
5205 match(AddP (AddP base (ConvI2L index)) off);
5207 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %}
5208 interface(MEMORY_INTER) %{
5209 base($base);
5210 index($index);
5211 scale(0x0);
5212 disp($off);
5213 %}
5214 %}
5216 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5217 operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale)
5218 %{
5219 constraint(ALLOC_IN_RC(p_reg));
5220 match(AddP (AddP reg (LShiftL lreg scale)) off);
5222 op_cost(10);
5223 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %}
5224 interface(MEMORY_INTER) %{
5225 base($reg);
5226 index($lreg);
5227 scale($scale);
5228 disp($off);
5229 %}
5230 %}
5232 operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale)
5233 %{
5234 constraint(ALLOC_IN_RC(p_reg));
5235 match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
5237 op_cost(10);
5238 format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %}
5239 interface(MEMORY_INTER) %{
5240 base($reg);
5241 index($ireg);
5242 scale($scale);
5243 disp($off);
5244 %}
5245 %}
5247 // [base + index<<scale + offset]
5248 operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
5249 %{
5250 constraint(ALLOC_IN_RC(p_reg));
5251 //predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5252 op_cost(10);
5253 match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off);
5255 format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %}
5256 interface(MEMORY_INTER) %{
5257 base($base);
5258 index($index);
5259 scale($scale);
5260 disp($off);
5261 %}
5262 %}
5264 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5265 operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale)
5266 %{
5267 predicate(Universe::narrow_oop_shift() == 0);
5268 constraint(ALLOC_IN_RC(p_reg));
5269 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
5271 op_cost(10);
5272 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %}
5273 interface(MEMORY_INTER) %{
5274 base($reg);
5275 index($lreg);
5276 scale($scale);
5277 disp($off);
5278 %}
5279 %}
5281 // [base + index<<scale + offset] for compressd Oops
5282 operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale)
5283 %{
5284 constraint(ALLOC_IN_RC(p_reg));
5285 //predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5286 predicate(Universe::narrow_oop_shift() == 0);
5287 op_cost(10);
5288 match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off);
5290 format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %}
5291 interface(MEMORY_INTER) %{
5292 base($base);
5293 index($index);
5294 scale($scale);
5295 disp($off);
5296 %}
5297 %}
5299 //FIXME: I think it's better to limit the immI to be 16-bit at most!
5300 // Indirect Memory Plus Long Offset Operand
5301 operand indOffset32(mRegP reg, immL32 off) %{
5302 constraint(ALLOC_IN_RC(p_reg));
5303 op_cost(20);
5304 match(AddP reg off);
5306 format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
5307 interface(MEMORY_INTER) %{
5308 base($reg);
5309 index(0x0); /* NO_INDEX */
5310 scale(0x0);
5311 disp($off);
5312 %}
5313 %}
5315 // Indirect Memory Plus Index Register
5316 operand indIndex(mRegP addr, mRegL index) %{
5317 constraint(ALLOC_IN_RC(p_reg));
5318 match(AddP addr index);
5320 op_cost(20);
5321 format %{"[$addr + $index] @ indIndex" %}
5322 interface(MEMORY_INTER) %{
5323 base($addr);
5324 index($index);
5325 scale(0x0);
5326 disp(0x0);
5327 %}
5328 %}
5330 operand indirectNarrowKlass(mRegN reg)
5331 %{
5332 predicate(Universe::narrow_klass_shift() == 0);
5333 constraint(ALLOC_IN_RC(p_reg));
5334 op_cost(10);
5335 match(DecodeNKlass reg);
5337 format %{ "[$reg] @ indirectNarrowKlass" %}
5338 interface(MEMORY_INTER) %{
5339 base($reg);
5340 index(0x0);
5341 scale(0x0);
5342 disp(0x0);
5343 %}
5344 %}
5346 operand indOffset8NarrowKlass(mRegN reg, immL8 off)
5347 %{
5348 predicate(Universe::narrow_klass_shift() == 0);
5349 constraint(ALLOC_IN_RC(p_reg));
5350 op_cost(10);
5351 match(AddP (DecodeNKlass reg) off);
5353 format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
5354 interface(MEMORY_INTER) %{
5355 base($reg);
5356 index(0x0);
5357 scale(0x0);
5358 disp($off);
5359 %}
5360 %}
5362 operand indOffset32NarrowKlass(mRegN reg, immL32 off)
5363 %{
5364 predicate(Universe::narrow_klass_shift() == 0);
5365 constraint(ALLOC_IN_RC(p_reg));
5366 op_cost(10);
5367 match(AddP (DecodeNKlass reg) off);
5369 format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
5370 interface(MEMORY_INTER) %{
5371 base($reg);
5372 index(0x0);
5373 scale(0x0);
5374 disp($off);
5375 %}
5376 %}
5378 operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
5379 %{
5380 predicate(Universe::narrow_klass_shift() == 0);
5381 constraint(ALLOC_IN_RC(p_reg));
5382 match(AddP (AddP (DecodeNKlass reg) lreg) off);
5384 op_cost(10);
5385 format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
5386 interface(MEMORY_INTER) %{
5387 base($reg);
5388 index($lreg);
5389 scale(0x0);
5390 disp($off);
5391 %}
5392 %}
5394 operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
5395 %{
5396 predicate(Universe::narrow_klass_shift() == 0);
5397 constraint(ALLOC_IN_RC(p_reg));
5398 match(AddP (DecodeNKlass reg) lreg);
5400 op_cost(10);
5401 format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
5402 interface(MEMORY_INTER) %{
5403 base($reg);
5404 index($lreg);
5405 scale(0x0);
5406 disp(0x0);
5407 %}
5408 %}
5410 // Indirect Memory Operand
5411 operand indirectNarrow(mRegN reg)
5412 %{
5413 predicate(Universe::narrow_oop_shift() == 0);
5414 constraint(ALLOC_IN_RC(p_reg));
5415 op_cost(10);
5416 match(DecodeN reg);
5418 format %{ "[$reg] @ indirectNarrow" %}
5419 interface(MEMORY_INTER) %{
5420 base($reg);
5421 index(0x0);
5422 scale(0x0);
5423 disp(0x0);
5424 %}
5425 %}
5427 // Indirect Memory Plus Short Offset Operand
5428 operand indOffset8Narrow(mRegN reg, immL8 off)
5429 %{
5430 predicate(Universe::narrow_oop_shift() == 0);
5431 constraint(ALLOC_IN_RC(p_reg));
5432 op_cost(10);
5433 match(AddP (DecodeN reg) off);
5435 format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %}
5436 interface(MEMORY_INTER) %{
5437 base($reg);
5438 index(0x0);
5439 scale(0x0);
5440 disp($off);
5441 %}
5442 %}
5444 // Indirect Memory Plus Index Register Plus Offset Operand
5445 operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
5446 %{
5447 predicate(Universe::narrow_oop_shift() == 0);
5448 constraint(ALLOC_IN_RC(p_reg));
5449 match(AddP (AddP (DecodeN reg) lreg) off);
5451 op_cost(10);
5452 format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %}
5453 interface(MEMORY_INTER) %{
5454 base($reg);
5455 index($lreg);
5456 scale(0x0);
5457 disp($off);
5458 %}
5459 %}
5461 //----------Load Long Memory Operands------------------------------------------
5462 // The load-long idiom will use it's address expression again after loading
5463 // the first word of the long. If the load-long destination overlaps with
5464 // registers used in the addressing expression, the 2nd half will be loaded
5465 // from a clobbered address. Fix this by requiring that load-long use
5466 // address registers that do not overlap with the load-long target.
5468 // load-long support
5469 operand load_long_RegP() %{
5470 constraint(ALLOC_IN_RC(p_reg));
5471 match(RegP);
5472 match(mRegP);
5473 op_cost(100);
5474 format %{ %}
5475 interface(REG_INTER);
5476 %}
5478 // Indirect Memory Operand Long
5479 operand load_long_indirect(load_long_RegP reg) %{
5480 constraint(ALLOC_IN_RC(p_reg));
5481 match(reg);
5483 format %{ "[$reg]" %}
5484 interface(MEMORY_INTER) %{
5485 base($reg);
5486 index(0x0);
5487 scale(0x0);
5488 disp(0x0);
5489 %}
5490 %}
5492 // Indirect Memory Plus Long Offset Operand
5493 operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
5494 match(AddP reg off);
5496 format %{ "[$reg + $off]" %}
5497 interface(MEMORY_INTER) %{
5498 base($reg);
5499 index(0x0);
5500 scale(0x0);
5501 disp($off);
5502 %}
5503 %}
5505 //----------Conditional Branch Operands----------------------------------------
5506 // Comparison Op - This is the operation of the comparison, and is limited to
5507 // the following set of codes:
5508 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5509 //
5510 // Other attributes of the comparison, such as unsignedness, are specified
5511 // by the comparison instruction that sets a condition code flags register.
5512 // That result is represented by a flags operand whose subtype is appropriate
5513 // to the unsignedness (etc.) of the comparison.
5514 //
5515 // Later, the instruction which matches both the Comparison Op (a Bool) and
5516 // the flags (produced by the Cmp) specifies the coding of the comparison op
5517 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5519 // Comparision Code
5520 operand cmpOp() %{
5521 match(Bool);
5523 format %{ "" %}
5524 interface(COND_INTER) %{
5525 equal(0x01);
5526 not_equal(0x02);
5527 greater(0x03);
5528 greater_equal(0x04);
5529 less(0x05);
5530 less_equal(0x06);
5531 overflow(0x7);
5532 no_overflow(0x8);
5533 %}
5534 %}
5537 // Comparision Code
5538 // Comparison Code, unsigned compare. Used by FP also, with
5539 // C2 (unordered) turned into GT or LT already. The other bits
5540 // C0 and C3 are turned into Carry & Zero flags.
5541 operand cmpOpU() %{
5542 match(Bool);
5544 format %{ "" %}
5545 interface(COND_INTER) %{
5546 equal(0x01);
5547 not_equal(0x02);
5548 greater(0x03);
5549 greater_equal(0x04);
5550 less(0x05);
5551 less_equal(0x06);
5552 overflow(0x7);
5553 no_overflow(0x8);
5554 %}
5555 %}
5558 //----------Special Memory Operands--------------------------------------------
5559 // Stack Slot Operand - This operand is used for loading and storing temporary
5560 // values on the stack where a match requires a value to
5561 // flow through memory.
5562 operand stackSlotP(sRegP reg) %{
5563 constraint(ALLOC_IN_RC(stack_slots));
5564 // No match rule because this operand is only generated in matching
5565 op_cost(50);
5566 format %{ "[$reg]" %}
5567 interface(MEMORY_INTER) %{
5568 base(0x1d); // SP
5569 index(0x0); // No Index
5570 scale(0x0); // No Scale
5571 disp($reg); // Stack Offset
5572 %}
5573 %}
5575 operand stackSlotI(sRegI reg) %{
5576 constraint(ALLOC_IN_RC(stack_slots));
5577 // No match rule because this operand is only generated in matching
5578 op_cost(50);
5579 format %{ "[$reg]" %}
5580 interface(MEMORY_INTER) %{
5581 base(0x1d); // SP
5582 index(0x0); // No Index
5583 scale(0x0); // No Scale
5584 disp($reg); // Stack Offset
5585 %}
5586 %}
5588 operand stackSlotF(sRegF reg) %{
5589 constraint(ALLOC_IN_RC(stack_slots));
5590 // No match rule because this operand is only generated in matching
5591 op_cost(50);
5592 format %{ "[$reg]" %}
5593 interface(MEMORY_INTER) %{
5594 base(0x1d); // SP
5595 index(0x0); // No Index
5596 scale(0x0); // No Scale
5597 disp($reg); // Stack Offset
5598 %}
5599 %}
5601 operand stackSlotD(sRegD reg) %{
5602 constraint(ALLOC_IN_RC(stack_slots));
5603 // No match rule because this operand is only generated in matching
5604 op_cost(50);
5605 format %{ "[$reg]" %}
5606 interface(MEMORY_INTER) %{
5607 base(0x1d); // SP
5608 index(0x0); // No Index
5609 scale(0x0); // No Scale
5610 disp($reg); // Stack Offset
5611 %}
5612 %}
5614 operand stackSlotL(sRegL reg) %{
5615 constraint(ALLOC_IN_RC(stack_slots));
5616 // No match rule because this operand is only generated in matching
5617 op_cost(50);
5618 format %{ "[$reg]" %}
5619 interface(MEMORY_INTER) %{
5620 base(0x1d); // SP
5621 index(0x0); // No Index
5622 scale(0x0); // No Scale
5623 disp($reg); // Stack Offset
5624 %}
5625 %}
5628 //------------------------OPERAND CLASSES--------------------------------------
5629 //opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
5630 opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
5633 //----------PIPELINE-----------------------------------------------------------
5634 // Rules which define the behavior of the target architectures pipeline.
5636 pipeline %{
5638 //----------ATTRIBUTES---------------------------------------------------------
5639 attributes %{
5640 fixed_size_instructions; // Fixed size instructions
5641 branch_has_delay_slot; // branch have delay slot in gs2
5642 max_instructions_per_bundle = 1; // 1 instruction per bundle
5643 max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
5644 bundle_unit_size=4;
5645 instruction_unit_size = 4; // An instruction is 4 bytes long
5646 instruction_fetch_unit_size = 16; // The processor fetches one line
5647 instruction_fetch_units = 1; // of 16 bytes
5649 // List of nop instructions
5650 nops( MachNop );
5651 %}
5653 //----------RESOURCES----------------------------------------------------------
5654 // Resources are the functional units available to the machine
5656 resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
5658 //----------PIPELINE DESCRIPTION-----------------------------------------------
5659 // Pipeline Description specifies the stages in the machine's pipeline
5661 // IF: fetch
5662 // ID: decode
5663 // RD: read
5664 // CA: caculate
5665 // WB: write back
5666 // CM: commit
5668 pipe_desc(IF, ID, RD, CA, WB, CM);
5671 //----------PIPELINE CLASSES---------------------------------------------------
5672 // Pipeline Classes describe the stages in which input and output are
5673 // referenced by the hardware pipeline.
5675 //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
5676 pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
5677 single_instruction;
5678 src1 : RD(read);
5679 src2 : RD(read);
5680 dst : WB(write)+1;
5681 DECODE : ID;
5682 ALU : CA;
5683 %}
5685 //No.19 Integer mult operation : dst <-- reg1 mult reg2
5686 pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
5687 src1 : RD(read);
5688 src2 : RD(read);
5689 dst : WB(write)+5;
5690 DECODE : ID;
5691 ALU2 : CA;
5692 %}
5694 pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
5695 src1 : RD(read);
5696 src2 : RD(read);
5697 dst : WB(write)+10;
5698 DECODE : ID;
5699 ALU2 : CA;
5700 %}
5702 //No.19 Integer div operation : dst <-- reg1 div reg2
5703 pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
5704 src1 : RD(read);
5705 src2 : RD(read);
5706 dst : WB(write)+10;
5707 DECODE : ID;
5708 ALU2 : CA;
5709 %}
5711 //No.19 Integer mod operation : dst <-- reg1 mod reg2
5712 pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
5713 instruction_count(2);
5714 src1 : RD(read);
5715 src2 : RD(read);
5716 dst : WB(write)+10;
5717 DECODE : ID;
5718 ALU2 : CA;
5719 %}
5721 //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
5722 pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
5723 instruction_count(2);
5724 src1 : RD(read);
5725 src2 : RD(read);
5726 dst : WB(write);
5727 DECODE : ID;
5728 ALU : CA;
5729 %}
5731 //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
5732 pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
5733 instruction_count(2);
5734 src : RD(read);
5735 dst : WB(write);
5736 DECODE : ID;
5737 ALU : CA;
5738 %}
5740 //no.16 load Long from memory :
5741 pipe_class ialu_loadL(mRegL dst, memory mem) %{
5742 instruction_count(2);
5743 mem : RD(read);
5744 dst : WB(write)+5;
5745 DECODE : ID;
5746 MEM : RD;
5747 %}
5749 //No.17 Store Long to Memory :
5750 pipe_class ialu_storeL(mRegL src, memory mem) %{
5751 instruction_count(2);
5752 mem : RD(read);
5753 src : RD(read);
5754 DECODE : ID;
5755 MEM : RD;
5756 %}
5758 //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
5759 pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
5760 single_instruction;
5761 src : RD(read);
5762 dst : WB(write);
5763 DECODE : ID;
5764 ALU : CA;
5765 %}
5767 //No.3 Integer move operation : dst <-- reg
5768 pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
5769 src : RD(read);
5770 dst : WB(write);
5771 DECODE : ID;
5772 ALU : CA;
5773 %}
5775 //No.4 No instructions : do nothing
5776 pipe_class empty( ) %{
5777 instruction_count(0);
5778 %}
5780 //No.5 UnConditional branch :
5781 pipe_class pipe_jump( label labl ) %{
5782 multiple_bundles;
5783 DECODE : ID;
5784 BR : RD;
5785 %}
5787 //No.6 ALU Conditional branch :
5788 pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
5789 multiple_bundles;
5790 src1 : RD(read);
5791 src2 : RD(read);
5792 DECODE : ID;
5793 BR : RD;
5794 %}
5796 //no.7 load integer from memory :
5797 pipe_class ialu_loadI(mRegI dst, memory mem) %{
5798 mem : RD(read);
5799 dst : WB(write)+3;
5800 DECODE : ID;
5801 MEM : RD;
5802 %}
5804 //No.8 Store Integer to Memory :
5805 pipe_class ialu_storeI(mRegI src, memory mem) %{
5806 mem : RD(read);
5807 src : RD(read);
5808 DECODE : ID;
5809 MEM : RD;
5810 %}
5813 //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
5814 pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
5815 src1 : RD(read);
5816 src2 : RD(read);
5817 dst : WB(write);
5818 DECODE : ID;
5819 FPU : CA;
5820 %}
5822 //No.22 Floating div operation : dst <-- reg1 div reg2
5823 pipe_class fpu_div(regF dst, regF src1, regF src2) %{
5824 src1 : RD(read);
5825 src2 : RD(read);
5826 dst : WB(write);
5827 DECODE : ID;
5828 FPU2 : CA;
5829 %}
5831 pipe_class fcvt_I2D(regD dst, mRegI src) %{
5832 src : RD(read);
5833 dst : WB(write);
5834 DECODE : ID;
5835 FPU1 : CA;
5836 %}
5838 pipe_class fcvt_D2I(mRegI dst, regD src) %{
5839 src : RD(read);
5840 dst : WB(write);
5841 DECODE : ID;
5842 FPU1 : CA;
5843 %}
5845 pipe_class pipe_mfc1(mRegI dst, regD src) %{
5846 src : RD(read);
5847 dst : WB(write);
5848 DECODE : ID;
5849 MEM : RD;
5850 %}
5852 pipe_class pipe_mtc1(regD dst, mRegI src) %{
5853 src : RD(read);
5854 dst : WB(write);
5855 DECODE : ID;
5856 MEM : RD(5);
5857 %}
5859 //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
5860 pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
5861 multiple_bundles;
5862 src1 : RD(read);
5863 src2 : RD(read);
5864 dst : WB(write);
5865 DECODE : ID;
5866 FPU2 : CA;
5867 %}
5869 //No.11 Load Floating from Memory :
5870 pipe_class fpu_loadF(regF dst, memory mem) %{
5871 instruction_count(1);
5872 mem : RD(read);
5873 dst : WB(write)+3;
5874 DECODE : ID;
5875 MEM : RD;
5876 %}
5878 //No.12 Store Floating to Memory :
5879 pipe_class fpu_storeF(regF src, memory mem) %{
5880 instruction_count(1);
5881 mem : RD(read);
5882 src : RD(read);
5883 DECODE : ID;
5884 MEM : RD;
5885 %}
5887 //No.13 FPU Conditional branch :
5888 pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
5889 multiple_bundles;
5890 src1 : RD(read);
5891 src2 : RD(read);
5892 DECODE : ID;
5893 BR : RD;
5894 %}
5896 //No.14 Floating FPU reg operation : dst <-- op reg
5897 pipe_class fpu1_regF(regF dst, regF src) %{
5898 src : RD(read);
5899 dst : WB(write);
5900 DECODE : ID;
5901 FPU : CA;
5902 %}
5904 pipe_class long_memory_op() %{
5905 instruction_count(10); multiple_bundles; force_serialization;
5906 fixed_latency(30);
5907 %}
5909 pipe_class simple_call() %{
5910 instruction_count(10); multiple_bundles; force_serialization;
5911 fixed_latency(200);
5912 BR : RD;
5913 %}
5915 pipe_class call() %{
5916 instruction_count(10); multiple_bundles; force_serialization;
5917 fixed_latency(200);
5918 %}
5920 //FIXME:
5921 //No.9 Piple slow : for multi-instructions
5922 pipe_class pipe_slow( ) %{
5923 instruction_count(20);
5924 force_serialization;
5925 multiple_bundles;
5926 fixed_latency(50);
5927 %}
5929 %}
5933 //----------INSTRUCTIONS-------------------------------------------------------
5934 //
5935 // match -- States which machine-independent subtree may be replaced
5936 // by this instruction.
5937 // ins_cost -- The estimated cost of this instruction is used by instruction
5938 // selection to identify a minimum cost tree of machine
5939 // instructions that matches a tree of machine-independent
5940 // instructions.
5941 // format -- A string providing the disassembly for this instruction.
5942 // The value of an instruction's operand may be inserted
5943 // by referring to it with a '$' prefix.
5944 // opcode -- Three instruction opcodes may be provided. These are referred
5945 // to within an encode class as $primary, $secondary, and $tertiary
5946 // respectively. The primary opcode is commonly used to
5947 // indicate the type of machine instruction, while secondary
5948 // and tertiary are often used for prefix options or addressing
5949 // modes.
5950 // ins_encode -- A list of encode classes with parameters. The encode class
5951 // name must have been defined in an 'enc_class' specification
5952 // in the encode section of the architecture description.
5955 // Load Integer
5956 instruct loadI(mRegI dst, memory mem) %{
5957 match(Set dst (LoadI mem));
5959 ins_cost(125);
5960 format %{ "lw $dst, $mem #@loadI" %}
5961 ins_encode (load_I_enc(dst, mem));
5962 ins_pipe( ialu_loadI );
5963 %}
5965 instruct loadI_convI2L(mRegL dst, memory mem) %{
5966 match(Set dst (ConvI2L (LoadI mem)));
5968 ins_cost(125);
5969 format %{ "lw $dst, $mem #@loadI_convI2L" %}
5970 ins_encode (load_I_enc(dst, mem));
5971 ins_pipe( ialu_loadI );
5972 %}
5974 // Load Integer (32 bit signed) to Byte (8 bit signed)
5975 instruct loadI2B(mRegI dst, memory mem, immI_24 twentyfour) %{
5976 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5978 ins_cost(125);
5979 format %{ "lb $dst, $mem\t# int -> byte #@loadI2B" %}
5980 ins_encode(load_B_enc(dst, mem));
5981 ins_pipe(ialu_loadI);
5982 %}
5984 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5985 instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{
5986 match(Set dst (AndI (LoadI mem) mask));
5988 ins_cost(125);
5989 format %{ "lbu $dst, $mem\t# int -> ubyte #@loadI2UB" %}
5990 ins_encode(load_UB_enc(dst, mem));
5991 ins_pipe(ialu_loadI);
5992 %}
5994 // Load Integer (32 bit signed) to Short (16 bit signed)
5995 instruct loadI2S(mRegI dst, memory mem, immI_16 sixteen) %{
5996 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5998 ins_cost(125);
5999 format %{ "lh $dst, $mem\t# int -> short #@loadI2S" %}
6000 ins_encode(load_S_enc(dst, mem));
6001 ins_pipe(ialu_loadI);
6002 %}
6004 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6005 instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{
6006 match(Set dst (AndI (LoadI mem) mask));
6008 ins_cost(125);
6009 format %{ "lhu $dst, $mem\t# int -> ushort/char #@loadI2US" %}
6010 ins_encode(load_C_enc(dst, mem));
6011 ins_pipe(ialu_loadI);
6012 %}
6014 // Load Long.
6015 instruct loadL(mRegL dst, memory mem) %{
6016 // predicate(!((LoadLNode*)n)->require_atomic_access());
6017 match(Set dst (LoadL mem));
6019 ins_cost(250);
6020 format %{ "ld $dst, $mem #@loadL" %}
6021 ins_encode(load_L_enc(dst, mem));
6022 ins_pipe( ialu_loadL );
6023 %}
6025 // Load Long - UNaligned
6026 instruct loadL_unaligned(mRegL dst, memory mem) %{
6027 match(Set dst (LoadL_unaligned mem));
6029 // FIXME: Jin: Need more effective ldl/ldr
6030 ins_cost(450);
6031 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %}
6032 ins_encode(load_L_enc(dst, mem));
6033 ins_pipe( ialu_loadL );
6034 %}
6036 // Store Long
6037 instruct storeL_reg(memory mem, mRegL src) %{
6038 match(Set mem (StoreL mem src));
6040 ins_cost(200);
6041 format %{ "sd $mem, $src #@storeL_reg\n" %}
6042 ins_encode(store_L_reg_enc(mem, src));
6043 ins_pipe( ialu_storeL );
6044 %}
6046 instruct storeL_immL0(memory mem, immL0 zero) %{
6047 match(Set mem (StoreL mem zero));
6049 ins_cost(180);
6050 format %{ "sd zero, $mem #@storeL_immL0" %}
6051 ins_encode(store_L_immL0_enc(mem, zero));
6052 ins_pipe( ialu_storeL );
6053 %}
6055 instruct storeL_imm(memory mem, immL src) %{
6056 match(Set mem (StoreL mem src));
6058 ins_cost(200);
6059 format %{ "sd $src, $mem #@storeL_imm" %}
6060 ins_encode(store_L_immL_enc(mem, src));
6061 ins_pipe( ialu_storeL );
6062 %}
6064 // Load Compressed Pointer
6065 instruct loadN(mRegN dst, memory mem)
6066 %{
6067 match(Set dst (LoadN mem));
6069 ins_cost(125); // XXX
6070 format %{ "lwu $dst, $mem\t# compressed ptr @ loadN" %}
6071 ins_encode (load_N_enc(dst, mem));
6072 ins_pipe( ialu_loadI ); // XXX
6073 %}
6075 instruct loadN2P(mRegP dst, memory mem)
6076 %{
6077 match(Set dst (DecodeN (LoadN mem)));
6078 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6080 ins_cost(125); // XXX
6081 format %{ "lwu $dst, $mem\t# @ loadN2P" %}
6082 ins_encode (load_N_enc(dst, mem));
6083 ins_pipe( ialu_loadI ); // XXX
6084 %}
6086 // Load Pointer
6087 instruct loadP(mRegP dst, memory mem) %{
6088 match(Set dst (LoadP mem));
6090 ins_cost(125);
6091 format %{ "ld $dst, $mem #@loadP" %}
6092 ins_encode (load_P_enc(dst, mem));
6093 ins_pipe( ialu_loadI );
6094 %}
6096 // Load Klass Pointer
6097 instruct loadKlass(mRegP dst, memory mem) %{
6098 match(Set dst (LoadKlass mem));
6100 ins_cost(125);
6101 format %{ "MOV $dst,$mem @ loadKlass" %}
6102 ins_encode (load_P_enc(dst, mem));
6103 ins_pipe( ialu_loadI );
6104 %}
6106 // Load narrow Klass Pointer
6107 instruct loadNKlass(mRegN dst, memory mem)
6108 %{
6109 match(Set dst (LoadNKlass mem));
6111 ins_cost(125); // XXX
6112 format %{ "lwu $dst, $mem\t# compressed klass ptr @ loadNKlass" %}
6113 ins_encode (load_N_enc(dst, mem));
6114 ins_pipe( ialu_loadI ); // XXX
6115 %}
6117 instruct loadN2PKlass(mRegP dst, memory mem)
6118 %{
6119 match(Set dst (DecodeNKlass (LoadNKlass mem)));
6120 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
6122 ins_cost(125); // XXX
6123 format %{ "lwu $dst, $mem\t# compressed klass ptr @ loadN2PKlass" %}
6124 ins_encode (load_N_enc(dst, mem));
6125 ins_pipe( ialu_loadI ); // XXX
6126 %}
6128 // Load Constant
6129 instruct loadConI(mRegI dst, immI src) %{
6130 match(Set dst src);
6132 ins_cost(150);
6133 format %{ "mov $dst, $src #@loadConI" %}
6134 ins_encode %{
6135 Register dst = $dst$$Register;
6136 int value = $src$$constant;
6137 __ move(dst, value);
6138 %}
6139 ins_pipe( ialu_regI_regI );
6140 %}
6143 instruct loadConL_set64(mRegL dst, immL src) %{
6144 match(Set dst src);
6145 ins_cost(120);
6146 format %{ "li $dst, $src @ loadConL_set64" %}
6147 ins_encode %{
6148 __ set64($dst$$Register, $src$$constant);
6149 %}
6150 ins_pipe(ialu_regL_regL);
6151 %}
6153 /*
6154 // Load long value from constant table (predicated by immL_expensive).
6155 instruct loadConL_load(mRegL dst, immL_expensive src) %{
6156 match(Set dst src);
6157 ins_cost(150);
6158 format %{ "ld $dst, $constantoffset[$constanttablebase] # load long $src from table @ loadConL_ldx" %}
6159 ins_encode %{
6160 int con_offset = $constantoffset($src);
6162 if (Assembler::is_simm16(con_offset)) {
6163 __ ld($dst$$Register, $constanttablebase, con_offset);
6164 } else {
6165 __ set64(AT, con_offset);
6166 if (UseLoongsonISA) {
6167 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6168 } else {
6169 __ daddu(AT, $constanttablebase, AT);
6170 __ ld($dst$$Register, AT, 0);
6171 }
6172 }
6173 %}
6174 ins_pipe(ialu_loadI);
6175 %}
6176 */
6178 instruct loadConL16(mRegL dst, immL16 src) %{
6179 match(Set dst src);
6180 ins_cost(105);
6181 format %{ "mov $dst, $src #@loadConL16" %}
6182 ins_encode %{
6183 Register dst_reg = as_Register($dst$$reg);
6184 int value = $src$$constant;
6185 __ daddiu(dst_reg, R0, value);
6186 %}
6187 ins_pipe( ialu_regL_regL );
6188 %}
6191 instruct loadConL0(mRegL dst, immL0 src) %{
6192 match(Set dst src);
6193 ins_cost(100);
6194 format %{ "mov $dst, zero #@loadConL0" %}
6195 ins_encode %{
6196 Register dst_reg = as_Register($dst$$reg);
6197 __ daddu(dst_reg, R0, R0);
6198 %}
6199 ins_pipe( ialu_regL_regL );
6200 %}
6202 // Load Range
6203 instruct loadRange(mRegI dst, memory mem) %{
6204 match(Set dst (LoadRange mem));
6206 ins_cost(125);
6207 format %{ "MOV $dst,$mem @ loadRange" %}
6208 ins_encode(load_I_enc(dst, mem));
6209 ins_pipe( ialu_loadI );
6210 %}
6213 instruct storeP(memory mem, mRegP src ) %{
6214 match(Set mem (StoreP mem src));
6216 ins_cost(125);
6217 format %{ "sd $src, $mem #@storeP" %}
6218 ins_encode(store_P_reg_enc(mem, src));
6219 ins_pipe( ialu_storeI );
6220 %}
6222 // Store NULL Pointer, mark word, or other simple pointer constant.
6223 instruct storeImmP0(memory mem, immP0 zero) %{
6224 match(Set mem (StoreP mem zero));
6226 ins_cost(125);
6227 format %{ "mov $mem, $zero #@storeImmP0" %}
6228 ins_encode(store_P_immP0_enc(mem));
6229 ins_pipe( ialu_storeI );
6230 %}
6232 // Store Byte Immediate
6233 instruct storeImmB(memory mem, immI8 src) %{
6234 match(Set mem (StoreB mem src));
6236 ins_cost(150);
6237 format %{ "movb $mem, $src #@storeImmB" %}
6238 ins_encode(store_B_immI_enc(mem, src));
6239 ins_pipe( ialu_storeI );
6240 %}
6242 // Store Compressed Pointer
6243 instruct storeN(memory mem, mRegN src)
6244 %{
6245 match(Set mem (StoreN mem src));
6247 ins_cost(125); // XXX
6248 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %}
6249 ins_encode(store_N_reg_enc(mem, src));
6250 ins_pipe( ialu_storeI );
6251 %}
6253 instruct storeP2N(memory mem, mRegP src)
6254 %{
6255 match(Set mem (StoreN mem (EncodeP src)));
6256 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6258 ins_cost(125); // XXX
6259 format %{ "sw $mem, $src\t# @ storeP2N" %}
6260 ins_encode(store_N_reg_enc(mem, src));
6261 ins_pipe( ialu_storeI );
6262 %}
6264 instruct storeNKlass(memory mem, mRegN src)
6265 %{
6266 match(Set mem (StoreNKlass mem src));
6268 ins_cost(125); // XXX
6269 format %{ "sw $mem, $src\t# compressed klass ptr @ storeNKlass" %}
6270 ins_encode(store_N_reg_enc(mem, src));
6271 ins_pipe( ialu_storeI );
6272 %}
6274 instruct storeP2NKlass(memory mem, mRegP src)
6275 %{
6276 match(Set mem (StoreNKlass mem (EncodePKlass src)));
6277 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
6279 ins_cost(125); // XXX
6280 format %{ "sw $mem, $src\t# @ storeP2NKlass" %}
6281 ins_encode(store_N_reg_enc(mem, src));
6282 ins_pipe( ialu_storeI );
6283 %}
6285 instruct storeImmN0(memory mem, immN0 zero)
6286 %{
6287 match(Set mem (StoreN mem zero));
6289 ins_cost(125); // XXX
6290 format %{ "storeN0 zero, $mem\t# compressed ptr" %}
6291 ins_encode(storeImmN0_enc(mem, zero));
6292 ins_pipe( ialu_storeI );
6293 %}
6295 // Store Byte
6296 instruct storeB(memory mem, mRegI src) %{
6297 match(Set mem (StoreB mem src));
6299 ins_cost(125);
6300 format %{ "sb $src, $mem #@storeB" %}
6301 ins_encode(store_B_reg_enc(mem, src));
6302 ins_pipe( ialu_storeI );
6303 %}
6305 instruct storeB_convL2I(memory mem, mRegL src) %{
6306 match(Set mem (StoreB mem (ConvL2I src)));
6308 ins_cost(125);
6309 format %{ "sb $src, $mem #@storeB_convL2I" %}
6310 ins_encode(store_B_reg_enc(mem, src));
6311 ins_pipe( ialu_storeI );
6312 %}
6314 // Load Byte (8bit signed)
6315 instruct loadB(mRegI dst, memory mem) %{
6316 match(Set dst (LoadB mem));
6318 ins_cost(125);
6319 format %{ "lb $dst, $mem #@loadB" %}
6320 ins_encode(load_B_enc(dst, mem));
6321 ins_pipe( ialu_loadI );
6322 %}
6324 instruct loadB_convI2L(mRegL dst, memory mem) %{
6325 match(Set dst (ConvI2L (LoadB mem)));
6327 ins_cost(125);
6328 format %{ "lb $dst, $mem #@loadB_convI2L" %}
6329 ins_encode(load_B_enc(dst, mem));
6330 ins_pipe( ialu_loadI );
6331 %}
6333 // Load Byte (8bit UNsigned)
6334 instruct loadUB(mRegI dst, memory mem) %{
6335 match(Set dst (LoadUB mem));
6337 ins_cost(125);
6338 format %{ "lbu $dst, $mem #@loadUB" %}
6339 ins_encode(load_UB_enc(dst, mem));
6340 ins_pipe( ialu_loadI );
6341 %}
6343 instruct loadUB_convI2L(mRegL dst, memory mem) %{
6344 match(Set dst (ConvI2L (LoadUB mem)));
6346 ins_cost(125);
6347 format %{ "lbu $dst, $mem #@loadUB_convI2L" %}
6348 ins_encode(load_UB_enc(dst, mem));
6349 ins_pipe( ialu_loadI );
6350 %}
6352 // Load Short (16bit signed)
6353 instruct loadS(mRegI dst, memory mem) %{
6354 match(Set dst (LoadS mem));
6356 ins_cost(125);
6357 format %{ "lh $dst, $mem #@loadS" %}
6358 ins_encode(load_S_enc(dst, mem));
6359 ins_pipe( ialu_loadI );
6360 %}
6362 // Load Short (16 bit signed) to Byte (8 bit signed)
6363 instruct loadS2B(mRegI dst, memory mem, immI_24 twentyfour) %{
6364 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6366 ins_cost(125);
6367 format %{ "lb $dst, $mem\t# short -> byte #@loadS2B" %}
6368 ins_encode(load_B_enc(dst, mem));
6369 ins_pipe(ialu_loadI);
6370 %}
6372 instruct loadS_convI2L(mRegL dst, memory mem) %{
6373 match(Set dst (ConvI2L (LoadS mem)));
6375 ins_cost(125);
6376 format %{ "lh $dst, $mem #@loadS_convI2L" %}
6377 ins_encode(load_S_enc(dst, mem));
6378 ins_pipe( ialu_loadI );
6379 %}
6381 // Store Integer Immediate
6382 instruct storeImmI(memory mem, immI src) %{
6383 match(Set mem (StoreI mem src));
6385 ins_cost(150);
6386 format %{ "mov $mem, $src #@storeImmI" %}
6387 ins_encode(store_I_immI_enc(mem, src));
6388 ins_pipe( ialu_storeI );
6389 %}
6391 // Store Integer
6392 instruct storeI(memory mem, mRegI src) %{
6393 match(Set mem (StoreI mem src));
6395 ins_cost(125);
6396 format %{ "sw $mem, $src #@storeI" %}
6397 ins_encode(store_I_reg_enc(mem, src));
6398 ins_pipe( ialu_storeI );
6399 %}
6401 instruct storeI_convL2I(memory mem, mRegL src) %{
6402 match(Set mem (StoreI mem (ConvL2I src)));
6404 ins_cost(125);
6405 format %{ "sw $mem, $src #@storeI_convL2I" %}
6406 ins_encode(store_I_reg_enc(mem, src));
6407 ins_pipe( ialu_storeI );
6408 %}
6410 // Load Float
6411 instruct loadF(regF dst, memory mem) %{
6412 match(Set dst (LoadF mem));
6414 ins_cost(150);
6415 format %{ "loadF $dst, $mem #@loadF" %}
6416 ins_encode(load_F_enc(dst, mem));
6417 ins_pipe( ialu_loadI );
6418 %}
6420 instruct loadConP_general(mRegP dst, immP src) %{
6421 match(Set dst src);
6423 ins_cost(120);
6424 format %{ "li $dst, $src #@loadConP_general" %}
6426 ins_encode %{
6427 Register dst = $dst$$Register;
6428 long* value = (long*)$src$$constant;
6430 if($src->constant_reloc() == relocInfo::metadata_type){
6431 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6432 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6434 __ relocate(rspec);
6435 __ patchable_set48(dst, (long)value);
6436 }else if($src->constant_reloc() == relocInfo::oop_type){
6437 int oop_index = __ oop_recorder()->find_index((jobject)value);
6438 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6440 __ relocate(rspec);
6441 __ patchable_set48(dst, (long)value);
6442 } else if ($src->constant_reloc() == relocInfo::none) {
6443 __ set64(dst, (long)value);
6444 }
6445 %}
6447 ins_pipe( ialu_regI_regI );
6448 %}
6450 /*
6451 instruct loadConP_load(mRegP dst, immP_load src) %{
6452 match(Set dst src);
6454 ins_cost(100);
6455 format %{ "ld $dst, [$constanttablebase + $constantoffset] load from constant table: ptr=$src @ loadConP_load" %}
6457 ins_encode %{
6459 int con_offset = $constantoffset($src);
6461 if (Assembler::is_simm16(con_offset)) {
6462 __ ld($dst$$Register, $constanttablebase, con_offset);
6463 } else {
6464 __ set64(AT, con_offset);
6465 if (UseLoongsonISA) {
6466 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6467 } else {
6468 __ daddu(AT, $constanttablebase, AT);
6469 __ ld($dst$$Register, AT, 0);
6470 }
6471 }
6472 %}
6474 ins_pipe(ialu_loadI);
6475 %}
6476 */
6478 instruct loadConP_no_oop_cheap(mRegP dst, immP_no_oop_cheap src) %{
6479 match(Set dst src);
6481 ins_cost(80);
6482 format %{ "li $dst, $src @ loadConP_no_oop_cheap" %}
6484 ins_encode %{
6485 __ set64($dst$$Register, $src$$constant);
6486 %}
6488 ins_pipe(ialu_regI_regI);
6489 %}
6492 instruct loadConP_poll(mRegP dst, immP_poll src) %{
6493 match(Set dst src);
6495 ins_cost(50);
6496 format %{ "li $dst, $src #@loadConP_poll" %}
6498 ins_encode %{
6499 Register dst = $dst$$Register;
6500 intptr_t value = (intptr_t)$src$$constant;
6502 __ set64(dst, (jlong)value);
6503 %}
6505 ins_pipe( ialu_regI_regI );
6506 %}
6508 instruct loadConP0(mRegP dst, immP0 src)
6509 %{
6510 match(Set dst src);
6512 ins_cost(50);
6513 format %{ "mov $dst, R0\t# ptr" %}
6514 ins_encode %{
6515 Register dst_reg = $dst$$Register;
6516 __ daddu(dst_reg, R0, R0);
6517 %}
6518 ins_pipe( ialu_regI_regI );
6519 %}
6521 instruct loadConN0(mRegN dst, immN0 src) %{
6522 match(Set dst src);
6523 format %{ "move $dst, R0\t# compressed NULL ptr" %}
6524 ins_encode %{
6525 __ move($dst$$Register, R0);
6526 %}
6527 ins_pipe( ialu_regI_regI );
6528 %}
6530 instruct loadConN(mRegN dst, immN src) %{
6531 match(Set dst src);
6533 ins_cost(125);
6534 format %{ "li $dst, $src\t# compressed ptr @ loadConN" %}
6535 ins_encode %{
6536 Register dst = $dst$$Register;
6537 __ set_narrow_oop(dst, (jobject)$src$$constant);
6538 %}
6539 ins_pipe( ialu_regI_regI ); // XXX
6540 %}
6542 instruct loadConNKlass(mRegN dst, immNKlass src) %{
6543 match(Set dst src);
6545 ins_cost(125);
6546 format %{ "li $dst, $src\t# compressed klass ptr @ loadConNKlass" %}
6547 ins_encode %{
6548 Register dst = $dst$$Register;
6549 __ set_narrow_klass(dst, (Klass*)$src$$constant);
6550 %}
6551 ins_pipe( ialu_regI_regI ); // XXX
6552 %}
6554 //FIXME
6555 // Tail Call; Jump from runtime stub to Java code.
6556 // Also known as an 'interprocedural jump'.
6557 // Target of jump will eventually return to caller.
6558 // TailJump below removes the return address.
6559 instruct TailCalljmpInd(mRegP jump_target, mRegP method_oop) %{
6560 match(TailCall jump_target method_oop );
6561 ins_cost(300);
6562 format %{ "JMP $jump_target \t# @TailCalljmpInd" %}
6564 ins_encode %{
6565 Register target = $jump_target$$Register;
6566 Register oop = $method_oop$$Register;
6568 /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
6569 __ push(RA);
6571 __ move(S3, oop);
6572 __ jr(target);
6573 __ nop();
6574 %}
6576 ins_pipe( pipe_jump );
6577 %}
6579 // Create exception oop: created by stack-crawling runtime code.
6580 // Created exception is now available to this handler, and is setup
6581 // just prior to jumping to this handler. No code emitted.
6582 instruct CreateException( a0_RegP ex_oop )
6583 %{
6584 match(Set ex_oop (CreateEx));
6586 // use the following format syntax
6587 format %{ "# exception oop is in A0; no code emitted @CreateException" %}
6588 ins_encode %{
6589 /* Jin: X86 leaves this function empty */
6590 __ block_comment("CreateException is empty in X86/MIPS");
6591 %}
6592 ins_pipe( empty );
6593 // ins_pipe( pipe_jump );
6594 %}
6597 /* 2012/9/14 Jin: The mechanism of exception handling is clear now.
6599 - Common try/catch:
6600 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
6601 |- V0, V1 are created
6602 |- T9 <= SharedRuntime::exception_handler_for_return_address
6603 `- jr T9
6604 `- the caller's exception_handler
6605 `- jr OptoRuntime::exception_blob
6606 `- here
6607 - Rethrow(e.g. 'unwind'):
6608 * The callee:
6609 |- an exception is triggered during execution
6610 `- exits the callee method through RethrowException node
6611 |- The callee pushes exception_oop(T0) and exception_pc(RA)
6612 `- The callee jumps to OptoRuntime::rethrow_stub()
6613 * In OptoRuntime::rethrow_stub:
6614 |- The VM calls _rethrow_Java to determine the return address in the caller method
6615 `- exits the stub with tailjmpInd
6616 |- pops exception_oop(V0) and exception_pc(V1)
6617 `- jumps to the return address(usually an exception_handler)
6618 * The caller:
6619 `- continues processing the exception_blob with V0/V1
6620 */
6622 /*
6623 Disassembling OptoRuntime::rethrow_stub()
6625 ; locals
6626 0x2d3bf320: addiu sp, sp, 0xfffffff8
6627 0x2d3bf324: sw ra, 0x4(sp)
6628 0x2d3bf328: sw fp, 0x0(sp)
6629 0x2d3bf32c: addu fp, sp, zero
6630 0x2d3bf330: addiu sp, sp, 0xfffffff0
6631 0x2d3bf334: sw ra, 0x8(sp)
6632 0x2d3bf338: sw t0, 0x4(sp)
6633 0x2d3bf33c: sw sp, 0x0(sp)
6635 ; get_thread(S2)
6636 0x2d3bf340: addu s2, sp, zero
6637 0x2d3bf344: srl s2, s2, 12
6638 0x2d3bf348: sll s2, s2, 2
6639 0x2d3bf34c: lui at, 0x2c85
6640 0x2d3bf350: addu at, at, s2
6641 0x2d3bf354: lw s2, 0xffffcc80(at)
6643 0x2d3bf358: lw s0, 0x0(sp)
6644 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
6645 0x2d3bf360: sw s2, 0xc(sp)
6647 ; OptoRuntime::rethrow_C(oopDesc* exception, JavaThread* thread, address ret_pc)
6648 0x2d3bf364: lw a0, 0x4(sp)
6649 0x2d3bf368: lw a1, 0xc(sp)
6650 0x2d3bf36c: lw a2, 0x8(sp)
6651 ;; Java_To_Runtime
6652 0x2d3bf370: lui t9, 0x2c34
6653 0x2d3bf374: addiu t9, t9, 0xffff8a48
6654 0x2d3bf378: jalr t9
6655 0x2d3bf37c: nop
6657 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
6659 0x2d3bf384: lw s0, 0xc(sp)
6660 0x2d3bf388: sw zero, 0x118(s0)
6661 0x2d3bf38c: sw zero, 0x11c(s0)
6662 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
6663 0x2d3bf394: addu s2, s0, zero
6664 0x2d3bf398: sw zero, 0x144(s2)
6665 0x2d3bf39c: lw s0, 0x4(s2)
6666 0x2d3bf3a0: addiu s4, zero, 0x0
6667 0x2d3bf3a4: bne s0, s4, 0x2d3bf3d4
6668 0x2d3bf3a8: nop
6669 0x2d3bf3ac: addiu sp, sp, 0x10
6670 0x2d3bf3b0: addiu sp, sp, 0x8
6671 0x2d3bf3b4: lw ra, 0xfffffffc(sp)
6672 0x2d3bf3b8: lw fp, 0xfffffff8(sp)
6673 0x2d3bf3bc: lui at, 0x2b48
6674 0x2d3bf3c0: lw at, 0x100(at)
6676 ; tailjmpInd: Restores exception_oop & exception_pc
6677 0x2d3bf3c4: addu v1, ra, zero
6678 0x2d3bf3c8: addu v0, s1, zero
6679 0x2d3bf3cc: jr s3
6680 0x2d3bf3d0: nop
6681 ; Exception:
6682 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
6683 0x2d3bf3d8: addiu s1, s1, 0x40
6684 0x2d3bf3dc: addiu s2, zero, 0x0
6685 0x2d3bf3e0: addiu sp, sp, 0x10
6686 0x2d3bf3e4: addiu sp, sp, 0x8
6687 0x2d3bf3e8: lw ra, 0xfffffffc(sp)
6688 0x2d3bf3ec: lw fp, 0xfffffff8(sp)
6689 0x2d3bf3f0: lui at, 0x2b48
6690 0x2d3bf3f4: lw at, 0x100(at)
6691 ; TailCalljmpInd
6692 __ push(RA); ; to be used in generate_forward_exception()
6693 0x2d3bf3f8: addu t7, s2, zero
6694 0x2d3bf3fc: jr s1
6695 0x2d3bf400: nop
6696 */
6697 // Rethrow exception:
6698 // The exception oop will come in the first argument position.
6699 // Then JUMP (not call) to the rethrow stub code.
6700 instruct RethrowException()
6701 %{
6702 match(Rethrow);
6704 // use the following format syntax
6705 format %{ "JMP rethrow_stub #@RethrowException" %}
6706 ins_encode %{
6707 __ block_comment("@ RethrowException");
6709 cbuf.set_insts_mark();
6710 cbuf.relocate(cbuf.insts_mark(), runtime_call_Relocation::spec());
6712 // call OptoRuntime::rethrow_stub to get the exception handler in parent method
6713 __ patchable_jump((address)OptoRuntime::rethrow_stub());
6714 %}
6715 ins_pipe( pipe_jump );
6716 %}
6718 instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{
6719 match(If cmp (CmpP op1 zero));
6720 effect(USE labl);
6722 ins_cost(180);
6723 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero" %}
6725 ins_encode %{
6726 Register op1 = $op1$$Register;
6727 Register op2 = R0;
6728 Label &L = *($labl$$label);
6729 int flag = $cmp$$cmpcode;
6731 switch(flag)
6732 {
6733 case 0x01: //equal
6734 if (&L)
6735 __ beq(op1, op2, L);
6736 else
6737 __ beq(op1, op2, (int)0);
6738 break;
6739 case 0x02: //not_equal
6740 if (&L)
6741 __ bne(op1, op2, L);
6742 else
6743 __ bne(op1, op2, (int)0);
6744 break;
6745 default:
6746 Unimplemented();
6747 }
6748 __ nop();
6749 %}
6751 ins_pc_relative(1);
6752 ins_pipe( pipe_alu_branch );
6753 %}
6755 instruct branchConN2P_zero(cmpOpU cmp, mRegN op1, immP0 zero, label labl) %{
6756 match(If cmp (CmpP (DecodeN op1) zero));
6757 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6758 effect(USE labl);
6760 ins_cost(180);
6761 format %{ "b$cmp $op1, R0, $labl #@branchConN2P_zero" %}
6763 ins_encode %{
6764 Register op1 = $op1$$Register;
6765 Register op2 = R0;
6766 Label &L = *($labl$$label);
6767 int flag = $cmp$$cmpcode;
6769 switch(flag)
6770 {
6771 case 0x01: //equal
6772 if (&L)
6773 __ beq(op1, op2, L);
6774 else
6775 __ beq(op1, op2, (int)0);
6776 break;
6777 case 0x02: //not_equal
6778 if (&L)
6779 __ bne(op1, op2, L);
6780 else
6781 __ bne(op1, op2, (int)0);
6782 break;
6783 default:
6784 Unimplemented();
6785 }
6786 __ nop();
6787 %}
6789 ins_pc_relative(1);
6790 ins_pipe( pipe_alu_branch );
6791 %}
6794 instruct branchConP(cmpOpU cmp, mRegP op1, mRegP op2, label labl) %{
6795 match(If cmp (CmpP op1 op2));
6796 // predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6797 effect(USE labl);
6799 ins_cost(200);
6800 format %{ "b$cmp $op1, $op2, $labl #@branchConP" %}
6802 ins_encode %{
6803 Register op1 = $op1$$Register;
6804 Register op2 = $op2$$Register;
6805 Label &L = *($labl$$label);
6806 int flag = $cmp$$cmpcode;
6808 switch(flag)
6809 {
6810 case 0x01: //equal
6811 if (&L)
6812 __ beq(op1, op2, L);
6813 else
6814 __ beq(op1, op2, (int)0);
6815 break;
6816 case 0x02: //not_equal
6817 if (&L)
6818 __ bne(op1, op2, L);
6819 else
6820 __ bne(op1, op2, (int)0);
6821 break;
6822 case 0x03: //above
6823 __ sltu(AT, op2, op1);
6824 if(&L)
6825 __ bne(R0, AT, L);
6826 else
6827 __ bne(R0, AT, (int)0);
6828 break;
6829 case 0x04: //above_equal
6830 __ sltu(AT, op1, op2);
6831 if(&L)
6832 __ beq(AT, R0, L);
6833 else
6834 __ beq(AT, R0, (int)0);
6835 break;
6836 case 0x05: //below
6837 __ sltu(AT, op1, op2);
6838 if(&L)
6839 __ bne(R0, AT, L);
6840 else
6841 __ bne(R0, AT, (int)0);
6842 break;
6843 case 0x06: //below_equal
6844 __ sltu(AT, op2, op1);
6845 if(&L)
6846 __ beq(AT, R0, L);
6847 else
6848 __ beq(AT, R0, (int)0);
6849 break;
6850 default:
6851 Unimplemented();
6852 }
6853 __ nop();
6854 %}
6856 ins_pc_relative(1);
6857 ins_pipe( pipe_alu_branch );
6858 %}
6860 instruct cmpN_null_branch(cmpOp cmp, mRegN op1, immN0 null, label labl) %{
6861 match(If cmp (CmpN op1 null));
6862 effect(USE labl);
6864 ins_cost(180);
6865 format %{ "CMP $op1,0\t! compressed ptr\n\t"
6866 "BP$cmp $labl @ cmpN_null_branch" %}
6867 ins_encode %{
6868 Register op1 = $op1$$Register;
6869 Register op2 = R0;
6870 Label &L = *($labl$$label);
6871 int flag = $cmp$$cmpcode;
6873 switch(flag)
6874 {
6875 case 0x01: //equal
6876 if (&L)
6877 __ beq(op1, op2, L);
6878 else
6879 __ beq(op1, op2, (int)0);
6880 break;
6881 case 0x02: //not_equal
6882 if (&L)
6883 __ bne(op1, op2, L);
6884 else
6885 __ bne(op1, op2, (int)0);
6886 break;
6887 default:
6888 Unimplemented();
6889 }
6890 __ nop();
6891 %}
6892 //TODO: pipe_branchP or create pipe_branchN LEE
6893 ins_pc_relative(1);
6894 ins_pipe( pipe_alu_branch );
6895 %}
6897 instruct cmpN_reg_branch(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{
6898 match(If cmp (CmpN op1 op2));
6899 effect(USE labl);
6901 ins_cost(180);
6902 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
6903 "BP$cmp $labl" %}
6904 ins_encode %{
6905 Register op1_reg = $op1$$Register;
6906 Register op2_reg = $op2$$Register;
6907 Label &L = *($labl$$label);
6908 int flag = $cmp$$cmpcode;
6910 switch(flag)
6911 {
6912 case 0x01: //equal
6913 if (&L)
6914 __ beq(op1_reg, op2_reg, L);
6915 else
6916 __ beq(op1_reg, op2_reg, (int)0);
6917 break;
6918 case 0x02: //not_equal
6919 if (&L)
6920 __ bne(op1_reg, op2_reg, L);
6921 else
6922 __ bne(op1_reg, op2_reg, (int)0);
6923 break;
6924 case 0x03: //above
6925 __ sltu(AT, op2_reg, op1_reg);
6926 if(&L)
6927 __ bne(R0, AT, L);
6928 else
6929 __ bne(R0, AT, (int)0);
6930 break;
6931 case 0x04: //above_equal
6932 __ sltu(AT, op1_reg, op2_reg);
6933 if(&L)
6934 __ beq(AT, R0, L);
6935 else
6936 __ beq(AT, R0, (int)0);
6937 break;
6938 case 0x05: //below
6939 __ sltu(AT, op1_reg, op2_reg);
6940 if(&L)
6941 __ bne(R0, AT, L);
6942 else
6943 __ bne(R0, AT, (int)0);
6944 break;
6945 case 0x06: //below_equal
6946 __ sltu(AT, op2_reg, op1_reg);
6947 if(&L)
6948 __ beq(AT, R0, L);
6949 else
6950 __ beq(AT, R0, (int)0);
6951 break;
6952 default:
6953 Unimplemented();
6954 }
6955 __ nop();
6956 %}
6957 ins_pc_relative(1);
6958 ins_pipe( pipe_alu_branch );
6959 %}
6961 instruct branchConIU_reg_reg(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{
6962 match( If cmp (CmpU src1 src2) );
6963 effect(USE labl);
6964 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg" %}
6966 ins_encode %{
6967 Register op1 = $src1$$Register;
6968 Register op2 = $src2$$Register;
6969 Label &L = *($labl$$label);
6970 int flag = $cmp$$cmpcode;
6972 switch(flag)
6973 {
6974 case 0x01: //equal
6975 if (&L)
6976 __ beq(op1, op2, L);
6977 else
6978 __ beq(op1, op2, (int)0);
6979 break;
6980 case 0x02: //not_equal
6981 if (&L)
6982 __ bne(op1, op2, L);
6983 else
6984 __ bne(op1, op2, (int)0);
6985 break;
6986 case 0x03: //above
6987 __ sltu(AT, op2, op1);
6988 if(&L)
6989 __ bne(AT, R0, L);
6990 else
6991 __ bne(AT, R0, (int)0);
6992 break;
6993 case 0x04: //above_equal
6994 __ sltu(AT, op1, op2);
6995 if(&L)
6996 __ beq(AT, R0, L);
6997 else
6998 __ beq(AT, R0, (int)0);
6999 break;
7000 case 0x05: //below
7001 __ sltu(AT, op1, op2);
7002 if(&L)
7003 __ bne(AT, R0, L);
7004 else
7005 __ bne(AT, R0, (int)0);
7006 break;
7007 case 0x06: //below_equal
7008 __ sltu(AT, op2, op1);
7009 if(&L)
7010 __ beq(AT, R0, L);
7011 else
7012 __ beq(AT, R0, (int)0);
7013 break;
7014 default:
7015 Unimplemented();
7016 }
7017 __ nop();
7018 %}
7020 ins_pc_relative(1);
7021 ins_pipe( pipe_alu_branch );
7022 %}
7025 instruct branchConIU_reg_imm(cmpOpU cmp, mRegI src1, immI src2, label labl) %{
7026 match( If cmp (CmpU src1 src2) );
7027 effect(USE labl);
7028 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm" %}
7030 ins_encode %{
7031 Register op1 = $src1$$Register;
7032 int val = $src2$$constant;
7033 Label &L = *($labl$$label);
7034 int flag = $cmp$$cmpcode;
7036 __ move(AT, val);
7037 switch(flag)
7038 {
7039 case 0x01: //equal
7040 if (&L)
7041 __ beq(op1, AT, L);
7042 else
7043 __ beq(op1, AT, (int)0);
7044 break;
7045 case 0x02: //not_equal
7046 if (&L)
7047 __ bne(op1, AT, L);
7048 else
7049 __ bne(op1, AT, (int)0);
7050 break;
7051 case 0x03: //above
7052 __ sltu(AT, AT, op1);
7053 if(&L)
7054 __ bne(R0, AT, L);
7055 else
7056 __ bne(R0, AT, (int)0);
7057 break;
7058 case 0x04: //above_equal
7059 __ sltu(AT, op1, AT);
7060 if(&L)
7061 __ beq(AT, R0, L);
7062 else
7063 __ beq(AT, R0, (int)0);
7064 break;
7065 case 0x05: //below
7066 __ sltu(AT, op1, AT);
7067 if(&L)
7068 __ bne(R0, AT, L);
7069 else
7070 __ bne(R0, AT, (int)0);
7071 break;
7072 case 0x06: //below_equal
7073 __ sltu(AT, AT, op1);
7074 if(&L)
7075 __ beq(AT, R0, L);
7076 else
7077 __ beq(AT, R0, (int)0);
7078 break;
7079 default:
7080 Unimplemented();
7081 }
7082 __ nop();
7083 %}
7085 ins_pc_relative(1);
7086 ins_pipe( pipe_alu_branch );
7087 %}
7089 instruct branchConI_reg_reg(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{
7090 match( If cmp (CmpI src1 src2) );
7091 effect(USE labl);
7092 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg" %}
7094 ins_encode %{
7095 Register op1 = $src1$$Register;
7096 Register op2 = $src2$$Register;
7097 Label &L = *($labl$$label);
7098 int flag = $cmp$$cmpcode;
7100 switch(flag)
7101 {
7102 case 0x01: //equal
7103 if (&L)
7104 __ beq(op1, op2, L);
7105 else
7106 __ beq(op1, op2, (int)0);
7107 break;
7108 case 0x02: //not_equal
7109 if (&L)
7110 __ bne(op1, op2, L);
7111 else
7112 __ bne(op1, op2, (int)0);
7113 break;
7114 case 0x03: //above
7115 __ slt(AT, op2, op1);
7116 if(&L)
7117 __ bne(R0, AT, L);
7118 else
7119 __ bne(R0, AT, (int)0);
7120 break;
7121 case 0x04: //above_equal
7122 __ slt(AT, op1, op2);
7123 if(&L)
7124 __ beq(AT, R0, L);
7125 else
7126 __ beq(AT, R0, (int)0);
7127 break;
7128 case 0x05: //below
7129 __ slt(AT, op1, op2);
7130 if(&L)
7131 __ bne(R0, AT, L);
7132 else
7133 __ bne(R0, AT, (int)0);
7134 break;
7135 case 0x06: //below_equal
7136 __ slt(AT, op2, op1);
7137 if(&L)
7138 __ beq(AT, R0, L);
7139 else
7140 __ beq(AT, R0, (int)0);
7141 break;
7142 default:
7143 Unimplemented();
7144 }
7145 __ nop();
7146 %}
7148 ins_pc_relative(1);
7149 ins_pipe( pipe_alu_branch );
7150 %}
7152 instruct branchConI_reg_imm0(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{
7153 match( If cmp (CmpI src1 src2) );
7154 effect(USE labl);
7155 ins_cost(170);
7156 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0" %}
7158 ins_encode %{
7159 Register op1 = $src1$$Register;
7160 // int val = $src2$$constant;
7161 Label &L = *($labl$$label);
7162 int flag = $cmp$$cmpcode;
7164 //__ move(AT, val);
7165 switch(flag)
7166 {
7167 case 0x01: //equal
7168 if (&L)
7169 __ beq(op1, R0, L);
7170 else
7171 __ beq(op1, R0, (int)0);
7172 break;
7173 case 0x02: //not_equal
7174 if (&L)
7175 __ bne(op1, R0, L);
7176 else
7177 __ bne(op1, R0, (int)0);
7178 break;
7179 case 0x03: //greater
7180 if(&L)
7181 __ bgtz(op1, L);
7182 else
7183 __ bgtz(op1, (int)0);
7184 break;
7185 case 0x04: //greater_equal
7186 if(&L)
7187 __ bgez(op1, L);
7188 else
7189 __ bgez(op1, (int)0);
7190 break;
7191 case 0x05: //less
7192 if(&L)
7193 __ bltz(op1, L);
7194 else
7195 __ bltz(op1, (int)0);
7196 break;
7197 case 0x06: //less_equal
7198 if(&L)
7199 __ blez(op1, L);
7200 else
7201 __ blez(op1, (int)0);
7202 break;
7203 default:
7204 Unimplemented();
7205 }
7206 __ nop();
7207 %}
7209 ins_pc_relative(1);
7210 ins_pipe( pipe_alu_branch );
7211 %}
7214 instruct branchConI_reg_imm(cmpOp cmp, mRegI src1, immI src2, label labl) %{
7215 match( If cmp (CmpI src1 src2) );
7216 effect(USE labl);
7217 ins_cost(200);
7218 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm" %}
7220 ins_encode %{
7221 Register op1 = $src1$$Register;
7222 int val = $src2$$constant;
7223 Label &L = *($labl$$label);
7224 int flag = $cmp$$cmpcode;
7226 __ move(AT, val);
7227 switch(flag)
7228 {
7229 case 0x01: //equal
7230 if (&L)
7231 __ beq(op1, AT, L);
7232 else
7233 __ beq(op1, AT, (int)0);
7234 break;
7235 case 0x02: //not_equal
7236 if (&L)
7237 __ bne(op1, AT, L);
7238 else
7239 __ bne(op1, AT, (int)0);
7240 break;
7241 case 0x03: //greater
7242 __ slt(AT, AT, op1);
7243 if(&L)
7244 __ bne(R0, AT, L);
7245 else
7246 __ bne(R0, AT, (int)0);
7247 break;
7248 case 0x04: //greater_equal
7249 __ slt(AT, op1, AT);
7250 if(&L)
7251 __ beq(AT, R0, L);
7252 else
7253 __ beq(AT, R0, (int)0);
7254 break;
7255 case 0x05: //less
7256 __ slt(AT, op1, AT);
7257 if(&L)
7258 __ bne(R0, AT, L);
7259 else
7260 __ bne(R0, AT, (int)0);
7261 break;
7262 case 0x06: //less_equal
7263 __ slt(AT, AT, op1);
7264 if(&L)
7265 __ beq(AT, R0, L);
7266 else
7267 __ beq(AT, R0, (int)0);
7268 break;
7269 default:
7270 Unimplemented();
7271 }
7272 __ nop();
7273 %}
7275 ins_pc_relative(1);
7276 ins_pipe( pipe_alu_branch );
7277 %}
7279 instruct branchConIU_reg_imm0(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{
7280 match( If cmp (CmpU src1 zero) );
7281 effect(USE labl);
7282 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0" %}
7284 ins_encode %{
7285 Register op1 = $src1$$Register;
7286 Label &L = *($labl$$label);
7287 int flag = $cmp$$cmpcode;
7289 switch(flag)
7290 {
7291 case 0x01: //equal
7292 if (&L)
7293 __ beq(op1, R0, L);
7294 else
7295 __ beq(op1, R0, (int)0);
7296 break;
7297 case 0x02: //not_equal
7298 if (&L)
7299 __ bne(op1, R0, L);
7300 else
7301 __ bne(op1, R0, (int)0);
7302 break;
7303 case 0x03: //above
7304 if(&L)
7305 __ bne(R0, op1, L);
7306 else
7307 __ bne(R0, op1, (int)0);
7308 break;
7309 case 0x04: //above_equal
7310 if(&L)
7311 __ beq(R0, R0, L);
7312 else
7313 __ beq(R0, R0, (int)0);
7314 break;
7315 case 0x05: //below
7316 return;
7317 break;
7318 case 0x06: //below_equal
7319 if(&L)
7320 __ beq(op1, R0, L);
7321 else
7322 __ beq(op1, R0, (int)0);
7323 break;
7324 default:
7325 Unimplemented();
7326 }
7327 __ nop();
7328 %}
7330 ins_pc_relative(1);
7331 ins_pipe( pipe_alu_branch );
7332 %}
7335 instruct branchConIU_reg_immI16(cmpOpU cmp, mRegI src1, immI16 src2, label labl) %{
7336 match( If cmp (CmpU src1 src2) );
7337 effect(USE labl);
7338 ins_cost(180);
7339 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16" %}
7341 ins_encode %{
7342 Register op1 = $src1$$Register;
7343 int val = $src2$$constant;
7344 Label &L = *($labl$$label);
7345 int flag = $cmp$$cmpcode;
7347 switch(flag)
7348 {
7349 case 0x01: //equal
7350 __ move(AT, val);
7351 if (&L)
7352 __ beq(op1, AT, L);
7353 else
7354 __ beq(op1, AT, (int)0);
7355 break;
7356 case 0x02: //not_equal
7357 __ move(AT, val);
7358 if (&L)
7359 __ bne(op1, AT, L);
7360 else
7361 __ bne(op1, AT, (int)0);
7362 break;
7363 case 0x03: //above
7364 __ move(AT, val);
7365 __ sltu(AT, AT, op1);
7366 if(&L)
7367 __ bne(R0, AT, L);
7368 else
7369 __ bne(R0, AT, (int)0);
7370 break;
7371 case 0x04: //above_equal
7372 __ sltiu(AT, op1, val);
7373 if(&L)
7374 __ beq(AT, R0, L);
7375 else
7376 __ beq(AT, R0, (int)0);
7377 break;
7378 case 0x05: //below
7379 __ sltiu(AT, op1, val);
7380 if(&L)
7381 __ bne(R0, AT, L);
7382 else
7383 __ bne(R0, AT, (int)0);
7384 break;
7385 case 0x06: //below_equal
7386 __ move(AT, val);
7387 __ sltu(AT, AT, op1);
7388 if(&L)
7389 __ beq(AT, R0, L);
7390 else
7391 __ beq(AT, R0, (int)0);
7392 break;
7393 default:
7394 Unimplemented();
7395 }
7396 __ nop();
7397 %}
7399 ins_pc_relative(1);
7400 ins_pipe( pipe_alu_branch );
7401 %}
7404 instruct branchConL_regL_regL(cmpOp cmp, mRegL src1, mRegL src2, label labl) %{
7405 match( If cmp (CmpL src1 src2) );
7406 effect(USE labl);
7407 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_regL" %}
7408 ins_cost(250);
7410 ins_encode %{
7411 Register opr1_reg = as_Register($src1$$reg);
7412 Register opr2_reg = as_Register($src2$$reg);
7414 Label &target = *($labl$$label);
7415 int flag = $cmp$$cmpcode;
7417 switch(flag)
7418 {
7419 case 0x01: //equal
7420 if (&target)
7421 __ beq(opr1_reg, opr2_reg, target);
7422 else
7423 __ beq(opr1_reg, opr2_reg, (int)0);
7424 __ delayed()->nop();
7425 break;
7427 case 0x02: //not_equal
7428 if(&target)
7429 __ bne(opr1_reg, opr2_reg, target);
7430 else
7431 __ bne(opr1_reg, opr2_reg, (int)0);
7432 __ delayed()->nop();
7433 break;
7435 case 0x03: //greater
7436 __ slt(AT, opr2_reg, opr1_reg);
7437 if(&target)
7438 __ bne(AT, R0, target);
7439 else
7440 __ bne(AT, R0, (int)0);
7441 __ delayed()->nop();
7442 break;
7444 case 0x04: //greater_equal
7445 __ slt(AT, opr1_reg, opr2_reg);
7446 if(&target)
7447 __ beq(AT, R0, target);
7448 else
7449 __ beq(AT, R0, (int)0);
7450 __ delayed()->nop();
7452 break;
7454 case 0x05: //less
7455 __ slt(AT, opr1_reg, opr2_reg);
7456 if(&target)
7457 __ bne(AT, R0, target);
7458 else
7459 __ bne(AT, R0, (int)0);
7460 __ delayed()->nop();
7462 break;
7464 case 0x06: //less_equal
7465 __ slt(AT, opr2_reg, opr1_reg);
7467 if(&target)
7468 __ beq(AT, R0, target);
7469 else
7470 __ beq(AT, R0, (int)0);
7471 __ delayed()->nop();
7473 break;
7475 default:
7476 Unimplemented();
7477 }
7478 %}
7481 ins_pc_relative(1);
7482 ins_pipe( pipe_alu_branch );
7483 %}
7486 instruct branchConL_regL_immL0(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{
7487 match( If cmp (CmpL src1 zero) );
7488 effect(USE labl);
7489 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0" %}
7490 ins_cost(150);
7492 ins_encode %{
7493 Register opr1_reg = as_Register($src1$$reg);
7494 Label &target = *($labl$$label);
7495 int flag = $cmp$$cmpcode;
7497 switch(flag)
7498 {
7499 case 0x01: //equal
7500 if (&target)
7501 __ beq(opr1_reg, R0, target);
7502 else
7503 __ beq(opr1_reg, R0, int(0));
7504 break;
7506 case 0x02: //not_equal
7507 if(&target)
7508 __ bne(opr1_reg, R0, target);
7509 else
7510 __ bne(opr1_reg, R0, (int)0);
7511 break;
7513 case 0x03: //greater
7514 if(&target)
7515 __ bgtz(opr1_reg, target);
7516 else
7517 __ bgtz(opr1_reg, (int)0);
7518 break;
7520 case 0x04: //greater_equal
7521 if(&target)
7522 __ bgez(opr1_reg, target);
7523 else
7524 __ bgez(opr1_reg, (int)0);
7525 break;
7527 case 0x05: //less
7528 __ slt(AT, opr1_reg, R0);
7529 if(&target)
7530 __ bne(AT, R0, target);
7531 else
7532 __ bne(AT, R0, (int)0);
7533 break;
7535 case 0x06: //less_equal
7536 if (&target)
7537 __ blez(opr1_reg, target);
7538 else
7539 __ blez(opr1_reg, int(0));
7540 break;
7542 default:
7543 Unimplemented();
7544 }
7545 __ delayed()->nop();
7546 %}
7549 ins_pc_relative(1);
7550 ins_pipe( pipe_alu_branch );
7551 %}
7553 instruct branchConL_regL_immL(cmpOp cmp, mRegL src1, immL src2, label labl) %{
7554 match( If cmp (CmpL src1 src2) );
7555 effect(USE labl);
7556 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_immL" %}
7557 ins_cost(180);
7559 ins_encode %{
7560 Register opr1_reg = as_Register($src1$$reg);
7561 Register opr2_reg = AT;
7563 Label &target = *($labl$$label);
7564 int flag = $cmp$$cmpcode;
7566 __ set64(opr2_reg, $src2$$constant);
7568 switch(flag)
7569 {
7570 case 0x01: //equal
7571 if (&target)
7572 __ beq(opr1_reg, opr2_reg, target);
7573 else
7574 __ beq(opr1_reg, opr2_reg, (int)0);
7575 break;
7577 case 0x02: //not_equal
7578 if(&target)
7579 __ bne(opr1_reg, opr2_reg, target);
7580 else
7581 __ bne(opr1_reg, opr2_reg, (int)0);
7582 break;
7584 case 0x03: //greater
7585 __ slt(AT, opr2_reg, opr1_reg);
7586 if(&target)
7587 __ bne(AT, R0, target);
7588 else
7589 __ bne(AT, R0, (int)0);
7590 break;
7592 case 0x04: //greater_equal
7593 __ slt(AT, opr1_reg, opr2_reg);
7594 if(&target)
7595 __ beq(AT, R0, target);
7596 else
7597 __ beq(AT, R0, (int)0);
7598 break;
7600 case 0x05: //less
7601 __ slt(AT, opr1_reg, opr2_reg);
7602 if(&target)
7603 __ bne(AT, R0, target);
7604 else
7605 __ bne(AT, R0, (int)0);
7606 break;
7608 case 0x06: //less_equal
7609 __ slt(AT, opr2_reg, opr1_reg);
7610 if(&target)
7611 __ beq(AT, R0, target);
7612 else
7613 __ beq(AT, R0, (int)0);
7614 break;
7616 default:
7617 Unimplemented();
7618 }
7619 __ nop();
7620 %}
7623 ins_pc_relative(1);
7624 ins_pipe( pipe_alu_branch );
7625 %}
7628 //FIXME
7629 instruct branchConF_reg_reg(cmpOp cmp, regF src1, regF src2, label labl) %{
7630 match( If cmp (CmpF src1 src2) );
7631 effect(USE labl);
7632 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg" %}
7634 ins_encode %{
7635 FloatRegister reg_op1 = $src1$$FloatRegister;
7636 FloatRegister reg_op2 = $src2$$FloatRegister;
7637 Label &L = *($labl$$label);
7638 int flag = $cmp$$cmpcode;
7640 switch(flag)
7641 {
7642 case 0x01: //equal
7643 __ c_eq_s(reg_op1, reg_op2);
7644 if (&L)
7645 __ bc1t(L);
7646 else
7647 __ bc1t((int)0);
7648 break;
7649 case 0x02: //not_equal
7650 __ c_eq_s(reg_op1, reg_op2);
7651 if (&L)
7652 __ bc1f(L);
7653 else
7654 __ bc1f((int)0);
7655 break;
7656 case 0x03: //greater
7657 __ c_ule_s(reg_op1, reg_op2);
7658 if(&L)
7659 __ bc1f(L);
7660 else
7661 __ bc1f((int)0);
7662 break;
7663 case 0x04: //greater_equal
7664 __ c_ult_s(reg_op1, reg_op2);
7665 if(&L)
7666 __ bc1f(L);
7667 else
7668 __ bc1f((int)0);
7669 break;
7670 case 0x05: //less
7671 __ c_ult_s(reg_op1, reg_op2);
7672 if(&L)
7673 __ bc1t(L);
7674 else
7675 __ bc1t((int)0);
7676 break;
7677 case 0x06: //less_equal
7678 __ c_ule_s(reg_op1, reg_op2);
7679 if(&L)
7680 __ bc1t(L);
7681 else
7682 __ bc1t((int)0);
7683 break;
7684 default:
7685 Unimplemented();
7686 }
7687 __ nop();
7688 %}
7690 ins_pc_relative(1);
7691 ins_pipe(pipe_slow);
7692 %}
7694 instruct branchConD_reg_reg(cmpOp cmp, regD src1, regD src2, label labl) %{
7695 match( If cmp (CmpD src1 src2) );
7696 effect(USE labl);
7697 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg" %}
7699 ins_encode %{
7700 FloatRegister reg_op1 = $src1$$FloatRegister;
7701 FloatRegister reg_op2 = $src2$$FloatRegister;
7702 Label &L = *($labl$$label);
7703 int flag = $cmp$$cmpcode;
7705 switch(flag)
7706 {
7707 case 0x01: //equal
7708 __ c_eq_d(reg_op1, reg_op2);
7709 if (&L)
7710 __ bc1t(L);
7711 else
7712 __ bc1t((int)0);
7713 break;
7714 case 0x02: //not_equal
7715 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
7716 __ c_eq_d(reg_op1, reg_op2);
7717 if (&L)
7718 __ bc1f(L);
7719 else
7720 __ bc1f((int)0);
7721 break;
7722 case 0x03: //greater
7723 __ c_ule_d(reg_op1, reg_op2);
7724 if(&L)
7725 __ bc1f(L);
7726 else
7727 __ bc1f((int)0);
7728 break;
7729 case 0x04: //greater_equal
7730 __ c_ult_d(reg_op1, reg_op2);
7731 if(&L)
7732 __ bc1f(L);
7733 else
7734 __ bc1f((int)0);
7735 break;
7736 case 0x05: //less
7737 __ c_ult_d(reg_op1, reg_op2);
7738 if(&L)
7739 __ bc1t(L);
7740 else
7741 __ bc1t((int)0);
7742 break;
7743 case 0x06: //less_equal
7744 __ c_ule_d(reg_op1, reg_op2);
7745 if(&L)
7746 __ bc1t(L);
7747 else
7748 __ bc1t((int)0);
7749 break;
7750 default:
7751 Unimplemented();
7752 }
7753 __ nop();
7754 %}
7756 ins_pc_relative(1);
7757 ins_pipe(pipe_slow);
7758 %}
7761 // Call Runtime Instruction
7762 instruct CallRuntimeDirect(method meth) %{
7763 match(CallRuntime );
7764 effect(USE meth);
7766 ins_cost(300);
7767 format %{ "CALL,runtime #@CallRuntimeDirect" %}
7768 ins_encode( Java_To_Runtime( meth ) );
7769 ins_pipe( pipe_slow );
7770 ins_alignment(16);
7771 %}
7775 //------------------------MemBar Instructions-------------------------------
7776 //Memory barrier flavors
7778 instruct membar_acquire() %{
7779 match(MemBarAcquire);
7780 ins_cost(0);
7782 size(0);
7783 format %{ "MEMBAR-acquire (empty) @ membar_acquire" %}
7784 ins_encode();
7785 ins_pipe(empty);
7786 %}
7788 instruct load_fence() %{
7789 match(LoadFence);
7790 ins_cost(400);
7792 format %{ "MEMBAR @ load_fence" %}
7793 ins_encode %{
7794 __ sync();
7795 %}
7796 ins_pipe(pipe_slow);
7797 %}
7799 instruct membar_acquire_lock()
7800 %{
7801 match(MemBarAcquireLock);
7802 ins_cost(0);
7804 size(0);
7805 format %{ "MEMBAR-acquire (acquire as part of CAS in prior FastLock so empty encoding) @ membar_acquire_lock" %}
7806 ins_encode();
7807 ins_pipe(empty);
7808 %}
7810 instruct membar_release() %{
7811 match(MemBarRelease);
7812 ins_cost(400);
7814 format %{ "MEMBAR-release @ membar_release" %}
7816 ins_encode %{
7817 // Attention: DO NOT DELETE THIS GUY!
7818 __ sync();
7819 %}
7821 ins_pipe(pipe_slow);
7822 %}
7824 instruct store_fence() %{
7825 match(StoreFence);
7826 ins_cost(400);
7828 format %{ "MEMBAR @ store_fence" %}
7830 ins_encode %{
7831 __ sync();
7832 %}
7834 ins_pipe(pipe_slow);
7835 %}
7837 instruct membar_release_lock()
7838 %{
7839 match(MemBarReleaseLock);
7840 ins_cost(0);
7842 size(0);
7843 format %{ "MEMBAR-release-lock (release in FastUnlock so empty) @ membar_release_lock" %}
7844 ins_encode();
7845 ins_pipe(empty);
7846 %}
7849 instruct membar_volatile() %{
7850 match(MemBarVolatile);
7851 ins_cost(400);
7853 format %{ "MEMBAR-volatile" %}
7854 ins_encode %{
7855 if( !os::is_MP() ) return; // Not needed on single CPU
7856 __ sync();
7858 %}
7859 ins_pipe(pipe_slow);
7860 %}
7862 instruct unnecessary_membar_volatile() %{
7863 match(MemBarVolatile);
7864 predicate(Matcher::post_store_load_barrier(n));
7865 ins_cost(0);
7867 size(0);
7868 format %{ "MEMBAR-volatile (unnecessary so empty encoding) @ unnecessary_membar_volatile" %}
7869 ins_encode( );
7870 ins_pipe(empty);
7871 %}
7873 instruct membar_storestore() %{
7874 match(MemBarStoreStore);
7876 ins_cost(0);
7877 size(0);
7878 format %{ "MEMBAR-storestore (empty encoding) @ membar_storestore" %}
7879 ins_encode( );
7880 ins_pipe(empty);
7881 %}
7883 //----------Move Instructions--------------------------------------------------
7884 instruct castX2P(mRegP dst, mRegL src) %{
7885 match(Set dst (CastX2P src));
7886 format %{ "castX2P $dst, $src @ castX2P" %}
7887 ins_encode %{
7888 Register src = $src$$Register;
7889 Register dst = $dst$$Register;
7891 if(src != dst)
7892 __ move(dst, src);
7893 %}
7894 ins_cost(10);
7895 ins_pipe( ialu_regI_mov );
7896 %}
7898 instruct castP2X(mRegL dst, mRegP src ) %{
7899 match(Set dst (CastP2X src));
7901 format %{ "mov $dst, $src\t #@castP2X" %}
7902 ins_encode %{
7903 Register src = $src$$Register;
7904 Register dst = $dst$$Register;
7906 if(src != dst)
7907 __ move(dst, src);
7908 %}
7909 ins_pipe( ialu_regI_mov );
7910 %}
7912 instruct MoveF2I_reg_reg(mRegI dst, regF src) %{
7913 match(Set dst (MoveF2I src));
7914 effect(DEF dst, USE src);
7915 ins_cost(85);
7916 format %{ "MoveF2I $dst, $src @ MoveF2I_reg_reg" %}
7917 ins_encode %{
7918 Register dst = as_Register($dst$$reg);
7919 FloatRegister src = as_FloatRegister($src$$reg);
7921 __ mfc1(dst, src);
7922 %}
7923 ins_pipe( pipe_slow );
7924 %}
7926 instruct MoveI2F_reg_reg(regF dst, mRegI src) %{
7927 match(Set dst (MoveI2F src));
7928 effect(DEF dst, USE src);
7929 ins_cost(85);
7930 format %{ "MoveI2F $dst, $src @ MoveI2F_reg_reg" %}
7931 ins_encode %{
7932 Register src = as_Register($src$$reg);
7933 FloatRegister dst = as_FloatRegister($dst$$reg);
7935 __ mtc1(src, dst);
7936 %}
7937 ins_pipe( pipe_slow );
7938 %}
7940 instruct MoveD2L_reg_reg(mRegL dst, regD src) %{
7941 match(Set dst (MoveD2L src));
7942 effect(DEF dst, USE src);
7943 ins_cost(85);
7944 format %{ "MoveD2L $dst, $src @ MoveD2L_reg_reg" %}
7945 ins_encode %{
7946 Register dst = as_Register($dst$$reg);
7947 FloatRegister src = as_FloatRegister($src$$reg);
7949 __ dmfc1(dst, src);
7950 %}
7951 ins_pipe( pipe_slow );
7952 %}
7954 instruct MoveL2D_reg_reg(regD dst, mRegL src) %{
7955 match(Set dst (MoveL2D src));
7956 effect(DEF dst, USE src);
7957 ins_cost(85);
7958 format %{ "MoveL2D $dst, $src @ MoveL2D_reg_reg" %}
7959 ins_encode %{
7960 FloatRegister dst = as_FloatRegister($dst$$reg);
7961 Register src = as_Register($src$$reg);
7963 __ dmtc1(src, dst);
7964 %}
7965 ins_pipe( pipe_slow );
7966 %}
7968 //----------Conditional Move---------------------------------------------------
7969 // Conditional move
7970 instruct cmovI_cmpI_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
7971 match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
7972 ins_cost(80);
7973 format %{
7974 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n"
7975 "\tCMOV $dst,$src \t @cmovI_cmpI_reg_reg"
7976 %}
7978 ins_encode %{
7979 Register op1 = $tmp1$$Register;
7980 Register op2 = $tmp2$$Register;
7981 Register dst = $dst$$Register;
7982 Register src = $src$$Register;
7983 int flag = $cop$$cmpcode;
7985 switch(flag)
7986 {
7987 case 0x01: //equal
7988 __ subu32(AT, op1, op2);
7989 __ movz(dst, src, AT);
7990 break;
7992 case 0x02: //not_equal
7993 __ subu32(AT, op1, op2);
7994 __ movn(dst, src, AT);
7995 break;
7997 case 0x03: //great
7998 __ slt(AT, op2, op1);
7999 __ movn(dst, src, AT);
8000 break;
8002 case 0x04: //great_equal
8003 __ slt(AT, op1, op2);
8004 __ movz(dst, src, AT);
8005 break;
8007 case 0x05: //less
8008 __ slt(AT, op1, op2);
8009 __ movn(dst, src, AT);
8010 break;
8012 case 0x06: //less_equal
8013 __ slt(AT, op2, op1);
8014 __ movz(dst, src, AT);
8015 break;
8017 default:
8018 Unimplemented();
8019 }
8020 %}
8022 ins_pipe( pipe_slow );
8023 %}
8025 instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8026 match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8027 ins_cost(80);
8028 format %{
8029 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t"
8030 "CMOV $dst,$src\t @cmovI_cmpP_reg_reg"
8031 %}
8032 ins_encode %{
8033 Register op1 = $tmp1$$Register;
8034 Register op2 = $tmp2$$Register;
8035 Register dst = $dst$$Register;
8036 Register src = $src$$Register;
8037 int flag = $cop$$cmpcode;
8039 switch(flag)
8040 {
8041 case 0x01: //equal
8042 __ subu(AT, op1, op2);
8043 __ movz(dst, src, AT);
8044 break;
8046 case 0x02: //not_equal
8047 __ subu(AT, op1, op2);
8048 __ movn(dst, src, AT);
8049 break;
8051 case 0x03: //above
8052 __ sltu(AT, op2, op1);
8053 __ movn(dst, src, AT);
8054 break;
8056 case 0x04: //above_equal
8057 __ sltu(AT, op1, op2);
8058 __ movz(dst, src, AT);
8059 break;
8061 case 0x05: //below
8062 __ sltu(AT, op1, op2);
8063 __ movn(dst, src, AT);
8064 break;
8066 case 0x06: //below_equal
8067 __ sltu(AT, op2, op1);
8068 __ movz(dst, src, AT);
8069 break;
8071 default:
8072 Unimplemented();
8073 }
8074 %}
8076 ins_pipe( pipe_slow );
8077 %}
8079 instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8080 match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8081 ins_cost(80);
8082 format %{
8083 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_reg\n\t"
8084 "CMOV $dst,$src\t @cmovI_cmpN_reg_reg"
8085 %}
8086 ins_encode %{
8087 Register op1 = $tmp1$$Register;
8088 Register op2 = $tmp2$$Register;
8089 Register dst = $dst$$Register;
8090 Register src = $src$$Register;
8091 int flag = $cop$$cmpcode;
8093 switch(flag)
8094 {
8095 case 0x01: //equal
8096 __ subu32(AT, op1, op2);
8097 __ movz(dst, src, AT);
8098 break;
8100 case 0x02: //not_equal
8101 __ subu32(AT, op1, op2);
8102 __ movn(dst, src, AT);
8103 break;
8105 case 0x03: //above
8106 __ sltu(AT, op2, op1);
8107 __ movn(dst, src, AT);
8108 break;
8110 case 0x04: //above_equal
8111 __ sltu(AT, op1, op2);
8112 __ movz(dst, src, AT);
8113 break;
8115 case 0x05: //below
8116 __ sltu(AT, op1, op2);
8117 __ movn(dst, src, AT);
8118 break;
8120 case 0x06: //below_equal
8121 __ sltu(AT, op2, op1);
8122 __ movz(dst, src, AT);
8123 break;
8125 default:
8126 Unimplemented();
8127 }
8128 %}
8130 ins_pipe( pipe_slow );
8131 %}
8133 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8134 match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8135 ins_cost(80);
8136 format %{
8137 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpN_reg_reg\n\t"
8138 "CMOV $dst,$src\t @cmovP_cmpN_reg_reg"
8139 %}
8140 ins_encode %{
8141 Register op1 = $tmp1$$Register;
8142 Register op2 = $tmp2$$Register;
8143 Register dst = $dst$$Register;
8144 Register src = $src$$Register;
8145 int flag = $cop$$cmpcode;
8147 switch(flag)
8148 {
8149 case 0x01: //equal
8150 __ subu32(AT, op1, op2);
8151 __ movz(dst, src, AT);
8152 break;
8154 case 0x02: //not_equal
8155 __ subu32(AT, op1, op2);
8156 __ movn(dst, src, AT);
8157 break;
8159 case 0x03: //above
8160 __ sltu(AT, op2, op1);
8161 __ movn(dst, src, AT);
8162 break;
8164 case 0x04: //above_equal
8165 __ sltu(AT, op1, op2);
8166 __ movz(dst, src, AT);
8167 break;
8169 case 0x05: //below
8170 __ sltu(AT, op1, op2);
8171 __ movn(dst, src, AT);
8172 break;
8174 case 0x06: //below_equal
8175 __ sltu(AT, op2, op1);
8176 __ movz(dst, src, AT);
8177 break;
8179 default:
8180 Unimplemented();
8181 }
8182 %}
8184 ins_pipe( pipe_slow );
8185 %}
8187 instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8188 match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8189 ins_cost(80);
8190 format %{
8191 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_reg\n\t"
8192 "CMOV $dst,$src\t @cmovN_cmpP_reg_reg"
8193 %}
8194 ins_encode %{
8195 Register op1 = $tmp1$$Register;
8196 Register op2 = $tmp2$$Register;
8197 Register dst = $dst$$Register;
8198 Register src = $src$$Register;
8199 int flag = $cop$$cmpcode;
8201 switch(flag)
8202 {
8203 case 0x01: //equal
8204 __ subu(AT, op1, op2);
8205 __ movz(dst, src, AT);
8206 break;
8208 case 0x02: //not_equal
8209 __ subu(AT, op1, op2);
8210 __ movn(dst, src, AT);
8211 break;
8213 case 0x03: //above
8214 __ sltu(AT, op2, op1);
8215 __ movn(dst, src, AT);
8216 break;
8218 case 0x04: //above_equal
8219 __ sltu(AT, op1, op2);
8220 __ movz(dst, src, AT);
8221 break;
8223 case 0x05: //below
8224 __ sltu(AT, op1, op2);
8225 __ movn(dst, src, AT);
8226 break;
8228 case 0x06: //below_equal
8229 __ sltu(AT, op2, op1);
8230 __ movz(dst, src, AT);
8231 break;
8233 default:
8234 Unimplemented();
8235 }
8236 %}
8238 ins_pipe( pipe_slow );
8239 %}
8241 instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{
8242 match(Set dst (CMoveP (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8243 ins_cost(80);
8244 format %{
8245 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpD_reg_reg\n"
8246 "\tCMOV $dst,$src \t @cmovP_cmpD_reg_reg"
8247 %}
8248 ins_encode %{
8249 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8250 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8251 Register dst = as_Register($dst$$reg);
8252 Register src = as_Register($src$$reg);
8254 int flag = $cop$$cmpcode;
8256 switch(flag)
8257 {
8258 case 0x01: //equal
8259 __ c_eq_d(reg_op1, reg_op2);
8260 __ movt(dst, src);
8261 break;
8262 case 0x02: //not_equal
8263 __ c_eq_d(reg_op1, reg_op2);
8264 __ movf(dst, src);
8265 break;
8266 case 0x03: //greater
8267 __ c_ole_d(reg_op1, reg_op2);
8268 __ movf(dst, src);
8269 break;
8270 case 0x04: //greater_equal
8271 __ c_olt_d(reg_op1, reg_op2);
8272 __ movf(dst, src);
8273 break;
8274 case 0x05: //less
8275 __ c_ult_d(reg_op1, reg_op2);
8276 __ movt(dst, src);
8277 break;
8278 case 0x06: //less_equal
8279 __ c_ule_d(reg_op1, reg_op2);
8280 __ movt(dst, src);
8281 break;
8282 default:
8283 Unimplemented();
8284 }
8285 %}
8287 ins_pipe( pipe_slow );
8288 %}
8291 instruct cmovN_cmpN_reg_reg(mRegN dst, mRegN src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8292 match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8293 ins_cost(80);
8294 format %{
8295 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_reg\n\t"
8296 "CMOV $dst,$src\t @cmovN_cmpN_reg_reg"
8297 %}
8298 ins_encode %{
8299 Register op1 = $tmp1$$Register;
8300 Register op2 = $tmp2$$Register;
8301 Register dst = $dst$$Register;
8302 Register src = $src$$Register;
8303 int flag = $cop$$cmpcode;
8305 switch(flag)
8306 {
8307 case 0x01: //equal
8308 __ subu32(AT, op1, op2);
8309 __ movz(dst, src, AT);
8310 break;
8312 case 0x02: //not_equal
8313 __ subu32(AT, op1, op2);
8314 __ movn(dst, src, AT);
8315 break;
8317 case 0x03: //above
8318 __ sltu(AT, op2, op1);
8319 __ movn(dst, src, AT);
8320 break;
8322 case 0x04: //above_equal
8323 __ sltu(AT, op1, op2);
8324 __ movz(dst, src, AT);
8325 break;
8327 case 0x05: //below
8328 __ sltu(AT, op1, op2);
8329 __ movn(dst, src, AT);
8330 break;
8332 case 0x06: //below_equal
8333 __ sltu(AT, op2, op1);
8334 __ movz(dst, src, AT);
8335 break;
8337 default:
8338 Unimplemented();
8339 }
8340 %}
8342 ins_pipe( pipe_slow );
8343 %}
8346 instruct cmovI_cmpU_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
8347 match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
8348 ins_cost(80);
8349 format %{
8350 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_reg\n\t"
8351 "CMOV $dst,$src\t @cmovI_cmpU_reg_reg"
8352 %}
8353 ins_encode %{
8354 Register op1 = $tmp1$$Register;
8355 Register op2 = $tmp2$$Register;
8356 Register dst = $dst$$Register;
8357 Register src = $src$$Register;
8358 int flag = $cop$$cmpcode;
8360 switch(flag)
8361 {
8362 case 0x01: //equal
8363 __ subu(AT, op1, op2);
8364 __ movz(dst, src, AT);
8365 break;
8367 case 0x02: //not_equal
8368 __ subu(AT, op1, op2);
8369 __ movn(dst, src, AT);
8370 break;
8372 case 0x03: //above
8373 __ sltu(AT, op2, op1);
8374 __ movn(dst, src, AT);
8375 break;
8377 case 0x04: //above_equal
8378 __ sltu(AT, op1, op2);
8379 __ movz(dst, src, AT);
8380 break;
8382 case 0x05: //below
8383 __ sltu(AT, op1, op2);
8384 __ movn(dst, src, AT);
8385 break;
8387 case 0x06: //below_equal
8388 __ sltu(AT, op2, op1);
8389 __ movz(dst, src, AT);
8390 break;
8392 default:
8393 Unimplemented();
8394 }
8395 %}
8397 ins_pipe( pipe_slow );
8398 %}
8400 instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8401 match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8402 ins_cost(80);
8403 format %{
8404 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_reg\n"
8405 "\tCMOV $dst,$src \t @cmovI_cmpL_reg_reg"
8406 %}
8407 ins_encode %{
8408 Register opr1 = as_Register($tmp1$$reg);
8409 Register opr2 = as_Register($tmp2$$reg);
8410 Register dst = $dst$$Register;
8411 Register src = $src$$Register;
8412 int flag = $cop$$cmpcode;
8414 switch(flag)
8415 {
8416 case 0x01: //equal
8417 __ subu(AT, opr1, opr2);
8418 __ movz(dst, src, AT);
8419 break;
8421 case 0x02: //not_equal
8422 __ subu(AT, opr1, opr2);
8423 __ movn(dst, src, AT);
8424 break;
8426 case 0x03: //greater
8427 __ slt(AT, opr2, opr1);
8428 __ movn(dst, src, AT);
8429 break;
8431 case 0x04: //greater_equal
8432 __ slt(AT, opr1, opr2);
8433 __ movz(dst, src, AT);
8434 break;
8436 case 0x05: //less
8437 __ slt(AT, opr1, opr2);
8438 __ movn(dst, src, AT);
8439 break;
8441 case 0x06: //less_equal
8442 __ slt(AT, opr2, opr1);
8443 __ movz(dst, src, AT);
8444 break;
8446 default:
8447 Unimplemented();
8448 }
8449 %}
8451 ins_pipe( pipe_slow );
8452 %}
8454 instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8455 match(Set dst (CMoveP (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8456 ins_cost(80);
8457 format %{
8458 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpL_reg_reg\n"
8459 "\tCMOV $dst,$src \t @cmovP_cmpL_reg_reg"
8460 %}
8461 ins_encode %{
8462 Register opr1 = as_Register($tmp1$$reg);
8463 Register opr2 = as_Register($tmp2$$reg);
8464 Register dst = $dst$$Register;
8465 Register src = $src$$Register;
8466 int flag = $cop$$cmpcode;
8468 switch(flag)
8469 {
8470 case 0x01: //equal
8471 __ subu(AT, opr1, opr2);
8472 __ movz(dst, src, AT);
8473 break;
8475 case 0x02: //not_equal
8476 __ subu(AT, opr1, opr2);
8477 __ movn(dst, src, AT);
8478 break;
8480 case 0x03: //greater
8481 __ slt(AT, opr2, opr1);
8482 __ movn(dst, src, AT);
8483 break;
8485 case 0x04: //greater_equal
8486 __ slt(AT, opr1, opr2);
8487 __ movz(dst, src, AT);
8488 break;
8490 case 0x05: //less
8491 __ slt(AT, opr1, opr2);
8492 __ movn(dst, src, AT);
8493 break;
8495 case 0x06: //less_equal
8496 __ slt(AT, opr2, opr1);
8497 __ movz(dst, src, AT);
8498 break;
8500 default:
8501 Unimplemented();
8502 }
8503 %}
8505 ins_pipe( pipe_slow );
8506 %}
8508 instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src, regD tmp1, regD tmp2, cmpOp cop ) %{
8509 match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8510 ins_cost(80);
8511 format %{
8512 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_reg\n"
8513 "\tCMOV $dst,$src \t @cmovI_cmpD_reg_reg"
8514 %}
8515 ins_encode %{
8516 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8517 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8518 Register dst = as_Register($dst$$reg);
8519 Register src = as_Register($src$$reg);
8521 int flag = $cop$$cmpcode;
8523 switch(flag)
8524 {
8525 case 0x01: //equal
8526 __ c_eq_d(reg_op1, reg_op2);
8527 __ movt(dst, src);
8528 break;
8529 case 0x02: //not_equal
8530 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
8531 __ c_eq_d(reg_op1, reg_op2);
8532 __ movf(dst, src);
8533 break;
8534 case 0x03: //greater
8535 __ c_ole_d(reg_op1, reg_op2);
8536 __ movf(dst, src);
8537 break;
8538 case 0x04: //greater_equal
8539 __ c_olt_d(reg_op1, reg_op2);
8540 __ movf(dst, src);
8541 break;
8542 case 0x05: //less
8543 __ c_ult_d(reg_op1, reg_op2);
8544 __ movt(dst, src);
8545 break;
8546 case 0x06: //less_equal
8547 __ c_ule_d(reg_op1, reg_op2);
8548 __ movt(dst, src);
8549 break;
8550 default:
8551 Unimplemented();
8552 }
8553 %}
8555 ins_pipe( pipe_slow );
8556 %}
8559 instruct cmovP_cmpP_reg_reg(mRegP dst, mRegP src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8560 match(Set dst (CMoveP (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8561 ins_cost(80);
8562 format %{
8563 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpP_reg_reg\n\t"
8564 "CMOV $dst,$src\t @cmovP_cmpP_reg_reg"
8565 %}
8566 ins_encode %{
8567 Register op1 = $tmp1$$Register;
8568 Register op2 = $tmp2$$Register;
8569 Register dst = $dst$$Register;
8570 Register src = $src$$Register;
8571 int flag = $cop$$cmpcode;
8573 switch(flag)
8574 {
8575 case 0x01: //equal
8576 __ subu(AT, op1, op2);
8577 __ movz(dst, src, AT);
8578 break;
8580 case 0x02: //not_equal
8581 __ subu(AT, op1, op2);
8582 __ movn(dst, src, AT);
8583 break;
8585 case 0x03: //above
8586 __ sltu(AT, op2, op1);
8587 __ movn(dst, src, AT);
8588 break;
8590 case 0x04: //above_equal
8591 __ sltu(AT, op1, op2);
8592 __ movz(dst, src, AT);
8593 break;
8595 case 0x05: //below
8596 __ sltu(AT, op1, op2);
8597 __ movn(dst, src, AT);
8598 break;
8600 case 0x06: //below_equal
8601 __ sltu(AT, op2, op1);
8602 __ movz(dst, src, AT);
8603 break;
8605 default:
8606 Unimplemented();
8607 }
8608 %}
8610 ins_pipe( pipe_slow );
8611 %}
8613 instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8614 match(Set dst (CMoveP (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8615 ins_cost(80);
8616 format %{
8617 "CMP$cop $tmp1,$tmp2\t @cmovP_cmpI_reg_reg\n\t"
8618 "CMOV $dst,$src\t @cmovP_cmpI_reg_reg"
8619 %}
8620 ins_encode %{
8621 Register op1 = $tmp1$$Register;
8622 Register op2 = $tmp2$$Register;
8623 Register dst = $dst$$Register;
8624 Register src = $src$$Register;
8625 int flag = $cop$$cmpcode;
8627 switch(flag)
8628 {
8629 case 0x01: //equal
8630 __ subu32(AT, op1, op2);
8631 __ movz(dst, src, AT);
8632 break;
8634 case 0x02: //not_equal
8635 __ subu32(AT, op1, op2);
8636 __ movn(dst, src, AT);
8637 break;
8639 case 0x03: //above
8640 __ slt(AT, op2, op1);
8641 __ movn(dst, src, AT);
8642 break;
8644 case 0x04: //above_equal
8645 __ slt(AT, op1, op2);
8646 __ movz(dst, src, AT);
8647 break;
8649 case 0x05: //below
8650 __ slt(AT, op1, op2);
8651 __ movn(dst, src, AT);
8652 break;
8654 case 0x06: //below_equal
8655 __ slt(AT, op2, op1);
8656 __ movz(dst, src, AT);
8657 break;
8659 default:
8660 Unimplemented();
8661 }
8662 %}
8664 ins_pipe( pipe_slow );
8665 %}
8667 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8668 match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8669 ins_cost(80);
8670 format %{
8671 "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_reg\n\t"
8672 "CMOV $dst,$src\t @cmovN_cmpI_reg_reg"
8673 %}
8674 ins_encode %{
8675 Register op1 = $tmp1$$Register;
8676 Register op2 = $tmp2$$Register;
8677 Register dst = $dst$$Register;
8678 Register src = $src$$Register;
8679 int flag = $cop$$cmpcode;
8681 switch(flag)
8682 {
8683 case 0x01: //equal
8684 __ subu32(AT, op1, op2);
8685 __ movz(dst, src, AT);
8686 break;
8688 case 0x02: //not_equal
8689 __ subu32(AT, op1, op2);
8690 __ movn(dst, src, AT);
8691 break;
8693 case 0x03: //above
8694 __ slt(AT, op2, op1);
8695 __ movn(dst, src, AT);
8696 break;
8698 case 0x04: //above_equal
8699 __ slt(AT, op1, op2);
8700 __ movz(dst, src, AT);
8701 break;
8703 case 0x05: //below
8704 __ slt(AT, op1, op2);
8705 __ movn(dst, src, AT);
8706 break;
8708 case 0x06: //below_equal
8709 __ slt(AT, op2, op1);
8710 __ movz(dst, src, AT);
8711 break;
8713 default:
8714 Unimplemented();
8715 }
8716 %}
8718 ins_pipe( pipe_slow );
8719 %}
8722 instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8723 match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8724 ins_cost(80);
8725 format %{
8726 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_reg\n"
8727 "\tCMOV $dst,$src \t @cmovL_cmpI_reg_reg"
8728 %}
8730 ins_encode %{
8731 Register op1 = $tmp1$$Register;
8732 Register op2 = $tmp2$$Register;
8733 Register dst = as_Register($dst$$reg);
8734 Register src = as_Register($src$$reg);
8735 int flag = $cop$$cmpcode;
8737 switch(flag)
8738 {
8739 case 0x01: //equal
8740 __ subu32(AT, op1, op2);
8741 __ movz(dst, src, AT);
8742 break;
8744 case 0x02: //not_equal
8745 __ subu32(AT, op1, op2);
8746 __ movn(dst, src, AT);
8747 break;
8749 case 0x03: //great
8750 __ slt(AT, op2, op1);
8751 __ movn(dst, src, AT);
8752 break;
8754 case 0x04: //great_equal
8755 __ slt(AT, op1, op2);
8756 __ movz(dst, src, AT);
8757 break;
8759 case 0x05: //less
8760 __ slt(AT, op1, op2);
8761 __ movn(dst, src, AT);
8762 break;
8764 case 0x06: //less_equal
8765 __ slt(AT, op2, op1);
8766 __ movz(dst, src, AT);
8767 break;
8769 default:
8770 Unimplemented();
8771 }
8772 %}
8774 ins_pipe( pipe_slow );
8775 %}
8777 instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8778 match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8779 ins_cost(80);
8780 format %{
8781 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_reg\n"
8782 "\tCMOV $dst,$src \t @cmovL_cmpL_reg_reg"
8783 %}
8784 ins_encode %{
8785 Register opr1 = as_Register($tmp1$$reg);
8786 Register opr2 = as_Register($tmp2$$reg);
8787 Register dst = as_Register($dst$$reg);
8788 Register src = as_Register($src$$reg);
8789 int flag = $cop$$cmpcode;
8791 switch(flag)
8792 {
8793 case 0x01: //equal
8794 __ subu(AT, opr1, opr2);
8795 __ movz(dst, src, AT);
8796 break;
8798 case 0x02: //not_equal
8799 __ subu(AT, opr1, opr2);
8800 __ movn(dst, src, AT);
8801 break;
8803 case 0x03: //greater
8804 __ slt(AT, opr2, opr1);
8805 __ movn(dst, src, AT);
8806 break;
8808 case 0x04: //greater_equal
8809 __ slt(AT, opr1, opr2);
8810 __ movz(dst, src, AT);
8811 break;
8813 case 0x05: //less
8814 __ slt(AT, opr1, opr2);
8815 __ movn(dst, src, AT);
8816 break;
8818 case 0x06: //less_equal
8819 __ slt(AT, opr2, opr1);
8820 __ movz(dst, src, AT);
8821 break;
8823 default:
8824 Unimplemented();
8825 }
8826 %}
8828 ins_pipe( pipe_slow );
8829 %}
8831 instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8832 match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8833 ins_cost(80);
8834 format %{
8835 "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_reg\n\t"
8836 "CMOV $dst,$src\t @cmovL_cmpN_reg_reg"
8837 %}
8838 ins_encode %{
8839 Register op1 = $tmp1$$Register;
8840 Register op2 = $tmp2$$Register;
8841 Register dst = $dst$$Register;
8842 Register src = $src$$Register;
8843 int flag = $cop$$cmpcode;
8845 switch(flag)
8846 {
8847 case 0x01: //equal
8848 __ subu32(AT, op1, op2);
8849 __ movz(dst, src, AT);
8850 break;
8852 case 0x02: //not_equal
8853 __ subu32(AT, op1, op2);
8854 __ movn(dst, src, AT);
8855 break;
8857 case 0x03: //above
8858 __ sltu(AT, op2, op1);
8859 __ movn(dst, src, AT);
8860 break;
8862 case 0x04: //above_equal
8863 __ sltu(AT, op1, op2);
8864 __ movz(dst, src, AT);
8865 break;
8867 case 0x05: //below
8868 __ sltu(AT, op1, op2);
8869 __ movn(dst, src, AT);
8870 break;
8872 case 0x06: //below_equal
8873 __ sltu(AT, op2, op1);
8874 __ movz(dst, src, AT);
8875 break;
8877 default:
8878 Unimplemented();
8879 }
8880 %}
8882 ins_pipe( pipe_slow );
8883 %}
8886 instruct cmovL_cmpD_reg_reg(mRegL dst, mRegL src, regD tmp1, regD tmp2, cmpOp cop ) %{
8887 match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8888 ins_cost(80);
8889 format %{
8890 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_reg\n"
8891 "\tCMOV $dst,$src \t @cmovL_cmpD_reg_reg"
8892 %}
8893 ins_encode %{
8894 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8895 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8896 Register dst = as_Register($dst$$reg);
8897 Register src = as_Register($src$$reg);
8899 int flag = $cop$$cmpcode;
8901 switch(flag)
8902 {
8903 case 0x01: //equal
8904 __ c_eq_d(reg_op1, reg_op2);
8905 __ movt(dst, src);
8906 break;
8907 case 0x02: //not_equal
8908 __ c_eq_d(reg_op1, reg_op2);
8909 __ movf(dst, src);
8910 break;
8911 case 0x03: //greater
8912 __ c_ole_d(reg_op1, reg_op2);
8913 __ movf(dst, src);
8914 break;
8915 case 0x04: //greater_equal
8916 __ c_olt_d(reg_op1, reg_op2);
8917 __ movf(dst, src);
8918 break;
8919 case 0x05: //less
8920 __ c_ult_d(reg_op1, reg_op2);
8921 __ movt(dst, src);
8922 break;
8923 case 0x06: //less_equal
8924 __ c_ule_d(reg_op1, reg_op2);
8925 __ movt(dst, src);
8926 break;
8927 default:
8928 Unimplemented();
8929 }
8930 %}
8932 ins_pipe( pipe_slow );
8933 %}
8935 instruct cmovD_cmpD_reg_reg(regD dst, regD src, regD tmp1, regD tmp2, cmpOp cop ) %{
8936 match(Set dst (CMoveD (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8937 ins_cost(200);
8938 format %{
8939 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpD_reg_reg\n"
8940 "\tCMOV $dst,$src \t @cmovD_cmpD_reg_reg"
8941 %}
8942 ins_encode %{
8943 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8944 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8945 FloatRegister dst = as_FloatRegister($dst$$reg);
8946 FloatRegister src = as_FloatRegister($src$$reg);
8948 int flag = $cop$$cmpcode;
8950 switch(flag)
8951 {
8952 case 0x01: //equal
8953 __ c_eq_d(reg_op1, reg_op2);
8954 __ movt_d(dst, src);
8955 break;
8956 case 0x02: //not_equal
8957 __ c_eq_d(reg_op1, reg_op2);
8958 __ movf_d(dst, src);
8959 break;
8960 case 0x03: //greater
8961 __ c_ole_d(reg_op1, reg_op2);
8962 __ movf_d(dst, src);
8963 break;
8964 case 0x04: //greater_equal
8965 __ c_olt_d(reg_op1, reg_op2);
8966 __ movf_d(dst, src);
8967 break;
8968 case 0x05: //less
8969 __ c_ult_d(reg_op1, reg_op2);
8970 __ movt_d(dst, src);
8971 break;
8972 case 0x06: //less_equal
8973 __ c_ule_d(reg_op1, reg_op2);
8974 __ movt_d(dst, src);
8975 break;
8976 default:
8977 Unimplemented();
8978 }
8979 %}
8981 ins_pipe( pipe_slow );
8982 %}
8984 instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8985 match(Set dst (CMoveF (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8986 ins_cost(200);
8987 format %{
8988 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpI_reg_reg\n"
8989 "\tCMOV $dst, $src \t @cmovF_cmpI_reg_reg"
8990 %}
8992 ins_encode %{
8993 Register op1 = $tmp1$$Register;
8994 Register op2 = $tmp2$$Register;
8995 FloatRegister dst = as_FloatRegister($dst$$reg);
8996 FloatRegister src = as_FloatRegister($src$$reg);
8997 int flag = $cop$$cmpcode;
8998 Label L;
9000 switch(flag)
9001 {
9002 case 0x01: //equal
9003 __ bne(op1, op2, L);
9004 __ nop();
9005 __ mov_s(dst, src);
9006 __ bind(L);
9007 break;
9008 case 0x02: //not_equal
9009 __ beq(op1, op2, L);
9010 __ nop();
9011 __ mov_s(dst, src);
9012 __ bind(L);
9013 break;
9014 case 0x03: //great
9015 __ slt(AT, op2, op1);
9016 __ beq(AT, R0, L);
9017 __ nop();
9018 __ mov_s(dst, src);
9019 __ bind(L);
9020 break;
9021 case 0x04: //great_equal
9022 __ slt(AT, op1, op2);
9023 __ bne(AT, R0, L);
9024 __ nop();
9025 __ mov_s(dst, src);
9026 __ bind(L);
9027 break;
9028 case 0x05: //less
9029 __ slt(AT, op1, op2);
9030 __ beq(AT, R0, L);
9031 __ nop();
9032 __ mov_s(dst, src);
9033 __ bind(L);
9034 break;
9035 case 0x06: //less_equal
9036 __ slt(AT, op2, op1);
9037 __ bne(AT, R0, L);
9038 __ nop();
9039 __ mov_s(dst, src);
9040 __ bind(L);
9041 break;
9042 default:
9043 Unimplemented();
9044 }
9045 %}
9047 ins_pipe( pipe_slow );
9048 %}
9050 instruct cmovD_cmpI_reg_reg(regD dst, regD src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9051 match(Set dst (CMoveD (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9052 ins_cost(200);
9053 format %{
9054 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpI_reg_reg\n"
9055 "\tCMOV $dst, $src \t @cmovD_cmpI_reg_reg"
9056 %}
9058 ins_encode %{
9059 Register op1 = $tmp1$$Register;
9060 Register op2 = $tmp2$$Register;
9061 FloatRegister dst = as_FloatRegister($dst$$reg);
9062 FloatRegister src = as_FloatRegister($src$$reg);
9063 int flag = $cop$$cmpcode;
9064 Label L;
9066 switch(flag)
9067 {
9068 case 0x01: //equal
9069 __ bne(op1, op2, L);
9070 __ nop();
9071 __ mov_d(dst, src);
9072 __ bind(L);
9073 break;
9074 case 0x02: //not_equal
9075 __ beq(op1, op2, L);
9076 __ nop();
9077 __ mov_d(dst, src);
9078 __ bind(L);
9079 break;
9080 case 0x03: //great
9081 __ slt(AT, op2, op1);
9082 __ beq(AT, R0, L);
9083 __ nop();
9084 __ mov_d(dst, src);
9085 __ bind(L);
9086 break;
9087 case 0x04: //great_equal
9088 __ slt(AT, op1, op2);
9089 __ bne(AT, R0, L);
9090 __ nop();
9091 __ mov_d(dst, src);
9092 __ bind(L);
9093 break;
9094 case 0x05: //less
9095 __ slt(AT, op1, op2);
9096 __ beq(AT, R0, L);
9097 __ nop();
9098 __ mov_d(dst, src);
9099 __ bind(L);
9100 break;
9101 case 0x06: //less_equal
9102 __ slt(AT, op2, op1);
9103 __ bne(AT, R0, L);
9104 __ nop();
9105 __ mov_d(dst, src);
9106 __ bind(L);
9107 break;
9108 default:
9109 Unimplemented();
9110 }
9111 %}
9113 ins_pipe( pipe_slow );
9114 %}
9116 instruct cmovD_cmpP_reg_reg(regD dst, regD src, mRegP tmp1, mRegP tmp2, cmpOp cop ) %{
9117 match(Set dst (CMoveD (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
9118 ins_cost(200);
9119 format %{
9120 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpP_reg_reg\n"
9121 "\tCMOV $dst, $src \t @cmovD_cmpP_reg_reg"
9122 %}
9124 ins_encode %{
9125 Register op1 = $tmp1$$Register;
9126 Register op2 = $tmp2$$Register;
9127 FloatRegister dst = as_FloatRegister($dst$$reg);
9128 FloatRegister src = as_FloatRegister($src$$reg);
9129 int flag = $cop$$cmpcode;
9130 Label L;
9132 switch(flag)
9133 {
9134 case 0x01: //equal
9135 __ bne(op1, op2, L);
9136 __ nop();
9137 __ mov_d(dst, src);
9138 __ bind(L);
9139 break;
9140 case 0x02: //not_equal
9141 __ beq(op1, op2, L);
9142 __ nop();
9143 __ mov_d(dst, src);
9144 __ bind(L);
9145 break;
9146 case 0x03: //great
9147 __ slt(AT, op2, op1);
9148 __ beq(AT, R0, L);
9149 __ nop();
9150 __ mov_d(dst, src);
9151 __ bind(L);
9152 break;
9153 case 0x04: //great_equal
9154 __ slt(AT, op1, op2);
9155 __ bne(AT, R0, L);
9156 __ nop();
9157 __ mov_d(dst, src);
9158 __ bind(L);
9159 break;
9160 case 0x05: //less
9161 __ slt(AT, op1, op2);
9162 __ beq(AT, R0, L);
9163 __ nop();
9164 __ mov_d(dst, src);
9165 __ bind(L);
9166 break;
9167 case 0x06: //less_equal
9168 __ slt(AT, op2, op1);
9169 __ bne(AT, R0, L);
9170 __ nop();
9171 __ mov_d(dst, src);
9172 __ bind(L);
9173 break;
9174 default:
9175 Unimplemented();
9176 }
9177 %}
9179 ins_pipe( pipe_slow );
9180 %}
9182 //FIXME
9183 instruct cmovI_cmpF_reg_reg(mRegI dst, mRegI src, regF tmp1, regF tmp2, cmpOp cop ) %{
9184 match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9185 ins_cost(80);
9186 format %{
9187 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_reg\n"
9188 "\tCMOV $dst,$src \t @cmovI_cmpF_reg_reg"
9189 %}
9191 ins_encode %{
9192 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9193 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9194 Register dst = $dst$$Register;
9195 Register src = $src$$Register;
9196 int flag = $cop$$cmpcode;
9198 switch(flag)
9199 {
9200 case 0x01: //equal
9201 __ c_eq_s(reg_op1, reg_op2);
9202 __ movt(dst, src);
9203 break;
9204 case 0x02: //not_equal
9205 __ c_eq_s(reg_op1, reg_op2);
9206 __ movf(dst, src);
9207 break;
9208 case 0x03: //greater
9209 __ c_ole_s(reg_op1, reg_op2);
9210 __ movf(dst, src);
9211 break;
9212 case 0x04: //greater_equal
9213 __ c_olt_s(reg_op1, reg_op2);
9214 __ movf(dst, src);
9215 break;
9216 case 0x05: //less
9217 __ c_ult_s(reg_op1, reg_op2);
9218 __ movt(dst, src);
9219 break;
9220 case 0x06: //less_equal
9221 __ c_ule_s(reg_op1, reg_op2);
9222 __ movt(dst, src);
9223 break;
9224 default:
9225 Unimplemented();
9226 }
9227 %}
9228 ins_pipe( pipe_slow );
9229 %}
9231 instruct cmovF_cmpF_reg_reg(regF dst, regF src, regF tmp1, regF tmp2, cmpOp cop ) %{
9232 match(Set dst (CMoveF (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9233 ins_cost(200);
9234 format %{
9235 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpF_reg_reg\n"
9236 "\tCMOV $dst,$src \t @cmovF_cmpF_reg_reg"
9237 %}
9239 ins_encode %{
9240 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9241 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9242 FloatRegister dst = $dst$$FloatRegister;
9243 FloatRegister src = $src$$FloatRegister;
9244 int flag = $cop$$cmpcode;
9246 switch(flag)
9247 {
9248 case 0x01: //equal
9249 __ c_eq_s(reg_op1, reg_op2);
9250 __ movt_s(dst, src);
9251 break;
9252 case 0x02: //not_equal
9253 __ c_eq_s(reg_op1, reg_op2);
9254 __ movf_s(dst, src);
9255 break;
9256 case 0x03: //greater
9257 __ c_ole_s(reg_op1, reg_op2);
9258 __ movf_s(dst, src);
9259 break;
9260 case 0x04: //greater_equal
9261 __ c_olt_s(reg_op1, reg_op2);
9262 __ movf_s(dst, src);
9263 break;
9264 case 0x05: //less
9265 __ c_ult_s(reg_op1, reg_op2);
9266 __ movt_s(dst, src);
9267 break;
9268 case 0x06: //less_equal
9269 __ c_ule_s(reg_op1, reg_op2);
9270 __ movt_s(dst, src);
9271 break;
9272 default:
9273 Unimplemented();
9274 }
9275 %}
9276 ins_pipe( pipe_slow );
9277 %}
9279 // Manifest a CmpL result in an integer register. Very painful.
9280 // This is the test to avoid.
9281 instruct cmpL3_reg_reg(mRegI dst, mRegL src1, mRegL src2) %{
9282 match(Set dst (CmpL3 src1 src2));
9283 ins_cost(1000);
9284 format %{ "cmpL3 $dst, $src1, $src2 @ cmpL3_reg_reg" %}
9285 ins_encode %{
9286 Register opr1 = as_Register($src1$$reg);
9287 Register opr2 = as_Register($src2$$reg);
9288 Register dst = as_Register($dst$$reg);
9290 Label Done;
9292 __ subu(AT, opr1, opr2);
9293 __ bltz(AT, Done);
9294 __ delayed()->daddiu(dst, R0, -1);
9296 __ move(dst, 1);
9297 __ movz(dst, R0, AT);
9299 __ bind(Done);
9300 %}
9301 ins_pipe( pipe_slow );
9302 %}
9304 //
9305 // less_rsult = -1
9306 // greater_result = 1
9307 // equal_result = 0
9308 // nan_result = -1
9309 //
9310 instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{
9311 match(Set dst (CmpF3 src1 src2));
9312 ins_cost(1000);
9313 format %{ "cmpF3 $dst, $src1, $src2 @ cmpF3_reg_reg" %}
9314 ins_encode %{
9315 FloatRegister src1 = as_FloatRegister($src1$$reg);
9316 FloatRegister src2 = as_FloatRegister($src2$$reg);
9317 Register dst = as_Register($dst$$reg);
9319 Label Done;
9321 __ c_ult_s(src1, src2);
9322 __ bc1t(Done);
9323 __ delayed()->daddiu(dst, R0, -1);
9325 __ c_eq_s(src1, src2);
9326 __ move(dst, 1);
9327 __ movt(dst, R0);
9329 __ bind(Done);
9330 %}
9331 ins_pipe( pipe_slow );
9332 %}
9334 instruct cmpD3_reg_reg(mRegI dst, regD src1, regD src2) %{
9335 match(Set dst (CmpD3 src1 src2));
9336 ins_cost(1000);
9337 format %{ "cmpD3 $dst, $src1, $src2 @ cmpD3_reg_reg" %}
9338 ins_encode %{
9339 FloatRegister src1 = as_FloatRegister($src1$$reg);
9340 FloatRegister src2 = as_FloatRegister($src2$$reg);
9341 Register dst = as_Register($dst$$reg);
9343 Label Done;
9345 __ c_ult_d(src1, src2);
9346 __ bc1t(Done);
9347 __ delayed()->daddiu(dst, R0, -1);
9349 __ c_eq_d(src1, src2);
9350 __ move(dst, 1);
9351 __ movt(dst, R0);
9353 __ bind(Done);
9354 %}
9355 ins_pipe( pipe_slow );
9356 %}
9358 instruct clear_array(mRegL cnt, mRegP base, Universe dummy) %{
9359 match(Set dummy (ClearArray cnt base));
9360 format %{ "CLEAR_ARRAY base = $base, cnt = $cnt # Clear doublewords" %}
9361 ins_encode %{
9362 //Assume cnt is the number of bytes in an array to be cleared,
9363 //and base points to the starting address of the array.
9364 Register base = $base$$Register;
9365 Register num = $cnt$$Register;
9366 Label Loop, done;
9368 __ beq(num, R0, done);
9369 __ delayed()->daddu(AT, base, R0);
9371 __ move(T9, num); /* T9 = words */
9373 __ bind(Loop);
9374 __ sd(R0, AT, 0);
9375 __ daddi(T9, T9, -1);
9376 __ bne(T9, R0, Loop);
9377 __ delayed()->daddi(AT, AT, wordSize);
9379 __ bind(done);
9380 %}
9381 ins_pipe( pipe_slow );
9382 %}
9384 instruct string_compare(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, no_Ax_mRegI result) %{
9385 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9386 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
9388 format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %}
9389 ins_encode %{
9390 // Get the first character position in both strings
9391 // [8] char array, [12] offset, [16] count
9392 Register str1 = $str1$$Register;
9393 Register str2 = $str2$$Register;
9394 Register cnt1 = $cnt1$$Register;
9395 Register cnt2 = $cnt2$$Register;
9396 Register result = $result$$Register;
9398 Label L, Loop, haveResult, done;
9400 // compute the and difference of lengths (in result)
9401 __ subu(result, cnt1, cnt2); // result holds the difference of two lengths
9403 // compute the shorter length (in cnt1)
9404 __ slt(AT, cnt2, cnt1);
9405 __ movn(cnt1, cnt2, AT);
9407 // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register
9408 __ bind(Loop); // Loop begin
9409 __ beq(cnt1, R0, done);
9410 __ delayed()->lhu(AT, str1, 0);;
9412 // compare current character
9413 __ lhu(cnt2, str2, 0);
9414 __ bne(AT, cnt2, haveResult);
9415 __ delayed()->addi(str1, str1, 2);
9416 __ addi(str2, str2, 2);
9417 __ b(Loop);
9418 __ delayed()->addi(cnt1, cnt1, -1); // Loop end
9420 __ bind(haveResult);
9421 __ subu(result, AT, cnt2);
9423 __ bind(done);
9424 %}
9426 ins_pipe( pipe_slow );
9427 %}
9429 // intrinsic optimization
9430 instruct string_equals(a4_RegP str1, a5_RegP str2, mA6RegI cnt, mA7RegI temp, no_Ax_mRegI result) %{
9431 match(Set result (StrEquals (Binary str1 str2) cnt));
9432 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL temp);
9434 format %{ "String Equal $str1, $str2, len:$cnt tmp:$temp -> $result @ string_equals" %}
9435 ins_encode %{
9436 // Get the first character position in both strings
9437 // [8] char array, [12] offset, [16] count
9438 Register str1 = $str1$$Register;
9439 Register str2 = $str2$$Register;
9440 Register cnt = $cnt$$Register;
9441 Register tmp = $temp$$Register;
9442 Register result = $result$$Register;
9444 Label Loop, done;
9447 __ beq(str1, str2, done); // same char[] ?
9448 __ daddiu(result, R0, 1);
9450 __ bind(Loop); // Loop begin
9451 __ beq(cnt, R0, done);
9452 __ daddiu(result, R0, 1); // count == 0
9454 // compare current character
9455 __ lhu(AT, str1, 0);;
9456 __ lhu(tmp, str2, 0);
9457 __ bne(AT, tmp, done);
9458 __ delayed()->daddi(result, R0, 0);
9459 __ addi(str1, str1, 2);
9460 __ addi(str2, str2, 2);
9461 __ b(Loop);
9462 __ delayed()->addi(cnt, cnt, -1); // Loop end
9464 __ bind(done);
9465 %}
9467 ins_pipe( pipe_slow );
9468 %}
9470 //----------Arithmetic Instructions-------------------------------------------
9471 //----------Addition Instructions---------------------------------------------
9472 instruct addI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9473 match(Set dst (AddI src1 src2));
9475 format %{ "add $dst, $src1, $src2 #@addI_Reg_Reg" %}
9476 ins_encode %{
9477 Register dst = $dst$$Register;
9478 Register src1 = $src1$$Register;
9479 Register src2 = $src2$$Register;
9480 __ addu32(dst, src1, src2);
9481 %}
9482 ins_pipe( ialu_regI_regI );
9483 %}
9485 instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
9486 match(Set dst (AddI src1 src2));
9488 format %{ "add $dst, $src1, $src2 #@addI_Reg_imm" %}
9489 ins_encode %{
9490 Register dst = $dst$$Register;
9491 Register src1 = $src1$$Register;
9492 int imm = $src2$$constant;
9494 if(Assembler::is_simm16(imm)) {
9495 __ addiu32(dst, src1, imm);
9496 } else {
9497 __ move(AT, imm);
9498 __ addu32(dst, src1, AT);
9499 }
9500 %}
9501 ins_pipe( ialu_regI_regI );
9502 %}
9504 instruct addP_reg_reg(mRegP dst, mRegP src1, mRegL src2) %{
9505 match(Set dst (AddP src1 src2));
9507 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
9509 ins_encode %{
9510 Register dst = $dst$$Register;
9511 Register src1 = $src1$$Register;
9512 Register src2 = $src2$$Register;
9513 __ daddu(dst, src1, src2);
9514 %}
9516 ins_pipe( ialu_regI_regI );
9517 %}
9519 instruct addP_reg_reg_convI2L(mRegP dst, mRegP src1, mRegI src2) %{
9520 match(Set dst (AddP src1 (ConvI2L src2)));
9522 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg_convI2L" %}
9524 ins_encode %{
9525 Register dst = $dst$$Register;
9526 Register src1 = $src1$$Register;
9527 Register src2 = $src2$$Register;
9528 __ daddu(dst, src1, src2);
9529 %}
9531 ins_pipe( ialu_regI_regI );
9532 %}
9534 instruct addP_reg_imm(mRegP dst, mRegP src1, immL src2) %{
9535 match(Set dst (AddP src1 src2));
9537 format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm" %}
9538 ins_encode %{
9539 Register src1 = $src1$$Register;
9540 long src2 = $src2$$constant;
9541 Register dst = $dst$$Register;
9543 if(Assembler::is_simm16(src2)) {
9544 __ daddiu(dst, src1, src2);
9545 } else {
9546 __ set64(AT, src2);
9547 __ daddu(dst, src1, AT);
9548 }
9549 %}
9550 ins_pipe( ialu_regI_imm16 );
9551 %}
9553 // Add Long Register with Register
9554 instruct addL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9555 match(Set dst (AddL src1 src2));
9556 ins_cost(200);
9557 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_Reg\t" %}
9559 ins_encode %{
9560 Register dst_reg = as_Register($dst$$reg);
9561 Register src1_reg = as_Register($src1$$reg);
9562 Register src2_reg = as_Register($src2$$reg);
9564 __ daddu(dst_reg, src1_reg, src2_reg);
9565 %}
9567 ins_pipe( ialu_regL_regL );
9568 %}
9570 instruct addL_Reg_imm(mRegL dst, mRegL src1, immL16 src2)
9571 %{
9572 match(Set dst (AddL src1 src2));
9574 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_imm " %}
9575 ins_encode %{
9576 Register dst_reg = as_Register($dst$$reg);
9577 Register src1_reg = as_Register($src1$$reg);
9578 int src2_imm = $src2$$constant;
9580 __ daddiu(dst_reg, src1_reg, src2_imm);
9581 %}
9583 ins_pipe( ialu_regL_regL );
9584 %}
9586 instruct addL_RegI2L_imm(mRegL dst, mRegI src1, immL16 src2)
9587 %{
9588 match(Set dst (AddL (ConvI2L src1) src2));
9590 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_imm " %}
9591 ins_encode %{
9592 Register dst_reg = as_Register($dst$$reg);
9593 Register src1_reg = as_Register($src1$$reg);
9594 int src2_imm = $src2$$constant;
9596 __ daddiu(dst_reg, src1_reg, src2_imm);
9597 %}
9599 ins_pipe( ialu_regL_regL );
9600 %}
9602 instruct addL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9603 match(Set dst (AddL (ConvI2L src1) src2));
9604 ins_cost(200);
9605 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_Reg\t" %}
9607 ins_encode %{
9608 Register dst_reg = as_Register($dst$$reg);
9609 Register src1_reg = as_Register($src1$$reg);
9610 Register src2_reg = as_Register($src2$$reg);
9612 __ daddu(dst_reg, src1_reg, src2_reg);
9613 %}
9615 ins_pipe( ialu_regL_regL );
9616 %}
9618 instruct addL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9619 match(Set dst (AddL (ConvI2L src1) (ConvI2L src2)));
9620 ins_cost(200);
9621 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_RegI2L\t" %}
9623 ins_encode %{
9624 Register dst_reg = as_Register($dst$$reg);
9625 Register src1_reg = as_Register($src1$$reg);
9626 Register src2_reg = as_Register($src2$$reg);
9628 __ daddu(dst_reg, src1_reg, src2_reg);
9629 %}
9631 ins_pipe( ialu_regL_regL );
9632 %}
9634 instruct addL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9635 match(Set dst (AddL src1 (ConvI2L src2)));
9636 ins_cost(200);
9637 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_RegI2L\t" %}
9639 ins_encode %{
9640 Register dst_reg = as_Register($dst$$reg);
9641 Register src1_reg = as_Register($src1$$reg);
9642 Register src2_reg = as_Register($src2$$reg);
9644 __ daddu(dst_reg, src1_reg, src2_reg);
9645 %}
9647 ins_pipe( ialu_regL_regL );
9648 %}
9650 //----------Subtraction Instructions-------------------------------------------
9651 // Integer Subtraction Instructions
9652 instruct subI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9653 match(Set dst (SubI src1 src2));
9654 ins_cost(100);
9656 format %{ "sub $dst, $src1, $src2 #@subI_Reg_Reg" %}
9657 ins_encode %{
9658 Register dst = $dst$$Register;
9659 Register src1 = $src1$$Register;
9660 Register src2 = $src2$$Register;
9661 __ subu32(dst, src1, src2);
9662 %}
9663 ins_pipe( ialu_regI_regI );
9664 %}
9666 instruct subI_Reg_immI16_sub(mRegI dst, mRegI src1, immI16_sub src2) %{
9667 match(Set dst (SubI src1 src2));
9668 ins_cost(80);
9670 format %{ "sub $dst, $src1, $src2 #@subI_Reg_immI16_sub" %}
9671 ins_encode %{
9672 Register dst = $dst$$Register;
9673 Register src1 = $src1$$Register;
9674 __ addiu32(dst, src1, -1 * $src2$$constant);
9675 %}
9676 ins_pipe( ialu_regI_regI );
9677 %}
9679 instruct negI_Reg(mRegI dst, immI0 zero, mRegI src) %{
9680 match(Set dst (SubI zero src));
9681 ins_cost(80);
9683 format %{ "neg $dst, $src #@negI_Reg" %}
9684 ins_encode %{
9685 Register dst = $dst$$Register;
9686 Register src = $src$$Register;
9687 __ subu32(dst, R0, src);
9688 %}
9689 ins_pipe( ialu_regI_regI );
9690 %}
9692 instruct negL_Reg(mRegL dst, immL0 zero, mRegL src) %{
9693 match(Set dst (SubL zero src));
9694 ins_cost(80);
9696 format %{ "neg $dst, $src #@negL_Reg" %}
9697 ins_encode %{
9698 Register dst = $dst$$Register;
9699 Register src = $src$$Register;
9700 __ subu(dst, R0, src);
9701 %}
9702 ins_pipe( ialu_regI_regI );
9703 %}
9705 instruct subL_Reg_immL16_sub(mRegL dst, mRegL src1, immL16_sub src2) %{
9706 match(Set dst (SubL src1 src2));
9707 ins_cost(80);
9709 format %{ "sub $dst, $src1, $src2 #@subL_Reg_immL16_sub" %}
9710 ins_encode %{
9711 Register dst = $dst$$Register;
9712 Register src1 = $src1$$Register;
9713 __ daddiu(dst, src1, -1 * $src2$$constant);
9714 %}
9715 ins_pipe( ialu_regI_regI );
9716 %}
9718 // Subtract Long Register with Register.
9719 instruct subL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9720 match(Set dst (SubL src1 src2));
9721 ins_cost(100);
9722 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_Reg" %}
9723 ins_encode %{
9724 Register dst = as_Register($dst$$reg);
9725 Register src1 = as_Register($src1$$reg);
9726 Register src2 = as_Register($src2$$reg);
9728 __ subu(dst, src1, src2);
9729 %}
9730 ins_pipe( ialu_regL_regL );
9731 %}
9733 instruct subL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9734 match(Set dst (SubL src1 (ConvI2L src2)));
9735 ins_cost(100);
9736 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_RegI2L" %}
9737 ins_encode %{
9738 Register dst = as_Register($dst$$reg);
9739 Register src1 = as_Register($src1$$reg);
9740 Register src2 = as_Register($src2$$reg);
9742 __ subu(dst, src1, src2);
9743 %}
9744 ins_pipe( ialu_regL_regL );
9745 %}
9747 instruct subL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9748 match(Set dst (SubL (ConvI2L src1) src2));
9749 ins_cost(200);
9750 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_Reg" %}
9751 ins_encode %{
9752 Register dst = as_Register($dst$$reg);
9753 Register src1 = as_Register($src1$$reg);
9754 Register src2 = as_Register($src2$$reg);
9756 __ subu(dst, src1, src2);
9757 %}
9758 ins_pipe( ialu_regL_regL );
9759 %}
9761 instruct subL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9762 match(Set dst (SubL (ConvI2L src1) (ConvI2L src2)));
9763 ins_cost(200);
9764 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_RegI2L" %}
9765 ins_encode %{
9766 Register dst = as_Register($dst$$reg);
9767 Register src1 = as_Register($src1$$reg);
9768 Register src2 = as_Register($src2$$reg);
9770 __ subu(dst, src1, src2);
9771 %}
9772 ins_pipe( ialu_regL_regL );
9773 %}
9775 // Integer MOD with Register
9776 instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9777 match(Set dst (ModI src1 src2));
9778 ins_cost(300);
9779 format %{ "modi $dst, $src1, $src2 @ modI_Reg_Reg" %}
9780 ins_encode %{
9781 Register dst = $dst$$Register;
9782 Register src1 = $src1$$Register;
9783 Register src2 = $src2$$Register;
9785 //if (UseLoongsonISA) {
9786 if (0) {
9787 // 2016.08.10
9788 // Experiments show that gsmod is slower that div+mfhi.
9789 // So I just disable it here.
9790 __ gsmod(dst, src1, src2);
9791 } else {
9792 __ div(src1, src2);
9793 __ mfhi(dst);
9794 }
9795 %}
9797 //ins_pipe( ialu_mod );
9798 ins_pipe( ialu_regI_regI );
9799 %}
9801 instruct modL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
9802 match(Set dst (ModL src1 src2));
9803 format %{ "modL $dst, $src1, $src2 @modL_reg_reg" %}
9805 ins_encode %{
9806 Register dst = as_Register($dst$$reg);
9807 Register op1 = as_Register($src1$$reg);
9808 Register op2 = as_Register($src2$$reg);
9810 if (UseLoongsonISA) {
9811 __ gsdmod(dst, op1, op2);
9812 } else {
9813 __ ddiv(op1, op2);
9814 __ mfhi(dst);
9815 }
9816 %}
9817 ins_pipe( pipe_slow );
9818 %}
9820 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9821 match(Set dst (MulI src1 src2));
9823 ins_cost(300);
9824 format %{ "mul $dst, $src1, $src2 @ mulI_Reg_Reg" %}
9825 ins_encode %{
9826 Register src1 = $src1$$Register;
9827 Register src2 = $src2$$Register;
9828 Register dst = $dst$$Register;
9830 __ mul(dst, src1, src2);
9831 %}
9832 ins_pipe( ialu_mult );
9833 %}
9835 instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{
9836 match(Set dst (AddI (MulI src1 src2) src3));
9838 ins_cost(999);
9839 format %{ "madd $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %}
9840 ins_encode %{
9841 Register src1 = $src1$$Register;
9842 Register src2 = $src2$$Register;
9843 Register src3 = $src3$$Register;
9844 Register dst = $dst$$Register;
9846 __ mtlo(src3);
9847 __ madd(src1, src2);
9848 __ mflo(dst);
9849 %}
9850 ins_pipe( ialu_mult );
9851 %}
9853 instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9854 match(Set dst (DivI src1 src2));
9856 ins_cost(300);
9857 format %{ "div $dst, $src1, $src2 @ divI_Reg_Reg" %}
9858 ins_encode %{
9859 Register src1 = $src1$$Register;
9860 Register src2 = $src2$$Register;
9861 Register dst = $dst$$Register;
9863 /* 2012/4/21 Jin: In MIPS, div does not cause exception.
9864 We must trap an exception manually. */
9865 __ teq(R0, src2, 0x7);
9867 if (UseLoongsonISA) {
9868 __ gsdiv(dst, src1, src2);
9869 } else {
9870 __ div(src1, src2);
9872 __ nop();
9873 __ nop();
9874 __ mflo(dst);
9875 }
9876 %}
9877 ins_pipe( ialu_mod );
9878 %}
9880 instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{
9881 match(Set dst (DivF src1 src2));
9883 ins_cost(300);
9884 format %{ "divF $dst, $src1, $src2 @ divF_Reg_Reg" %}
9885 ins_encode %{
9886 FloatRegister src1 = $src1$$FloatRegister;
9887 FloatRegister src2 = $src2$$FloatRegister;
9888 FloatRegister dst = $dst$$FloatRegister;
9890 /* Here do we need to trap an exception manually ? */
9891 __ div_s(dst, src1, src2);
9892 %}
9893 ins_pipe( pipe_slow );
9894 %}
9896 instruct divD_Reg_Reg(regD dst, regD src1, regD src2) %{
9897 match(Set dst (DivD src1 src2));
9899 ins_cost(300);
9900 format %{ "divD $dst, $src1, $src2 @ divD_Reg_Reg" %}
9901 ins_encode %{
9902 FloatRegister src1 = $src1$$FloatRegister;
9903 FloatRegister src2 = $src2$$FloatRegister;
9904 FloatRegister dst = $dst$$FloatRegister;
9906 /* Here do we need to trap an exception manually ? */
9907 __ div_d(dst, src1, src2);
9908 %}
9909 ins_pipe( pipe_slow );
9910 %}
9912 instruct mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
9913 match(Set dst (MulL src1 src2));
9914 format %{ "mulL $dst, $src1, $src2 @mulL_reg_reg" %}
9915 ins_encode %{
9916 Register dst = as_Register($dst$$reg);
9917 Register op1 = as_Register($src1$$reg);
9918 Register op2 = as_Register($src2$$reg);
9920 if (UseLoongsonISA) {
9921 __ gsdmult(dst, op1, op2);
9922 } else {
9923 __ dmult(op1, op2);
9924 __ mflo(dst);
9925 }
9926 %}
9927 ins_pipe( pipe_slow );
9928 %}
9930 instruct mulL_reg_regI2L(mRegL dst, mRegL src1, mRegI src2) %{
9931 match(Set dst (MulL src1 (ConvI2L src2)));
9932 format %{ "mulL $dst, $src1, $src2 @mulL_reg_regI2L" %}
9933 ins_encode %{
9934 Register dst = as_Register($dst$$reg);
9935 Register op1 = as_Register($src1$$reg);
9936 Register op2 = as_Register($src2$$reg);
9938 if (UseLoongsonISA) {
9939 __ gsdmult(dst, op1, op2);
9940 } else {
9941 __ dmult(op1, op2);
9942 __ mflo(dst);
9943 }
9944 %}
9945 ins_pipe( pipe_slow );
9946 %}
9948 instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
9949 match(Set dst (DivL src1 src2));
9950 format %{ "divL $dst, $src1, $src2 @divL_reg_reg" %}
9952 ins_encode %{
9953 Register dst = as_Register($dst$$reg);
9954 Register op1 = as_Register($src1$$reg);
9955 Register op2 = as_Register($src2$$reg);
9957 if (UseLoongsonISA) {
9958 __ gsddiv(dst, op1, op2);
9959 } else {
9960 __ ddiv(op1, op2);
9961 __ mflo(dst);
9962 }
9963 %}
9964 ins_pipe( pipe_slow );
9965 %}
9967 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
9968 match(Set dst (AddF src1 src2));
9969 format %{ "AddF $dst, $src1, $src2 @addF_reg_reg" %}
9970 ins_encode %{
9971 FloatRegister src1 = as_FloatRegister($src1$$reg);
9972 FloatRegister src2 = as_FloatRegister($src2$$reg);
9973 FloatRegister dst = as_FloatRegister($dst$$reg);
9975 __ add_s(dst, src1, src2);
9976 %}
9977 ins_pipe( fpu_regF_regF );
9978 %}
9980 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
9981 match(Set dst (SubF src1 src2));
9982 format %{ "SubF $dst, $src1, $src2 @subF_reg_reg" %}
9983 ins_encode %{
9984 FloatRegister src1 = as_FloatRegister($src1$$reg);
9985 FloatRegister src2 = as_FloatRegister($src2$$reg);
9986 FloatRegister dst = as_FloatRegister($dst$$reg);
9988 __ sub_s(dst, src1, src2);
9989 %}
9990 ins_pipe( fpu_regF_regF );
9991 %}
9992 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
9993 match(Set dst (AddD src1 src2));
9994 format %{ "AddD $dst, $src1, $src2 @addD_reg_reg" %}
9995 ins_encode %{
9996 FloatRegister src1 = as_FloatRegister($src1$$reg);
9997 FloatRegister src2 = as_FloatRegister($src2$$reg);
9998 FloatRegister dst = as_FloatRegister($dst$$reg);
10000 __ add_d(dst, src1, src2);
10001 %}
10002 ins_pipe( fpu_regF_regF );
10003 %}
10005 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
10006 match(Set dst (SubD src1 src2));
10007 format %{ "SubD $dst, $src1, $src2 @subD_reg_reg" %}
10008 ins_encode %{
10009 FloatRegister src1 = as_FloatRegister($src1$$reg);
10010 FloatRegister src2 = as_FloatRegister($src2$$reg);
10011 FloatRegister dst = as_FloatRegister($dst$$reg);
10013 __ sub_d(dst, src1, src2);
10014 %}
10015 ins_pipe( fpu_regF_regF );
10016 %}
10018 instruct negF_reg(regF dst, regF src) %{
10019 match(Set dst (NegF src));
10020 format %{ "negF $dst, $src @negF_reg" %}
10021 ins_encode %{
10022 FloatRegister src = as_FloatRegister($src$$reg);
10023 FloatRegister dst = as_FloatRegister($dst$$reg);
10025 __ neg_s(dst, src);
10026 %}
10027 ins_pipe( fpu_regF_regF );
10028 %}
10030 instruct negD_reg(regD dst, regD src) %{
10031 match(Set dst (NegD src));
10032 format %{ "negD $dst, $src @negD_reg" %}
10033 ins_encode %{
10034 FloatRegister src = as_FloatRegister($src$$reg);
10035 FloatRegister dst = as_FloatRegister($dst$$reg);
10037 __ neg_d(dst, src);
10038 %}
10039 ins_pipe( fpu_regF_regF );
10040 %}
10043 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
10044 match(Set dst (MulF src1 src2));
10045 format %{ "MULF $dst, $src1, $src2 @mulF_reg_reg" %}
10046 ins_encode %{
10047 FloatRegister src1 = $src1$$FloatRegister;
10048 FloatRegister src2 = $src2$$FloatRegister;
10049 FloatRegister dst = $dst$$FloatRegister;
10051 __ mul_s(dst, src1, src2);
10052 %}
10053 ins_pipe( fpu_regF_regF );
10054 %}
10056 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10057 match(Set dst (AddF (MulF src1 src2) src3));
10058 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10059 ins_cost(44444);
10060 format %{ "maddF $dst, $src1, $src2, $src3 @maddF_reg_reg" %}
10061 ins_encode %{
10062 FloatRegister src1 = $src1$$FloatRegister;
10063 FloatRegister src2 = $src2$$FloatRegister;
10064 FloatRegister src3 = $src3$$FloatRegister;
10065 FloatRegister dst = $dst$$FloatRegister;
10067 __ madd_s(dst, src1, src2, src3);
10068 %}
10069 ins_pipe( fpu_regF_regF );
10070 %}
10072 // Mul two double precision floating piont number
10073 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
10074 match(Set dst (MulD src1 src2));
10075 format %{ "MULD $dst, $src1, $src2 @mulD_reg_reg" %}
10076 ins_encode %{
10077 FloatRegister src1 = $src1$$FloatRegister;
10078 FloatRegister src2 = $src2$$FloatRegister;
10079 FloatRegister dst = $dst$$FloatRegister;
10081 __ mul_d(dst, src1, src2);
10082 %}
10083 ins_pipe( fpu_regF_regF );
10084 %}
10086 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10087 match(Set dst (AddD (MulD src1 src2) src3));
10088 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10089 ins_cost(44444);
10090 format %{ "maddD $dst, $src1, $src2, $src3 @maddD_reg_reg" %}
10091 ins_encode %{
10092 FloatRegister src1 = $src1$$FloatRegister;
10093 FloatRegister src2 = $src2$$FloatRegister;
10094 FloatRegister src3 = $src3$$FloatRegister;
10095 FloatRegister dst = $dst$$FloatRegister;
10097 __ madd_d(dst, src1, src2, src3);
10098 %}
10099 ins_pipe( fpu_regF_regF );
10100 %}
10102 instruct absF_reg(regF dst, regF src) %{
10103 match(Set dst (AbsF src));
10104 ins_cost(100);
10105 format %{ "absF $dst, $src @absF_reg" %}
10106 ins_encode %{
10107 FloatRegister src = as_FloatRegister($src$$reg);
10108 FloatRegister dst = as_FloatRegister($dst$$reg);
10110 __ abs_s(dst, src);
10111 %}
10112 ins_pipe( fpu_regF_regF );
10113 %}
10116 // intrinsics for math_native.
10117 // AbsD SqrtD CosD SinD TanD LogD Log10D
10119 instruct absD_reg(regD dst, regD src) %{
10120 match(Set dst (AbsD src));
10121 ins_cost(100);
10122 format %{ "absD $dst, $src @absD_reg" %}
10123 ins_encode %{
10124 FloatRegister src = as_FloatRegister($src$$reg);
10125 FloatRegister dst = as_FloatRegister($dst$$reg);
10127 __ abs_d(dst, src);
10128 %}
10129 ins_pipe( fpu_regF_regF );
10130 %}
10132 instruct sqrtD_reg(regD dst, regD src) %{
10133 match(Set dst (SqrtD src));
10134 ins_cost(100);
10135 format %{ "SqrtD $dst, $src @sqrtD_reg" %}
10136 ins_encode %{
10137 FloatRegister src = as_FloatRegister($src$$reg);
10138 FloatRegister dst = as_FloatRegister($dst$$reg);
10140 __ sqrt_d(dst, src);
10141 %}
10142 ins_pipe( fpu_regF_regF );
10143 %}
10145 instruct sqrtF_reg(regF dst, regF src) %{
10146 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10147 ins_cost(100);
10148 format %{ "SqrtF $dst, $src @sqrtF_reg" %}
10149 ins_encode %{
10150 FloatRegister src = as_FloatRegister($src$$reg);
10151 FloatRegister dst = as_FloatRegister($dst$$reg);
10153 __ sqrt_s(dst, src);
10154 %}
10155 ins_pipe( fpu_regF_regF );
10156 %}
10157 //----------------------------------Logical Instructions----------------------
10158 //__________________________________Integer Logical Instructions-------------
10160 //And Instuctions
10161 // And Register with Immediate
10162 instruct andI_Reg_immI(mRegI dst, mRegI src1, immI src2) %{
10163 match(Set dst (AndI src1 src2));
10165 format %{ "and $dst, $src1, $src2 #@andI_Reg_immI" %}
10166 ins_encode %{
10167 Register dst = $dst$$Register;
10168 Register src = $src1$$Register;
10169 int val = $src2$$constant;
10171 __ move(AT, val);
10172 __ andr(dst, src, AT);
10173 %}
10174 ins_pipe( ialu_regI_regI );
10175 %}
10177 instruct andI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10178 match(Set dst (AndI src1 src2));
10179 ins_cost(60);
10181 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm_0_65535" %}
10182 ins_encode %{
10183 Register dst = $dst$$Register;
10184 Register src = $src1$$Register;
10185 int val = $src2$$constant;
10187 __ andi(dst, src, val);
10188 %}
10189 ins_pipe( ialu_regI_regI );
10190 %}
10192 instruct andI_Reg_immI_nonneg_mask(mRegI dst, mRegI src1, immI_nonneg_mask mask) %{
10193 match(Set dst (AndI src1 mask));
10194 ins_cost(60);
10196 format %{ "and $dst, $src1, $mask #@andI_Reg_immI_nonneg_mask" %}
10197 ins_encode %{
10198 Register dst = $dst$$Register;
10199 Register src = $src1$$Register;
10200 int size = Assembler::is_int_mask($mask$$constant);
10202 __ ext(dst, src, 0, size);
10203 %}
10204 ins_pipe( ialu_regI_regI );
10205 %}
10207 instruct andL_Reg_immL_nonneg_mask(mRegL dst, mRegL src1, immL_nonneg_mask mask) %{
10208 match(Set dst (AndL src1 mask));
10209 ins_cost(60);
10211 format %{ "and $dst, $src1, $mask #@andL_Reg_immL_nonneg_mask" %}
10212 ins_encode %{
10213 Register dst = $dst$$Register;
10214 Register src = $src1$$Register;
10215 int size = Assembler::is_jlong_mask($mask$$constant);
10217 __ dext(dst, src, 0, size);
10218 %}
10219 ins_pipe( ialu_regI_regI );
10220 %}
10222 instruct xorI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10223 match(Set dst (XorI src1 src2));
10224 ins_cost(60);
10226 format %{ "xori $dst, $src1, $src2 #@xorI_Reg_imm_0_65535" %}
10227 ins_encode %{
10228 Register dst = $dst$$Register;
10229 Register src = $src1$$Register;
10230 int val = $src2$$constant;
10232 __ xori(dst, src, val);
10233 %}
10234 ins_pipe( ialu_regI_regI );
10235 %}
10237 instruct xorI_Reg_immI_M1(mRegI dst, mRegI src1, immI_M1 M1) %{
10238 match(Set dst (XorI src1 M1));
10239 predicate(UseLoongsonISA && Use3A2000);
10240 ins_cost(60);
10242 format %{ "xor $dst, $src1, $M1 #@xorI_Reg_immI_M1" %}
10243 ins_encode %{
10244 Register dst = $dst$$Register;
10245 Register src = $src1$$Register;
10247 __ gsorn(dst, R0, src);
10248 %}
10249 ins_pipe( ialu_regI_regI );
10250 %}
10252 instruct xorL2I_Reg_immI_M1(mRegI dst, mRegL src1, immI_M1 M1) %{
10253 match(Set dst (XorI (ConvL2I src1) M1));
10254 predicate(UseLoongsonISA && Use3A2000);
10255 ins_cost(60);
10257 format %{ "xor $dst, $src1, $M1 #@xorL2I_Reg_immI_M1" %}
10258 ins_encode %{
10259 Register dst = $dst$$Register;
10260 Register src = $src1$$Register;
10262 __ gsorn(dst, R0, src);
10263 %}
10264 ins_pipe( ialu_regI_regI );
10265 %}
10267 instruct xorL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10268 match(Set dst (XorL src1 src2));
10269 ins_cost(60);
10271 format %{ "xori $dst, $src1, $src2 #@xorL_Reg_imm_0_65535" %}
10272 ins_encode %{
10273 Register dst = $dst$$Register;
10274 Register src = $src1$$Register;
10275 int val = $src2$$constant;
10277 __ xori(dst, src, val);
10278 %}
10279 ins_pipe( ialu_regI_regI );
10280 %}
10282 /*
10283 instruct xorL_Reg_immL_M1(mRegL dst, mRegL src1, immL_M1 M1) %{
10284 match(Set dst (XorL src1 M1));
10285 predicate(UseLoongsonISA);
10286 ins_cost(60);
10288 format %{ "xor $dst, $src1, $M1 #@xorL_Reg_immL_M1" %}
10289 ins_encode %{
10290 Register dst = $dst$$Register;
10291 Register src = $src1$$Register;
10293 __ gsorn(dst, R0, src);
10294 %}
10295 ins_pipe( ialu_regI_regI );
10296 %}
10297 */
10299 instruct lbu_and_lmask(mRegI dst, memory mem, immI_255 mask) %{
10300 match(Set dst (AndI mask (LoadB mem)));
10301 ins_cost(60);
10303 format %{ "lhu $dst, $mem #@lbu_and_lmask" %}
10304 ins_encode(load_UB_enc(dst, mem));
10305 ins_pipe( ialu_loadI );
10306 %}
10308 instruct lbu_and_rmask(mRegI dst, memory mem, immI_255 mask) %{
10309 match(Set dst (AndI (LoadB mem) mask));
10310 ins_cost(60);
10312 format %{ "lhu $dst, $mem #@lbu_and_rmask" %}
10313 ins_encode(load_UB_enc(dst, mem));
10314 ins_pipe( ialu_loadI );
10315 %}
10317 instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10318 match(Set dst (AndI src1 src2));
10320 format %{ "and $dst, $src1, $src2 #@andI_Reg_Reg" %}
10321 ins_encode %{
10322 Register dst = $dst$$Register;
10323 Register src1 = $src1$$Register;
10324 Register src2 = $src2$$Register;
10325 __ andr(dst, src1, src2);
10326 %}
10327 ins_pipe( ialu_regI_regI );
10328 %}
10330 instruct andnI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10331 match(Set dst (AndI src1 (XorI src2 M1)));
10332 predicate(UseLoongsonISA && Use3A2000);
10334 format %{ "andn $dst, $src1, $src2 #@andnI_Reg_nReg" %}
10335 ins_encode %{
10336 Register dst = $dst$$Register;
10337 Register src1 = $src1$$Register;
10338 Register src2 = $src2$$Register;
10340 __ gsandn(dst, src1, src2);
10341 %}
10342 ins_pipe( ialu_regI_regI );
10343 %}
10345 instruct ornI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10346 match(Set dst (OrI src1 (XorI src2 M1)));
10347 predicate(UseLoongsonISA && Use3A2000);
10349 format %{ "orn $dst, $src1, $src2 #@ornI_Reg_nReg" %}
10350 ins_encode %{
10351 Register dst = $dst$$Register;
10352 Register src1 = $src1$$Register;
10353 Register src2 = $src2$$Register;
10355 __ gsorn(dst, src1, src2);
10356 %}
10357 ins_pipe( ialu_regI_regI );
10358 %}
10360 instruct andnI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10361 match(Set dst (AndI (XorI src1 M1) src2));
10362 predicate(UseLoongsonISA && Use3A2000);
10364 format %{ "andn $dst, $src2, $src1 #@andnI_nReg_Reg" %}
10365 ins_encode %{
10366 Register dst = $dst$$Register;
10367 Register src1 = $src1$$Register;
10368 Register src2 = $src2$$Register;
10370 __ gsandn(dst, src2, src1);
10371 %}
10372 ins_pipe( ialu_regI_regI );
10373 %}
10375 instruct ornI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10376 match(Set dst (OrI (XorI src1 M1) src2));
10377 predicate(UseLoongsonISA && Use3A2000);
10379 format %{ "orn $dst, $src2, $src1 #@ornI_nReg_Reg" %}
10380 ins_encode %{
10381 Register dst = $dst$$Register;
10382 Register src1 = $src1$$Register;
10383 Register src2 = $src2$$Register;
10385 __ gsorn(dst, src2, src1);
10386 %}
10387 ins_pipe( ialu_regI_regI );
10388 %}
10390 // And Long Register with Register
10391 instruct andL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10392 match(Set dst (AndL src1 src2));
10393 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg\n\t" %}
10394 ins_encode %{
10395 Register dst_reg = as_Register($dst$$reg);
10396 Register src1_reg = as_Register($src1$$reg);
10397 Register src2_reg = as_Register($src2$$reg);
10399 __ andr(dst_reg, src1_reg, src2_reg);
10400 %}
10401 ins_pipe( ialu_regL_regL );
10402 %}
10404 instruct andL_Reg_Reg_convI2L(mRegL dst, mRegL src1, mRegI src2) %{
10405 match(Set dst (AndL src1 (ConvI2L src2)));
10406 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg_convI2L\n\t" %}
10407 ins_encode %{
10408 Register dst_reg = as_Register($dst$$reg);
10409 Register src1_reg = as_Register($src1$$reg);
10410 Register src2_reg = as_Register($src2$$reg);
10412 __ andr(dst_reg, src1_reg, src2_reg);
10413 %}
10414 ins_pipe( ialu_regL_regL );
10415 %}
10417 instruct andL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10418 match(Set dst (AndL src1 src2));
10419 ins_cost(60);
10421 format %{ "and $dst, $src1, $src2 #@andL_Reg_imm_0_65535" %}
10422 ins_encode %{
10423 Register dst = $dst$$Register;
10424 Register src = $src1$$Register;
10425 long val = $src2$$constant;
10427 __ andi(dst, src, val);
10428 %}
10429 ins_pipe( ialu_regI_regI );
10430 %}
10432 instruct andL2I_Reg_imm_0_65535(mRegI dst, mRegL src1, immL_0_65535 src2) %{
10433 match(Set dst (ConvL2I (AndL src1 src2)));
10434 ins_cost(60);
10436 format %{ "and $dst, $src1, $src2 #@andL2I_Reg_imm_0_65535" %}
10437 ins_encode %{
10438 Register dst = $dst$$Register;
10439 Register src = $src1$$Register;
10440 long val = $src2$$constant;
10442 __ andi(dst, src, val);
10443 %}
10444 ins_pipe( ialu_regI_regI );
10445 %}
10447 /*
10448 instruct andnL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10449 match(Set dst (AndL src1 (XorL src2 M1)));
10450 predicate(UseLoongsonISA);
10452 format %{ "andn $dst, $src1, $src2 #@andnL_Reg_nReg" %}
10453 ins_encode %{
10454 Register dst = $dst$$Register;
10455 Register src1 = $src1$$Register;
10456 Register src2 = $src2$$Register;
10458 __ gsandn(dst, src1, src2);
10459 %}
10460 ins_pipe( ialu_regI_regI );
10461 %}
10462 */
10464 /*
10465 instruct ornL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10466 match(Set dst (OrL src1 (XorL src2 M1)));
10467 predicate(UseLoongsonISA);
10469 format %{ "orn $dst, $src1, $src2 #@ornL_Reg_nReg" %}
10470 ins_encode %{
10471 Register dst = $dst$$Register;
10472 Register src1 = $src1$$Register;
10473 Register src2 = $src2$$Register;
10475 __ gsorn(dst, src1, src2);
10476 %}
10477 ins_pipe( ialu_regI_regI );
10478 %}
10479 */
10481 /*
10482 instruct andnL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10483 match(Set dst (AndL (XorL src1 M1) src2));
10484 predicate(UseLoongsonISA);
10486 format %{ "andn $dst, $src2, $src1 #@andnL_nReg_Reg" %}
10487 ins_encode %{
10488 Register dst = $dst$$Register;
10489 Register src1 = $src1$$Register;
10490 Register src2 = $src2$$Register;
10492 __ gsandn(dst, src2, src1);
10493 %}
10494 ins_pipe( ialu_regI_regI );
10495 %}
10496 */
10498 /*
10499 instruct ornL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10500 match(Set dst (OrL (XorL src1 M1) src2));
10501 predicate(UseLoongsonISA);
10503 format %{ "orn $dst, $src2, $src1 #@ornL_nReg_Reg" %}
10504 ins_encode %{
10505 Register dst = $dst$$Register;
10506 Register src1 = $src1$$Register;
10507 Register src2 = $src2$$Register;
10509 __ gsorn(dst, src2, src1);
10510 %}
10511 ins_pipe( ialu_regI_regI );
10512 %}
10513 */
10515 instruct andL_Reg_immL_M8(mRegL dst, immL_M8 M8) %{
10516 match(Set dst (AndL dst M8));
10517 ins_cost(60);
10519 format %{ "and $dst, $dst, $M8 #@andL_Reg_immL_M8" %}
10520 ins_encode %{
10521 Register dst = $dst$$Register;
10523 __ dins(dst, R0, 0, 3);
10524 %}
10525 ins_pipe( ialu_regI_regI );
10526 %}
10528 instruct andL_Reg_immL_M5(mRegL dst, immL_M5 M5) %{
10529 match(Set dst (AndL dst M5));
10530 ins_cost(60);
10532 format %{ "and $dst, $dst, $M5 #@andL_Reg_immL_M5" %}
10533 ins_encode %{
10534 Register dst = $dst$$Register;
10536 __ dins(dst, R0, 2, 1);
10537 %}
10538 ins_pipe( ialu_regI_regI );
10539 %}
10541 instruct andL_Reg_immL_M7(mRegL dst, immL_M7 M7) %{
10542 match(Set dst (AndL dst M7));
10543 ins_cost(60);
10545 format %{ "and $dst, $dst, $M7 #@andL_Reg_immL_M7" %}
10546 ins_encode %{
10547 Register dst = $dst$$Register;
10549 __ dins(dst, R0, 1, 2);
10550 %}
10551 ins_pipe( ialu_regI_regI );
10552 %}
10554 instruct andL_Reg_immL_M4(mRegL dst, immL_M4 M4) %{
10555 match(Set dst (AndL dst M4));
10556 ins_cost(60);
10558 format %{ "and $dst, $dst, $M4 #@andL_Reg_immL_M4" %}
10559 ins_encode %{
10560 Register dst = $dst$$Register;
10562 __ dins(dst, R0, 0, 2);
10563 %}
10564 ins_pipe( ialu_regI_regI );
10565 %}
10567 instruct andL_Reg_immL_M121(mRegL dst, immL_M121 M121) %{
10568 match(Set dst (AndL dst M121));
10569 ins_cost(60);
10571 format %{ "and $dst, $dst, $M121 #@andL_Reg_immL_M121" %}
10572 ins_encode %{
10573 Register dst = $dst$$Register;
10575 __ dins(dst, R0, 3, 4);
10576 %}
10577 ins_pipe( ialu_regI_regI );
10578 %}
10580 // Or Long Register with Register
10581 instruct orL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10582 match(Set dst (OrL src1 src2));
10583 format %{ "OR $dst, $src1, $src2 @ orL_Reg_Reg\t" %}
10584 ins_encode %{
10585 Register dst_reg = $dst$$Register;
10586 Register src1_reg = $src1$$Register;
10587 Register src2_reg = $src2$$Register;
10589 __ orr(dst_reg, src1_reg, src2_reg);
10590 %}
10591 ins_pipe( ialu_regL_regL );
10592 %}
10594 instruct orL_Reg_P2XReg(mRegL dst, mRegP src1, mRegL src2) %{
10595 match(Set dst (OrL (CastP2X src1) src2));
10596 format %{ "OR $dst, $src1, $src2 @ orL_Reg_P2XReg\t" %}
10597 ins_encode %{
10598 Register dst_reg = $dst$$Register;
10599 Register src1_reg = $src1$$Register;
10600 Register src2_reg = $src2$$Register;
10602 __ orr(dst_reg, src1_reg, src2_reg);
10603 %}
10604 ins_pipe( ialu_regL_regL );
10605 %}
10607 // Xor Long Register with Register
10608 instruct xorL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10609 match(Set dst (XorL src1 src2));
10610 format %{ "XOR $dst, $src1, $src2 @ xorL_Reg_Reg\t" %}
10611 ins_encode %{
10612 Register dst_reg = as_Register($dst$$reg);
10613 Register src1_reg = as_Register($src1$$reg);
10614 Register src2_reg = as_Register($src2$$reg);
10616 __ xorr(dst_reg, src1_reg, src2_reg);
10617 %}
10618 ins_pipe( ialu_regL_regL );
10619 %}
10621 // Shift Left by 8-bit immediate
10622 instruct salI_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
10623 match(Set dst (LShiftI src shift));
10625 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm" %}
10626 ins_encode %{
10627 Register src = $src$$Register;
10628 Register dst = $dst$$Register;
10629 int shamt = $shift$$constant;
10631 __ sll(dst, src, shamt);
10632 %}
10633 ins_pipe( ialu_regI_regI );
10634 %}
10636 instruct salL2I_Reg_imm(mRegI dst, mRegL src, immI8 shift) %{
10637 match(Set dst (LShiftI (ConvL2I src) shift));
10639 format %{ "SHL $dst, $src, $shift #@salL2I_Reg_imm" %}
10640 ins_encode %{
10641 Register src = $src$$Register;
10642 Register dst = $dst$$Register;
10643 int shamt = $shift$$constant;
10645 __ sll(dst, src, shamt);
10646 %}
10647 ins_pipe( ialu_regI_regI );
10648 %}
10650 instruct salI_Reg_imm_and_M65536(mRegI dst, mRegI src, immI_16 shift, immI_M65536 mask) %{
10651 match(Set dst (AndI (LShiftI src shift) mask));
10653 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm_and_M65536" %}
10654 ins_encode %{
10655 Register src = $src$$Register;
10656 Register dst = $dst$$Register;
10658 __ sll(dst, src, 16);
10659 %}
10660 ins_pipe( ialu_regI_regI );
10661 %}
10663 instruct land7_2_s(mRegI dst, mRegL src, immL7 seven, immI_16 sixteen)
10664 %{
10665 match(Set dst (RShiftI (LShiftI (ConvL2I (AndL src seven)) sixteen) sixteen));
10667 format %{ "andi $dst, $src, 7\t# @land7_2_s" %}
10668 ins_encode %{
10669 Register src = $src$$Register;
10670 Register dst = $dst$$Register;
10672 __ andi(dst, src, 7);
10673 %}
10674 ins_pipe(ialu_regI_regI);
10675 %}
10677 instruct ori2s(mRegI dst, mRegI src1, immI_0_32767 src2, immI_16 sixteen)
10678 %{
10679 match(Set dst (RShiftI (LShiftI (OrI src1 src2) sixteen) sixteen));
10681 format %{ "ori $dst, $src1, $src2\t# @ori2s" %}
10682 ins_encode %{
10683 Register src = $src1$$Register;
10684 int val = $src2$$constant;
10685 Register dst = $dst$$Register;
10687 __ ori(dst, src, val);
10688 %}
10689 ins_pipe(ialu_regI_regI);
10690 %}
10692 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
10693 // This idiom is used by the compiler the i2s bytecode.
10694 instruct i2s(mRegI dst, mRegI src, immI_16 sixteen)
10695 %{
10696 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
10698 format %{ "i2s $dst, $src\t# @i2s" %}
10699 ins_encode %{
10700 Register src = $src$$Register;
10701 Register dst = $dst$$Register;
10703 __ seh(dst, src);
10704 %}
10705 ins_pipe(ialu_regI_regI);
10706 %}
10708 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
10709 // This idiom is used by the compiler for the i2b bytecode.
10710 instruct i2b(mRegI dst, mRegI src, immI_24 twentyfour)
10711 %{
10712 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
10714 format %{ "i2b $dst, $src\t# @i2b" %}
10715 ins_encode %{
10716 Register src = $src$$Register;
10717 Register dst = $dst$$Register;
10719 __ seb(dst, src);
10720 %}
10721 ins_pipe(ialu_regI_regI);
10722 %}
10725 instruct salI_RegL2I_imm(mRegI dst, mRegL src, immI8 shift) %{
10726 match(Set dst (LShiftI (ConvL2I src) shift));
10728 format %{ "SHL $dst, $src, $shift #@salI_RegL2I_imm" %}
10729 ins_encode %{
10730 Register src = $src$$Register;
10731 Register dst = $dst$$Register;
10732 int shamt = $shift$$constant;
10734 __ sll(dst, src, shamt);
10735 %}
10736 ins_pipe( ialu_regI_regI );
10737 %}
10739 // Shift Left by 8-bit immediate
10740 instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
10741 match(Set dst (LShiftI src shift));
10743 format %{ "SHL $dst, $src, $shift #@salI_Reg_Reg" %}
10744 ins_encode %{
10745 Register src = $src$$Register;
10746 Register dst = $dst$$Register;
10747 Register shamt = $shift$$Register;
10748 __ sllv(dst, src, shamt);
10749 %}
10750 ins_pipe( ialu_regI_regI );
10751 %}
10754 // Shift Left Long
10755 instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10756 //predicate(UseNewLongLShift);
10757 match(Set dst (LShiftL src shift));
10758 ins_cost(100);
10759 format %{ "salL $dst, $src, $shift @ salL_Reg_imm" %}
10760 ins_encode %{
10761 Register src_reg = as_Register($src$$reg);
10762 Register dst_reg = as_Register($dst$$reg);
10763 int shamt = $shift$$constant;
10765 if (__ is_simm(shamt, 5))
10766 __ dsll(dst_reg, src_reg, shamt);
10767 else
10768 {
10769 int sa = Assembler::low(shamt, 6);
10770 if (sa < 32) {
10771 __ dsll(dst_reg, src_reg, sa);
10772 } else {
10773 __ dsll32(dst_reg, src_reg, sa - 32);
10774 }
10775 }
10776 %}
10777 ins_pipe( ialu_regL_regL );
10778 %}
10780 instruct salL_RegI2L_imm(mRegL dst, mRegI src, immI8 shift) %{
10781 //predicate(UseNewLongLShift);
10782 match(Set dst (LShiftL (ConvI2L src) shift));
10783 ins_cost(100);
10784 format %{ "salL $dst, $src, $shift @ salL_RegI2L_imm" %}
10785 ins_encode %{
10786 Register src_reg = as_Register($src$$reg);
10787 Register dst_reg = as_Register($dst$$reg);
10788 int shamt = $shift$$constant;
10790 if (__ is_simm(shamt, 5))
10791 __ dsll(dst_reg, src_reg, shamt);
10792 else
10793 {
10794 int sa = Assembler::low(shamt, 6);
10795 if (sa < 32) {
10796 __ dsll(dst_reg, src_reg, sa);
10797 } else {
10798 __ dsll32(dst_reg, src_reg, sa - 32);
10799 }
10800 }
10801 %}
10802 ins_pipe( ialu_regL_regL );
10803 %}
10805 // Shift Left Long
10806 instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10807 //predicate(UseNewLongLShift);
10808 match(Set dst (LShiftL src shift));
10809 ins_cost(100);
10810 format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %}
10811 ins_encode %{
10812 Register src_reg = as_Register($src$$reg);
10813 Register dst_reg = as_Register($dst$$reg);
10815 __ dsllv(dst_reg, src_reg, $shift$$Register);
10816 %}
10817 ins_pipe( ialu_regL_regL );
10818 %}
10820 instruct salL_convI2L_Reg_imm(mRegL dst, mRegI src, immI8 shift) %{
10821 match(Set dst (LShiftL (ConvI2L src) shift));
10822 ins_cost(100);
10823 format %{ "salL $dst, $src, $shift @ salL_convI2L_Reg_imm" %}
10824 ins_encode %{
10825 Register src_reg = as_Register($src$$reg);
10826 Register dst_reg = as_Register($dst$$reg);
10827 int shamt = $shift$$constant;
10829 if (__ is_simm(shamt, 5)) {
10830 __ dsll(dst_reg, src_reg, shamt);
10831 } else {
10832 int sa = Assembler::low(shamt, 6);
10833 if (sa < 32) {
10834 __ dsll(dst_reg, src_reg, sa);
10835 } else {
10836 __ dsll32(dst_reg, src_reg, sa - 32);
10837 }
10838 }
10839 %}
10840 ins_pipe( ialu_regL_regL );
10841 %}
10843 // Shift Right Long
10844 instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10845 match(Set dst (RShiftL src shift));
10846 ins_cost(100);
10847 format %{ "sarL $dst, $src, $shift @ sarL_Reg_imm" %}
10848 ins_encode %{
10849 Register src_reg = as_Register($src$$reg);
10850 Register dst_reg = as_Register($dst$$reg);
10851 int shamt = ($shift$$constant & 0x3f);
10852 if (__ is_simm(shamt, 5))
10853 __ dsra(dst_reg, src_reg, shamt);
10854 else {
10855 int sa = Assembler::low(shamt, 6);
10856 if (sa < 32) {
10857 __ dsra(dst_reg, src_reg, sa);
10858 } else {
10859 __ dsra32(dst_reg, src_reg, sa - 32);
10860 }
10861 }
10862 %}
10863 ins_pipe( ialu_regL_regL );
10864 %}
10866 instruct sarL2I_Reg_immI_32_63(mRegI dst, mRegL src, immI_32_63 shift) %{
10867 match(Set dst (ConvL2I (RShiftL src shift)));
10868 ins_cost(100);
10869 format %{ "sarL $dst, $src, $shift @ sarL2I_Reg_immI_32_63" %}
10870 ins_encode %{
10871 Register src_reg = as_Register($src$$reg);
10872 Register dst_reg = as_Register($dst$$reg);
10873 int shamt = $shift$$constant;
10875 __ dsra32(dst_reg, src_reg, shamt - 32);
10876 %}
10877 ins_pipe( ialu_regL_regL );
10878 %}
10880 // Shift Right Long arithmetically
10881 instruct sarL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10882 //predicate(UseNewLongLShift);
10883 match(Set dst (RShiftL src shift));
10884 ins_cost(100);
10885 format %{ "sarL $dst, $src, $shift @ sarL_Reg_Reg" %}
10886 ins_encode %{
10887 Register src_reg = as_Register($src$$reg);
10888 Register dst_reg = as_Register($dst$$reg);
10890 __ dsrav(dst_reg, src_reg, $shift$$Register);
10891 %}
10892 ins_pipe( ialu_regL_regL );
10893 %}
10895 // Shift Right Long logically
10896 instruct slrL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10897 match(Set dst (URShiftL src shift));
10898 ins_cost(100);
10899 format %{ "slrL $dst, $src, $shift @ slrL_Reg_Reg" %}
10900 ins_encode %{
10901 Register src_reg = as_Register($src$$reg);
10902 Register dst_reg = as_Register($dst$$reg);
10904 __ dsrlv(dst_reg, src_reg, $shift$$Register);
10905 %}
10906 ins_pipe( ialu_regL_regL );
10907 %}
10909 instruct slrL_Reg_immI_0_31(mRegL dst, mRegL src, immI_0_31 shift) %{
10910 match(Set dst (URShiftL src shift));
10911 ins_cost(80);
10912 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_0_31" %}
10913 ins_encode %{
10914 Register src_reg = as_Register($src$$reg);
10915 Register dst_reg = as_Register($dst$$reg);
10916 int shamt = $shift$$constant;
10918 __ dsrl(dst_reg, src_reg, shamt);
10919 %}
10920 ins_pipe( ialu_regL_regL );
10921 %}
10923 instruct slrL_Reg_immI_0_31_and_max_int(mRegI dst, mRegL src, immI_0_31 shift, immI_MaxI max_int) %{
10924 match(Set dst (AndI (ConvL2I (URShiftL src shift)) max_int));
10925 ins_cost(80);
10926 format %{ "dext $dst, $src, $shift, 31 @ slrL_Reg_immI_0_31_and_max_int" %}
10927 ins_encode %{
10928 Register src_reg = as_Register($src$$reg);
10929 Register dst_reg = as_Register($dst$$reg);
10930 int shamt = $shift$$constant;
10932 __ dext(dst_reg, src_reg, shamt, 31);
10933 %}
10934 ins_pipe( ialu_regL_regL );
10935 %}
10937 instruct slrL_P2XReg_immI_0_31(mRegL dst, mRegP src, immI_0_31 shift) %{
10938 match(Set dst (URShiftL (CastP2X src) shift));
10939 ins_cost(80);
10940 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_0_31" %}
10941 ins_encode %{
10942 Register src_reg = as_Register($src$$reg);
10943 Register dst_reg = as_Register($dst$$reg);
10944 int shamt = $shift$$constant;
10946 __ dsrl(dst_reg, src_reg, shamt);
10947 %}
10948 ins_pipe( ialu_regL_regL );
10949 %}
10951 instruct slrL_Reg_immI_32_63(mRegL dst, mRegL src, immI_32_63 shift) %{
10952 match(Set dst (URShiftL src shift));
10953 ins_cost(80);
10954 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_32_63" %}
10955 ins_encode %{
10956 Register src_reg = as_Register($src$$reg);
10957 Register dst_reg = as_Register($dst$$reg);
10958 int shamt = $shift$$constant;
10960 __ dsrl32(dst_reg, src_reg, shamt - 32);
10961 %}
10962 ins_pipe( ialu_regL_regL );
10963 %}
10965 instruct slrL_Reg_immI_convL2I(mRegI dst, mRegL src, immI_32_63 shift) %{
10966 match(Set dst (ConvL2I (URShiftL src shift)));
10967 predicate(n->in(1)->in(2)->get_int() > 32);
10968 ins_cost(80);
10969 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_convL2I" %}
10970 ins_encode %{
10971 Register src_reg = as_Register($src$$reg);
10972 Register dst_reg = as_Register($dst$$reg);
10973 int shamt = $shift$$constant;
10975 __ dsrl32(dst_reg, src_reg, shamt - 32);
10976 %}
10977 ins_pipe( ialu_regL_regL );
10978 %}
10980 instruct slrL_P2XReg_immI_32_63(mRegL dst, mRegP src, immI_32_63 shift) %{
10981 match(Set dst (URShiftL (CastP2X src) shift));
10982 ins_cost(80);
10983 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_32_63" %}
10984 ins_encode %{
10985 Register src_reg = as_Register($src$$reg);
10986 Register dst_reg = as_Register($dst$$reg);
10987 int shamt = $shift$$constant;
10989 __ dsrl32(dst_reg, src_reg, shamt - 32);
10990 %}
10991 ins_pipe( ialu_regL_regL );
10992 %}
10994 // Xor Instructions
10995 // Xor Register with Register
10996 instruct xorI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10997 match(Set dst (XorI src1 src2));
10999 format %{ "XOR $dst, $src1, $src2 #@xorI_Reg_Reg" %}
11001 ins_encode %{
11002 Register dst = $dst$$Register;
11003 Register src1 = $src1$$Register;
11004 Register src2 = $src2$$Register;
11005 __ xorr(dst, src1, src2);
11006 __ sll(dst, dst, 0); /* long -> int */
11007 %}
11009 ins_pipe( ialu_regI_regI );
11010 %}
11012 // Or Instructions
11013 // Or Register with Register
11014 instruct orI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11015 match(Set dst (OrI src1 src2));
11017 format %{ "OR $dst, $src1, $src2 #@orI_Reg_Reg" %}
11018 ins_encode %{
11019 Register dst = $dst$$Register;
11020 Register src1 = $src1$$Register;
11021 Register src2 = $src2$$Register;
11022 __ orr(dst, src1, src2);
11023 %}
11025 ins_pipe( ialu_regI_regI );
11026 %}
11028 instruct rotI_shr_logical_Reg(mRegI dst, mRegI src, immI_0_31 rshift, immI_0_31 lshift, immI_1 one) %{
11029 match(Set dst (OrI (URShiftI src rshift) (LShiftI (AndI src one) lshift)));
11030 predicate(32 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int())));
11032 format %{ "rotr $dst, $src, 1 ...\n\t"
11033 "srl $dst, $dst, ($rshift-1) @ rotI_shr_logical_Reg" %}
11034 ins_encode %{
11035 Register dst = $dst$$Register;
11036 Register src = $src$$Register;
11037 int rshift = $rshift$$constant;
11039 __ rotr(dst, src, 1);
11040 if (rshift - 1) {
11041 __ srl(dst, dst, rshift - 1);
11042 }
11043 %}
11045 ins_pipe( ialu_regI_regI );
11046 %}
11048 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{
11049 match(Set dst (OrI src1 (CastP2X src2)));
11051 format %{ "OR $dst, $src1, $src2 #@orI_Reg_castP2X" %}
11052 ins_encode %{
11053 Register dst = $dst$$Register;
11054 Register src1 = $src1$$Register;
11055 Register src2 = $src2$$Register;
11056 __ orr(dst, src1, src2);
11057 %}
11059 ins_pipe( ialu_regI_regI );
11060 %}
11062 // Logical Shift Right by 8-bit immediate
11063 instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11064 match(Set dst (URShiftI src shift));
11065 // effect(KILL cr);
11067 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %}
11068 ins_encode %{
11069 Register src = $src$$Register;
11070 Register dst = $dst$$Register;
11071 int shift = $shift$$constant;
11073 __ srl(dst, src, shift);
11074 %}
11075 ins_pipe( ialu_regI_regI );
11076 %}
11078 instruct shr_logical_Reg_imm_nonneg_mask(mRegI dst, mRegI src, immI_0_31 shift, immI_nonneg_mask mask) %{
11079 match(Set dst (AndI (URShiftI src shift) mask));
11081 format %{ "ext $dst, $src, $shift, one-bits($mask) #@shr_logical_Reg_imm_nonneg_mask" %}
11082 ins_encode %{
11083 Register src = $src$$Register;
11084 Register dst = $dst$$Register;
11085 int pos = $shift$$constant;
11086 int size = Assembler::is_int_mask($mask$$constant);
11088 __ ext(dst, src, pos, size);
11089 %}
11090 ins_pipe( ialu_regI_regI );
11091 %}
11093 instruct rolI_Reg_immI_0_31(mRegI dst, immI_0_31 lshift, immI_0_31 rshift)
11094 %{
11095 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11096 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
11098 ins_cost(100);
11099 format %{ "rotr $dst, $dst, $rshift #@rolI_Reg_immI_0_31" %}
11100 ins_encode %{
11101 Register dst = $dst$$Register;
11102 int sa = $rshift$$constant;
11104 __ rotr(dst, dst, sa);
11105 %}
11106 ins_pipe( ialu_regI_regI );
11107 %}
11109 instruct rolL_Reg_immI_0_31(mRegL dst, immI_32_63 lshift, immI_0_31 rshift)
11110 %{
11111 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11112 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
11114 ins_cost(100);
11115 format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_0_31" %}
11116 ins_encode %{
11117 Register dst = $dst$$Register;
11118 int sa = $rshift$$constant;
11120 __ drotr(dst, dst, sa);
11121 %}
11122 ins_pipe( ialu_regI_regI );
11123 %}
11125 instruct rolL_Reg_immI_32_63(mRegL dst, immI_0_31 lshift, immI_32_63 rshift)
11126 %{
11127 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11128 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
11130 ins_cost(100);
11131 format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_32_63" %}
11132 ins_encode %{
11133 Register dst = $dst$$Register;
11134 int sa = $rshift$$constant;
11136 __ drotr32(dst, dst, sa - 32);
11137 %}
11138 ins_pipe( ialu_regI_regI );
11139 %}
11141 instruct rorI_Reg_immI_0_31(mRegI dst, immI_0_31 rshift, immI_0_31 lshift)
11142 %{
11143 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11144 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
11146 ins_cost(100);
11147 format %{ "rotr $dst, $dst, $rshift #@rorI_Reg_immI_0_31" %}
11148 ins_encode %{
11149 Register dst = $dst$$Register;
11150 int sa = $rshift$$constant;
11152 __ rotr(dst, dst, sa);
11153 %}
11154 ins_pipe( ialu_regI_regI );
11155 %}
11157 instruct rorL_Reg_immI_0_31(mRegL dst, immI_0_31 rshift, immI_32_63 lshift)
11158 %{
11159 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11160 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
11162 ins_cost(100);
11163 format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_0_31" %}
11164 ins_encode %{
11165 Register dst = $dst$$Register;
11166 int sa = $rshift$$constant;
11168 __ drotr(dst, dst, sa);
11169 %}
11170 ins_pipe( ialu_regI_regI );
11171 %}
11173 instruct rorL_Reg_immI_32_63(mRegL dst, immI_32_63 rshift, immI_0_31 lshift)
11174 %{
11175 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11176 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
11178 ins_cost(100);
11179 format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_32_63" %}
11180 ins_encode %{
11181 Register dst = $dst$$Register;
11182 int sa = $rshift$$constant;
11184 __ drotr32(dst, dst, sa - 32);
11185 %}
11186 ins_pipe( ialu_regI_regI );
11187 %}
11189 // Logical Shift Right
11190 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11191 match(Set dst (URShiftI src shift));
11193 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_Reg" %}
11194 ins_encode %{
11195 Register src = $src$$Register;
11196 Register dst = $dst$$Register;
11197 Register shift = $shift$$Register;
11198 __ srlv(dst, src, shift);
11199 %}
11200 ins_pipe( ialu_regI_regI );
11201 %}
11204 instruct shr_arith_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11205 match(Set dst (RShiftI src shift));
11206 // effect(KILL cr);
11208 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_imm" %}
11209 ins_encode %{
11210 Register src = $src$$Register;
11211 Register dst = $dst$$Register;
11212 int shift = $shift$$constant;
11213 __ sra(dst, src, shift);
11214 %}
11215 ins_pipe( ialu_regI_regI );
11216 %}
11218 instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11219 match(Set dst (RShiftI src shift));
11220 // effect(KILL cr);
11222 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_Reg" %}
11223 ins_encode %{
11224 Register src = $src$$Register;
11225 Register dst = $dst$$Register;
11226 Register shift = $shift$$Register;
11227 __ srav(dst, src, shift);
11228 %}
11229 ins_pipe( ialu_regI_regI );
11230 %}
11232 //----------Convert Int to Boolean---------------------------------------------
11234 instruct convI2B(mRegI dst, mRegI src) %{
11235 match(Set dst (Conv2B src));
11237 ins_cost(100);
11238 format %{ "convI2B $dst, $src @ convI2B" %}
11239 ins_encode %{
11240 Register dst = as_Register($dst$$reg);
11241 Register src = as_Register($src$$reg);
11243 if (dst != src) {
11244 __ daddiu(dst, R0, 1);
11245 __ movz(dst, R0, src);
11246 } else {
11247 __ move(AT, src);
11248 __ daddiu(dst, R0, 1);
11249 __ movz(dst, R0, AT);
11250 }
11251 %}
11253 ins_pipe( ialu_regL_regL );
11254 %}
11256 instruct convI2L_reg( mRegL dst, mRegI src) %{
11257 match(Set dst (ConvI2L src));
11259 ins_cost(100);
11260 format %{ "SLL $dst, $src @ convI2L_reg\t" %}
11261 ins_encode %{
11262 Register dst = as_Register($dst$$reg);
11263 Register src = as_Register($src$$reg);
11265 if(dst != src) __ sll(dst, src, 0);
11266 %}
11267 ins_pipe( ialu_regL_regL );
11268 %}
11271 instruct convL2I_reg( mRegI dst, mRegL src ) %{
11272 match(Set dst (ConvL2I src));
11274 format %{ "MOV $dst, $src @ convL2I_reg" %}
11275 ins_encode %{
11276 Register dst = as_Register($dst$$reg);
11277 Register src = as_Register($src$$reg);
11279 __ sll(dst, src, 0);
11280 %}
11282 ins_pipe( ialu_regI_regI );
11283 %}
11285 instruct convL2I2L_reg( mRegL dst, mRegL src ) %{
11286 match(Set dst (ConvI2L (ConvL2I src)));
11288 format %{ "sll $dst, $src, 0 @ convL2I2L_reg" %}
11289 ins_encode %{
11290 Register dst = as_Register($dst$$reg);
11291 Register src = as_Register($src$$reg);
11293 __ sll(dst, src, 0);
11294 %}
11296 ins_pipe( ialu_regI_regI );
11297 %}
11299 instruct convL2D_reg( regD dst, mRegL src ) %{
11300 match(Set dst (ConvL2D src));
11301 format %{ "convL2D $dst, $src @ convL2D_reg" %}
11302 ins_encode %{
11303 Register src = as_Register($src$$reg);
11304 FloatRegister dst = as_FloatRegister($dst$$reg);
11306 __ dmtc1(src, dst);
11307 __ cvt_d_l(dst, dst);
11308 %}
11310 ins_pipe( pipe_slow );
11311 %}
11314 instruct convD2L_reg_fast( mRegL dst, regD src ) %{
11315 match(Set dst (ConvD2L src));
11316 ins_cost(150);
11317 format %{ "convD2L $dst, $src @ convD2L_reg_fast" %}
11318 ins_encode %{
11319 Register dst = as_Register($dst$$reg);
11320 FloatRegister src = as_FloatRegister($src$$reg);
11322 Label Done;
11324 __ trunc_l_d(F30, src);
11325 // max_long: 0x7fffffffffffffff
11326 // __ set64(AT, 0x7fffffffffffffff);
11327 __ daddiu(AT, R0, -1);
11328 __ dsrl(AT, AT, 1);
11329 __ dmfc1(dst, F30);
11331 __ bne(dst, AT, Done);
11332 __ delayed()->mtc1(R0, F30);
11334 __ cvt_d_w(F30, F30);
11335 __ c_ult_d(src, F30);
11336 __ bc1f(Done);
11337 __ delayed()->daddiu(T9, R0, -1);
11339 __ c_un_d(src, src); //NaN?
11340 __ subu(dst, T9, AT);
11341 __ movt(dst, R0);
11343 __ bind(Done);
11344 %}
11346 ins_pipe( pipe_slow );
11347 %}
11350 instruct convD2L_reg_slow( mRegL dst, regD src ) %{
11351 match(Set dst (ConvD2L src));
11352 ins_cost(250);
11353 format %{ "convD2L $dst, $src @ convD2L_reg_slow" %}
11354 ins_encode %{
11355 Register dst = as_Register($dst$$reg);
11356 FloatRegister src = as_FloatRegister($src$$reg);
11358 Label L;
11360 __ c_un_d(src, src); //NaN?
11361 __ bc1t(L);
11362 __ delayed();
11363 __ move(dst, R0);
11365 __ trunc_l_d(F30, src);
11366 __ cfc1(AT, 31);
11367 __ li(T9, 0x10000);
11368 __ andr(AT, AT, T9);
11369 __ beq(AT, R0, L);
11370 __ delayed()->dmfc1(dst, F30);
11372 __ mov_d(F12, src);
11373 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1);
11374 __ move(dst, V0);
11375 __ bind(L);
11376 %}
11378 ins_pipe( pipe_slow );
11379 %}
11382 instruct convF2I_reg_fast( mRegI dst, regF src ) %{
11383 match(Set dst (ConvF2I src));
11384 ins_cost(150);
11385 format %{ "convf2i $dst, $src @ convF2I_reg_fast" %}
11386 ins_encode %{
11387 Register dreg = $dst$$Register;
11388 FloatRegister fval = $src$$FloatRegister;
11389 Label L;
11391 __ trunc_w_s(F30, fval);
11392 __ move(AT, 0x7fffffff);
11393 __ mfc1(dreg, F30);
11394 __ c_un_s(fval, fval); //NaN?
11395 __ movt(dreg, R0);
11397 __ bne(AT, dreg, L);
11398 __ delayed()->lui(T9, 0x8000);
11400 __ mfc1(AT, fval);
11401 __ andr(AT, AT, T9);
11403 __ movn(dreg, T9, AT);
11405 __ bind(L);
11407 %}
11409 ins_pipe( pipe_slow );
11410 %}
11414 instruct convF2I_reg_slow( mRegI dst, regF src ) %{
11415 match(Set dst (ConvF2I src));
11416 ins_cost(250);
11417 format %{ "convf2i $dst, $src @ convF2I_reg_slow" %}
11418 ins_encode %{
11419 Register dreg = $dst$$Register;
11420 FloatRegister fval = $src$$FloatRegister;
11421 Label L;
11423 __ c_un_s(fval, fval); //NaN?
11424 __ bc1t(L);
11425 __ delayed();
11426 __ move(dreg, R0);
11428 __ trunc_w_s(F30, fval);
11430 /* Call SharedRuntime:f2i() to do valid convention */
11431 __ cfc1(AT, 31);
11432 __ li(T9, 0x10000);
11433 __ andr(AT, AT, T9);
11434 __ beq(AT, R0, L);
11435 __ delayed()->mfc1(dreg, F30);
11437 __ mov_s(F12, fval);
11439 /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
11440 * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
11441 *
11442 * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
11443 * V0 is corrupted during call_VM_leaf(), and should be preserved.
11444 */
11445 __ push(fval);
11446 if(dreg != V0) {
11447 __ push(V0);
11448 }
11449 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
11450 if(dreg != V0) {
11451 __ move(dreg, V0);
11452 __ pop(V0);
11453 }
11454 __ pop(fval);
11455 __ bind(L);
11456 %}
11458 ins_pipe( pipe_slow );
11459 %}
11462 instruct convF2L_reg_fast( mRegL dst, regF src ) %{
11463 match(Set dst (ConvF2L src));
11464 ins_cost(150);
11465 format %{ "convf2l $dst, $src @ convF2L_reg_fast" %}
11466 ins_encode %{
11467 Register dreg = $dst$$Register;
11468 FloatRegister fval = $src$$FloatRegister;
11469 Label L;
11471 __ trunc_l_s(F30, fval);
11472 __ daddiu(AT, R0, -1);
11473 __ dsrl(AT, AT, 1);
11474 __ dmfc1(dreg, F30);
11475 __ c_un_s(fval, fval); //NaN?
11476 __ movt(dreg, R0);
11478 __ bne(AT, dreg, L);
11479 __ delayed()->lui(T9, 0x8000);
11481 __ mfc1(AT, fval);
11482 __ andr(AT, AT, T9);
11484 __ dsll32(T9, T9, 0);
11485 __ movn(dreg, T9, AT);
11487 __ bind(L);
11488 %}
11490 ins_pipe( pipe_slow );
11491 %}
11494 instruct convF2L_reg_slow( mRegL dst, regF src ) %{
11495 match(Set dst (ConvF2L src));
11496 ins_cost(250);
11497 format %{ "convf2l $dst, $src @ convF2L_reg_slow" %}
11498 ins_encode %{
11499 Register dst = as_Register($dst$$reg);
11500 FloatRegister fval = $src$$FloatRegister;
11501 Label L;
11503 __ c_un_s(fval, fval); //NaN?
11504 __ bc1t(L);
11505 __ delayed();
11506 __ move(dst, R0);
11508 __ trunc_l_s(F30, fval);
11509 __ cfc1(AT, 31);
11510 __ li(T9, 0x10000);
11511 __ andr(AT, AT, T9);
11512 __ beq(AT, R0, L);
11513 __ delayed()->dmfc1(dst, F30);
11515 __ mov_s(F12, fval);
11516 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1);
11517 __ move(dst, V0);
11518 __ bind(L);
11519 %}
11521 ins_pipe( pipe_slow );
11522 %}
11524 instruct convL2F_reg( regF dst, mRegL src ) %{
11525 match(Set dst (ConvL2F src));
11526 format %{ "convl2f $dst, $src @ convL2F_reg" %}
11527 ins_encode %{
11528 FloatRegister dst = $dst$$FloatRegister;
11529 Register src = as_Register($src$$reg);
11530 Label L;
11532 __ dmtc1(src, dst);
11533 __ cvt_s_l(dst, dst);
11534 %}
11536 ins_pipe( pipe_slow );
11537 %}
11539 instruct convI2F_reg( regF dst, mRegI src ) %{
11540 match(Set dst (ConvI2F src));
11541 format %{ "convi2f $dst, $src @ convI2F_reg" %}
11542 ins_encode %{
11543 Register src = $src$$Register;
11544 FloatRegister dst = $dst$$FloatRegister;
11546 __ mtc1(src, dst);
11547 __ cvt_s_w(dst, dst);
11548 %}
11550 ins_pipe( fpu_regF_regF );
11551 %}
11553 instruct cmpLTMask_immI0( mRegI dst, mRegI p, immI0 zero ) %{
11554 match(Set dst (CmpLTMask p zero));
11555 ins_cost(100);
11557 format %{ "sra $dst, $p, 31 @ cmpLTMask_immI0" %}
11558 ins_encode %{
11559 Register src = $p$$Register;
11560 Register dst = $dst$$Register;
11562 __ sra(dst, src, 31);
11563 %}
11564 ins_pipe( pipe_slow );
11565 %}
11568 instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{
11569 match(Set dst (CmpLTMask p q));
11570 ins_cost(400);
11572 format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %}
11573 ins_encode %{
11574 Register p = $p$$Register;
11575 Register q = $q$$Register;
11576 Register dst = $dst$$Register;
11578 __ slt(dst, p, q);
11579 __ subu(dst, R0, dst);
11580 %}
11581 ins_pipe( pipe_slow );
11582 %}
11584 instruct convP2B(mRegI dst, mRegP src) %{
11585 match(Set dst (Conv2B src));
11587 ins_cost(100);
11588 format %{ "convP2B $dst, $src @ convP2B" %}
11589 ins_encode %{
11590 Register dst = as_Register($dst$$reg);
11591 Register src = as_Register($src$$reg);
11593 if (dst != src) {
11594 __ daddiu(dst, R0, 1);
11595 __ movz(dst, R0, src);
11596 } else {
11597 __ move(AT, src);
11598 __ daddiu(dst, R0, 1);
11599 __ movz(dst, R0, AT);
11600 }
11601 %}
11603 ins_pipe( ialu_regL_regL );
11604 %}
11607 instruct convI2D_reg_reg(regD dst, mRegI src) %{
11608 match(Set dst (ConvI2D src));
11609 format %{ "conI2D $dst, $src @convI2D_reg" %}
11610 ins_encode %{
11611 Register src = $src$$Register;
11612 FloatRegister dst = $dst$$FloatRegister;
11613 __ mtc1(src, dst);
11614 __ cvt_d_w(dst, dst);
11615 %}
11616 ins_pipe( fpu_regF_regF );
11617 %}
11619 instruct convF2D_reg_reg(regD dst, regF src) %{
11620 match(Set dst (ConvF2D src));
11621 format %{ "convF2D $dst, $src\t# @convF2D_reg_reg" %}
11622 ins_encode %{
11623 FloatRegister dst = $dst$$FloatRegister;
11624 FloatRegister src = $src$$FloatRegister;
11626 __ cvt_d_s(dst, src);
11627 %}
11628 ins_pipe( fpu_regF_regF );
11629 %}
11631 instruct convD2F_reg_reg(regF dst, regD src) %{
11632 match(Set dst (ConvD2F src));
11633 format %{ "convD2F $dst, $src\t# @convD2F_reg_reg" %}
11634 ins_encode %{
11635 FloatRegister dst = $dst$$FloatRegister;
11636 FloatRegister src = $src$$FloatRegister;
11638 __ cvt_s_d(dst, src);
11639 %}
11640 ins_pipe( fpu_regF_regF );
11641 %}
11644 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11645 instruct convD2I_reg_reg_fast( mRegI dst, regD src ) %{
11646 match(Set dst (ConvD2I src));
11648 ins_cost(150);
11649 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_fast" %}
11651 ins_encode %{
11652 FloatRegister src = $src$$FloatRegister;
11653 Register dst = $dst$$Register;
11655 Label Done;
11657 __ trunc_w_d(F30, src);
11658 // max_int: 2147483647
11659 __ move(AT, 0x7fffffff);
11660 __ mfc1(dst, F30);
11662 __ bne(dst, AT, Done);
11663 __ delayed()->mtc1(R0, F30);
11665 __ cvt_d_w(F30, F30);
11666 __ c_ult_d(src, F30);
11667 __ bc1f(Done);
11668 __ delayed()->addiu(T9, R0, -1);
11670 __ c_un_d(src, src); //NaN?
11671 __ subu32(dst, T9, AT);
11672 __ movt(dst, R0);
11674 __ bind(Done);
11675 %}
11676 ins_pipe( pipe_slow );
11677 %}
11680 instruct convD2I_reg_reg_slow( mRegI dst, regD src ) %{
11681 match(Set dst (ConvD2I src));
11683 ins_cost(250);
11684 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_slow" %}
11686 ins_encode %{
11687 FloatRegister src = $src$$FloatRegister;
11688 Register dst = $dst$$Register;
11689 Label L;
11691 __ trunc_w_d(F30, src);
11692 __ cfc1(AT, 31);
11693 __ li(T9, 0x10000);
11694 __ andr(AT, AT, T9);
11695 __ beq(AT, R0, L);
11696 __ delayed()->mfc1(dst, F30);
11698 __ mov_d(F12, src);
11699 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
11700 __ move(dst, V0);
11701 __ bind(L);
11703 %}
11704 ins_pipe( pipe_slow );
11705 %}
11707 // Convert oop pointer into compressed form
11708 instruct encodeHeapOop(mRegN dst, mRegP src) %{
11709 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
11710 match(Set dst (EncodeP src));
11711 format %{ "encode_heap_oop $dst,$src" %}
11712 ins_encode %{
11713 Register src = $src$$Register;
11714 Register dst = $dst$$Register;
11716 __ encode_heap_oop(dst, src);
11717 %}
11718 ins_pipe( ialu_regL_regL );
11719 %}
11721 instruct encodeHeapOop_not_null(mRegN dst, mRegP src) %{
11722 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
11723 match(Set dst (EncodeP src));
11724 format %{ "encode_heap_oop_not_null $dst,$src @ encodeHeapOop_not_null" %}
11725 ins_encode %{
11726 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
11727 %}
11728 ins_pipe( ialu_regL_regL );
11729 %}
11731 instruct decodeHeapOop(mRegP dst, mRegN src) %{
11732 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
11733 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
11734 match(Set dst (DecodeN src));
11735 format %{ "decode_heap_oop $dst,$src @ decodeHeapOop" %}
11736 ins_encode %{
11737 Register s = $src$$Register;
11738 Register d = $dst$$Register;
11740 __ decode_heap_oop(d, s);
11741 %}
11742 ins_pipe( ialu_regL_regL );
11743 %}
11745 instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{
11746 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
11747 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
11748 match(Set dst (DecodeN src));
11749 format %{ "decode_heap_oop_not_null $dst,$src @ decodeHeapOop_not_null" %}
11750 ins_encode %{
11751 Register s = $src$$Register;
11752 Register d = $dst$$Register;
11753 if (s != d) {
11754 __ decode_heap_oop_not_null(d, s);
11755 } else {
11756 __ decode_heap_oop_not_null(d);
11757 }
11758 %}
11759 ins_pipe( ialu_regL_regL );
11760 %}
11762 instruct encodeKlass_not_null(mRegN dst, mRegP src) %{
11763 match(Set dst (EncodePKlass src));
11764 format %{ "encode_heap_oop_not_null $dst,$src @ encodeKlass_not_null" %}
11765 ins_encode %{
11766 __ encode_klass_not_null($dst$$Register, $src$$Register);
11767 %}
11768 ins_pipe( ialu_regL_regL );
11769 %}
11771 instruct decodeKlass_not_null(mRegP dst, mRegN src) %{
11772 match(Set dst (DecodeNKlass src));
11773 format %{ "decode_heap_klass_not_null $dst,$src" %}
11774 ins_encode %{
11775 Register s = $src$$Register;
11776 Register d = $dst$$Register;
11777 if (s != d) {
11778 __ decode_klass_not_null(d, s);
11779 } else {
11780 __ decode_klass_not_null(d);
11781 }
11782 %}
11783 ins_pipe( ialu_regL_regL );
11784 %}
11786 //FIXME
11787 instruct tlsLoadP(mRegP dst) %{
11788 match(Set dst (ThreadLocal));
11790 ins_cost(0);
11791 format %{ " get_thread in $dst #@tlsLoadP" %}
11792 ins_encode %{
11793 Register dst = $dst$$Register;
11794 #ifdef OPT_THREAD
11795 __ move(dst, TREG);
11796 #else
11797 __ get_thread(dst);
11798 #endif
11799 %}
11801 ins_pipe( ialu_loadI );
11802 %}
11805 instruct checkCastPP( mRegP dst ) %{
11806 match(Set dst (CheckCastPP dst));
11808 format %{ "#checkcastPP of $dst (empty encoding) #@chekCastPP" %}
11809 ins_encode( /*empty encoding*/ );
11810 ins_pipe( empty );
11811 %}
11813 instruct castPP(mRegP dst)
11814 %{
11815 match(Set dst (CastPP dst));
11817 size(0);
11818 format %{ "# castPP of $dst" %}
11819 ins_encode(/* empty encoding */);
11820 ins_pipe(empty);
11821 %}
11823 instruct castII( mRegI dst ) %{
11824 match(Set dst (CastII dst));
11825 format %{ "#castII of $dst empty encoding" %}
11826 ins_encode( /*empty encoding*/ );
11827 ins_cost(0);
11828 ins_pipe( empty );
11829 %}
11831 // Return Instruction
11832 // Remove the return address & jump to it.
11833 instruct Ret() %{
11834 match(Return);
11835 format %{ "RET #@Ret" %}
11837 ins_encode %{
11838 __ jr(RA);
11839 __ nop();
11840 %}
11842 ins_pipe( pipe_jump );
11843 %}
11845 /*
11846 // For Loongson CPUs, jr seems too slow, so this rule shouldn't be imported.
11847 instruct jumpXtnd(mRegL switch_val) %{
11848 match(Jump switch_val);
11850 ins_cost(350);
11852 format %{ "load T9 <-- [$constanttablebase, $switch_val, $constantoffset] @ jumpXtnd\n\t"
11853 "jr T9\n\t"
11854 "nop" %}
11855 ins_encode %{
11856 Register table_base = $constanttablebase;
11857 int con_offset = $constantoffset;
11858 Register switch_reg = $switch_val$$Register;
11860 if (UseLoongsonISA) {
11861 if (Assembler::is_simm(con_offset, 8)) {
11862 __ gsldx(T9, table_base, switch_reg, con_offset);
11863 } else if (Assembler::is_simm16(con_offset)) {
11864 __ daddu(T9, table_base, switch_reg);
11865 __ ld(T9, T9, con_offset);
11866 } else {
11867 __ move(T9, con_offset);
11868 __ daddu(AT, table_base, switch_reg);
11869 __ gsldx(T9, AT, T9, 0);
11870 }
11871 } else {
11872 if (Assembler::is_simm16(con_offset)) {
11873 __ daddu(T9, table_base, switch_reg);
11874 __ ld(T9, T9, con_offset);
11875 } else {
11876 __ move(T9, con_offset);
11877 __ daddu(AT, table_base, switch_reg);
11878 __ daddu(AT, T9, AT);
11879 __ ld(T9, AT, 0);
11880 }
11881 }
11883 __ jr(T9);
11884 __ nop();
11886 %}
11887 ins_pipe(pipe_jump);
11888 %}
11889 */
11891 // Jump Direct - Label defines a relative address from JMP
11892 instruct jmpDir(label labl) %{
11893 match(Goto);
11894 effect(USE labl);
11896 ins_cost(300);
11897 format %{ "JMP $labl #@jmpDir" %}
11899 ins_encode %{
11900 Label &L = *($labl$$label);
11901 if(&L)
11902 __ b(L);
11903 else
11904 __ b(int(0));
11905 __ nop();
11906 %}
11908 ins_pipe( pipe_jump );
11909 ins_pc_relative(1);
11910 %}
11914 // Tail Jump; remove the return address; jump to target.
11915 // TailCall above leaves the return address around.
11916 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11917 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11918 // "restore" before this instruction (in Epilogue), we need to materialize it
11919 // in %i0.
11920 //FIXME
11921 instruct tailjmpInd(mRegP jump_target,mRegP ex_oop) %{
11922 match( TailJump jump_target ex_oop );
11923 ins_cost(200);
11924 format %{ "Jmp $jump_target ; ex_oop = $ex_oop #@tailjmpInd" %}
11925 ins_encode %{
11926 Register target = $jump_target$$Register;
11928 /* 2012/9/14 Jin: V0, V1 are indicated in:
11929 * [stubGenerator_mips.cpp] generate_forward_exception()
11930 * [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
11931 */
11932 Register oop = $ex_oop$$Register;
11933 Register exception_oop = V0;
11934 Register exception_pc = V1;
11936 __ move(exception_pc, RA);
11937 __ move(exception_oop, oop);
11939 __ jr(target);
11940 __ nop();
11941 %}
11942 ins_pipe( pipe_jump );
11943 %}
11945 // ============================================================================
11946 // Procedure Call/Return Instructions
11947 // Call Java Static Instruction
11948 // Note: If this code changes, the corresponding ret_addr_offset() and
11949 // compute_padding() functions will have to be adjusted.
11950 instruct CallStaticJavaDirect(method meth) %{
11951 match(CallStaticJava);
11952 effect(USE meth);
11954 ins_cost(300);
11955 format %{ "CALL,static #@CallStaticJavaDirect " %}
11956 ins_encode( Java_Static_Call( meth ) );
11957 ins_pipe( pipe_slow );
11958 ins_pc_relative(1);
11959 %}
11961 // Call Java Dynamic Instruction
11962 // Note: If this code changes, the corresponding ret_addr_offset() and
11963 // compute_padding() functions will have to be adjusted.
11964 instruct CallDynamicJavaDirect(method meth) %{
11965 match(CallDynamicJava);
11966 effect(USE meth);
11968 ins_cost(300);
11969 format %{"MOV IC_Klass, (oop)-1\n\t"
11970 "CallDynamic @ CallDynamicJavaDirect" %}
11971 ins_encode( Java_Dynamic_Call( meth ) );
11972 ins_pipe( pipe_slow );
11973 ins_pc_relative(1);
11974 %}
11976 instruct CallLeafNoFPDirect(method meth) %{
11977 match(CallLeafNoFP);
11978 effect(USE meth);
11980 ins_cost(300);
11981 format %{ "CALL_LEAF_NOFP,runtime " %}
11982 ins_encode(Java_To_Runtime(meth));
11983 ins_pipe( pipe_slow );
11984 ins_pc_relative(1);
11985 ins_alignment(16);
11986 %}
11988 // Prefetch instructions.
11990 instruct prefetchrNTA( memory mem ) %{
11991 match(PrefetchRead mem);
11992 ins_cost(125);
11994 format %{ "pref $mem\t# Prefetch into non-temporal cache for read @ prefetchrNTA" %}
11995 ins_encode %{
11996 int base = $mem$$base;
11997 int index = $mem$$index;
11998 int scale = $mem$$scale;
11999 int disp = $mem$$disp;
12001 if( index != 0 ) {
12002 if (scale == 0) {
12003 __ daddu(AT, as_Register(base), as_Register(index));
12004 } else {
12005 __ dsll(AT, as_Register(index), scale);
12006 __ daddu(AT, as_Register(base), AT);
12007 }
12008 } else {
12009 __ move(AT, as_Register(base));
12010 }
12011 if( Assembler::is_simm16(disp) ) {
12012 __ daddiu(AT, as_Register(base), disp);
12013 __ daddiu(AT, AT, disp);
12014 } else {
12015 __ move(T9, disp);
12016 __ daddu(AT, as_Register(base), T9);
12017 }
12018 __ pref(0, AT, 0); //hint: 0:load
12019 %}
12020 ins_pipe(pipe_slow);
12021 %}
12023 instruct prefetchwNTA( memory mem ) %{
12024 match(PrefetchWrite mem);
12025 ins_cost(125);
12026 format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %}
12027 ins_encode %{
12028 int base = $mem$$base;
12029 int index = $mem$$index;
12030 int scale = $mem$$scale;
12031 int disp = $mem$$disp;
12033 if( index != 0 ) {
12034 if (scale == 0) {
12035 __ daddu(AT, as_Register(base), as_Register(index));
12036 } else {
12037 __ dsll(AT, as_Register(index), scale);
12038 __ daddu(AT, as_Register(base), AT);
12039 }
12040 } else {
12041 __ move(AT, as_Register(base));
12042 }
12043 if( Assembler::is_simm16(disp) ) {
12044 __ daddiu(AT, as_Register(base), disp);
12045 __ daddiu(AT, AT, disp);
12046 } else {
12047 __ move(T9, disp);
12048 __ daddu(AT, as_Register(base), T9);
12049 }
12050 __ pref(1, AT, 0); //hint: 1:store
12051 %}
12052 ins_pipe(pipe_slow);
12053 %}
12055 // Prefetch instructions for allocation.
12057 instruct prefetchAllocNTA( memory mem ) %{
12058 match(PrefetchAllocation mem);
12059 ins_cost(125);
12060 format %{ "pref $mem\t# Prefetch allocation @ prefetchAllocNTA" %}
12061 ins_encode %{
12062 int base = $mem$$base;
12063 int index = $mem$$index;
12064 int scale = $mem$$scale;
12065 int disp = $mem$$disp;
12067 Register dst = R0;
12069 if( index != 0 ) {
12070 if( Assembler::is_simm16(disp) ) {
12071 if( UseLoongsonISA ) {
12072 if (scale == 0) {
12073 __ gslbx(dst, as_Register(base), as_Register(index), disp);
12074 } else {
12075 __ dsll(AT, as_Register(index), scale);
12076 __ gslbx(dst, as_Register(base), AT, disp);
12077 }
12078 } else {
12079 if (scale == 0) {
12080 __ addu(AT, as_Register(base), as_Register(index));
12081 } else {
12082 __ dsll(AT, as_Register(index), scale);
12083 __ addu(AT, as_Register(base), AT);
12084 }
12085 __ lb(dst, AT, disp);
12086 }
12087 } else {
12088 if (scale == 0) {
12089 __ addu(AT, as_Register(base), as_Register(index));
12090 } else {
12091 __ dsll(AT, as_Register(index), scale);
12092 __ addu(AT, as_Register(base), AT);
12093 }
12094 __ move(T9, disp);
12095 if( UseLoongsonISA ) {
12096 __ gslbx(dst, AT, T9, 0);
12097 } else {
12098 __ addu(AT, AT, T9);
12099 __ lb(dst, AT, 0);
12100 }
12101 }
12102 } else {
12103 if( Assembler::is_simm16(disp) ) {
12104 __ lb(dst, as_Register(base), disp);
12105 } else {
12106 __ move(T9, disp);
12107 if( UseLoongsonISA ) {
12108 __ gslbx(dst, as_Register(base), T9, 0);
12109 } else {
12110 __ addu(AT, as_Register(base), T9);
12111 __ lb(dst, AT, 0);
12112 }
12113 }
12114 }
12115 %}
12116 ins_pipe(pipe_slow);
12117 %}
12120 // Call runtime without safepoint
12121 instruct CallLeafDirect(method meth) %{
12122 match(CallLeaf);
12123 effect(USE meth);
12125 ins_cost(300);
12126 format %{ "CALL_LEAF,runtime #@CallLeafDirect " %}
12127 ins_encode(Java_To_Runtime(meth));
12128 ins_pipe( pipe_slow );
12129 ins_pc_relative(1);
12130 ins_alignment(16);
12131 %}
12133 // Load Char (16bit unsigned)
12134 instruct loadUS(mRegI dst, memory mem) %{
12135 match(Set dst (LoadUS mem));
12137 ins_cost(125);
12138 format %{ "loadUS $dst,$mem @ loadC" %}
12139 ins_encode(load_C_enc(dst, mem));
12140 ins_pipe( ialu_loadI );
12141 %}
12143 instruct loadUS_convI2L(mRegL dst, memory mem) %{
12144 match(Set dst (ConvI2L (LoadUS mem)));
12146 ins_cost(125);
12147 format %{ "loadUS $dst,$mem @ loadUS_convI2L" %}
12148 ins_encode(load_C_enc(dst, mem));
12149 ins_pipe( ialu_loadI );
12150 %}
12152 // Store Char (16bit unsigned)
12153 instruct storeC(memory mem, mRegI src) %{
12154 match(Set mem (StoreC mem src));
12156 ins_cost(125);
12157 format %{ "storeC $src, $mem @ storeC" %}
12158 ins_encode(store_C_reg_enc(mem, src));
12159 ins_pipe( ialu_loadI );
12160 %}
12162 instruct storeC0(memory mem, immI0 zero) %{
12163 match(Set mem (StoreC mem zero));
12165 ins_cost(125);
12166 format %{ "storeC $zero, $mem @ storeC0" %}
12167 ins_encode(store_C0_enc(mem));
12168 ins_pipe( ialu_loadI );
12169 %}
12172 instruct loadConF0(regF dst, immF0 zero) %{
12173 match(Set dst zero);
12174 ins_cost(100);
12176 format %{ "mov $dst, zero @ loadConF0\n"%}
12177 ins_encode %{
12178 FloatRegister dst = $dst$$FloatRegister;
12180 __ mtc1(R0, dst);
12181 %}
12182 ins_pipe( fpu_loadF );
12183 %}
12186 instruct loadConF(regF dst, immF src) %{
12187 match(Set dst src);
12188 ins_cost(125);
12190 format %{ "lwc1 $dst, $constantoffset[$constanttablebase] # load FLOAT $src from table @ loadConF" %}
12191 ins_encode %{
12192 int con_offset = $constantoffset($src);
12194 if (Assembler::is_simm16(con_offset)) {
12195 __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset);
12196 } else {
12197 __ set64(AT, con_offset);
12198 if (UseLoongsonISA) {
12199 __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12200 } else {
12201 __ daddu(AT, $constanttablebase, AT);
12202 __ lwc1($dst$$FloatRegister, AT, 0);
12203 }
12204 }
12205 %}
12206 ins_pipe( fpu_loadF );
12207 %}
12210 instruct loadConD0(regD dst, immD0 zero) %{
12211 match(Set dst zero);
12212 ins_cost(100);
12214 format %{ "mov $dst, zero @ loadConD0"%}
12215 ins_encode %{
12216 FloatRegister dst = as_FloatRegister($dst$$reg);
12218 __ dmtc1(R0, dst);
12219 %}
12220 ins_pipe( fpu_loadF );
12221 %}
12223 instruct loadConD(regD dst, immD src) %{
12224 match(Set dst src);
12225 ins_cost(125);
12227 format %{ "ldc1 $dst, $constantoffset[$constanttablebase] # load DOUBLE $src from table @ loadConD" %}
12228 ins_encode %{
12229 int con_offset = $constantoffset($src);
12231 if (Assembler::is_simm16(con_offset)) {
12232 __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset);
12233 } else {
12234 __ set64(AT, con_offset);
12235 if (UseLoongsonISA) {
12236 __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12237 } else {
12238 __ daddu(AT, $constanttablebase, AT);
12239 __ ldc1($dst$$FloatRegister, AT, 0);
12240 }
12241 }
12242 %}
12243 ins_pipe( fpu_loadF );
12244 %}
12246 // Store register Float value (it is faster than store from FPU register)
12247 instruct storeF_reg( memory mem, regF src) %{
12248 match(Set mem (StoreF mem src));
12250 ins_cost(50);
12251 format %{ "store $mem, $src\t# store float @ storeF_reg" %}
12252 ins_encode(store_F_reg_enc(mem, src));
12253 ins_pipe( fpu_storeF );
12254 %}
12256 instruct storeF_imm0( memory mem, immF0 zero) %{
12257 match(Set mem (StoreF mem zero));
12259 ins_cost(40);
12260 format %{ "store $mem, zero\t# store float @ storeF_imm0" %}
12261 ins_encode %{
12262 int base = $mem$$base;
12263 int index = $mem$$index;
12264 int scale = $mem$$scale;
12265 int disp = $mem$$disp;
12267 if( index != 0 ) {
12268 if ( UseLoongsonISA ) {
12269 if ( Assembler::is_simm(disp, 8) ) {
12270 if ( scale == 0 ) {
12271 __ gsswx(R0, as_Register(base), as_Register(index), disp);
12272 } else {
12273 __ dsll(T9, as_Register(index), scale);
12274 __ gsswx(R0, as_Register(base), T9, disp);
12275 }
12276 } else if ( Assembler::is_simm16(disp) ) {
12277 if ( scale == 0 ) {
12278 __ daddu(AT, as_Register(base), as_Register(index));
12279 } else {
12280 __ dsll(T9, as_Register(index), scale);
12281 __ daddu(AT, as_Register(base), T9);
12282 }
12283 __ sw(R0, AT, disp);
12284 } else {
12285 if ( scale == 0 ) {
12286 __ move(T9, disp);
12287 __ daddu(AT, as_Register(index), T9);
12288 __ gsswx(R0, as_Register(base), AT, 0);
12289 } else {
12290 __ dsll(T9, as_Register(index), scale);
12291 __ move(AT, disp);
12292 __ daddu(AT, AT, T9);
12293 __ gsswx(R0, as_Register(base), AT, 0);
12294 }
12295 }
12296 } else { //not use loongson isa
12297 if(scale != 0) {
12298 __ dsll(T9, as_Register(index), scale);
12299 __ daddu(AT, as_Register(base), T9);
12300 } else {
12301 __ daddu(AT, as_Register(base), as_Register(index));
12302 }
12303 if( Assembler::is_simm16(disp) ) {
12304 __ sw(R0, AT, disp);
12305 } else {
12306 __ move(T9, disp);
12307 __ daddu(AT, AT, T9);
12308 __ sw(R0, AT, 0);
12309 }
12310 }
12311 } else { //index is 0
12312 if ( UseLoongsonISA ) {
12313 if ( Assembler::is_simm16(disp) ) {
12314 __ sw(R0, as_Register(base), disp);
12315 } else {
12316 __ move(T9, disp);
12317 __ gsswx(R0, as_Register(base), T9, 0);
12318 }
12319 } else {
12320 if( Assembler::is_simm16(disp) ) {
12321 __ sw(R0, as_Register(base), disp);
12322 } else {
12323 __ move(T9, disp);
12324 __ daddu(AT, as_Register(base), T9);
12325 __ sw(R0, AT, 0);
12326 }
12327 }
12328 }
12329 %}
12330 ins_pipe( ialu_storeI );
12331 %}
12333 // Load Double
12334 instruct loadD(regD dst, memory mem) %{
12335 match(Set dst (LoadD mem));
12337 ins_cost(150);
12338 format %{ "loadD $dst, $mem #@loadD" %}
12339 ins_encode(load_D_enc(dst, mem));
12340 ins_pipe( ialu_loadI );
12341 %}
12343 // Load Double - UNaligned
12344 instruct loadD_unaligned(regD dst, memory mem ) %{
12345 match(Set dst (LoadD_unaligned mem));
12346 ins_cost(250);
12347 // FIXME: Jin: Need more effective ldl/ldr
12348 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %}
12349 ins_encode(load_D_enc(dst, mem));
12350 ins_pipe( ialu_loadI );
12351 %}
12353 instruct storeD_reg( memory mem, regD src) %{
12354 match(Set mem (StoreD mem src));
12356 ins_cost(50);
12357 format %{ "store $mem, $src\t# store float @ storeD_reg" %}
12358 ins_encode(store_D_reg_enc(mem, src));
12359 ins_pipe( fpu_storeF );
12360 %}
12362 instruct storeD_imm0( memory mem, immD0 zero) %{
12363 match(Set mem (StoreD mem zero));
12365 ins_cost(40);
12366 format %{ "store $mem, zero\t# store float @ storeD_imm0" %}
12367 ins_encode %{
12368 int base = $mem$$base;
12369 int index = $mem$$index;
12370 int scale = $mem$$scale;
12371 int disp = $mem$$disp;
12373 __ mtc1(R0, F30);
12374 __ cvt_d_w(F30, F30);
12376 if( index != 0 ) {
12377 if ( UseLoongsonISA ) {
12378 if ( Assembler::is_simm(disp, 8) ) {
12379 if (scale == 0) {
12380 __ gssdxc1(F30, as_Register(base), as_Register(index), disp);
12381 } else {
12382 __ dsll(T9, as_Register(index), scale);
12383 __ gssdxc1(F30, as_Register(base), T9, disp);
12384 }
12385 } else if ( Assembler::is_simm16(disp) ) {
12386 if (scale == 0) {
12387 __ daddu(AT, as_Register(base), as_Register(index));
12388 __ sdc1(F30, AT, disp);
12389 } else {
12390 __ dsll(T9, as_Register(index), scale);
12391 __ daddu(AT, as_Register(base), T9);
12392 __ sdc1(F30, AT, disp);
12393 }
12394 } else {
12395 if (scale == 0) {
12396 __ move(T9, disp);
12397 __ daddu(AT, as_Register(index), T9);
12398 __ gssdxc1(F30, as_Register(base), AT, 0);
12399 } else {
12400 __ move(T9, disp);
12401 __ dsll(AT, as_Register(index), scale);
12402 __ daddu(AT, AT, T9);
12403 __ gssdxc1(F30, as_Register(base), AT, 0);
12404 }
12405 }
12406 } else { // not use loongson isa
12407 if(scale != 0) {
12408 __ dsll(T9, as_Register(index), scale);
12409 __ daddu(AT, as_Register(base), T9);
12410 } else {
12411 __ daddu(AT, as_Register(base), as_Register(index));
12412 }
12413 if( Assembler::is_simm16(disp) ) {
12414 __ sdc1(F30, AT, disp);
12415 } else {
12416 __ move(T9, disp);
12417 __ daddu(AT, AT, T9);
12418 __ sdc1(F30, AT, 0);
12419 }
12420 }
12421 } else {// index is 0
12422 if ( UseLoongsonISA ) {
12423 if ( Assembler::is_simm16(disp) ) {
12424 __ sdc1(F30, as_Register(base), disp);
12425 } else {
12426 __ move(T9, disp);
12427 __ gssdxc1(F30, as_Register(base), T9, 0);
12428 }
12429 } else {
12430 if( Assembler::is_simm16(disp) ) {
12431 __ sdc1(F30, as_Register(base), disp);
12432 } else {
12433 __ move(T9, disp);
12434 __ daddu(AT, as_Register(base), T9);
12435 __ sdc1(F30, AT, 0);
12436 }
12437 }
12438 }
12439 %}
12440 ins_pipe( ialu_storeI );
12441 %}
12443 instruct loadSSI(mRegI dst, stackSlotI src)
12444 %{
12445 match(Set dst src);
12447 ins_cost(125);
12448 format %{ "lw $dst, $src\t# int stk @ loadSSI" %}
12449 ins_encode %{
12450 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSI) !");
12451 __ lw($dst$$Register, SP, $src$$disp);
12452 %}
12453 ins_pipe(ialu_loadI);
12454 %}
12456 instruct storeSSI(stackSlotI dst, mRegI src)
12457 %{
12458 match(Set dst src);
12460 ins_cost(100);
12461 format %{ "sw $dst, $src\t# int stk @ storeSSI" %}
12462 ins_encode %{
12463 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSI) !");
12464 __ sw($src$$Register, SP, $dst$$disp);
12465 %}
12466 ins_pipe(ialu_storeI);
12467 %}
12469 instruct loadSSL(mRegL dst, stackSlotL src)
12470 %{
12471 match(Set dst src);
12473 ins_cost(125);
12474 format %{ "ld $dst, $src\t# long stk @ loadSSL" %}
12475 ins_encode %{
12476 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSL) !");
12477 __ ld($dst$$Register, SP, $src$$disp);
12478 %}
12479 ins_pipe(ialu_loadI);
12480 %}
12482 instruct storeSSL(stackSlotL dst, mRegL src)
12483 %{
12484 match(Set dst src);
12486 ins_cost(100);
12487 format %{ "sd $dst, $src\t# long stk @ storeSSL" %}
12488 ins_encode %{
12489 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSL) !");
12490 __ sd($src$$Register, SP, $dst$$disp);
12491 %}
12492 ins_pipe(ialu_storeI);
12493 %}
12495 instruct loadSSP(mRegP dst, stackSlotP src)
12496 %{
12497 match(Set dst src);
12499 ins_cost(125);
12500 format %{ "ld $dst, $src\t# ptr stk @ loadSSP" %}
12501 ins_encode %{
12502 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSP) !");
12503 __ ld($dst$$Register, SP, $src$$disp);
12504 %}
12505 ins_pipe(ialu_loadI);
12506 %}
12508 instruct storeSSP(stackSlotP dst, mRegP src)
12509 %{
12510 match(Set dst src);
12512 ins_cost(100);
12513 format %{ "sd $dst, $src\t# ptr stk @ storeSSP" %}
12514 ins_encode %{
12515 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSP) !");
12516 __ sd($src$$Register, SP, $dst$$disp);
12517 %}
12518 ins_pipe(ialu_storeI);
12519 %}
12521 instruct loadSSF(regF dst, stackSlotF src)
12522 %{
12523 match(Set dst src);
12525 ins_cost(125);
12526 format %{ "lwc1 $dst, $src\t# float stk @ loadSSF" %}
12527 ins_encode %{
12528 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSF) !");
12529 __ lwc1($dst$$FloatRegister, SP, $src$$disp);
12530 %}
12531 ins_pipe(ialu_loadI);
12532 %}
12534 instruct storeSSF(stackSlotF dst, regF src)
12535 %{
12536 match(Set dst src);
12538 ins_cost(100);
12539 format %{ "swc1 $dst, $src\t# float stk @ storeSSF" %}
12540 ins_encode %{
12541 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSF) !");
12542 __ swc1($src$$FloatRegister, SP, $dst$$disp);
12543 %}
12544 ins_pipe(fpu_storeF);
12545 %}
12547 // Use the same format since predicate() can not be used here.
12548 instruct loadSSD(regD dst, stackSlotD src)
12549 %{
12550 match(Set dst src);
12552 ins_cost(125);
12553 format %{ "ldc1 $dst, $src\t# double stk @ loadSSD" %}
12554 ins_encode %{
12555 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSD) !");
12556 __ ldc1($dst$$FloatRegister, SP, $src$$disp);
12557 %}
12558 ins_pipe(ialu_loadI);
12559 %}
12561 instruct storeSSD(stackSlotD dst, regD src)
12562 %{
12563 match(Set dst src);
12565 ins_cost(100);
12566 format %{ "sdc1 $dst, $src\t# double stk @ storeSSD" %}
12567 ins_encode %{
12568 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSD) !");
12569 __ sdc1($src$$FloatRegister, SP, $dst$$disp);
12570 %}
12571 ins_pipe(fpu_storeF);
12572 %}
12574 instruct cmpFastLock( FlagsReg cr, mRegP object, s0_RegP box, mRegI tmp, mRegP scr) %{
12575 match( Set cr (FastLock object box) );
12576 effect( TEMP tmp, TEMP scr, USE_KILL box );
12577 ins_cost(300);
12578 format %{ "FASTLOCK $cr $object, $box, $tmp #@ cmpFastLock" %}
12579 ins_encode %{
12580 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register);
12581 %}
12583 ins_pipe( pipe_slow );
12584 ins_pc_relative(1);
12585 %}
12587 instruct cmpFastUnlock( FlagsReg cr, mRegP object, s0_RegP box, mRegP tmp ) %{
12588 match( Set cr (FastUnlock object box) );
12589 effect( TEMP tmp, USE_KILL box );
12590 ins_cost(300);
12591 format %{ "FASTUNLOCK $object, $box, $tmp #@cmpFastUnlock" %}
12592 ins_encode %{
12593 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12594 %}
12596 ins_pipe( pipe_slow );
12597 ins_pc_relative(1);
12598 %}
12600 // Store CMS card-mark Immediate
12601 instruct storeImmCM(memory mem, immI8 src) %{
12602 match(Set mem (StoreCM mem src));
12604 ins_cost(150);
12605 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
12606 // opcode(0xC6);
12607 ins_encode(store_B_immI_enc_sync(mem, src));
12608 ins_pipe( ialu_storeI );
12609 %}
12611 // Die now
12612 instruct ShouldNotReachHere( )
12613 %{
12614 match(Halt);
12615 ins_cost(300);
12617 // Use the following format syntax
12618 format %{ "ILLTRAP ;#@ShouldNotReachHere" %}
12619 ins_encode %{
12620 // Here we should emit illtrap !
12622 __ stop("in ShoudNotReachHere");
12624 %}
12625 ins_pipe( pipe_jump );
12626 %}
12628 instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem)
12629 %{
12630 predicate(Universe::narrow_oop_shift() == 0);
12631 match(Set dst mem);
12633 ins_cost(110);
12634 format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
12635 ins_encode %{
12636 Register dst = $dst$$Register;
12637 Register base = as_Register($mem$$base);
12638 int disp = $mem$$disp;
12640 __ daddiu(dst, base, disp);
12641 %}
12642 ins_pipe( ialu_regI_imm16 );
12643 %}
12645 instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem)
12646 %{
12647 match(Set dst mem);
12649 ins_cost(110);
12650 format %{ "leaq $dst, $mem\t# @ PosIdxScaleOff8" %}
12651 ins_encode %{
12652 Register dst = $dst$$Register;
12653 Register base = as_Register($mem$$base);
12654 Register index = as_Register($mem$$index);
12655 int scale = $mem$$scale;
12656 int disp = $mem$$disp;
12658 if (scale == 0) {
12659 __ daddu(AT, base, index);
12660 __ daddiu(dst, AT, disp);
12661 } else {
12662 __ dsll(AT, index, scale);
12663 __ daddu(AT, base, AT);
12664 __ daddiu(dst, AT, disp);
12665 }
12666 %}
12668 ins_pipe( ialu_regI_imm16 );
12669 %}
12671 instruct leaPIdxScale(mRegP dst, indIndexScale mem)
12672 %{
12673 match(Set dst mem);
12675 ins_cost(110);
12676 format %{ "leaq $dst, $mem\t# @ leaPIdxScale" %}
12677 ins_encode %{
12678 Register dst = $dst$$Register;
12679 Register base = as_Register($mem$$base);
12680 Register index = as_Register($mem$$index);
12681 int scale = $mem$$scale;
12683 if (scale == 0) {
12684 __ daddu(dst, base, index);
12685 } else {
12686 __ dsll(AT, index, scale);
12687 __ daddu(dst, base, AT);
12688 }
12689 %}
12691 ins_pipe( ialu_regI_imm16 );
12692 %}
12694 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12695 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
12696 match(CountedLoopEnd cop (CmpI src1 src2));
12697 effect(USE labl);
12699 ins_cost(300);
12700 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %}
12701 ins_encode %{
12702 Register op1 = $src1$$Register;
12703 Register op2 = $src2$$Register;
12704 Label &L = *($labl$$label);
12705 int flag = $cop$$cmpcode;
12707 switch(flag)
12708 {
12709 case 0x01: //equal
12710 if (&L)
12711 __ beq(op1, op2, L);
12712 else
12713 __ beq(op1, op2, (int)0);
12714 break;
12715 case 0x02: //not_equal
12716 if (&L)
12717 __ bne(op1, op2, L);
12718 else
12719 __ bne(op1, op2, (int)0);
12720 break;
12721 case 0x03: //above
12722 __ slt(AT, op2, op1);
12723 if(&L)
12724 __ bne(AT, R0, L);
12725 else
12726 __ bne(AT, R0, (int)0);
12727 break;
12728 case 0x04: //above_equal
12729 __ slt(AT, op1, op2);
12730 if(&L)
12731 __ beq(AT, R0, L);
12732 else
12733 __ beq(AT, R0, (int)0);
12734 break;
12735 case 0x05: //below
12736 __ slt(AT, op1, op2);
12737 if(&L)
12738 __ bne(AT, R0, L);
12739 else
12740 __ bne(AT, R0, (int)0);
12741 break;
12742 case 0x06: //below_equal
12743 __ slt(AT, op2, op1);
12744 if(&L)
12745 __ beq(AT, R0, L);
12746 else
12747 __ beq(AT, R0, (int)0);
12748 break;
12749 default:
12750 Unimplemented();
12751 }
12752 __ nop();
12753 %}
12754 ins_pipe( pipe_jump );
12755 ins_pc_relative(1);
12756 %}
12758 instruct jmpLoopEnd_reg_immI(cmpOp cop, mRegI src1, immI src2, label labl) %{
12759 match(CountedLoopEnd cop (CmpI src1 src2));
12760 effect(USE labl);
12762 ins_cost(300);
12763 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_immI" %}
12764 ins_encode %{
12765 Register op1 = $src1$$Register;
12766 Register op2 = AT;
12767 Label &L = *($labl$$label);
12768 int flag = $cop$$cmpcode;
12770 __ move(op2, $src2$$constant);
12772 switch(flag)
12773 {
12774 case 0x01: //equal
12775 if (&L)
12776 __ beq(op1, op2, L);
12777 else
12778 __ beq(op1, op2, (int)0);
12779 break;
12780 case 0x02: //not_equal
12781 if (&L)
12782 __ bne(op1, op2, L);
12783 else
12784 __ bne(op1, op2, (int)0);
12785 break;
12786 case 0x03: //above
12787 __ slt(AT, op2, op1);
12788 if(&L)
12789 __ bne(AT, R0, L);
12790 else
12791 __ bne(AT, R0, (int)0);
12792 break;
12793 case 0x04: //above_equal
12794 __ slt(AT, op1, op2);
12795 if(&L)
12796 __ beq(AT, R0, L);
12797 else
12798 __ beq(AT, R0, (int)0);
12799 break;
12800 case 0x05: //below
12801 __ slt(AT, op1, op2);
12802 if(&L)
12803 __ bne(AT, R0, L);
12804 else
12805 __ bne(AT, R0, (int)0);
12806 break;
12807 case 0x06: //below_equal
12808 __ slt(AT, op2, op1);
12809 if(&L)
12810 __ beq(AT, R0, L);
12811 else
12812 __ beq(AT, R0, (int)0);
12813 break;
12814 default:
12815 Unimplemented();
12816 }
12817 __ nop();
12818 %}
12819 ins_pipe( pipe_jump );
12820 ins_pc_relative(1);
12821 %}
12824 // This match pattern is created for StoreIConditional since I cannot match IfNode without a RegFlags! fujie 2012/07/17
12825 instruct jmpCon_flags(cmpOp cop, FlagsReg cr, label labl) %{
12826 match(If cop cr);
12827 effect(USE labl);
12829 ins_cost(300);
12830 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags" %}
12832 ins_encode %{
12833 Label &L = *($labl$$label);
12834 switch($cop$$cmpcode)
12835 {
12836 case 0x01: //equal
12837 if (&L)
12838 __ bne(AT, R0, L);
12839 else
12840 __ bne(AT, R0, (int)0);
12841 break;
12842 case 0x02: //not equal
12843 if (&L)
12844 __ beq(AT, R0, L);
12845 else
12846 __ beq(AT, R0, (int)0);
12847 break;
12848 default:
12849 Unimplemented();
12850 }
12851 __ nop();
12852 %}
12854 ins_pipe( pipe_jump );
12855 ins_pc_relative(1);
12856 %}
12859 // ============================================================================
12860 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12861 // array for an instance of the superklass. Set a hidden internal cache on a
12862 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12863 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12864 instruct partialSubtypeCheck( mRegP result, no_T8_mRegP sub, no_T8_mRegP super, mT8RegI tmp ) %{
12865 match(Set result (PartialSubtypeCheck sub super));
12866 effect(KILL tmp);
12867 ins_cost(1100); // slightly larger than the next version
12868 format %{ "partialSubtypeCheck result=$result, sub=$sub, super=$super, tmp=$tmp " %}
12870 ins_encode( enc_PartialSubtypeCheck(result, sub, super, tmp) );
12871 ins_pipe( pipe_slow );
12872 %}
12875 // Conditional-store of an int value.
12876 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
12877 instruct storeIConditional( memory mem, mRegI oldval, mRegI newval, FlagsReg cr ) %{
12878 match(Set cr (StoreIConditional mem (Binary oldval newval)));
12879 // effect(KILL oldval);
12880 format %{ "CMPXCHG $newval, $mem, $oldval \t# @storeIConditional" %}
12882 ins_encode %{
12883 Register oldval = $oldval$$Register;
12884 Register newval = $newval$$Register;
12885 Address addr(as_Register($mem$$base), $mem$$disp);
12886 Label again, failure;
12888 // int base = $mem$$base;
12889 int index = $mem$$index;
12890 int scale = $mem$$scale;
12891 int disp = $mem$$disp;
12893 guarantee(Assembler::is_simm16(disp), "");
12895 if( index != 0 ) {
12896 __ stop("in storeIConditional: index != 0");
12897 } else {
12898 __ bind(again);
12899 if(!Use3A2000) __ sync();
12900 __ ll(AT, addr);
12901 __ bne(AT, oldval, failure);
12902 __ delayed()->addu(AT, R0, R0);
12904 __ addu(AT, newval, R0);
12905 __ sc(AT, addr);
12906 __ beq(AT, R0, again);
12907 __ delayed()->addiu(AT, R0, 0xFF);
12908 __ bind(failure);
12909 __ sync();
12910 }
12911 %}
12913 ins_pipe( long_memory_op );
12914 %}
12916 // Conditional-store of a long value.
12917 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
12918 instruct storeLConditional(memory mem, t2RegL oldval, mRegL newval, FlagsReg cr )
12919 %{
12920 match(Set cr (StoreLConditional mem (Binary oldval newval)));
12921 effect(KILL oldval);
12923 format %{ "cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %}
12924 ins_encode%{
12925 Register oldval = $oldval$$Register;
12926 Register newval = $newval$$Register;
12927 Address addr((Register)$mem$$base, $mem$$disp);
12929 int index = $mem$$index;
12930 int scale = $mem$$scale;
12931 int disp = $mem$$disp;
12933 guarantee(Assembler::is_simm16(disp), "");
12935 if( index != 0 ) {
12936 __ stop("in storeIConditional: index != 0");
12937 } else {
12938 __ cmpxchg(newval, addr, oldval);
12939 }
12940 %}
12941 ins_pipe( long_memory_op );
12942 %}
12945 instruct compareAndSwapI( mRegI res, mRegP mem_ptr, mS2RegI oldval, mRegI newval) %{
12946 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
12947 effect(KILL oldval);
12948 // match(CompareAndSwapI mem_ptr (Binary oldval newval));
12949 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapI\n\t"
12950 "MOV $res, 1 @ compareAndSwapI\n\t"
12951 "BNE AT, R0 @ compareAndSwapI\n\t"
12952 "MOV $res, 0 @ compareAndSwapI\n"
12953 "L:" %}
12954 ins_encode %{
12955 Register newval = $newval$$Register;
12956 Register oldval = $oldval$$Register;
12957 Register res = $res$$Register;
12958 Address addr($mem_ptr$$Register, 0);
12959 Label L;
12961 __ cmpxchg32(newval, addr, oldval);
12962 __ move(res, AT);
12963 %}
12964 ins_pipe( long_memory_op );
12965 %}
12967 //FIXME:
12968 instruct compareAndSwapP( mRegI res, mRegP mem_ptr, s2_RegP oldval, mRegP newval) %{
12969 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
12970 effect(KILL oldval);
12971 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapP\n\t"
12972 "MOV $res, AT @ compareAndSwapP\n\t"
12973 "L:" %}
12974 ins_encode %{
12975 Register newval = $newval$$Register;
12976 Register oldval = $oldval$$Register;
12977 Register res = $res$$Register;
12978 Address addr($mem_ptr$$Register, 0);
12979 Label L;
12981 __ cmpxchg(newval, addr, oldval);
12982 __ move(res, AT);
12983 %}
12984 ins_pipe( long_memory_op );
12985 %}
12987 instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval) %{
12988 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
12989 effect(KILL oldval);
12990 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapN\n\t"
12991 "MOV $res, AT @ compareAndSwapN\n\t"
12992 "L:" %}
12993 ins_encode %{
12994 Register newval = $newval$$Register;
12995 Register oldval = $oldval$$Register;
12996 Register res = $res$$Register;
12997 Address addr($mem_ptr$$Register, 0);
12998 Label L;
13000 /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
13001 * Thus, we should extend oldval's sign for correct comparision.
13002 */
13003 __ sll(oldval, oldval, 0);
13005 __ cmpxchg32(newval, addr, oldval);
13006 __ move(res, AT);
13007 %}
13008 ins_pipe( long_memory_op );
13009 %}
13011 //----------Max and Min--------------------------------------------------------
13012 // Min Instructions
13013 ////
13014 // *** Min and Max using the conditional move are slower than the
13015 // *** branch version on a Pentium III.
13016 // // Conditional move for min
13017 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13018 // effect( USE_DEF op2, USE op1, USE cr );
13019 // format %{ "CMOVlt $op2,$op1\t! min" %}
13020 // opcode(0x4C,0x0F);
13021 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13022 // ins_pipe( pipe_cmov_reg );
13023 //%}
13024 //
13025 //// Min Register with Register (P6 version)
13026 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
13027 // predicate(VM_Version::supports_cmov() );
13028 // match(Set op2 (MinI op1 op2));
13029 // ins_cost(200);
13030 // expand %{
13031 // eFlagsReg cr;
13032 // compI_eReg(cr,op1,op2);
13033 // cmovI_reg_lt(op2,op1,cr);
13034 // %}
13035 //%}
13037 // Min Register with Register (generic version)
13038 instruct minI_Reg_Reg(mRegI dst, mRegI src) %{
13039 match(Set dst (MinI dst src));
13040 //effect(KILL flags);
13041 ins_cost(80);
13043 format %{ "MIN $dst, $src @minI_Reg_Reg" %}
13044 ins_encode %{
13045 Register dst = $dst$$Register;
13046 Register src = $src$$Register;
13048 __ slt(AT, src, dst);
13049 __ movn(dst, src, AT);
13051 %}
13053 ins_pipe( pipe_slow );
13054 %}
13056 // Max Register with Register
13057 // *** Min and Max using the conditional move are slower than the
13058 // *** branch version on a Pentium III.
13059 // // Conditional move for max
13060 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13061 // effect( USE_DEF op2, USE op1, USE cr );
13062 // format %{ "CMOVgt $op2,$op1\t! max" %}
13063 // opcode(0x4F,0x0F);
13064 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13065 // ins_pipe( pipe_cmov_reg );
13066 //%}
13067 //
13068 // // Max Register with Register (P6 version)
13069 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
13070 // predicate(VM_Version::supports_cmov() );
13071 // match(Set op2 (MaxI op1 op2));
13072 // ins_cost(200);
13073 // expand %{
13074 // eFlagsReg cr;
13075 // compI_eReg(cr,op1,op2);
13076 // cmovI_reg_gt(op2,op1,cr);
13077 // %}
13078 //%}
13080 // Max Register with Register (generic version)
13081 instruct maxI_Reg_Reg(mRegI dst, mRegI src) %{
13082 match(Set dst (MaxI dst src));
13083 ins_cost(80);
13085 format %{ "MAX $dst, $src @maxI_Reg_Reg" %}
13087 ins_encode %{
13088 Register dst = $dst$$Register;
13089 Register src = $src$$Register;
13091 __ slt(AT, dst, src);
13092 __ movn(dst, src, AT);
13094 %}
13096 ins_pipe( pipe_slow );
13097 %}
13099 instruct maxI_Reg_zero(mRegI dst, immI0 zero) %{
13100 match(Set dst (MaxI dst zero));
13101 ins_cost(50);
13103 format %{ "MAX $dst, 0 @maxI_Reg_zero" %}
13105 ins_encode %{
13106 Register dst = $dst$$Register;
13108 __ slt(AT, dst, R0);
13109 __ movn(dst, R0, AT);
13111 %}
13113 ins_pipe( pipe_slow );
13114 %}
13116 instruct zerox_long_reg_reg(mRegL dst, mRegL src, immL_32bits mask)
13117 %{
13118 match(Set dst (AndL src mask));
13120 format %{ "movl $dst, $src\t# zero-extend long @ zerox_long_reg_reg" %}
13121 ins_encode %{
13122 Register dst = $dst$$Register;
13123 Register src = $src$$Register;
13125 __ dext(dst, src, 0, 32);
13126 %}
13127 ins_pipe(ialu_regI_regI);
13128 %}
13130 instruct combine_i2l(mRegL dst, mRegI src1, immL_32bits mask, mRegI src2, immI_32 shift32)
13131 %{
13132 match(Set dst (OrL (AndL (ConvI2L src1) mask) (LShiftL (ConvI2L src2) shift32)));
13134 format %{ "combine_i2l $dst, $src2(H), $src1(L) @ combine_i2l" %}
13135 ins_encode %{
13136 Register dst = $dst$$Register;
13137 Register src1 = $src1$$Register;
13138 Register src2 = $src2$$Register;
13140 if (src1 == dst) {
13141 __ dinsu(dst, src2, 32, 32);
13142 } else if (src2 == dst) {
13143 __ dsll32(dst, dst, 0);
13144 __ dins(dst, src1, 0, 32);
13145 } else {
13146 __ dext(dst, src1, 0, 32);
13147 __ dinsu(dst, src2, 32, 32);
13148 }
13149 %}
13150 ins_pipe(ialu_regI_regI);
13151 %}
13153 // Zero-extend convert int to long
13154 instruct convI2L_reg_reg_zex(mRegL dst, mRegI src, immL_32bits mask)
13155 %{
13156 match(Set dst (AndL (ConvI2L src) mask));
13158 format %{ "movl $dst, $src\t# i2l zero-extend @ convI2L_reg_reg_zex" %}
13159 ins_encode %{
13160 Register dst = $dst$$Register;
13161 Register src = $src$$Register;
13163 __ dext(dst, src, 0, 32);
13164 %}
13165 ins_pipe(ialu_regI_regI);
13166 %}
13168 instruct convL2I2L_reg_reg_zex(mRegL dst, mRegL src, immL_32bits mask)
13169 %{
13170 match(Set dst (AndL (ConvI2L (ConvL2I src)) mask));
13172 format %{ "movl $dst, $src\t# i2l zero-extend @ convL2I2L_reg_reg_zex" %}
13173 ins_encode %{
13174 Register dst = $dst$$Register;
13175 Register src = $src$$Register;
13177 __ dext(dst, src, 0, 32);
13178 %}
13179 ins_pipe(ialu_regI_regI);
13180 %}
13182 // Match loading integer and casting it to unsigned int in long register.
13183 // LoadI + ConvI2L + AndL 0xffffffff.
13184 instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{
13185 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
13187 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %}
13188 ins_encode (load_N_enc(dst, mem));
13189 ins_pipe(ialu_loadI);
13190 %}
13192 instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{
13193 match(Set dst (AndL mask (ConvI2L (LoadI mem))));
13195 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %}
13196 ins_encode (load_N_enc(dst, mem));
13197 ins_pipe(ialu_loadI);
13198 %}
13201 // ============================================================================
13202 // Safepoint Instruction
13203 instruct safePoint_poll_reg(mRegP poll) %{
13204 match(SafePoint poll);
13205 predicate(false);
13206 effect(USE poll);
13208 ins_cost(125);
13209 format %{ "Safepoint @ [$poll] : poll for GC @ safePoint_poll_reg" %}
13211 ins_encode %{
13212 Register poll_reg = $poll$$Register;
13214 __ block_comment("Safepoint:");
13215 __ relocate(relocInfo::poll_type);
13216 __ lw(AT, poll_reg, 0);
13217 %}
13219 ins_pipe( ialu_storeI );
13220 %}
13222 instruct safePoint_poll() %{
13223 match(SafePoint);
13225 ins_cost(105);
13226 format %{ "poll for GC @ safePoint_poll" %}
13228 ins_encode %{
13229 __ block_comment("Safepoint:");
13230 __ set64(T9, (long)os::get_polling_page());
13231 __ relocate(relocInfo::poll_type);
13232 __ lw(AT, T9, 0);
13233 %}
13235 ins_pipe( ialu_storeI );
13236 %}
13238 //----------Arithmetic Conversion Instructions---------------------------------
13240 instruct roundFloat_nop(regF dst)
13241 %{
13242 match(Set dst (RoundFloat dst));
13244 ins_cost(0);
13245 ins_encode();
13246 ins_pipe(empty);
13247 %}
13249 instruct roundDouble_nop(regD dst)
13250 %{
13251 match(Set dst (RoundDouble dst));
13253 ins_cost(0);
13254 ins_encode();
13255 ins_pipe(empty);
13256 %}
13258 //---------- Zeros Count Instructions ------------------------------------------
13259 // CountLeadingZerosINode CountTrailingZerosINode
13260 instruct countLeadingZerosI(mRegI dst, mRegI src) %{
13261 predicate(UseCountLeadingZerosInstruction);
13262 match(Set dst (CountLeadingZerosI src));
13264 format %{ "clz $dst, $src\t# count leading zeros (int)" %}
13265 ins_encode %{
13266 __ clz($dst$$Register, $src$$Register);
13267 %}
13268 ins_pipe( ialu_regL_regL );
13269 %}
13271 instruct countLeadingZerosL(mRegI dst, mRegL src) %{
13272 predicate(UseCountLeadingZerosInstruction);
13273 match(Set dst (CountLeadingZerosL src));
13275 format %{ "dclz $dst, $src\t# count leading zeros (long)" %}
13276 ins_encode %{
13277 __ dclz($dst$$Register, $src$$Register);
13278 %}
13279 ins_pipe( ialu_regL_regL );
13280 %}
13282 instruct countTrailingZerosI(mRegI dst, mRegI src) %{
13283 predicate(UseCountTrailingZerosInstruction);
13284 match(Set dst (CountTrailingZerosI src));
13286 format %{ "ctz $dst, $src\t# count trailing zeros (int)" %}
13287 ins_encode %{
13288 // ctz and dctz is gs instructions.
13289 __ ctz($dst$$Register, $src$$Register);
13290 %}
13291 ins_pipe( ialu_regL_regL );
13292 %}
13294 instruct countTrailingZerosL(mRegI dst, mRegL src) %{
13295 predicate(UseCountTrailingZerosInstruction);
13296 match(Set dst (CountTrailingZerosL src));
13298 format %{ "dcto $dst, $src\t# count trailing zeros (long)" %}
13299 ins_encode %{
13300 __ dctz($dst$$Register, $src$$Register);
13301 %}
13302 ins_pipe( ialu_regL_regL );
13303 %}
13305 // ====================VECTOR INSTRUCTIONS=====================================
13307 // Load vectors (8 bytes long)
13308 instruct loadV8(vecD dst, memory mem) %{
13309 predicate(n->as_LoadVector()->memory_size() == 8);
13310 match(Set dst (LoadVector mem));
13311 ins_cost(125);
13312 format %{ "load $dst, $mem\t! load vector (8 bytes)" %}
13313 ins_encode(load_D_enc(dst, mem));
13314 ins_pipe( fpu_loadF );
13315 %}
13317 // Store vectors (8 bytes long)
13318 instruct storeV8(memory mem, vecD src) %{
13319 predicate(n->as_StoreVector()->memory_size() == 8);
13320 match(Set mem (StoreVector mem src));
13321 ins_cost(145);
13322 format %{ "store $mem, $src\t! store vector (8 bytes)" %}
13323 ins_encode(store_D_reg_enc(mem, src));
13324 ins_pipe( fpu_storeF );
13325 %}
13327 instruct Repl8B_DSP(vecD dst, mRegI src) %{
13328 predicate(n->as_Vector()->length() == 8 && Use3A2000);
13329 match(Set dst (ReplicateB src));
13330 ins_cost(100);
13331 format %{ "replv_ob AT, $src\n\t"
13332 "dmtc1 AT, $dst\t! replicate8B" %}
13333 ins_encode %{
13334 __ replv_ob(AT, $src$$Register);
13335 __ dmtc1(AT, $dst$$FloatRegister);
13336 %}
13337 ins_pipe( pipe_mtc1 );
13338 %}
13340 instruct Repl8B(vecD dst, mRegI src) %{
13341 predicate(n->as_Vector()->length() == 8);
13342 match(Set dst (ReplicateB src));
13343 ins_cost(140);
13344 format %{ "move AT, $src\n\t"
13345 "dins AT, AT, 8, 8\n\t"
13346 "dins AT, AT, 16, 16\n\t"
13347 "dinsu AT, AT, 32, 32\n\t"
13348 "dmtc1 AT, $dst\t! replicate8B" %}
13349 ins_encode %{
13350 __ move(AT, $src$$Register);
13351 __ dins(AT, AT, 8, 8);
13352 __ dins(AT, AT, 16, 16);
13353 __ dinsu(AT, AT, 32, 32);
13354 __ dmtc1(AT, $dst$$FloatRegister);
13355 %}
13356 ins_pipe( pipe_mtc1 );
13357 %}
13359 instruct Repl8B_imm_DSP(vecD dst, immI con) %{
13360 predicate(n->as_Vector()->length() == 8 && Use3A2000);
13361 match(Set dst (ReplicateB con));
13362 ins_cost(110);
13363 format %{ "repl_ob AT, [$con]\n\t"
13364 "dmtc1 AT, $dst,0x00\t! replicate8B($con)" %}
13365 ins_encode %{
13366 int val = $con$$constant;
13367 __ repl_ob(AT, val);
13368 __ dmtc1(AT, $dst$$FloatRegister);
13369 %}
13370 ins_pipe( pipe_mtc1 );
13371 %}
13373 instruct Repl8B_imm(vecD dst, immI con) %{
13374 predicate(n->as_Vector()->length() == 8);
13375 match(Set dst (ReplicateB con));
13376 ins_cost(150);
13377 format %{ "move AT, [$con]\n\t"
13378 "dins AT, AT, 8, 8\n\t"
13379 "dins AT, AT, 16, 16\n\t"
13380 "dinsu AT, AT, 32, 32\n\t"
13381 "dmtc1 AT, $dst,0x00\t! replicate8B($con)" %}
13382 ins_encode %{
13383 __ move(AT, $con$$constant);
13384 __ dins(AT, AT, 8, 8);
13385 __ dins(AT, AT, 16, 16);
13386 __ dinsu(AT, AT, 32, 32);
13387 __ dmtc1(AT, $dst$$FloatRegister);
13388 %}
13389 ins_pipe( pipe_mtc1 );
13390 %}
13392 instruct Repl8B_zero(vecD dst, immI0 zero) %{
13393 predicate(n->as_Vector()->length() == 8);
13394 match(Set dst (ReplicateB zero));
13395 ins_cost(90);
13396 format %{ "dmtc1 R0, $dst\t! replicate8B zero" %}
13397 ins_encode %{
13398 __ dmtc1(R0, $dst$$FloatRegister);
13399 %}
13400 ins_pipe( pipe_mtc1 );
13401 %}
13403 instruct Repl8B_M1(vecD dst, immI_M1 M1) %{
13404 predicate(n->as_Vector()->length() == 8);
13405 match(Set dst (ReplicateB M1));
13406 ins_cost(80);
13407 format %{ "dmtc1 -1, $dst\t! replicate8B -1" %}
13408 ins_encode %{
13409 __ nor(AT, R0, R0);
13410 __ dmtc1(AT, $dst$$FloatRegister);
13411 %}
13412 ins_pipe( pipe_mtc1 );
13413 %}
13415 instruct Repl4S_DSP(vecD dst, mRegI src) %{
13416 predicate(n->as_Vector()->length() == 4 && Use3A2000);
13417 match(Set dst (ReplicateS src));
13418 ins_cost(100);
13419 format %{ "replv_qh AT, $src\n\t"
13420 "dmtc1 AT, $dst\t! replicate4S" %}
13421 ins_encode %{
13422 __ replv_qh(AT, $src$$Register);
13423 __ dmtc1(AT, $dst$$FloatRegister);
13424 %}
13425 ins_pipe( pipe_mtc1 );
13426 %}
13428 instruct Repl4S(vecD dst, mRegI src) %{
13429 predicate(n->as_Vector()->length() == 4);
13430 match(Set dst (ReplicateS src));
13431 ins_cost(120);
13432 format %{ "move AT, $src \n\t"
13433 "dins AT, AT, 16, 16\n\t"
13434 "dinsu AT, AT, 32, 32\n\t"
13435 "dmtc1 AT, $dst\t! replicate4S" %}
13436 ins_encode %{
13437 __ move(AT, $src$$Register);
13438 __ dins(AT, AT, 16, 16);
13439 __ dinsu(AT, AT, 32, 32);
13440 __ dmtc1(AT, $dst$$FloatRegister);
13441 %}
13442 ins_pipe( pipe_mtc1 );
13443 %}
13445 instruct Repl4S_imm_DSP(vecD dst, immI con) %{
13446 predicate(n->as_Vector()->length() == 4 && Use3A2000);
13447 match(Set dst (ReplicateS con));
13448 ins_cost(100);
13449 format %{ "replv_qh AT, [$con]\n\t"
13450 "dmtc1 AT, $dst\t! replicate4S($con)" %}
13451 ins_encode %{
13452 int val = $con$$constant;
13453 if ( Assembler::is_simm(val, 10)) {
13454 //repl_qh supports 10 bits immediate
13455 __ repl_qh(AT, val);
13456 } else {
13457 __ li32(AT, val);
13458 __ replv_qh(AT, AT);
13459 }
13460 __ dmtc1(AT, $dst$$FloatRegister);
13461 %}
13462 ins_pipe( pipe_mtc1 );
13463 %}
13465 instruct Repl4S_imm(vecD dst, immI con) %{
13466 predicate(n->as_Vector()->length() == 4);
13467 match(Set dst (ReplicateS con));
13468 ins_cost(110);
13469 format %{ "move AT, [$con]\n\t"
13470 "dins AT, AT, 16, 16\n\t"
13471 "dinsu AT, AT, 32, 32\n\t"
13472 "dmtc1 AT, $dst\t! replicate4S($con)" %}
13473 ins_encode %{
13474 __ move(AT, $con$$constant);
13475 __ dins(AT, AT, 16, 16);
13476 __ dinsu(AT, AT, 32, 32);
13477 __ dmtc1(AT, $dst$$FloatRegister);
13478 %}
13479 ins_pipe( pipe_mtc1 );
13480 %}
13482 instruct Repl4S_zero(vecD dst, immI0 zero) %{
13483 predicate(n->as_Vector()->length() == 4);
13484 match(Set dst (ReplicateS zero));
13485 format %{ "dmtc1 R0, $dst\t! replicate4S zero" %}
13486 ins_encode %{
13487 __ dmtc1(R0, $dst$$FloatRegister);
13488 %}
13489 ins_pipe( pipe_mtc1 );
13490 %}
13492 instruct Repl4S_M1(vecD dst, immI_M1 M1) %{
13493 predicate(n->as_Vector()->length() == 4);
13494 match(Set dst (ReplicateS M1));
13495 format %{ "dmtc1 -1, $dst\t! replicate4S -1" %}
13496 ins_encode %{
13497 __ nor(AT, R0, R0);
13498 __ dmtc1(AT, $dst$$FloatRegister);
13499 %}
13500 ins_pipe( pipe_mtc1 );
13501 %}
13503 // Replicate integer (4 byte) scalar to be vector
13504 instruct Repl2I(vecD dst, mRegI src) %{
13505 predicate(n->as_Vector()->length() == 2);
13506 match(Set dst (ReplicateI src));
13507 format %{ "dins AT, $src, 0, 32\n\t"
13508 "dinsu AT, $src, 32, 32\n\t"
13509 "dmtc1 AT, $dst\t! replicate2I" %}
13510 ins_encode %{
13511 __ dins(AT, $src$$Register, 0, 32);
13512 __ dinsu(AT, $src$$Register, 32, 32);
13513 __ dmtc1(AT, $dst$$FloatRegister);
13514 %}
13515 ins_pipe( pipe_mtc1 );
13516 %}
13518 // Replicate integer (4 byte) scalar immediate to be vector by loading from const table.
13519 instruct Repl2I_imm(vecD dst, immI con, mA7RegI tmp) %{
13520 predicate(n->as_Vector()->length() == 2);
13521 match(Set dst (ReplicateI con));
13522 effect(KILL tmp);
13523 format %{ "li32 AT, [$con], 32\n\t"
13524 "dinsu AT, AT\n\t"
13525 "dmtc1 AT, $dst\t! replicate2I($con)" %}
13526 ins_encode %{
13527 int val = $con$$constant;
13528 __ li32(AT, val);
13529 __ dinsu(AT, AT, 32, 32);
13530 __ dmtc1(AT, $dst$$FloatRegister);
13531 %}
13532 ins_pipe( pipe_mtc1 );
13533 %}
13535 // Replicate integer (4 byte) scalar zero to be vector
13536 instruct Repl2I_zero(vecD dst, immI0 zero) %{
13537 predicate(n->as_Vector()->length() == 2);
13538 match(Set dst (ReplicateI zero));
13539 format %{ "dmtc1 R0, $dst\t! replicate2I zero" %}
13540 ins_encode %{
13541 __ dmtc1(R0, $dst$$FloatRegister);
13542 %}
13543 ins_pipe( pipe_mtc1 );
13544 %}
13546 // Replicate integer (4 byte) scalar -1 to be vector
13547 instruct Repl2I_M1(vecD dst, immI_M1 M1) %{
13548 predicate(n->as_Vector()->length() == 2);
13549 match(Set dst (ReplicateI M1));
13550 format %{ "dmtc1 -1, $dst\t! replicate2I -1, use AT" %}
13551 ins_encode %{
13552 __ nor(AT, R0, R0);
13553 __ dmtc1(AT, $dst$$FloatRegister);
13554 %}
13555 ins_pipe( pipe_mtc1 );
13556 %}
13558 // Replicate float (4 byte) scalar to be vector
13559 instruct Repl2F(vecD dst, regF src) %{
13560 predicate(n->as_Vector()->length() == 2);
13561 match(Set dst (ReplicateF src));
13562 format %{ "cvt.ps $dst, $src, $src\t! replicate2F" %}
13563 ins_encode %{
13564 __ cvt_ps_s($dst$$FloatRegister, $src$$FloatRegister, $src$$FloatRegister);
13565 %}
13566 ins_pipe( pipe_slow );
13567 %}
13569 // Replicate float (4 byte) scalar zero to be vector
13570 instruct Repl2F_zero(vecD dst, immF0 zero) %{
13571 predicate(n->as_Vector()->length() == 2);
13572 match(Set dst (ReplicateF zero));
13573 format %{ "dmtc1 R0, $dst\t! replicate2F zero" %}
13574 ins_encode %{
13575 __ dmtc1(R0, $dst$$FloatRegister);
13576 %}
13577 ins_pipe( pipe_mtc1 );
13578 %}
13581 // ====================VECTOR ARITHMETIC=======================================
13583 // --------------------------------- ADD --------------------------------------
13585 // Floats vector add
13586 // kernel does not have emulation of PS instructions yet, so PS instructions is disabled.
13587 instruct vadd2F(vecD dst, vecD src) %{
13588 predicate(n->as_Vector()->length() == 2);
13589 match(Set dst (AddVF dst src));
13590 format %{ "add.ps $dst,$src\t! add packed2F" %}
13591 ins_encode %{
13592 __ add_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13593 %}
13594 ins_pipe( pipe_slow );
13595 %}
13597 instruct vadd2F3(vecD dst, vecD src1, vecD src2) %{
13598 predicate(n->as_Vector()->length() == 2);
13599 match(Set dst (AddVF src1 src2));
13600 format %{ "add.ps $dst,$src1,$src2\t! add packed2F" %}
13601 ins_encode %{
13602 __ add_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13603 %}
13604 ins_pipe( fpu_regF_regF );
13605 %}
13607 // --------------------------------- SUB --------------------------------------
13609 // Floats vector sub
13610 instruct vsub2F(vecD dst, vecD src) %{
13611 predicate(n->as_Vector()->length() == 2);
13612 match(Set dst (SubVF dst src));
13613 format %{ "sub.ps $dst,$src\t! sub packed2F" %}
13614 ins_encode %{
13615 __ sub_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13616 %}
13617 ins_pipe( fpu_regF_regF );
13618 %}
13620 // --------------------------------- MUL --------------------------------------
13622 // Floats vector mul
13623 instruct vmul2F(vecD dst, vecD src) %{
13624 predicate(n->as_Vector()->length() == 2);
13625 match(Set dst (MulVF dst src));
13626 format %{ "mul.ps $dst, $src\t! mul packed2F" %}
13627 ins_encode %{
13628 __ mul_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13629 %}
13630 ins_pipe( fpu_regF_regF );
13631 %}
13633 instruct vmul2F3(vecD dst, vecD src1, vecD src2) %{
13634 predicate(n->as_Vector()->length() == 2);
13635 match(Set dst (MulVF src1 src2));
13636 format %{ "mul.ps $dst, $src1, $src2\t! mul packed2F" %}
13637 ins_encode %{
13638 __ mul_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13639 %}
13640 ins_pipe( fpu_regF_regF );
13641 %}
13643 // --------------------------------- DIV --------------------------------------
13644 // MIPS do not have div.ps
13646 // --------------------------------- MADD --------------------------------------
13647 // Floats vector madd
13648 //instruct vmadd2F(vecD dst, vecD src1, vecD src2, vecD src3) %{
13649 // predicate(n->as_Vector()->length() == 2);
13650 // match(Set dst (AddVF (MulVF src1 src2) src3));
13651 // ins_cost(50);
13652 // format %{ "madd.ps $dst, $src3, $src1, $src2\t! madd packed2F" %}
13653 // ins_encode %{
13654 // __ madd_ps($dst$$FloatRegister, $src3$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13655 // %}
13656 // ins_pipe( fpu_regF_regF );
13657 //%}
13660 //----------PEEPHOLE RULES-----------------------------------------------------
13661 // These must follow all instruction definitions as they use the names
13662 // defined in the instructions definitions.
13663 //
13664 // peepmatch ( root_instr_name [preceeding_instruction]* );
13665 //
13666 // peepconstraint %{
13667 // (instruction_number.operand_name relational_op instruction_number.operand_name
13668 // [, ...] );
13669 // // instruction numbers are zero-based using left to right order in peepmatch
13670 //
13671 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13672 // // provide an instruction_number.operand_name for each operand that appears
13673 // // in the replacement instruction's match rule
13674 //
13675 // ---------VM FLAGS---------------------------------------------------------
13676 //
13677 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13678 //
13679 // Each peephole rule is given an identifying number starting with zero and
13680 // increasing by one in the order seen by the parser. An individual peephole
13681 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13682 // on the command-line.
13683 //
13684 // ---------CURRENT LIMITATIONS----------------------------------------------
13685 //
13686 // Only match adjacent instructions in same basic block
13687 // Only equality constraints
13688 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13689 // Only one replacement instruction
13690 //
13691 // ---------EXAMPLE----------------------------------------------------------
13692 //
13693 // // pertinent parts of existing instructions in architecture description
13694 // instruct movI(eRegI dst, eRegI src) %{
13695 // match(Set dst (CopyI src));
13696 // %}
13697 //
13698 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13699 // match(Set dst (AddI dst src));
13700 // effect(KILL cr);
13701 // %}
13702 //
13703 // // Change (inc mov) to lea
13704 // peephole %{
13705 // // increment preceeded by register-register move
13706 // peepmatch ( incI_eReg movI );
13707 // // require that the destination register of the increment
13708 // // match the destination register of the move
13709 // peepconstraint ( 0.dst == 1.dst );
13710 // // construct a replacement instruction that sets
13711 // // the destination to ( move's source register + one )
13712 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13713 // %}
13714 //
13715 // Implementation no longer uses movX instructions since
13716 // machine-independent system no longer uses CopyX nodes.
13717 //
13718 // peephole %{
13719 // peepmatch ( incI_eReg movI );
13720 // peepconstraint ( 0.dst == 1.dst );
13721 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13722 // %}
13723 //
13724 // peephole %{
13725 // peepmatch ( decI_eReg movI );
13726 // peepconstraint ( 0.dst == 1.dst );
13727 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13728 // %}
13729 //
13730 // peephole %{
13731 // peepmatch ( addI_eReg_imm movI );
13732 // peepconstraint ( 0.dst == 1.dst );
13733 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13734 // %}
13735 //
13736 // peephole %{
13737 // peepmatch ( addP_eReg_imm movP );
13738 // peepconstraint ( 0.dst == 1.dst );
13739 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13740 // %}
13742 // // Change load of spilled value to only a spill
13743 // instruct storeI(memory mem, eRegI src) %{
13744 // match(Set mem (StoreI mem src));
13745 // %}
13746 //
13747 // instruct loadI(eRegI dst, memory mem) %{
13748 // match(Set dst (LoadI mem));
13749 // %}
13750 //
13751 //peephole %{
13752 // peepmatch ( loadI storeI );
13753 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13754 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13755 //%}
13757 //----------SMARTSPILL RULES---------------------------------------------------
13758 // These must follow all instruction definitions as they use the names
13759 // defined in the instructions definitions.
