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src/share/vm/c1/c1_LIR.cpp@a738a625039a
src/share/vm/c1/c1_LIR.cpp
Fri, 12 Dec 2008 19:54:46 -0800
- author
- never
- date
- Fri, 12 Dec 2008 19:54:46 -0800
- changeset 921
- a738a625039a
- parent 739
- dc7f315e41f7
- child 1388
- ff1a29907b6c
- permissions
- -rw-r--r--
6757316: load_constant() produces a wrong long constant, with high a low words swapped
Reviewed-by: rasbold, jrose, kvn
1 /*
2 * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIR.cpp.incl"
28 Register LIR_OprDesc::as_register() const {
29 return FrameMap::cpu_rnr2reg(cpu_regnr());
30 }
32 Register LIR_OprDesc::as_register_lo() const {
33 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
34 }
36 Register LIR_OprDesc::as_register_hi() const {
37 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
38 }
40 #if defined(X86)
42 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
43 return FrameMap::nr2xmmreg(xmm_regnr());
44 }
46 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
47 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
48 return FrameMap::nr2xmmreg(xmm_regnrLo());
49 }
51 #endif // X86
54 #ifdef SPARC
56 FloatRegister LIR_OprDesc::as_float_reg() const {
57 return FrameMap::nr2floatreg(fpu_regnr());
58 }
60 FloatRegister LIR_OprDesc::as_double_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnrHi());
62 }
64 #endif
66 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
68 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
69 ValueTag tag = type->tag();
70 switch (tag) {
71 case objectTag : {
72 ClassConstant* c = type->as_ClassConstant();
73 if (c != NULL && !c->value()->is_loaded()) {
74 return LIR_OprFact::oopConst(NULL);
75 } else {
76 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
77 }
78 }
79 case addressTag: return LIR_OprFact::intConst(type->as_AddressConstant()->value());
80 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
81 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
82 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
83 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
84 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
85 }
86 }
89 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
90 switch (type->tag()) {
91 case objectTag: return LIR_OprFact::oopConst(NULL);
92 case addressTag:
93 case intTag: return LIR_OprFact::intConst(0);
94 case floatTag: return LIR_OprFact::floatConst(0.0);
95 case longTag: return LIR_OprFact::longConst(0);
96 case doubleTag: return LIR_OprFact::doubleConst(0.0);
97 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
98 }
99 return illegalOpr;
100 }
104 //---------------------------------------------------
107 LIR_Address::Scale LIR_Address::scale(BasicType type) {
108 int elem_size = type2aelembytes(type);
109 switch (elem_size) {
110 case 1: return LIR_Address::times_1;
111 case 2: return LIR_Address::times_2;
112 case 4: return LIR_Address::times_4;
113 case 8: return LIR_Address::times_8;
114 }
115 ShouldNotReachHere();
116 return LIR_Address::times_1;
117 }
120 #ifndef PRODUCT
121 void LIR_Address::verify() const {
122 #ifdef SPARC
123 assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used");
124 assert(disp() == 0 || index()->is_illegal(), "can't have both");
125 #endif
126 #ifdef _LP64
127 assert(base()->is_cpu_register(), "wrong base operand");
128 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
129 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
130 "wrong type for addresses");
131 #else
132 assert(base()->is_single_cpu(), "wrong base operand");
133 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
134 assert(base()->type() == T_OBJECT || base()->type() == T_INT,
135 "wrong type for addresses");
136 #endif
137 }
138 #endif
141 //---------------------------------------------------
143 char LIR_OprDesc::type_char(BasicType t) {
144 switch (t) {
145 case T_ARRAY:
146 t = T_OBJECT;
147 case T_BOOLEAN:
148 case T_CHAR:
149 case T_FLOAT:
150 case T_DOUBLE:
151 case T_BYTE:
152 case T_SHORT:
153 case T_INT:
154 case T_LONG:
155 case T_OBJECT:
156 case T_ADDRESS:
157 case T_VOID:
158 return ::type2char(t);
160 case T_ILLEGAL:
161 return '?';
163 default:
164 ShouldNotReachHere();
165 return '?';
166 }
167 }
169 #ifndef PRODUCT
170 void LIR_OprDesc::validate_type() const {
172 #ifdef ASSERT
173 if (!is_pointer() && !is_illegal()) {
174 switch (as_BasicType(type_field())) {
175 case T_LONG:
176 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == double_size, "must match");
177 break;
178 case T_FLOAT:
179 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == single_size, "must match");
180 break;
181 case T_DOUBLE:
182 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == double_size, "must match");
183 break;
184 case T_BOOLEAN:
185 case T_CHAR:
186 case T_BYTE:
187 case T_SHORT:
188 case T_INT:
189 case T_OBJECT:
190 case T_ARRAY:
191 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == single_size, "must match");
192 break;
194 case T_ILLEGAL:
195 // XXX TKR also means unknown right now
196 // assert(is_illegal(), "must match");
197 break;
199 default:
200 ShouldNotReachHere();
201 }
202 }
203 #endif
205 }
206 #endif // PRODUCT
209 bool LIR_OprDesc::is_oop() const {
210 if (is_pointer()) {
211 return pointer()->is_oop_pointer();
212 } else {
213 OprType t= type_field();
214 assert(t != unknown_type, "not set");
215 return t == object_type;
216 }
217 }
221 void LIR_Op2::verify() const {
222 #ifdef ASSERT
223 switch (code()) {
224 case lir_cmove:
225 break;
227 default:
228 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
229 "can't produce oops from arith");
230 }
232 if (TwoOperandLIRForm) {
233 switch (code()) {
234 case lir_add:
235 case lir_sub:
236 case lir_mul:
237 case lir_mul_strictfp:
238 case lir_div:
239 case lir_div_strictfp:
240 case lir_rem:
241 case lir_logic_and:
242 case lir_logic_or:
243 case lir_logic_xor:
244 case lir_shl:
245 case lir_shr:
246 assert(in_opr1() == result_opr(), "opr1 and result must match");
247 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
248 break;
250 // special handling for lir_ushr because of write barriers
251 case lir_ushr:
252 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
253 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
254 break;
256 }
257 }
258 #endif
259 }
262 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
263 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
264 , _cond(cond)
265 , _type(type)
266 , _label(block->label())
267 , _block(block)
268 , _ublock(NULL)
269 , _stub(NULL) {
270 }
272 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
273 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
274 , _cond(cond)
275 , _type(type)
276 , _label(stub->entry())
277 , _block(NULL)
278 , _ublock(NULL)
279 , _stub(stub) {
280 }
282 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
283 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
284 , _cond(cond)
285 , _type(type)
286 , _label(block->label())
287 , _block(block)
288 , _ublock(ublock)
289 , _stub(NULL)
290 {
291 }
293 void LIR_OpBranch::change_block(BlockBegin* b) {
294 assert(_block != NULL, "must have old block");
295 assert(_block->label() == label(), "must be equal");
297 _block = b;
298 _label = b->label();
299 }
301 void LIR_OpBranch::change_ublock(BlockBegin* b) {
302 assert(_ublock != NULL, "must have old block");
303 _ublock = b;
304 }
306 void LIR_OpBranch::negate_cond() {
307 switch (_cond) {
308 case lir_cond_equal: _cond = lir_cond_notEqual; break;
309 case lir_cond_notEqual: _cond = lir_cond_equal; break;
310 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
311 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
312 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
313 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
314 default: ShouldNotReachHere();
315 }
316 }
319 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
320 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
321 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
322 CodeStub* stub,
323 ciMethod* profiled_method,
324 int profiled_bci)
325 : LIR_Op(code, result, NULL)
326 , _object(object)
327 , _array(LIR_OprFact::illegalOpr)
328 , _klass(klass)
329 , _tmp1(tmp1)
330 , _tmp2(tmp2)
331 , _tmp3(tmp3)
332 , _fast_check(fast_check)
333 , _stub(stub)
334 , _info_for_patch(info_for_patch)
335 , _info_for_exception(info_for_exception)
336 , _profiled_method(profiled_method)
337 , _profiled_bci(profiled_bci) {
338 if (code == lir_checkcast) {
339 assert(info_for_exception != NULL, "checkcast throws exceptions");
340 } else if (code == lir_instanceof) {
341 assert(info_for_exception == NULL, "instanceof throws no exceptions");
342 } else {
343 ShouldNotReachHere();
344 }
345 }
349 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci)
350 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
351 , _object(object)
352 , _array(array)
353 , _klass(NULL)
354 , _tmp1(tmp1)
355 , _tmp2(tmp2)
356 , _tmp3(tmp3)
357 , _fast_check(false)
358 , _stub(NULL)
359 , _info_for_patch(NULL)
360 , _info_for_exception(info_for_exception)
361 , _profiled_method(profiled_method)
362 , _profiled_bci(profiled_bci) {
363 if (code == lir_store_check) {
364 _stub = new ArrayStoreExceptionStub(info_for_exception);
365 assert(info_for_exception != NULL, "store_check throws exceptions");
366 } else {
367 ShouldNotReachHere();
368 }
369 }
372 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
373 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
374 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
375 , _tmp(tmp)
376 , _src(src)
377 , _src_pos(src_pos)
378 , _dst(dst)
379 , _dst_pos(dst_pos)
380 , _flags(flags)
381 , _expected_type(expected_type)
382 , _length(length) {
383 _stub = new ArrayCopyStub(this);
384 }
387 //-------------------verify--------------------------
389 void LIR_Op1::verify() const {
390 switch(code()) {
391 case lir_move:
392 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
393 break;
394 case lir_null_check:
395 assert(in_opr()->is_register(), "must be");
396 break;
397 case lir_return:
398 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
399 break;
400 }
401 }
403 void LIR_OpRTCall::verify() const {
404 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
405 }
407 //-------------------visits--------------------------
409 // complete rework of LIR instruction visitor.
410 // The virtual calls for each instruction type is replaced by a big
411 // switch that adds the operands for each instruction
413 void LIR_OpVisitState::visit(LIR_Op* op) {
414 // copy information from the LIR_Op
415 reset();
416 set_op(op);
418 switch (op->code()) {
420 // LIR_Op0
421 case lir_word_align: // result and info always invalid
422 case lir_backwardbranch_target: // result and info always invalid
423 case lir_build_frame: // result and info always invalid
424 case lir_fpop_raw: // result and info always invalid
425 case lir_24bit_FPU: // result and info always invalid
426 case lir_reset_FPU: // result and info always invalid
427 case lir_breakpoint: // result and info always invalid
428 case lir_membar: // result and info always invalid
429 case lir_membar_acquire: // result and info always invalid
430 case lir_membar_release: // result and info always invalid
431 {
432 assert(op->as_Op0() != NULL, "must be");
433 assert(op->_info == NULL, "info not used by this instruction");
434 assert(op->_result->is_illegal(), "not used");
435 break;
436 }
438 case lir_nop: // may have info, result always invalid
439 case lir_std_entry: // may have result, info always invalid
440 case lir_osr_entry: // may have result, info always invalid
441 case lir_get_thread: // may have result, info always invalid
442 {
443 assert(op->as_Op0() != NULL, "must be");
444 if (op->_info != NULL) do_info(op->_info);
445 if (op->_result->is_valid()) do_output(op->_result);
446 break;
447 }
450 // LIR_OpLabel
451 case lir_label: // result and info always invalid
452 {
453 assert(op->as_OpLabel() != NULL, "must be");
454 assert(op->_info == NULL, "info not used by this instruction");
455 assert(op->_result->is_illegal(), "not used");
456 break;
457 }
460 // LIR_Op1
461 case lir_fxch: // input always valid, result and info always invalid
462 case lir_fld: // input always valid, result and info always invalid
463 case lir_ffree: // input always valid, result and info always invalid
464 case lir_push: // input always valid, result and info always invalid
465 case lir_pop: // input always valid, result and info always invalid
466 case lir_return: // input always valid, result and info always invalid
467 case lir_leal: // input and result always valid, info always invalid
468 case lir_neg: // input and result always valid, info always invalid
469 case lir_monaddr: // input and result always valid, info always invalid
470 case lir_null_check: // input and info always valid, result always invalid
471 case lir_move: // input and result always valid, may have info
472 case lir_prefetchr: // input always valid, result and info always invalid
473 case lir_prefetchw: // input always valid, result and info always invalid
474 {
475 assert(op->as_Op1() != NULL, "must be");
476 LIR_Op1* op1 = (LIR_Op1*)op;
478 if (op1->_info) do_info(op1->_info);
479 if (op1->_opr->is_valid()) do_input(op1->_opr);
480 if (op1->_result->is_valid()) do_output(op1->_result);
482 break;
483 }
485 case lir_safepoint:
486 {
487 assert(op->as_Op1() != NULL, "must be");
488 LIR_Op1* op1 = (LIR_Op1*)op;
490 assert(op1->_info != NULL, ""); do_info(op1->_info);
491 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
492 assert(op1->_result->is_illegal(), "safepoint does not produce value");
494 break;
495 }
497 // LIR_OpConvert;
498 case lir_convert: // input and result always valid, info always invalid
499 {
500 assert(op->as_OpConvert() != NULL, "must be");
501 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
503 assert(opConvert->_info == NULL, "must be");
504 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
505 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
506 do_stub(opConvert->_stub);
508 break;
509 }
511 // LIR_OpBranch;
512 case lir_branch: // may have info, input and result register always invalid
513 case lir_cond_float_branch: // may have info, input and result register always invalid
514 {
515 assert(op->as_OpBranch() != NULL, "must be");
516 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
518 if (opBranch->_info != NULL) do_info(opBranch->_info);
519 assert(opBranch->_result->is_illegal(), "not used");
520 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
522 break;
523 }
526 // LIR_OpAllocObj
527 case lir_alloc_object:
528 {
529 assert(op->as_OpAllocObj() != NULL, "must be");
530 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
532 if (opAllocObj->_info) do_info(opAllocObj->_info);
533 if (opAllocObj->_opr->is_valid()) do_input(opAllocObj->_opr);
534 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
535 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
536 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
537 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
538 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
539 do_stub(opAllocObj->_stub);
540 break;
541 }
544 // LIR_OpRoundFP;
545 case lir_roundfp: {
546 assert(op->as_OpRoundFP() != NULL, "must be");
547 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
549 assert(op->_info == NULL, "info not used by this instruction");
550 assert(opRoundFP->_tmp->is_illegal(), "not used");
551 do_input(opRoundFP->_opr);
552 do_output(opRoundFP->_result);
554 break;
555 }
558 // LIR_Op2
559 case lir_cmp:
560 case lir_cmp_l2i:
561 case lir_ucmp_fd2i:
562 case lir_cmp_fd2i:
563 case lir_add:
564 case lir_sub:
565 case lir_mul:
566 case lir_div:
567 case lir_rem:
568 case lir_sqrt:
569 case lir_abs:
570 case lir_log:
571 case lir_log10:
572 case lir_logic_and:
573 case lir_logic_or:
574 case lir_logic_xor:
575 case lir_shl:
576 case lir_shr:
577 case lir_ushr:
578 {
579 assert(op->as_Op2() != NULL, "must be");
580 LIR_Op2* op2 = (LIR_Op2*)op;
582 if (op2->_info) do_info(op2->_info);
583 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
584 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
585 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
586 if (op2->_result->is_valid()) do_output(op2->_result);
588 break;
589 }
591 // special handling for cmove: right input operand must not be equal
592 // to the result operand, otherwise the backend fails
593 case lir_cmove:
594 {
595 assert(op->as_Op2() != NULL, "must be");
596 LIR_Op2* op2 = (LIR_Op2*)op;
598 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used");
599 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
601 do_input(op2->_opr1);
602 do_input(op2->_opr2);
603 do_temp(op2->_opr2);
604 do_output(op2->_result);
606 break;
607 }
609 // vspecial handling for strict operations: register input operands
610 // as temp to guarantee that they do not overlap with other
611 // registers
612 case lir_mul_strictfp:
613 case lir_div_strictfp:
614 {
615 assert(op->as_Op2() != NULL, "must be");
616 LIR_Op2* op2 = (LIR_Op2*)op;
618 assert(op2->_info == NULL, "not used");
619 assert(op2->_opr1->is_valid(), "used");
620 assert(op2->_opr2->is_valid(), "used");
621 assert(op2->_result->is_valid(), "used");
623 do_input(op2->_opr1); do_temp(op2->_opr1);
624 do_input(op2->_opr2); do_temp(op2->_opr2);
625 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
626 do_output(op2->_result);
628 break;
629 }
631 case lir_throw:
632 case lir_unwind: {
633 assert(op->as_Op2() != NULL, "must be");
634 LIR_Op2* op2 = (LIR_Op2*)op;
636 if (op2->_info) do_info(op2->_info);
637 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
638 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
639 assert(op2->_result->is_illegal(), "no result");
641 break;
642 }
645 case lir_tan:
646 case lir_sin:
647 case lir_cos: {
648 assert(op->as_Op2() != NULL, "must be");
649 LIR_Op2* op2 = (LIR_Op2*)op;
651 // sin and cos need two temporary fpu stack slots, so register
652 // two temp operands. Register input operand as temp to
653 // guarantee that they do not overlap
654 assert(op2->_info == NULL, "not used");
655 assert(op2->_opr1->is_valid(), "used");
656 do_input(op2->_opr1); do_temp(op2->_opr1);
658 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
659 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
660 if (op2->_result->is_valid()) do_output(op2->_result);
662 break;
663 }
666 // LIR_Op3
667 case lir_idiv:
668 case lir_irem: {
669 assert(op->as_Op3() != NULL, "must be");
670 LIR_Op3* op3= (LIR_Op3*)op;
672 if (op3->_info) do_info(op3->_info);
673 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
675 // second operand is input and temp, so ensure that second operand
676 // and third operand get not the same register
677 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
678 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
679 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
681 if (op3->_result->is_valid()) do_output(op3->_result);
683 break;
684 }
687 // LIR_OpJavaCall
688 case lir_static_call:
689 case lir_optvirtual_call:
690 case lir_icvirtual_call:
691 case lir_virtual_call: {
692 assert(op->as_OpJavaCall() != NULL, "must be");
693 LIR_OpJavaCall* opJavaCall = (LIR_OpJavaCall*)op;
695 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
697 // only visit register parameters
698 int n = opJavaCall->_arguments->length();
699 for (int i = 0; i < n; i++) {
700 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
701 do_input(*opJavaCall->_arguments->adr_at(i));
702 }
703 }
705 if (opJavaCall->_info) do_info(opJavaCall->_info);
706 do_call();
707 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
709 break;
710 }
713 // LIR_OpRTCall
714 case lir_rtcall: {
715 assert(op->as_OpRTCall() != NULL, "must be");
716 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
718 // only visit register parameters
719 int n = opRTCall->_arguments->length();
720 for (int i = 0; i < n; i++) {
721 if (!opRTCall->_arguments->at(i)->is_pointer()) {
722 do_input(*opRTCall->_arguments->adr_at(i));
723 }
724 }
725 if (opRTCall->_info) do_info(opRTCall->_info);
726 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
727 do_call();
728 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
730 break;
731 }
734 // LIR_OpArrayCopy
735 case lir_arraycopy: {
736 assert(op->as_OpArrayCopy() != NULL, "must be");
737 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
739 assert(opArrayCopy->_result->is_illegal(), "unused");
740 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
741 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
742 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
743 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
744 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
745 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
746 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
748 // the implementation of arraycopy always has a call into the runtime
749 do_call();
751 break;
752 }
755 // LIR_OpLock
756 case lir_lock:
757 case lir_unlock: {
758 assert(op->as_OpLock() != NULL, "must be");
759 LIR_OpLock* opLock = (LIR_OpLock*)op;
761 if (opLock->_info) do_info(opLock->_info);
763 // TODO: check if these operands really have to be temp
764 // (or if input is sufficient). This may have influence on the oop map!
765 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
766 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
767 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
769 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
770 assert(opLock->_result->is_illegal(), "unused");
772 do_stub(opLock->_stub);
774 break;
775 }
778 // LIR_OpDelay
779 case lir_delay_slot: {
780 assert(op->as_OpDelay() != NULL, "must be");
781 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
783 visit(opDelay->delay_op());
784 break;
785 }
787 // LIR_OpTypeCheck
788 case lir_instanceof:
789 case lir_checkcast:
790 case lir_store_check: {
791 assert(op->as_OpTypeCheck() != NULL, "must be");
792 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
794 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
795 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
796 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
797 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
798 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
799 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
800 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
801 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
802 do_stub(opTypeCheck->_stub);
803 break;
804 }
806 // LIR_OpCompareAndSwap
807 case lir_cas_long:
808 case lir_cas_obj:
809 case lir_cas_int: {
810 assert(op->as_OpCompareAndSwap() != NULL, "must be");
811 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
813 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
814 if (opCompareAndSwap->_addr->is_valid()) do_input(opCompareAndSwap->_addr);
815 if (opCompareAndSwap->_cmp_value->is_valid()) do_input(opCompareAndSwap->_cmp_value);
816 if (opCompareAndSwap->_new_value->is_valid()) do_input(opCompareAndSwap->_new_value);
817 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
818 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
819 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
821 break;
822 }
825 // LIR_OpAllocArray;
826 case lir_alloc_array: {
827 assert(op->as_OpAllocArray() != NULL, "must be");
828 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
830 if (opAllocArray->_info) do_info(opAllocArray->_info);
831 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
832 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
833 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
834 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
835 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
836 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
837 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
838 do_stub(opAllocArray->_stub);
839 break;
840 }
842 // LIR_OpProfileCall:
843 case lir_profile_call: {
844 assert(op->as_OpProfileCall() != NULL, "must be");
845 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
847 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
848 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
849 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
850 break;
851 }
853 default:
854 ShouldNotReachHere();
855 }
856 }
859 void LIR_OpVisitState::do_stub(CodeStub* stub) {
860 if (stub != NULL) {
861 stub->visit(this);
862 }
863 }
865 XHandlers* LIR_OpVisitState::all_xhandler() {
866 XHandlers* result = NULL;
868 int i;
869 for (i = 0; i < info_count(); i++) {
870 if (info_at(i)->exception_handlers() != NULL) {
871 result = info_at(i)->exception_handlers();
872 break;
873 }
874 }
876 #ifdef ASSERT
877 for (i = 0; i < info_count(); i++) {
878 assert(info_at(i)->exception_handlers() == NULL ||
879 info_at(i)->exception_handlers() == result,
880 "only one xhandler list allowed per LIR-operation");
881 }
882 #endif
884 if (result != NULL) {
885 return result;
886 } else {
887 return new XHandlers();
888 }
890 return result;
891 }
894 #ifdef ASSERT
895 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
896 visit(op);
898 return opr_count(inputMode) == 0 &&
899 opr_count(outputMode) == 0 &&
900 opr_count(tempMode) == 0 &&
901 info_count() == 0 &&
902 !has_call() &&
903 !has_slow_case();
904 }
905 #endif
907 //---------------------------------------------------
910 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
911 masm->emit_call(this);
912 }
914 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
915 masm->emit_rtcall(this);
916 }
918 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
919 masm->emit_opLabel(this);
920 }
922 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
923 masm->emit_arraycopy(this);
924 masm->emit_code_stub(stub());
925 }
927 void LIR_Op0::emit_code(LIR_Assembler* masm) {
928 masm->emit_op0(this);
929 }
931 void LIR_Op1::emit_code(LIR_Assembler* masm) {
932 masm->emit_op1(this);
933 }
935 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
936 masm->emit_alloc_obj(this);
937 masm->emit_code_stub(stub());
938 }
940 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
941 masm->emit_opBranch(this);
942 if (stub()) {
943 masm->emit_code_stub(stub());
944 }
945 }
947 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
948 masm->emit_opConvert(this);
949 if (stub() != NULL) {
950 masm->emit_code_stub(stub());
951 }
952 }
954 void LIR_Op2::emit_code(LIR_Assembler* masm) {
955 masm->emit_op2(this);
956 }
958 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
959 masm->emit_alloc_array(this);
960 masm->emit_code_stub(stub());
961 }
963 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
964 masm->emit_opTypeCheck(this);
965 if (stub()) {
966 masm->emit_code_stub(stub());
967 }
968 }
970 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
971 masm->emit_compare_and_swap(this);
972 }
974 void LIR_Op3::emit_code(LIR_Assembler* masm) {
975 masm->emit_op3(this);
976 }
978 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
979 masm->emit_lock(this);
980 if (stub()) {
981 masm->emit_code_stub(stub());
982 }
983 }
986 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
987 masm->emit_delay(this);
988 }
991 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
992 masm->emit_profile_call(this);
993 }
996 // LIR_List
997 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
998 : _operations(8)
999 , _compilation(compilation)
1000 #ifndef PRODUCT
1001 , _block(block)
1002 #endif
1003 #ifdef ASSERT
1004 , _file(NULL)
1005 , _line(0)
1006 #endif
1007 { }
1010 #ifdef ASSERT
1011 void LIR_List::set_file_and_line(const char * file, int line) {
1012 const char * f = strrchr(file, '/');
1013 if (f == NULL) f = strrchr(file, '\\');
1014 if (f == NULL) {
1015 f = file;
1016 } else {
1017 f++;
1018 }
1019 _file = f;
1020 _line = line;
1021 }
1022 #endif
1025 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1026 assert(this == buffer->lir_list(), "wrong lir list");
1027 const int n = _operations.length();
1029 if (buffer->number_of_ops() > 0) {
1030 // increase size of instructions list
1031 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1032 // insert ops from buffer into instructions list
1033 int op_index = buffer->number_of_ops() - 1;
1034 int ip_index = buffer->number_of_insertion_points() - 1;
1035 int from_index = n - 1;
1036 int to_index = _operations.length() - 1;
1037 for (; ip_index >= 0; ip_index --) {
1038 int index = buffer->index_at(ip_index);
1039 // make room after insertion point
1040 while (index < from_index) {
1041 _operations.at_put(to_index --, _operations.at(from_index --));
1042 }
1043 // insert ops from buffer
1044 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1045 _operations.at_put(to_index --, buffer->op_at(op_index --));
1046 }
1047 }
1048 }
1050 buffer->finish();
1051 }
1054 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1055 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1056 }
1059 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1060 append(new LIR_Op1(
1061 lir_move,
1062 LIR_OprFact::address(addr),
1063 src,
1064 addr->type(),
1065 patch_code,
1066 info));
1067 }
1070 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1071 append(new LIR_Op1(
1072 lir_move,
1073 LIR_OprFact::address(address),
1074 dst,
1075 address->type(),
1076 patch_code,
1077 info, lir_move_volatile));
1078 }
1080 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1081 append(new LIR_Op1(
1082 lir_move,
1083 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1084 dst,
1085 type,
1086 patch_code,
1087 info, lir_move_volatile));
1088 }
1091 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1092 append(new LIR_Op1(
1093 is_store ? lir_prefetchw : lir_prefetchr,
1094 LIR_OprFact::address(addr)));
1095 }
1098 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1099 append(new LIR_Op1(
1100 lir_move,
1101 LIR_OprFact::intConst(v),
1102 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1103 type,
1104 patch_code,
1105 info));
1106 }
1109 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1110 append(new LIR_Op1(
1111 lir_move,
1112 LIR_OprFact::oopConst(o),
1113 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1114 type,
1115 patch_code,
1116 info));
1117 }
1120 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1121 append(new LIR_Op1(
1122 lir_move,
1123 src,
1124 LIR_OprFact::address(addr),
1125 addr->type(),
1126 patch_code,
1127 info));
1128 }
1131 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1132 append(new LIR_Op1(
1133 lir_move,
1134 src,
1135 LIR_OprFact::address(addr),
1136 addr->type(),
1137 patch_code,
1138 info,
1139 lir_move_volatile));
1140 }
1142 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1143 append(new LIR_Op1(
1144 lir_move,
1145 src,
1146 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1147 type,
1148 patch_code,
1149 info, lir_move_volatile));
1150 }
1153 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1154 append(new LIR_Op3(
1155 lir_idiv,
1156 left,
1157 right,
1158 tmp,
1159 res,
1160 info));
1161 }
1164 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1165 append(new LIR_Op3(
1166 lir_idiv,
1167 left,
1168 LIR_OprFact::intConst(right),
1169 tmp,
1170 res,
1171 info));
1172 }
1175 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1176 append(new LIR_Op3(
1177 lir_irem,
1178 left,
1179 right,
1180 tmp,
1181 res,
1182 info));
1183 }
1186 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1187 append(new LIR_Op3(
1188 lir_irem,
1189 left,
1190 LIR_OprFact::intConst(right),
1191 tmp,
1192 res,
1193 info));
1194 }
1197 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1198 append(new LIR_Op2(
1199 lir_cmp,
1200 condition,
1201 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1202 LIR_OprFact::intConst(c),
1203 info));
1204 }
1207 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1208 append(new LIR_Op2(
1209 lir_cmp,
1210 condition,
1211 reg,
1212 LIR_OprFact::address(addr),
1213 info));
1214 }
1216 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1217 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1218 append(new LIR_OpAllocObj(
1219 klass,
1220 dst,
1221 t1,
1222 t2,
1223 t3,
1224 t4,
1225 header_size,
1226 object_size,
1227 init_check,
1228 stub));
1229 }
1231 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1232 append(new LIR_OpAllocArray(
1233 klass,
1234 len,
1235 dst,
1236 t1,
1237 t2,
1238 t3,
1239 t4,
1240 type,
1241 stub));
1242 }
1244 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1245 append(new LIR_Op2(
1246 lir_shl,
1247 value,
1248 count,
1249 dst,
1250 tmp));
1251 }
1253 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1254 append(new LIR_Op2(
1255 lir_shr,
1256 value,
1257 count,
1258 dst,
1259 tmp));
1260 }
1263 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1264 append(new LIR_Op2(
1265 lir_ushr,
1266 value,
1267 count,
1268 dst,
1269 tmp));
1270 }
1272 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1273 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1274 left,
1275 right,
1276 dst));
1277 }
1279 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1280 append(new LIR_OpLock(
1281 lir_lock,
1282 hdr,
1283 obj,
1284 lock,
1285 scratch,
1286 stub,
1287 info));
1288 }
1290 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, CodeStub* stub) {
1291 append(new LIR_OpLock(
1292 lir_unlock,
1293 hdr,
1294 obj,
1295 lock,
1296 LIR_OprFact::illegalOpr,
1297 stub,
1298 NULL));
1299 }
1302 void check_LIR() {
1303 // cannot do the proper checking as PRODUCT and other modes return different results
1304 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1305 }
1309 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1310 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1311 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1312 ciMethod* profiled_method, int profiled_bci) {
1313 append(new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1314 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub,
1315 profiled_method, profiled_bci));
1316 }
1319 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch) {
1320 append(new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL, NULL, 0));
1321 }
1324 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) {
1325 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception, NULL, 0));
1326 }
1329 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) {
1330 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1331 // implying successful swap of new_value into addr
1332 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2));
1333 }
1335 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) {
1336 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1337 // implying successful swap of new_value into addr
1338 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2));
1339 }
1341 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) {
1342 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1343 // implying successful swap of new_value into addr
1344 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2));
1345 }
1348 #ifdef PRODUCT
1350 void print_LIR(BlockList* blocks) {
1351 }
1353 #else
1354 // LIR_OprDesc
1355 void LIR_OprDesc::print() const {
1356 print(tty);
1357 }
1359 void LIR_OprDesc::print(outputStream* out) const {
1360 if (is_illegal()) {
1361 return;
1362 }
1364 out->print("[");
1365 if (is_pointer()) {
1366 pointer()->print_value_on(out);
1367 } else if (is_single_stack()) {
1368 out->print("stack:%d", single_stack_ix());
1369 } else if (is_double_stack()) {
1370 out->print("dbl_stack:%d",double_stack_ix());
1371 } else if (is_virtual()) {
1372 out->print("R%d", vreg_number());
1373 } else if (is_single_cpu()) {
1374 out->print(as_register()->name());
1375 } else if (is_double_cpu()) {
1376 out->print(as_register_hi()->name());
1377 out->print(as_register_lo()->name());
1378 #if defined(X86)
1379 } else if (is_single_xmm()) {
1380 out->print(as_xmm_float_reg()->name());
1381 } else if (is_double_xmm()) {
1382 out->print(as_xmm_double_reg()->name());
1383 } else if (is_single_fpu()) {
1384 out->print("fpu%d", fpu_regnr());
1385 } else if (is_double_fpu()) {
1386 out->print("fpu%d", fpu_regnrLo());
1387 #else
1388 } else if (is_single_fpu()) {
1389 out->print(as_float_reg()->name());
1390 } else if (is_double_fpu()) {
1391 out->print(as_double_reg()->name());
1392 #endif
1394 } else if (is_illegal()) {
1395 out->print("-");
1396 } else {
1397 out->print("Unknown Operand");
1398 }
1399 if (!is_illegal()) {
1400 out->print("|%c", type_char());
1401 }
1402 if (is_register() && is_last_use()) {
1403 out->print("(last_use)");
1404 }
1405 out->print("]");
1406 }
1409 // LIR_Address
1410 void LIR_Const::print_value_on(outputStream* out) const {
1411 switch (type()) {
1412 case T_INT: out->print("int:%d", as_jint()); break;
1413 case T_LONG: out->print("lng:%lld", as_jlong()); break;
1414 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1415 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1416 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1417 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1418 }
1419 }
1421 // LIR_Address
1422 void LIR_Address::print_value_on(outputStream* out) const {
1423 out->print("Base:"); _base->print(out);
1424 if (!_index->is_illegal()) {
1425 out->print(" Index:"); _index->print(out);
1426 switch (scale()) {
1427 case times_1: break;
1428 case times_2: out->print(" * 2"); break;
1429 case times_4: out->print(" * 4"); break;
1430 case times_8: out->print(" * 8"); break;
1431 }
1432 }
1433 out->print(" Disp: %d", _disp);
1434 }
1436 // debug output of block header without InstructionPrinter
1437 // (because phi functions are not necessary for LIR)
1438 static void print_block(BlockBegin* x) {
1439 // print block id
1440 BlockEnd* end = x->end();
1441 tty->print("B%d ", x->block_id());
1443 // print flags
1444 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1445 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1446 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1447 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1448 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1449 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1450 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1452 // print block bci range
1453 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->bci()));
1455 // print predecessors and successors
1456 if (x->number_of_preds() > 0) {
1457 tty->print("preds: ");
1458 for (int i = 0; i < x->number_of_preds(); i ++) {
1459 tty->print("B%d ", x->pred_at(i)->block_id());
1460 }
1461 }
1463 if (x->number_of_sux() > 0) {
1464 tty->print("sux: ");
1465 for (int i = 0; i < x->number_of_sux(); i ++) {
1466 tty->print("B%d ", x->sux_at(i)->block_id());
1467 }
1468 }
1470 // print exception handlers
1471 if (x->number_of_exception_handlers() > 0) {
1472 tty->print("xhandler: ");
1473 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1474 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1475 }
1476 }
1478 tty->cr();
1479 }
1481 void print_LIR(BlockList* blocks) {
1482 tty->print_cr("LIR:");
1483 int i;
1484 for (i = 0; i < blocks->length(); i++) {
1485 BlockBegin* bb = blocks->at(i);
1486 print_block(bb);
1487 tty->print("__id_Instruction___________________________________________"); tty->cr();
1488 bb->lir()->print_instructions();
1489 }
1490 }
1492 void LIR_List::print_instructions() {
1493 for (int i = 0; i < _operations.length(); i++) {
1494 _operations.at(i)->print(); tty->cr();
1495 }
1496 tty->cr();
1497 }
1499 // LIR_Ops printing routines
1500 // LIR_Op
1501 void LIR_Op::print_on(outputStream* out) const {
1502 if (id() != -1 || PrintCFGToFile) {
1503 out->print("%4d ", id());
1504 } else {
1505 out->print(" ");
1506 }
1507 out->print(name()); out->print(" ");
1508 print_instr(out);
1509 if (info() != NULL) out->print(" [bci:%d]", info()->bci());
1510 #ifdef ASSERT
1511 if (Verbose && _file != NULL) {
1512 out->print(" (%s:%d)", _file, _line);
1513 }
1514 #endif
1515 }
1517 const char * LIR_Op::name() const {
1518 const char* s = NULL;
1519 switch(code()) {
1520 // LIR_Op0
1521 case lir_membar: s = "membar"; break;
1522 case lir_membar_acquire: s = "membar_acquire"; break;
1523 case lir_membar_release: s = "membar_release"; break;
1524 case lir_word_align: s = "word_align"; break;
1525 case lir_label: s = "label"; break;
1526 case lir_nop: s = "nop"; break;
1527 case lir_backwardbranch_target: s = "backbranch"; break;
1528 case lir_std_entry: s = "std_entry"; break;
1529 case lir_osr_entry: s = "osr_entry"; break;
1530 case lir_build_frame: s = "build_frm"; break;
1531 case lir_fpop_raw: s = "fpop_raw"; break;
1532 case lir_24bit_FPU: s = "24bit_FPU"; break;
1533 case lir_reset_FPU: s = "reset_FPU"; break;
1534 case lir_breakpoint: s = "breakpoint"; break;
1535 case lir_get_thread: s = "get_thread"; break;
1536 // LIR_Op1
1537 case lir_fxch: s = "fxch"; break;
1538 case lir_fld: s = "fld"; break;
1539 case lir_ffree: s = "ffree"; break;
1540 case lir_push: s = "push"; break;
1541 case lir_pop: s = "pop"; break;
1542 case lir_null_check: s = "null_check"; break;
1543 case lir_return: s = "return"; break;
1544 case lir_safepoint: s = "safepoint"; break;
1545 case lir_neg: s = "neg"; break;
1546 case lir_leal: s = "leal"; break;
1547 case lir_branch: s = "branch"; break;
1548 case lir_cond_float_branch: s = "flt_cond_br"; break;
1549 case lir_move: s = "move"; break;
1550 case lir_roundfp: s = "roundfp"; break;
1551 case lir_rtcall: s = "rtcall"; break;
1552 case lir_throw: s = "throw"; break;
1553 case lir_unwind: s = "unwind"; break;
1554 case lir_convert: s = "convert"; break;
1555 case lir_alloc_object: s = "alloc_obj"; break;
1556 case lir_monaddr: s = "mon_addr"; break;
1557 // LIR_Op2
1558 case lir_cmp: s = "cmp"; break;
1559 case lir_cmp_l2i: s = "cmp_l2i"; break;
1560 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1561 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1562 case lir_cmove: s = "cmove"; break;
1563 case lir_add: s = "add"; break;
1564 case lir_sub: s = "sub"; break;
1565 case lir_mul: s = "mul"; break;
1566 case lir_mul_strictfp: s = "mul_strictfp"; break;
1567 case lir_div: s = "div"; break;
1568 case lir_div_strictfp: s = "div_strictfp"; break;
1569 case lir_rem: s = "rem"; break;
1570 case lir_abs: s = "abs"; break;
1571 case lir_sqrt: s = "sqrt"; break;
1572 case lir_sin: s = "sin"; break;
1573 case lir_cos: s = "cos"; break;
1574 case lir_tan: s = "tan"; break;
1575 case lir_log: s = "log"; break;
1576 case lir_log10: s = "log10"; break;
1577 case lir_logic_and: s = "logic_and"; break;
1578 case lir_logic_or: s = "logic_or"; break;
1579 case lir_logic_xor: s = "logic_xor"; break;
1580 case lir_shl: s = "shift_left"; break;
1581 case lir_shr: s = "shift_right"; break;
1582 case lir_ushr: s = "ushift_right"; break;
1583 case lir_alloc_array: s = "alloc_array"; break;
1584 // LIR_Op3
1585 case lir_idiv: s = "idiv"; break;
1586 case lir_irem: s = "irem"; break;
1587 // LIR_OpJavaCall
1588 case lir_static_call: s = "static"; break;
1589 case lir_optvirtual_call: s = "optvirtual"; break;
1590 case lir_icvirtual_call: s = "icvirtual"; break;
1591 case lir_virtual_call: s = "virtual"; break;
1592 // LIR_OpArrayCopy
1593 case lir_arraycopy: s = "arraycopy"; break;
1594 // LIR_OpLock
1595 case lir_lock: s = "lock"; break;
1596 case lir_unlock: s = "unlock"; break;
1597 // LIR_OpDelay
1598 case lir_delay_slot: s = "delay"; break;
1599 // LIR_OpTypeCheck
1600 case lir_instanceof: s = "instanceof"; break;
1601 case lir_checkcast: s = "checkcast"; break;
1602 case lir_store_check: s = "store_check"; break;
1603 // LIR_OpCompareAndSwap
1604 case lir_cas_long: s = "cas_long"; break;
1605 case lir_cas_obj: s = "cas_obj"; break;
1606 case lir_cas_int: s = "cas_int"; break;
1607 // LIR_OpProfileCall
1608 case lir_profile_call: s = "profile_call"; break;
1610 case lir_none: ShouldNotReachHere();break;
1611 default: s = "illegal_op"; break;
1612 }
1613 return s;
1614 }
1616 // LIR_OpJavaCall
1617 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1618 out->print("call: ");
1619 out->print("[addr: 0x%x]", address());
1620 if (receiver()->is_valid()) {
1621 out->print(" [recv: "); receiver()->print(out); out->print("]");
1622 }
1623 if (result_opr()->is_valid()) {
1624 out->print(" [result: "); result_opr()->print(out); out->print("]");
1625 }
1626 }
1628 // LIR_OpLabel
1629 void LIR_OpLabel::print_instr(outputStream* out) const {
1630 out->print("[label:0x%x]", _label);
1631 }
1633 // LIR_OpArrayCopy
1634 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1635 src()->print(out); out->print(" ");
1636 src_pos()->print(out); out->print(" ");
1637 dst()->print(out); out->print(" ");
1638 dst_pos()->print(out); out->print(" ");
1639 length()->print(out); out->print(" ");
1640 tmp()->print(out); out->print(" ");
1641 }
1643 // LIR_OpCompareAndSwap
1644 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1645 addr()->print(out); out->print(" ");
1646 cmp_value()->print(out); out->print(" ");
1647 new_value()->print(out); out->print(" ");
1648 tmp1()->print(out); out->print(" ");
1649 tmp2()->print(out); out->print(" ");
1651 }
1653 // LIR_Op0
1654 void LIR_Op0::print_instr(outputStream* out) const {
1655 result_opr()->print(out);
1656 }
1658 // LIR_Op1
1659 const char * LIR_Op1::name() const {
1660 if (code() == lir_move) {
1661 switch (move_kind()) {
1662 case lir_move_normal:
1663 return "move";
1664 case lir_move_unaligned:
1665 return "unaligned move";
1666 case lir_move_volatile:
1667 return "volatile_move";
1668 default:
1669 ShouldNotReachHere();
1670 return "illegal_op";
1671 }
1672 } else {
1673 return LIR_Op::name();
1674 }
1675 }
1678 void LIR_Op1::print_instr(outputStream* out) const {
1679 _opr->print(out); out->print(" ");
1680 result_opr()->print(out); out->print(" ");
1681 print_patch_code(out, patch_code());
1682 }
1685 // LIR_Op1
1686 void LIR_OpRTCall::print_instr(outputStream* out) const {
1687 intx a = (intx)addr();
1688 out->print(Runtime1::name_for_address(addr()));
1689 out->print(" ");
1690 tmp()->print(out);
1691 }
1693 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1694 switch(code) {
1695 case lir_patch_none: break;
1696 case lir_patch_low: out->print("[patch_low]"); break;
1697 case lir_patch_high: out->print("[patch_high]"); break;
1698 case lir_patch_normal: out->print("[patch_normal]"); break;
1699 default: ShouldNotReachHere();
1700 }
1701 }
1703 // LIR_OpBranch
1704 void LIR_OpBranch::print_instr(outputStream* out) const {
1705 print_condition(out, cond()); out->print(" ");
1706 if (block() != NULL) {
1707 out->print("[B%d] ", block()->block_id());
1708 } else if (stub() != NULL) {
1709 out->print("[");
1710 stub()->print_name(out);
1711 out->print(": 0x%x]", stub());
1712 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->bci());
1713 } else {
1714 out->print("[label:0x%x] ", label());
1715 }
1716 if (ublock() != NULL) {
1717 out->print("unordered: [B%d] ", ublock()->block_id());
1718 }
1719 }
1721 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1722 switch(cond) {
1723 case lir_cond_equal: out->print("[EQ]"); break;
1724 case lir_cond_notEqual: out->print("[NE]"); break;
1725 case lir_cond_less: out->print("[LT]"); break;
1726 case lir_cond_lessEqual: out->print("[LE]"); break;
1727 case lir_cond_greaterEqual: out->print("[GE]"); break;
1728 case lir_cond_greater: out->print("[GT]"); break;
1729 case lir_cond_belowEqual: out->print("[BE]"); break;
1730 case lir_cond_aboveEqual: out->print("[AE]"); break;
1731 case lir_cond_always: out->print("[AL]"); break;
1732 default: out->print("[%d]",cond); break;
1733 }
1734 }
1736 // LIR_OpConvert
1737 void LIR_OpConvert::print_instr(outputStream* out) const {
1738 print_bytecode(out, bytecode());
1739 in_opr()->print(out); out->print(" ");
1740 result_opr()->print(out); out->print(" ");
1741 }
1743 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1744 switch(code) {
1745 case Bytecodes::_d2f: out->print("[d2f] "); break;
1746 case Bytecodes::_d2i: out->print("[d2i] "); break;
1747 case Bytecodes::_d2l: out->print("[d2l] "); break;
1748 case Bytecodes::_f2d: out->print("[f2d] "); break;
1749 case Bytecodes::_f2i: out->print("[f2i] "); break;
1750 case Bytecodes::_f2l: out->print("[f2l] "); break;
1751 case Bytecodes::_i2b: out->print("[i2b] "); break;
1752 case Bytecodes::_i2c: out->print("[i2c] "); break;
1753 case Bytecodes::_i2d: out->print("[i2d] "); break;
1754 case Bytecodes::_i2f: out->print("[i2f] "); break;
1755 case Bytecodes::_i2l: out->print("[i2l] "); break;
1756 case Bytecodes::_i2s: out->print("[i2s] "); break;
1757 case Bytecodes::_l2i: out->print("[l2i] "); break;
1758 case Bytecodes::_l2f: out->print("[l2f] "); break;
1759 case Bytecodes::_l2d: out->print("[l2d] "); break;
1760 default:
1761 out->print("[?%d]",code);
1762 break;
1763 }
1764 }
1766 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1767 klass()->print(out); out->print(" ");
1768 obj()->print(out); out->print(" ");
1769 tmp1()->print(out); out->print(" ");
1770 tmp2()->print(out); out->print(" ");
1771 tmp3()->print(out); out->print(" ");
1772 tmp4()->print(out); out->print(" ");
1773 out->print("[hdr:%d]", header_size()); out->print(" ");
1774 out->print("[obj:%d]", object_size()); out->print(" ");
1775 out->print("[lbl:0x%x]", stub()->entry());
1776 }
1778 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1779 _opr->print(out); out->print(" ");
1780 tmp()->print(out); out->print(" ");
1781 result_opr()->print(out); out->print(" ");
1782 }
1784 // LIR_Op2
1785 void LIR_Op2::print_instr(outputStream* out) const {
1786 if (code() == lir_cmove) {
1787 print_condition(out, condition()); out->print(" ");
1788 }
1789 in_opr1()->print(out); out->print(" ");
1790 in_opr2()->print(out); out->print(" ");
1791 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); }
1792 result_opr()->print(out);
1793 }
1795 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1796 klass()->print(out); out->print(" ");
1797 len()->print(out); out->print(" ");
1798 obj()->print(out); out->print(" ");
1799 tmp1()->print(out); out->print(" ");
1800 tmp2()->print(out); out->print(" ");
1801 tmp3()->print(out); out->print(" ");
1802 tmp4()->print(out); out->print(" ");
1803 out->print("[type:0x%x]", type()); out->print(" ");
1804 out->print("[label:0x%x]", stub()->entry());
1805 }
1808 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1809 object()->print(out); out->print(" ");
1810 if (code() == lir_store_check) {
1811 array()->print(out); out->print(" ");
1812 }
1813 if (code() != lir_store_check) {
1814 klass()->print_name_on(out); out->print(" ");
1815 if (fast_check()) out->print("fast_check ");
1816 }
1817 tmp1()->print(out); out->print(" ");
1818 tmp2()->print(out); out->print(" ");
1819 tmp3()->print(out); out->print(" ");
1820 result_opr()->print(out); out->print(" ");
1821 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->bci());
1822 }
1825 // LIR_Op3
1826 void LIR_Op3::print_instr(outputStream* out) const {
1827 in_opr1()->print(out); out->print(" ");
1828 in_opr2()->print(out); out->print(" ");
1829 in_opr3()->print(out); out->print(" ");
1830 result_opr()->print(out);
1831 }
1834 void LIR_OpLock::print_instr(outputStream* out) const {
1835 hdr_opr()->print(out); out->print(" ");
1836 obj_opr()->print(out); out->print(" ");
1837 lock_opr()->print(out); out->print(" ");
1838 if (_scratch->is_valid()) {
1839 _scratch->print(out); out->print(" ");
1840 }
1841 out->print("[lbl:0x%x]", stub()->entry());
1842 }
1845 void LIR_OpDelay::print_instr(outputStream* out) const {
1846 _op->print_on(out);
1847 }
1850 // LIR_OpProfileCall
1851 void LIR_OpProfileCall::print_instr(outputStream* out) const {
1852 profiled_method()->name()->print_symbol_on(out);
1853 out->print(".");
1854 profiled_method()->holder()->name()->print_symbol_on(out);
1855 out->print(" @ %d ", profiled_bci());
1856 mdo()->print(out); out->print(" ");
1857 recv()->print(out); out->print(" ");
1858 tmp1()->print(out); out->print(" ");
1859 }
1862 #endif // PRODUCT
1864 // Implementation of LIR_InsertionBuffer
1866 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
1867 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
1869 int i = number_of_insertion_points() - 1;
1870 if (i < 0 || index_at(i) < index) {
1871 append_new(index, 1);
1872 } else {
1873 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
1874 assert(count_at(i) > 0, "check");
1875 set_count_at(i, count_at(i) + 1);
1876 }
1877 _ops.push(op);
1879 DEBUG_ONLY(verify());
1880 }
1882 #ifdef ASSERT
1883 void LIR_InsertionBuffer::verify() {
1884 int sum = 0;
1885 int prev_idx = -1;
1887 for (int i = 0; i < number_of_insertion_points(); i++) {
1888 assert(prev_idx < index_at(i), "index must be ordered ascending");
1889 sum += count_at(i);
1890 }
1891 assert(sum == number_of_ops(), "wrong total sum");
1892 }
1893 #endif
