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src/cpu/x86/vm/assembler_x86.hpp@a3ecd773a7b9
src/cpu/x86/vm/assembler_x86.hpp
Wed, 24 Oct 2012 14:33:22 -0700
- author
- kvn
- date
- Wed, 24 Oct 2012 14:33:22 -0700
- changeset 4205
- a3ecd773a7b9
- parent 4159
- 8e47bac5643a
- child 4317
- 6ab62ad83507
- permissions
- -rw-r--r--
7184394: add intrinsics to use AES instructions
Summary: Use new x86 AES instructions for AESCrypt.
Reviewed-by: twisti, kvn, roland
Contributed-by: tom.deneau@amd.com
1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
28 class BiasedLockingCounters;
30 // Contains all the definitions needed for x86 assembly code generation.
32 // Calling convention
33 class Argument VALUE_OBJ_CLASS_SPEC {
34 public:
35 enum {
36 #ifdef _LP64
37 #ifdef _WIN64
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
40 #else
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
43 #endif // _WIN64
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
46 #else
47 n_register_parameters = 0 // 0 registers used to pass arguments
48 #endif // _LP64
49 };
50 };
53 #ifdef _LP64
54 // Symbolically name the register arguments used by the c calling convention.
55 // Windows is different from linux/solaris. So much for standards...
57 #ifdef _WIN64
59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
61 REGISTER_DECLARATION(Register, c_rarg2, r8);
62 REGISTER_DECLARATION(Register, c_rarg3, r9);
64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
69 #else
71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
75 REGISTER_DECLARATION(Register, c_rarg4, r8);
76 REGISTER_DECLARATION(Register, c_rarg5, r9);
78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
87 #endif // _WIN64
89 // Symbolically name the register arguments used by the Java calling convention.
90 // We have control over the convention for java so we can do what we please.
91 // What pleases us is to offset the java calling convention so that when
92 // we call a suitable jni method the arguments are lined up and we don't
93 // have to do little shuffling. A suitable jni method is non-static and a
94 // small number of arguments (two fewer args on windows)
95 //
96 // |-------------------------------------------------------|
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
98 // |-------------------------------------------------------|
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux
101 // |-------------------------------------------------------|
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
103 // |-------------------------------------------------------|
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
108 // Windows runs out of register args here
109 #ifdef _WIN64
110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
112 #else
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
115 #endif /* _WIN64 */
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
133 #else
134 // rscratch1 will apear in 32bit code that is dead but of course must compile
135 // Using noreg ensures if the dead code is incorrectly live and executed it
136 // will cause an assertion failure
137 #define rscratch1 noreg
138 #define rscratch2 noreg
140 #endif // _LP64
142 // JSR 292 fixed register usages:
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
145 // Address is an abstraction used to represent a memory location
146 // using any of the amd64 addressing modes with one object.
147 //
148 // Note: A register location is represented via a Register, not
149 // via an address for efficiency & simplicity reasons.
151 class ArrayAddress;
153 class Address VALUE_OBJ_CLASS_SPEC {
154 public:
155 enum ScaleFactor {
156 no_scale = -1,
157 times_1 = 0,
158 times_2 = 1,
159 times_4 = 2,
160 times_8 = 3,
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
162 };
163 static ScaleFactor times(int size) {
164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
165 if (size == 8) return times_8;
166 if (size == 4) return times_4;
167 if (size == 2) return times_2;
168 return times_1;
169 }
170 static int scale_size(ScaleFactor scale) {
171 assert(scale != no_scale, "");
172 assert(((1 << (int)times_1) == 1 &&
173 (1 << (int)times_2) == 2 &&
174 (1 << (int)times_4) == 4 &&
175 (1 << (int)times_8) == 8), "");
176 return (1 << (int)scale);
177 }
179 private:
180 Register _base;
181 Register _index;
182 ScaleFactor _scale;
183 int _disp;
184 RelocationHolder _rspec;
186 // Easily misused constructors make them private
187 // %%% can we make these go away?
188 NOT_LP64(Address(address loc, RelocationHolder spec);)
189 Address(int disp, address loc, relocInfo::relocType rtype);
190 Address(int disp, address loc, RelocationHolder spec);
192 public:
194 int disp() { return _disp; }
195 // creation
196 Address()
197 : _base(noreg),
198 _index(noreg),
199 _scale(no_scale),
200 _disp(0) {
201 }
203 // No default displacement otherwise Register can be implicitly
204 // converted to 0(Register) which is quite a different animal.
206 Address(Register base, int disp)
207 : _base(base),
208 _index(noreg),
209 _scale(no_scale),
210 _disp(disp) {
211 }
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
214 : _base (base),
215 _index(index),
216 _scale(scale),
217 _disp (disp) {
218 assert(!index->is_valid() == (scale == Address::no_scale),
219 "inconsistent address");
220 }
222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
223 : _base (base),
224 _index(index.register_or_noreg()),
225 _scale(scale),
226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
227 if (!index.is_register()) scale = Address::no_scale;
228 assert(!_index->is_valid() == (scale == Address::no_scale),
229 "inconsistent address");
230 }
232 Address plus_disp(int disp) const {
233 Address a = (*this);
234 a._disp += disp;
235 return a;
236 }
237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
238 Address a = (*this);
239 a._disp += disp.constant_or_zero() * scale_size(scale);
240 if (disp.is_register()) {
241 assert(!a.index()->is_valid(), "competing indexes");
242 a._index = disp.as_register();
243 a._scale = scale;
244 }
245 return a;
246 }
247 bool is_same_address(Address a) const {
248 // disregard _rspec
249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
250 }
252 // The following two overloads are used in connection with the
253 // ByteSize type (see sizes.hpp). They simplify the use of
254 // ByteSize'd arguments in assembly code. Note that their equivalent
255 // for the optimized build are the member functions with int disp
256 // argument since ByteSize is mapped to an int type in that case.
257 //
258 // Note: DO NOT introduce similar overloaded functions for WordSize
259 // arguments as in the optimized mode, both ByteSize and WordSize
260 // are mapped to the same type and thus the compiler cannot make a
261 // distinction anymore (=> compiler errors).
263 #ifdef ASSERT
264 Address(Register base, ByteSize disp)
265 : _base(base),
266 _index(noreg),
267 _scale(no_scale),
268 _disp(in_bytes(disp)) {
269 }
271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
272 : _base(base),
273 _index(index),
274 _scale(scale),
275 _disp(in_bytes(disp)) {
276 assert(!index->is_valid() == (scale == Address::no_scale),
277 "inconsistent address");
278 }
280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
281 : _base (base),
282 _index(index.register_or_noreg()),
283 _scale(scale),
284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
285 if (!index.is_register()) scale = Address::no_scale;
286 assert(!_index->is_valid() == (scale == Address::no_scale),
287 "inconsistent address");
288 }
290 #endif // ASSERT
292 // accessors
293 bool uses(Register reg) const { return _base == reg || _index == reg; }
294 Register base() const { return _base; }
295 Register index() const { return _index; }
296 ScaleFactor scale() const { return _scale; }
297 int disp() const { return _disp; }
299 // Convert the raw encoding form into the form expected by the constructor for
300 // Address. An index of 4 (rsp) corresponds to having no index, so convert
301 // that to noreg for the Address constructor.
302 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
304 static Address make_array(ArrayAddress);
306 private:
307 bool base_needs_rex() const {
308 return _base != noreg && _base->encoding() >= 8;
309 }
311 bool index_needs_rex() const {
312 return _index != noreg &&_index->encoding() >= 8;
313 }
315 relocInfo::relocType reloc() const { return _rspec.type(); }
317 friend class Assembler;
318 friend class MacroAssembler;
319 friend class LIR_Assembler; // base/index/scale/disp
320 };
322 //
323 // AddressLiteral has been split out from Address because operands of this type
324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
325 // the few instructions that need to deal with address literals are unique and the
326 // MacroAssembler does not have to implement every instruction in the Assembler
327 // in order to search for address literals that may need special handling depending
328 // on the instruction and the platform. As small step on the way to merging i486/amd64
329 // directories.
330 //
331 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
332 friend class ArrayAddress;
333 RelocationHolder _rspec;
334 // Typically we use AddressLiterals we want to use their rval
335 // However in some situations we want the lval (effect address) of the item.
336 // We provide a special factory for making those lvals.
337 bool _is_lval;
339 // If the target is far we'll need to load the ea of this to
340 // a register to reach it. Otherwise if near we can do rip
341 // relative addressing.
343 address _target;
345 protected:
346 // creation
347 AddressLiteral()
348 : _is_lval(false),
349 _target(NULL)
350 {}
352 public:
355 AddressLiteral(address target, relocInfo::relocType rtype);
357 AddressLiteral(address target, RelocationHolder const& rspec)
358 : _rspec(rspec),
359 _is_lval(false),
360 _target(target)
361 {}
363 AddressLiteral addr() {
364 AddressLiteral ret = *this;
365 ret._is_lval = true;
366 return ret;
367 }
370 private:
372 address target() { return _target; }
373 bool is_lval() { return _is_lval; }
375 relocInfo::relocType reloc() const { return _rspec.type(); }
376 const RelocationHolder& rspec() const { return _rspec; }
378 friend class Assembler;
379 friend class MacroAssembler;
380 friend class Address;
381 friend class LIR_Assembler;
382 };
384 // Convience classes
385 class RuntimeAddress: public AddressLiteral {
387 public:
389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
391 };
393 class ExternalAddress: public AddressLiteral {
394 private:
395 static relocInfo::relocType reloc_for_target(address target) {
396 // Sometimes ExternalAddress is used for values which aren't
397 // exactly addresses, like the card table base.
398 // external_word_type can't be used for values in the first page
399 // so just skip the reloc in that case.
400 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
401 }
403 public:
405 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
407 };
409 class InternalAddress: public AddressLiteral {
411 public:
413 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
415 };
417 // x86 can do array addressing as a single operation since disp can be an absolute
418 // address amd64 can't. We create a class that expresses the concept but does extra
419 // magic on amd64 to get the final result
421 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
422 private:
424 AddressLiteral _base;
425 Address _index;
427 public:
429 ArrayAddress() {};
430 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
431 AddressLiteral base() { return _base; }
432 Address index() { return _index; }
434 };
436 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
438 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
439 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
440 // is what you get. The Assembler is generating code into a CodeBuffer.
442 class Assembler : public AbstractAssembler {
443 friend class AbstractAssembler; // for the non-virtual hack
444 friend class LIR_Assembler; // as_Address()
445 friend class StubGenerator;
447 public:
448 enum Condition { // The x86 condition codes used for conditional jumps/moves.
449 zero = 0x4,
450 notZero = 0x5,
451 equal = 0x4,
452 notEqual = 0x5,
453 less = 0xc,
454 lessEqual = 0xe,
455 greater = 0xf,
456 greaterEqual = 0xd,
457 below = 0x2,
458 belowEqual = 0x6,
459 above = 0x7,
460 aboveEqual = 0x3,
461 overflow = 0x0,
462 noOverflow = 0x1,
463 carrySet = 0x2,
464 carryClear = 0x3,
465 negative = 0x8,
466 positive = 0x9,
467 parity = 0xa,
468 noParity = 0xb
469 };
471 enum Prefix {
472 // segment overrides
473 CS_segment = 0x2e,
474 SS_segment = 0x36,
475 DS_segment = 0x3e,
476 ES_segment = 0x26,
477 FS_segment = 0x64,
478 GS_segment = 0x65,
480 REX = 0x40,
482 REX_B = 0x41,
483 REX_X = 0x42,
484 REX_XB = 0x43,
485 REX_R = 0x44,
486 REX_RB = 0x45,
487 REX_RX = 0x46,
488 REX_RXB = 0x47,
490 REX_W = 0x48,
492 REX_WB = 0x49,
493 REX_WX = 0x4A,
494 REX_WXB = 0x4B,
495 REX_WR = 0x4C,
496 REX_WRB = 0x4D,
497 REX_WRX = 0x4E,
498 REX_WRXB = 0x4F,
500 VEX_3bytes = 0xC4,
501 VEX_2bytes = 0xC5
502 };
504 enum VexPrefix {
505 VEX_B = 0x20,
506 VEX_X = 0x40,
507 VEX_R = 0x80,
508 VEX_W = 0x80
509 };
511 enum VexSimdPrefix {
512 VEX_SIMD_NONE = 0x0,
513 VEX_SIMD_66 = 0x1,
514 VEX_SIMD_F3 = 0x2,
515 VEX_SIMD_F2 = 0x3
516 };
518 enum VexOpcode {
519 VEX_OPCODE_NONE = 0x0,
520 VEX_OPCODE_0F = 0x1,
521 VEX_OPCODE_0F_38 = 0x2,
522 VEX_OPCODE_0F_3A = 0x3
523 };
525 enum WhichOperand {
526 // input to locate_operand, and format code for relocations
527 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
528 disp32_operand = 1, // embedded 32-bit displacement or address
529 call32_operand = 2, // embedded 32-bit self-relative displacement
530 #ifndef _LP64
531 _WhichOperand_limit = 3
532 #else
533 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
534 _WhichOperand_limit = 4
535 #endif
536 };
540 // NOTE: The general philopsophy of the declarations here is that 64bit versions
541 // of instructions are freely declared without the need for wrapping them an ifdef.
542 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
543 // In the .cpp file the implementations are wrapped so that they are dropped out
544 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
545 // to the size it was prior to merging up the 32bit and 64bit assemblers.
546 //
547 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
548 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
550 private:
553 // 64bit prefixes
554 int prefix_and_encode(int reg_enc, bool byteinst = false);
555 int prefixq_and_encode(int reg_enc);
557 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
558 int prefixq_and_encode(int dst_enc, int src_enc);
560 void prefix(Register reg);
561 void prefix(Address adr);
562 void prefixq(Address adr);
564 void prefix(Address adr, Register reg, bool byteinst = false);
565 void prefix(Address adr, XMMRegister reg);
566 void prefixq(Address adr, Register reg);
567 void prefixq(Address adr, XMMRegister reg);
569 void prefetch_prefix(Address src);
571 void rex_prefix(Address adr, XMMRegister xreg,
572 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
573 int rex_prefix_and_encode(int dst_enc, int src_enc,
574 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
576 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
577 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
578 bool vector256);
580 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
581 VexSimdPrefix pre, VexOpcode opc,
582 bool vex_w, bool vector256);
584 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
585 VexSimdPrefix pre, bool vector256 = false) {
586 int dst_enc = dst->encoding();
587 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
588 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
589 }
591 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
592 VexSimdPrefix pre, VexOpcode opc,
593 bool vex_w, bool vector256);
595 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
596 VexSimdPrefix pre, bool vector256 = false,
597 VexOpcode opc = VEX_OPCODE_0F) {
598 int src_enc = src->encoding();
599 int dst_enc = dst->encoding();
600 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
601 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256);
602 }
604 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
605 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
606 bool rex_w = false, bool vector256 = false);
608 void simd_prefix(XMMRegister dst, Address src,
609 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
610 simd_prefix(dst, xnoreg, src, pre, opc);
611 }
613 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
614 simd_prefix(src, dst, pre);
615 }
616 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
617 VexSimdPrefix pre) {
618 bool rex_w = true;
619 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
620 }
622 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
623 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
624 bool rex_w = false, bool vector256 = false);
626 // Move/convert 32-bit integer value.
627 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
628 VexSimdPrefix pre) {
629 // It is OK to cast from Register to XMMRegister to pass argument here
630 // since only encoding is used in simd_prefix_and_encode() and number of
631 // Gen and Xmm registers are the same.
632 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre);
633 }
634 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
635 return simd_prefix_and_encode(dst, xnoreg, src, pre);
636 }
637 int simd_prefix_and_encode(Register dst, XMMRegister src,
638 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
639 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc);
640 }
642 // Move/convert 64-bit integer value.
643 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
644 VexSimdPrefix pre) {
645 bool rex_w = true;
646 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w);
647 }
648 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
649 return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
650 }
651 int simd_prefix_and_encode_q(Register dst, XMMRegister src,
652 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
653 bool rex_w = true;
654 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w);
655 }
657 // Helper functions for groups of instructions
658 void emit_arith_b(int op1, int op2, Register dst, int imm8);
660 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
661 // Force generation of a 4 byte immediate value even if it fits into 8bit
662 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
663 void emit_arith(int op1, int op2, Register dst, Register src);
665 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
666 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
667 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
668 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
669 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
670 Address src, VexSimdPrefix pre, bool vector256);
671 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
672 XMMRegister src, VexSimdPrefix pre, bool vector256);
674 void emit_operand(Register reg,
675 Register base, Register index, Address::ScaleFactor scale,
676 int disp,
677 RelocationHolder const& rspec,
678 int rip_relative_correction = 0);
680 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
682 // operands that only take the original 32bit registers
683 void emit_operand32(Register reg, Address adr);
685 void emit_operand(XMMRegister reg,
686 Register base, Register index, Address::ScaleFactor scale,
687 int disp,
688 RelocationHolder const& rspec);
690 void emit_operand(XMMRegister reg, Address adr);
692 void emit_operand(MMXRegister reg, Address adr);
694 // workaround gcc (3.2.1-7) bug
695 void emit_operand(Address adr, MMXRegister reg);
698 // Immediate-to-memory forms
699 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
701 void emit_farith(int b1, int b2, int i);
704 protected:
705 #ifdef ASSERT
706 void check_relocation(RelocationHolder const& rspec, int format);
707 #endif
709 inline void emit_long64(jlong x);
711 void emit_data(jint data, relocInfo::relocType rtype, int format);
712 void emit_data(jint data, RelocationHolder const& rspec, int format);
713 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
714 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
716 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
718 // These are all easily abused and hence protected
720 // 32BIT ONLY SECTION
721 #ifndef _LP64
722 // Make these disappear in 64bit mode since they would never be correct
723 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
724 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
726 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
727 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
729 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
730 #else
731 // 64BIT ONLY SECTION
732 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
734 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
735 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
737 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
738 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
739 #endif // _LP64
741 // These are unique in that we are ensured by the caller that the 32bit
742 // relative in these instructions will always be able to reach the potentially
743 // 64bit address described by entry. Since they can take a 64bit address they
744 // don't have the 32 suffix like the other instructions in this class.
746 void call_literal(address entry, RelocationHolder const& rspec);
747 void jmp_literal(address entry, RelocationHolder const& rspec);
749 // Avoid using directly section
750 // Instructions in this section are actually usable by anyone without danger
751 // of failure but have performance issues that are addressed my enhanced
752 // instructions which will do the proper thing base on the particular cpu.
753 // We protect them because we don't trust you...
755 // Don't use next inc() and dec() methods directly. INC & DEC instructions
756 // could cause a partial flag stall since they don't set CF flag.
757 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
758 // which call inc() & dec() or add() & sub() in accordance with
759 // the product flag UseIncDec value.
761 void decl(Register dst);
762 void decl(Address dst);
763 void decq(Register dst);
764 void decq(Address dst);
766 void incl(Register dst);
767 void incl(Address dst);
768 void incq(Register dst);
769 void incq(Address dst);
771 // New cpus require use of movsd and movss to avoid partial register stall
772 // when loading from memory. But for old Opteron use movlpd instead of movsd.
773 // The selection is done in MacroAssembler::movdbl() and movflt().
775 // Move Scalar Single-Precision Floating-Point Values
776 void movss(XMMRegister dst, Address src);
777 void movss(XMMRegister dst, XMMRegister src);
778 void movss(Address dst, XMMRegister src);
780 // Move Scalar Double-Precision Floating-Point Values
781 void movsd(XMMRegister dst, Address src);
782 void movsd(XMMRegister dst, XMMRegister src);
783 void movsd(Address dst, XMMRegister src);
784 void movlpd(XMMRegister dst, Address src);
786 // New cpus require use of movaps and movapd to avoid partial register stall
787 // when moving between registers.
788 void movaps(XMMRegister dst, XMMRegister src);
789 void movapd(XMMRegister dst, XMMRegister src);
791 // End avoid using directly
794 // Instruction prefixes
795 void prefix(Prefix p);
797 public:
799 // Creation
800 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
802 // Decoding
803 static address locate_operand(address inst, WhichOperand which);
804 static address locate_next_instruction(address inst);
806 // Utilities
807 static bool is_polling_page_far() NOT_LP64({ return false;});
809 // Generic instructions
810 // Does 32bit or 64bit as needed for the platform. In some sense these
811 // belong in macro assembler but there is no need for both varieties to exist
813 void lea(Register dst, Address src);
815 void mov(Register dst, Register src);
817 void pusha();
818 void popa();
820 void pushf();
821 void popf();
823 void push(int32_t imm32);
825 void push(Register src);
827 void pop(Register dst);
829 // These are dummies to prevent surprise implicit conversions to Register
830 void push(void* v);
831 void pop(void* v);
833 // These do register sized moves/scans
834 void rep_mov();
835 void rep_set();
836 void repne_scan();
837 #ifdef _LP64
838 void repne_scanl();
839 #endif
841 // Vanilla instructions in lexical order
843 void adcl(Address dst, int32_t imm32);
844 void adcl(Address dst, Register src);
845 void adcl(Register dst, int32_t imm32);
846 void adcl(Register dst, Address src);
847 void adcl(Register dst, Register src);
849 void adcq(Register dst, int32_t imm32);
850 void adcq(Register dst, Address src);
851 void adcq(Register dst, Register src);
853 void addl(Address dst, int32_t imm32);
854 void addl(Address dst, Register src);
855 void addl(Register dst, int32_t imm32);
856 void addl(Register dst, Address src);
857 void addl(Register dst, Register src);
859 void addq(Address dst, int32_t imm32);
860 void addq(Address dst, Register src);
861 void addq(Register dst, int32_t imm32);
862 void addq(Register dst, Address src);
863 void addq(Register dst, Register src);
865 void addr_nop_4();
866 void addr_nop_5();
867 void addr_nop_7();
868 void addr_nop_8();
870 // Add Scalar Double-Precision Floating-Point Values
871 void addsd(XMMRegister dst, Address src);
872 void addsd(XMMRegister dst, XMMRegister src);
874 // Add Scalar Single-Precision Floating-Point Values
875 void addss(XMMRegister dst, Address src);
876 void addss(XMMRegister dst, XMMRegister src);
878 // AES instructions
879 void aesdec(XMMRegister dst, Address src);
880 void aesdec(XMMRegister dst, XMMRegister src);
881 void aesdeclast(XMMRegister dst, Address src);
882 void aesdeclast(XMMRegister dst, XMMRegister src);
883 void aesenc(XMMRegister dst, Address src);
884 void aesenc(XMMRegister dst, XMMRegister src);
885 void aesenclast(XMMRegister dst, Address src);
886 void aesenclast(XMMRegister dst, XMMRegister src);
889 void andl(Address dst, int32_t imm32);
890 void andl(Register dst, int32_t imm32);
891 void andl(Register dst, Address src);
892 void andl(Register dst, Register src);
894 void andq(Address dst, int32_t imm32);
895 void andq(Register dst, int32_t imm32);
896 void andq(Register dst, Address src);
897 void andq(Register dst, Register src);
899 void bsfl(Register dst, Register src);
900 void bsrl(Register dst, Register src);
902 #ifdef _LP64
903 void bsfq(Register dst, Register src);
904 void bsrq(Register dst, Register src);
905 #endif
907 void bswapl(Register reg);
909 void bswapq(Register reg);
911 void call(Label& L, relocInfo::relocType rtype);
912 void call(Register reg); // push pc; pc <- reg
913 void call(Address adr); // push pc; pc <- adr
915 void cdql();
917 void cdqq();
919 void cld() { emit_byte(0xfc); }
921 void clflush(Address adr);
923 void cmovl(Condition cc, Register dst, Register src);
924 void cmovl(Condition cc, Register dst, Address src);
926 void cmovq(Condition cc, Register dst, Register src);
927 void cmovq(Condition cc, Register dst, Address src);
930 void cmpb(Address dst, int imm8);
932 void cmpl(Address dst, int32_t imm32);
934 void cmpl(Register dst, int32_t imm32);
935 void cmpl(Register dst, Register src);
936 void cmpl(Register dst, Address src);
938 void cmpq(Address dst, int32_t imm32);
939 void cmpq(Address dst, Register src);
941 void cmpq(Register dst, int32_t imm32);
942 void cmpq(Register dst, Register src);
943 void cmpq(Register dst, Address src);
945 // these are dummies used to catch attempting to convert NULL to Register
946 void cmpl(Register dst, void* junk); // dummy
947 void cmpq(Register dst, void* junk); // dummy
949 void cmpw(Address dst, int imm16);
951 void cmpxchg8 (Address adr);
953 void cmpxchgl(Register reg, Address adr);
955 void cmpxchgq(Register reg, Address adr);
957 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
958 void comisd(XMMRegister dst, Address src);
959 void comisd(XMMRegister dst, XMMRegister src);
961 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
962 void comiss(XMMRegister dst, Address src);
963 void comiss(XMMRegister dst, XMMRegister src);
965 // Identify processor type and features
966 void cpuid() {
967 emit_byte(0x0F);
968 emit_byte(0xA2);
969 }
971 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
972 void cvtsd2ss(XMMRegister dst, XMMRegister src);
973 void cvtsd2ss(XMMRegister dst, Address src);
975 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
976 void cvtsi2sdl(XMMRegister dst, Register src);
977 void cvtsi2sdl(XMMRegister dst, Address src);
978 void cvtsi2sdq(XMMRegister dst, Register src);
979 void cvtsi2sdq(XMMRegister dst, Address src);
981 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
982 void cvtsi2ssl(XMMRegister dst, Register src);
983 void cvtsi2ssl(XMMRegister dst, Address src);
984 void cvtsi2ssq(XMMRegister dst, Register src);
985 void cvtsi2ssq(XMMRegister dst, Address src);
987 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
988 void cvtdq2pd(XMMRegister dst, XMMRegister src);
990 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
991 void cvtdq2ps(XMMRegister dst, XMMRegister src);
993 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
994 void cvtss2sd(XMMRegister dst, XMMRegister src);
995 void cvtss2sd(XMMRegister dst, Address src);
997 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
998 void cvttsd2sil(Register dst, Address src);
999 void cvttsd2sil(Register dst, XMMRegister src);
1000 void cvttsd2siq(Register dst, XMMRegister src);
1002 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1003 void cvttss2sil(Register dst, XMMRegister src);
1004 void cvttss2siq(Register dst, XMMRegister src);
1006 // Divide Scalar Double-Precision Floating-Point Values
1007 void divsd(XMMRegister dst, Address src);
1008 void divsd(XMMRegister dst, XMMRegister src);
1010 // Divide Scalar Single-Precision Floating-Point Values
1011 void divss(XMMRegister dst, Address src);
1012 void divss(XMMRegister dst, XMMRegister src);
1014 void emms();
1016 void fabs();
1018 void fadd(int i);
1020 void fadd_d(Address src);
1021 void fadd_s(Address src);
1023 // "Alternate" versions of x87 instructions place result down in FPU
1024 // stack instead of on TOS
1026 void fadda(int i); // "alternate" fadd
1027 void faddp(int i = 1);
1029 void fchs();
1031 void fcom(int i);
1033 void fcomp(int i = 1);
1034 void fcomp_d(Address src);
1035 void fcomp_s(Address src);
1037 void fcompp();
1039 void fcos();
1041 void fdecstp();
1043 void fdiv(int i);
1044 void fdiv_d(Address src);
1045 void fdivr_s(Address src);
1046 void fdiva(int i); // "alternate" fdiv
1047 void fdivp(int i = 1);
1049 void fdivr(int i);
1050 void fdivr_d(Address src);
1051 void fdiv_s(Address src);
1053 void fdivra(int i); // "alternate" reversed fdiv
1055 void fdivrp(int i = 1);
1057 void ffree(int i = 0);
1059 void fild_d(Address adr);
1060 void fild_s(Address adr);
1062 void fincstp();
1064 void finit();
1066 void fist_s (Address adr);
1067 void fistp_d(Address adr);
1068 void fistp_s(Address adr);
1070 void fld1();
1072 void fld_d(Address adr);
1073 void fld_s(Address adr);
1074 void fld_s(int index);
1075 void fld_x(Address adr); // extended-precision (80-bit) format
1077 void fldcw(Address src);
1079 void fldenv(Address src);
1081 void fldlg2();
1083 void fldln2();
1085 void fldz();
1087 void flog();
1088 void flog10();
1090 void fmul(int i);
1092 void fmul_d(Address src);
1093 void fmul_s(Address src);
1095 void fmula(int i); // "alternate" fmul
1097 void fmulp(int i = 1);
1099 void fnsave(Address dst);
1101 void fnstcw(Address src);
1103 void fnstsw_ax();
1105 void fprem();
1106 void fprem1();
1108 void frstor(Address src);
1110 void fsin();
1112 void fsqrt();
1114 void fst_d(Address adr);
1115 void fst_s(Address adr);
1117 void fstp_d(Address adr);
1118 void fstp_d(int index);
1119 void fstp_s(Address adr);
1120 void fstp_x(Address adr); // extended-precision (80-bit) format
1122 void fsub(int i);
1123 void fsub_d(Address src);
1124 void fsub_s(Address src);
1126 void fsuba(int i); // "alternate" fsub
1128 void fsubp(int i = 1);
1130 void fsubr(int i);
1131 void fsubr_d(Address src);
1132 void fsubr_s(Address src);
1134 void fsubra(int i); // "alternate" reversed fsub
1136 void fsubrp(int i = 1);
1138 void ftan();
1140 void ftst();
1142 void fucomi(int i = 1);
1143 void fucomip(int i = 1);
1145 void fwait();
1147 void fxch(int i = 1);
1149 void fxrstor(Address src);
1151 void fxsave(Address dst);
1153 void fyl2x();
1154 void frndint();
1155 void f2xm1();
1156 void fldl2e();
1158 void hlt();
1160 void idivl(Register src);
1161 void divl(Register src); // Unsigned division
1163 void idivq(Register src);
1165 void imull(Register dst, Register src);
1166 void imull(Register dst, Register src, int value);
1168 void imulq(Register dst, Register src);
1169 void imulq(Register dst, Register src, int value);
1172 // jcc is the generic conditional branch generator to run-
1173 // time routines, jcc is used for branches to labels. jcc
1174 // takes a branch opcode (cc) and a label (L) and generates
1175 // either a backward branch or a forward branch and links it
1176 // to the label fixup chain. Usage:
1177 //
1178 // Label L; // unbound label
1179 // jcc(cc, L); // forward branch to unbound label
1180 // bind(L); // bind label to the current pc
1181 // jcc(cc, L); // backward branch to bound label
1182 // bind(L); // illegal: a label may be bound only once
1183 //
1184 // Note: The same Label can be used for forward and backward branches
1185 // but it may be bound only once.
1187 void jcc(Condition cc, Label& L, bool maybe_short = true);
1189 // Conditional jump to a 8-bit offset to L.
1190 // WARNING: be very careful using this for forward jumps. If the label is
1191 // not bound within an 8-bit offset of this instruction, a run-time error
1192 // will occur.
1193 void jccb(Condition cc, Label& L);
1195 void jmp(Address entry); // pc <- entry
1197 // Label operations & relative jumps (PPUM Appendix D)
1198 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1200 void jmp(Register entry); // pc <- entry
1202 // Unconditional 8-bit offset jump to L.
1203 // WARNING: be very careful using this for forward jumps. If the label is
1204 // not bound within an 8-bit offset of this instruction, a run-time error
1205 // will occur.
1206 void jmpb(Label& L);
1208 void ldmxcsr( Address src );
1210 void leal(Register dst, Address src);
1212 void leaq(Register dst, Address src);
1214 void lfence() {
1215 emit_byte(0x0F);
1216 emit_byte(0xAE);
1217 emit_byte(0xE8);
1218 }
1220 void lock();
1222 void lzcntl(Register dst, Register src);
1224 #ifdef _LP64
1225 void lzcntq(Register dst, Register src);
1226 #endif
1228 enum Membar_mask_bits {
1229 StoreStore = 1 << 3,
1230 LoadStore = 1 << 2,
1231 StoreLoad = 1 << 1,
1232 LoadLoad = 1 << 0
1233 };
1235 // Serializes memory and blows flags
1236 void membar(Membar_mask_bits order_constraint) {
1237 if (os::is_MP()) {
1238 // We only have to handle StoreLoad
1239 if (order_constraint & StoreLoad) {
1240 // All usable chips support "locked" instructions which suffice
1241 // as barriers, and are much faster than the alternative of
1242 // using cpuid instruction. We use here a locked add [esp],0.
1243 // This is conveniently otherwise a no-op except for blowing
1244 // flags.
1245 // Any change to this code may need to revisit other places in
1246 // the code where this idiom is used, in particular the
1247 // orderAccess code.
1248 lock();
1249 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1250 }
1251 }
1252 }
1254 void mfence();
1256 // Moves
1258 void mov64(Register dst, int64_t imm64);
1260 void movb(Address dst, Register src);
1261 void movb(Address dst, int imm8);
1262 void movb(Register dst, Address src);
1264 void movdl(XMMRegister dst, Register src);
1265 void movdl(Register dst, XMMRegister src);
1266 void movdl(XMMRegister dst, Address src);
1267 void movdl(Address dst, XMMRegister src);
1269 // Move Double Quadword
1270 void movdq(XMMRegister dst, Register src);
1271 void movdq(Register dst, XMMRegister src);
1273 // Move Aligned Double Quadword
1274 void movdqa(XMMRegister dst, XMMRegister src);
1276 // Move Unaligned Double Quadword
1277 void movdqu(Address dst, XMMRegister src);
1278 void movdqu(XMMRegister dst, Address src);
1279 void movdqu(XMMRegister dst, XMMRegister src);
1281 // Move Unaligned 256bit Vector
1282 void vmovdqu(Address dst, XMMRegister src);
1283 void vmovdqu(XMMRegister dst, Address src);
1284 void vmovdqu(XMMRegister dst, XMMRegister src);
1286 // Move lower 64bit to high 64bit in 128bit register
1287 void movlhps(XMMRegister dst, XMMRegister src);
1289 void movl(Register dst, int32_t imm32);
1290 void movl(Address dst, int32_t imm32);
1291 void movl(Register dst, Register src);
1292 void movl(Register dst, Address src);
1293 void movl(Address dst, Register src);
1295 // These dummies prevent using movl from converting a zero (like NULL) into Register
1296 // by giving the compiler two choices it can't resolve
1298 void movl(Address dst, void* junk);
1299 void movl(Register dst, void* junk);
1301 #ifdef _LP64
1302 void movq(Register dst, Register src);
1303 void movq(Register dst, Address src);
1304 void movq(Address dst, Register src);
1305 #endif
1307 void movq(Address dst, MMXRegister src );
1308 void movq(MMXRegister dst, Address src );
1310 #ifdef _LP64
1311 // These dummies prevent using movq from converting a zero (like NULL) into Register
1312 // by giving the compiler two choices it can't resolve
1314 void movq(Address dst, void* dummy);
1315 void movq(Register dst, void* dummy);
1316 #endif
1318 // Move Quadword
1319 void movq(Address dst, XMMRegister src);
1320 void movq(XMMRegister dst, Address src);
1322 void movsbl(Register dst, Address src);
1323 void movsbl(Register dst, Register src);
1325 #ifdef _LP64
1326 void movsbq(Register dst, Address src);
1327 void movsbq(Register dst, Register src);
1329 // Move signed 32bit immediate to 64bit extending sign
1330 void movslq(Address dst, int32_t imm64);
1331 void movslq(Register dst, int32_t imm64);
1333 void movslq(Register dst, Address src);
1334 void movslq(Register dst, Register src);
1335 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1336 #endif
1338 void movswl(Register dst, Address src);
1339 void movswl(Register dst, Register src);
1341 #ifdef _LP64
1342 void movswq(Register dst, Address src);
1343 void movswq(Register dst, Register src);
1344 #endif
1346 void movw(Address dst, int imm16);
1347 void movw(Register dst, Address src);
1348 void movw(Address dst, Register src);
1350 void movzbl(Register dst, Address src);
1351 void movzbl(Register dst, Register src);
1353 #ifdef _LP64
1354 void movzbq(Register dst, Address src);
1355 void movzbq(Register dst, Register src);
1356 #endif
1358 void movzwl(Register dst, Address src);
1359 void movzwl(Register dst, Register src);
1361 #ifdef _LP64
1362 void movzwq(Register dst, Address src);
1363 void movzwq(Register dst, Register src);
1364 #endif
1366 void mull(Address src);
1367 void mull(Register src);
1369 // Multiply Scalar Double-Precision Floating-Point Values
1370 void mulsd(XMMRegister dst, Address src);
1371 void mulsd(XMMRegister dst, XMMRegister src);
1373 // Multiply Scalar Single-Precision Floating-Point Values
1374 void mulss(XMMRegister dst, Address src);
1375 void mulss(XMMRegister dst, XMMRegister src);
1377 void negl(Register dst);
1379 #ifdef _LP64
1380 void negq(Register dst);
1381 #endif
1383 void nop(int i = 1);
1385 void notl(Register dst);
1387 #ifdef _LP64
1388 void notq(Register dst);
1389 #endif
1391 void orl(Address dst, int32_t imm32);
1392 void orl(Register dst, int32_t imm32);
1393 void orl(Register dst, Address src);
1394 void orl(Register dst, Register src);
1396 void orq(Address dst, int32_t imm32);
1397 void orq(Register dst, int32_t imm32);
1398 void orq(Register dst, Address src);
1399 void orq(Register dst, Register src);
1401 // Pack with unsigned saturation
1402 void packuswb(XMMRegister dst, XMMRegister src);
1403 void packuswb(XMMRegister dst, Address src);
1405 // SSE4.2 string instructions
1406 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1407 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1409 // SSE4.1 packed move
1410 void pmovzxbw(XMMRegister dst, XMMRegister src);
1411 void pmovzxbw(XMMRegister dst, Address src);
1413 #ifndef _LP64 // no 32bit push/pop on amd64
1414 void popl(Address dst);
1415 #endif
1417 #ifdef _LP64
1418 void popq(Address dst);
1419 #endif
1421 void popcntl(Register dst, Address src);
1422 void popcntl(Register dst, Register src);
1424 #ifdef _LP64
1425 void popcntq(Register dst, Address src);
1426 void popcntq(Register dst, Register src);
1427 #endif
1429 // Prefetches (SSE, SSE2, 3DNOW only)
1431 void prefetchnta(Address src);
1432 void prefetchr(Address src);
1433 void prefetcht0(Address src);
1434 void prefetcht1(Address src);
1435 void prefetcht2(Address src);
1436 void prefetchw(Address src);
1438 // Shuffle Bytes
1439 void pshufb(XMMRegister dst, XMMRegister src);
1440 void pshufb(XMMRegister dst, Address src);
1442 // Shuffle Packed Doublewords
1443 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1444 void pshufd(XMMRegister dst, Address src, int mode);
1446 // Shuffle Packed Low Words
1447 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1448 void pshuflw(XMMRegister dst, Address src, int mode);
1450 // Shift Right by bytes Logical DoubleQuadword Immediate
1451 void psrldq(XMMRegister dst, int shift);
1453 // Logical Compare Double Quadword
1454 void ptest(XMMRegister dst, XMMRegister src);
1455 void ptest(XMMRegister dst, Address src);
1457 // Interleave Low Bytes
1458 void punpcklbw(XMMRegister dst, XMMRegister src);
1459 void punpcklbw(XMMRegister dst, Address src);
1461 // Interleave Low Doublewords
1462 void punpckldq(XMMRegister dst, XMMRegister src);
1463 void punpckldq(XMMRegister dst, Address src);
1465 // Interleave Low Quadwords
1466 void punpcklqdq(XMMRegister dst, XMMRegister src);
1468 #ifndef _LP64 // no 32bit push/pop on amd64
1469 void pushl(Address src);
1470 #endif
1472 void pushq(Address src);
1474 void rcll(Register dst, int imm8);
1476 void rclq(Register dst, int imm8);
1478 void ret(int imm16);
1480 void sahf();
1482 void sarl(Register dst, int imm8);
1483 void sarl(Register dst);
1485 void sarq(Register dst, int imm8);
1486 void sarq(Register dst);
1488 void sbbl(Address dst, int32_t imm32);
1489 void sbbl(Register dst, int32_t imm32);
1490 void sbbl(Register dst, Address src);
1491 void sbbl(Register dst, Register src);
1493 void sbbq(Address dst, int32_t imm32);
1494 void sbbq(Register dst, int32_t imm32);
1495 void sbbq(Register dst, Address src);
1496 void sbbq(Register dst, Register src);
1498 void setb(Condition cc, Register dst);
1500 void shldl(Register dst, Register src);
1502 void shll(Register dst, int imm8);
1503 void shll(Register dst);
1505 void shlq(Register dst, int imm8);
1506 void shlq(Register dst);
1508 void shrdl(Register dst, Register src);
1510 void shrl(Register dst, int imm8);
1511 void shrl(Register dst);
1513 void shrq(Register dst, int imm8);
1514 void shrq(Register dst);
1516 void smovl(); // QQQ generic?
1518 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1519 void sqrtsd(XMMRegister dst, Address src);
1520 void sqrtsd(XMMRegister dst, XMMRegister src);
1522 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1523 void sqrtss(XMMRegister dst, Address src);
1524 void sqrtss(XMMRegister dst, XMMRegister src);
1526 void std() { emit_byte(0xfd); }
1528 void stmxcsr( Address dst );
1530 void subl(Address dst, int32_t imm32);
1531 void subl(Address dst, Register src);
1532 void subl(Register dst, int32_t imm32);
1533 void subl(Register dst, Address src);
1534 void subl(Register dst, Register src);
1536 void subq(Address dst, int32_t imm32);
1537 void subq(Address dst, Register src);
1538 void subq(Register dst, int32_t imm32);
1539 void subq(Register dst, Address src);
1540 void subq(Register dst, Register src);
1542 // Force generation of a 4 byte immediate value even if it fits into 8bit
1543 void subl_imm32(Register dst, int32_t imm32);
1544 void subq_imm32(Register dst, int32_t imm32);
1546 // Subtract Scalar Double-Precision Floating-Point Values
1547 void subsd(XMMRegister dst, Address src);
1548 void subsd(XMMRegister dst, XMMRegister src);
1550 // Subtract Scalar Single-Precision Floating-Point Values
1551 void subss(XMMRegister dst, Address src);
1552 void subss(XMMRegister dst, XMMRegister src);
1554 void testb(Register dst, int imm8);
1556 void testl(Register dst, int32_t imm32);
1557 void testl(Register dst, Register src);
1558 void testl(Register dst, Address src);
1560 void testq(Register dst, int32_t imm32);
1561 void testq(Register dst, Register src);
1564 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1565 void ucomisd(XMMRegister dst, Address src);
1566 void ucomisd(XMMRegister dst, XMMRegister src);
1568 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1569 void ucomiss(XMMRegister dst, Address src);
1570 void ucomiss(XMMRegister dst, XMMRegister src);
1572 void xaddl(Address dst, Register src);
1574 void xaddq(Address dst, Register src);
1576 void xchgl(Register reg, Address adr);
1577 void xchgl(Register dst, Register src);
1579 void xchgq(Register reg, Address adr);
1580 void xchgq(Register dst, Register src);
1582 // Get Value of Extended Control Register
1583 void xgetbv() {
1584 emit_byte(0x0F);
1585 emit_byte(0x01);
1586 emit_byte(0xD0);
1587 }
1589 void xorl(Register dst, int32_t imm32);
1590 void xorl(Register dst, Address src);
1591 void xorl(Register dst, Register src);
1593 void xorq(Register dst, Address src);
1594 void xorq(Register dst, Register src);
1596 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1598 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1600 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1601 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1602 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1603 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1604 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1605 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1606 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1607 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1608 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1609 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1610 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1611 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1612 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1613 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1614 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1615 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1618 //====================VECTOR ARITHMETIC=====================================
1620 // Add Packed Floating-Point Values
1621 void addpd(XMMRegister dst, XMMRegister src);
1622 void addps(XMMRegister dst, XMMRegister src);
1623 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1624 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1625 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1626 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1628 // Subtract Packed Floating-Point Values
1629 void subpd(XMMRegister dst, XMMRegister src);
1630 void subps(XMMRegister dst, XMMRegister src);
1631 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1632 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1633 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1634 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1636 // Multiply Packed Floating-Point Values
1637 void mulpd(XMMRegister dst, XMMRegister src);
1638 void mulps(XMMRegister dst, XMMRegister src);
1639 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1640 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1641 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1642 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1644 // Divide Packed Floating-Point Values
1645 void divpd(XMMRegister dst, XMMRegister src);
1646 void divps(XMMRegister dst, XMMRegister src);
1647 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1648 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1649 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1650 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1652 // Bitwise Logical AND of Packed Floating-Point Values
1653 void andpd(XMMRegister dst, XMMRegister src);
1654 void andps(XMMRegister dst, XMMRegister src);
1655 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1656 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1657 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1658 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1660 // Bitwise Logical XOR of Packed Floating-Point Values
1661 void xorpd(XMMRegister dst, XMMRegister src);
1662 void xorps(XMMRegister dst, XMMRegister src);
1663 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1664 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1665 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1666 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1668 // Add packed integers
1669 void paddb(XMMRegister dst, XMMRegister src);
1670 void paddw(XMMRegister dst, XMMRegister src);
1671 void paddd(XMMRegister dst, XMMRegister src);
1672 void paddq(XMMRegister dst, XMMRegister src);
1673 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1674 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1675 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1676 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1677 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1678 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1679 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1680 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1682 // Sub packed integers
1683 void psubb(XMMRegister dst, XMMRegister src);
1684 void psubw(XMMRegister dst, XMMRegister src);
1685 void psubd(XMMRegister dst, XMMRegister src);
1686 void psubq(XMMRegister dst, XMMRegister src);
1687 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1688 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1689 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1690 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1691 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1692 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1693 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1694 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1696 // Multiply packed integers (only shorts and ints)
1697 void pmullw(XMMRegister dst, XMMRegister src);
1698 void pmulld(XMMRegister dst, XMMRegister src);
1699 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1700 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1701 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1702 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1704 // Shift left packed integers
1705 void psllw(XMMRegister dst, int shift);
1706 void pslld(XMMRegister dst, int shift);
1707 void psllq(XMMRegister dst, int shift);
1708 void psllw(XMMRegister dst, XMMRegister shift);
1709 void pslld(XMMRegister dst, XMMRegister shift);
1710 void psllq(XMMRegister dst, XMMRegister shift);
1711 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1712 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1713 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1714 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1715 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1716 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1718 // Logical shift right packed integers
1719 void psrlw(XMMRegister dst, int shift);
1720 void psrld(XMMRegister dst, int shift);
1721 void psrlq(XMMRegister dst, int shift);
1722 void psrlw(XMMRegister dst, XMMRegister shift);
1723 void psrld(XMMRegister dst, XMMRegister shift);
1724 void psrlq(XMMRegister dst, XMMRegister shift);
1725 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1726 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1727 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1728 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1729 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1730 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1732 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1733 void psraw(XMMRegister dst, int shift);
1734 void psrad(XMMRegister dst, int shift);
1735 void psraw(XMMRegister dst, XMMRegister shift);
1736 void psrad(XMMRegister dst, XMMRegister shift);
1737 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1738 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1739 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1740 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1742 // And packed integers
1743 void pand(XMMRegister dst, XMMRegister src);
1744 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1745 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1747 // Or packed integers
1748 void por(XMMRegister dst, XMMRegister src);
1749 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1750 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1752 // Xor packed integers
1753 void pxor(XMMRegister dst, XMMRegister src);
1754 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1755 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1757 // Copy low 128bit into high 128bit of YMM registers.
1758 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1759 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1761 // Load/store high 128bit of YMM registers which does not destroy other half.
1762 void vinsertf128h(XMMRegister dst, Address src);
1763 void vinserti128h(XMMRegister dst, Address src);
1764 void vextractf128h(Address dst, XMMRegister src);
1765 void vextracti128h(Address dst, XMMRegister src);
1767 // AVX instruction which is used to clear upper 128 bits of YMM registers and
1768 // to avoid transaction penalty between AVX and SSE states. There is no
1769 // penalty if legacy SSE instructions are encoded using VEX prefix because
1770 // they always clear upper 128 bits. It should be used before calling
1771 // runtime code and native libraries.
1772 void vzeroupper();
1774 protected:
1775 // Next instructions require address alignment 16 bytes SSE mode.
1776 // They should be called only from corresponding MacroAssembler instructions.
1777 void andpd(XMMRegister dst, Address src);
1778 void andps(XMMRegister dst, Address src);
1779 void xorpd(XMMRegister dst, Address src);
1780 void xorps(XMMRegister dst, Address src);
1782 };
1785 // MacroAssembler extends Assembler by frequently used macros.
1786 //
1787 // Instructions for which a 'better' code sequence exists depending
1788 // on arguments should also go in here.
1790 class MacroAssembler: public Assembler {
1791 friend class LIR_Assembler;
1792 friend class Runtime1; // as_Address()
1794 protected:
1796 Address as_Address(AddressLiteral adr);
1797 Address as_Address(ArrayAddress adr);
1799 // Support for VM calls
1800 //
1801 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1802 // may customize this version by overriding it for its purposes (e.g., to save/restore
1803 // additional registers when doing a VM call).
1804 #ifdef CC_INTERP
1805 // c++ interpreter never wants to use interp_masm version of call_VM
1806 #define VIRTUAL
1807 #else
1808 #define VIRTUAL virtual
1809 #endif
1811 VIRTUAL void call_VM_leaf_base(
1812 address entry_point, // the entry point
1813 int number_of_arguments // the number of arguments to pop after the call
1814 );
1816 // This is the base routine called by the different versions of call_VM. The interpreter
1817 // may customize this version by overriding it for its purposes (e.g., to save/restore
1818 // additional registers when doing a VM call).
1819 //
1820 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1821 // returns the register which contains the thread upon return. If a thread register has been
1822 // specified, the return value will correspond to that register. If no last_java_sp is specified
1823 // (noreg) than rsp will be used instead.
1824 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1825 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1826 Register java_thread, // the thread if computed before ; use noreg otherwise
1827 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1828 address entry_point, // the entry point
1829 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1830 bool check_exceptions // whether to check for pending exceptions after return
1831 );
1833 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1834 // The implementation is only non-empty for the InterpreterMacroAssembler,
1835 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1836 virtual void check_and_handle_popframe(Register java_thread);
1837 virtual void check_and_handle_earlyret(Register java_thread);
1839 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1841 // helpers for FPU flag access
1842 // tmp is a temporary register, if none is available use noreg
1843 void save_rax (Register tmp);
1844 void restore_rax(Register tmp);
1846 public:
1847 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1849 // Support for NULL-checks
1850 //
1851 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1852 // If the accessed location is M[reg + offset] and the offset is known, provide the
1853 // offset. No explicit code generation is needed if the offset is within a certain
1854 // range (0 <= offset <= page_size).
1856 void null_check(Register reg, int offset = -1);
1857 static bool needs_explicit_null_check(intptr_t offset);
1859 // Required platform-specific helpers for Label::patch_instructions.
1860 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1861 void pd_patch_instruction(address branch, address target);
1862 #ifndef PRODUCT
1863 static void pd_print_patched_instruction(address branch);
1864 #endif
1866 // The following 4 methods return the offset of the appropriate move instruction
1868 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1869 int load_unsigned_byte(Register dst, Address src);
1870 int load_unsigned_short(Register dst, Address src);
1872 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1873 int load_signed_byte(Register dst, Address src);
1874 int load_signed_short(Register dst, Address src);
1876 // Support for sign-extension (hi:lo = extend_sign(lo))
1877 void extend_sign(Register hi, Register lo);
1879 // Load and store values by size and signed-ness
1880 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1881 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1883 // Support for inc/dec with optimal instruction selection depending on value
1885 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1886 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1888 void decrementl(Address dst, int value = 1);
1889 void decrementl(Register reg, int value = 1);
1891 void decrementq(Register reg, int value = 1);
1892 void decrementq(Address dst, int value = 1);
1894 void incrementl(Address dst, int value = 1);
1895 void incrementl(Register reg, int value = 1);
1897 void incrementq(Register reg, int value = 1);
1898 void incrementq(Address dst, int value = 1);
1901 // Support optimal SSE move instructions.
1902 void movflt(XMMRegister dst, XMMRegister src) {
1903 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1904 else { movss (dst, src); return; }
1905 }
1906 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1907 void movflt(XMMRegister dst, AddressLiteral src);
1908 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1910 void movdbl(XMMRegister dst, XMMRegister src) {
1911 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1912 else { movsd (dst, src); return; }
1913 }
1915 void movdbl(XMMRegister dst, AddressLiteral src);
1917 void movdbl(XMMRegister dst, Address src) {
1918 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1919 else { movlpd(dst, src); return; }
1920 }
1921 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1923 void incrementl(AddressLiteral dst);
1924 void incrementl(ArrayAddress dst);
1926 // Alignment
1927 void align(int modulus);
1929 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1930 void fat_nop();
1932 // Stack frame creation/removal
1933 void enter();
1934 void leave();
1936 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1937 // The pointer will be loaded into the thread register.
1938 void get_thread(Register thread);
1941 // Support for VM calls
1942 //
1943 // It is imperative that all calls into the VM are handled via the call_VM macros.
1944 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1945 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1948 void call_VM(Register oop_result,
1949 address entry_point,
1950 bool check_exceptions = true);
1951 void call_VM(Register oop_result,
1952 address entry_point,
1953 Register arg_1,
1954 bool check_exceptions = true);
1955 void call_VM(Register oop_result,
1956 address entry_point,
1957 Register arg_1, Register arg_2,
1958 bool check_exceptions = true);
1959 void call_VM(Register oop_result,
1960 address entry_point,
1961 Register arg_1, Register arg_2, Register arg_3,
1962 bool check_exceptions = true);
1964 // Overloadings with last_Java_sp
1965 void call_VM(Register oop_result,
1966 Register last_java_sp,
1967 address entry_point,
1968 int number_of_arguments = 0,
1969 bool check_exceptions = true);
1970 void call_VM(Register oop_result,
1971 Register last_java_sp,
1972 address entry_point,
1973 Register arg_1, bool
1974 check_exceptions = true);
1975 void call_VM(Register oop_result,
1976 Register last_java_sp,
1977 address entry_point,
1978 Register arg_1, Register arg_2,
1979 bool check_exceptions = true);
1980 void call_VM(Register oop_result,
1981 Register last_java_sp,
1982 address entry_point,
1983 Register arg_1, Register arg_2, Register arg_3,
1984 bool check_exceptions = true);
1986 void get_vm_result (Register oop_result, Register thread);
1987 void get_vm_result_2(Register metadata_result, Register thread);
1989 // These always tightly bind to MacroAssembler::call_VM_base
1990 // bypassing the virtual implementation
1991 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1992 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1993 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1994 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1995 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1997 void call_VM_leaf(address entry_point,
1998 int number_of_arguments = 0);
1999 void call_VM_leaf(address entry_point,
2000 Register arg_1);
2001 void call_VM_leaf(address entry_point,
2002 Register arg_1, Register arg_2);
2003 void call_VM_leaf(address entry_point,
2004 Register arg_1, Register arg_2, Register arg_3);
2006 // These always tightly bind to MacroAssembler::call_VM_leaf_base
2007 // bypassing the virtual implementation
2008 void super_call_VM_leaf(address entry_point);
2009 void super_call_VM_leaf(address entry_point, Register arg_1);
2010 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
2011 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
2012 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
2014 // last Java Frame (fills frame anchor)
2015 void set_last_Java_frame(Register thread,
2016 Register last_java_sp,
2017 Register last_java_fp,
2018 address last_java_pc);
2020 // thread in the default location (r15_thread on 64bit)
2021 void set_last_Java_frame(Register last_java_sp,
2022 Register last_java_fp,
2023 address last_java_pc);
2025 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
2027 // thread in the default location (r15_thread on 64bit)
2028 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
2030 // Stores
2031 void store_check(Register obj); // store check for obj - register is destroyed afterwards
2032 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
2034 #ifndef SERIALGC
2036 void g1_write_barrier_pre(Register obj,
2037 Register pre_val,
2038 Register thread,
2039 Register tmp,
2040 bool tosca_live,
2041 bool expand_call);
2043 void g1_write_barrier_post(Register store_addr,
2044 Register new_val,
2045 Register thread,
2046 Register tmp,
2047 Register tmp2);
2049 #endif // SERIALGC
2051 // split store_check(Register obj) to enhance instruction interleaving
2052 void store_check_part_1(Register obj);
2053 void store_check_part_2(Register obj);
2055 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
2056 void c2bool(Register x);
2058 // C++ bool manipulation
2060 void movbool(Register dst, Address src);
2061 void movbool(Address dst, bool boolconst);
2062 void movbool(Address dst, Register src);
2063 void testbool(Register dst);
2065 // oop manipulations
2066 void load_klass(Register dst, Register src);
2067 void store_klass(Register dst, Register src);
2069 void load_heap_oop(Register dst, Address src);
2070 void load_heap_oop_not_null(Register dst, Address src);
2071 void store_heap_oop(Address dst, Register src);
2072 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
2074 // Used for storing NULL. All other oop constants should be
2075 // stored using routines that take a jobject.
2076 void store_heap_oop_null(Address dst);
2078 void load_prototype_header(Register dst, Register src);
2080 #ifdef _LP64
2081 void store_klass_gap(Register dst, Register src);
2083 // This dummy is to prevent a call to store_heap_oop from
2084 // converting a zero (like NULL) into a Register by giving
2085 // the compiler two choices it can't resolve
2087 void store_heap_oop(Address dst, void* dummy);
2089 void encode_heap_oop(Register r);
2090 void decode_heap_oop(Register r);
2091 void encode_heap_oop_not_null(Register r);
2092 void decode_heap_oop_not_null(Register r);
2093 void encode_heap_oop_not_null(Register dst, Register src);
2094 void decode_heap_oop_not_null(Register dst, Register src);
2096 void set_narrow_oop(Register dst, jobject obj);
2097 void set_narrow_oop(Address dst, jobject obj);
2098 void cmp_narrow_oop(Register dst, jobject obj);
2099 void cmp_narrow_oop(Address dst, jobject obj);
2101 void encode_klass_not_null(Register r);
2102 void decode_klass_not_null(Register r);
2103 void encode_klass_not_null(Register dst, Register src);
2104 void decode_klass_not_null(Register dst, Register src);
2105 void set_narrow_klass(Register dst, Klass* k);
2106 void set_narrow_klass(Address dst, Klass* k);
2107 void cmp_narrow_klass(Register dst, Klass* k);
2108 void cmp_narrow_klass(Address dst, Klass* k);
2110 // if heap base register is used - reinit it with the correct value
2111 void reinit_heapbase();
2113 DEBUG_ONLY(void verify_heapbase(const char* msg);)
2115 #endif // _LP64
2117 // Int division/remainder for Java
2118 // (as idivl, but checks for special case as described in JVM spec.)
2119 // returns idivl instruction offset for implicit exception handling
2120 int corrected_idivl(Register reg);
2122 // Long division/remainder for Java
2123 // (as idivq, but checks for special case as described in JVM spec.)
2124 // returns idivq instruction offset for implicit exception handling
2125 int corrected_idivq(Register reg);
2127 void int3();
2129 // Long operation macros for a 32bit cpu
2130 // Long negation for Java
2131 void lneg(Register hi, Register lo);
2133 // Long multiplication for Java
2134 // (destroys contents of eax, ebx, ecx and edx)
2135 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
2137 // Long shifts for Java
2138 // (semantics as described in JVM spec.)
2139 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
2140 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
2142 // Long compare for Java
2143 // (semantics as described in JVM spec.)
2144 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
2147 // misc
2149 // Sign extension
2150 void sign_extend_short(Register reg);
2151 void sign_extend_byte(Register reg);
2153 // Division by power of 2, rounding towards 0
2154 void division_with_shift(Register reg, int shift_value);
2156 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
2157 //
2158 // CF (corresponds to C0) if x < y
2159 // PF (corresponds to C2) if unordered
2160 // ZF (corresponds to C3) if x = y
2161 //
2162 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2163 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
2164 void fcmp(Register tmp);
2165 // Variant of the above which allows y to be further down the stack
2166 // and which only pops x and y if specified. If pop_right is
2167 // specified then pop_left must also be specified.
2168 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
2170 // Floating-point comparison for Java
2171 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
2172 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2173 // (semantics as described in JVM spec.)
2174 void fcmp2int(Register dst, bool unordered_is_less);
2175 // Variant of the above which allows y to be further down the stack
2176 // and which only pops x and y if specified. If pop_right is
2177 // specified then pop_left must also be specified.
2178 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
2180 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
2181 // tmp is a temporary register, if none is available use noreg
2182 void fremr(Register tmp);
2185 // same as fcmp2int, but using SSE2
2186 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2187 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2189 // Inlined sin/cos generator for Java; must not use CPU instruction
2190 // directly on Intel as it does not have high enough precision
2191 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
2192 // number of FPU stack slots in use; all but the topmost will
2193 // require saving if a slow case is necessary. Assumes argument is
2194 // on FP TOS; result is on FP TOS. No cpu registers are changed by
2195 // this code.
2196 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
2198 // branch to L if FPU flag C2 is set/not set
2199 // tmp is a temporary register, if none is available use noreg
2200 void jC2 (Register tmp, Label& L);
2201 void jnC2(Register tmp, Label& L);
2203 // Pop ST (ffree & fincstp combined)
2204 void fpop();
2206 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2207 void push_fTOS();
2209 // pops double TOS element from CPU stack and pushes on FPU stack
2210 void pop_fTOS();
2212 void empty_FPU_stack();
2214 void push_IU_state();
2215 void pop_IU_state();
2217 void push_FPU_state();
2218 void pop_FPU_state();
2220 void push_CPU_state();
2221 void pop_CPU_state();
2223 // Round up to a power of two
2224 void round_to(Register reg, int modulus);
2226 // Callee saved registers handling
2227 void push_callee_saved_registers();
2228 void pop_callee_saved_registers();
2230 // allocation
2231 void eden_allocate(
2232 Register obj, // result: pointer to object after successful allocation
2233 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2234 int con_size_in_bytes, // object size in bytes if known at compile time
2235 Register t1, // temp register
2236 Label& slow_case // continuation point if fast allocation fails
2237 );
2238 void tlab_allocate(
2239 Register obj, // result: pointer to object after successful allocation
2240 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2241 int con_size_in_bytes, // object size in bytes if known at compile time
2242 Register t1, // temp register
2243 Register t2, // temp register
2244 Label& slow_case // continuation point if fast allocation fails
2245 );
2246 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
2247 void incr_allocated_bytes(Register thread,
2248 Register var_size_in_bytes, int con_size_in_bytes,
2249 Register t1 = noreg);
2251 // interface method calling
2252 void lookup_interface_method(Register recv_klass,
2253 Register intf_klass,
2254 RegisterOrConstant itable_index,
2255 Register method_result,
2256 Register scan_temp,
2257 Label& no_such_interface);
2259 // virtual method calling
2260 void lookup_virtual_method(Register recv_klass,
2261 RegisterOrConstant vtable_index,
2262 Register method_result);
2264 // Test sub_klass against super_klass, with fast and slow paths.
2266 // The fast path produces a tri-state answer: yes / no / maybe-slow.
2267 // One of the three labels can be NULL, meaning take the fall-through.
2268 // If super_check_offset is -1, the value is loaded up from super_klass.
2269 // No registers are killed, except temp_reg.
2270 void check_klass_subtype_fast_path(Register sub_klass,
2271 Register super_klass,
2272 Register temp_reg,
2273 Label* L_success,
2274 Label* L_failure,
2275 Label* L_slow_path,
2276 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2278 // The rest of the type check; must be wired to a corresponding fast path.
2279 // It does not repeat the fast path logic, so don't use it standalone.
2280 // The temp_reg and temp2_reg can be noreg, if no temps are available.
2281 // Updates the sub's secondary super cache as necessary.
2282 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
2283 void check_klass_subtype_slow_path(Register sub_klass,
2284 Register super_klass,
2285 Register temp_reg,
2286 Register temp2_reg,
2287 Label* L_success,
2288 Label* L_failure,
2289 bool set_cond_codes = false);
2291 // Simplified, combined version, good for typical uses.
2292 // Falls through on failure.
2293 void check_klass_subtype(Register sub_klass,
2294 Register super_klass,
2295 Register temp_reg,
2296 Label& L_success);
2298 // method handles (JSR 292)
2299 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
2301 //----
2302 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
2304 // Debugging
2306 // only if +VerifyOops
2307 // TODO: Make these macros with file and line like sparc version!
2308 void verify_oop(Register reg, const char* s = "broken oop");
2309 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
2311 // TODO: verify method and klass metadata (compare against vptr?)
2312 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
2313 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
2315 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
2316 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
2318 // only if +VerifyFPU
2319 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2321 // prints msg, dumps registers and stops execution
2322 void stop(const char* msg);
2324 // prints msg and continues
2325 void warn(const char* msg);
2327 // dumps registers and other state
2328 void print_state();
2330 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
2331 static void debug64(char* msg, int64_t pc, int64_t regs[]);
2332 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
2333 static void print_state64(int64_t pc, int64_t regs[]);
2335 void os_breakpoint();
2337 void untested() { stop("untested"); }
2339 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
2341 void should_not_reach_here() { stop("should not reach here"); }
2343 void print_CPU_state();
2345 // Stack overflow checking
2346 void bang_stack_with_offset(int offset) {
2347 // stack grows down, caller passes positive offset
2348 assert(offset > 0, "must bang with negative offset");
2349 movl(Address(rsp, (-offset)), rax);
2350 }
2352 // Writes to stack successive pages until offset reached to check for
2353 // stack overflow + shadow pages. Also, clobbers tmp
2354 void bang_stack_size(Register size, Register tmp);
2356 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2357 Register tmp,
2358 int offset);
2360 // Support for serializing memory accesses between threads
2361 void serialize_memory(Register thread, Register tmp);
2363 void verify_tlab();
2365 // Biased locking support
2366 // lock_reg and obj_reg must be loaded up with the appropriate values.
2367 // swap_reg must be rax, and is killed.
2368 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2369 // be killed; if not supplied, push/pop will be used internally to
2370 // allocate a temporary (inefficient, avoid if possible).
2371 // Optional slow case is for implementations (interpreter and C1) which branch to
2372 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2373 // Returns offset of first potentially-faulting instruction for null
2374 // check info (currently consumed only by C1). If
2375 // swap_reg_contains_mark is true then returns -1 as it is assumed
2376 // the calling code has already passed any potential faults.
2377 int biased_locking_enter(Register lock_reg, Register obj_reg,
2378 Register swap_reg, Register tmp_reg,
2379 bool swap_reg_contains_mark,
2380 Label& done, Label* slow_case = NULL,
2381 BiasedLockingCounters* counters = NULL);
2382 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2385 Condition negate_condition(Condition cond);
2387 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2388 // operands. In general the names are modified to avoid hiding the instruction in Assembler
2389 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2390 // here in MacroAssembler. The major exception to this rule is call
2392 // Arithmetics
2395 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2396 void addptr(Address dst, Register src);
2398 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2399 void addptr(Register dst, int32_t src);
2400 void addptr(Register dst, Register src);
2401 void addptr(Register dst, RegisterOrConstant src) {
2402 if (src.is_constant()) addptr(dst, (int) src.as_constant());
2403 else addptr(dst, src.as_register());
2404 }
2406 void andptr(Register dst, int32_t src);
2407 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2409 void cmp8(AddressLiteral src1, int imm);
2411 // renamed to drag out the casting of address to int32_t/intptr_t
2412 void cmp32(Register src1, int32_t imm);
2414 void cmp32(AddressLiteral src1, int32_t imm);
2415 // compare reg - mem, or reg - &mem
2416 void cmp32(Register src1, AddressLiteral src2);
2418 void cmp32(Register src1, Address src2);
2420 #ifndef _LP64
2421 void cmpklass(Address dst, Metadata* obj);
2422 void cmpklass(Register dst, Metadata* obj);
2423 void cmpoop(Address dst, jobject obj);
2424 void cmpoop(Register dst, jobject obj);
2425 #endif // _LP64
2427 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2428 void cmpptr(Address src1, AddressLiteral src2);
2430 void cmpptr(Register src1, AddressLiteral src2);
2432 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2433 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2434 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2436 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2437 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2439 // cmp64 to avoild hiding cmpq
2440 void cmp64(Register src1, AddressLiteral src);
2442 void cmpxchgptr(Register reg, Address adr);
2444 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2447 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2450 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2452 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2454 void shlptr(Register dst, int32_t shift);
2455 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2457 void shrptr(Register dst, int32_t shift);
2458 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2460 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2461 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2463 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2465 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2466 void subptr(Register dst, int32_t src);
2467 // Force generation of a 4 byte immediate value even if it fits into 8bit
2468 void subptr_imm32(Register dst, int32_t src);
2469 void subptr(Register dst, Register src);
2470 void subptr(Register dst, RegisterOrConstant src) {
2471 if (src.is_constant()) subptr(dst, (int) src.as_constant());
2472 else subptr(dst, src.as_register());
2473 }
2475 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2476 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2478 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2479 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2481 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2485 // Helper functions for statistics gathering.
2486 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2487 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2488 // Unconditional atomic increment.
2489 void atomic_incl(AddressLiteral counter_addr);
2491 void lea(Register dst, AddressLiteral adr);
2492 void lea(Address dst, AddressLiteral adr);
2493 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2495 void leal32(Register dst, Address src) { leal(dst, src); }
2497 // Import other testl() methods from the parent class or else
2498 // they will be hidden by the following overriding declaration.
2499 using Assembler::testl;
2500 void testl(Register dst, AddressLiteral src);
2502 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2503 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2504 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2506 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2507 void testptr(Register src1, Register src2);
2509 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2510 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2512 // Calls
2514 void call(Label& L, relocInfo::relocType rtype);
2515 void call(Register entry);
2517 // NOTE: this call tranfers to the effective address of entry NOT
2518 // the address contained by entry. This is because this is more natural
2519 // for jumps/calls.
2520 void call(AddressLiteral entry);
2522 // Emit the CompiledIC call idiom
2523 void ic_call(address entry);
2525 // Jumps
2527 // NOTE: these jumps tranfer to the effective address of dst NOT
2528 // the address contained by dst. This is because this is more natural
2529 // for jumps/calls.
2530 void jump(AddressLiteral dst);
2531 void jump_cc(Condition cc, AddressLiteral dst);
2533 // 32bit can do a case table jump in one instruction but we no longer allow the base
2534 // to be installed in the Address class. This jump will tranfers to the address
2535 // contained in the location described by entry (not the address of entry)
2536 void jump(ArrayAddress entry);
2538 // Floating
2540 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2541 void andpd(XMMRegister dst, AddressLiteral src);
2543 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
2544 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
2545 void andps(XMMRegister dst, AddressLiteral src);
2547 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
2548 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2549 void comiss(XMMRegister dst, AddressLiteral src);
2551 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
2552 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2553 void comisd(XMMRegister dst, AddressLiteral src);
2555 void fadd_s(Address src) { Assembler::fadd_s(src); }
2556 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2558 void fldcw(Address src) { Assembler::fldcw(src); }
2559 void fldcw(AddressLiteral src);
2561 void fld_s(int index) { Assembler::fld_s(index); }
2562 void fld_s(Address src) { Assembler::fld_s(src); }
2563 void fld_s(AddressLiteral src);
2565 void fld_d(Address src) { Assembler::fld_d(src); }
2566 void fld_d(AddressLiteral src);
2568 void fld_x(Address src) { Assembler::fld_x(src); }
2569 void fld_x(AddressLiteral src);
2571 void fmul_s(Address src) { Assembler::fmul_s(src); }
2572 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2574 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2575 void ldmxcsr(AddressLiteral src);
2577 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
2578 // all corner cases and may result in NaN and require fallback to a
2579 // runtime call.
2580 void fast_pow();
2581 void fast_exp();
2582 void increase_precision();
2583 void restore_precision();
2585 // computes exp(x). Fallback to runtime call included.
2586 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
2587 // computes pow(x,y). Fallback to runtime call included.
2588 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
2590 private:
2592 // call runtime as a fallback for trig functions and pow/exp.
2593 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
2595 // computes 2^(Ylog2X); Ylog2X in ST(0)
2596 void pow_exp_core_encoding();
2598 // computes pow(x,y) or exp(x). Fallback to runtime call included.
2599 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
2601 // these are private because users should be doing movflt/movdbl
2603 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2604 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2605 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2606 void movss(XMMRegister dst, AddressLiteral src);
2608 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2609 void movlpd(XMMRegister dst, AddressLiteral src);
2611 public:
2613 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2614 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2615 void addsd(XMMRegister dst, AddressLiteral src);
2617 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2618 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2619 void addss(XMMRegister dst, AddressLiteral src);
2621 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2622 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2623 void divsd(XMMRegister dst, AddressLiteral src);
2625 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2626 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2627 void divss(XMMRegister dst, AddressLiteral src);
2629 // Move Unaligned Double Quadword
2630 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); }
2631 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); }
2632 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); }
2633 void movdqu(XMMRegister dst, AddressLiteral src);
2635 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2636 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2637 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2638 void movsd(XMMRegister dst, AddressLiteral src);
2640 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2641 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2642 void mulsd(XMMRegister dst, AddressLiteral src);
2644 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2645 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2646 void mulss(XMMRegister dst, AddressLiteral src);
2648 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2649 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2650 void sqrtsd(XMMRegister dst, AddressLiteral src);
2652 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2653 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2654 void sqrtss(XMMRegister dst, AddressLiteral src);
2656 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2657 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2658 void subsd(XMMRegister dst, AddressLiteral src);
2660 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2661 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2662 void subss(XMMRegister dst, AddressLiteral src);
2664 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2665 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2666 void ucomiss(XMMRegister dst, AddressLiteral src);
2668 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2669 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2670 void ucomisd(XMMRegister dst, AddressLiteral src);
2672 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2673 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2674 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2675 void xorpd(XMMRegister dst, AddressLiteral src);
2677 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2678 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2679 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2680 void xorps(XMMRegister dst, AddressLiteral src);
2682 // Shuffle Bytes
2683 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
2684 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
2685 void pshufb(XMMRegister dst, AddressLiteral src);
2686 // AVX 3-operands instructions
2688 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
2689 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
2690 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2692 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
2693 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
2694 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2696 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2697 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2698 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2700 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2701 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2702 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2704 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
2705 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
2706 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2708 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
2709 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
2710 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2712 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
2713 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
2714 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2716 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
2717 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
2718 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2720 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
2721 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
2722 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2724 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
2725 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
2726 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2728 // AVX Vector instructions
2730 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2731 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2732 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2734 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2735 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2736 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2738 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2739 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2740 Assembler::vpxor(dst, nds, src, vector256);
2741 else
2742 Assembler::vxorpd(dst, nds, src, vector256);
2743 }
2744 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2745 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2746 Assembler::vpxor(dst, nds, src, vector256);
2747 else
2748 Assembler::vxorpd(dst, nds, src, vector256);
2749 }
2751 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
2752 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2753 if (UseAVX > 1) // vinserti128h is available only in AVX2
2754 Assembler::vinserti128h(dst, nds, src);
2755 else
2756 Assembler::vinsertf128h(dst, nds, src);
2757 }
2759 // Data
2761 void cmov32( Condition cc, Register dst, Address src);
2762 void cmov32( Condition cc, Register dst, Register src);
2764 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2766 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2767 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2769 void movoop(Register dst, jobject obj);
2770 void movoop(Address dst, jobject obj);
2772 void mov_metadata(Register dst, Metadata* obj);
2773 void mov_metadata(Address dst, Metadata* obj);
2775 void movptr(ArrayAddress dst, Register src);
2776 // can this do an lea?
2777 void movptr(Register dst, ArrayAddress src);
2779 void movptr(Register dst, Address src);
2781 void movptr(Register dst, AddressLiteral src);
2783 void movptr(Register dst, intptr_t src);
2784 void movptr(Register dst, Register src);
2785 void movptr(Address dst, intptr_t src);
2787 void movptr(Address dst, Register src);
2789 void movptr(Register dst, RegisterOrConstant src) {
2790 if (src.is_constant()) movptr(dst, src.as_constant());
2791 else movptr(dst, src.as_register());
2792 }
2794 #ifdef _LP64
2795 // Generally the next two are only used for moving NULL
2796 // Although there are situations in initializing the mark word where
2797 // they could be used. They are dangerous.
2799 // They only exist on LP64 so that int32_t and intptr_t are not the same
2800 // and we have ambiguous declarations.
2802 void movptr(Address dst, int32_t imm32);
2803 void movptr(Register dst, int32_t imm32);
2804 #endif // _LP64
2806 // to avoid hiding movl
2807 void mov32(AddressLiteral dst, Register src);
2808 void mov32(Register dst, AddressLiteral src);
2810 // to avoid hiding movb
2811 void movbyte(ArrayAddress dst, int src);
2813 // Import other mov() methods from the parent class or else
2814 // they will be hidden by the following overriding declaration.
2815 using Assembler::movdl;
2816 using Assembler::movq;
2817 void movdl(XMMRegister dst, AddressLiteral src);
2818 void movq(XMMRegister dst, AddressLiteral src);
2820 // Can push value or effective address
2821 void pushptr(AddressLiteral src);
2823 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2824 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2826 void pushoop(jobject obj);
2827 void pushklass(Metadata* obj);
2829 // sign extend as need a l to ptr sized element
2830 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2831 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2833 // C2 compiled method's prolog code.
2834 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
2836 // IndexOf strings.
2837 // Small strings are loaded through stack if they cross page boundary.
2838 void string_indexof(Register str1, Register str2,
2839 Register cnt1, Register cnt2,
2840 int int_cnt2, Register result,
2841 XMMRegister vec, Register tmp);
2843 // IndexOf for constant substrings with size >= 8 elements
2844 // which don't need to be loaded through stack.
2845 void string_indexofC8(Register str1, Register str2,
2846 Register cnt1, Register cnt2,
2847 int int_cnt2, Register result,
2848 XMMRegister vec, Register tmp);
2850 // Smallest code: we don't need to load through stack,
2851 // check string tail.
2853 // Compare strings.
2854 void string_compare(Register str1, Register str2,
2855 Register cnt1, Register cnt2, Register result,
2856 XMMRegister vec1);
2858 // Compare char[] arrays.
2859 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2860 Register limit, Register result, Register chr,
2861 XMMRegister vec1, XMMRegister vec2);
2863 // Fill primitive arrays
2864 void generate_fill(BasicType t, bool aligned,
2865 Register to, Register value, Register count,
2866 Register rtmp, XMMRegister xtmp);
2868 #undef VIRTUAL
2870 };
2872 /**
2873 * class SkipIfEqual:
2874 *
2875 * Instantiating this class will result in assembly code being output that will
2876 * jump around any code emitted between the creation of the instance and it's
2877 * automatic destruction at the end of a scope block, depending on the value of
2878 * the flag passed to the constructor, which will be checked at run-time.
2879 */
2880 class SkipIfEqual {
2881 private:
2882 MacroAssembler* _masm;
2883 Label _label;
2885 public:
2886 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2887 ~SkipIfEqual();
2888 };
2890 #ifdef ASSERT
2891 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2892 #endif
2894 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP
