Thu, 21 Aug 2008 23:36:31 -0400
Merge
1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 class BiasedLockingCounters;
27 // Contains all the definitions needed for x86 assembly code generation.
29 // Calling convention
30 class Argument VALUE_OBJ_CLASS_SPEC {
31 public:
32 enum {
33 #ifdef _LP64
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 #else
44 n_register_parameters = 0 // 0 registers used to pass arguments
45 #endif // _LP64
46 };
47 };
50 #ifdef _LP64
51 // Symbolically name the register arguments used by the c calling convention.
52 // Windows is different from linux/solaris. So much for standards...
54 #ifdef _WIN64
56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
58 REGISTER_DECLARATION(Register, c_rarg2, r8);
59 REGISTER_DECLARATION(Register, c_rarg3, r9);
61 REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
62 REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
63 REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
64 REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
66 #else
68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
72 REGISTER_DECLARATION(Register, c_rarg4, r8);
73 REGISTER_DECLARATION(Register, c_rarg5, r9);
75 REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
76 REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
77 REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
78 REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
79 REGISTER_DECLARATION(FloatRegister, c_farg4, xmm4);
80 REGISTER_DECLARATION(FloatRegister, c_farg5, xmm5);
81 REGISTER_DECLARATION(FloatRegister, c_farg6, xmm6);
82 REGISTER_DECLARATION(FloatRegister, c_farg7, xmm7);
84 #endif // _WIN64
86 // Symbolically name the register arguments used by the Java calling convention.
87 // We have control over the convention for java so we can do what we please.
88 // What pleases us is to offset the java calling convention so that when
89 // we call a suitable jni method the arguments are lined up and we don't
90 // have to do little shuffling. A suitable jni method is non-static and a
91 // small number of arguments (two fewer args on windows)
92 //
93 // |-------------------------------------------------------|
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
95 // |-------------------------------------------------------|
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
98 // |-------------------------------------------------------|
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
100 // |-------------------------------------------------------|
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
105 // Windows runs out of register args here
106 #ifdef _WIN64
107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
109 #else
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
112 #endif /* _WIN64 */
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
115 REGISTER_DECLARATION(FloatRegister, j_farg0, xmm0);
116 REGISTER_DECLARATION(FloatRegister, j_farg1, xmm1);
117 REGISTER_DECLARATION(FloatRegister, j_farg2, xmm2);
118 REGISTER_DECLARATION(FloatRegister, j_farg3, xmm3);
119 REGISTER_DECLARATION(FloatRegister, j_farg4, xmm4);
120 REGISTER_DECLARATION(FloatRegister, j_farg5, xmm5);
121 REGISTER_DECLARATION(FloatRegister, j_farg6, xmm6);
122 REGISTER_DECLARATION(FloatRegister, j_farg7, xmm7);
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
127 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
129 #endif // _LP64
131 // Address is an abstraction used to represent a memory location
132 // using any of the amd64 addressing modes with one object.
133 //
134 // Note: A register location is represented via a Register, not
135 // via an address for efficiency & simplicity reasons.
137 class ArrayAddress;
139 class Address VALUE_OBJ_CLASS_SPEC {
140 public:
141 enum ScaleFactor {
142 no_scale = -1,
143 times_1 = 0,
144 times_2 = 1,
145 times_4 = 2,
146 times_8 = 3
147 };
149 private:
150 Register _base;
151 Register _index;
152 ScaleFactor _scale;
153 int _disp;
154 RelocationHolder _rspec;
156 // Easily misused constructor make them private
157 #ifndef _LP64
158 Address(address loc, RelocationHolder spec);
159 #endif // _LP64
161 public:
162 // creation
163 Address()
164 : _base(noreg),
165 _index(noreg),
166 _scale(no_scale),
167 _disp(0) {
168 }
170 // No default displacement otherwise Register can be implicitly
171 // converted to 0(Register) which is quite a different animal.
173 Address(Register base, int disp)
174 : _base(base),
175 _index(noreg),
176 _scale(no_scale),
177 _disp(disp) {
178 }
180 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
181 : _base (base),
182 _index(index),
183 _scale(scale),
184 _disp (disp) {
185 assert(!index->is_valid() == (scale == Address::no_scale),
186 "inconsistent address");
187 }
189 // The following two overloads are used in connection with the
190 // ByteSize type (see sizes.hpp). They simplify the use of
191 // ByteSize'd arguments in assembly code. Note that their equivalent
192 // for the optimized build are the member functions with int disp
193 // argument since ByteSize is mapped to an int type in that case.
194 //
195 // Note: DO NOT introduce similar overloaded functions for WordSize
196 // arguments as in the optimized mode, both ByteSize and WordSize
197 // are mapped to the same type and thus the compiler cannot make a
198 // distinction anymore (=> compiler errors).
200 #ifdef ASSERT
201 Address(Register base, ByteSize disp)
202 : _base(base),
203 _index(noreg),
204 _scale(no_scale),
205 _disp(in_bytes(disp)) {
206 }
208 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
209 : _base(base),
210 _index(index),
211 _scale(scale),
212 _disp(in_bytes(disp)) {
213 assert(!index->is_valid() == (scale == Address::no_scale),
214 "inconsistent address");
215 }
216 #endif // ASSERT
218 // accessors
219 bool uses(Register reg) const { return _base == reg || _index == reg; }
220 Register base() const { return _base; }
221 Register index() const { return _index; }
222 ScaleFactor scale() const { return _scale; }
223 int disp() const { return _disp; }
225 // Convert the raw encoding form into the form expected by the constructor for
226 // Address. An index of 4 (rsp) corresponds to having no index, so convert
227 // that to noreg for the Address constructor.
228 static Address make_raw(int base, int index, int scale, int disp);
230 static Address make_array(ArrayAddress);
233 private:
234 bool base_needs_rex() const {
235 return _base != noreg && _base->encoding() >= 8;
236 }
238 bool index_needs_rex() const {
239 return _index != noreg &&_index->encoding() >= 8;
240 }
242 relocInfo::relocType reloc() const { return _rspec.type(); }
244 friend class Assembler;
245 friend class MacroAssembler;
246 friend class LIR_Assembler; // base/index/scale/disp
247 };
249 //
250 // AddressLiteral has been split out from Address because operands of this type
251 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
252 // the few instructions that need to deal with address literals are unique and the
253 // MacroAssembler does not have to implement every instruction in the Assembler
254 // in order to search for address literals that may need special handling depending
255 // on the instruction and the platform. As small step on the way to merging i486/amd64
256 // directories.
257 //
258 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
259 friend class ArrayAddress;
260 RelocationHolder _rspec;
261 // Typically we use AddressLiterals we want to use their rval
262 // However in some situations we want the lval (effect address) of the item.
263 // We provide a special factory for making those lvals.
264 bool _is_lval;
266 // If the target is far we'll need to load the ea of this to
267 // a register to reach it. Otherwise if near we can do rip
268 // relative addressing.
270 address _target;
272 protected:
273 // creation
274 AddressLiteral()
275 : _is_lval(false),
276 _target(NULL)
277 {}
279 public:
282 AddressLiteral(address target, relocInfo::relocType rtype);
284 AddressLiteral(address target, RelocationHolder const& rspec)
285 : _rspec(rspec),
286 _is_lval(false),
287 _target(target)
288 {}
290 AddressLiteral addr() {
291 AddressLiteral ret = *this;
292 ret._is_lval = true;
293 return ret;
294 }
297 private:
299 address target() { return _target; }
300 bool is_lval() { return _is_lval; }
302 relocInfo::relocType reloc() const { return _rspec.type(); }
303 const RelocationHolder& rspec() const { return _rspec; }
305 friend class Assembler;
306 friend class MacroAssembler;
307 friend class Address;
308 friend class LIR_Assembler;
309 };
311 // Convience classes
312 class RuntimeAddress: public AddressLiteral {
314 public:
316 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
318 };
320 class OopAddress: public AddressLiteral {
322 public:
324 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
326 };
328 class ExternalAddress: public AddressLiteral {
330 public:
332 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
334 };
336 class InternalAddress: public AddressLiteral {
338 public:
340 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
342 };
344 // x86 can do array addressing as a single operation since disp can be an absolute
345 // address amd64 can't. We create a class that expresses the concept but does extra
346 // magic on amd64 to get the final result
348 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
349 private:
351 AddressLiteral _base;
352 Address _index;
354 public:
356 ArrayAddress() {};
357 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
358 AddressLiteral base() { return _base; }
359 Address index() { return _index; }
361 };
363 #ifndef _LP64
364 const int FPUStateSizeInWords = 27;
365 #else
366 const int FPUStateSizeInWords = 512 / wordSize;
367 #endif // _LP64
369 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
370 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
371 // is what you get. The Assembler is generating code into a CodeBuffer.
373 class Assembler : public AbstractAssembler {
374 friend class AbstractAssembler; // for the non-virtual hack
375 friend class LIR_Assembler; // as_Address()
377 protected:
378 #ifdef ASSERT
379 void check_relocation(RelocationHolder const& rspec, int format);
380 #endif
382 inline void emit_long64(jlong x);
384 void emit_data(jint data, relocInfo::relocType rtype, int format /* = 0 */);
385 void emit_data(jint data, RelocationHolder const& rspec, int format /* = 0 */);
386 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
387 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
389 // Helper functions for groups of instructions
390 void emit_arith_b(int op1, int op2, Register dst, int imm8);
392 void emit_arith(int op1, int op2, Register dst, int imm32);
393 // only x86??
394 void emit_arith(int op1, int op2, Register dst, jobject obj);
395 void emit_arith(int op1, int op2, Register dst, Register src);
397 void emit_operand(Register reg,
398 Register base, Register index, Address::ScaleFactor scale,
399 int disp,
400 RelocationHolder const& rspec);
401 void emit_operand(Register reg, Address adr);
403 // Immediate-to-memory forms
404 void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
406 void emit_farith(int b1, int b2, int i);
408 // macroassembler?? QQQ
409 bool reachable(AddressLiteral adr) { return true; }
411 // These are all easily abused and hence protected
413 // Make these disappear in 64bit mode since they would never be correct
414 #ifndef _LP64
415 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
416 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
418 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
419 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
421 void push_literal32(int32_t imm32, RelocationHolder const& rspec);
422 #endif // _LP64
424 // These are unique in that we are ensured by the caller that the 32bit
425 // relative in these instructions will always be able to reach the potentially
426 // 64bit address described by entry. Since they can take a 64bit address they
427 // don't have the 32 suffix like the other instructions in this class.
429 void call_literal(address entry, RelocationHolder const& rspec);
430 void jmp_literal(address entry, RelocationHolder const& rspec);
433 public:
434 enum Condition { // The x86 condition codes used for conditional jumps/moves.
435 zero = 0x4,
436 notZero = 0x5,
437 equal = 0x4,
438 notEqual = 0x5,
439 less = 0xc,
440 lessEqual = 0xe,
441 greater = 0xf,
442 greaterEqual = 0xd,
443 below = 0x2,
444 belowEqual = 0x6,
445 above = 0x7,
446 aboveEqual = 0x3,
447 overflow = 0x0,
448 noOverflow = 0x1,
449 carrySet = 0x2,
450 carryClear = 0x3,
451 negative = 0x8,
452 positive = 0x9,
453 parity = 0xa,
454 noParity = 0xb
455 };
457 enum Prefix {
458 // segment overrides
459 CS_segment = 0x2e,
460 SS_segment = 0x36,
461 DS_segment = 0x3e,
462 ES_segment = 0x26,
463 FS_segment = 0x64,
464 GS_segment = 0x65,
466 REX = 0x40,
468 REX_B = 0x41,
469 REX_X = 0x42,
470 REX_XB = 0x43,
471 REX_R = 0x44,
472 REX_RB = 0x45,
473 REX_RX = 0x46,
474 REX_RXB = 0x47,
476 REX_W = 0x48,
478 REX_WB = 0x49,
479 REX_WX = 0x4A,
480 REX_WXB = 0x4B,
481 REX_WR = 0x4C,
482 REX_WRB = 0x4D,
483 REX_WRX = 0x4E,
484 REX_WRXB = 0x4F
485 };
487 enum WhichOperand {
488 // input to locate_operand, and format code for relocations
489 imm32_operand = 0, // embedded 32-bit immediate operand
490 disp32_operand = 1, // embedded 32-bit displacement or address
491 call32_operand = 2, // embedded 32-bit self-relative displacement
492 _WhichOperand_limit = 3
493 };
495 public:
497 // Creation
498 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
500 // Decoding
501 static address locate_operand(address inst, WhichOperand which);
502 static address locate_next_instruction(address inst);
504 // Stack
505 void pushad();
506 void popad();
508 void pushfd();
509 void popfd();
511 void pushl(int imm32);
512 void pushoop(jobject obj);
514 void pushl(Register src);
515 void pushl(Address src);
516 // void pushl(Label& L, relocInfo::relocType rtype); ? needed?
518 // dummy to prevent NULL being converted to Register
519 void pushl(void* dummy);
521 void popl(Register dst);
522 void popl(Address dst);
524 // Instruction prefixes
525 void prefix(Prefix p);
527 // Moves
528 void movb(Register dst, Address src);
529 void movb(Address dst, int imm8);
530 void movb(Address dst, Register src);
532 void movw(Address dst, int imm16);
533 void movw(Register dst, Address src);
534 void movw(Address dst, Register src);
536 // these are dummies used to catch attempting to convert NULL to Register
537 void movl(Register dst, void* junk);
538 void movl(Address dst, void* junk);
540 void movl(Register dst, int imm32);
541 void movl(Address dst, int imm32);
542 void movl(Register dst, Register src);
543 void movl(Register dst, Address src);
544 void movl(Address dst, Register src);
546 void movsxb(Register dst, Address src);
547 void movsxb(Register dst, Register src);
549 void movsxw(Register dst, Address src);
550 void movsxw(Register dst, Register src);
552 void movzxb(Register dst, Address src);
553 void movzxb(Register dst, Register src);
555 void movzxw(Register dst, Address src);
556 void movzxw(Register dst, Register src);
558 // Conditional moves (P6 only)
559 void cmovl(Condition cc, Register dst, Register src);
560 void cmovl(Condition cc, Register dst, Address src);
562 // Prefetches (SSE, SSE2, 3DNOW only)
563 void prefetcht0(Address src);
564 void prefetcht1(Address src);
565 void prefetcht2(Address src);
566 void prefetchnta(Address src);
567 void prefetchw(Address src);
568 void prefetchr(Address src);
570 // Arithmetics
571 void adcl(Register dst, int imm32);
572 void adcl(Register dst, Address src);
573 void adcl(Register dst, Register src);
575 void addl(Address dst, int imm32);
576 void addl(Address dst, Register src);
577 void addl(Register dst, int imm32);
578 void addl(Register dst, Address src);
579 void addl(Register dst, Register src);
581 void andl(Register dst, int imm32);
582 void andl(Register dst, Address src);
583 void andl(Register dst, Register src);
585 void cmpb(Address dst, int imm8);
586 void cmpw(Address dst, int imm16);
587 void cmpl(Address dst, int imm32);
588 void cmpl(Register dst, int imm32);
589 void cmpl(Register dst, Register src);
590 void cmpl(Register dst, Address src);
592 // this is a dummy used to catch attempting to convert NULL to Register
593 void cmpl(Register dst, void* junk);
595 protected:
596 // Don't use next inc() and dec() methods directly. INC & DEC instructions
597 // could cause a partial flag stall since they don't set CF flag.
598 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
599 // which call inc() & dec() or add() & sub() in accordance with
600 // the product flag UseIncDec value.
602 void decl(Register dst);
603 void decl(Address dst);
605 void incl(Register dst);
606 void incl(Address dst);
608 public:
609 void idivl(Register src);
610 void cdql();
612 void imull(Register dst, Register src);
613 void imull(Register dst, Register src, int value);
615 void leal(Register dst, Address src);
617 void mull(Address src);
618 void mull(Register src);
620 void negl(Register dst);
622 void notl(Register dst);
624 void orl(Address dst, int imm32);
625 void orl(Register dst, int imm32);
626 void orl(Register dst, Address src);
627 void orl(Register dst, Register src);
629 void rcll(Register dst, int imm8);
631 void sarl(Register dst, int imm8);
632 void sarl(Register dst);
634 void sbbl(Address dst, int imm32);
635 void sbbl(Register dst, int imm32);
636 void sbbl(Register dst, Address src);
637 void sbbl(Register dst, Register src);
639 void shldl(Register dst, Register src);
641 void shll(Register dst, int imm8);
642 void shll(Register dst);
644 void shrdl(Register dst, Register src);
646 void shrl(Register dst, int imm8);
647 void shrl(Register dst);
649 void subl(Address dst, int imm32);
650 void subl(Address dst, Register src);
651 void subl(Register dst, int imm32);
652 void subl(Register dst, Address src);
653 void subl(Register dst, Register src);
655 void testb(Register dst, int imm8);
656 void testl(Register dst, int imm32);
657 void testl(Register dst, Address src);
658 void testl(Register dst, Register src);
660 void xaddl(Address dst, Register src);
662 void xorl(Register dst, int imm32);
663 void xorl(Register dst, Address src);
664 void xorl(Register dst, Register src);
666 // Miscellaneous
667 void bswap(Register reg);
668 void lock();
670 void xchg (Register reg, Address adr);
671 void xchgl(Register dst, Register src);
673 void cmpxchg (Register reg, Address adr);
674 void cmpxchg8 (Address adr);
676 void nop(int i = 1);
677 void addr_nop_4();
678 void addr_nop_5();
679 void addr_nop_7();
680 void addr_nop_8();
682 void hlt();
683 void ret(int imm16);
684 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
685 void smovl();
686 void rep_movl();
687 void rep_set();
688 void repne_scan();
689 void setb(Condition cc, Register dst);
690 void membar(); // Serializing memory-fence
691 void cpuid();
692 void cld();
693 void std();
695 void emit_raw (unsigned char);
697 // Calls
698 void call(Label& L, relocInfo::relocType rtype);
699 void call(Register reg); // push pc; pc <- reg
700 void call(Address adr); // push pc; pc <- adr
702 // Jumps
703 void jmp(Address entry); // pc <- entry
704 void jmp(Register entry); // pc <- entry
706 // Label operations & relative jumps (PPUM Appendix D)
707 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
709 // Force an 8-bit jump offset
710 // void jmpb(address entry);
712 // Unconditional 8-bit offset jump to L.
713 // WARNING: be very careful using this for forward jumps. If the label is
714 // not bound within an 8-bit offset of this instruction, a run-time error
715 // will occur.
716 void jmpb(Label& L);
718 // jcc is the generic conditional branch generator to run-
719 // time routines, jcc is used for branches to labels. jcc
720 // takes a branch opcode (cc) and a label (L) and generates
721 // either a backward branch or a forward branch and links it
722 // to the label fixup chain. Usage:
723 //
724 // Label L; // unbound label
725 // jcc(cc, L); // forward branch to unbound label
726 // bind(L); // bind label to the current pc
727 // jcc(cc, L); // backward branch to bound label
728 // bind(L); // illegal: a label may be bound only once
729 //
730 // Note: The same Label can be used for forward and backward branches
731 // but it may be bound only once.
733 void jcc(Condition cc, Label& L,
734 relocInfo::relocType rtype = relocInfo::none);
736 // Conditional jump to a 8-bit offset to L.
737 // WARNING: be very careful using this for forward jumps. If the label is
738 // not bound within an 8-bit offset of this instruction, a run-time error
739 // will occur.
740 void jccb(Condition cc, Label& L);
742 // Floating-point operations
743 void fld1();
744 void fldz();
746 void fld_s(Address adr);
747 void fld_s(int index);
748 void fld_d(Address adr);
749 void fld_x(Address adr); // extended-precision (80-bit) format
751 void fst_s(Address adr);
752 void fst_d(Address adr);
754 void fstp_s(Address adr);
755 void fstp_d(Address adr);
756 void fstp_d(int index);
757 void fstp_x(Address adr); // extended-precision (80-bit) format
759 void fild_s(Address adr);
760 void fild_d(Address adr);
762 void fist_s (Address adr);
763 void fistp_s(Address adr);
764 void fistp_d(Address adr);
766 void fabs();
767 void fchs();
769 void flog();
770 void flog10();
772 void fldln2();
773 void fyl2x();
774 void fldlg2();
776 void fcos();
777 void fsin();
778 void ftan();
779 void fsqrt();
781 // "Alternate" versions of instructions place result down in FPU
782 // stack instead of on TOS
783 void fadd_s(Address src);
784 void fadd_d(Address src);
785 void fadd(int i);
786 void fadda(int i); // "alternate" fadd
788 void fsub_s(Address src);
789 void fsub_d(Address src);
790 void fsubr_s(Address src);
791 void fsubr_d(Address src);
793 void fmul_s(Address src);
794 void fmul_d(Address src);
795 void fmul(int i);
796 void fmula(int i); // "alternate" fmul
798 void fdiv_s(Address src);
799 void fdiv_d(Address src);
800 void fdivr_s(Address src);
801 void fdivr_d(Address src);
803 void fsub(int i);
804 void fsuba(int i); // "alternate" fsub
805 void fsubr(int i);
806 void fsubra(int i); // "alternate" reversed fsub
807 void fdiv(int i);
808 void fdiva(int i); // "alternate" fdiv
809 void fdivr(int i);
810 void fdivra(int i); // "alternate" reversed fdiv
812 void faddp(int i = 1);
813 void fsubp(int i = 1);
814 void fsubrp(int i = 1);
815 void fmulp(int i = 1);
816 void fdivp(int i = 1);
817 void fdivrp(int i = 1);
818 void fprem();
819 void fprem1();
821 void fxch(int i = 1);
822 void fincstp();
823 void fdecstp();
824 void ffree(int i = 0);
826 void fcomp_s(Address src);
827 void fcomp_d(Address src);
828 void fcom(int i);
829 void fcomp(int i = 1);
830 void fcompp();
832 void fucomi(int i = 1);
833 void fucomip(int i = 1);
835 void ftst();
836 void fnstsw_ax();
837 void fwait();
838 void finit();
839 void fldcw(Address src);
840 void fnstcw(Address src);
842 void fnsave(Address dst);
843 void frstor(Address src);
844 void fldenv(Address src);
846 void sahf();
848 protected:
849 void emit_sse_operand(XMMRegister reg, Address adr);
850 void emit_sse_operand(Register reg, Address adr);
851 void emit_sse_operand(XMMRegister dst, XMMRegister src);
852 void emit_sse_operand(XMMRegister dst, Register src);
853 void emit_sse_operand(Register dst, XMMRegister src);
855 void emit_operand(MMXRegister reg, Address adr);
857 public:
858 // mmx operations
859 void movq( MMXRegister dst, Address src );
860 void movq( Address dst, MMXRegister src );
861 void emms();
863 // xmm operations
864 void addss(XMMRegister dst, Address src); // Add Scalar Single-Precision Floating-Point Values
865 void addss(XMMRegister dst, XMMRegister src);
866 void addsd(XMMRegister dst, Address src); // Add Scalar Double-Precision Floating-Point Values
867 void addsd(XMMRegister dst, XMMRegister src);
869 void subss(XMMRegister dst, Address src); // Subtract Scalar Single-Precision Floating-Point Values
870 void subss(XMMRegister dst, XMMRegister src);
871 void subsd(XMMRegister dst, Address src); // Subtract Scalar Double-Precision Floating-Point Values
872 void subsd(XMMRegister dst, XMMRegister src);
874 void mulss(XMMRegister dst, Address src); // Multiply Scalar Single-Precision Floating-Point Values
875 void mulss(XMMRegister dst, XMMRegister src);
876 void mulsd(XMMRegister dst, Address src); // Multiply Scalar Double-Precision Floating-Point Values
877 void mulsd(XMMRegister dst, XMMRegister src);
879 void divss(XMMRegister dst, Address src); // Divide Scalar Single-Precision Floating-Point Values
880 void divss(XMMRegister dst, XMMRegister src);
881 void divsd(XMMRegister dst, Address src); // Divide Scalar Double-Precision Floating-Point Values
882 void divsd(XMMRegister dst, XMMRegister src);
884 void sqrtss(XMMRegister dst, Address src); // Compute Square Root of Scalar Single-Precision Floating-Point Value
885 void sqrtss(XMMRegister dst, XMMRegister src);
886 void sqrtsd(XMMRegister dst, Address src); // Compute Square Root of Scalar Double-Precision Floating-Point Value
887 void sqrtsd(XMMRegister dst, XMMRegister src);
889 void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values
890 void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values
892 void comiss(XMMRegister dst, Address src); // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
893 void comiss(XMMRegister dst, XMMRegister src);
894 void comisd(XMMRegister dst, Address src); // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
895 void comisd(XMMRegister dst, XMMRegister src);
897 void ucomiss(XMMRegister dst, Address src); // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
898 void ucomiss(XMMRegister dst, XMMRegister src);
899 void ucomisd(XMMRegister dst, Address src); // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
900 void ucomisd(XMMRegister dst, XMMRegister src);
902 void cvtss2sd(XMMRegister dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
903 void cvtss2sd(XMMRegister dst, XMMRegister src);
904 void cvtsd2ss(XMMRegister dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
905 void cvtsd2ss(XMMRegister dst, XMMRegister src);
906 void cvtdq2pd(XMMRegister dst, XMMRegister src);
907 void cvtdq2ps(XMMRegister dst, XMMRegister src);
909 void cvtsi2ss(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
910 void cvtsi2ss(XMMRegister dst, Register src);
911 void cvtsi2sd(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
912 void cvtsi2sd(XMMRegister dst, Register src);
914 void cvtss2si(Register dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
915 void cvtss2si(Register dst, XMMRegister src);
916 void cvtsd2si(Register dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
917 void cvtsd2si(Register dst, XMMRegister src);
919 void cvttss2si(Register dst, Address src); // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
920 void cvttss2si(Register dst, XMMRegister src);
921 void cvttsd2si(Register dst, Address src); // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
922 void cvttsd2si(Register dst, XMMRegister src);
924 protected: // Avoid using the next instructions directly.
925 // New cpus require use of movsd and movss to avoid partial register stall
926 // when loading from memory. But for old Opteron use movlpd instead of movsd.
927 // The selection is done in MacroAssembler::movdbl() and movflt().
928 void movss(XMMRegister dst, Address src); // Move Scalar Single-Precision Floating-Point Values
929 void movss(XMMRegister dst, XMMRegister src);
930 void movss(Address dst, XMMRegister src);
931 void movsd(XMMRegister dst, Address src); // Move Scalar Double-Precision Floating-Point Values
932 void movsd(XMMRegister dst, XMMRegister src);
933 void movsd(Address dst, XMMRegister src);
934 void movlpd(XMMRegister dst, Address src);
935 // New cpus require use of movaps and movapd to avoid partial register stall
936 // when moving between registers.
937 void movaps(XMMRegister dst, XMMRegister src);
938 void movapd(XMMRegister dst, XMMRegister src);
939 public:
941 void andps(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
942 void andps(XMMRegister dst, XMMRegister src);
943 void andpd(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
944 void andpd(XMMRegister dst, XMMRegister src);
946 void andnps(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
947 void andnps(XMMRegister dst, XMMRegister src);
948 void andnpd(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
949 void andnpd(XMMRegister dst, XMMRegister src);
951 void orps(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Single-Precision Floating-Point Values
952 void orps(XMMRegister dst, XMMRegister src);
953 void orpd(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Double-Precision Floating-Point Values
954 void orpd(XMMRegister dst, XMMRegister src);
956 void xorps(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
957 void xorps(XMMRegister dst, XMMRegister src);
958 void xorpd(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
959 void xorpd(XMMRegister dst, XMMRegister src);
961 void movq(XMMRegister dst, Address src); // Move Quadword
962 void movq(XMMRegister dst, XMMRegister src);
963 void movq(Address dst, XMMRegister src);
965 void movd(XMMRegister dst, Address src); // Move Doubleword
966 void movd(XMMRegister dst, Register src);
967 void movd(Register dst, XMMRegister src);
968 void movd(Address dst, XMMRegister src);
970 void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword
971 void movdqa(XMMRegister dst, XMMRegister src);
972 void movdqa(Address dst, XMMRegister src);
974 void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
975 void pshufd(XMMRegister dst, Address src, int mode);
976 void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
977 void pshuflw(XMMRegister dst, Address src, int mode);
979 void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
981 void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
982 void punpcklbw(XMMRegister dst, Address src);
984 void ldmxcsr( Address src );
985 void stmxcsr( Address dst );
986 };
989 // MacroAssembler extends Assembler by frequently used macros.
990 //
991 // Instructions for which a 'better' code sequence exists depending
992 // on arguments should also go in here.
994 class MacroAssembler: public Assembler {
995 friend class LIR_Assembler;
996 friend class Runtime1; // as_Address()
997 protected:
999 Address as_Address(AddressLiteral adr);
1000 Address as_Address(ArrayAddress adr);
1002 // Support for VM calls
1003 //
1004 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1005 // may customize this version by overriding it for its purposes (e.g., to save/restore
1006 // additional registers when doing a VM call).
1007 #ifdef CC_INTERP
1008 // c++ interpreter never wants to use interp_masm version of call_VM
1009 #define VIRTUAL
1010 #else
1011 #define VIRTUAL virtual
1012 #endif
1014 VIRTUAL void call_VM_leaf_base(
1015 address entry_point, // the entry point
1016 int number_of_arguments // the number of arguments to pop after the call
1017 );
1019 // This is the base routine called by the different versions of call_VM. The interpreter
1020 // may customize this version by overriding it for its purposes (e.g., to save/restore
1021 // additional registers when doing a VM call).
1022 //
1023 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1024 // returns the register which contains the thread upon return. If a thread register has been
1025 // specified, the return value will correspond to that register. If no last_java_sp is specified
1026 // (noreg) than rsp will be used instead.
1027 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1028 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1029 Register java_thread, // the thread if computed before ; use noreg otherwise
1030 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1031 address entry_point, // the entry point
1032 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1033 bool check_exceptions // whether to check for pending exceptions after return
1034 );
1036 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1037 // The implementation is only non-empty for the InterpreterMacroAssembler,
1038 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1039 virtual void check_and_handle_popframe(Register java_thread);
1040 virtual void check_and_handle_earlyret(Register java_thread);
1042 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1044 // helpers for FPU flag access
1045 // tmp is a temporary register, if none is available use noreg
1046 void save_rax (Register tmp);
1047 void restore_rax(Register tmp);
1049 public:
1050 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1052 // Support for NULL-checks
1053 //
1054 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1055 // If the accessed location is M[reg + offset] and the offset is known, provide the
1056 // offset. No explicit code generation is needed if the offset is within a certain
1057 // range (0 <= offset <= page_size).
1059 void null_check(Register reg, int offset = -1);
1060 static bool needs_explicit_null_check(intptr_t offset);
1062 // Required platform-specific helpers for Label::patch_instructions.
1063 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1064 void pd_patch_instruction(address branch, address target);
1065 #ifndef PRODUCT
1066 static void pd_print_patched_instruction(address branch);
1067 #endif
1069 // The following 4 methods return the offset of the appropriate move instruction
1071 // Support for fast byte/word loading with zero extension (depending on particular CPU)
1072 int load_unsigned_byte(Register dst, Address src);
1073 int load_unsigned_word(Register dst, Address src);
1075 // Support for fast byte/word loading with sign extension (depending on particular CPU)
1076 int load_signed_byte(Register dst, Address src);
1077 int load_signed_word(Register dst, Address src);
1079 // Support for sign-extension (hi:lo = extend_sign(lo))
1080 void extend_sign(Register hi, Register lo);
1082 // Support for inc/dec with optimal instruction selection depending on value
1083 void increment(Register reg, int value = 1);
1084 void decrement(Register reg, int value = 1);
1085 void increment(Address dst, int value = 1);
1086 void decrement(Address dst, int value = 1);
1088 // Support optimal SSE move instructions.
1089 void movflt(XMMRegister dst, XMMRegister src) {
1090 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1091 else { movss (dst, src); return; }
1092 }
1093 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1094 void movflt(XMMRegister dst, AddressLiteral src);
1095 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1097 void movdbl(XMMRegister dst, XMMRegister src) {
1098 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1099 else { movsd (dst, src); return; }
1100 }
1102 void movdbl(XMMRegister dst, AddressLiteral src);
1104 void movdbl(XMMRegister dst, Address src) {
1105 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1106 else { movlpd(dst, src); return; }
1107 }
1108 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1110 void increment(AddressLiteral dst);
1111 void increment(ArrayAddress dst);
1114 // Alignment
1115 void align(int modulus);
1117 // Misc
1118 void fat_nop(); // 5 byte nop
1120 // Stack frame creation/removal
1121 void enter();
1122 void leave();
1124 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1125 // The pointer will be loaded into the thread register.
1126 void get_thread(Register thread);
1128 // Support for VM calls
1129 //
1130 // It is imperative that all calls into the VM are handled via the call_VM macros.
1131 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1132 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1134 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
1135 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
1136 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1137 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1139 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1140 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1141 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1142 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1144 void call_VM_leaf(address entry_point, int number_of_arguments = 0);
1145 void call_VM_leaf(address entry_point, Register arg_1);
1146 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1147 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
1149 // last Java Frame (fills frame anchor)
1150 void set_last_Java_frame(Register thread, Register last_java_sp, Register last_java_fp, address last_java_pc);
1151 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1153 // Stores
1154 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1155 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1157 void g1_write_barrier_pre(Register obj, Register thread, Register tmp, Register tmp2, bool tosca_live );
1158 void g1_write_barrier_post(Register store_addr, Register new_val, Register thread, Register tmp, Register tmp2);
1161 // split store_check(Register obj) to enhance instruction interleaving
1162 void store_check_part_1(Register obj);
1163 void store_check_part_2(Register obj);
1165 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1166 void c2bool(Register x);
1168 // C++ bool manipulation
1170 void movbool(Register dst, Address src);
1171 void movbool(Address dst, bool boolconst);
1172 void movbool(Address dst, Register src);
1173 void testbool(Register dst);
1175 // Int division/reminder for Java
1176 // (as idivl, but checks for special case as described in JVM spec.)
1177 // returns idivl instruction offset for implicit exception handling
1178 int corrected_idivl(Register reg);
1180 void int3();
1182 // Long negation for Java
1183 void lneg(Register hi, Register lo);
1185 // Long multiplication for Java
1186 // (destroys contents of rax, rbx, rcx and rdx)
1187 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1189 // Long shifts for Java
1190 // (semantics as described in JVM spec.)
1191 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1192 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1194 // Long compare for Java
1195 // (semantics as described in JVM spec.)
1196 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1198 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1199 //
1200 // CF (corresponds to C0) if x < y
1201 // PF (corresponds to C2) if unordered
1202 // ZF (corresponds to C3) if x = y
1203 //
1204 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1205 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1206 void fcmp(Register tmp);
1207 // Variant of the above which allows y to be further down the stack
1208 // and which only pops x and y if specified. If pop_right is
1209 // specified then pop_left must also be specified.
1210 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1212 // Floating-point comparison for Java
1213 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1214 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1215 // (semantics as described in JVM spec.)
1216 void fcmp2int(Register dst, bool unordered_is_less);
1217 // Variant of the above which allows y to be further down the stack
1218 // and which only pops x and y if specified. If pop_right is
1219 // specified then pop_left must also be specified.
1220 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1222 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1223 // tmp is a temporary register, if none is available use noreg
1224 void fremr(Register tmp);
1227 // same as fcmp2int, but using SSE2
1228 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1229 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1231 // Inlined sin/cos generator for Java; must not use CPU instruction
1232 // directly on Intel as it does not have high enough precision
1233 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1234 // number of FPU stack slots in use; all but the topmost will
1235 // require saving if a slow case is necessary. Assumes argument is
1236 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1237 // this code.
1238 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1240 // branch to L if FPU flag C2 is set/not set
1241 // tmp is a temporary register, if none is available use noreg
1242 void jC2 (Register tmp, Label& L);
1243 void jnC2(Register tmp, Label& L);
1245 // Pop ST (ffree & fincstp combined)
1246 void fpop();
1248 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1249 void push_fTOS();
1251 // pops double TOS element from CPU stack and pushes on FPU stack
1252 void pop_fTOS();
1254 void empty_FPU_stack();
1256 void push_IU_state();
1257 void pop_IU_state();
1259 void push_FPU_state();
1260 void pop_FPU_state();
1262 void push_CPU_state();
1263 void pop_CPU_state();
1265 // Sign extension
1266 void sign_extend_short(Register reg);
1267 void sign_extend_byte(Register reg);
1269 // Division by power of 2, rounding towards 0
1270 void division_with_shift(Register reg, int shift_value);
1272 // Round up to a power of two
1273 void round_to(Register reg, int modulus);
1275 // Callee saved registers handling
1276 void push_callee_saved_registers();
1277 void pop_callee_saved_registers();
1279 // allocation
1280 void eden_allocate(
1281 Register obj, // result: pointer to object after successful allocation
1282 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1283 int con_size_in_bytes, // object size in bytes if known at compile time
1284 Register t1, // temp register
1285 Label& slow_case // continuation point if fast allocation fails
1286 );
1287 void tlab_allocate(
1288 Register obj, // result: pointer to object after successful allocation
1289 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1290 int con_size_in_bytes, // object size in bytes if known at compile time
1291 Register t1, // temp register
1292 Register t2, // temp register
1293 Label& slow_case // continuation point if fast allocation fails
1294 );
1295 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1297 //----
1298 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1300 // Debugging
1301 void verify_oop(Register reg, const char* s = "broken oop"); // only if +VerifyOops
1302 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1304 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); // only if +VerifyFPU
1305 void stop(const char* msg); // prints msg, dumps registers and stops execution
1306 void warn(const char* msg); // prints msg and continues
1307 static void debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1308 void os_breakpoint();
1309 void untested() { stop("untested"); }
1310 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
1311 void should_not_reach_here() { stop("should not reach here"); }
1312 void print_CPU_state();
1314 // Stack overflow checking
1315 void bang_stack_with_offset(int offset) {
1316 // stack grows down, caller passes positive offset
1317 assert(offset > 0, "must bang with negative offset");
1318 movl(Address(rsp, (-offset)), rax);
1319 }
1321 // Writes to stack successive pages until offset reached to check for
1322 // stack overflow + shadow pages. Also, clobbers tmp
1323 void bang_stack_size(Register size, Register tmp);
1325 // Support for serializing memory accesses between threads
1326 void serialize_memory(Register thread, Register tmp);
1328 void verify_tlab();
1330 // Biased locking support
1331 // lock_reg and obj_reg must be loaded up with the appropriate values.
1332 // swap_reg must be rax, and is killed.
1333 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1334 // be killed; if not supplied, push/pop will be used internally to
1335 // allocate a temporary (inefficient, avoid if possible).
1336 // Optional slow case is for implementations (interpreter and C1) which branch to
1337 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1338 // Returns offset of first potentially-faulting instruction for null
1339 // check info (currently consumed only by C1). If
1340 // swap_reg_contains_mark is true then returns -1 as it is assumed
1341 // the calling code has already passed any potential faults.
1342 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
1343 bool swap_reg_contains_mark,
1344 Label& done, Label* slow_case = NULL,
1345 BiasedLockingCounters* counters = NULL);
1346 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1349 Condition negate_condition(Condition cond);
1351 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1352 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1353 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1354 // here in MacroAssembler. The major exception to this rule is call
1356 // Arithmetics
1358 void cmp8(AddressLiteral src1, int8_t imm);
1360 // QQQ renamed to drag out the casting of address to int32_t/intptr_t
1361 void cmp32(Register src1, int32_t imm);
1363 void cmp32(AddressLiteral src1, int32_t imm);
1364 // compare reg - mem, or reg - &mem
1365 void cmp32(Register src1, AddressLiteral src2);
1367 void cmp32(Register src1, Address src2);
1369 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1370 void cmpptr(Address src1, AddressLiteral src2);
1372 void cmpptr(Register src1, AddressLiteral src2);
1374 void cmpoop(Address dst, jobject obj);
1375 void cmpoop(Register dst, jobject obj);
1378 void cmpxchgptr(Register reg, AddressLiteral adr);
1380 // Helper functions for statistics gathering.
1381 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
1382 void cond_inc32(Condition cond, AddressLiteral counter_addr);
1383 // Unconditional atomic increment.
1384 void atomic_incl(AddressLiteral counter_addr);
1386 void lea(Register dst, AddressLiteral adr);
1387 void lea(Address dst, AddressLiteral adr);
1389 void test32(Register dst, AddressLiteral src);
1391 // Calls
1393 void call(Label& L, relocInfo::relocType rtype);
1394 void call(Register entry);
1396 // NOTE: this call tranfers to the effective address of entry NOT
1397 // the address contained by entry. This is because this is more natural
1398 // for jumps/calls.
1399 void call(AddressLiteral entry);
1401 // Jumps
1403 // NOTE: these jumps tranfer to the effective address of dst NOT
1404 // the address contained by dst. This is because this is more natural
1405 // for jumps/calls.
1406 void jump(AddressLiteral dst);
1407 void jump_cc(Condition cc, AddressLiteral dst);
1409 // 32bit can do a case table jump in one instruction but we no longer allow the base
1410 // to be installed in the Address class. This jump will tranfers to the address
1411 // contained in the location described by entry (not the address of entry)
1412 void jump(ArrayAddress entry);
1414 // Floating
1416 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1417 void andpd(XMMRegister dst, AddressLiteral src);
1419 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1420 void comiss(XMMRegister dst, AddressLiteral src);
1422 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1423 void comisd(XMMRegister dst, AddressLiteral src);
1425 void fldcw(Address src) { Assembler::fldcw(src); }
1426 void fldcw(AddressLiteral src);
1428 void fld_s(int index) { Assembler::fld_s(index); }
1429 void fld_s(Address src) { Assembler::fld_s(src); }
1430 void fld_s(AddressLiteral src);
1432 void fld_d(Address src) { Assembler::fld_d(src); }
1433 void fld_d(AddressLiteral src);
1435 void fld_x(Address src) { Assembler::fld_x(src); }
1436 void fld_x(AddressLiteral src);
1438 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1439 void ldmxcsr(AddressLiteral src);
1441 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1442 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1443 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1444 void movss(XMMRegister dst, AddressLiteral src);
1446 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1447 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1448 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1449 void movsd(XMMRegister dst, AddressLiteral src);
1451 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1452 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1453 void ucomiss(XMMRegister dst, AddressLiteral src);
1455 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1456 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1457 void ucomisd(XMMRegister dst, AddressLiteral src);
1459 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1460 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
1461 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1462 void xorpd(XMMRegister dst, AddressLiteral src);
1464 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1465 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
1466 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1467 void xorps(XMMRegister dst, AddressLiteral src);
1469 // Data
1471 void movoop(Register dst, jobject obj);
1472 void movoop(Address dst, jobject obj);
1474 void movptr(ArrayAddress dst, Register src);
1475 // can this do an lea?
1476 void movptr(Register dst, ArrayAddress src);
1478 void movptr(Register dst, AddressLiteral src);
1480 // to avoid hiding movl
1481 void mov32(AddressLiteral dst, Register src);
1482 void mov32(Register dst, AddressLiteral src);
1483 // to avoid hiding movb
1484 void movbyte(ArrayAddress dst, int src);
1486 // Can push value or effective address
1487 void pushptr(AddressLiteral src);
1489 #undef VIRTUAL
1491 };
1493 /**
1494 * class SkipIfEqual:
1495 *
1496 * Instantiating this class will result in assembly code being output that will
1497 * jump around any code emitted between the creation of the instance and it's
1498 * automatic destruction at the end of a scope block, depending on the value of
1499 * the flag passed to the constructor, which will be checked at run-time.
1500 */
1501 class SkipIfEqual {
1502 private:
1503 MacroAssembler* _masm;
1504 Label _label;
1506 public:
1507 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1508 ~SkipIfEqual();
1509 };
1511 #ifdef ASSERT
1512 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
1513 #endif