Tue, 10 Mar 2020 10:46:35 +0100
8146612: C2: Precedence edges specification violated
Reviewed-by: kvn
1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "opto/vectornode.hpp"
39 #include "runtime/atomic.hpp"
40 #include "runtime/os.hpp"
41 #if defined AD_MD_HPP
42 # include AD_MD_HPP
43 #elif defined TARGET_ARCH_MODEL_x86_32
44 # include "adfiles/ad_x86_32.hpp"
45 #elif defined TARGET_ARCH_MODEL_x86_64
46 # include "adfiles/ad_x86_64.hpp"
47 #elif defined TARGET_ARCH_MODEL_sparc
48 # include "adfiles/ad_sparc.hpp"
49 #elif defined TARGET_ARCH_MODEL_zero
50 # include "adfiles/ad_zero.hpp"
51 #elif defined TARGET_ARCH_MODEL_ppc_64
52 # include "adfiles/ad_ppc_64.hpp"
53 #endif
55 OptoReg::Name OptoReg::c_frame_pointer;
57 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
58 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
59 RegMask Matcher::STACK_ONLY_mask;
60 RegMask Matcher::c_frame_ptr_mask;
61 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
62 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
64 //---------------------------Matcher-------------------------------------------
65 Matcher::Matcher()
66 : PhaseTransform( Phase::Ins_Select ),
67 #ifdef ASSERT
68 _old2new_map(C->comp_arena()),
69 _new2old_map(C->comp_arena()),
70 #endif
71 _shared_nodes(C->comp_arena()),
72 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
73 _swallowed(swallowed),
74 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
75 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
76 _must_clone(must_clone),
77 _register_save_policy(register_save_policy),
78 _c_reg_save_policy(c_reg_save_policy),
79 _register_save_type(register_save_type),
80 _ruleName(ruleName),
81 _allocation_started(false),
82 _states_arena(Chunk::medium_size, mtCompiler),
83 _visited(&_states_arena),
84 _shared(&_states_arena),
85 _dontcare(&_states_arena) {
86 C->set_matcher(this);
88 idealreg2spillmask [Op_RegI] = NULL;
89 idealreg2spillmask [Op_RegN] = NULL;
90 idealreg2spillmask [Op_RegL] = NULL;
91 idealreg2spillmask [Op_RegF] = NULL;
92 idealreg2spillmask [Op_RegD] = NULL;
93 idealreg2spillmask [Op_RegP] = NULL;
94 idealreg2spillmask [Op_VecS] = NULL;
95 idealreg2spillmask [Op_VecD] = NULL;
96 idealreg2spillmask [Op_VecX] = NULL;
97 idealreg2spillmask [Op_VecY] = NULL;
98 idealreg2spillmask [Op_RegFlags] = NULL;
100 idealreg2debugmask [Op_RegI] = NULL;
101 idealreg2debugmask [Op_RegN] = NULL;
102 idealreg2debugmask [Op_RegL] = NULL;
103 idealreg2debugmask [Op_RegF] = NULL;
104 idealreg2debugmask [Op_RegD] = NULL;
105 idealreg2debugmask [Op_RegP] = NULL;
106 idealreg2debugmask [Op_VecS] = NULL;
107 idealreg2debugmask [Op_VecD] = NULL;
108 idealreg2debugmask [Op_VecX] = NULL;
109 idealreg2debugmask [Op_VecY] = NULL;
110 idealreg2debugmask [Op_RegFlags] = NULL;
112 idealreg2mhdebugmask[Op_RegI] = NULL;
113 idealreg2mhdebugmask[Op_RegN] = NULL;
114 idealreg2mhdebugmask[Op_RegL] = NULL;
115 idealreg2mhdebugmask[Op_RegF] = NULL;
116 idealreg2mhdebugmask[Op_RegD] = NULL;
117 idealreg2mhdebugmask[Op_RegP] = NULL;
118 idealreg2mhdebugmask[Op_VecS] = NULL;
119 idealreg2mhdebugmask[Op_VecD] = NULL;
120 idealreg2mhdebugmask[Op_VecX] = NULL;
121 idealreg2mhdebugmask[Op_VecY] = NULL;
122 idealreg2mhdebugmask[Op_RegFlags] = NULL;
124 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
125 }
127 //------------------------------warp_incoming_stk_arg------------------------
128 // This warps a VMReg into an OptoReg::Name
129 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
130 OptoReg::Name warped;
131 if( reg->is_stack() ) { // Stack slot argument?
132 warped = OptoReg::add(_old_SP, reg->reg2stack() );
133 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
134 if( warped >= _in_arg_limit )
135 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
136 if (!RegMask::can_represent_arg(warped)) {
137 // the compiler cannot represent this method's calling sequence
138 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
139 return OptoReg::Bad;
140 }
141 return warped;
142 }
143 return OptoReg::as_OptoReg(reg);
144 }
146 //---------------------------compute_old_SP------------------------------------
147 OptoReg::Name Compile::compute_old_SP() {
148 int fixed = fixed_slots();
149 int preserve = in_preserve_stack_slots();
150 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
151 }
155 #ifdef ASSERT
156 void Matcher::verify_new_nodes_only(Node* xroot) {
157 // Make sure that the new graph only references new nodes
158 ResourceMark rm;
159 Unique_Node_List worklist;
160 VectorSet visited(Thread::current()->resource_area());
161 worklist.push(xroot);
162 while (worklist.size() > 0) {
163 Node* n = worklist.pop();
164 visited <<= n->_idx;
165 assert(C->node_arena()->contains(n), "dead node");
166 for (uint j = 0; j < n->req(); j++) {
167 Node* in = n->in(j);
168 if (in != NULL) {
169 assert(C->node_arena()->contains(in), "dead node");
170 if (!visited.test(in->_idx)) {
171 worklist.push(in);
172 }
173 }
174 }
175 }
176 }
177 #endif
180 //---------------------------match---------------------------------------------
181 void Matcher::match( ) {
182 if( MaxLabelRootDepth < 100 ) { // Too small?
183 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
184 MaxLabelRootDepth = 100;
185 }
186 // One-time initialization of some register masks.
187 init_spill_mask( C->root()->in(1) );
188 _return_addr_mask = return_addr();
189 #ifdef _LP64
190 // Pointers take 2 slots in 64-bit land
191 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
192 #endif
194 // Map a Java-signature return type into return register-value
195 // machine registers for 0, 1 and 2 returned values.
196 const TypeTuple *range = C->tf()->range();
197 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
198 // Get ideal-register return type
199 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
200 // Get machine return register
201 uint sop = C->start()->Opcode();
202 OptoRegPair regs = return_value(ireg, false);
204 // And mask for same
205 _return_value_mask = RegMask(regs.first());
206 if( OptoReg::is_valid(regs.second()) )
207 _return_value_mask.Insert(regs.second());
208 }
210 // ---------------
211 // Frame Layout
213 // Need the method signature to determine the incoming argument types,
214 // because the types determine which registers the incoming arguments are
215 // in, and this affects the matched code.
216 const TypeTuple *domain = C->tf()->domain();
217 uint argcnt = domain->cnt() - TypeFunc::Parms;
218 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
219 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
220 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
221 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
222 uint i;
223 for( i = 0; i<argcnt; i++ ) {
224 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
225 }
227 // Pass array of ideal registers and length to USER code (from the AD file)
228 // that will convert this to an array of register numbers.
229 const StartNode *start = C->start();
230 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
231 #ifdef ASSERT
232 // Sanity check users' calling convention. Real handy while trying to
233 // get the initial port correct.
234 { for (uint i = 0; i<argcnt; i++) {
235 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
236 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
237 _parm_regs[i].set_bad();
238 continue;
239 }
240 VMReg parm_reg = vm_parm_regs[i].first();
241 assert(parm_reg->is_valid(), "invalid arg?");
242 if (parm_reg->is_reg()) {
243 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
244 assert(can_be_java_arg(opto_parm_reg) ||
245 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
246 opto_parm_reg == inline_cache_reg(),
247 "parameters in register must be preserved by runtime stubs");
248 }
249 for (uint j = 0; j < i; j++) {
250 assert(parm_reg != vm_parm_regs[j].first(),
251 "calling conv. must produce distinct regs");
252 }
253 }
254 }
255 #endif
257 // Do some initial frame layout.
259 // Compute the old incoming SP (may be called FP) as
260 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
261 _old_SP = C->compute_old_SP();
262 assert( is_even(_old_SP), "must be even" );
264 // Compute highest incoming stack argument as
265 // _old_SP + out_preserve_stack_slots + incoming argument size.
266 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
267 assert( is_even(_in_arg_limit), "out_preserve must be even" );
268 for( i = 0; i < argcnt; i++ ) {
269 // Permit args to have no register
270 _calling_convention_mask[i].Clear();
271 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
272 continue;
273 }
274 // calling_convention returns stack arguments as a count of
275 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
276 // the allocators point of view, taking into account all the
277 // preserve area, locks & pad2.
279 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
280 if( OptoReg::is_valid(reg1))
281 _calling_convention_mask[i].Insert(reg1);
283 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
284 if( OptoReg::is_valid(reg2))
285 _calling_convention_mask[i].Insert(reg2);
287 // Saved biased stack-slot register number
288 _parm_regs[i].set_pair(reg2, reg1);
289 }
291 // Finally, make sure the incoming arguments take up an even number of
292 // words, in case the arguments or locals need to contain doubleword stack
293 // slots. The rest of the system assumes that stack slot pairs (in
294 // particular, in the spill area) which look aligned will in fact be
295 // aligned relative to the stack pointer in the target machine. Double
296 // stack slots will always be allocated aligned.
297 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
299 // Compute highest outgoing stack argument as
300 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
301 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
302 assert( is_even(_out_arg_limit), "out_preserve must be even" );
304 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
305 // the compiler cannot represent this method's calling sequence
306 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
307 }
309 if (C->failing()) return; // bailed out on incoming arg failure
311 // ---------------
312 // Collect roots of matcher trees. Every node for which
313 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
314 // can be a valid interior of some tree.
315 find_shared( C->root() );
316 find_shared( C->top() );
318 C->print_method(PHASE_BEFORE_MATCHING);
320 // Create new ideal node ConP #NULL even if it does exist in old space
321 // to avoid false sharing if the corresponding mach node is not used.
322 // The corresponding mach node is only used in rare cases for derived
323 // pointers.
324 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
326 // Swap out to old-space; emptying new-space
327 Arena *old = C->node_arena()->move_contents(C->old_arena());
329 // Save debug and profile information for nodes in old space:
330 _old_node_note_array = C->node_note_array();
331 if (_old_node_note_array != NULL) {
332 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
333 (C->comp_arena(), _old_node_note_array->length(),
334 0, NULL));
335 }
337 // Pre-size the new_node table to avoid the need for range checks.
338 grow_new_node_array(C->unique());
340 // Reset node counter so MachNodes start with _idx at 0
341 int live_nodes = C->live_nodes();
342 C->set_unique(0);
343 C->reset_dead_node_list();
345 // Recursively match trees from old space into new space.
346 // Correct leaves of new-space Nodes; they point to old-space.
347 _visited.Clear(); // Clear visit bits for xform call
348 C->set_cached_top_node(xform( C->top(), live_nodes));
349 if (!C->failing()) {
350 Node* xroot = xform( C->root(), 1 );
351 if (xroot == NULL) {
352 Matcher::soft_match_failure(); // recursive matching process failed
353 C->record_method_not_compilable("instruction match failed");
354 } else {
355 // During matching shared constants were attached to C->root()
356 // because xroot wasn't available yet, so transfer the uses to
357 // the xroot.
358 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
359 Node* n = C->root()->fast_out(j);
360 if (C->node_arena()->contains(n)) {
361 assert(n->in(0) == C->root(), "should be control user");
362 n->set_req(0, xroot);
363 --j;
364 --jmax;
365 }
366 }
368 // Generate new mach node for ConP #NULL
369 assert(new_ideal_null != NULL, "sanity");
370 _mach_null = match_tree(new_ideal_null);
371 // Don't set control, it will confuse GCM since there are no uses.
372 // The control will be set when this node is used first time
373 // in find_base_for_derived().
374 assert(_mach_null != NULL, "");
376 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
378 #ifdef ASSERT
379 verify_new_nodes_only(xroot);
380 #endif
381 }
382 }
383 if (C->top() == NULL || C->root() == NULL) {
384 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
385 }
386 if (C->failing()) {
387 // delete old;
388 old->destruct_contents();
389 return;
390 }
391 assert( C->top(), "" );
392 assert( C->root(), "" );
393 validate_null_checks();
395 // Now smoke old-space
396 NOT_DEBUG( old->destruct_contents() );
398 // ------------------------
399 // Set up save-on-entry registers
400 Fixup_Save_On_Entry( );
401 }
404 //------------------------------Fixup_Save_On_Entry----------------------------
405 // The stated purpose of this routine is to take care of save-on-entry
406 // registers. However, the overall goal of the Match phase is to convert into
407 // machine-specific instructions which have RegMasks to guide allocation.
408 // So what this procedure really does is put a valid RegMask on each input
409 // to the machine-specific variations of all Return, TailCall and Halt
410 // instructions. It also adds edgs to define the save-on-entry values (and of
411 // course gives them a mask).
413 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
414 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
415 // Do all the pre-defined register masks
416 rms[TypeFunc::Control ] = RegMask::Empty;
417 rms[TypeFunc::I_O ] = RegMask::Empty;
418 rms[TypeFunc::Memory ] = RegMask::Empty;
419 rms[TypeFunc::ReturnAdr] = ret_adr;
420 rms[TypeFunc::FramePtr ] = fp;
421 return rms;
422 }
424 //---------------------------init_first_stack_mask-----------------------------
425 // Create the initial stack mask used by values spilling to the stack.
426 // Disallow any debug info in outgoing argument areas by setting the
427 // initial mask accordingly.
428 void Matcher::init_first_stack_mask() {
430 // Allocate storage for spill masks as masks for the appropriate load type.
431 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
433 idealreg2spillmask [Op_RegN] = &rms[0];
434 idealreg2spillmask [Op_RegI] = &rms[1];
435 idealreg2spillmask [Op_RegL] = &rms[2];
436 idealreg2spillmask [Op_RegF] = &rms[3];
437 idealreg2spillmask [Op_RegD] = &rms[4];
438 idealreg2spillmask [Op_RegP] = &rms[5];
440 idealreg2debugmask [Op_RegN] = &rms[6];
441 idealreg2debugmask [Op_RegI] = &rms[7];
442 idealreg2debugmask [Op_RegL] = &rms[8];
443 idealreg2debugmask [Op_RegF] = &rms[9];
444 idealreg2debugmask [Op_RegD] = &rms[10];
445 idealreg2debugmask [Op_RegP] = &rms[11];
447 idealreg2mhdebugmask[Op_RegN] = &rms[12];
448 idealreg2mhdebugmask[Op_RegI] = &rms[13];
449 idealreg2mhdebugmask[Op_RegL] = &rms[14];
450 idealreg2mhdebugmask[Op_RegF] = &rms[15];
451 idealreg2mhdebugmask[Op_RegD] = &rms[16];
452 idealreg2mhdebugmask[Op_RegP] = &rms[17];
454 idealreg2spillmask [Op_VecS] = &rms[18];
455 idealreg2spillmask [Op_VecD] = &rms[19];
456 idealreg2spillmask [Op_VecX] = &rms[20];
457 idealreg2spillmask [Op_VecY] = &rms[21];
459 OptoReg::Name i;
461 // At first, start with the empty mask
462 C->FIRST_STACK_mask().Clear();
464 // Add in the incoming argument area
465 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
466 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
467 C->FIRST_STACK_mask().Insert(i);
468 }
469 // Add in all bits past the outgoing argument area
470 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
471 "must be able to represent all call arguments in reg mask");
472 OptoReg::Name init = _out_arg_limit;
473 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
474 C->FIRST_STACK_mask().Insert(i);
475 }
476 // Finally, set the "infinite stack" bit.
477 C->FIRST_STACK_mask().set_AllStack();
479 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
480 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
481 // Keep spill masks aligned.
482 aligned_stack_mask.clear_to_pairs();
483 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
485 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
486 #ifdef _LP64
487 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
488 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
489 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
490 #else
491 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
492 #endif
493 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
494 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
495 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
496 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
497 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
498 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
499 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
500 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
502 if (Matcher::vector_size_supported(T_BYTE,4)) {
503 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
504 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
505 }
506 if (Matcher::vector_size_supported(T_FLOAT,2)) {
507 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
508 // RA guarantees such alignment since it is needed for Double and Long values.
509 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
510 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
511 }
512 if (Matcher::vector_size_supported(T_FLOAT,4)) {
513 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
514 //
515 // RA can use input arguments stack slots for spills but until RA
516 // we don't know frame size and offset of input arg stack slots.
517 //
518 // Exclude last input arg stack slots to avoid spilling vectors there
519 // otherwise vector spills could stomp over stack slots in caller frame.
520 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
521 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
522 aligned_stack_mask.Remove(in);
523 in = OptoReg::add(in, -1);
524 }
525 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
526 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
527 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
528 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
529 }
530 if (Matcher::vector_size_supported(T_FLOAT,8)) {
531 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
532 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
533 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
534 aligned_stack_mask.Remove(in);
535 in = OptoReg::add(in, -1);
536 }
537 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
538 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
539 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
540 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
541 }
542 if (UseFPUForSpilling) {
543 // This mask logic assumes that the spill operations are
544 // symmetric and that the registers involved are the same size.
545 // On sparc for instance we may have to use 64 bit moves will
546 // kill 2 registers when used with F0-F31.
547 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
548 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
549 #ifdef _LP64
550 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
551 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
552 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
553 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
554 #else
555 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
556 #ifdef ARM
557 // ARM has support for moving 64bit values between a pair of
558 // integer registers and a double register
559 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
560 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
561 #endif
562 #endif
563 }
565 // Make up debug masks. Any spill slot plus callee-save registers.
566 // Caller-save registers are assumed to be trashable by the various
567 // inline-cache fixup routines.
568 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
569 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
570 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
571 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
572 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
573 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
575 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
576 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
577 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
578 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
579 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
580 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
582 // Prevent stub compilations from attempting to reference
583 // callee-saved registers from debug info
584 bool exclude_soe = !Compile::current()->is_method_compilation();
586 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
587 // registers the caller has to save do not work
588 if( _register_save_policy[i] == 'C' ||
589 _register_save_policy[i] == 'A' ||
590 (_register_save_policy[i] == 'E' && exclude_soe) ) {
591 idealreg2debugmask [Op_RegN]->Remove(i);
592 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
593 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
594 idealreg2debugmask [Op_RegF]->Remove(i); // masks
595 idealreg2debugmask [Op_RegD]->Remove(i);
596 idealreg2debugmask [Op_RegP]->Remove(i);
598 idealreg2mhdebugmask[Op_RegN]->Remove(i);
599 idealreg2mhdebugmask[Op_RegI]->Remove(i);
600 idealreg2mhdebugmask[Op_RegL]->Remove(i);
601 idealreg2mhdebugmask[Op_RegF]->Remove(i);
602 idealreg2mhdebugmask[Op_RegD]->Remove(i);
603 idealreg2mhdebugmask[Op_RegP]->Remove(i);
604 }
605 }
607 // Subtract the register we use to save the SP for MethodHandle
608 // invokes to from the debug mask.
609 const RegMask save_mask = method_handle_invoke_SP_save_mask();
610 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
611 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
612 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
616 }
618 //---------------------------is_save_on_entry----------------------------------
619 bool Matcher::is_save_on_entry( int reg ) {
620 return
621 _register_save_policy[reg] == 'E' ||
622 _register_save_policy[reg] == 'A' || // Save-on-entry register?
623 // Also save argument registers in the trampolining stubs
624 (C->save_argument_registers() && is_spillable_arg(reg));
625 }
627 //---------------------------Fixup_Save_On_Entry-------------------------------
628 void Matcher::Fixup_Save_On_Entry( ) {
629 init_first_stack_mask();
631 Node *root = C->root(); // Short name for root
632 // Count number of save-on-entry registers.
633 uint soe_cnt = number_of_saved_registers();
634 uint i;
636 // Find the procedure Start Node
637 StartNode *start = C->start();
638 assert( start, "Expect a start node" );
640 // Save argument registers in the trampolining stubs
641 if( C->save_argument_registers() )
642 for( i = 0; i < _last_Mach_Reg; i++ )
643 if( is_spillable_arg(i) )
644 soe_cnt++;
646 // Input RegMask array shared by all Returns.
647 // The type for doubles and longs has a count of 2, but
648 // there is only 1 returned value
649 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
650 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
651 // Returns have 0 or 1 returned values depending on call signature.
652 // Return register is specified by return_value in the AD file.
653 if (ret_edge_cnt > TypeFunc::Parms)
654 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
656 // Input RegMask array shared by all Rethrows.
657 uint reth_edge_cnt = TypeFunc::Parms+1;
658 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
659 // Rethrow takes exception oop only, but in the argument 0 slot.
660 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
661 #ifdef _LP64
662 // Need two slots for ptrs in 64-bit land
663 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
664 #endif
666 // Input RegMask array shared by all TailCalls
667 uint tail_call_edge_cnt = TypeFunc::Parms+2;
668 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
670 // Input RegMask array shared by all TailJumps
671 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
672 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
674 // TailCalls have 2 returned values (target & moop), whose masks come
675 // from the usual MachNode/MachOper mechanism. Find a sample
676 // TailCall to extract these masks and put the correct masks into
677 // the tail_call_rms array.
678 for( i=1; i < root->req(); i++ ) {
679 MachReturnNode *m = root->in(i)->as_MachReturn();
680 if( m->ideal_Opcode() == Op_TailCall ) {
681 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
682 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
683 break;
684 }
685 }
687 // TailJumps have 2 returned values (target & ex_oop), whose masks come
688 // from the usual MachNode/MachOper mechanism. Find a sample
689 // TailJump to extract these masks and put the correct masks into
690 // the tail_jump_rms array.
691 for( i=1; i < root->req(); i++ ) {
692 MachReturnNode *m = root->in(i)->as_MachReturn();
693 if( m->ideal_Opcode() == Op_TailJump ) {
694 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
695 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
696 break;
697 }
698 }
700 // Input RegMask array shared by all Halts
701 uint halt_edge_cnt = TypeFunc::Parms;
702 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
704 // Capture the return input masks into each exit flavor
705 for( i=1; i < root->req(); i++ ) {
706 MachReturnNode *exit = root->in(i)->as_MachReturn();
707 switch( exit->ideal_Opcode() ) {
708 case Op_Return : exit->_in_rms = ret_rms; break;
709 case Op_Rethrow : exit->_in_rms = reth_rms; break;
710 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
711 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
712 case Op_Halt : exit->_in_rms = halt_rms; break;
713 default : ShouldNotReachHere();
714 }
715 }
717 // Next unused projection number from Start.
718 int proj_cnt = C->tf()->domain()->cnt();
720 // Do all the save-on-entry registers. Make projections from Start for
721 // them, and give them a use at the exit points. To the allocator, they
722 // look like incoming register arguments.
723 for( i = 0; i < _last_Mach_Reg; i++ ) {
724 if( is_save_on_entry(i) ) {
726 // Add the save-on-entry to the mask array
727 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
728 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
729 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
730 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
731 // Halts need the SOE registers, but only in the stack as debug info.
732 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
733 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
735 Node *mproj;
737 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
738 // into a single RegD.
739 if( (i&1) == 0 &&
740 _register_save_type[i ] == Op_RegF &&
741 _register_save_type[i+1] == Op_RegF &&
742 is_save_on_entry(i+1) ) {
743 // Add other bit for double
744 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
745 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
746 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
747 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
748 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
749 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
750 proj_cnt += 2; // Skip 2 for doubles
751 }
752 else if( (i&1) == 1 && // Else check for high half of double
753 _register_save_type[i-1] == Op_RegF &&
754 _register_save_type[i ] == Op_RegF &&
755 is_save_on_entry(i-1) ) {
756 ret_rms [ ret_edge_cnt] = RegMask::Empty;
757 reth_rms [ reth_edge_cnt] = RegMask::Empty;
758 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
759 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
760 halt_rms [ halt_edge_cnt] = RegMask::Empty;
761 mproj = C->top();
762 }
763 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
764 // into a single RegL.
765 else if( (i&1) == 0 &&
766 _register_save_type[i ] == Op_RegI &&
767 _register_save_type[i+1] == Op_RegI &&
768 is_save_on_entry(i+1) ) {
769 // Add other bit for long
770 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
771 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
772 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
773 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
774 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
775 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
776 proj_cnt += 2; // Skip 2 for longs
777 }
778 else if( (i&1) == 1 && // Else check for high half of long
779 _register_save_type[i-1] == Op_RegI &&
780 _register_save_type[i ] == Op_RegI &&
781 is_save_on_entry(i-1) ) {
782 ret_rms [ ret_edge_cnt] = RegMask::Empty;
783 reth_rms [ reth_edge_cnt] = RegMask::Empty;
784 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
785 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
786 halt_rms [ halt_edge_cnt] = RegMask::Empty;
787 mproj = C->top();
788 } else {
789 // Make a projection for it off the Start
790 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
791 }
793 ret_edge_cnt ++;
794 reth_edge_cnt ++;
795 tail_call_edge_cnt ++;
796 tail_jump_edge_cnt ++;
797 halt_edge_cnt ++;
799 // Add a use of the SOE register to all exit paths
800 for( uint j=1; j < root->req(); j++ )
801 root->in(j)->add_req(mproj);
802 } // End of if a save-on-entry register
803 } // End of for all machine registers
804 }
806 //------------------------------init_spill_mask--------------------------------
807 void Matcher::init_spill_mask( Node *ret ) {
808 if( idealreg2regmask[Op_RegI] ) return; // One time only init
810 OptoReg::c_frame_pointer = c_frame_pointer();
811 c_frame_ptr_mask = c_frame_pointer();
812 #ifdef _LP64
813 // pointers are twice as big
814 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
815 #endif
817 // Start at OptoReg::stack0()
818 STACK_ONLY_mask.Clear();
819 OptoReg::Name init = OptoReg::stack2reg(0);
820 // STACK_ONLY_mask is all stack bits
821 OptoReg::Name i;
822 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
823 STACK_ONLY_mask.Insert(i);
824 // Also set the "infinite stack" bit.
825 STACK_ONLY_mask.set_AllStack();
827 // Copy the register names over into the shared world
828 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
829 // SharedInfo::regName[i] = regName[i];
830 // Handy RegMasks per machine register
831 mreg2regmask[i].Insert(i);
832 }
834 // Grab the Frame Pointer
835 Node *fp = ret->in(TypeFunc::FramePtr);
836 Node *mem = ret->in(TypeFunc::Memory);
837 const TypePtr* atp = TypePtr::BOTTOM;
838 // Share frame pointer while making spill ops
839 set_shared(fp);
841 // Compute generic short-offset Loads
842 #ifdef _LP64
843 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
844 #endif
845 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
846 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest,false));
847 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
848 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
849 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
850 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
851 spillD != NULL && spillP != NULL, "");
852 // Get the ADLC notion of the right regmask, for each basic type.
853 #ifdef _LP64
854 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
855 #endif
856 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
857 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
858 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
859 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
860 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
862 // Vector regmasks.
863 if (Matcher::vector_size_supported(T_BYTE,4)) {
864 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
865 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
866 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
867 }
868 if (Matcher::vector_size_supported(T_FLOAT,2)) {
869 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
870 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
871 }
872 if (Matcher::vector_size_supported(T_FLOAT,4)) {
873 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
874 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
875 }
876 if (Matcher::vector_size_supported(T_FLOAT,8)) {
877 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
878 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
879 }
880 }
882 #ifdef ASSERT
883 static void match_alias_type(Compile* C, Node* n, Node* m) {
884 if (!VerifyAliases) return; // do not go looking for trouble by default
885 const TypePtr* nat = n->adr_type();
886 const TypePtr* mat = m->adr_type();
887 int nidx = C->get_alias_index(nat);
888 int midx = C->get_alias_index(mat);
889 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
890 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
891 for (uint i = 1; i < n->req(); i++) {
892 Node* n1 = n->in(i);
893 const TypePtr* n1at = n1->adr_type();
894 if (n1at != NULL) {
895 nat = n1at;
896 nidx = C->get_alias_index(n1at);
897 }
898 }
899 }
900 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
901 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
902 switch (n->Opcode()) {
903 case Op_PrefetchRead:
904 case Op_PrefetchWrite:
905 case Op_PrefetchAllocation:
906 nidx = Compile::AliasIdxRaw;
907 nat = TypeRawPtr::BOTTOM;
908 break;
909 }
910 }
911 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
912 switch (n->Opcode()) {
913 case Op_ClearArray:
914 midx = Compile::AliasIdxRaw;
915 mat = TypeRawPtr::BOTTOM;
916 break;
917 }
918 }
919 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
920 switch (n->Opcode()) {
921 case Op_Return:
922 case Op_Rethrow:
923 case Op_Halt:
924 case Op_TailCall:
925 case Op_TailJump:
926 nidx = Compile::AliasIdxBot;
927 nat = TypePtr::BOTTOM;
928 break;
929 }
930 }
931 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
932 switch (n->Opcode()) {
933 case Op_StrComp:
934 case Op_StrEquals:
935 case Op_StrIndexOf:
936 case Op_AryEq:
937 case Op_MemBarVolatile:
938 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
939 case Op_EncodeISOArray:
940 nidx = Compile::AliasIdxTop;
941 nat = NULL;
942 break;
943 }
944 }
945 if (nidx != midx) {
946 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
947 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
948 n->dump();
949 m->dump();
950 }
951 assert(C->subsume_loads() && C->must_alias(nat, midx),
952 "must not lose alias info when matching");
953 }
954 }
955 #endif
958 //------------------------------MStack-----------------------------------------
959 // State and MStack class used in xform() and find_shared() iterative methods.
960 enum Node_State { Pre_Visit, // node has to be pre-visited
961 Visit, // visit node
962 Post_Visit, // post-visit node
963 Alt_Post_Visit // alternative post-visit path
964 };
966 class MStack: public Node_Stack {
967 public:
968 MStack(int size) : Node_Stack(size) { }
970 void push(Node *n, Node_State ns) {
971 Node_Stack::push(n, (uint)ns);
972 }
973 void push(Node *n, Node_State ns, Node *parent, int indx) {
974 ++_inode_top;
975 if ((_inode_top + 1) >= _inode_max) grow();
976 _inode_top->node = parent;
977 _inode_top->indx = (uint)indx;
978 ++_inode_top;
979 _inode_top->node = n;
980 _inode_top->indx = (uint)ns;
981 }
982 Node *parent() {
983 pop();
984 return node();
985 }
986 Node_State state() const {
987 return (Node_State)index();
988 }
989 void set_state(Node_State ns) {
990 set_index((uint)ns);
991 }
992 };
995 //------------------------------xform------------------------------------------
996 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
997 // Node in new-space. Given a new-space Node, recursively walk his children.
998 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
999 Node *Matcher::xform( Node *n, int max_stack ) {
1000 // Use one stack to keep both: child's node/state and parent's node/index
1001 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1002 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1004 while (mstack.is_nonempty()) {
1005 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1006 if (C->failing()) return NULL;
1007 n = mstack.node(); // Leave node on stack
1008 Node_State nstate = mstack.state();
1009 if (nstate == Visit) {
1010 mstack.set_state(Post_Visit);
1011 Node *oldn = n;
1012 // Old-space or new-space check
1013 if (!C->node_arena()->contains(n)) {
1014 // Old space!
1015 Node* m;
1016 if (has_new_node(n)) { // Not yet Label/Reduced
1017 m = new_node(n);
1018 } else {
1019 if (!is_dontcare(n)) { // Matcher can match this guy
1020 // Calls match special. They match alone with no children.
1021 // Their children, the incoming arguments, match normally.
1022 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1023 if (C->failing()) return NULL;
1024 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1025 } else { // Nothing the matcher cares about
1026 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections?
1027 // Convert to machine-dependent projection
1028 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1029 #ifdef ASSERT
1030 _new2old_map.map(m->_idx, n);
1031 #endif
1032 if (m->in(0) != NULL) // m might be top
1033 collect_null_checks(m, n);
1034 } else { // Else just a regular 'ol guy
1035 m = n->clone(); // So just clone into new-space
1036 #ifdef ASSERT
1037 _new2old_map.map(m->_idx, n);
1038 #endif
1039 // Def-Use edges will be added incrementally as Uses
1040 // of this node are matched.
1041 assert(m->outcnt() == 0, "no Uses of this clone yet");
1042 }
1043 }
1045 set_new_node(n, m); // Map old to new
1046 if (_old_node_note_array != NULL) {
1047 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1048 n->_idx);
1049 C->set_node_notes_at(m->_idx, nn);
1050 }
1051 debug_only(match_alias_type(C, n, m));
1052 }
1053 n = m; // n is now a new-space node
1054 mstack.set_node(n);
1055 }
1057 // New space!
1058 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1060 int i;
1061 // Put precedence edges on stack first (match them last).
1062 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1063 Node *m = oldn->in(i);
1064 if (m == NULL) break;
1065 // set -1 to call add_prec() instead of set_req() during Step1
1066 mstack.push(m, Visit, n, -1);
1067 }
1069 // For constant debug info, I'd rather have unmatched constants.
1070 int cnt = n->req();
1071 JVMState* jvms = n->jvms();
1072 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1074 // Now do only debug info. Clone constants rather than matching.
1075 // Constants are represented directly in the debug info without
1076 // the need for executable machine instructions.
1077 // Monitor boxes are also represented directly.
1078 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1079 Node *m = n->in(i); // Get input
1080 int op = m->Opcode();
1081 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1082 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1083 op == Op_ConF || op == Op_ConD || op == Op_ConL
1084 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1085 ) {
1086 m = m->clone();
1087 #ifdef ASSERT
1088 _new2old_map.map(m->_idx, n);
1089 #endif
1090 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1091 mstack.push(m->in(0), Visit, m, 0);
1092 } else {
1093 mstack.push(m, Visit, n, i);
1094 }
1095 }
1097 // And now walk his children, and convert his inputs to new-space.
1098 for( ; i >= 0; --i ) { // For all normal inputs do
1099 Node *m = n->in(i); // Get input
1100 if(m != NULL)
1101 mstack.push(m, Visit, n, i);
1102 }
1104 }
1105 else if (nstate == Post_Visit) {
1106 // Set xformed input
1107 Node *p = mstack.parent();
1108 if (p != NULL) { // root doesn't have parent
1109 int i = (int)mstack.index();
1110 if (i >= 0)
1111 p->set_req(i, n); // required input
1112 else if (i == -1)
1113 p->add_prec(n); // precedence input
1114 else
1115 ShouldNotReachHere();
1116 }
1117 mstack.pop(); // remove processed node from stack
1118 }
1119 else {
1120 ShouldNotReachHere();
1121 }
1122 } // while (mstack.is_nonempty())
1123 return n; // Return new-space Node
1124 }
1126 //------------------------------warp_outgoing_stk_arg------------------------
1127 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1128 // Convert outgoing argument location to a pre-biased stack offset
1129 if (reg->is_stack()) {
1130 OptoReg::Name warped = reg->reg2stack();
1131 // Adjust the stack slot offset to be the register number used
1132 // by the allocator.
1133 warped = OptoReg::add(begin_out_arg_area, warped);
1134 // Keep track of the largest numbered stack slot used for an arg.
1135 // Largest used slot per call-site indicates the amount of stack
1136 // that is killed by the call.
1137 if( warped >= out_arg_limit_per_call )
1138 out_arg_limit_per_call = OptoReg::add(warped,1);
1139 if (!RegMask::can_represent_arg(warped)) {
1140 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1141 return OptoReg::Bad;
1142 }
1143 return warped;
1144 }
1145 return OptoReg::as_OptoReg(reg);
1146 }
1149 //------------------------------match_sfpt-------------------------------------
1150 // Helper function to match call instructions. Calls match special.
1151 // They match alone with no children. Their children, the incoming
1152 // arguments, match normally.
1153 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1154 MachSafePointNode *msfpt = NULL;
1155 MachCallNode *mcall = NULL;
1156 uint cnt;
1157 // Split out case for SafePoint vs Call
1158 CallNode *call;
1159 const TypeTuple *domain;
1160 ciMethod* method = NULL;
1161 bool is_method_handle_invoke = false; // for special kill effects
1162 if( sfpt->is_Call() ) {
1163 call = sfpt->as_Call();
1164 domain = call->tf()->domain();
1165 cnt = domain->cnt();
1167 // Match just the call, nothing else
1168 MachNode *m = match_tree(call);
1169 if (C->failing()) return NULL;
1170 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1172 // Copy data from the Ideal SafePoint to the machine version
1173 mcall = m->as_MachCall();
1175 mcall->set_tf( call->tf());
1176 mcall->set_entry_point(call->entry_point());
1177 mcall->set_cnt( call->cnt());
1179 if( mcall->is_MachCallJava() ) {
1180 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1181 const CallJavaNode *call_java = call->as_CallJava();
1182 method = call_java->method();
1183 mcall_java->_method = method;
1184 mcall_java->_bci = call_java->_bci;
1185 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1186 is_method_handle_invoke = call_java->is_method_handle_invoke();
1187 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1188 if (is_method_handle_invoke) {
1189 C->set_has_method_handle_invokes(true);
1190 }
1191 if( mcall_java->is_MachCallStaticJava() )
1192 mcall_java->as_MachCallStaticJava()->_name =
1193 call_java->as_CallStaticJava()->_name;
1194 if( mcall_java->is_MachCallDynamicJava() )
1195 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1196 call_java->as_CallDynamicJava()->_vtable_index;
1197 }
1198 else if( mcall->is_MachCallRuntime() ) {
1199 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1200 }
1201 msfpt = mcall;
1202 }
1203 // This is a non-call safepoint
1204 else {
1205 call = NULL;
1206 domain = NULL;
1207 MachNode *mn = match_tree(sfpt);
1208 if (C->failing()) return NULL;
1209 msfpt = mn->as_MachSafePoint();
1210 cnt = TypeFunc::Parms;
1211 }
1213 // Advertise the correct memory effects (for anti-dependence computation).
1214 msfpt->set_adr_type(sfpt->adr_type());
1216 // Allocate a private array of RegMasks. These RegMasks are not shared.
1217 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1218 // Empty them all.
1219 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1221 // Do all the pre-defined non-Empty register masks
1222 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1223 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1225 // Place first outgoing argument can possibly be put.
1226 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1227 assert( is_even(begin_out_arg_area), "" );
1228 // Compute max outgoing register number per call site.
1229 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1230 // Calls to C may hammer extra stack slots above and beyond any arguments.
1231 // These are usually backing store for register arguments for varargs.
1232 if( call != NULL && call->is_CallRuntime() )
1233 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1236 // Do the normal argument list (parameters) register masks
1237 int argcnt = cnt - TypeFunc::Parms;
1238 if( argcnt > 0 ) { // Skip it all if we have no args
1239 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1240 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1241 int i;
1242 for( i = 0; i < argcnt; i++ ) {
1243 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1244 }
1245 // V-call to pick proper calling convention
1246 call->calling_convention( sig_bt, parm_regs, argcnt );
1248 #ifdef ASSERT
1249 // Sanity check users' calling convention. Really handy during
1250 // the initial porting effort. Fairly expensive otherwise.
1251 { for (int i = 0; i<argcnt; i++) {
1252 if( !parm_regs[i].first()->is_valid() &&
1253 !parm_regs[i].second()->is_valid() ) continue;
1254 VMReg reg1 = parm_regs[i].first();
1255 VMReg reg2 = parm_regs[i].second();
1256 for (int j = 0; j < i; j++) {
1257 if( !parm_regs[j].first()->is_valid() &&
1258 !parm_regs[j].second()->is_valid() ) continue;
1259 VMReg reg3 = parm_regs[j].first();
1260 VMReg reg4 = parm_regs[j].second();
1261 if( !reg1->is_valid() ) {
1262 assert( !reg2->is_valid(), "valid halvsies" );
1263 } else if( !reg3->is_valid() ) {
1264 assert( !reg4->is_valid(), "valid halvsies" );
1265 } else {
1266 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1267 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1268 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1269 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1270 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1271 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1272 }
1273 }
1274 }
1275 }
1276 #endif
1278 // Visit each argument. Compute its outgoing register mask.
1279 // Return results now can have 2 bits returned.
1280 // Compute max over all outgoing arguments both per call-site
1281 // and over the entire method.
1282 for( i = 0; i < argcnt; i++ ) {
1283 // Address of incoming argument mask to fill in
1284 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1285 if( !parm_regs[i].first()->is_valid() &&
1286 !parm_regs[i].second()->is_valid() ) {
1287 continue; // Avoid Halves
1288 }
1289 // Grab first register, adjust stack slots and insert in mask.
1290 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1291 if (OptoReg::is_valid(reg1))
1292 rm->Insert( reg1 );
1293 // Grab second register (if any), adjust stack slots and insert in mask.
1294 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1295 if (OptoReg::is_valid(reg2))
1296 rm->Insert( reg2 );
1297 } // End of for all arguments
1299 // Compute number of stack slots needed to restore stack in case of
1300 // Pascal-style argument popping.
1301 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1302 }
1304 // Compute the max stack slot killed by any call. These will not be
1305 // available for debug info, and will be used to adjust FIRST_STACK_mask
1306 // after all call sites have been visited.
1307 if( _out_arg_limit < out_arg_limit_per_call)
1308 _out_arg_limit = out_arg_limit_per_call;
1310 if (mcall) {
1311 // Kill the outgoing argument area, including any non-argument holes and
1312 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1313 // Since the max-per-method covers the max-per-call-site and debug info
1314 // is excluded on the max-per-method basis, debug info cannot land in
1315 // this killed area.
1316 uint r_cnt = mcall->tf()->range()->cnt();
1317 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1318 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1319 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1320 } else {
1321 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1322 proj->_rout.Insert(OptoReg::Name(i));
1323 }
1324 if (proj->_rout.is_NotEmpty()) {
1325 push_projection(proj);
1326 }
1327 }
1328 // Transfer the safepoint information from the call to the mcall
1329 // Move the JVMState list
1330 msfpt->set_jvms(sfpt->jvms());
1331 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1332 jvms->set_map(sfpt);
1333 }
1335 // Debug inputs begin just after the last incoming parameter
1336 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1337 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1339 // Move the OopMap
1340 msfpt->_oop_map = sfpt->_oop_map;
1342 // Add additional edges.
1343 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1344 // For these calls we can not add MachConstantBase in expand(), as the
1345 // ins are not complete then.
1346 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1347 if (msfpt->jvms() &&
1348 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1349 // We added an edge before jvms, so we must adapt the position of the ins.
1350 msfpt->jvms()->adapt_position(+1);
1351 }
1352 }
1354 // Registers killed by the call are set in the local scheduling pass
1355 // of Global Code Motion.
1356 return msfpt;
1357 }
1359 //---------------------------match_tree----------------------------------------
1360 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1361 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1362 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1363 // a Load's result RegMask for memoization in idealreg2regmask[]
1364 MachNode *Matcher::match_tree( const Node *n ) {
1365 assert( n->Opcode() != Op_Phi, "cannot match" );
1366 assert( !n->is_block_start(), "cannot match" );
1367 // Set the mark for all locally allocated State objects.
1368 // When this call returns, the _states_arena arena will be reset
1369 // freeing all State objects.
1370 ResourceMark rm( &_states_arena );
1372 LabelRootDepth = 0;
1374 // StoreNodes require their Memory input to match any LoadNodes
1375 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1376 #ifdef ASSERT
1377 Node* save_mem_node = _mem_node;
1378 _mem_node = n->is_Store() ? (Node*)n : NULL;
1379 #endif
1380 // State object for root node of match tree
1381 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1382 State *s = new (&_states_arena) State;
1383 s->_kids[0] = NULL;
1384 s->_kids[1] = NULL;
1385 s->_leaf = (Node*)n;
1386 // Label the input tree, allocating labels from top-level arena
1387 Label_Root( n, s, n->in(0), mem );
1388 if (C->failing()) return NULL;
1390 // The minimum cost match for the whole tree is found at the root State
1391 uint mincost = max_juint;
1392 uint cost = max_juint;
1393 uint i;
1394 for( i = 0; i < NUM_OPERANDS; i++ ) {
1395 if( s->valid(i) && // valid entry and
1396 s->_cost[i] < cost && // low cost and
1397 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1398 cost = s->_cost[mincost=i];
1399 }
1400 if (mincost == max_juint) {
1401 #ifndef PRODUCT
1402 tty->print("No matching rule for:");
1403 s->dump();
1404 #endif
1405 Matcher::soft_match_failure();
1406 return NULL;
1407 }
1408 // Reduce input tree based upon the state labels to machine Nodes
1409 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1410 #ifdef ASSERT
1411 _old2new_map.map(n->_idx, m);
1412 _new2old_map.map(m->_idx, (Node*)n);
1413 #endif
1415 // Add any Matcher-ignored edges
1416 uint cnt = n->req();
1417 uint start = 1;
1418 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1419 if( n->is_AddP() ) {
1420 assert( mem == (Node*)1, "" );
1421 start = AddPNode::Base+1;
1422 }
1423 for( i = start; i < cnt; i++ ) {
1424 if( !n->match_edge(i) ) {
1425 if( i < m->req() )
1426 m->ins_req( i, n->in(i) );
1427 else
1428 m->add_req( n->in(i) );
1429 }
1430 }
1432 debug_only( _mem_node = save_mem_node; )
1433 return m;
1434 }
1437 //------------------------------match_into_reg---------------------------------
1438 // Choose to either match this Node in a register or part of the current
1439 // match tree. Return true for requiring a register and false for matching
1440 // as part of the current match tree.
1441 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1443 const Type *t = m->bottom_type();
1445 if (t->singleton()) {
1446 // Never force constants into registers. Allow them to match as
1447 // constants or registers. Copies of the same value will share
1448 // the same register. See find_shared_node.
1449 return false;
1450 } else { // Not a constant
1451 // Stop recursion if they have different Controls.
1452 Node* m_control = m->in(0);
1453 // Control of load's memory can post-dominates load's control.
1454 // So use it since load can't float above its memory.
1455 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1456 if (control && m_control && control != m_control && control != mem_control) {
1458 // Actually, we can live with the most conservative control we
1459 // find, if it post-dominates the others. This allows us to
1460 // pick up load/op/store trees where the load can float a little
1461 // above the store.
1462 Node *x = control;
1463 const uint max_scan = 6; // Arbitrary scan cutoff
1464 uint j;
1465 for (j=0; j<max_scan; j++) {
1466 if (x->is_Region()) // Bail out at merge points
1467 return true;
1468 x = x->in(0);
1469 if (x == m_control) // Does 'control' post-dominate
1470 break; // m->in(0)? If so, we can use it
1471 if (x == mem_control) // Does 'control' post-dominate
1472 break; // mem_control? If so, we can use it
1473 }
1474 if (j == max_scan) // No post-domination before scan end?
1475 return true; // Then break the match tree up
1476 }
1477 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1478 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1479 // These are commonly used in address expressions and can
1480 // efficiently fold into them on X64 in some cases.
1481 return false;
1482 }
1483 }
1485 // Not forceable cloning. If shared, put it into a register.
1486 return shared;
1487 }
1490 //------------------------------Instruction Selection--------------------------
1491 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1492 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1493 // things the Matcher does not match (e.g., Memory), and things with different
1494 // Controls (hence forced into different blocks). We pass in the Control
1495 // selected for this entire State tree.
1497 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1498 // Store and the Load must have identical Memories (as well as identical
1499 // pointers). Since the Matcher does not have anything for Memory (and
1500 // does not handle DAGs), I have to match the Memory input myself. If the
1501 // Tree root is a Store, I require all Loads to have the identical memory.
1502 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1503 // Since Label_Root is a recursive function, its possible that we might run
1504 // out of stack space. See bugs 6272980 & 6227033 for more info.
1505 LabelRootDepth++;
1506 if (LabelRootDepth > MaxLabelRootDepth) {
1507 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1508 return NULL;
1509 }
1510 uint care = 0; // Edges matcher cares about
1511 uint cnt = n->req();
1512 uint i = 0;
1514 // Examine children for memory state
1515 // Can only subsume a child into your match-tree if that child's memory state
1516 // is not modified along the path to another input.
1517 // It is unsafe even if the other inputs are separate roots.
1518 Node *input_mem = NULL;
1519 for( i = 1; i < cnt; i++ ) {
1520 if( !n->match_edge(i) ) continue;
1521 Node *m = n->in(i); // Get ith input
1522 assert( m, "expect non-null children" );
1523 if( m->is_Load() ) {
1524 if( input_mem == NULL ) {
1525 input_mem = m->in(MemNode::Memory);
1526 } else if( input_mem != m->in(MemNode::Memory) ) {
1527 input_mem = NodeSentinel;
1528 }
1529 }
1530 }
1532 for( i = 1; i < cnt; i++ ){// For my children
1533 if( !n->match_edge(i) ) continue;
1534 Node *m = n->in(i); // Get ith input
1535 // Allocate states out of a private arena
1536 State *s = new (&_states_arena) State;
1537 svec->_kids[care++] = s;
1538 assert( care <= 2, "binary only for now" );
1540 // Recursively label the State tree.
1541 s->_kids[0] = NULL;
1542 s->_kids[1] = NULL;
1543 s->_leaf = m;
1545 // Check for leaves of the State Tree; things that cannot be a part of
1546 // the current tree. If it finds any, that value is matched as a
1547 // register operand. If not, then the normal matching is used.
1548 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1549 //
1550 // Stop recursion if this is LoadNode and the root of this tree is a
1551 // StoreNode and the load & store have different memories.
1552 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1553 // Can NOT include the match of a subtree when its memory state
1554 // is used by any of the other subtrees
1555 (input_mem == NodeSentinel) ) {
1556 #ifndef PRODUCT
1557 // Print when we exclude matching due to different memory states at input-loads
1558 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1559 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1560 tty->print_cr("invalid input_mem");
1561 }
1562 #endif
1563 // Switch to a register-only opcode; this value must be in a register
1564 // and cannot be subsumed as part of a larger instruction.
1565 s->DFA( m->ideal_reg(), m );
1567 } else {
1568 // If match tree has no control and we do, adopt it for entire tree
1569 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1570 control = m->in(0); // Pick up control
1571 // Else match as a normal part of the match tree.
1572 control = Label_Root(m,s,control,mem);
1573 if (C->failing()) return NULL;
1574 }
1575 }
1578 // Call DFA to match this node, and return
1579 svec->DFA( n->Opcode(), n );
1581 #ifdef ASSERT
1582 uint x;
1583 for( x = 0; x < _LAST_MACH_OPER; x++ )
1584 if( svec->valid(x) )
1585 break;
1587 if (x >= _LAST_MACH_OPER) {
1588 n->dump();
1589 svec->dump();
1590 assert( false, "bad AD file" );
1591 }
1592 #endif
1593 return control;
1594 }
1597 // Con nodes reduced using the same rule can share their MachNode
1598 // which reduces the number of copies of a constant in the final
1599 // program. The register allocator is free to split uses later to
1600 // split live ranges.
1601 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1602 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1604 // See if this Con has already been reduced using this rule.
1605 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1606 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1607 if (last != NULL && rule == last->rule()) {
1608 // Don't expect control change for DecodeN
1609 if (leaf->is_DecodeNarrowPtr())
1610 return last;
1611 // Get the new space root.
1612 Node* xroot = new_node(C->root());
1613 if (xroot == NULL) {
1614 // This shouldn't happen give the order of matching.
1615 return NULL;
1616 }
1618 // Shared constants need to have their control be root so they
1619 // can be scheduled properly.
1620 Node* control = last->in(0);
1621 if (control != xroot) {
1622 if (control == NULL || control == C->root()) {
1623 last->set_req(0, xroot);
1624 } else {
1625 assert(false, "unexpected control");
1626 return NULL;
1627 }
1628 }
1629 return last;
1630 }
1631 return NULL;
1632 }
1635 //------------------------------ReduceInst-------------------------------------
1636 // Reduce a State tree (with given Control) into a tree of MachNodes.
1637 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1638 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1639 // Each MachNode has a number of complicated MachOper operands; each
1640 // MachOper also covers a further tree of Ideal Nodes.
1642 // The root of the Ideal match tree is always an instruction, so we enter
1643 // the recursion here. After building the MachNode, we need to recurse
1644 // the tree checking for these cases:
1645 // (1) Child is an instruction -
1646 // Build the instruction (recursively), add it as an edge.
1647 // Build a simple operand (register) to hold the result of the instruction.
1648 // (2) Child is an interior part of an instruction -
1649 // Skip over it (do nothing)
1650 // (3) Child is the start of a operand -
1651 // Build the operand, place it inside the instruction
1652 // Call ReduceOper.
1653 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1654 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1656 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1657 if (shared_node != NULL) {
1658 return shared_node;
1659 }
1661 // Build the object to represent this state & prepare for recursive calls
1662 MachNode *mach = s->MachNodeGenerator( rule, C );
1663 guarantee(mach != NULL, "Missing MachNode");
1664 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1665 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1666 Node *leaf = s->_leaf;
1667 // Check for instruction or instruction chain rule
1668 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1669 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1670 "duplicating node that's already been matched");
1671 // Instruction
1672 mach->add_req( leaf->in(0) ); // Set initial control
1673 // Reduce interior of complex instruction
1674 ReduceInst_Interior( s, rule, mem, mach, 1 );
1675 } else {
1676 // Instruction chain rules are data-dependent on their inputs
1677 mach->add_req(0); // Set initial control to none
1678 ReduceInst_Chain_Rule( s, rule, mem, mach );
1679 }
1681 // If a Memory was used, insert a Memory edge
1682 if( mem != (Node*)1 ) {
1683 mach->ins_req(MemNode::Memory,mem);
1684 #ifdef ASSERT
1685 // Verify adr type after matching memory operation
1686 const MachOper* oper = mach->memory_operand();
1687 if (oper != NULL && oper != (MachOper*)-1) {
1688 // It has a unique memory operand. Find corresponding ideal mem node.
1689 Node* m = NULL;
1690 if (leaf->is_Mem()) {
1691 m = leaf;
1692 } else {
1693 m = _mem_node;
1694 assert(m != NULL && m->is_Mem(), "expecting memory node");
1695 }
1696 const Type* mach_at = mach->adr_type();
1697 // DecodeN node consumed by an address may have different type
1698 // then its input. Don't compare types for such case.
1699 if (m->adr_type() != mach_at &&
1700 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1701 m->in(MemNode::Address)->is_AddP() &&
1702 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1703 m->in(MemNode::Address)->is_AddP() &&
1704 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1705 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1706 mach_at = m->adr_type();
1707 }
1708 if (m->adr_type() != mach_at) {
1709 m->dump();
1710 tty->print_cr("mach:");
1711 mach->dump(1);
1712 }
1713 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1714 }
1715 #endif
1716 }
1718 // If the _leaf is an AddP, insert the base edge
1719 if (leaf->is_AddP()) {
1720 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1721 }
1723 uint number_of_projections_prior = number_of_projections();
1725 // Perform any 1-to-many expansions required
1726 MachNode *ex = mach->Expand(s, _projection_list, mem);
1727 if (ex != mach) {
1728 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1729 if( ex->in(1)->is_Con() )
1730 ex->in(1)->set_req(0, C->root());
1731 // Remove old node from the graph
1732 for( uint i=0; i<mach->req(); i++ ) {
1733 mach->set_req(i,NULL);
1734 }
1735 #ifdef ASSERT
1736 _new2old_map.map(ex->_idx, s->_leaf);
1737 #endif
1738 }
1740 // PhaseChaitin::fixup_spills will sometimes generate spill code
1741 // via the matcher. By the time, nodes have been wired into the CFG,
1742 // and any further nodes generated by expand rules will be left hanging
1743 // in space, and will not get emitted as output code. Catch this.
1744 // Also, catch any new register allocation constraints ("projections")
1745 // generated belatedly during spill code generation.
1746 if (_allocation_started) {
1747 guarantee(ex == mach, "no expand rules during spill generation");
1748 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1749 }
1751 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1752 // Record the con for sharing
1753 _shared_nodes.map(leaf->_idx, ex);
1754 }
1756 return ex;
1757 }
1759 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1760 // 'op' is what I am expecting to receive
1761 int op = _leftOp[rule];
1762 // Operand type to catch childs result
1763 // This is what my child will give me.
1764 int opnd_class_instance = s->_rule[op];
1765 // Choose between operand class or not.
1766 // This is what I will receive.
1767 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1768 // New rule for child. Chase operand classes to get the actual rule.
1769 int newrule = s->_rule[catch_op];
1771 if( newrule < NUM_OPERANDS ) {
1772 // Chain from operand or operand class, may be output of shared node
1773 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1774 "Bad AD file: Instruction chain rule must chain from operand");
1775 // Insert operand into array of operands for this instruction
1776 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1778 ReduceOper( s, newrule, mem, mach );
1779 } else {
1780 // Chain from the result of an instruction
1781 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1782 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1783 Node *mem1 = (Node*)1;
1784 debug_only(Node *save_mem_node = _mem_node;)
1785 mach->add_req( ReduceInst(s, newrule, mem1) );
1786 debug_only(_mem_node = save_mem_node;)
1787 }
1788 return;
1789 }
1792 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1793 if( s->_leaf->is_Load() ) {
1794 Node *mem2 = s->_leaf->in(MemNode::Memory);
1795 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1796 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1797 mem = mem2;
1798 }
1799 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1800 if( mach->in(0) == NULL )
1801 mach->set_req(0, s->_leaf->in(0));
1802 }
1804 // Now recursively walk the state tree & add operand list.
1805 for( uint i=0; i<2; i++ ) { // binary tree
1806 State *newstate = s->_kids[i];
1807 if( newstate == NULL ) break; // Might only have 1 child
1808 // 'op' is what I am expecting to receive
1809 int op;
1810 if( i == 0 ) {
1811 op = _leftOp[rule];
1812 } else {
1813 op = _rightOp[rule];
1814 }
1815 // Operand type to catch childs result
1816 // This is what my child will give me.
1817 int opnd_class_instance = newstate->_rule[op];
1818 // Choose between operand class or not.
1819 // This is what I will receive.
1820 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1821 // New rule for child. Chase operand classes to get the actual rule.
1822 int newrule = newstate->_rule[catch_op];
1824 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1825 // Operand/operandClass
1826 // Insert operand into array of operands for this instruction
1827 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1828 ReduceOper( newstate, newrule, mem, mach );
1830 } else { // Child is internal operand or new instruction
1831 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1832 // internal operand --> call ReduceInst_Interior
1833 // Interior of complex instruction. Do nothing but recurse.
1834 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1835 } else {
1836 // instruction --> call build operand( ) to catch result
1837 // --> ReduceInst( newrule )
1838 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1839 Node *mem1 = (Node*)1;
1840 debug_only(Node *save_mem_node = _mem_node;)
1841 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1842 debug_only(_mem_node = save_mem_node;)
1843 }
1844 }
1845 assert( mach->_opnds[num_opnds-1], "" );
1846 }
1847 return num_opnds;
1848 }
1850 // This routine walks the interior of possible complex operands.
1851 // At each point we check our children in the match tree:
1852 // (1) No children -
1853 // We are a leaf; add _leaf field as an input to the MachNode
1854 // (2) Child is an internal operand -
1855 // Skip over it ( do nothing )
1856 // (3) Child is an instruction -
1857 // Call ReduceInst recursively and
1858 // and instruction as an input to the MachNode
1859 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1860 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1861 State *kid = s->_kids[0];
1862 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1864 // Leaf? And not subsumed?
1865 if( kid == NULL && !_swallowed[rule] ) {
1866 mach->add_req( s->_leaf ); // Add leaf pointer
1867 return; // Bail out
1868 }
1870 if( s->_leaf->is_Load() ) {
1871 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1872 mem = s->_leaf->in(MemNode::Memory);
1873 debug_only(_mem_node = s->_leaf;)
1874 }
1875 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1876 if( !mach->in(0) )
1877 mach->set_req(0,s->_leaf->in(0));
1878 else {
1879 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1880 }
1881 }
1883 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1884 int newrule;
1885 if( i == 0)
1886 newrule = kid->_rule[_leftOp[rule]];
1887 else
1888 newrule = kid->_rule[_rightOp[rule]];
1890 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1891 // Internal operand; recurse but do nothing else
1892 ReduceOper( kid, newrule, mem, mach );
1894 } else { // Child is a new instruction
1895 // Reduce the instruction, and add a direct pointer from this
1896 // machine instruction to the newly reduced one.
1897 Node *mem1 = (Node*)1;
1898 debug_only(Node *save_mem_node = _mem_node;)
1899 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1900 debug_only(_mem_node = save_mem_node;)
1901 }
1902 }
1903 }
1906 // -------------------------------------------------------------------------
1907 // Java-Java calling convention
1908 // (what you use when Java calls Java)
1910 //------------------------------find_receiver----------------------------------
1911 // For a given signature, return the OptoReg for parameter 0.
1912 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1913 VMRegPair regs;
1914 BasicType sig_bt = T_OBJECT;
1915 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1916 // Return argument 0 register. In the LP64 build pointers
1917 // take 2 registers, but the VM wants only the 'main' name.
1918 return OptoReg::as_OptoReg(regs.first());
1919 }
1921 // This function identifies sub-graphs in which a 'load' node is
1922 // input to two different nodes, and such that it can be matched
1923 // with BMI instructions like blsi, blsr, etc.
1924 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1925 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1926 // refers to the same node.
1927 #ifdef X86
1928 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1929 // This is a temporary solution until we make DAGs expressible in ADL.
1930 template<typename ConType>
1931 class FusedPatternMatcher {
1932 Node* _op1_node;
1933 Node* _mop_node;
1934 int _con_op;
1936 static int match_next(Node* n, int next_op, int next_op_idx) {
1937 if (n->in(1) == NULL || n->in(2) == NULL) {
1938 return -1;
1939 }
1941 if (next_op_idx == -1) { // n is commutative, try rotations
1942 if (n->in(1)->Opcode() == next_op) {
1943 return 1;
1944 } else if (n->in(2)->Opcode() == next_op) {
1945 return 2;
1946 }
1947 } else {
1948 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1949 if (n->in(next_op_idx)->Opcode() == next_op) {
1950 return next_op_idx;
1951 }
1952 }
1953 return -1;
1954 }
1955 public:
1956 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1957 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1959 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1960 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1961 typename ConType::NativeType con_value) {
1962 if (_op1_node->Opcode() != op1) {
1963 return false;
1964 }
1965 if (_mop_node->outcnt() > 2) {
1966 return false;
1967 }
1968 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1969 if (op1_op2_idx == -1) {
1970 return false;
1971 }
1972 // Memory operation must be the other edge
1973 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1975 // Check that the mop node is really what we want
1976 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1977 Node *op2_node = _op1_node->in(op1_op2_idx);
1978 if (op2_node->outcnt() > 1) {
1979 return false;
1980 }
1981 assert(op2_node->Opcode() == op2, "Should be");
1982 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1983 if (op2_con_idx == -1) {
1984 return false;
1985 }
1986 // Memory operation must be the other edge
1987 int op2_mop_idx = (op2_con_idx & 1) + 1;
1988 // Check that the memory operation is the same node
1989 if (op2_node->in(op2_mop_idx) == _mop_node) {
1990 // Now check the constant
1991 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1992 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1993 return true;
1994 }
1995 }
1996 }
1997 return false;
1998 }
1999 };
2002 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2003 if (n != NULL && m != NULL) {
2004 if (m->Opcode() == Op_LoadI) {
2005 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2006 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2007 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2008 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2009 } else if (m->Opcode() == Op_LoadL) {
2010 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2011 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2012 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2013 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2014 }
2015 }
2016 return false;
2017 }
2018 #endif // X86
2020 // A method-klass-holder may be passed in the inline_cache_reg
2021 // and then expanded into the inline_cache_reg and a method_oop register
2022 // defined in ad_<arch>.cpp
2025 //------------------------------find_shared------------------------------------
2026 // Set bits if Node is shared or otherwise a root
2027 void Matcher::find_shared( Node *n ) {
2028 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2029 MStack mstack(C->live_nodes() * 2);
2030 // Mark nodes as address_visited if they are inputs to an address expression
2031 VectorSet address_visited(Thread::current()->resource_area());
2032 mstack.push(n, Visit); // Don't need to pre-visit root node
2033 while (mstack.is_nonempty()) {
2034 n = mstack.node(); // Leave node on stack
2035 Node_State nstate = mstack.state();
2036 uint nop = n->Opcode();
2037 if (nstate == Pre_Visit) {
2038 if (address_visited.test(n->_idx)) { // Visited in address already?
2039 // Flag as visited and shared now.
2040 set_visited(n);
2041 }
2042 if (is_visited(n)) { // Visited already?
2043 // Node is shared and has no reason to clone. Flag it as shared.
2044 // This causes it to match into a register for the sharing.
2045 set_shared(n); // Flag as shared and
2046 if (n->is_DecodeNarrowPtr()) {
2047 // Oop field/array element loads must be shared but since
2048 // they are shared through a DecodeN they may appear to have
2049 // a single use so force sharing here.
2050 set_shared(n->in(1));
2051 }
2052 mstack.pop(); // remove node from stack
2053 continue;
2054 }
2055 nstate = Visit; // Not already visited; so visit now
2056 }
2057 if (nstate == Visit) {
2058 mstack.set_state(Post_Visit);
2059 set_visited(n); // Flag as visited now
2060 bool mem_op = false;
2062 switch( nop ) { // Handle some opcodes special
2063 case Op_Phi: // Treat Phis as shared roots
2064 case Op_Parm:
2065 case Op_Proj: // All handled specially during matching
2066 case Op_SafePointScalarObject:
2067 set_shared(n);
2068 set_dontcare(n);
2069 break;
2070 case Op_If:
2071 case Op_CountedLoopEnd:
2072 mstack.set_state(Alt_Post_Visit); // Alternative way
2073 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2074 // with matching cmp/branch in 1 instruction. The Matcher needs the
2075 // Bool and CmpX side-by-side, because it can only get at constants
2076 // that are at the leaves of Match trees, and the Bool's condition acts
2077 // as a constant here.
2078 mstack.push(n->in(1), Visit); // Clone the Bool
2079 mstack.push(n->in(0), Pre_Visit); // Visit control input
2080 continue; // while (mstack.is_nonempty())
2081 case Op_ConvI2D: // These forms efficiently match with a prior
2082 case Op_ConvI2F: // Load but not a following Store
2083 if( n->in(1)->is_Load() && // Prior load
2084 n->outcnt() == 1 && // Not already shared
2085 n->unique_out()->is_Store() ) // Following store
2086 set_shared(n); // Force it to be a root
2087 break;
2088 case Op_ReverseBytesI:
2089 case Op_ReverseBytesL:
2090 if( n->in(1)->is_Load() && // Prior load
2091 n->outcnt() == 1 ) // Not already shared
2092 set_shared(n); // Force it to be a root
2093 break;
2094 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2095 case Op_IfFalse:
2096 case Op_IfTrue:
2097 case Op_MachProj:
2098 case Op_MergeMem:
2099 case Op_Catch:
2100 case Op_CatchProj:
2101 case Op_CProj:
2102 case Op_JumpProj:
2103 case Op_JProj:
2104 case Op_NeverBranch:
2105 set_dontcare(n);
2106 break;
2107 case Op_Jump:
2108 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2109 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2110 continue; // while (mstack.is_nonempty())
2111 case Op_StrComp:
2112 case Op_StrEquals:
2113 case Op_StrIndexOf:
2114 case Op_AryEq:
2115 case Op_EncodeISOArray:
2116 set_shared(n); // Force result into register (it will be anyways)
2117 break;
2118 case Op_ConP: { // Convert pointers above the centerline to NUL
2119 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2120 const TypePtr* tp = tn->type()->is_ptr();
2121 if (tp->_ptr == TypePtr::AnyNull) {
2122 tn->set_type(TypePtr::NULL_PTR);
2123 }
2124 break;
2125 }
2126 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2127 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2128 const TypePtr* tp = tn->type()->make_ptr();
2129 if (tp && tp->_ptr == TypePtr::AnyNull) {
2130 tn->set_type(TypeNarrowOop::NULL_PTR);
2131 }
2132 break;
2133 }
2134 case Op_Binary: // These are introduced in the Post_Visit state.
2135 ShouldNotReachHere();
2136 break;
2137 case Op_ClearArray:
2138 case Op_SafePoint:
2139 mem_op = true;
2140 break;
2141 default:
2142 if( n->is_Store() ) {
2143 // Do match stores, despite no ideal reg
2144 mem_op = true;
2145 break;
2146 }
2147 if( n->is_Mem() ) { // Loads and LoadStores
2148 mem_op = true;
2149 // Loads must be root of match tree due to prior load conflict
2150 if( C->subsume_loads() == false )
2151 set_shared(n);
2152 }
2153 // Fall into default case
2154 if( !n->ideal_reg() )
2155 set_dontcare(n); // Unmatchable Nodes
2156 } // end_switch
2158 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2159 Node *m = n->in(i); // Get ith input
2160 if (m == NULL) continue; // Ignore NULLs
2161 uint mop = m->Opcode();
2163 // Must clone all producers of flags, or we will not match correctly.
2164 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2165 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2166 // are also there, so we may match a float-branch to int-flags and
2167 // expect the allocator to haul the flags from the int-side to the
2168 // fp-side. No can do.
2169 if( _must_clone[mop] ) {
2170 mstack.push(m, Visit);
2171 continue; // for(int i = ...)
2172 }
2174 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2175 #ifdef X86
2176 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2177 mstack.push(m, Visit);
2178 continue;
2179 }
2180 #endif
2182 // Clone addressing expressions as they are "free" in memory access instructions
2183 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2184 // Some inputs for address expression are not put on stack
2185 // to avoid marking them as shared and forcing them into register
2186 // if they are used only in address expressions.
2187 // But they should be marked as shared if there are other uses
2188 // besides address expressions.
2190 Node *off = m->in(AddPNode::Offset);
2191 if( off->is_Con() &&
2192 // When there are other uses besides address expressions
2193 // put it on stack and mark as shared.
2194 !is_visited(m) ) {
2195 address_visited.test_set(m->_idx); // Flag as address_visited
2196 Node *adr = m->in(AddPNode::Address);
2198 // Intel, ARM and friends can handle 2 adds in addressing mode
2199 if( clone_shift_expressions && adr->is_AddP() &&
2200 // AtomicAdd is not an addressing expression.
2201 // Cheap to find it by looking for screwy base.
2202 !adr->in(AddPNode::Base)->is_top() &&
2203 // Are there other uses besides address expressions?
2204 !is_visited(adr) ) {
2205 address_visited.set(adr->_idx); // Flag as address_visited
2206 Node *shift = adr->in(AddPNode::Offset);
2207 // Check for shift by small constant as well
2208 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2209 shift->in(2)->get_int() <= 3 &&
2210 // Are there other uses besides address expressions?
2211 !is_visited(shift) ) {
2212 address_visited.set(shift->_idx); // Flag as address_visited
2213 mstack.push(shift->in(2), Visit);
2214 Node *conv = shift->in(1);
2215 #ifdef _LP64
2216 // Allow Matcher to match the rule which bypass
2217 // ConvI2L operation for an array index on LP64
2218 // if the index value is positive.
2219 if( conv->Opcode() == Op_ConvI2L &&
2220 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2221 // Are there other uses besides address expressions?
2222 !is_visited(conv) ) {
2223 address_visited.set(conv->_idx); // Flag as address_visited
2224 mstack.push(conv->in(1), Pre_Visit);
2225 } else
2226 #endif
2227 mstack.push(conv, Pre_Visit);
2228 } else {
2229 mstack.push(shift, Pre_Visit);
2230 }
2231 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2232 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2233 } else { // Sparc, Alpha, PPC and friends
2234 mstack.push(adr, Pre_Visit);
2235 }
2237 // Clone X+offset as it also folds into most addressing expressions
2238 mstack.push(off, Visit);
2239 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2240 continue; // for(int i = ...)
2241 } // if( off->is_Con() )
2242 } // if( mem_op &&
2243 mstack.push(m, Pre_Visit);
2244 } // for(int i = ...)
2245 }
2246 else if (nstate == Alt_Post_Visit) {
2247 mstack.pop(); // Remove node from stack
2248 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2249 // shared and all users of the Bool need to move the Cmp in parallel.
2250 // This leaves both the Bool and the If pointing at the Cmp. To
2251 // prevent the Matcher from trying to Match the Cmp along both paths
2252 // BoolNode::match_edge always returns a zero.
2254 // We reorder the Op_If in a pre-order manner, so we can visit without
2255 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2256 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2257 }
2258 else if (nstate == Post_Visit) {
2259 mstack.pop(); // Remove node from stack
2261 // Now hack a few special opcodes
2262 switch( n->Opcode() ) { // Handle some opcodes special
2263 case Op_StorePConditional:
2264 case Op_StoreIConditional:
2265 case Op_StoreLConditional:
2266 case Op_CompareAndSwapI:
2267 case Op_CompareAndSwapL:
2268 case Op_CompareAndSwapP:
2269 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2270 Node *newval = n->in(MemNode::ValueIn );
2271 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2272 Node *pair = new (C) BinaryNode( oldval, newval );
2273 n->set_req(MemNode::ValueIn,pair);
2274 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2275 break;
2276 }
2277 case Op_CMoveD: // Convert trinary to binary-tree
2278 case Op_CMoveF:
2279 case Op_CMoveI:
2280 case Op_CMoveL:
2281 case Op_CMoveN:
2282 case Op_CMoveP: {
2283 // Restructure into a binary tree for Matching. It's possible that
2284 // we could move this code up next to the graph reshaping for IfNodes
2285 // or vice-versa, but I do not want to debug this for Ladybird.
2286 // 10/2/2000 CNC.
2287 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1));
2288 n->set_req(1,pair1);
2289 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3));
2290 n->set_req(2,pair2);
2291 n->del_req(3);
2292 break;
2293 }
2294 case Op_LoopLimit: {
2295 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2));
2296 n->set_req(1,pair1);
2297 n->set_req(2,n->in(3));
2298 n->del_req(3);
2299 break;
2300 }
2301 case Op_StrEquals: {
2302 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2303 n->set_req(2,pair1);
2304 n->set_req(3,n->in(4));
2305 n->del_req(4);
2306 break;
2307 }
2308 case Op_StrComp:
2309 case Op_StrIndexOf: {
2310 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2311 n->set_req(2,pair1);
2312 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5));
2313 n->set_req(3,pair2);
2314 n->del_req(5);
2315 n->del_req(4);
2316 break;
2317 }
2318 case Op_EncodeISOArray: {
2319 // Restructure into a binary tree for Matching.
2320 Node* pair = new (C) BinaryNode(n->in(3), n->in(4));
2321 n->set_req(3, pair);
2322 n->del_req(4);
2323 break;
2324 }
2325 default:
2326 break;
2327 }
2328 }
2329 else {
2330 ShouldNotReachHere();
2331 }
2332 } // end of while (mstack.is_nonempty())
2333 }
2335 #ifdef ASSERT
2336 // machine-independent root to machine-dependent root
2337 void Matcher::dump_old2new_map() {
2338 _old2new_map.dump();
2339 }
2340 #endif
2342 //---------------------------collect_null_checks-------------------------------
2343 // Find null checks in the ideal graph; write a machine-specific node for
2344 // it. Used by later implicit-null-check handling. Actually collects
2345 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2346 // value being tested.
2347 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2348 Node *iff = proj->in(0);
2349 if( iff->Opcode() == Op_If ) {
2350 // During matching If's have Bool & Cmp side-by-side
2351 BoolNode *b = iff->in(1)->as_Bool();
2352 Node *cmp = iff->in(2);
2353 int opc = cmp->Opcode();
2354 if (opc != Op_CmpP && opc != Op_CmpN) return;
2356 const Type* ct = cmp->in(2)->bottom_type();
2357 if (ct == TypePtr::NULL_PTR ||
2358 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2360 bool push_it = false;
2361 if( proj->Opcode() == Op_IfTrue ) {
2362 extern int all_null_checks_found;
2363 all_null_checks_found++;
2364 if( b->_test._test == BoolTest::ne ) {
2365 push_it = true;
2366 }
2367 } else {
2368 assert( proj->Opcode() == Op_IfFalse, "" );
2369 if( b->_test._test == BoolTest::eq ) {
2370 push_it = true;
2371 }
2372 }
2373 if( push_it ) {
2374 _null_check_tests.push(proj);
2375 Node* val = cmp->in(1);
2376 #ifdef _LP64
2377 if (val->bottom_type()->isa_narrowoop() &&
2378 !Matcher::narrow_oop_use_complex_address()) {
2379 //
2380 // Look for DecodeN node which should be pinned to orig_proj.
2381 // On platforms (Sparc) which can not handle 2 adds
2382 // in addressing mode we have to keep a DecodeN node and
2383 // use it to do implicit NULL check in address.
2384 //
2385 // DecodeN node was pinned to non-null path (orig_proj) during
2386 // CastPP transformation in final_graph_reshaping_impl().
2387 //
2388 uint cnt = orig_proj->outcnt();
2389 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2390 Node* d = orig_proj->raw_out(i);
2391 if (d->is_DecodeN() && d->in(1) == val) {
2392 val = d;
2393 val->set_req(0, NULL); // Unpin now.
2394 // Mark this as special case to distinguish from
2395 // a regular case: CmpP(DecodeN, NULL).
2396 val = (Node*)(((intptr_t)val) | 1);
2397 break;
2398 }
2399 }
2400 }
2401 #endif
2402 _null_check_tests.push(val);
2403 }
2404 }
2405 }
2406 }
2408 //---------------------------validate_null_checks------------------------------
2409 // Its possible that the value being NULL checked is not the root of a match
2410 // tree. If so, I cannot use the value in an implicit null check.
2411 void Matcher::validate_null_checks( ) {
2412 uint cnt = _null_check_tests.size();
2413 for( uint i=0; i < cnt; i+=2 ) {
2414 Node *test = _null_check_tests[i];
2415 Node *val = _null_check_tests[i+1];
2416 bool is_decoden = ((intptr_t)val) & 1;
2417 val = (Node*)(((intptr_t)val) & ~1);
2418 if (has_new_node(val)) {
2419 Node* new_val = new_node(val);
2420 if (is_decoden) {
2421 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2422 // Note: new_val may have a control edge if
2423 // the original ideal node DecodeN was matched before
2424 // it was unpinned in Matcher::collect_null_checks().
2425 // Unpin the mach node and mark it.
2426 new_val->set_req(0, NULL);
2427 new_val = (Node*)(((intptr_t)new_val) | 1);
2428 }
2429 // Is a match-tree root, so replace with the matched value
2430 _null_check_tests.map(i+1, new_val);
2431 } else {
2432 // Yank from candidate list
2433 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2434 _null_check_tests.map(i,_null_check_tests[--cnt]);
2435 _null_check_tests.pop();
2436 _null_check_tests.pop();
2437 i-=2;
2438 }
2439 }
2440 }
2442 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2443 // atomic instruction acting as a store_load barrier without any
2444 // intervening volatile load, and thus we don't need a barrier here.
2445 // We retain the Node to act as a compiler ordering barrier.
2446 bool Matcher::post_store_load_barrier(const Node* vmb) {
2447 Compile* C = Compile::current();
2448 assert(vmb->is_MemBar(), "");
2449 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2450 const MemBarNode* membar = vmb->as_MemBar();
2452 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2453 Node* ctrl = NULL;
2454 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2455 Node* p = membar->fast_out(i);
2456 assert(p->is_Proj(), "only projections here");
2457 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2458 !C->node_arena()->contains(p)) { // Unmatched old-space only
2459 ctrl = p;
2460 break;
2461 }
2462 }
2463 assert((ctrl != NULL), "missing control projection");
2465 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2466 Node *x = ctrl->fast_out(j);
2467 int xop = x->Opcode();
2469 // We don't need current barrier if we see another or a lock
2470 // before seeing volatile load.
2471 //
2472 // Op_Fastunlock previously appeared in the Op_* list below.
2473 // With the advent of 1-0 lock operations we're no longer guaranteed
2474 // that a monitor exit operation contains a serializing instruction.
2476 if (xop == Op_MemBarVolatile ||
2477 xop == Op_CompareAndSwapL ||
2478 xop == Op_CompareAndSwapP ||
2479 xop == Op_CompareAndSwapN ||
2480 xop == Op_CompareAndSwapI) {
2481 return true;
2482 }
2484 // Op_FastLock previously appeared in the Op_* list above.
2485 // With biased locking we're no longer guaranteed that a monitor
2486 // enter operation contains a serializing instruction.
2487 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2488 return true;
2489 }
2491 if (x->is_MemBar()) {
2492 // We must retain this membar if there is an upcoming volatile
2493 // load, which will be followed by acquire membar.
2494 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2495 return false;
2496 } else {
2497 // For other kinds of barriers, check by pretending we
2498 // are them, and seeing if we can be removed.
2499 return post_store_load_barrier(x->as_MemBar());
2500 }
2501 }
2503 // probably not necessary to check for these
2504 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2505 return false;
2506 }
2507 }
2508 return false;
2509 }
2511 // Check whether node n is a branch to an uncommon trap that we could
2512 // optimize as test with very high branch costs in case of going to
2513 // the uncommon trap. The code must be able to be recompiled to use
2514 // a cheaper test.
2515 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2516 // Don't do it for natives, adapters, or runtime stubs
2517 Compile *C = Compile::current();
2518 if (!C->is_method_compilation()) return false;
2520 assert(n->is_If(), "You should only call this on if nodes.");
2521 IfNode *ifn = n->as_If();
2523 Node *ifFalse = NULL;
2524 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2525 if (ifn->fast_out(i)->is_IfFalse()) {
2526 ifFalse = ifn->fast_out(i);
2527 break;
2528 }
2529 }
2530 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2532 Node *reg = ifFalse;
2533 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2534 // Alternatively use visited set? Seems too expensive.
2535 while (reg != NULL && cnt > 0) {
2536 CallNode *call = NULL;
2537 RegionNode *nxt_reg = NULL;
2538 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2539 Node *o = reg->fast_out(i);
2540 if (o->is_Call()) {
2541 call = o->as_Call();
2542 }
2543 if (o->is_Region()) {
2544 nxt_reg = o->as_Region();
2545 }
2546 }
2548 if (call &&
2549 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2550 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2551 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2552 jint tr_con = trtype->is_int()->get_con();
2553 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2554 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2555 assert((int)reason < (int)BitsPerInt, "recode bit map");
2557 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2558 && action != Deoptimization::Action_none) {
2559 // This uncommon trap is sure to recompile, eventually.
2560 // When that happens, C->too_many_traps will prevent
2561 // this transformation from happening again.
2562 return true;
2563 }
2564 }
2565 }
2567 reg = nxt_reg;
2568 cnt--;
2569 }
2571 return false;
2572 }
2574 //=============================================================================
2575 //---------------------------State---------------------------------------------
2576 State::State(void) {
2577 #ifdef ASSERT
2578 _id = 0;
2579 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2580 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2581 //memset(_cost, -1, sizeof(_cost));
2582 //memset(_rule, -1, sizeof(_rule));
2583 #endif
2584 memset(_valid, 0, sizeof(_valid));
2585 }
2587 #ifdef ASSERT
2588 State::~State() {
2589 _id = 99;
2590 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2591 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2592 memset(_cost, -3, sizeof(_cost));
2593 memset(_rule, -3, sizeof(_rule));
2594 }
2595 #endif
2597 #ifndef PRODUCT
2598 //---------------------------dump----------------------------------------------
2599 void State::dump() {
2600 tty->print("\n");
2601 dump(0);
2602 }
2604 void State::dump(int depth) {
2605 for( int j = 0; j < depth; j++ )
2606 tty->print(" ");
2607 tty->print("--N: ");
2608 _leaf->dump();
2609 uint i;
2610 for( i = 0; i < _LAST_MACH_OPER; i++ )
2611 // Check for valid entry
2612 if( valid(i) ) {
2613 for( int j = 0; j < depth; j++ )
2614 tty->print(" ");
2615 assert(_cost[i] != max_juint, "cost must be a valid value");
2616 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2617 tty->print_cr("%s %d %s",
2618 ruleName[i], _cost[i], ruleName[_rule[i]] );
2619 }
2620 tty->cr();
2622 for( i=0; i<2; i++ )
2623 if( _kids[i] )
2624 _kids[i]->dump(depth+1);
2625 }
2626 #endif