Mon, 27 May 2013 12:56:34 +0200
8015428: Remove unused CDS support from StringTable
Summary: The string in StringTable is not used by CDS anymore. Remove the unnecessary code in preparation for 8015422: Large performance hit when the StringTable is walked twice in Parallel Scavenge
Reviewed-by: pliden, tschatzl, coleenp
1 /*
2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
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16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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23 */
25 #include "precompiled.hpp"
26 #include "libadt/vectset.hpp"
27 #include "memory/allocation.inline.hpp"
28 #include "opto/addnode.hpp"
29 #include "opto/c2compiler.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/cfgnode.hpp"
32 #include "opto/chaitin.hpp"
33 #include "opto/loopnode.hpp"
34 #include "opto/machnode.hpp"
36 //------------------------------Split--------------------------------------
37 // Walk the graph in RPO and for each lrg which spills, propagate reaching
38 // definitions. During propagation, split the live range around regions of
39 // High Register Pressure (HRP). If a Def is in a region of Low Register
40 // Pressure (LRP), it will not get spilled until we encounter a region of
41 // HRP between it and one of its uses. We will spill at the transition
42 // point between LRP and HRP. Uses in the HRP region will use the spilled
43 // Def. The first Use outside the HRP region will generate a SpillCopy to
44 // hoist the live range back up into a register, and all subsequent uses
45 // will use that new Def until another HRP region is encountered. Defs in
46 // HRP regions will get trailing SpillCopies to push the LRG down into the
47 // stack immediately.
48 //
49 // As a side effect, unlink from (hence make dead) coalesced copies.
50 //
52 static const char out_of_nodes[] = "out of nodes during split";
54 //------------------------------get_spillcopy_wide-----------------------------
55 // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the
56 // wide ideal-register spill-mask if possible. If the 'wide-mask' does
57 // not cover the input (or output), use the input (or output) mask instead.
58 Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) {
59 // If ideal reg doesn't exist we've got a bad schedule happening
60 // that is forcing us to spill something that isn't spillable.
61 // Bail rather than abort
62 int ireg = def->ideal_reg();
63 if( ireg == 0 || ireg == Op_RegFlags ) {
64 assert(false, "attempted to spill a non-spillable item");
65 C->record_method_not_compilable("attempted to spill a non-spillable item");
66 return NULL;
67 }
68 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
69 return NULL;
70 }
71 const RegMask *i_mask = &def->out_RegMask();
72 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
73 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
74 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
75 const RegMask *w_o_mask;
77 int num_regs = RegMask::num_registers(ireg);
78 bool is_vect = RegMask::is_vector(ireg);
79 if( w_mask->overlap( *o_mask ) && // Overlap AND
80 ((num_regs == 1) // Single use or aligned
81 || is_vect // or vector
82 || !is_vect && o_mask->is_aligned_pairs()) ) {
83 assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned");
84 // Don't come here for mis-aligned doubles
85 w_o_mask = w_mask;
86 } else { // wide ideal mask does not overlap with o_mask
87 // Mis-aligned doubles come here and XMM->FPR moves on x86.
88 w_o_mask = o_mask; // Must target desired registers
89 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use
90 // a reg-reg move or do I need a trip across register classes
91 // (and thus through memory)?
92 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
93 // Here we assume a trip through memory is required.
94 w_i_mask = &C->FIRST_STACK_mask();
95 }
96 return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask );
97 }
99 //------------------------------insert_proj------------------------------------
100 // Insert the spill at chosen location. Skip over any intervening Proj's or
101 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block
102 // instead. Update high-pressure indices. Create a new live range.
103 void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) {
104 // Skip intervening ProjNodes. Do not insert between a ProjNode and
105 // its definer.
106 while( i < b->_nodes.size() &&
107 (b->_nodes[i]->is_Proj() ||
108 b->_nodes[i]->is_Phi() ) )
109 i++;
111 // Do not insert between a call and his Catch
112 if( b->_nodes[i]->is_Catch() ) {
113 // Put the instruction at the top of the fall-thru block.
114 // Find the fall-thru projection
115 while( 1 ) {
116 const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj();
117 if( cp->_con == CatchProjNode::fall_through_index )
118 break;
119 }
120 int sidx = i - b->end_idx()-1;
121 b = b->_succs[sidx]; // Switch to successor block
122 i = 1; // Right at start of block
123 }
125 b->_nodes.insert(i,spill); // Insert node in block
126 _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect
127 // Adjust the point where we go hi-pressure
128 if( i <= b->_ihrp_index ) b->_ihrp_index++;
129 if( i <= b->_fhrp_index ) b->_fhrp_index++;
131 // Assign a new Live Range Number to the SpillCopy and grow
132 // the node->live range mapping.
133 new_lrg(spill,maxlrg);
134 }
136 //------------------------------split_DEF--------------------------------------
137 // There are four categories of Split; UP/DOWN x DEF/USE
138 // Only three of these really occur as DOWN/USE will always color
139 // Any Split with a DEF cannot CISC-Spill now. Thus we need
140 // two helper routines, one for Split DEFS (insert after instruction),
141 // one for Split USES (insert before instruction). DEF insertion
142 // happens inside Split, where the Leaveblock array is updated.
143 uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) {
144 #ifdef ASSERT
145 // Increment the counter for this lrg
146 splits.at_put(slidx, splits.at(slidx)+1);
147 #endif
148 // If we are spilling the memory op for an implicit null check, at the
149 // null check location (ie - null check is in HRP block) we need to do
150 // the null-check first, then spill-down in the following block.
151 // (The implicit_null_check function ensures the use is also dominated
152 // by the branch-not-taken block.)
153 Node *be = b->end();
154 if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) {
155 // Spill goes in the branch-not-taken block
156 b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue];
157 loc = 0; // Just past the Region
158 }
159 assert( loc >= 0, "must insert past block head" );
161 // Get a def-side SpillCopy
162 Node *spill = get_spillcopy_wide(def,NULL,0);
163 // Did we fail to split?, then bail
164 if (!spill) {
165 return 0;
166 }
168 // Insert the spill at chosen location
169 insert_proj( b, loc+1, spill, maxlrg++);
171 // Insert new node into Reaches array
172 Reachblock[slidx] = spill;
173 // Update debug list of reaching down definitions by adding this one
174 debug_defs[slidx] = spill;
176 // return updated count of live ranges
177 return maxlrg;
178 }
180 //------------------------------split_USE--------------------------------------
181 // Splits at uses can involve redeffing the LRG, so no CISC Spilling there.
182 // Debug uses want to know if def is already stack enabled.
183 uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) {
184 #ifdef ASSERT
185 // Increment the counter for this lrg
186 splits.at_put(slidx, splits.at(slidx)+1);
187 #endif
189 // Some setup stuff for handling debug node uses
190 JVMState* jvms = use->jvms();
191 uint debug_start = jvms ? jvms->debug_start() : 999999;
192 uint debug_end = jvms ? jvms->debug_end() : 999999;
194 //-------------------------------------------
195 // Check for use of debug info
196 if (useidx >= debug_start && useidx < debug_end) {
197 // Actually it's perfectly legal for constant debug info to appear
198 // just unlikely. In this case the optimizer left a ConI of a 4
199 // as both inputs to a Phi with only a debug use. It's a single-def
200 // live range of a rematerializable value. The live range spills,
201 // rematerializes and now the ConI directly feeds into the debug info.
202 // assert(!def->is_Con(), "constant debug info already constructed directly");
204 // Special split handling for Debug Info
205 // If DEF is DOWN, just hook the edge and return
206 // If DEF is UP, Split it DOWN for this USE.
207 if( def->is_Mach() ) {
208 if( def_down ) {
209 // DEF is DOWN, so connect USE directly to the DEF
210 use->set_req(useidx, def);
211 } else {
212 // Block and index where the use occurs.
213 Block *b = _cfg._bbs[use->_idx];
214 // Put the clone just prior to use
215 int bindex = b->find_node(use);
216 // DEF is UP, so must copy it DOWN and hook in USE
217 // Insert SpillCopy before the USE, which uses DEF as its input,
218 // and defs a new live range, which is used by this node.
219 Node *spill = get_spillcopy_wide(def,use,useidx);
220 // did we fail to split?
221 if (!spill) {
222 // Bail
223 return 0;
224 }
225 // insert into basic block
226 insert_proj( b, bindex, spill, maxlrg++ );
227 // Use the new split
228 use->set_req(useidx,spill);
229 }
230 // No further split handling needed for this use
231 return maxlrg;
232 } // End special splitting for debug info live range
233 } // If debug info
235 // CISC-SPILLING
236 // Finally, check to see if USE is CISC-Spillable, and if so,
237 // gather_lrg_masks will add the flags bit to its mask, and
238 // no use side copy is needed. This frees up the live range
239 // register choices without causing copy coalescing, etc.
240 if( UseCISCSpill && cisc_sp ) {
241 int inp = use->cisc_operand();
242 if( inp != AdlcVMDeps::Not_cisc_spillable )
243 // Convert operand number to edge index number
244 inp = use->as_Mach()->operand_index(inp);
245 if( inp == (int)useidx ) {
246 use->set_req(useidx, def);
247 #ifndef PRODUCT
248 if( TraceCISCSpill ) {
249 tty->print(" set_split: ");
250 use->dump();
251 }
252 #endif
253 return maxlrg;
254 }
255 }
257 //-------------------------------------------
258 // Insert a Copy before the use
260 // Block and index where the use occurs.
261 int bindex;
262 // Phi input spill-copys belong at the end of the prior block
263 if( use->is_Phi() ) {
264 b = _cfg._bbs[b->pred(useidx)->_idx];
265 bindex = b->end_idx();
266 } else {
267 // Put the clone just prior to use
268 bindex = b->find_node(use);
269 }
271 Node *spill = get_spillcopy_wide( def, use, useidx );
272 if( !spill ) return 0; // Bailed out
273 // Insert SpillCopy before the USE, which uses the reaching DEF as
274 // its input, and defs a new live range, which is used by this node.
275 insert_proj( b, bindex, spill, maxlrg++ );
276 // Use the spill/clone
277 use->set_req(useidx,spill);
279 // return updated live range count
280 return maxlrg;
281 }
283 //------------------------------clone_node----------------------------
284 // Clone node with anti dependence check.
285 Node* clone_node(Node* def, Block *b, Compile* C) {
286 if (def->needs_anti_dependence_check()) {
287 #ifdef ASSERT
288 if (Verbose) {
289 tty->print_cr("RA attempts to clone node with anti_dependence:");
290 def->dump(-1); tty->cr();
291 tty->print_cr("into block:");
292 b->dump();
293 }
294 #endif
295 if (C->subsume_loads() == true && !C->failing()) {
296 // Retry with subsume_loads == false
297 // If this is the first failure, the sentinel string will "stick"
298 // to the Compile object, and the C2Compiler will see it and retry.
299 C->record_failure(C2Compiler::retry_no_subsuming_loads());
300 } else {
301 // Bailout without retry
302 C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence");
303 }
304 return 0;
305 }
306 return def->clone();
307 }
309 //------------------------------split_Rematerialize----------------------------
310 // Clone a local copy of the def.
311 Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) {
312 // The input live ranges will be stretched to the site of the new
313 // instruction. They might be stretched past a def and will thus
314 // have the old and new values of the same live range alive at the
315 // same time - a definite no-no. Split out private copies of
316 // the inputs.
317 if( def->req() > 1 ) {
318 for( uint i = 1; i < def->req(); i++ ) {
319 Node *in = def->in(i);
320 // Check for single-def (LRG cannot redefined)
321 uint lidx = _lrg_map.live_range_id(in);
322 if (lidx >= _lrg_map.max_lrg_id()) {
323 continue; // Value is a recent spill-copy
324 }
325 if (lrgs(lidx).is_singledef()) {
326 continue;
327 }
329 Block *b_def = _cfg._bbs[def->_idx];
330 int idx_def = b_def->find_node(def);
331 Node *in_spill = get_spillcopy_wide( in, def, i );
332 if( !in_spill ) return 0; // Bailed out
333 insert_proj(b_def,idx_def,in_spill,maxlrg++);
334 if( b_def == b )
335 insidx++;
336 def->set_req(i,in_spill);
337 }
338 }
340 Node *spill = clone_node(def, b, C);
341 if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
342 // Check when generating nodes
343 return 0;
344 }
346 // See if any inputs are currently being spilled, and take the
347 // latest copy of spilled inputs.
348 if( spill->req() > 1 ) {
349 for( uint i = 1; i < spill->req(); i++ ) {
350 Node *in = spill->in(i);
351 uint lidx = _lrg_map.find_id(in);
353 // Walk backwards thru spill copy node intermediates
354 if (walkThru) {
355 while (in->is_SpillCopy() && lidx >= _lrg_map.max_lrg_id()) {
356 in = in->in(1);
357 lidx = _lrg_map.find_id(in);
358 }
360 if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).is_multidef()) {
361 // walkThru found a multidef LRG, which is unsafe to use, so
362 // just keep the original def used in the clone.
363 in = spill->in(i);
364 lidx = _lrg_map.find_id(in);
365 }
366 }
368 if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).reg() >= LRG::SPILL_REG) {
369 Node *rdef = Reachblock[lrg2reach[lidx]];
370 if (rdef) {
371 spill->set_req(i, rdef);
372 }
373 }
374 }
375 }
378 assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" );
379 // Rematerialized op is def->spilled+1
380 set_was_spilled(spill);
381 if( _spilled_once.test(def->_idx) )
382 set_was_spilled(spill);
384 insert_proj( b, insidx, spill, maxlrg++ );
385 #ifdef ASSERT
386 // Increment the counter for this lrg
387 splits.at_put(slidx, splits.at(slidx)+1);
388 #endif
389 // See if the cloned def kills any flags, and copy those kills as well
390 uint i = insidx+1;
391 if( clone_projs( b, i, def, spill, maxlrg) ) {
392 // Adjust the point where we go hi-pressure
393 if( i <= b->_ihrp_index ) b->_ihrp_index++;
394 if( i <= b->_fhrp_index ) b->_fhrp_index++;
395 }
397 return spill;
398 }
400 //------------------------------is_high_pressure-------------------------------
401 // Function to compute whether or not this live range is "high pressure"
402 // in this block - whether it spills eagerly or not.
403 bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) {
404 if( lrg->_was_spilled1 ) return true;
405 // Forced spilling due to conflict? Then split only at binding uses
406 // or defs, not for supposed capacity problems.
407 // CNC - Turned off 7/8/99, causes too much spilling
408 // if( lrg->_is_bound ) return false;
410 // Use float pressure numbers for vectors.
411 bool is_float_or_vector = lrg->_is_float || lrg->_is_vector;
412 // Not yet reached the high-pressure cutoff point, so low pressure
413 uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index;
414 if( insidx < hrp_idx ) return false;
415 // Register pressure for the block as a whole depends on reg class
416 int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure;
417 // Bound live ranges will split at the binding points first;
418 // Intermediate splits should assume the live range's register set
419 // got "freed up" and that num_regs will become INT_PRESSURE.
420 int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE;
421 // Effective register pressure limit.
422 int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs())
423 ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres;
424 // High pressure if block pressure requires more register freedom
425 // than live range has.
426 return block_pres >= lrg_pres;
427 }
430 //------------------------------prompt_use---------------------------------
431 // True if lidx is used before any real register is def'd in the block
432 bool PhaseChaitin::prompt_use( Block *b, uint lidx ) {
433 if (lrgs(lidx)._was_spilled2) {
434 return false;
435 }
437 // Scan block for 1st use.
438 for( uint i = 1; i <= b->end_idx(); i++ ) {
439 Node *n = b->_nodes[i];
440 // Ignore PHI use, these can be up or down
441 if (n->is_Phi()) {
442 continue;
443 }
444 for (uint j = 1; j < n->req(); j++) {
445 if (_lrg_map.find_id(n->in(j)) == lidx) {
446 return true; // Found 1st use!
447 }
448 }
449 if (n->out_RegMask().is_NotEmpty()) {
450 return false;
451 }
452 }
453 return false;
454 }
456 //------------------------------Split--------------------------------------
457 //----------Split Routine----------
458 // ***** NEW SPLITTING HEURISTIC *****
459 // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there.
460 // Else, no split unless there is a HRP block between a DEF and
461 // one of its uses, and then split at the HRP block.
462 //
463 // USES: If USE is in HRP, split at use to leave main LRG on stack.
464 // Else, hoist LRG back up to register only (ie - split is also DEF)
465 // We will compute a new maxlrg as we go
466 uint PhaseChaitin::Split(uint maxlrg, ResourceArea* split_arena) {
467 NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); )
469 // Free thread local resources used by this method on exit.
470 ResourceMark rm(split_arena);
472 uint bidx, pidx, slidx, insidx, inpidx, twoidx;
473 uint non_phi = 1, spill_cnt = 0;
474 Node **Reachblock;
475 Node *n1, *n2, *n3;
476 Node_List *defs,*phis;
477 bool *UPblock;
478 bool u1, u2, u3;
479 Block *b, *pred;
480 PhiNode *phi;
481 GrowableArray<uint> lidxs(split_arena, maxlrg, 0, 0);
483 // Array of counters to count splits per live range
484 GrowableArray<uint> splits(split_arena, maxlrg, 0, 0);
486 #define NEW_SPLIT_ARRAY(type, size)\
487 (type*) split_arena->allocate_bytes((size) * sizeof(type))
489 //----------Setup Code----------
490 // Create a convenient mapping from lrg numbers to reaches/leaves indices
491 uint *lrg2reach = NEW_SPLIT_ARRAY(uint, maxlrg);
492 // Keep track of DEFS & Phis for later passes
493 defs = new Node_List();
494 phis = new Node_List();
495 // Gather info on which LRG's are spilling, and build maps
496 for (bidx = 1; bidx < maxlrg; bidx++) {
497 if (lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG) {
498 assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color");
499 lrg2reach[bidx] = spill_cnt;
500 spill_cnt++;
501 lidxs.append(bidx);
502 #ifdef ASSERT
503 // Initialize the split counts to zero
504 splits.append(0);
505 #endif
506 #ifndef PRODUCT
507 if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 )
508 tty->print_cr("Warning, 2nd spill of L%d",bidx);
509 #endif
510 }
511 }
513 // Create side arrays for propagating reaching defs info.
514 // Each block needs a node pointer for each spilling live range for the
515 // Def which is live into the block. Phi nodes handle multiple input
516 // Defs by querying the output of their predecessor blocks and resolving
517 // them to a single Def at the phi. The pointer is updated for each
518 // Def in the block, and then becomes the output for the block when
519 // processing of the block is complete. We also need to track whether
520 // a Def is UP or DOWN. UP means that it should get a register (ie -
521 // it is always in LRP regions), and DOWN means that it is probably
522 // on the stack (ie - it crosses HRP regions).
523 Node ***Reaches = NEW_SPLIT_ARRAY( Node**, _cfg._num_blocks+1 );
524 bool **UP = NEW_SPLIT_ARRAY( bool*, _cfg._num_blocks+1 );
525 Node **debug_defs = NEW_SPLIT_ARRAY( Node*, spill_cnt );
526 VectorSet **UP_entry= NEW_SPLIT_ARRAY( VectorSet*, spill_cnt );
528 // Initialize Reaches & UP
529 for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) {
530 Reaches[bidx] = NEW_SPLIT_ARRAY( Node*, spill_cnt );
531 UP[bidx] = NEW_SPLIT_ARRAY( bool, spill_cnt );
532 Node **Reachblock = Reaches[bidx];
533 bool *UPblock = UP[bidx];
534 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
535 UPblock[slidx] = true; // Assume they start in registers
536 Reachblock[slidx] = NULL; // Assume that no def is present
537 }
538 }
540 #undef NEW_SPLIT_ARRAY
542 // Initialize to array of empty vectorsets
543 for( slidx = 0; slidx < spill_cnt; slidx++ )
544 UP_entry[slidx] = new VectorSet(split_arena);
546 //----------PASS 1----------
547 //----------Propagation & Node Insertion Code----------
548 // Walk the Blocks in RPO for DEF & USE info
549 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) {
551 if (C->check_node_count(spill_cnt, out_of_nodes)) {
552 return 0;
553 }
555 b = _cfg._blocks[bidx];
556 // Reaches & UP arrays for this block
557 Reachblock = Reaches[b->_pre_order];
558 UPblock = UP[b->_pre_order];
559 // Reset counter of start of non-Phi nodes in block
560 non_phi = 1;
561 //----------Block Entry Handling----------
562 // Check for need to insert a new phi
563 // Cycle through this block's predecessors, collecting Reaches
564 // info for each spilled LRG. If they are identical, no phi is
565 // needed. If they differ, check for a phi, and insert if missing,
566 // or update edges if present. Set current block's Reaches set to
567 // be either the phi's or the reaching def, as appropriate.
568 // If no Phi is needed, check if the LRG needs to spill on entry
569 // to the block due to HRP.
570 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
571 // Grab the live range number
572 uint lidx = lidxs.at(slidx);
573 // Do not bother splitting or putting in Phis for single-def
574 // rematerialized live ranges. This happens alot to constants
575 // with long live ranges.
576 if( lrgs(lidx).is_singledef() &&
577 lrgs(lidx)._def->rematerialize() ) {
578 // reset the Reaches & UP entries
579 Reachblock[slidx] = lrgs(lidx)._def;
580 UPblock[slidx] = true;
581 // Record following instruction in case 'n' rematerializes and
582 // kills flags
583 Block *pred1 = _cfg._bbs[b->pred(1)->_idx];
584 continue;
585 }
587 // Initialize needs_phi and needs_split
588 bool needs_phi = false;
589 bool needs_split = false;
590 bool has_phi = false;
591 // Walk the predecessor blocks to check inputs for that live range
592 // Grab predecessor block header
593 n1 = b->pred(1);
594 // Grab the appropriate reaching def info for inpidx
595 pred = _cfg._bbs[n1->_idx];
596 pidx = pred->_pre_order;
597 Node **Ltmp = Reaches[pidx];
598 bool *Utmp = UP[pidx];
599 n1 = Ltmp[slidx];
600 u1 = Utmp[slidx];
601 // Initialize node for saving type info
602 n3 = n1;
603 u3 = u1;
605 // Compare inputs to see if a Phi is needed
606 for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) {
607 // Grab predecessor block headers
608 n2 = b->pred(inpidx);
609 // Grab the appropriate reaching def info for inpidx
610 pred = _cfg._bbs[n2->_idx];
611 pidx = pred->_pre_order;
612 Ltmp = Reaches[pidx];
613 Utmp = UP[pidx];
614 n2 = Ltmp[slidx];
615 u2 = Utmp[slidx];
616 // For each LRG, decide if a phi is necessary
617 if( n1 != n2 ) {
618 needs_phi = true;
619 }
620 // See if the phi has mismatched inputs, UP vs. DOWN
621 if( n1 && n2 && (u1 != u2) ) {
622 needs_split = true;
623 }
624 // Move n2/u2 to n1/u1 for next iteration
625 n1 = n2;
626 u1 = u2;
627 // Preserve a non-NULL predecessor for later type referencing
628 if( (n3 == NULL) && (n2 != NULL) ){
629 n3 = n2;
630 u3 = u2;
631 }
632 } // End for all potential Phi inputs
634 // check block for appropriate phinode & update edges
635 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
636 n1 = b->_nodes[insidx];
637 // bail if this is not a phi
638 phi = n1->is_Phi() ? n1->as_Phi() : NULL;
639 if( phi == NULL ) {
640 // Keep track of index of first non-PhiNode instruction in block
641 non_phi = insidx;
642 // break out of the for loop as we have handled all phi nodes
643 break;
644 }
645 // must be looking at a phi
646 if (_lrg_map.find_id(n1) == lidxs.at(slidx)) {
647 // found the necessary phi
648 needs_phi = false;
649 has_phi = true;
650 // initialize the Reaches entry for this LRG
651 Reachblock[slidx] = phi;
652 break;
653 } // end if found correct phi
654 } // end for all phi's
656 // If a phi is needed or exist, check for it
657 if( needs_phi || has_phi ) {
658 // add new phinode if one not already found
659 if( needs_phi ) {
660 // create a new phi node and insert it into the block
661 // type is taken from left over pointer to a predecessor
662 assert(n3,"No non-NULL reaching DEF for a Phi");
663 phi = new (C) PhiNode(b->head(), n3->bottom_type());
664 // initialize the Reaches entry for this LRG
665 Reachblock[slidx] = phi;
667 // add node to block & node_to_block mapping
668 insert_proj(b, insidx++, phi, maxlrg++);
669 non_phi++;
670 // Reset new phi's mapping to be the spilling live range
671 _lrg_map.map(phi->_idx, lidx);
672 assert(_lrg_map.find_id(phi) == lidx, "Bad update on Union-Find mapping");
673 } // end if not found correct phi
674 // Here you have either found or created the Phi, so record it
675 assert(phi != NULL,"Must have a Phi Node here");
676 phis->push(phi);
677 // PhiNodes should either force the LRG UP or DOWN depending
678 // on its inputs and the register pressure in the Phi's block.
679 UPblock[slidx] = true; // Assume new DEF is UP
680 // If entering a high-pressure area with no immediate use,
681 // assume Phi is DOWN
682 if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) )
683 UPblock[slidx] = false;
684 // If we are not split up/down and all inputs are down, then we
685 // are down
686 if( !needs_split && !u3 )
687 UPblock[slidx] = false;
688 } // end if phi is needed
690 // Do not need a phi, so grab the reaching DEF
691 else {
692 // Grab predecessor block header
693 n1 = b->pred(1);
694 // Grab the appropriate reaching def info for k
695 pred = _cfg._bbs[n1->_idx];
696 pidx = pred->_pre_order;
697 Node **Ltmp = Reaches[pidx];
698 bool *Utmp = UP[pidx];
699 // reset the Reaches & UP entries
700 Reachblock[slidx] = Ltmp[slidx];
701 UPblock[slidx] = Utmp[slidx];
702 } // end else no Phi is needed
703 } // end for all spilling live ranges
704 // DEBUG
705 #ifndef PRODUCT
706 if(trace_spilling()) {
707 tty->print("/`\nBlock %d: ", b->_pre_order);
708 tty->print("Reaching Definitions after Phi handling\n");
709 for( uint x = 0; x < spill_cnt; x++ ) {
710 tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]);
711 if( Reachblock[x] )
712 Reachblock[x]->dump();
713 else
714 tty->print("Undefined\n");
715 }
716 }
717 #endif
719 //----------Non-Phi Node Splitting----------
720 // Since phi-nodes have now been handled, the Reachblock array for this
721 // block is initialized with the correct starting value for the defs which
722 // reach non-phi instructions in this block. Thus, process non-phi
723 // instructions normally, inserting SpillCopy nodes for all spill
724 // locations.
726 // Memoize any DOWN reaching definitions for use as DEBUG info
727 for( insidx = 0; insidx < spill_cnt; insidx++ ) {
728 debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx];
729 if( UPblock[insidx] ) // Memoize UP decision at block start
730 UP_entry[insidx]->set( b->_pre_order );
731 }
733 //----------Walk Instructions in the Block and Split----------
734 // For all non-phi instructions in the block
735 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
736 Node *n = b->_nodes[insidx];
737 // Find the defining Node's live range index
738 uint defidx = _lrg_map.find_id(n);
739 uint cnt = n->req();
741 if (n->is_Phi()) {
742 // Skip phi nodes after removing dead copies.
743 if (defidx < _lrg_map.max_lrg_id()) {
744 // Check for useless Phis. These appear if we spill, then
745 // coalesce away copies. Dont touch Phis in spilling live
746 // ranges; they are busy getting modifed in this pass.
747 if( lrgs(defidx).reg() < LRG::SPILL_REG ) {
748 uint i;
749 Node *u = NULL;
750 // Look for the Phi merging 2 unique inputs
751 for( i = 1; i < cnt; i++ ) {
752 // Ignore repeats and self
753 if( n->in(i) != u && n->in(i) != n ) {
754 // Found a unique input
755 if( u != NULL ) // If it's the 2nd, bail out
756 break;
757 u = n->in(i); // Else record it
758 }
759 }
760 assert( u, "at least 1 valid input expected" );
761 if (i >= cnt) { // Found one unique input
762 assert(_lrg_map.find_id(n) == _lrg_map.find_id(u), "should be the same lrg");
763 n->replace_by(u); // Then replace with unique input
764 n->disconnect_inputs(NULL, C);
765 b->_nodes.remove(insidx);
766 insidx--;
767 b->_ihrp_index--;
768 b->_fhrp_index--;
769 }
770 }
771 }
772 continue;
773 }
774 assert( insidx > b->_ihrp_index ||
775 (b->_reg_pressure < (uint)INTPRESSURE) ||
776 b->_ihrp_index > 4000000 ||
777 b->_ihrp_index >= b->end_idx() ||
778 !b->_nodes[b->_ihrp_index]->is_Proj(), "" );
779 assert( insidx > b->_fhrp_index ||
780 (b->_freg_pressure < (uint)FLOATPRESSURE) ||
781 b->_fhrp_index > 4000000 ||
782 b->_fhrp_index >= b->end_idx() ||
783 !b->_nodes[b->_fhrp_index]->is_Proj(), "" );
785 // ********** Handle Crossing HRP Boundry **********
786 if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) {
787 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
788 // Check for need to split at HRP boundary - split if UP
789 n1 = Reachblock[slidx];
790 // bail out if no reaching DEF
791 if( n1 == NULL ) continue;
792 // bail out if live range is 'isolated' around inner loop
793 uint lidx = lidxs.at(slidx);
794 // If live range is currently UP
795 if( UPblock[slidx] ) {
796 // set location to insert spills at
797 // SPLIT DOWN HERE - NO CISC SPILL
798 if( is_high_pressure( b, &lrgs(lidx), insidx ) &&
799 !n1->rematerialize() ) {
800 // If there is already a valid stack definition available, use it
801 if( debug_defs[slidx] != NULL ) {
802 Reachblock[slidx] = debug_defs[slidx];
803 }
804 else {
805 // Insert point is just past last use or def in the block
806 int insert_point = insidx-1;
807 while( insert_point > 0 ) {
808 Node *n = b->_nodes[insert_point];
809 // Hit top of block? Quit going backwards
810 if (n->is_Phi()) {
811 break;
812 }
813 // Found a def? Better split after it.
814 if (_lrg_map.live_range_id(n) == lidx) {
815 break;
816 }
817 // Look for a use
818 uint i;
819 for( i = 1; i < n->req(); i++ ) {
820 if (_lrg_map.live_range_id(n->in(i)) == lidx) {
821 break;
822 }
823 }
824 // Found a use? Better split after it.
825 if (i < n->req()) {
826 break;
827 }
828 insert_point--;
829 }
830 uint orig_eidx = b->end_idx();
831 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx);
832 // If it wasn't split bail
833 if (!maxlrg) {
834 return 0;
835 }
836 // Spill of NULL check mem op goes into the following block.
837 if (b->end_idx() > orig_eidx) {
838 insidx++;
839 }
840 }
841 // This is a new DEF, so update UP
842 UPblock[slidx] = false;
843 #ifndef PRODUCT
844 // DEBUG
845 if( trace_spilling() ) {
846 tty->print("\nNew Split DOWN DEF of Spill Idx ");
847 tty->print("%d, UP %d:\n",slidx,false);
848 n1->dump();
849 }
850 #endif
851 }
852 } // end if LRG is UP
853 } // end for all spilling live ranges
854 assert( b->_nodes[insidx] == n, "got insidx set incorrectly" );
855 } // end if crossing HRP Boundry
857 // If the LRG index is oob, then this is a new spillcopy, skip it.
858 if (defidx >= _lrg_map.max_lrg_id()) {
859 continue;
860 }
861 LRG &deflrg = lrgs(defidx);
862 uint copyidx = n->is_Copy();
863 // Remove coalesced copy from CFG
864 if (copyidx && defidx == _lrg_map.live_range_id(n->in(copyidx))) {
865 n->replace_by( n->in(copyidx) );
866 n->set_req( copyidx, NULL );
867 b->_nodes.remove(insidx--);
868 b->_ihrp_index--; // Adjust the point where we go hi-pressure
869 b->_fhrp_index--;
870 continue;
871 }
873 #define DERIVED 0
875 // ********** Handle USES **********
876 bool nullcheck = false;
877 // Implicit null checks never use the spilled value
878 if( n->is_MachNullCheck() )
879 nullcheck = true;
880 if( !nullcheck ) {
881 // Search all inputs for a Spill-USE
882 JVMState* jvms = n->jvms();
883 uint oopoff = jvms ? jvms->oopoff() : cnt;
884 uint old_last = cnt - 1;
885 for( inpidx = 1; inpidx < cnt; inpidx++ ) {
886 // Derived/base pairs may be added to our inputs during this loop.
887 // If inpidx > old_last, then one of these new inputs is being
888 // handled. Skip the derived part of the pair, but process
889 // the base like any other input.
890 if (inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED) {
891 continue; // skip derived_debug added below
892 }
893 // Get lidx of input
894 uint useidx = _lrg_map.find_id(n->in(inpidx));
895 // Not a brand-new split, and it is a spill use
896 if (useidx < _lrg_map.max_lrg_id() && lrgs(useidx).reg() >= LRG::SPILL_REG) {
897 // Check for valid reaching DEF
898 slidx = lrg2reach[useidx];
899 Node *def = Reachblock[slidx];
900 assert( def != NULL, "Using Undefined Value in Split()\n");
902 // (+++) %%%% remove this in favor of pre-pass in matcher.cpp
903 // monitor references do not care where they live, so just hook
904 if ( jvms && jvms->is_monitor_use(inpidx) ) {
905 // The effect of this clone is to drop the node out of the block,
906 // so that the allocator does not see it anymore, and therefore
907 // does not attempt to assign it a register.
908 def = clone_node(def, b, C);
909 if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
910 return 0;
911 }
912 _lrg_map.extend(def->_idx, 0);
913 _cfg._bbs.map(def->_idx,b);
914 n->set_req(inpidx, def);
915 continue;
916 }
918 // Rematerializable? Then clone def at use site instead
919 // of store/load
920 if( def->rematerialize() ) {
921 int old_size = b->_nodes.size();
922 def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true );
923 if( !def ) return 0; // Bail out
924 insidx += b->_nodes.size()-old_size;
925 }
927 MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL;
928 // Base pointers and oopmap references do not care where they live.
929 if ((inpidx >= oopoff) ||
930 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) {
931 if (def->rematerialize() && lrgs(useidx)._was_spilled2) {
932 // This def has been rematerialized a couple of times without
933 // progress. It doesn't care if it lives UP or DOWN, so
934 // spill it down now.
935 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx);
936 // If it wasn't split bail
937 if (!maxlrg) {
938 return 0;
939 }
940 insidx++; // Reset iterator to skip USE side split
941 } else {
942 // Just hook the def edge
943 n->set_req(inpidx, def);
944 }
946 if (inpidx >= oopoff) {
947 // After oopoff, we have derived/base pairs. We must mention all
948 // derived pointers here as derived/base pairs for GC. If the
949 // derived value is spilling and we have a copy both in Reachblock
950 // (called here 'def') and debug_defs[slidx] we need to mention
951 // both in derived/base pairs or kill one.
952 Node *derived_debug = debug_defs[slidx];
953 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base?
954 mach && mach->ideal_Opcode() != Op_Halt &&
955 derived_debug != NULL &&
956 derived_debug != def ) { // Actual 2nd value appears
957 // We have already set 'def' as a derived value.
958 // Also set debug_defs[slidx] as a derived value.
959 uint k;
960 for( k = oopoff; k < cnt; k += 2 )
961 if( n->in(k) == derived_debug )
962 break; // Found an instance of debug derived
963 if( k == cnt ) {// No instance of debug_defs[slidx]
964 // Add a derived/base pair to cover the debug info.
965 // We have to process the added base later since it is not
966 // handled yet at this point but skip derived part.
967 assert(((n->req() - oopoff) & 1) == DERIVED,
968 "must match skip condition above");
969 n->add_req( derived_debug ); // this will be skipped above
970 n->add_req( n->in(inpidx+1) ); // this will be processed
971 // Increment cnt to handle added input edges on
972 // subsequent iterations.
973 cnt += 2;
974 }
975 }
976 }
977 continue;
978 }
979 // Special logic for DEBUG info
980 if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) {
981 uint debug_start = jvms->debug_start();
982 // If this is debug info use & there is a reaching DOWN def
983 if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) {
984 assert(inpidx < oopoff, "handle only debug info here");
985 // Just hook it in & move on
986 n->set_req(inpidx, debug_defs[slidx]);
987 // (Note that this can make two sides of a split live at the
988 // same time: The debug def on stack, and another def in a
989 // register. The GC needs to know about both of them, but any
990 // derived pointers after oopoff will refer to only one of the
991 // two defs and the GC would therefore miss the other. Thus
992 // this hack is only allowed for debug info which is Java state
993 // and therefore never a derived pointer.)
994 continue;
995 }
996 }
997 // Grab register mask info
998 const RegMask &dmask = def->out_RegMask();
999 const RegMask &umask = n->in_RegMask(inpidx);
1000 bool is_vect = RegMask::is_vector(def->ideal_reg());
1001 assert(inpidx < oopoff, "cannot use-split oop map info");
1003 bool dup = UPblock[slidx];
1004 bool uup = umask.is_UP();
1006 // Need special logic to handle bound USES. Insert a split at this
1007 // bound use if we can't rematerialize the def, or if we need the
1008 // split to form a misaligned pair.
1009 if( !umask.is_AllStack() &&
1010 (int)umask.Size() <= lrgs(useidx).num_regs() &&
1011 (!def->rematerialize() ||
1012 !is_vect && umask.is_misaligned_pair())) {
1013 // These need a Split regardless of overlap or pressure
1014 // SPLIT - NO DEF - NO CISC SPILL
1015 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1016 // If it wasn't split bail
1017 if (!maxlrg) {
1018 return 0;
1019 }
1020 insidx++; // Reset iterator to skip USE side split
1021 continue;
1022 }
1024 if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) {
1025 // The use at the call can force the def down so insert
1026 // a split before the use to allow the def more freedom.
1027 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1028 // If it wasn't split bail
1029 if (!maxlrg) {
1030 return 0;
1031 }
1032 insidx++; // Reset iterator to skip USE side split
1033 continue;
1034 }
1036 // Here is the logic chart which describes USE Splitting:
1037 // 0 = false or DOWN, 1 = true or UP
1038 //
1039 // Overlap | DEF | USE | Action
1040 //-------------------------------------------------------
1041 // 0 | 0 | 0 | Copy - mem -> mem
1042 // 0 | 0 | 1 | Split-UP - Check HRP
1043 // 0 | 1 | 0 | Split-DOWN - Debug Info?
1044 // 0 | 1 | 1 | Copy - reg -> reg
1045 // 1 | 0 | 0 | Reset Input Edge (no Split)
1046 // 1 | 0 | 1 | Split-UP - Check HRP
1047 // 1 | 1 | 0 | Split-DOWN - Debug Info?
1048 // 1 | 1 | 1 | Reset Input Edge (no Split)
1049 //
1050 // So, if (dup == uup), then overlap test determines action,
1051 // with true being no split, and false being copy. Else,
1052 // if DEF is DOWN, Split-UP, and check HRP to decide on
1053 // resetting DEF. Finally if DEF is UP, Split-DOWN, with
1054 // special handling for Debug Info.
1055 if( dup == uup ) {
1056 if( dmask.overlap(umask) ) {
1057 // Both are either up or down, and there is overlap, No Split
1058 n->set_req(inpidx, def);
1059 }
1060 else { // Both are either up or down, and there is no overlap
1061 if( dup ) { // If UP, reg->reg copy
1062 // COPY ACROSS HERE - NO DEF - NO CISC SPILL
1063 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1064 // If it wasn't split bail
1065 if (!maxlrg) {
1066 return 0;
1067 }
1068 insidx++; // Reset iterator to skip USE side split
1069 }
1070 else { // DOWN, mem->mem copy
1071 // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL
1072 // First Split-UP to move value into Register
1073 uint def_ideal = def->ideal_reg();
1074 const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal];
1075 Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm);
1076 insert_proj( b, insidx, spill, maxlrg );
1077 // Then Split-DOWN as if previous Split was DEF
1078 maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx);
1079 // If it wasn't split bail
1080 if (!maxlrg) {
1081 return 0;
1082 }
1083 insidx += 2; // Reset iterator to skip USE side splits
1084 }
1085 } // End else no overlap
1086 } // End if dup == uup
1087 // dup != uup, so check dup for direction of Split
1088 else {
1089 if( dup ) { // If UP, Split-DOWN and check Debug Info
1090 // If this node is already a SpillCopy, just patch the edge
1091 // except the case of spilling to stack.
1092 if( n->is_SpillCopy() ) {
1093 RegMask tmp_rm(umask);
1094 tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask);
1095 if( dmask.overlap(tmp_rm) ) {
1096 if( def != n->in(inpidx) ) {
1097 n->set_req(inpidx, def);
1098 }
1099 continue;
1100 }
1101 }
1102 // COPY DOWN HERE - NO DEF - NO CISC SPILL
1103 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1104 // If it wasn't split bail
1105 if (!maxlrg) {
1106 return 0;
1107 }
1108 insidx++; // Reset iterator to skip USE side split
1109 // Check for debug-info split. Capture it for later
1110 // debug splits of the same value
1111 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff)
1112 debug_defs[slidx] = n->in(inpidx);
1114 }
1115 else { // DOWN, Split-UP and check register pressure
1116 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) {
1117 // COPY UP HERE - NO DEF - CISC SPILL
1118 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx);
1119 // If it wasn't split bail
1120 if (!maxlrg) {
1121 return 0;
1122 }
1123 insidx++; // Reset iterator to skip USE side split
1124 } else { // LRP
1125 // COPY UP HERE - WITH DEF - NO CISC SPILL
1126 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx);
1127 // If it wasn't split bail
1128 if (!maxlrg) {
1129 return 0;
1130 }
1131 // Flag this lift-up in a low-pressure block as
1132 // already-spilled, so if it spills again it will
1133 // spill hard (instead of not spilling hard and
1134 // coalescing away).
1135 set_was_spilled(n->in(inpidx));
1136 // Since this is a new DEF, update Reachblock & UP
1137 Reachblock[slidx] = n->in(inpidx);
1138 UPblock[slidx] = true;
1139 insidx++; // Reset iterator to skip USE side split
1140 }
1141 } // End else DOWN
1142 } // End dup != uup
1143 } // End if Spill USE
1144 } // End For All Inputs
1145 } // End If not nullcheck
1147 // ********** Handle DEFS **********
1148 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
1149 // just reset the Reaches info in LRP regions. DEFS must always update
1150 // UP info.
1151 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1152 uint slidx = lrg2reach[defidx];
1153 // Add to defs list for later assignment of new live range number
1154 defs->push(n);
1155 // Set a flag on the Node indicating it has already spilled.
1156 // Only do it for capacity spills not conflict spills.
1157 if( !deflrg._direct_conflict )
1158 set_was_spilled(n);
1159 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1160 // Grab UP info for DEF
1161 const RegMask &dmask = n->out_RegMask();
1162 bool defup = dmask.is_UP();
1163 int ireg = n->ideal_reg();
1164 bool is_vect = RegMask::is_vector(ireg);
1165 // Only split at Def if this is a HRP block or bound (and spilled once)
1166 if( !n->rematerialize() &&
1167 (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) &&
1168 (deflrg._direct_conflict || deflrg._must_spill)) ||
1169 // Check for LRG being up in a register and we are inside a high
1170 // pressure area. Spill it down immediately.
1171 (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1172 assert( !n->rematerialize(), "" );
1173 assert( !n->is_SpillCopy(), "" );
1174 // Do a split at the def site.
1175 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1176 // If it wasn't split bail
1177 if (!maxlrg) {
1178 return 0;
1179 }
1180 // Split DEF's Down
1181 UPblock[slidx] = 0;
1182 #ifndef PRODUCT
1183 // DEBUG
1184 if( trace_spilling() ) {
1185 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1186 tty->print("%d, UP %d:\n",slidx,false);
1187 n->dump();
1188 }
1189 #endif
1190 }
1191 else { // Neither bound nor HRP, must be LRP
1192 // otherwise, just record the def
1193 Reachblock[slidx] = n;
1194 // UP should come from the outRegmask() of the DEF
1195 UPblock[slidx] = defup;
1196 // Update debug list of reaching down definitions, kill if DEF is UP
1197 debug_defs[slidx] = defup ? NULL : n;
1198 #ifndef PRODUCT
1199 // DEBUG
1200 if( trace_spilling() ) {
1201 tty->print("\nNew DEF of Spill Idx ");
1202 tty->print("%d, UP %d:\n",slidx,defup);
1203 n->dump();
1204 }
1205 #endif
1206 } // End else LRP
1207 } // End if spill def
1209 // ********** Split Left Over Mem-Mem Moves **********
1210 // Check for mem-mem copies and split them now. Do not do this
1211 // to copies about to be spilled; they will be Split shortly.
1212 if (copyidx) {
1213 Node *use = n->in(copyidx);
1214 uint useidx = _lrg_map.find_id(use);
1215 if (useidx < _lrg_map.max_lrg_id() && // This is not a new split
1216 OptoReg::is_stack(deflrg.reg()) &&
1217 deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack
1218 LRG &uselrg = lrgs(useidx);
1219 if( OptoReg::is_stack(uselrg.reg()) &&
1220 uselrg.reg() < LRG::SPILL_REG && // USE is from stack
1221 deflrg.reg() != uselrg.reg() ) { // Not trivially removed
1222 uint def_ideal_reg = n->bottom_type()->ideal_reg();
1223 const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg];
1224 const RegMask &use_rm = n->in_RegMask(copyidx);
1225 if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL
1226 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes
1227 return 0;
1228 }
1229 Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm);
1230 n->set_req(copyidx,spill);
1231 n->as_MachSpillCopy()->set_in_RegMask(def_rm);
1232 // Put the spill just before the copy
1233 insert_proj( b, insidx++, spill, maxlrg++ );
1234 }
1235 }
1236 }
1237 }
1238 } // End For All Instructions in Block - Non-PHI Pass
1240 // Check if each LRG is live out of this block so as not to propagate
1241 // beyond the last use of a LRG.
1242 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1243 uint defidx = lidxs.at(slidx);
1244 IndexSet *liveout = _live->live(b);
1245 if( !liveout->member(defidx) ) {
1246 #ifdef ASSERT
1247 // The index defidx is not live. Check the liveout array to ensure that
1248 // it contains no members which compress to defidx. Finding such an
1249 // instance may be a case to add liveout adjustment in compress_uf_map().
1250 // See 5063219.
1251 uint member;
1252 IndexSetIterator isi(liveout);
1253 while ((member = isi.next()) != 0) {
1254 assert(defidx != _lrg_map.find_const(member), "Live out member has not been compressed");
1255 }
1256 #endif
1257 Reachblock[slidx] = NULL;
1258 } else {
1259 assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value");
1260 }
1261 }
1262 #ifndef PRODUCT
1263 if( trace_spilling() )
1264 b->dump();
1265 #endif
1266 } // End For All Blocks
1268 //----------PASS 2----------
1269 // Reset all DEF live range numbers here
1270 for( insidx = 0; insidx < defs->size(); insidx++ ) {
1271 // Grab the def
1272 n1 = defs->at(insidx);
1273 // Set new lidx for DEF
1274 new_lrg(n1, maxlrg++);
1275 }
1276 //----------Phi Node Splitting----------
1277 // Clean up a phi here, and assign a new live range number
1278 // Cycle through this block's predecessors, collecting Reaches
1279 // info for each spilled LRG and update edges.
1280 // Walk the phis list to patch inputs, split phis, and name phis
1281 uint lrgs_before_phi_split = maxlrg;
1282 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1283 Node *phi = phis->at(insidx);
1284 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1285 Block *b = _cfg._bbs[phi->_idx];
1286 // Grab the live range number
1287 uint lidx = _lrg_map.find_id(phi);
1288 uint slidx = lrg2reach[lidx];
1289 // Update node to lidx map
1290 new_lrg(phi, maxlrg++);
1291 // Get PASS1's up/down decision for the block.
1292 int phi_up = !!UP_entry[slidx]->test(b->_pre_order);
1294 // Force down if double-spilling live range
1295 if( lrgs(lidx)._was_spilled1 )
1296 phi_up = false;
1298 // When splitting a Phi we an split it normal or "inverted".
1299 // An inverted split makes the splits target the Phi's UP/DOWN
1300 // sense inverted; then the Phi is followed by a final def-side
1301 // split to invert back. It changes which blocks the spill code
1302 // goes in.
1304 // Walk the predecessor blocks and assign the reaching def to the Phi.
1305 // Split Phi nodes by placing USE side splits wherever the reaching
1306 // DEF has the wrong UP/DOWN value.
1307 for( uint i = 1; i < b->num_preds(); i++ ) {
1308 // Get predecessor block pre-order number
1309 Block *pred = _cfg._bbs[b->pred(i)->_idx];
1310 pidx = pred->_pre_order;
1311 // Grab reaching def
1312 Node *def = Reaches[pidx][slidx];
1313 assert( def, "must have reaching def" );
1314 // If input up/down sense and reg-pressure DISagree
1315 if( def->rematerialize() ) {
1316 // Place the rematerialized node above any MSCs created during
1317 // phi node splitting. end_idx points at the insertion point
1318 // so look at the node before it.
1319 int insert = pred->end_idx();
1320 while (insert >= 1 &&
1321 pred->_nodes[insert - 1]->is_SpillCopy() &&
1322 _lrg_map.find(pred->_nodes[insert - 1]) >= lrgs_before_phi_split) {
1323 insert--;
1324 }
1325 def = split_Rematerialize(def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false);
1326 if (!def) {
1327 return 0; // Bail out
1328 }
1329 }
1330 // Update the Phi's input edge array
1331 phi->set_req(i,def);
1332 // Grab the UP/DOWN sense for the input
1333 u1 = UP[pidx][slidx];
1334 if( u1 != (phi_up != 0)) {
1335 maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx);
1336 // If it wasn't split bail
1337 if (!maxlrg) {
1338 return 0;
1339 }
1340 }
1341 } // End for all inputs to the Phi
1342 } // End for all Phi Nodes
1343 // Update _maxlrg to save Union asserts
1344 _lrg_map.set_max_lrg_id(maxlrg);
1347 //----------PASS 3----------
1348 // Pass over all Phi's to union the live ranges
1349 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1350 Node *phi = phis->at(insidx);
1351 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1352 // Walk all inputs to Phi and Union input live range with Phi live range
1353 for( uint i = 1; i < phi->req(); i++ ) {
1354 // Grab the input node
1355 Node *n = phi->in(i);
1356 assert(n, "node should exist");
1357 uint lidx = _lrg_map.find(n);
1358 uint pidx = _lrg_map.find(phi);
1359 if (lidx < pidx) {
1360 Union(n, phi);
1361 }
1362 else if(lidx > pidx) {
1363 Union(phi, n);
1364 }
1365 } // End for all inputs to the Phi Node
1366 } // End for all Phi Nodes
1367 // Now union all two address instructions
1368 for (insidx = 0; insidx < defs->size(); insidx++) {
1369 // Grab the def
1370 n1 = defs->at(insidx);
1371 // Set new lidx for DEF & handle 2-addr instructions
1372 if (n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0)) {
1373 assert(_lrg_map.find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index");
1374 // Union the input and output live ranges
1375 uint lr1 = _lrg_map.find(n1);
1376 uint lr2 = _lrg_map.find(n1->in(twoidx));
1377 if (lr1 < lr2) {
1378 Union(n1, n1->in(twoidx));
1379 }
1380 else if (lr1 > lr2) {
1381 Union(n1->in(twoidx), n1);
1382 }
1383 } // End if two address
1384 } // End for all defs
1385 // DEBUG
1386 #ifdef ASSERT
1387 // Validate all live range index assignments
1388 for (bidx = 0; bidx < _cfg._num_blocks; bidx++) {
1389 b = _cfg._blocks[bidx];
1390 for (insidx = 0; insidx <= b->end_idx(); insidx++) {
1391 Node *n = b->_nodes[insidx];
1392 uint defidx = _lrg_map.find(n);
1393 assert(defidx < _lrg_map.max_lrg_id(), "Bad live range index in Split");
1394 assert(defidx < maxlrg,"Bad live range index in Split");
1395 }
1396 }
1397 // Issue a warning if splitting made no progress
1398 int noprogress = 0;
1399 for (slidx = 0; slidx < spill_cnt; slidx++) {
1400 if (PrintOpto && WizardMode && splits.at(slidx) == 0) {
1401 tty->print_cr("Failed to split live range %d", lidxs.at(slidx));
1402 //BREAKPOINT;
1403 }
1404 else {
1405 noprogress++;
1406 }
1407 }
1408 if(!noprogress) {
1409 tty->print_cr("Failed to make progress in Split");
1410 //BREAKPOINT;
1411 }
1412 #endif
1413 // Return updated count of live ranges
1414 return maxlrg;
1415 }