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src/cpu/x86/vm/vm_version_x86.cpp@93c14e5562c4
src/cpu/x86/vm/vm_version_x86.cpp
Wed, 06 May 2009 00:27:52 -0700
- author
- twisti
- date
- Wed, 06 May 2009 00:27:52 -0700
- changeset 1210
- 93c14e5562c4
- parent 1116
- fbde8ec322d0
- child 1495
- 323bd24c6520
- permissions
- -rw-r--r--
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions.
Reviewed-by: kvn, never
1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 # include "incls/_precompiled.incl"
26 # include "incls/_vm_version_x86.cpp.incl"
29 int VM_Version::_cpu;
30 int VM_Version::_model;
31 int VM_Version::_stepping;
32 int VM_Version::_cpuFeatures;
33 const char* VM_Version::_features_str = "";
34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
36 static BufferBlob* stub_blob;
37 static const int stub_size = 300;
39 extern "C" {
40 typedef void (*getPsrInfo_stub_t)(void*);
41 }
42 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
45 class VM_Version_StubGenerator: public StubCodeGenerator {
46 public:
48 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
50 address generate_getPsrInfo() {
51 // Flags to test CPU type.
52 const uint32_t EFL_AC = 0x40000;
53 const uint32_t EFL_ID = 0x200000;
54 // Values for when we don't have a CPUID instruction.
55 const int CPU_FAMILY_SHIFT = 8;
56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
59 Label detect_486, cpu486, detect_586, std_cpuid1;
60 Label ext_cpuid1, ext_cpuid5, done;
62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
63 # define __ _masm->
65 address start = __ pc();
67 //
68 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
69 //
70 // LP64: rcx and rdx are first and second argument registers on windows
72 __ push(rbp);
73 #ifdef _LP64
74 __ mov(rbp, c_rarg0); // cpuid_info address
75 #else
76 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
77 #endif
78 __ push(rbx);
79 __ push(rsi);
80 __ pushf(); // preserve rbx, and flags
81 __ pop(rax);
82 __ push(rax);
83 __ mov(rcx, rax);
84 //
85 // if we are unable to change the AC flag, we have a 386
86 //
87 __ xorl(rax, EFL_AC);
88 __ push(rax);
89 __ popf();
90 __ pushf();
91 __ pop(rax);
92 __ cmpptr(rax, rcx);
93 __ jccb(Assembler::notEqual, detect_486);
95 __ movl(rax, CPU_FAMILY_386);
96 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
97 __ jmp(done);
99 //
100 // If we are unable to change the ID flag, we have a 486 which does
101 // not support the "cpuid" instruction.
102 //
103 __ bind(detect_486);
104 __ mov(rax, rcx);
105 __ xorl(rax, EFL_ID);
106 __ push(rax);
107 __ popf();
108 __ pushf();
109 __ pop(rax);
110 __ cmpptr(rcx, rax);
111 __ jccb(Assembler::notEqual, detect_586);
113 __ bind(cpu486);
114 __ movl(rax, CPU_FAMILY_486);
115 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
116 __ jmp(done);
118 //
119 // At this point, we have a chip which supports the "cpuid" instruction
120 //
121 __ bind(detect_586);
122 __ xorl(rax, rax);
123 __ cpuid();
124 __ orl(rax, rax);
125 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
126 // value of at least 1, we give up and
127 // assume a 486
128 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
129 __ movl(Address(rsi, 0), rax);
130 __ movl(Address(rsi, 4), rbx);
131 __ movl(Address(rsi, 8), rcx);
132 __ movl(Address(rsi,12), rdx);
134 __ cmpl(rax, 3); // Is cpuid(0x4) supported?
135 __ jccb(Assembler::belowEqual, std_cpuid1);
137 //
138 // cpuid(0x4) Deterministic cache params
139 //
140 __ movl(rax, 4);
141 __ xorl(rcx, rcx); // L1 cache
142 __ cpuid();
143 __ push(rax);
144 __ andl(rax, 0x1f); // Determine if valid cache parameters used
145 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
146 __ pop(rax);
147 __ jccb(Assembler::equal, std_cpuid1);
149 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
150 __ movl(Address(rsi, 0), rax);
151 __ movl(Address(rsi, 4), rbx);
152 __ movl(Address(rsi, 8), rcx);
153 __ movl(Address(rsi,12), rdx);
155 //
156 // Standard cpuid(0x1)
157 //
158 __ bind(std_cpuid1);
159 __ movl(rax, 1);
160 __ cpuid();
161 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
162 __ movl(Address(rsi, 0), rax);
163 __ movl(Address(rsi, 4), rbx);
164 __ movl(Address(rsi, 8), rcx);
165 __ movl(Address(rsi,12), rdx);
167 __ movl(rax, 0x80000000);
168 __ cpuid();
169 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
170 __ jcc(Assembler::belowEqual, done);
171 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
172 __ jccb(Assembler::belowEqual, ext_cpuid1);
173 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
174 __ jccb(Assembler::belowEqual, ext_cpuid5);
175 //
176 // Extended cpuid(0x80000008)
177 //
178 __ movl(rax, 0x80000008);
179 __ cpuid();
180 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
181 __ movl(Address(rsi, 0), rax);
182 __ movl(Address(rsi, 4), rbx);
183 __ movl(Address(rsi, 8), rcx);
184 __ movl(Address(rsi,12), rdx);
186 //
187 // Extended cpuid(0x80000005)
188 //
189 __ bind(ext_cpuid5);
190 __ movl(rax, 0x80000005);
191 __ cpuid();
192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
193 __ movl(Address(rsi, 0), rax);
194 __ movl(Address(rsi, 4), rbx);
195 __ movl(Address(rsi, 8), rcx);
196 __ movl(Address(rsi,12), rdx);
198 //
199 // Extended cpuid(0x80000001)
200 //
201 __ bind(ext_cpuid1);
202 __ movl(rax, 0x80000001);
203 __ cpuid();
204 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
205 __ movl(Address(rsi, 0), rax);
206 __ movl(Address(rsi, 4), rbx);
207 __ movl(Address(rsi, 8), rcx);
208 __ movl(Address(rsi,12), rdx);
210 //
211 // return
212 //
213 __ bind(done);
214 __ popf();
215 __ pop(rsi);
216 __ pop(rbx);
217 __ pop(rbp);
218 __ ret(0);
220 # undef __
222 return start;
223 };
224 };
227 void VM_Version::get_processor_features() {
229 _cpu = 4; // 486 by default
230 _model = 0;
231 _stepping = 0;
232 _cpuFeatures = 0;
233 _logical_processors_per_package = 1;
235 if (!Use486InstrsOnly) {
236 // Get raw processor info
237 getPsrInfo_stub(&_cpuid_info);
238 assert_is_initialized();
239 _cpu = extended_cpu_family();
240 _model = extended_cpu_model();
241 _stepping = cpu_stepping();
243 if (cpu_family() > 4) { // it supports CPUID
244 _cpuFeatures = feature_flags();
245 // Logical processors are only available on P4s and above,
246 // and only if hyperthreading is available.
247 _logical_processors_per_package = logical_processor_count();
248 }
249 }
251 _supports_cx8 = supports_cmpxchg8();
253 #ifdef _LP64
254 // OS should support SSE for x64 and hardware should support at least SSE2.
255 if (!VM_Version::supports_sse2()) {
256 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
257 }
258 #endif
260 // If the OS doesn't support SSE, we can't use this feature even if the HW does
261 if (!os::supports_sse())
262 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
264 if (UseSSE < 4) {
265 _cpuFeatures &= ~CPU_SSE4_1;
266 _cpuFeatures &= ~CPU_SSE4_2;
267 }
269 if (UseSSE < 3) {
270 _cpuFeatures &= ~CPU_SSE3;
271 _cpuFeatures &= ~CPU_SSSE3;
272 _cpuFeatures &= ~CPU_SSE4A;
273 }
275 if (UseSSE < 2)
276 _cpuFeatures &= ~CPU_SSE2;
278 if (UseSSE < 1)
279 _cpuFeatures &= ~CPU_SSE;
281 if (logical_processors_per_package() == 1) {
282 // HT processor could be installed on a system which doesn't support HT.
283 _cpuFeatures &= ~CPU_HT;
284 }
286 char buf[256];
287 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
288 cores_per_cpu(), threads_per_core(),
289 cpu_family(), _model, _stepping,
290 (supports_cmov() ? ", cmov" : ""),
291 (supports_cmpxchg8() ? ", cx8" : ""),
292 (supports_fxsr() ? ", fxsr" : ""),
293 (supports_mmx() ? ", mmx" : ""),
294 (supports_sse() ? ", sse" : ""),
295 (supports_sse2() ? ", sse2" : ""),
296 (supports_sse3() ? ", sse3" : ""),
297 (supports_ssse3()? ", ssse3": ""),
298 (supports_sse4_1() ? ", sse4.1" : ""),
299 (supports_sse4_2() ? ", sse4.2" : ""),
300 (supports_popcnt() ? ", popcnt" : ""),
301 (supports_mmx_ext() ? ", mmxext" : ""),
302 (supports_3dnow() ? ", 3dnow" : ""),
303 (supports_3dnow2() ? ", 3dnowext" : ""),
304 (supports_lzcnt() ? ", lzcnt": ""),
305 (supports_sse4a() ? ", sse4a": ""),
306 (supports_ht() ? ", ht": ""));
307 _features_str = strdup(buf);
309 // UseSSE is set to the smaller of what hardware supports and what
310 // the command line requires. I.e., you cannot set UseSSE to 2 on
311 // older Pentiums which do not support it.
312 if( UseSSE > 4 ) UseSSE=4;
313 if( UseSSE < 0 ) UseSSE=0;
314 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
315 UseSSE = MIN2((intx)3,UseSSE);
316 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
317 UseSSE = MIN2((intx)2,UseSSE);
318 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
319 UseSSE = MIN2((intx)1,UseSSE);
320 if( !supports_sse () ) // Drop to 0 if no SSE support
321 UseSSE = 0;
323 // On new cpus instructions which update whole XMM register should be used
324 // to prevent partial register stall due to dependencies on high half.
325 //
326 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
327 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
328 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
329 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
331 if( is_amd() ) { // AMD cpus specific settings
332 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
333 // Use it on new AMD cpus starting from Opteron.
334 UseAddressNop = true;
335 }
336 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
337 // Use it on new AMD cpus starting from Opteron.
338 UseNewLongLShift = true;
339 }
340 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
341 if( supports_sse4a() ) {
342 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
343 } else {
344 UseXmmLoadAndClearUpper = false;
345 }
346 }
347 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
348 if( supports_sse4a() ) {
349 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
350 } else {
351 UseXmmRegToRegMoveAll = false;
352 }
353 }
354 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
355 if( supports_sse4a() ) {
356 UseXmmI2F = true;
357 } else {
358 UseXmmI2F = false;
359 }
360 }
361 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
362 if( supports_sse4a() ) {
363 UseXmmI2D = true;
364 } else {
365 UseXmmI2D = false;
366 }
367 }
369 // Use count leading zeros count instruction if available.
370 if (supports_lzcnt()) {
371 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
372 UseCountLeadingZerosInstruction = true;
373 }
374 }
375 }
377 if( is_intel() ) { // Intel cpus specific settings
378 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
379 UseStoreImmI16 = false; // don't use it on Intel cpus
380 }
381 if( cpu_family() == 6 || cpu_family() == 15 ) {
382 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
383 // Use it on all Intel cpus starting from PentiumPro
384 UseAddressNop = true;
385 }
386 }
387 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
388 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
389 }
390 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
391 if( supports_sse3() ) {
392 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
393 } else {
394 UseXmmRegToRegMoveAll = false;
395 }
396 }
397 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
398 #ifdef COMPILER2
399 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
400 // For new Intel cpus do the next optimization:
401 // don't align the beginning of a loop if there are enough instructions
402 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
403 // in current fetch line (OptoLoopAlignment) or the padding
404 // is big (> MaxLoopPad).
405 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
406 // generated NOP instructions. 11 is the largest size of one
407 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
408 MaxLoopPad = 11;
409 }
410 #endif // COMPILER2
411 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
412 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
413 }
414 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
415 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
416 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
417 }
418 }
419 if( supports_sse4_2() && UseSSE >= 4 ) {
420 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
421 UseSSE42Intrinsics = true;
422 }
423 }
424 }
425 }
427 // Use population count instruction if available.
428 if (supports_popcnt()) {
429 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
430 UsePopCountInstruction = true;
431 }
432 }
434 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
435 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
437 // set valid Prefetch instruction
438 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
439 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
440 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
441 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
443 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
444 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
445 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
446 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
448 // Allocation prefetch settings
449 intx cache_line_size = L1_data_cache_line_size();
450 if( cache_line_size > AllocatePrefetchStepSize )
451 AllocatePrefetchStepSize = cache_line_size;
452 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
453 AllocatePrefetchLines = 3; // Optimistic value
454 assert(AllocatePrefetchLines > 0, "invalid value");
455 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
456 AllocatePrefetchLines = 1; // Conservative value
458 AllocatePrefetchDistance = allocate_prefetch_distance();
459 AllocatePrefetchStyle = allocate_prefetch_style();
461 if( AllocatePrefetchStyle == 2 && is_intel() &&
462 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
463 #ifdef _LP64
464 AllocatePrefetchDistance = 384;
465 #else
466 AllocatePrefetchDistance = 320;
467 #endif
468 }
469 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
471 #ifdef _LP64
472 // Prefetch settings
473 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
474 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
475 PrefetchFieldsAhead = prefetch_fields_ahead();
476 #endif
478 #ifndef PRODUCT
479 if (PrintMiscellaneous && Verbose) {
480 tty->print_cr("Logical CPUs per core: %u",
481 logical_processors_per_package());
482 tty->print_cr("UseSSE=%d",UseSSE);
483 tty->print("Allocation: ");
484 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
485 tty->print_cr("no prefetching");
486 } else {
487 if (UseSSE == 0 && supports_3dnow()) {
488 tty->print("PREFETCHW");
489 } else if (UseSSE >= 1) {
490 if (AllocatePrefetchInstr == 0) {
491 tty->print("PREFETCHNTA");
492 } else if (AllocatePrefetchInstr == 1) {
493 tty->print("PREFETCHT0");
494 } else if (AllocatePrefetchInstr == 2) {
495 tty->print("PREFETCHT2");
496 } else if (AllocatePrefetchInstr == 3) {
497 tty->print("PREFETCHW");
498 }
499 }
500 if (AllocatePrefetchLines > 1) {
501 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
502 } else {
503 tty->print_cr(" %d, one line", AllocatePrefetchDistance);
504 }
505 }
507 if (PrefetchCopyIntervalInBytes > 0) {
508 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
509 }
510 if (PrefetchScanIntervalInBytes > 0) {
511 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
512 }
513 if (PrefetchFieldsAhead > 0) {
514 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
515 }
516 }
517 #endif // !PRODUCT
518 }
520 void VM_Version::initialize() {
521 ResourceMark rm;
522 // Making this stub must be FIRST use of assembler
524 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
525 if (stub_blob == NULL) {
526 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
527 }
528 CodeBuffer c(stub_blob->instructions_begin(),
529 stub_blob->instructions_size());
530 VM_Version_StubGenerator g(&c);
531 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
532 g.generate_getPsrInfo());
534 get_processor_features();
535 }
