Thu, 29 May 2008 16:22:09 -0700
6695049: (coll) Create an x86 intrinsic for Arrays.equals
Summary: Intrinsify java/util/Arrays.equals(char[], char[])
Reviewed-by: kvn, never
1 //
2 // Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundry (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm32_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
242 #define __ _masm.
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
282 static int sizeof_FFree_Float_Stack_All = -1;
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
295 //
296 // Compute padding required for nodes which need alignment
297 //
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 tty->print("FLDCW 24 bit fpu control word");
499 tty->print_cr(""); tty->print("\t");
500 }
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 tty->print_cr("# stack bang"); tty->print("\t");
514 }
515 tty->print_cr("PUSHL EBP"); tty->print("\t");
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 tty->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 tty->print_cr(""); tty->print("\t");
520 framesize -= wordSize;
521 }
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 tty->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 tty->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.pushl(rax);
597 masm.movl(rax, rsp);
598 masm.andl(rax, StackAlignmentInBytes-1);
599 masm.cmpl(rax, StackAlignmentInBytes-wordSize);
600 masm.popl(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
607 }
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
669 emit_opcode(cbuf, 0x58 | EBP_enc);
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
690 size++; // popl rbp,
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
708 int MachEpilogNode::safepoint_offset() const { return 0; }
710 //=============================================================================
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size ) {
729 if( cbuf ) {
730 emit_opcode (*cbuf, opcode );
731 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
732 #ifndef PRODUCT
733 } else if( !do_size ) {
734 if( size != 0 ) tty->print("\n\t");
735 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
736 if( is_load ) tty->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
737 else tty->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
738 } else { // FLD, FST, PUSH, POP
739 tty->print("%s [ESP + #%d]",op_str,offset);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 return size+3+offset_size;
745 }
747 // Helper for XMM registers. Extra opcode bits, limited syntax.
748 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
749 int offset, int reg_lo, int reg_hi, int size ) {
750 if( cbuf ) {
751 if( reg_lo+1 == reg_hi ) { // double move?
752 if( is_load && !UseXmmLoadAndClearUpper )
753 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
754 else
755 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
756 } else {
757 emit_opcode(*cbuf, 0xF3 );
758 }
759 emit_opcode(*cbuf, 0x0F );
760 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
761 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
762 else
763 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
764 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
765 #ifndef PRODUCT
766 } else if( !do_size ) {
767 if( size != 0 ) tty->print("\n\t");
768 if( reg_lo+1 == reg_hi ) { // double move?
769 if( is_load ) tty->print("%s %s,[ESP + #%d]",
770 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
771 Matcher::regName[reg_lo], offset);
772 else tty->print("MOVSD [ESP + #%d],%s",
773 offset, Matcher::regName[reg_lo]);
774 } else {
775 if( is_load ) tty->print("MOVSS %s,[ESP + #%d]",
776 Matcher::regName[reg_lo], offset);
777 else tty->print("MOVSS [ESP + #%d],%s",
778 offset, Matcher::regName[reg_lo]);
779 }
780 #endif
781 }
782 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
783 return size+5+offset_size;
784 }
787 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
788 int src_hi, int dst_hi, int size ) {
789 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
790 if( cbuf ) {
791 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
792 emit_opcode(*cbuf, 0x66 );
793 }
794 emit_opcode(*cbuf, 0x0F );
795 emit_opcode(*cbuf, 0x28 );
796 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
797 #ifndef PRODUCT
798 } else if( !do_size ) {
799 if( size != 0 ) tty->print("\n\t");
800 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
801 tty->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
802 } else {
803 tty->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
804 }
805 #endif
806 }
807 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
808 } else {
809 if( cbuf ) {
810 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
811 emit_opcode(*cbuf, 0x0F );
812 emit_opcode(*cbuf, 0x10 );
813 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
814 #ifndef PRODUCT
815 } else if( !do_size ) {
816 if( size != 0 ) tty->print("\n\t");
817 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
818 tty->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
819 } else {
820 tty->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
821 }
822 #endif
823 }
824 return size+4;
825 }
826 }
828 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size ) {
829 if( cbuf ) {
830 emit_opcode(*cbuf, 0x8B );
831 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
832 #ifndef PRODUCT
833 } else if( !do_size ) {
834 if( size != 0 ) tty->print("\n\t");
835 tty->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
836 #endif
837 }
838 return size+2;
839 }
841 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, int offset, int size ) {
842 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
843 if( cbuf ) {
844 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
845 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
846 #ifndef PRODUCT
847 } else if( !do_size ) {
848 if( size != 0 ) tty->print("\n\t");
849 tty->print("FLD %s",Matcher::regName[src_lo]);
850 #endif
851 }
852 size += 2;
853 }
855 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
856 const char *op_str;
857 int op;
858 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
859 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
860 op = 0xDD;
861 } else { // 32-bit store
862 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
863 op = 0xD9;
864 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
865 }
867 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size);
868 }
870 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
871 // Get registers to move
872 OptoReg::Name src_second = ra_->get_reg_second(in(1));
873 OptoReg::Name src_first = ra_->get_reg_first(in(1));
874 OptoReg::Name dst_second = ra_->get_reg_second(this );
875 OptoReg::Name dst_first = ra_->get_reg_first(this );
877 enum RC src_second_rc = rc_class(src_second);
878 enum RC src_first_rc = rc_class(src_first);
879 enum RC dst_second_rc = rc_class(dst_second);
880 enum RC dst_first_rc = rc_class(dst_first);
882 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
884 // Generate spill code!
885 int size = 0;
887 if( src_first == dst_first && src_second == dst_second )
888 return size; // Self copy, no move
890 // --------------------------------------
891 // Check for mem-mem move. push/pop to move.
892 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
893 if( src_second == dst_first ) { // overlapping stack copy ranges
894 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
895 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size);
896 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size);
897 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
898 }
899 // move low bits
900 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size);
901 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size);
902 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
903 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size);
904 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size);
905 }
906 return size;
907 }
909 // --------------------------------------
910 // Check for integer reg-reg copy
911 if( src_first_rc == rc_int && dst_first_rc == rc_int )
912 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size);
914 // Check for integer store
915 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
916 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size);
918 // Check for integer load
919 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
920 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size);
922 // --------------------------------------
923 // Check for float reg-reg copy
924 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
925 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
926 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
927 if( cbuf ) {
929 // Note the mucking with the register encode to compensate for the 0/1
930 // indexing issue mentioned in a comment in the reg_def sections
931 // for FPR registers many lines above here.
933 if( src_first != FPR1L_num ) {
934 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
935 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
936 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
937 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
938 } else {
939 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
940 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
941 }
942 #ifndef PRODUCT
943 } else if( !do_size ) {
944 if( size != 0 ) st->print("\n\t");
945 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
946 else st->print( "FST %s", Matcher::regName[dst_first]);
947 #endif
948 }
949 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
950 }
952 // Check for float store
953 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
954 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size);
955 }
957 // Check for float load
958 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
959 int offset = ra_->reg2offset(src_first);
960 const char *op_str;
961 int op;
962 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
963 op_str = "FLD_D";
964 op = 0xDD;
965 } else { // 32-bit load
966 op_str = "FLD_S";
967 op = 0xD9;
968 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
969 }
970 if( cbuf ) {
971 emit_opcode (*cbuf, op );
972 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
973 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
974 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
975 #ifndef PRODUCT
976 } else if( !do_size ) {
977 if( size != 0 ) st->print("\n\t");
978 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
979 #endif
980 }
981 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
982 return size + 3+offset_size+2;
983 }
985 // Check for xmm reg-reg copy
986 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
987 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
988 (src_first+1 == src_second && dst_first+1 == dst_second),
989 "no non-adjacent float-moves" );
990 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size);
991 }
993 // Check for xmm store
994 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size);
996 }
998 // Check for float xmm load
999 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1000 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size);
1001 }
1003 // Copy from float reg to xmm reg
1004 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1005 // copy to the top of stack from floating point reg
1006 // and use LEA to preserve flags
1007 if( cbuf ) {
1008 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1009 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1010 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1011 emit_d8(*cbuf,0xF8);
1012 #ifndef PRODUCT
1013 } else if( !do_size ) {
1014 if( size != 0 ) st->print("\n\t");
1015 st->print("LEA ESP,[ESP-8]");
1016 #endif
1017 }
1018 size += 4;
1020 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size);
1022 // Copy from the temp memory to the xmm reg.
1023 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size);
1025 if( cbuf ) {
1026 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1027 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1028 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1029 emit_d8(*cbuf,0x08);
1030 #ifndef PRODUCT
1031 } else if( !do_size ) {
1032 if( size != 0 ) st->print("\n\t");
1033 st->print("LEA ESP,[ESP+8]");
1034 #endif
1035 }
1036 size += 4;
1037 return size;
1038 }
1040 assert( size > 0, "missed a case" );
1042 // --------------------------------------------------------------------
1043 // Check for second bits still needing moving.
1044 if( src_second == dst_second )
1045 return size; // Self copy; no move
1046 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1048 // Check for second word int-int move
1049 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1050 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size);
1052 // Check for second word integer store
1053 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1054 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size);
1056 // Check for second word integer load
1057 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1058 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size);
1061 Unimplemented();
1062 }
1064 #ifndef PRODUCT
1065 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1066 implementation( NULL, ra_, false, st );
1067 }
1068 #endif
1070 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1071 implementation( &cbuf, ra_, false, NULL );
1072 }
1074 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1075 return implementation( NULL, ra_, true, NULL );
1076 }
1078 //=============================================================================
1079 #ifndef PRODUCT
1080 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1081 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1082 }
1083 #endif
1085 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1086 MacroAssembler _masm(&cbuf);
1087 __ nop(_count);
1088 }
1090 uint MachNopNode::size(PhaseRegAlloc *) const {
1091 return _count;
1092 }
1095 //=============================================================================
1096 #ifndef PRODUCT
1097 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1098 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1099 int reg = ra_->get_reg_first(this);
1100 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1101 }
1102 #endif
1104 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1105 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1106 int reg = ra_->get_encode(this);
1107 if( offset >= 128 ) {
1108 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1109 emit_rm(cbuf, 0x2, reg, 0x04);
1110 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1111 emit_d32(cbuf, offset);
1112 }
1113 else {
1114 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1115 emit_rm(cbuf, 0x1, reg, 0x04);
1116 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1117 emit_d8(cbuf, offset);
1118 }
1119 }
1121 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1122 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1123 if( offset >= 128 ) {
1124 return 7;
1125 }
1126 else {
1127 return 4;
1128 }
1129 }
1131 //=============================================================================
1133 // emit call stub, compiled java to interpreter
1134 void emit_java_to_interp(CodeBuffer &cbuf ) {
1135 // Stub is fixed up when the corresponding call is converted from calling
1136 // compiled code to calling interpreted code.
1137 // mov rbx,0
1138 // jmp -1
1140 address mark = cbuf.inst_mark(); // get mark within main instrs section
1142 // Note that the code buffer's inst_mark is always relative to insts.
1143 // That's why we must use the macroassembler to generate a stub.
1144 MacroAssembler _masm(&cbuf);
1146 address base =
1147 __ start_a_stub(Compile::MAX_stubs_size);
1148 if (base == NULL) return; // CodeBuffer::expand failed
1149 // static stub relocation stores the instruction address of the call
1150 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1151 // static stub relocation also tags the methodOop in the code-stream.
1152 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1153 __ jump(RuntimeAddress((address)-1));
1155 __ end_a_stub();
1156 // Update current stubs pointer and restore code_end.
1157 }
1158 // size of call stub, compiled java to interpretor
1159 uint size_java_to_interp() {
1160 return 10; // movl; jmp
1161 }
1162 // relocation entries for call stub, compiled java to interpretor
1163 uint reloc_java_to_interp() {
1164 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1165 }
1167 //=============================================================================
1168 #ifndef PRODUCT
1169 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1170 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1171 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1172 st->print_cr("\tNOP");
1173 st->print_cr("\tNOP");
1174 if( !OptoBreakpoint )
1175 st->print_cr("\tNOP");
1176 }
1177 #endif
1179 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1180 MacroAssembler masm(&cbuf);
1181 #ifdef ASSERT
1182 uint code_size = cbuf.code_size();
1183 #endif
1184 masm.cmpl(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1185 masm.jump_cc(Assembler::notEqual,
1186 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1187 /* WARNING these NOPs are critical so that verified entry point is properly
1188 aligned for patching by NativeJump::patch_verified_entry() */
1189 int nops_cnt = 2;
1190 if( !OptoBreakpoint ) // Leave space for int3
1191 nops_cnt += 1;
1192 masm.nop(nops_cnt);
1194 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1195 }
1197 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1198 return OptoBreakpoint ? 11 : 12;
1199 }
1202 //=============================================================================
1203 uint size_exception_handler() {
1204 // NativeCall instruction size is the same as NativeJump.
1205 // exception handler starts out as jump and can be patched to
1206 // a call be deoptimization. (4932387)
1207 // Note that this value is also credited (in output.cpp) to
1208 // the size of the code section.
1209 return NativeJump::instruction_size;
1210 }
1212 // Emit exception handler code. Stuff framesize into a register
1213 // and call a VM stub routine.
1214 int emit_exception_handler(CodeBuffer& cbuf) {
1216 // Note that the code buffer's inst_mark is always relative to insts.
1217 // That's why we must use the macroassembler to generate a handler.
1218 MacroAssembler _masm(&cbuf);
1219 address base =
1220 __ start_a_stub(size_exception_handler());
1221 if (base == NULL) return 0; // CodeBuffer::expand failed
1222 int offset = __ offset();
1223 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1224 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1225 __ end_a_stub();
1226 return offset;
1227 }
1229 uint size_deopt_handler() {
1230 // NativeCall instruction size is the same as NativeJump.
1231 // exception handler starts out as jump and can be patched to
1232 // a call be deoptimization. (4932387)
1233 // Note that this value is also credited (in output.cpp) to
1234 // the size of the code section.
1235 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1236 }
1238 // Emit deopt handler code.
1239 int emit_deopt_handler(CodeBuffer& cbuf) {
1241 // Note that the code buffer's inst_mark is always relative to insts.
1242 // That's why we must use the macroassembler to generate a handler.
1243 MacroAssembler _masm(&cbuf);
1244 address base =
1245 __ start_a_stub(size_exception_handler());
1246 if (base == NULL) return 0; // CodeBuffer::expand failed
1247 int offset = __ offset();
1248 InternalAddress here(__ pc());
1249 __ pushptr(here.addr());
1251 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1252 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1253 __ end_a_stub();
1254 return offset;
1255 }
1258 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1259 int mark = cbuf.insts()->mark_off();
1260 MacroAssembler _masm(&cbuf);
1261 address double_address = __ double_constant(x);
1262 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1263 emit_d32_reloc(cbuf,
1264 (int)double_address,
1265 internal_word_Relocation::spec(double_address),
1266 RELOC_DISP32);
1267 }
1269 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1270 int mark = cbuf.insts()->mark_off();
1271 MacroAssembler _masm(&cbuf);
1272 address float_address = __ float_constant(x);
1273 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1274 emit_d32_reloc(cbuf,
1275 (int)float_address,
1276 internal_word_Relocation::spec(float_address),
1277 RELOC_DISP32);
1278 }
1281 int Matcher::regnum_to_fpu_offset(int regnum) {
1282 return regnum - 32; // The FP registers are in the second chunk
1283 }
1285 bool is_positive_zero_float(jfloat f) {
1286 return jint_cast(f) == jint_cast(0.0F);
1287 }
1289 bool is_positive_one_float(jfloat f) {
1290 return jint_cast(f) == jint_cast(1.0F);
1291 }
1293 bool is_positive_zero_double(jdouble d) {
1294 return jlong_cast(d) == jlong_cast(0.0);
1295 }
1297 bool is_positive_one_double(jdouble d) {
1298 return jlong_cast(d) == jlong_cast(1.0);
1299 }
1301 // This is UltraSparc specific, true just means we have fast l2f conversion
1302 const bool Matcher::convL2FSupported(void) {
1303 return true;
1304 }
1306 // Vector width in bytes
1307 const uint Matcher::vector_width_in_bytes(void) {
1308 return UseSSE >= 2 ? 8 : 0;
1309 }
1311 // Vector ideal reg
1312 const uint Matcher::vector_ideal_reg(void) {
1313 return Op_RegD;
1314 }
1316 // Is this branch offset short enough that a short branch can be used?
1317 //
1318 // NOTE: If the platform does not provide any short branch variants, then
1319 // this method should return false for offset 0.
1320 bool Matcher::is_short_branch_offset(int offset) {
1321 return (-128 <= offset && offset <= 127);
1322 }
1324 const bool Matcher::isSimpleConstant64(jlong value) {
1325 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1326 return false;
1327 }
1329 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1330 const bool Matcher::init_array_count_is_in_bytes = false;
1332 // Threshold size for cleararray.
1333 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1335 // Should the Matcher clone shifts on addressing modes, expecting them to
1336 // be subsumed into complex addressing expressions or compute them into
1337 // registers? True for Intel but false for most RISCs
1338 const bool Matcher::clone_shift_expressions = true;
1340 // Is it better to copy float constants, or load them directly from memory?
1341 // Intel can load a float constant from a direct address, requiring no
1342 // extra registers. Most RISCs will have to materialize an address into a
1343 // register first, so they would do better to copy the constant from stack.
1344 const bool Matcher::rematerialize_float_constants = true;
1346 // If CPU can load and store mis-aligned doubles directly then no fixup is
1347 // needed. Else we split the double into 2 integer pieces and move it
1348 // piece-by-piece. Only happens when passing doubles into C code as the
1349 // Java calling convention forces doubles to be aligned.
1350 const bool Matcher::misaligned_doubles_ok = true;
1353 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1354 // Get the memory operand from the node
1355 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1356 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1357 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1358 uint opcnt = 1; // First operand
1359 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1360 while( idx >= skipped+num_edges ) {
1361 skipped += num_edges;
1362 opcnt++; // Bump operand count
1363 assert( opcnt < numopnds, "Accessing non-existent operand" );
1364 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1365 }
1367 MachOper *memory = node->_opnds[opcnt];
1368 MachOper *new_memory = NULL;
1369 switch (memory->opcode()) {
1370 case DIRECT:
1371 case INDOFFSET32X:
1372 // No transformation necessary.
1373 return;
1374 case INDIRECT:
1375 new_memory = new (C) indirect_win95_safeOper( );
1376 break;
1377 case INDOFFSET8:
1378 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1379 break;
1380 case INDOFFSET32:
1381 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1382 break;
1383 case INDINDEXOFFSET:
1384 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1385 break;
1386 case INDINDEXSCALE:
1387 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1388 break;
1389 case INDINDEXSCALEOFFSET:
1390 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1391 break;
1392 case LOAD_LONG_INDIRECT:
1393 case LOAD_LONG_INDOFFSET32:
1394 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1395 return;
1396 default:
1397 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1398 return;
1399 }
1400 node->_opnds[opcnt] = new_memory;
1401 }
1403 // Advertise here if the CPU requires explicit rounding operations
1404 // to implement the UseStrictFP mode.
1405 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1407 // Do floats take an entire double register or just half?
1408 const bool Matcher::float_in_double = true;
1409 // Do ints take an entire long register or just half?
1410 const bool Matcher::int_in_long = false;
1412 // Return whether or not this register is ever used as an argument. This
1413 // function is used on startup to build the trampoline stubs in generateOptoStub.
1414 // Registers not mentioned will be killed by the VM call in the trampoline, and
1415 // arguments in those registers not be available to the callee.
1416 bool Matcher::can_be_java_arg( int reg ) {
1417 if( reg == ECX_num || reg == EDX_num ) return true;
1418 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1419 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1420 return false;
1421 }
1423 bool Matcher::is_spillable_arg( int reg ) {
1424 return can_be_java_arg(reg);
1425 }
1427 // Register for DIVI projection of divmodI
1428 RegMask Matcher::divI_proj_mask() {
1429 return EAX_REG_mask;
1430 }
1432 // Register for MODI projection of divmodI
1433 RegMask Matcher::modI_proj_mask() {
1434 return EDX_REG_mask;
1435 }
1437 // Register for DIVL projection of divmodL
1438 RegMask Matcher::divL_proj_mask() {
1439 ShouldNotReachHere();
1440 return RegMask();
1441 }
1443 // Register for MODL projection of divmodL
1444 RegMask Matcher::modL_proj_mask() {
1445 ShouldNotReachHere();
1446 return RegMask();
1447 }
1449 %}
1451 //----------ENCODING BLOCK-----------------------------------------------------
1452 // This block specifies the encoding classes used by the compiler to output
1453 // byte streams. Encoding classes generate functions which are called by
1454 // Machine Instruction Nodes in order to generate the bit encoding of the
1455 // instruction. Operands specify their base encoding interface with the
1456 // interface keyword. There are currently supported four interfaces,
1457 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1458 // operand to generate a function which returns its register number when
1459 // queried. CONST_INTER causes an operand to generate a function which
1460 // returns the value of the constant when queried. MEMORY_INTER causes an
1461 // operand to generate four functions which return the Base Register, the
1462 // Index Register, the Scale Value, and the Offset Value of the operand when
1463 // queried. COND_INTER causes an operand to generate six functions which
1464 // return the encoding code (ie - encoding bits for the instruction)
1465 // associated with each basic boolean condition for a conditional instruction.
1466 // Instructions specify two basic values for encoding. They use the
1467 // ins_encode keyword to specify their encoding class (which must be one of
1468 // the class names specified in the encoding block), and they use the
1469 // opcode keyword to specify, in order, their primary, secondary, and
1470 // tertiary opcode. Only the opcode sections which a particular instruction
1471 // needs for encoding need to be specified.
1472 encode %{
1473 // Build emit functions for each basic byte or larger field in the intel
1474 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1475 // code in the enc_class source block. Emit functions will live in the
1476 // main source block for now. In future, we can generalize this by
1477 // adding a syntax that specifies the sizes of fields in an order,
1478 // so that the adlc can build the emit functions automagically
1479 enc_class OpcP %{ // Emit opcode
1480 emit_opcode(cbuf,$primary);
1481 %}
1483 enc_class OpcS %{ // Emit opcode
1484 emit_opcode(cbuf,$secondary);
1485 %}
1487 enc_class Opcode(immI d8 ) %{ // Emit opcode
1488 emit_opcode(cbuf,$d8$$constant);
1489 %}
1491 enc_class SizePrefix %{
1492 emit_opcode(cbuf,0x66);
1493 %}
1495 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1496 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1497 %}
1499 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1500 emit_opcode(cbuf,$opcode$$constant);
1501 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1502 %}
1504 enc_class mov_r32_imm0( eRegI dst ) %{
1505 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1506 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1507 %}
1509 enc_class cdq_enc %{
1510 // Full implementation of Java idiv and irem; checks for
1511 // special case as described in JVM spec., p.243 & p.271.
1512 //
1513 // normal case special case
1514 //
1515 // input : rax,: dividend min_int
1516 // reg: divisor -1
1517 //
1518 // output: rax,: quotient (= rax, idiv reg) min_int
1519 // rdx: remainder (= rax, irem reg) 0
1520 //
1521 // Code sequnce:
1522 //
1523 // 81 F8 00 00 00 80 cmp rax,80000000h
1524 // 0F 85 0B 00 00 00 jne normal_case
1525 // 33 D2 xor rdx,edx
1526 // 83 F9 FF cmp rcx,0FFh
1527 // 0F 84 03 00 00 00 je done
1528 // normal_case:
1529 // 99 cdq
1530 // F7 F9 idiv rax,ecx
1531 // done:
1532 //
1533 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1534 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1535 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1536 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1537 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1538 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1539 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1540 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1541 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1542 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1543 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1544 // normal_case:
1545 emit_opcode(cbuf,0x99); // cdq
1546 // idiv (note: must be emitted by the user of this rule)
1547 // normal:
1548 %}
1550 // Dense encoding for older common ops
1551 enc_class Opc_plus(immI opcode, eRegI reg) %{
1552 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1553 %}
1556 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1557 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1558 // Check for 8-bit immediate, and set sign extend bit in opcode
1559 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1560 emit_opcode(cbuf, $primary | 0x02);
1561 }
1562 else { // If 32-bit immediate
1563 emit_opcode(cbuf, $primary);
1564 }
1565 %}
1567 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1568 // Emit primary opcode and set sign-extend bit
1569 // Check for 8-bit immediate, and set sign extend bit in opcode
1570 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1571 emit_opcode(cbuf, $primary | 0x02); }
1572 else { // If 32-bit immediate
1573 emit_opcode(cbuf, $primary);
1574 }
1575 // Emit r/m byte with secondary opcode, after primary opcode.
1576 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1577 %}
1579 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1580 // Check for 8-bit immediate, and set sign extend bit in opcode
1581 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1582 $$$emit8$imm$$constant;
1583 }
1584 else { // If 32-bit immediate
1585 // Output immediate
1586 $$$emit32$imm$$constant;
1587 }
1588 %}
1590 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1591 // Emit primary opcode and set sign-extend bit
1592 // Check for 8-bit immediate, and set sign extend bit in opcode
1593 int con = (int)$imm$$constant; // Throw away top bits
1594 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1595 // Emit r/m byte with secondary opcode, after primary opcode.
1596 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1597 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1598 else emit_d32(cbuf,con);
1599 %}
1601 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1602 // Emit primary opcode and set sign-extend bit
1603 // Check for 8-bit immediate, and set sign extend bit in opcode
1604 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1605 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1606 // Emit r/m byte with tertiary opcode, after primary opcode.
1607 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1608 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1609 else emit_d32(cbuf,con);
1610 %}
1612 enc_class Lbl (label labl) %{ // JMP, CALL
1613 Label *l = $labl$$label;
1614 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1615 %}
1617 enc_class LblShort (label labl) %{ // JMP, CALL
1618 Label *l = $labl$$label;
1619 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1620 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1621 emit_d8(cbuf, disp);
1622 %}
1624 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1625 emit_cc(cbuf, $secondary, $dst$$reg );
1626 %}
1628 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1629 int destlo = $dst$$reg;
1630 int desthi = HIGH_FROM_LOW(destlo);
1631 // bswap lo
1632 emit_opcode(cbuf, 0x0F);
1633 emit_cc(cbuf, 0xC8, destlo);
1634 // bswap hi
1635 emit_opcode(cbuf, 0x0F);
1636 emit_cc(cbuf, 0xC8, desthi);
1637 // xchg lo and hi
1638 emit_opcode(cbuf, 0x87);
1639 emit_rm(cbuf, 0x3, destlo, desthi);
1640 %}
1642 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1643 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1644 %}
1646 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1647 Label *l = $labl$$label;
1648 $$$emit8$primary;
1649 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1650 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1651 %}
1653 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1654 Label *l = $labl$$label;
1655 emit_cc(cbuf, $primary, $cop$$cmpcode);
1656 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1657 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1658 emit_d8(cbuf, disp);
1659 %}
1661 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1662 $$$emit8$primary;
1663 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1664 %}
1666 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1667 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1668 emit_d8(cbuf, op >> 8 );
1669 emit_d8(cbuf, op & 255);
1670 %}
1672 // emulate a CMOV with a conditional branch around a MOV
1673 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1674 // Invert sense of branch from sense of CMOV
1675 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1676 emit_d8( cbuf, $brOffs$$constant );
1677 %}
1679 enc_class enc_PartialSubtypeCheck( ) %{
1680 Register Redi = as_Register(EDI_enc); // result register
1681 Register Reax = as_Register(EAX_enc); // super class
1682 Register Recx = as_Register(ECX_enc); // killed
1683 Register Resi = as_Register(ESI_enc); // sub class
1684 Label hit, miss;
1686 MacroAssembler _masm(&cbuf);
1687 // Compare super with sub directly, since super is not in its own SSA.
1688 // The compiler used to emit this test, but we fold it in here,
1689 // to allow platform-specific tweaking on sparc.
1690 __ cmpl(Reax, Resi);
1691 __ jcc(Assembler::equal, hit);
1692 #ifndef PRODUCT
1693 __ increment(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1694 #endif //PRODUCT
1695 __ movl(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
1696 __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes()));
1697 __ addl(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
1698 __ repne_scan();
1699 __ jcc(Assembler::notEqual, miss);
1700 __ movl(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax);
1701 __ bind(hit);
1702 if( $primary )
1703 __ xorl(Redi,Redi);
1704 __ bind(miss);
1705 %}
1707 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1708 MacroAssembler masm(&cbuf);
1709 int start = masm.offset();
1710 if (UseSSE >= 2) {
1711 if (VerifyFPU) {
1712 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1713 }
1714 } else {
1715 // External c_calling_convention expects the FPU stack to be 'clean'.
1716 // Compiled code leaves it dirty. Do cleanup now.
1717 masm.empty_FPU_stack();
1718 }
1719 if (sizeof_FFree_Float_Stack_All == -1) {
1720 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1721 } else {
1722 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1723 }
1724 %}
1726 enc_class Verify_FPU_For_Leaf %{
1727 if( VerifyFPU ) {
1728 MacroAssembler masm(&cbuf);
1729 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1730 }
1731 %}
1733 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1734 // This is the instruction starting address for relocation info.
1735 cbuf.set_inst_mark();
1736 $$$emit8$primary;
1737 // CALL directly to the runtime
1738 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1739 runtime_call_Relocation::spec(), RELOC_IMM32 );
1741 if (UseSSE >= 2) {
1742 MacroAssembler _masm(&cbuf);
1743 BasicType rt = tf()->return_type();
1745 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1746 // A C runtime call where the return value is unused. In SSE2+
1747 // mode the result needs to be removed from the FPU stack. It's
1748 // likely that this function call could be removed by the
1749 // optimizer if the C function is a pure function.
1750 __ ffree(0);
1751 } else if (rt == T_FLOAT) {
1752 __ leal(rsp, Address(rsp, -4));
1753 __ fstp_s(Address(rsp, 0));
1754 __ movflt(xmm0, Address(rsp, 0));
1755 __ leal(rsp, Address(rsp, 4));
1756 } else if (rt == T_DOUBLE) {
1757 __ leal(rsp, Address(rsp, -8));
1758 __ fstp_d(Address(rsp, 0));
1759 __ movdbl(xmm0, Address(rsp, 0));
1760 __ leal(rsp, Address(rsp, 8));
1761 }
1762 }
1763 %}
1766 enc_class pre_call_FPU %{
1767 // If method sets FPU control word restore it here
1768 if( Compile::current()->in_24_bit_fp_mode() ) {
1769 MacroAssembler masm(&cbuf);
1770 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1771 }
1772 %}
1774 enc_class post_call_FPU %{
1775 // If method sets FPU control word do it here also
1776 if( Compile::current()->in_24_bit_fp_mode() ) {
1777 MacroAssembler masm(&cbuf);
1778 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1779 }
1780 %}
1782 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1783 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1784 // who we intended to call.
1785 cbuf.set_inst_mark();
1786 $$$emit8$primary;
1787 if ( !_method ) {
1788 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1789 runtime_call_Relocation::spec(), RELOC_IMM32 );
1790 } else if(_optimized_virtual) {
1791 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1792 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1793 } else {
1794 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1795 static_call_Relocation::spec(), RELOC_IMM32 );
1796 }
1797 if( _method ) { // Emit stub for static call
1798 emit_java_to_interp(cbuf);
1799 }
1800 %}
1802 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1803 // !!!!!
1804 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1805 // emit_call_dynamic_prologue( cbuf );
1806 cbuf.set_inst_mark();
1807 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1808 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1809 address virtual_call_oop_addr = cbuf.inst_mark();
1810 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1811 // who we intended to call.
1812 cbuf.set_inst_mark();
1813 $$$emit8$primary;
1814 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1815 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1816 %}
1818 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1819 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1820 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1822 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1823 cbuf.set_inst_mark();
1824 $$$emit8$primary;
1825 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1826 emit_d8(cbuf, disp); // Displacement
1828 %}
1830 enc_class Xor_Reg (eRegI dst) %{
1831 emit_opcode(cbuf, 0x33);
1832 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1833 %}
1835 // Following encoding is no longer used, but may be restored if calling
1836 // convention changes significantly.
1837 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1838 //
1839 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1840 // // int ic_reg = Matcher::inline_cache_reg();
1841 // // int ic_encode = Matcher::_regEncode[ic_reg];
1842 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1843 // // int imo_encode = Matcher::_regEncode[imo_reg];
1844 //
1845 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1846 // // // so we load it immediately before the call
1847 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1848 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1849 //
1850 // // xor rbp,ebp
1851 // emit_opcode(cbuf, 0x33);
1852 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1853 //
1854 // // CALL to interpreter.
1855 // cbuf.set_inst_mark();
1856 // $$$emit8$primary;
1857 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1858 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1859 // %}
1861 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1862 $$$emit8$primary;
1863 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1864 $$$emit8$shift$$constant;
1865 %}
1867 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1868 // Load immediate does not have a zero or sign extended version
1869 // for 8-bit immediates
1870 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1871 $$$emit32$src$$constant;
1872 %}
1874 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, $primary + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1881 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 int dst_enc = $dst$$reg;
1885 int src_con = $src$$constant & 0x0FFFFFFFFL;
1886 if (src_con == 0) {
1887 // xor dst, dst
1888 emit_opcode(cbuf, 0x33);
1889 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1890 } else {
1891 emit_opcode(cbuf, $primary + dst_enc);
1892 emit_d32(cbuf, src_con);
1893 }
1894 %}
1896 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1897 // Load immediate does not have a zero or sign extended version
1898 // for 8-bit immediates
1899 int dst_enc = $dst$$reg + 2;
1900 int src_con = ((julong)($src$$constant)) >> 32;
1901 if (src_con == 0) {
1902 // xor dst, dst
1903 emit_opcode(cbuf, 0x33);
1904 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1905 } else {
1906 emit_opcode(cbuf, $primary + dst_enc);
1907 emit_d32(cbuf, src_con);
1908 }
1909 %}
1912 enc_class LdImmD (immD src) %{ // Load Immediate
1913 if( is_positive_zero_double($src$$constant)) {
1914 // FLDZ
1915 emit_opcode(cbuf,0xD9);
1916 emit_opcode(cbuf,0xEE);
1917 } else if( is_positive_one_double($src$$constant)) {
1918 // FLD1
1919 emit_opcode(cbuf,0xD9);
1920 emit_opcode(cbuf,0xE8);
1921 } else {
1922 emit_opcode(cbuf,0xDD);
1923 emit_rm(cbuf, 0x0, 0x0, 0x5);
1924 emit_double_constant(cbuf, $src$$constant);
1925 }
1926 %}
1929 enc_class LdImmF (immF src) %{ // Load Immediate
1930 if( is_positive_zero_float($src$$constant)) {
1931 emit_opcode(cbuf,0xD9);
1932 emit_opcode(cbuf,0xEE);
1933 } else if( is_positive_one_float($src$$constant)) {
1934 emit_opcode(cbuf,0xD9);
1935 emit_opcode(cbuf,0xE8);
1936 } else {
1937 $$$emit8$primary;
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 // First load to TOS, then move to dst
1941 emit_rm(cbuf, 0x0, 0x0, 0x5);
1942 emit_float_constant(cbuf, $src$$constant);
1943 }
1944 %}
1946 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1947 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1948 emit_float_constant(cbuf, $con$$constant);
1949 %}
1951 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1952 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1953 emit_double_constant(cbuf, $con$$constant);
1954 %}
1956 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1957 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1958 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1959 emit_opcode(cbuf, 0x0F);
1960 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1961 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1962 emit_double_constant(cbuf, $con$$constant);
1963 %}
1965 enc_class Opc_MemImm_F(immF src) %{
1966 cbuf.set_inst_mark();
1967 $$$emit8$primary;
1968 emit_rm(cbuf, 0x0, $secondary, 0x5);
1969 emit_float_constant(cbuf, $src$$constant);
1970 %}
1973 enc_class MovI2X_reg(regX dst, eRegI src) %{
1974 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1975 emit_opcode(cbuf, 0x0F );
1976 emit_opcode(cbuf, 0x6E );
1977 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1978 %}
1980 enc_class MovX2I_reg(eRegI dst, regX src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x7E );
1984 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1985 %}
1987 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1988 { // MOVD $dst,$src.lo
1989 emit_opcode(cbuf,0x66);
1990 emit_opcode(cbuf,0x0F);
1991 emit_opcode(cbuf,0x6E);
1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1993 }
1994 { // MOVD $tmp,$src.hi
1995 emit_opcode(cbuf,0x66);
1996 emit_opcode(cbuf,0x0F);
1997 emit_opcode(cbuf,0x6E);
1998 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
1999 }
2000 { // PUNPCKLDQ $dst,$tmp
2001 emit_opcode(cbuf,0x66);
2002 emit_opcode(cbuf,0x0F);
2003 emit_opcode(cbuf,0x62);
2004 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2005 }
2006 %}
2008 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2009 { // MOVD $dst.lo,$src
2010 emit_opcode(cbuf,0x66);
2011 emit_opcode(cbuf,0x0F);
2012 emit_opcode(cbuf,0x7E);
2013 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2014 }
2015 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2016 emit_opcode(cbuf,0xF2);
2017 emit_opcode(cbuf,0x0F);
2018 emit_opcode(cbuf,0x70);
2019 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2020 emit_d8(cbuf, 0x4E);
2021 }
2022 { // MOVD $dst.hi,$tmp
2023 emit_opcode(cbuf,0x66);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x7E);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2027 }
2028 %}
2031 // Encode a reg-reg copy. If it is useless, then empty encoding.
2032 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2033 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2034 %}
2036 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2037 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2038 %}
2040 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2041 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2042 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2043 %}
2045 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2046 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2047 %}
2049 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2050 $$$emit8$primary;
2051 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2052 %}
2054 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2055 $$$emit8$secondary;
2056 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2057 %}
2059 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2060 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2061 %}
2063 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2064 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2065 %}
2067 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2068 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2069 %}
2071 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2072 // Output immediate
2073 $$$emit32$src$$constant;
2074 %}
2076 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2077 // Output Float immediate bits
2078 jfloat jf = $src$$constant;
2079 int jf_as_bits = jint_cast( jf );
2080 emit_d32(cbuf, jf_as_bits);
2081 %}
2083 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2090 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2091 // Output immediate
2092 $$$emit16$src$$constant;
2093 %}
2095 enc_class Con_d32(immI src) %{
2096 emit_d32(cbuf,$src$$constant);
2097 %}
2099 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2100 // Output immediate memory reference
2101 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2102 emit_d32(cbuf, 0x00);
2103 %}
2105 enc_class lock_prefix( ) %{
2106 if( os::is_MP() )
2107 emit_opcode(cbuf,0xF0); // [Lock]
2108 %}
2110 // Cmp-xchg long value.
2111 // Note: we need to swap rbx, and rcx before and after the
2112 // cmpxchg8 instruction because the instruction uses
2113 // rcx as the high order word of the new value to store but
2114 // our register encoding uses rbx,.
2115 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2117 // XCHG rbx,ecx
2118 emit_opcode(cbuf,0x87);
2119 emit_opcode(cbuf,0xD9);
2120 // [Lock]
2121 if( os::is_MP() )
2122 emit_opcode(cbuf,0xF0);
2123 // CMPXCHG8 [Eptr]
2124 emit_opcode(cbuf,0x0F);
2125 emit_opcode(cbuf,0xC7);
2126 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2127 // XCHG rbx,ecx
2128 emit_opcode(cbuf,0x87);
2129 emit_opcode(cbuf,0xD9);
2130 %}
2132 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2133 // [Lock]
2134 if( os::is_MP() )
2135 emit_opcode(cbuf,0xF0);
2137 // CMPXCHG [Eptr]
2138 emit_opcode(cbuf,0x0F);
2139 emit_opcode(cbuf,0xB1);
2140 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2141 %}
2143 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2144 int res_encoding = $res$$reg;
2146 // MOV res,0
2147 emit_opcode( cbuf, 0xB8 + res_encoding);
2148 emit_d32( cbuf, 0 );
2149 // JNE,s fail
2150 emit_opcode(cbuf,0x75);
2151 emit_d8(cbuf, 5 );
2152 // MOV res,1
2153 emit_opcode( cbuf, 0xB8 + res_encoding);
2154 emit_d32( cbuf, 1 );
2155 // fail:
2156 %}
2158 enc_class set_instruction_start( ) %{
2159 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2160 %}
2162 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2163 int reg_encoding = $ereg$$reg;
2164 int base = $mem$$base;
2165 int index = $mem$$index;
2166 int scale = $mem$$scale;
2167 int displace = $mem$$disp;
2168 bool disp_is_oop = $mem->disp_is_oop();
2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2170 %}
2172 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2173 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2174 int base = $mem$$base;
2175 int index = $mem$$index;
2176 int scale = $mem$$scale;
2177 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2178 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2179 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2180 %}
2182 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2183 int r1, r2;
2184 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2185 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2186 emit_opcode(cbuf,0x0F);
2187 emit_opcode(cbuf,$tertiary);
2188 emit_rm(cbuf, 0x3, r1, r2);
2189 emit_d8(cbuf,$cnt$$constant);
2190 emit_d8(cbuf,$primary);
2191 emit_rm(cbuf, 0x3, $secondary, r1);
2192 emit_d8(cbuf,$cnt$$constant);
2193 %}
2195 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2196 emit_opcode( cbuf, 0x8B ); // Move
2197 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2198 emit_d8(cbuf,$primary);
2199 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2200 emit_d8(cbuf,$cnt$$constant-32);
2201 emit_d8(cbuf,$primary);
2202 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2203 emit_d8(cbuf,31);
2204 %}
2206 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2207 int r1, r2;
2208 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2209 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2211 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2212 emit_rm(cbuf, 0x3, r1, r2);
2213 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2214 emit_opcode(cbuf,$primary);
2215 emit_rm(cbuf, 0x3, $secondary, r1);
2216 emit_d8(cbuf,$cnt$$constant-32);
2217 }
2218 emit_opcode(cbuf,0x33); // XOR r2,r2
2219 emit_rm(cbuf, 0x3, r2, r2);
2220 %}
2222 // Clone of RegMem but accepts an extra parameter to access each
2223 // half of a double in memory; it never needs relocation info.
2224 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2225 emit_opcode(cbuf,$opcode$$constant);
2226 int reg_encoding = $rm_reg$$reg;
2227 int base = $mem$$base;
2228 int index = $mem$$index;
2229 int scale = $mem$$scale;
2230 int displace = $mem$$disp + $disp_for_half$$constant;
2231 bool disp_is_oop = false;
2232 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2233 %}
2235 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2236 //
2237 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2238 // and it never needs relocation information.
2239 // Frequently used to move data between FPU's Stack Top and memory.
2240 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2241 int rm_byte_opcode = $rm_opcode$$constant;
2242 int base = $mem$$base;
2243 int index = $mem$$index;
2244 int scale = $mem$$scale;
2245 int displace = $mem$$disp;
2246 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2247 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2248 %}
2250 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2251 int rm_byte_opcode = $rm_opcode$$constant;
2252 int base = $mem$$base;
2253 int index = $mem$$index;
2254 int scale = $mem$$scale;
2255 int displace = $mem$$disp;
2256 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2257 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2258 %}
2260 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2261 int reg_encoding = $dst$$reg;
2262 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2263 int index = 0x04; // 0x04 indicates no index
2264 int scale = 0x00; // 0x00 indicates no scale
2265 int displace = $src1$$constant; // 0x00 indicates no displacement
2266 bool disp_is_oop = false;
2267 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2268 %}
2270 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2271 // Compare dst,src
2272 emit_opcode(cbuf,0x3B);
2273 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2274 // jmp dst < src around move
2275 emit_opcode(cbuf,0x7C);
2276 emit_d8(cbuf,2);
2277 // move dst,src
2278 emit_opcode(cbuf,0x8B);
2279 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2280 %}
2282 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2283 // Compare dst,src
2284 emit_opcode(cbuf,0x3B);
2285 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2286 // jmp dst > src around move
2287 emit_opcode(cbuf,0x7F);
2288 emit_d8(cbuf,2);
2289 // move dst,src
2290 emit_opcode(cbuf,0x8B);
2291 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2292 %}
2294 enc_class enc_FP_store(memory mem, regD src) %{
2295 // If src is FPR1, we can just FST to store it.
2296 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2297 int reg_encoding = 0x2; // Just store
2298 int base = $mem$$base;
2299 int index = $mem$$index;
2300 int scale = $mem$$scale;
2301 int displace = $mem$$disp;
2302 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2303 if( $src$$reg != FPR1L_enc ) {
2304 reg_encoding = 0x3; // Store & pop
2305 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2306 emit_d8( cbuf, 0xC0-1+$src$$reg );
2307 }
2308 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2309 emit_opcode(cbuf,$primary);
2310 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2311 %}
2313 enc_class neg_reg(eRegI dst) %{
2314 // NEG $dst
2315 emit_opcode(cbuf,0xF7);
2316 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2317 %}
2319 enc_class setLT_reg(eCXRegI dst) %{
2320 // SETLT $dst
2321 emit_opcode(cbuf,0x0F);
2322 emit_opcode(cbuf,0x9C);
2323 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2324 %}
2326 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2327 int tmpReg = $tmp$$reg;
2329 // SUB $p,$q
2330 emit_opcode(cbuf,0x2B);
2331 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2332 // SBB $tmp,$tmp
2333 emit_opcode(cbuf,0x1B);
2334 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2335 // AND $tmp,$y
2336 emit_opcode(cbuf,0x23);
2337 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2338 // ADD $p,$tmp
2339 emit_opcode(cbuf,0x03);
2340 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2341 %}
2343 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2344 int tmpReg = $tmp$$reg;
2346 // SUB $p,$q
2347 emit_opcode(cbuf,0x2B);
2348 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2349 // SBB $tmp,$tmp
2350 emit_opcode(cbuf,0x1B);
2351 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2352 // AND $tmp,$y
2353 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2354 emit_opcode(cbuf,0x23);
2355 int reg_encoding = tmpReg;
2356 int base = $mem$$base;
2357 int index = $mem$$index;
2358 int scale = $mem$$scale;
2359 int displace = $mem$$disp;
2360 bool disp_is_oop = $mem->disp_is_oop();
2361 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2362 // ADD $p,$tmp
2363 emit_opcode(cbuf,0x03);
2364 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2365 %}
2367 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2368 // TEST shift,32
2369 emit_opcode(cbuf,0xF7);
2370 emit_rm(cbuf, 0x3, 0, ECX_enc);
2371 emit_d32(cbuf,0x20);
2372 // JEQ,s small
2373 emit_opcode(cbuf, 0x74);
2374 emit_d8(cbuf, 0x04);
2375 // MOV $dst.hi,$dst.lo
2376 emit_opcode( cbuf, 0x8B );
2377 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2378 // CLR $dst.lo
2379 emit_opcode(cbuf, 0x33);
2380 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2381 // small:
2382 // SHLD $dst.hi,$dst.lo,$shift
2383 emit_opcode(cbuf,0x0F);
2384 emit_opcode(cbuf,0xA5);
2385 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2386 // SHL $dst.lo,$shift"
2387 emit_opcode(cbuf,0xD3);
2388 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2389 %}
2391 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2392 // TEST shift,32
2393 emit_opcode(cbuf,0xF7);
2394 emit_rm(cbuf, 0x3, 0, ECX_enc);
2395 emit_d32(cbuf,0x20);
2396 // JEQ,s small
2397 emit_opcode(cbuf, 0x74);
2398 emit_d8(cbuf, 0x04);
2399 // MOV $dst.lo,$dst.hi
2400 emit_opcode( cbuf, 0x8B );
2401 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2402 // CLR $dst.hi
2403 emit_opcode(cbuf, 0x33);
2404 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2405 // small:
2406 // SHRD $dst.lo,$dst.hi,$shift
2407 emit_opcode(cbuf,0x0F);
2408 emit_opcode(cbuf,0xAD);
2409 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2410 // SHR $dst.hi,$shift"
2411 emit_opcode(cbuf,0xD3);
2412 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2413 %}
2415 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2416 // TEST shift,32
2417 emit_opcode(cbuf,0xF7);
2418 emit_rm(cbuf, 0x3, 0, ECX_enc);
2419 emit_d32(cbuf,0x20);
2420 // JEQ,s small
2421 emit_opcode(cbuf, 0x74);
2422 emit_d8(cbuf, 0x05);
2423 // MOV $dst.lo,$dst.hi
2424 emit_opcode( cbuf, 0x8B );
2425 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2426 // SAR $dst.hi,31
2427 emit_opcode(cbuf, 0xC1);
2428 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2429 emit_d8(cbuf, 0x1F );
2430 // small:
2431 // SHRD $dst.lo,$dst.hi,$shift
2432 emit_opcode(cbuf,0x0F);
2433 emit_opcode(cbuf,0xAD);
2434 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2435 // SAR $dst.hi,$shift"
2436 emit_opcode(cbuf,0xD3);
2437 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2438 %}
2441 // ----------------- Encodings for floating point unit -----------------
2442 // May leave result in FPU-TOS or FPU reg depending on opcodes
2443 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2444 $$$emit8$primary;
2445 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2446 %}
2448 // Pop argument in FPR0 with FSTP ST(0)
2449 enc_class PopFPU() %{
2450 emit_opcode( cbuf, 0xDD );
2451 emit_d8( cbuf, 0xD8 );
2452 %}
2454 // !!!!! equivalent to Pop_Reg_F
2455 enc_class Pop_Reg_D( regD dst ) %{
2456 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2457 emit_d8( cbuf, 0xD8+$dst$$reg );
2458 %}
2460 enc_class Push_Reg_D( regD dst ) %{
2461 emit_opcode( cbuf, 0xD9 );
2462 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2463 %}
2465 enc_class strictfp_bias1( regD dst ) %{
2466 emit_opcode( cbuf, 0xDB ); // FLD m80real
2467 emit_opcode( cbuf, 0x2D );
2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2470 emit_opcode( cbuf, 0xC8+$dst$$reg );
2471 %}
2473 enc_class strictfp_bias2( regD dst ) %{
2474 emit_opcode( cbuf, 0xDB ); // FLD m80real
2475 emit_opcode( cbuf, 0x2D );
2476 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2477 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2478 emit_opcode( cbuf, 0xC8+$dst$$reg );
2479 %}
2481 // Special case for moving an integer register to a stack slot.
2482 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2483 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2484 %}
2486 // Special case for moving a register to a stack slot.
2487 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2488 // Opcode already emitted
2489 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2490 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2491 emit_d32(cbuf, $dst$$disp); // Displacement
2492 %}
2494 // Push the integer in stackSlot 'src' onto FP-stack
2495 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2496 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2497 %}
2499 // Push the float in stackSlot 'src' onto FP-stack
2500 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2501 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2502 %}
2504 // Push the double in stackSlot 'src' onto FP-stack
2505 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2506 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2507 %}
2509 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2510 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2511 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2512 %}
2514 // Same as Pop_Mem_F except for opcode
2515 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2516 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2517 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2518 %}
2520 enc_class Pop_Reg_F( regF dst ) %{
2521 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2522 emit_d8( cbuf, 0xD8+$dst$$reg );
2523 %}
2525 enc_class Push_Reg_F( regF dst ) %{
2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2527 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2528 %}
2530 // Push FPU's float to a stack-slot, and pop FPU-stack
2531 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2532 int pop = 0x02;
2533 if ($src$$reg != FPR1L_enc) {
2534 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2535 emit_d8( cbuf, 0xC0-1+$src$$reg );
2536 pop = 0x03;
2537 }
2538 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2539 %}
2541 // Push FPU's double to a stack-slot, and pop FPU-stack
2542 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2543 int pop = 0x02;
2544 if ($src$$reg != FPR1L_enc) {
2545 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2546 emit_d8( cbuf, 0xC0-1+$src$$reg );
2547 pop = 0x03;
2548 }
2549 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2550 %}
2552 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2553 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2554 int pop = 0xD0 - 1; // -1 since we skip FLD
2555 if ($src$$reg != FPR1L_enc) {
2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2557 emit_d8( cbuf, 0xC0-1+$src$$reg );
2558 pop = 0xD8;
2559 }
2560 emit_opcode( cbuf, 0xDD );
2561 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2562 %}
2565 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2566 MacroAssembler masm(&cbuf);
2567 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2568 masm.fmul( $src2$$reg+0); // value at TOS
2569 masm.fadd( $src$$reg+0); // value at TOS
2570 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2571 %}
2574 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2575 // load dst in FPR0
2576 emit_opcode( cbuf, 0xD9 );
2577 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2578 if ($src$$reg != FPR1L_enc) {
2579 // fincstp
2580 emit_opcode (cbuf, 0xD9);
2581 emit_opcode (cbuf, 0xF7);
2582 // swap src with FPR1:
2583 // FXCH FPR1 with src
2584 emit_opcode(cbuf, 0xD9);
2585 emit_d8(cbuf, 0xC8-1+$src$$reg );
2586 // fdecstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF6);
2589 }
2590 %}
2592 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2593 // Allocate a word
2594 emit_opcode(cbuf,0x83); // SUB ESP,8
2595 emit_opcode(cbuf,0xEC);
2596 emit_d8(cbuf,0x08);
2598 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2599 emit_opcode (cbuf, 0x0F );
2600 emit_opcode (cbuf, 0x11 );
2601 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2603 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2604 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2606 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2607 emit_opcode (cbuf, 0x0F );
2608 emit_opcode (cbuf, 0x11 );
2609 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2611 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2612 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2614 %}
2616 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2617 // Allocate a word
2618 emit_opcode(cbuf,0x83); // SUB ESP,4
2619 emit_opcode(cbuf,0xEC);
2620 emit_d8(cbuf,0x04);
2622 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2623 emit_opcode (cbuf, 0x0F );
2624 emit_opcode (cbuf, 0x11 );
2625 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2627 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2628 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2630 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2631 emit_opcode (cbuf, 0x0F );
2632 emit_opcode (cbuf, 0x11 );
2633 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2635 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2636 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2638 %}
2640 enc_class Push_ResultXD(regXD dst) %{
2641 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2643 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2644 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2645 emit_opcode (cbuf, 0x0F );
2646 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2647 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2649 emit_opcode(cbuf,0x83); // ADD ESP,8
2650 emit_opcode(cbuf,0xC4);
2651 emit_d8(cbuf,0x08);
2652 %}
2654 enc_class Push_ResultX(regX dst, immI d8) %{
2655 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2657 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2658 emit_opcode (cbuf, 0x0F );
2659 emit_opcode (cbuf, 0x10 );
2660 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2662 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2663 emit_opcode(cbuf,0xC4);
2664 emit_d8(cbuf,$d8$$constant);
2665 %}
2667 enc_class Push_SrcXD(regXD src) %{
2668 // Allocate a word
2669 emit_opcode(cbuf,0x83); // SUB ESP,8
2670 emit_opcode(cbuf,0xEC);
2671 emit_d8(cbuf,0x08);
2673 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2674 emit_opcode (cbuf, 0x0F );
2675 emit_opcode (cbuf, 0x11 );
2676 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2678 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2679 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2680 %}
2682 enc_class push_stack_temp_qword() %{
2683 emit_opcode(cbuf,0x83); // SUB ESP,8
2684 emit_opcode(cbuf,0xEC);
2685 emit_d8 (cbuf,0x08);
2686 %}
2688 enc_class pop_stack_temp_qword() %{
2689 emit_opcode(cbuf,0x83); // ADD ESP,8
2690 emit_opcode(cbuf,0xC4);
2691 emit_d8 (cbuf,0x08);
2692 %}
2694 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2695 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2696 emit_opcode (cbuf, 0x0F );
2697 emit_opcode (cbuf, 0x11 );
2698 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2700 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2701 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2702 %}
2704 // Compute X^Y using Intel's fast hardware instructions, if possible.
2705 // Otherwise return a NaN.
2706 enc_class pow_exp_core_encoding %{
2707 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2708 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2710 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2711 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2712 emit_opcode(cbuf,0x1C);
2713 emit_d8(cbuf,0x24);
2714 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2716 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2717 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2718 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2719 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2720 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2721 emit_d32(cbuf,0xFFFFF800);
2722 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2723 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2724 emit_d32(cbuf,1023);
2725 emit_opcode(cbuf,0x8B); // mov rbx,eax
2726 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2727 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2728 emit_rm(cbuf,0x3,0x4,EAX_enc);
2729 emit_d8(cbuf,20);
2730 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2731 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2732 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2733 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2734 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2735 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2736 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2737 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2738 emit_d32(cbuf,0);
2739 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2740 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2741 %}
2743 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2744 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2746 enc_class Push_Result_Mod_D( regD src) %{
2747 if ($src$$reg != FPR1L_enc) {
2748 // fincstp
2749 emit_opcode (cbuf, 0xD9);
2750 emit_opcode (cbuf, 0xF7);
2751 // FXCH FPR1 with src
2752 emit_opcode(cbuf, 0xD9);
2753 emit_d8(cbuf, 0xC8-1+$src$$reg );
2754 // fdecstp
2755 emit_opcode (cbuf, 0xD9);
2756 emit_opcode (cbuf, 0xF6);
2757 }
2758 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2759 // // FSTP FPR$dst$$reg
2760 // emit_opcode( cbuf, 0xDD );
2761 // emit_d8( cbuf, 0xD8+$dst$$reg );
2762 %}
2764 enc_class fnstsw_sahf_skip_parity() %{
2765 // fnstsw ax
2766 emit_opcode( cbuf, 0xDF );
2767 emit_opcode( cbuf, 0xE0 );
2768 // sahf
2769 emit_opcode( cbuf, 0x9E );
2770 // jnp ::skip
2771 emit_opcode( cbuf, 0x7B );
2772 emit_opcode( cbuf, 0x05 );
2773 %}
2775 enc_class emitModD() %{
2776 // fprem must be iterative
2777 // :: loop
2778 // fprem
2779 emit_opcode( cbuf, 0xD9 );
2780 emit_opcode( cbuf, 0xF8 );
2781 // wait
2782 emit_opcode( cbuf, 0x9b );
2783 // fnstsw ax
2784 emit_opcode( cbuf, 0xDF );
2785 emit_opcode( cbuf, 0xE0 );
2786 // sahf
2787 emit_opcode( cbuf, 0x9E );
2788 // jp ::loop
2789 emit_opcode( cbuf, 0x0F );
2790 emit_opcode( cbuf, 0x8A );
2791 emit_opcode( cbuf, 0xF4 );
2792 emit_opcode( cbuf, 0xFF );
2793 emit_opcode( cbuf, 0xFF );
2794 emit_opcode( cbuf, 0xFF );
2795 %}
2797 enc_class fpu_flags() %{
2798 // fnstsw_ax
2799 emit_opcode( cbuf, 0xDF);
2800 emit_opcode( cbuf, 0xE0);
2801 // test ax,0x0400
2802 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2803 emit_opcode( cbuf, 0xA9 );
2804 emit_d16 ( cbuf, 0x0400 );
2805 // // // This sequence works, but stalls for 12-16 cycles on PPro
2806 // // test rax,0x0400
2807 // emit_opcode( cbuf, 0xA9 );
2808 // emit_d32 ( cbuf, 0x00000400 );
2809 //
2810 // jz exit (no unordered comparison)
2811 emit_opcode( cbuf, 0x74 );
2812 emit_d8 ( cbuf, 0x02 );
2813 // mov ah,1 - treat as LT case (set carry flag)
2814 emit_opcode( cbuf, 0xB4 );
2815 emit_d8 ( cbuf, 0x01 );
2816 // sahf
2817 emit_opcode( cbuf, 0x9E);
2818 %}
2820 enc_class cmpF_P6_fixup() %{
2821 // Fixup the integer flags in case comparison involved a NaN
2822 //
2823 // JNP exit (no unordered comparison, P-flag is set by NaN)
2824 emit_opcode( cbuf, 0x7B );
2825 emit_d8 ( cbuf, 0x03 );
2826 // MOV AH,1 - treat as LT case (set carry flag)
2827 emit_opcode( cbuf, 0xB4 );
2828 emit_d8 ( cbuf, 0x01 );
2829 // SAHF
2830 emit_opcode( cbuf, 0x9E);
2831 // NOP // target for branch to avoid branch to branch
2832 emit_opcode( cbuf, 0x90);
2833 %}
2835 // fnstsw_ax();
2836 // sahf();
2837 // movl(dst, nan_result);
2838 // jcc(Assembler::parity, exit);
2839 // movl(dst, less_result);
2840 // jcc(Assembler::below, exit);
2841 // movl(dst, equal_result);
2842 // jcc(Assembler::equal, exit);
2843 // movl(dst, greater_result);
2845 // less_result = 1;
2846 // greater_result = -1;
2847 // equal_result = 0;
2848 // nan_result = -1;
2850 enc_class CmpF_Result(eRegI dst) %{
2851 // fnstsw_ax();
2852 emit_opcode( cbuf, 0xDF);
2853 emit_opcode( cbuf, 0xE0);
2854 // sahf
2855 emit_opcode( cbuf, 0x9E);
2856 // movl(dst, nan_result);
2857 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2858 emit_d32( cbuf, -1 );
2859 // jcc(Assembler::parity, exit);
2860 emit_opcode( cbuf, 0x7A );
2861 emit_d8 ( cbuf, 0x13 );
2862 // movl(dst, less_result);
2863 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2864 emit_d32( cbuf, -1 );
2865 // jcc(Assembler::below, exit);
2866 emit_opcode( cbuf, 0x72 );
2867 emit_d8 ( cbuf, 0x0C );
2868 // movl(dst, equal_result);
2869 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2870 emit_d32( cbuf, 0 );
2871 // jcc(Assembler::equal, exit);
2872 emit_opcode( cbuf, 0x74 );
2873 emit_d8 ( cbuf, 0x05 );
2874 // movl(dst, greater_result);
2875 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2876 emit_d32( cbuf, 1 );
2877 %}
2880 // XMM version of CmpF_Result. Because the XMM compare
2881 // instructions set the EFLAGS directly. It becomes simpler than
2882 // the float version above.
2883 enc_class CmpX_Result(eRegI dst) %{
2884 MacroAssembler _masm(&cbuf);
2885 Label nan, inc, done;
2887 __ jccb(Assembler::parity, nan);
2888 __ jccb(Assembler::equal, done);
2889 __ jccb(Assembler::above, inc);
2890 __ bind(nan);
2891 __ decrement(as_Register($dst$$reg));
2892 __ jmpb(done);
2893 __ bind(inc);
2894 __ increment(as_Register($dst$$reg));
2895 __ bind(done);
2896 %}
2898 // Compare the longs and set flags
2899 // BROKEN! Do Not use as-is
2900 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2901 // CMP $src1.hi,$src2.hi
2902 emit_opcode( cbuf, 0x3B );
2903 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2904 // JNE,s done
2905 emit_opcode(cbuf,0x75);
2906 emit_d8(cbuf, 2 );
2907 // CMP $src1.lo,$src2.lo
2908 emit_opcode( cbuf, 0x3B );
2909 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2910 // done:
2911 %}
2913 enc_class convert_int_long( regL dst, eRegI src ) %{
2914 // mov $dst.lo,$src
2915 int dst_encoding = $dst$$reg;
2916 int src_encoding = $src$$reg;
2917 encode_Copy( cbuf, dst_encoding , src_encoding );
2918 // mov $dst.hi,$src
2919 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2920 // sar $dst.hi,31
2921 emit_opcode( cbuf, 0xC1 );
2922 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2923 emit_d8(cbuf, 0x1F );
2924 %}
2926 enc_class convert_long_double( eRegL src ) %{
2927 // push $src.hi
2928 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2929 // push $src.lo
2930 emit_opcode(cbuf, 0x50+$src$$reg );
2931 // fild 64-bits at [SP]
2932 emit_opcode(cbuf,0xdf);
2933 emit_d8(cbuf, 0x6C);
2934 emit_d8(cbuf, 0x24);
2935 emit_d8(cbuf, 0x00);
2936 // pop stack
2937 emit_opcode(cbuf, 0x83); // add SP, #8
2938 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2939 emit_d8(cbuf, 0x8);
2940 %}
2942 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2943 // IMUL EDX:EAX,$src1
2944 emit_opcode( cbuf, 0xF7 );
2945 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2946 // SAR EDX,$cnt-32
2947 int shift_count = ((int)$cnt$$constant) - 32;
2948 if (shift_count > 0) {
2949 emit_opcode(cbuf, 0xC1);
2950 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2951 emit_d8(cbuf, shift_count);
2952 }
2953 %}
2955 // this version doesn't have add sp, 8
2956 enc_class convert_long_double2( eRegL src ) %{
2957 // push $src.hi
2958 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2959 // push $src.lo
2960 emit_opcode(cbuf, 0x50+$src$$reg );
2961 // fild 64-bits at [SP]
2962 emit_opcode(cbuf,0xdf);
2963 emit_d8(cbuf, 0x6C);
2964 emit_d8(cbuf, 0x24);
2965 emit_d8(cbuf, 0x00);
2966 %}
2968 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2969 // Basic idea: long = (long)int * (long)int
2970 // IMUL EDX:EAX, src
2971 emit_opcode( cbuf, 0xF7 );
2972 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2973 %}
2975 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2977 // MUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2980 %}
2982 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2983 // Basic idea: lo(result) = lo(x_lo * y_lo)
2984 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2985 // MOV $tmp,$src.lo
2986 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2987 // IMUL $tmp,EDX
2988 emit_opcode( cbuf, 0x0F );
2989 emit_opcode( cbuf, 0xAF );
2990 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2991 // MOV EDX,$src.hi
2992 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2993 // IMUL EDX,EAX
2994 emit_opcode( cbuf, 0x0F );
2995 emit_opcode( cbuf, 0xAF );
2996 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2997 // ADD $tmp,EDX
2998 emit_opcode( cbuf, 0x03 );
2999 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3000 // MUL EDX:EAX,$src.lo
3001 emit_opcode( cbuf, 0xF7 );
3002 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3003 // ADD EDX,ESI
3004 emit_opcode( cbuf, 0x03 );
3005 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3006 %}
3008 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3009 // Basic idea: lo(result) = lo(src * y_lo)
3010 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3011 // IMUL $tmp,EDX,$src
3012 emit_opcode( cbuf, 0x6B );
3013 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3014 emit_d8( cbuf, (int)$src$$constant );
3015 // MOV EDX,$src
3016 emit_opcode(cbuf, 0xB8 + EDX_enc);
3017 emit_d32( cbuf, (int)$src$$constant );
3018 // MUL EDX:EAX,EDX
3019 emit_opcode( cbuf, 0xF7 );
3020 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3021 // ADD EDX,ESI
3022 emit_opcode( cbuf, 0x03 );
3023 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3024 %}
3026 enc_class long_div( eRegL src1, eRegL src2 ) %{
3027 // PUSH src1.hi
3028 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3029 // PUSH src1.lo
3030 emit_opcode(cbuf, 0x50+$src1$$reg );
3031 // PUSH src2.hi
3032 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3033 // PUSH src2.lo
3034 emit_opcode(cbuf, 0x50+$src2$$reg );
3035 // CALL directly to the runtime
3036 cbuf.set_inst_mark();
3037 emit_opcode(cbuf,0xE8); // Call into runtime
3038 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3039 // Restore stack
3040 emit_opcode(cbuf, 0x83); // add SP, #framesize
3041 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3042 emit_d8(cbuf, 4*4);
3043 %}
3045 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3046 // PUSH src1.hi
3047 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3048 // PUSH src1.lo
3049 emit_opcode(cbuf, 0x50+$src1$$reg );
3050 // PUSH src2.hi
3051 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3052 // PUSH src2.lo
3053 emit_opcode(cbuf, 0x50+$src2$$reg );
3054 // CALL directly to the runtime
3055 cbuf.set_inst_mark();
3056 emit_opcode(cbuf,0xE8); // Call into runtime
3057 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3058 // Restore stack
3059 emit_opcode(cbuf, 0x83); // add SP, #framesize
3060 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3061 emit_d8(cbuf, 4*4);
3062 %}
3064 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3065 // MOV $tmp,$src.lo
3066 emit_opcode(cbuf, 0x8B);
3067 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3068 // OR $tmp,$src.hi
3069 emit_opcode(cbuf, 0x0B);
3070 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3071 %}
3073 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3074 // CMP $src1.lo,$src2.lo
3075 emit_opcode( cbuf, 0x3B );
3076 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3077 // JNE,s skip
3078 emit_cc(cbuf, 0x70, 0x5);
3079 emit_d8(cbuf,2);
3080 // CMP $src1.hi,$src2.hi
3081 emit_opcode( cbuf, 0x3B );
3082 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3083 %}
3085 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3086 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3087 emit_opcode( cbuf, 0x3B );
3088 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3089 // MOV $tmp,$src1.hi
3090 emit_opcode( cbuf, 0x8B );
3091 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3092 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3093 emit_opcode( cbuf, 0x1B );
3094 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3095 %}
3097 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3098 // XOR $tmp,$tmp
3099 emit_opcode(cbuf,0x33); // XOR
3100 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3101 // CMP $tmp,$src.lo
3102 emit_opcode( cbuf, 0x3B );
3103 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3104 // SBB $tmp,$src.hi
3105 emit_opcode( cbuf, 0x1B );
3106 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3107 %}
3109 // Sniff, sniff... smells like Gnu Superoptimizer
3110 enc_class neg_long( eRegL dst ) %{
3111 emit_opcode(cbuf,0xF7); // NEG hi
3112 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3113 emit_opcode(cbuf,0xF7); // NEG lo
3114 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3115 emit_opcode(cbuf,0x83); // SBB hi,0
3116 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3117 emit_d8 (cbuf,0 );
3118 %}
3120 enc_class movq_ld(regXD dst, memory mem) %{
3121 MacroAssembler _masm(&cbuf);
3122 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3123 __ movq(as_XMMRegister($dst$$reg), madr);
3124 %}
3126 enc_class movq_st(memory mem, regXD src) %{
3127 MacroAssembler _masm(&cbuf);
3128 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3129 __ movq(madr, as_XMMRegister($src$$reg));
3130 %}
3132 enc_class pshufd_8x8(regX dst, regX src) %{
3133 MacroAssembler _masm(&cbuf);
3135 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3136 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3137 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3138 %}
3140 enc_class pshufd_4x16(regX dst, regX src) %{
3141 MacroAssembler _masm(&cbuf);
3143 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3144 %}
3146 enc_class pshufd(regXD dst, regXD src, int mode) %{
3147 MacroAssembler _masm(&cbuf);
3149 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3150 %}
3152 enc_class pxor(regXD dst, regXD src) %{
3153 MacroAssembler _masm(&cbuf);
3155 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3156 %}
3158 enc_class mov_i2x(regXD dst, eRegI src) %{
3159 MacroAssembler _masm(&cbuf);
3161 __ movd(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3162 %}
3165 // Because the transitions from emitted code to the runtime
3166 // monitorenter/exit helper stubs are so slow it's critical that
3167 // we inline both the stack-locking fast-path and the inflated fast path.
3168 //
3169 // See also: cmpFastLock and cmpFastUnlock.
3170 //
3171 // What follows is a specialized inline transliteration of the code
3172 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3173 // another option would be to emit TrySlowEnter and TrySlowExit methods
3174 // at startup-time. These methods would accept arguments as
3175 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3176 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3177 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3178 // In practice, however, the # of lock sites is bounded and is usually small.
3179 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3180 // if the processor uses simple bimodal branch predictors keyed by EIP
3181 // Since the helper routines would be called from multiple synchronization
3182 // sites.
3183 //
3184 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3185 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3186 // to those specialized methods. That'd give us a mostly platform-independent
3187 // implementation that the JITs could optimize and inline at their pleasure.
3188 // Done correctly, the only time we'd need to cross to native could would be
3189 // to park() or unpark() threads. We'd also need a few more unsafe operators
3190 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3191 // (b) explicit barriers or fence operations.
3192 //
3193 // TODO:
3194 //
3195 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3196 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3197 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3198 // the lock operators would typically be faster than reifying Self.
3199 //
3200 // * Ideally I'd define the primitives as:
3201 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3202 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3203 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3204 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3205 // Furthermore the register assignments are overconstrained, possibly resulting in
3206 // sub-optimal code near the synchronization site.
3207 //
3208 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3209 // Alternately, use a better sp-proximity test.
3210 //
3211 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3212 // Either one is sufficient to uniquely identify a thread.
3213 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3214 //
3215 // * Intrinsify notify() and notifyAll() for the common cases where the
3216 // object is locked by the calling thread but the waitlist is empty.
3217 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3218 //
3219 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3220 // But beware of excessive branch density on AMD Opterons.
3221 //
3222 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3223 // or failure of the fast-path. If the fast-path fails then we pass
3224 // control to the slow-path, typically in C. In Fast_Lock and
3225 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3226 // will emit a conditional branch immediately after the node.
3227 // So we have branches to branches and lots of ICC.ZF games.
3228 // Instead, it might be better to have C2 pass a "FailureLabel"
3229 // into Fast_Lock and Fast_Unlock. In the case of success, control
3230 // will drop through the node. ICC.ZF is undefined at exit.
3231 // In the case of failure, the node will branch directly to the
3232 // FailureLabel
3235 // obj: object to lock
3236 // box: on-stack box address (displaced header location) - KILLED
3237 // rax,: tmp -- KILLED
3238 // scr: tmp -- KILLED
3239 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3241 Register objReg = as_Register($obj$$reg);
3242 Register boxReg = as_Register($box$$reg);
3243 Register tmpReg = as_Register($tmp$$reg);
3244 Register scrReg = as_Register($scr$$reg);
3246 // Ensure the register assignents are disjoint
3247 guarantee (objReg != boxReg, "") ;
3248 guarantee (objReg != tmpReg, "") ;
3249 guarantee (objReg != scrReg, "") ;
3250 guarantee (boxReg != tmpReg, "") ;
3251 guarantee (boxReg != scrReg, "") ;
3252 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3254 MacroAssembler masm(&cbuf);
3256 if (_counters != NULL) {
3257 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3258 }
3259 if (EmitSync & 1) {
3260 // set box->dhw = unused_mark (3)
3261 // Force all sync thru slow-path: slow_enter() and slow_exit()
3262 masm.movl (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
3263 masm.cmpl (rsp, 0) ;
3264 } else
3265 if (EmitSync & 2) {
3266 Label DONE_LABEL ;
3267 if (UseBiasedLocking) {
3268 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3269 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3270 }
3272 masm.movl (tmpReg, Address(objReg, 0)) ; // fetch markword
3273 masm.orl (tmpReg, 0x1);
3274 masm.movl (Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3275 if (os::is_MP()) { masm.lock(); }
3276 masm.cmpxchg(boxReg, Address(objReg, 0)); // Updates tmpReg
3277 masm.jcc(Assembler::equal, DONE_LABEL);
3278 // Recursive locking
3279 masm.subl(tmpReg, rsp);
3280 masm.andl(tmpReg, 0xFFFFF003 );
3281 masm.movl(Address(boxReg, 0), tmpReg);
3282 masm.bind(DONE_LABEL) ;
3283 } else {
3284 // Possible cases that we'll encounter in fast_lock
3285 // ------------------------------------------------
3286 // * Inflated
3287 // -- unlocked
3288 // -- Locked
3289 // = by self
3290 // = by other
3291 // * biased
3292 // -- by Self
3293 // -- by other
3294 // * neutral
3295 // * stack-locked
3296 // -- by self
3297 // = sp-proximity test hits
3298 // = sp-proximity test generates false-negative
3299 // -- by other
3300 //
3302 Label IsInflated, DONE_LABEL, PopDone ;
3304 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3305 // order to reduce the number of conditional branches in the most common cases.
3306 // Beware -- there's a subtle invariant that fetch of the markword
3307 // at [FETCH], below, will never observe a biased encoding (*101b).
3308 // If this invariant is not held we risk exclusion (safety) failure.
3309 if (UseBiasedLocking) {
3310 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3311 }
3313 masm.movl (tmpReg, Address(objReg, 0)) ; // [FETCH]
3314 masm.testl (tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3315 masm.jccb (Assembler::notZero, IsInflated) ;
3317 // Attempt stack-locking ...
3318 masm.orl (tmpReg, 0x1);
3319 masm.movl (Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3320 if (os::is_MP()) { masm.lock(); }
3321 masm.cmpxchg(boxReg, Address(objReg, 0)); // Updates tmpReg
3322 if (_counters != NULL) {
3323 masm.cond_inc32(Assembler::equal,
3324 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3325 }
3326 masm.jccb (Assembler::equal, DONE_LABEL);
3328 // Recursive locking
3329 masm.subl(tmpReg, rsp);
3330 masm.andl(tmpReg, 0xFFFFF003 );
3331 masm.movl(Address(boxReg, 0), tmpReg);
3332 if (_counters != NULL) {
3333 masm.cond_inc32(Assembler::equal,
3334 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3335 }
3336 masm.jmp (DONE_LABEL) ;
3338 masm.bind (IsInflated) ;
3340 // The object is inflated.
3341 //
3342 // TODO-FIXME: eliminate the ugly use of manifest constants:
3343 // Use markOopDesc::monitor_value instead of "2".
3344 // use markOop::unused_mark() instead of "3".
3345 // The tmpReg value is an objectMonitor reference ORed with
3346 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3347 // objectmonitor pointer by masking off the "2" bit or we can just
3348 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3349 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3350 //
3351 // I use the latter as it avoids AGI stalls.
3352 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3353 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3354 //
3355 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3357 // boxReg refers to the on-stack BasicLock in the current frame.
3358 // We'd like to write:
3359 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3360 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3361 // additional latency as we have another ST in the store buffer that must drain.
3363 if (EmitSync & 8192) {
3364 masm.movl (Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3365 masm.get_thread (scrReg) ;
3366 masm.movl (boxReg, tmpReg); // consider: LEA box, [tmp-2]
3367 masm.movl (tmpReg, 0); // consider: xor vs mov
3368 if (os::is_MP()) { masm.lock(); }
3369 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3370 } else
3371 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3372 masm.movl (scrReg, boxReg) ;
3373 masm.movl (boxReg, tmpReg); // consider: LEA box, [tmp-2]
3375 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3376 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3377 // prefetchw [eax + Offset(_owner)-2]
3378 masm.emit_raw (0x0F) ;
3379 masm.emit_raw (0x0D) ;
3380 masm.emit_raw (0x48) ;
3381 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ;
3382 }
3384 if ((EmitSync & 64) == 0) {
3385 // Optimistic form: consider XORL tmpReg,tmpReg
3386 masm.movl (tmpReg, 0 ) ;
3387 } else {
3388 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3389 // Test-And-CAS instead of CAS
3390 masm.movl (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3391 masm.testl (tmpReg, tmpReg) ; // Locked ?
3392 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3393 }
3395 // Appears unlocked - try to swing _owner from null to non-null.
3396 // Ideally, I'd manifest "Self" with get_thread and then attempt
3397 // to CAS the register containing Self into m->Owner.
3398 // But we don't have enough registers, so instead we can either try to CAS
3399 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3400 // we later store "Self" into m->Owner. Transiently storing a stack address
3401 // (rsp or the address of the box) into m->owner is harmless.
3402 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3403 if (os::is_MP()) { masm.lock(); }
3404 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3405 masm.movl (Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3406 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3407 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3408 masm.movl (Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3409 masm.xorl (boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3411 // If the CAS fails we can either retry or pass control to the slow-path.
3412 // We use the latter tactic.
3413 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3414 // If the CAS was successful ...
3415 // Self has acquired the lock
3416 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3417 // Intentional fall-through into DONE_LABEL ...
3418 } else {
3419 masm.movl (Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3420 masm.movl (boxReg, tmpReg) ;
3422 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3423 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3424 // prefetchw [eax + Offset(_owner)-2]
3425 masm.emit_raw (0x0F) ;
3426 masm.emit_raw (0x0D) ;
3427 masm.emit_raw (0x48) ;
3428 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ;
3429 }
3431 if ((EmitSync & 64) == 0) {
3432 // Optimistic form
3433 masm.xorl (tmpReg, tmpReg) ;
3434 } else {
3435 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3436 masm.movl (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3437 masm.testl (tmpReg, tmpReg) ; // Locked ?
3438 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3439 }
3441 // Appears unlocked - try to swing _owner from null to non-null.
3442 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3443 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3444 masm.get_thread (scrReg) ;
3445 if (os::is_MP()) { masm.lock(); }
3446 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3448 // If the CAS fails we can either retry or pass control to the slow-path.
3449 // We use the latter tactic.
3450 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3451 // If the CAS was successful ...
3452 // Self has acquired the lock
3453 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3454 // Intentional fall-through into DONE_LABEL ...
3455 }
3457 // DONE_LABEL is a hot target - we'd really like to place it at the
3458 // start of cache line by padding with NOPs.
3459 // See the AMD and Intel software optimization manuals for the
3460 // most efficient "long" NOP encodings.
3461 // Unfortunately none of our alignment mechanisms suffice.
3462 masm.bind(DONE_LABEL);
3464 // Avoid branch-to-branch on AMD processors
3465 // This appears to be superstition.
3466 if (EmitSync & 32) masm.nop() ;
3469 // At DONE_LABEL the icc ZFlag is set as follows ...
3470 // Fast_Unlock uses the same protocol.
3471 // ZFlag == 1 -> Success
3472 // ZFlag == 0 -> Failure - force control through the slow-path
3473 }
3474 %}
3476 // obj: object to unlock
3477 // box: box address (displaced header location), killed. Must be EAX.
3478 // rbx,: killed tmp; cannot be obj nor box.
3479 //
3480 // Some commentary on balanced locking:
3481 //
3482 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3483 // Methods that don't have provably balanced locking are forced to run in the
3484 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3485 // The interpreter provides two properties:
3486 // I1: At return-time the interpreter automatically and quietly unlocks any
3487 // objects acquired the current activation (frame). Recall that the
3488 // interpreter maintains an on-stack list of locks currently held by
3489 // a frame.
3490 // I2: If a method attempts to unlock an object that is not held by the
3491 // the frame the interpreter throws IMSX.
3492 //
3493 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3494 // B() doesn't have provably balanced locking so it runs in the interpreter.
3495 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3496 // is still locked by A().
3497 //
3498 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3499 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3500 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3501 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3503 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3505 Register objReg = as_Register($obj$$reg);
3506 Register boxReg = as_Register($box$$reg);
3507 Register tmpReg = as_Register($tmp$$reg);
3509 guarantee (objReg != boxReg, "") ;
3510 guarantee (objReg != tmpReg, "") ;
3511 guarantee (boxReg != tmpReg, "") ;
3512 guarantee (boxReg == as_Register(EAX_enc), "") ;
3513 MacroAssembler masm(&cbuf);
3515 if (EmitSync & 4) {
3516 // Disable - inhibit all inlining. Force control through the slow-path
3517 masm.cmpl (rsp, 0) ;
3518 } else
3519 if (EmitSync & 8) {
3520 Label DONE_LABEL ;
3521 if (UseBiasedLocking) {
3522 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3523 }
3524 // classic stack-locking code ...
3525 masm.movl (tmpReg, Address(boxReg, 0)) ;
3526 masm.testl (tmpReg, tmpReg) ;
3527 masm.jcc (Assembler::zero, DONE_LABEL) ;
3528 if (os::is_MP()) { masm.lock(); }
3529 masm.cmpxchg(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3530 masm.bind(DONE_LABEL);
3531 } else {
3532 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3534 // Critically, the biased locking test must have precedence over
3535 // and appear before the (box->dhw == 0) recursive stack-lock test.
3536 if (UseBiasedLocking) {
3537 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3538 }
3540 masm.cmpl (Address(boxReg, 0), 0) ; // Examine the displaced header
3541 masm.movl (tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3542 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3544 masm.testl (tmpReg, 0x02) ; // Inflated?
3545 masm.jccb (Assembler::zero, Stacked) ;
3547 masm.bind (Inflated) ;
3548 // It's inflated.
3549 // Despite our balanced locking property we still check that m->_owner == Self
3550 // as java routines or native JNI code called by this thread might
3551 // have released the lock.
3552 // Refer to the comments in synchronizer.cpp for how we might encode extra
3553 // state in _succ so we can avoid fetching EntryList|cxq.
3554 //
3555 // I'd like to add more cases in fast_lock() and fast_unlock() --
3556 // such as recursive enter and exit -- but we have to be wary of
3557 // I$ bloat, T$ effects and BP$ effects.
3558 //
3559 // If there's no contention try a 1-0 exit. That is, exit without
3560 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3561 // we detect and recover from the race that the 1-0 exit admits.
3562 //
3563 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3564 // before it STs null into _owner, releasing the lock. Updates
3565 // to data protected by the critical section must be visible before
3566 // we drop the lock (and thus before any other thread could acquire
3567 // the lock and observe the fields protected by the lock).
3568 // IA32's memory-model is SPO, so STs are ordered with respect to
3569 // each other and there's no need for an explicit barrier (fence).
3570 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3572 masm.get_thread (boxReg) ;
3573 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3574 // prefetchw [ebx + Offset(_owner)-2]
3575 masm.emit_raw (0x0F) ;
3576 masm.emit_raw (0x0D) ;
3577 masm.emit_raw (0x4B) ;
3578 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ;
3579 }
3581 // Note that we could employ various encoding schemes to reduce
3582 // the number of loads below (currently 4) to just 2 or 3.
3583 // Refer to the comments in synchronizer.cpp.
3584 // In practice the chain of fetches doesn't seem to impact performance, however.
3585 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3586 // Attempt to reduce branch density - AMD's branch predictor.
3587 masm.xorl (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3588 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3589 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3590 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3591 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3592 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3593 masm.jmpb (DONE_LABEL) ;
3594 } else {
3595 masm.xorl (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3596 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3597 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3598 masm.movl (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3599 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3600 masm.jccb (Assembler::notZero, CheckSucc) ;
3601 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3602 masm.jmpb (DONE_LABEL) ;
3603 }
3605 // The Following code fragment (EmitSync & 65536) improves the performance of
3606 // contended applications and contended synchronization microbenchmarks.
3607 // Unfortunately the emission of the code - even though not executed - causes regressions
3608 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3609 // with an equal number of never-executed NOPs results in the same regression.
3610 // We leave it off by default.
3612 if ((EmitSync & 65536) != 0) {
3613 Label LSuccess, LGoSlowPath ;
3615 masm.bind (CheckSucc) ;
3617 // Optional pre-test ... it's safe to elide this
3618 if ((EmitSync & 16) == 0) {
3619 masm.cmpl (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3620 masm.jccb (Assembler::zero, LGoSlowPath) ;
3621 }
3623 // We have a classic Dekker-style idiom:
3624 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3625 // There are a number of ways to implement the barrier:
3626 // (1) lock:andl &m->_owner, 0
3627 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3628 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3629 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3630 // (2) If supported, an explicit MFENCE is appealing.
3631 // In older IA32 processors MFENCE is slower than lock:add or xchg
3632 // particularly if the write-buffer is full as might be the case if
3633 // if stores closely precede the fence or fence-equivalent instruction.
3634 // In more modern implementations MFENCE appears faster, however.
3635 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3636 // The $lines underlying the top-of-stack should be in M-state.
3637 // The locked add instruction is serializing, of course.
3638 // (4) Use xchg, which is serializing
3639 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3640 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3641 // The integer condition codes will tell us if succ was 0.
3642 // Since _succ and _owner should reside in the same $line and
3643 // we just stored into _owner, it's likely that the $line
3644 // remains in M-state for the lock:orl.
3645 //
3646 // We currently use (3), although it's likely that switching to (2)
3647 // is correct for the future.
3649 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3650 if (os::is_MP()) {
3651 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3652 masm.emit_raw (0x0F) ; // MFENCE ...
3653 masm.emit_raw (0xAE) ;
3654 masm.emit_raw (0xF0) ;
3655 } else {
3656 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
3657 }
3658 }
3659 // Ratify _succ remains non-null
3660 masm.cmpl (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3661 masm.jccb (Assembler::notZero, LSuccess) ;
3663 masm.xorl (boxReg, boxReg) ; // box is really EAX
3664 if (os::is_MP()) { masm.lock(); }
3665 masm.cmpxchg(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3666 masm.jccb (Assembler::notEqual, LSuccess) ;
3667 // Since we're low on registers we installed rsp as a placeholding in _owner.
3668 // Now install Self over rsp. This is safe as we're transitioning from
3669 // non-null to non=null
3670 masm.get_thread (boxReg) ;
3671 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3672 // Intentional fall-through into LGoSlowPath ...
3674 masm.bind (LGoSlowPath) ;
3675 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3676 masm.jmpb (DONE_LABEL) ;
3678 masm.bind (LSuccess) ;
3679 masm.xorl (boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3680 masm.jmpb (DONE_LABEL) ;
3681 }
3683 masm.bind (Stacked) ;
3684 // It's not inflated and it's not recursively stack-locked and it's not biased.
3685 // It must be stack-locked.
3686 // Try to reset the header to displaced header.
3687 // The "box" value on the stack is stable, so we can reload
3688 // and be assured we observe the same value as above.
3689 masm.movl (tmpReg, Address(boxReg, 0)) ;
3690 if (os::is_MP()) { masm.lock(); }
3691 masm.cmpxchg(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3692 // Intention fall-thru into DONE_LABEL
3695 // DONE_LABEL is a hot target - we'd really like to place it at the
3696 // start of cache line by padding with NOPs.
3697 // See the AMD and Intel software optimization manuals for the
3698 // most efficient "long" NOP encodings.
3699 // Unfortunately none of our alignment mechanisms suffice.
3700 if ((EmitSync & 65536) == 0) {
3701 masm.bind (CheckSucc) ;
3702 }
3703 masm.bind(DONE_LABEL);
3705 // Avoid branch to branch on AMD processors
3706 if (EmitSync & 32768) { masm.nop() ; }
3707 }
3708 %}
3710 enc_class enc_String_Compare() %{
3711 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3712 POP_LABEL, DONE_LABEL, CONT_LABEL,
3713 WHILE_HEAD_LABEL;
3714 MacroAssembler masm(&cbuf);
3716 // Get the first character position in both strings
3717 // [8] char array, [12] offset, [16] count
3718 int value_offset = java_lang_String::value_offset_in_bytes();
3719 int offset_offset = java_lang_String::offset_offset_in_bytes();
3720 int count_offset = java_lang_String::count_offset_in_bytes();
3721 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3723 masm.movl(rax, Address(rsi, value_offset));
3724 masm.movl(rcx, Address(rsi, offset_offset));
3725 masm.leal(rax, Address(rax, rcx, Address::times_2, base_offset));
3726 masm.movl(rbx, Address(rdi, value_offset));
3727 masm.movl(rcx, Address(rdi, offset_offset));
3728 masm.leal(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3730 // Compute the minimum of the string lengths(rsi) and the
3731 // difference of the string lengths (stack)
3734 if (VM_Version::supports_cmov()) {
3735 masm.movl(rdi, Address(rdi, count_offset));
3736 masm.movl(rsi, Address(rsi, count_offset));
3737 masm.movl(rcx, rdi);
3738 masm.subl(rdi, rsi);
3739 masm.pushl(rdi);
3740 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3741 } else {
3742 masm.movl(rdi, Address(rdi, count_offset));
3743 masm.movl(rcx, Address(rsi, count_offset));
3744 masm.movl(rsi, rdi);
3745 masm.subl(rdi, rcx);
3746 masm.pushl(rdi);
3747 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL);
3748 masm.movl(rsi, rcx);
3749 // rsi holds min, rcx is unused
3750 }
3752 // Is the minimum length zero?
3753 masm.bind(ECX_GOOD_LABEL);
3754 masm.testl(rsi, rsi);
3755 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3757 // Load first characters
3758 masm.load_unsigned_word(rcx, Address(rbx, 0));
3759 masm.load_unsigned_word(rdi, Address(rax, 0));
3761 // Compare first characters
3762 masm.subl(rcx, rdi);
3763 masm.jcc(Assembler::notZero, POP_LABEL);
3764 masm.decrement(rsi);
3765 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3767 {
3768 // Check after comparing first character to see if strings are equivalent
3769 Label LSkip2;
3770 // Check if the strings start at same location
3771 masm.cmpl(rbx,rax);
3772 masm.jcc(Assembler::notEqual, LSkip2);
3774 // Check if the length difference is zero (from stack)
3775 masm.cmpl(Address(rsp, 0), 0x0);
3776 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3778 // Strings might not be equivalent
3779 masm.bind(LSkip2);
3780 }
3782 // Shift rax, and rbx, to the end of the arrays, negate min
3783 masm.leal(rax, Address(rax, rsi, Address::times_2, 2));
3784 masm.leal(rbx, Address(rbx, rsi, Address::times_2, 2));
3785 masm.negl(rsi);
3787 // Compare the rest of the characters
3788 masm.bind(WHILE_HEAD_LABEL);
3789 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
3790 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
3791 masm.subl(rcx, rdi);
3792 masm.jcc(Assembler::notZero, POP_LABEL);
3793 masm.increment(rsi);
3794 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3796 // Strings are equal up to min length. Return the length difference.
3797 masm.bind(LENGTH_DIFF_LABEL);
3798 masm.popl(rcx);
3799 masm.jmp(DONE_LABEL);
3801 // Discard the stored length difference
3802 masm.bind(POP_LABEL);
3803 masm.addl(rsp, 4);
3805 // That's it
3806 masm.bind(DONE_LABEL);
3807 %}
3809 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result) %{
3810 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
3811 MacroAssembler masm(&cbuf);
3813 Register ary1Reg = as_Register($ary1$$reg);
3814 Register ary2Reg = as_Register($ary2$$reg);
3815 Register tmp1Reg = as_Register($tmp1$$reg);
3816 Register tmp2Reg = as_Register($tmp2$$reg);
3817 Register resultReg = as_Register($result$$reg);
3819 int length_offset = arrayOopDesc::length_offset_in_bytes();
3820 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3822 // Check the input args
3823 masm.cmpl(ary1Reg, ary2Reg);
3824 masm.jcc(Assembler::equal, TRUE_LABEL);
3825 masm.testl(ary1Reg, ary1Reg);
3826 masm.jcc(Assembler::zero, FALSE_LABEL);
3827 masm.testl(ary2Reg, ary2Reg);
3828 masm.jcc(Assembler::zero, FALSE_LABEL);
3830 // Check the lengths
3831 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
3832 masm.movl(resultReg, Address(ary2Reg, length_offset));
3833 masm.cmpl(tmp2Reg, resultReg);
3834 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3835 masm.testl(resultReg, resultReg);
3836 masm.jcc(Assembler::zero, TRUE_LABEL);
3838 // Get the number of 4 byte vectors to compare
3839 masm.shrl(resultReg, 1);
3841 // Check for odd-length arrays
3842 masm.andl(tmp2Reg, 1);
3843 masm.testl(tmp2Reg, tmp2Reg);
3844 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR);
3846 // Compare 2-byte "tail" at end of arrays
3847 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3848 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3849 masm.cmpl(tmp1Reg, tmp2Reg);
3850 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3851 masm.testl(resultReg, resultReg);
3852 masm.jcc(Assembler::zero, TRUE_LABEL);
3854 // Setup compare loop
3855 masm.bind(COMPARE_LOOP_HDR);
3856 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
3857 masm.leal(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3858 masm.leal(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3859 masm.negl(resultReg);
3861 // 4-byte-wide compare loop
3862 masm.bind(COMPARE_LOOP);
3863 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
3864 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
3865 masm.cmpl(ary1Reg, ary2Reg);
3866 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3867 masm.increment(resultReg);
3868 masm.jcc(Assembler::notZero, COMPARE_LOOP);
3870 masm.bind(TRUE_LABEL);
3871 masm.movl(resultReg, 1); // return true
3872 masm.jmp(DONE_LABEL);
3874 masm.bind(FALSE_LABEL);
3875 masm.xorl(resultReg, resultReg); // return false
3877 // That's it
3878 masm.bind(DONE_LABEL);
3879 %}
3881 enc_class enc_pop_rdx() %{
3882 emit_opcode(cbuf,0x5A);
3883 %}
3885 enc_class enc_rethrow() %{
3886 cbuf.set_inst_mark();
3887 emit_opcode(cbuf, 0xE9); // jmp entry
3888 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3889 runtime_call_Relocation::spec(), RELOC_IMM32 );
3890 %}
3893 // Convert a double to an int. Java semantics require we do complex
3894 // manglelations in the corner cases. So we set the rounding mode to
3895 // 'zero', store the darned double down as an int, and reset the
3896 // rounding mode to 'nearest'. The hardware throws an exception which
3897 // patches up the correct value directly to the stack.
3898 enc_class D2I_encoding( regD src ) %{
3899 // Flip to round-to-zero mode. We attempted to allow invalid-op
3900 // exceptions here, so that a NAN or other corner-case value will
3901 // thrown an exception (but normal values get converted at full speed).
3902 // However, I2C adapters and other float-stack manglers leave pending
3903 // invalid-op exceptions hanging. We would have to clear them before
3904 // enabling them and that is more expensive than just testing for the
3905 // invalid value Intel stores down in the corner cases.
3906 emit_opcode(cbuf,0xD9); // FLDCW trunc
3907 emit_opcode(cbuf,0x2D);
3908 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3909 // Allocate a word
3910 emit_opcode(cbuf,0x83); // SUB ESP,4
3911 emit_opcode(cbuf,0xEC);
3912 emit_d8(cbuf,0x04);
3913 // Encoding assumes a double has been pushed into FPR0.
3914 // Store down the double as an int, popping the FPU stack
3915 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3916 emit_opcode(cbuf,0x1C);
3917 emit_d8(cbuf,0x24);
3918 // Restore the rounding mode; mask the exception
3919 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3920 emit_opcode(cbuf,0x2D);
3921 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3922 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3923 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3925 // Load the converted int; adjust CPU stack
3926 emit_opcode(cbuf,0x58); // POP EAX
3927 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3928 emit_d32 (cbuf,0x80000000); // 0x80000000
3929 emit_opcode(cbuf,0x75); // JNE around_slow_call
3930 emit_d8 (cbuf,0x07); // Size of slow_call
3931 // Push src onto stack slow-path
3932 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3933 emit_d8 (cbuf,0xC0-1+$src$$reg );
3934 // CALL directly to the runtime
3935 cbuf.set_inst_mark();
3936 emit_opcode(cbuf,0xE8); // Call into runtime
3937 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3938 // Carry on here...
3939 %}
3941 enc_class D2L_encoding( regD src ) %{
3942 emit_opcode(cbuf,0xD9); // FLDCW trunc
3943 emit_opcode(cbuf,0x2D);
3944 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3945 // Allocate a word
3946 emit_opcode(cbuf,0x83); // SUB ESP,8
3947 emit_opcode(cbuf,0xEC);
3948 emit_d8(cbuf,0x08);
3949 // Encoding assumes a double has been pushed into FPR0.
3950 // Store down the double as a long, popping the FPU stack
3951 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3952 emit_opcode(cbuf,0x3C);
3953 emit_d8(cbuf,0x24);
3954 // Restore the rounding mode; mask the exception
3955 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3956 emit_opcode(cbuf,0x2D);
3957 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3958 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3959 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3961 // Load the converted int; adjust CPU stack
3962 emit_opcode(cbuf,0x58); // POP EAX
3963 emit_opcode(cbuf,0x5A); // POP EDX
3964 emit_opcode(cbuf,0x81); // CMP EDX,imm
3965 emit_d8 (cbuf,0xFA); // rdx
3966 emit_d32 (cbuf,0x80000000); // 0x80000000
3967 emit_opcode(cbuf,0x75); // JNE around_slow_call
3968 emit_d8 (cbuf,0x07+4); // Size of slow_call
3969 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3970 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3971 emit_opcode(cbuf,0x75); // JNE around_slow_call
3972 emit_d8 (cbuf,0x07); // Size of slow_call
3973 // Push src onto stack slow-path
3974 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3975 emit_d8 (cbuf,0xC0-1+$src$$reg );
3976 // CALL directly to the runtime
3977 cbuf.set_inst_mark();
3978 emit_opcode(cbuf,0xE8); // Call into runtime
3979 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3980 // Carry on here...
3981 %}
3983 enc_class X2L_encoding( regX src ) %{
3984 // Allocate a word
3985 emit_opcode(cbuf,0x83); // SUB ESP,8
3986 emit_opcode(cbuf,0xEC);
3987 emit_d8(cbuf,0x08);
3989 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3990 emit_opcode (cbuf, 0x0F );
3991 emit_opcode (cbuf, 0x11 );
3992 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3994 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3995 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3997 emit_opcode(cbuf,0xD9); // FLDCW trunc
3998 emit_opcode(cbuf,0x2D);
3999 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4001 // Encoding assumes a double has been pushed into FPR0.
4002 // Store down the double as a long, popping the FPU stack
4003 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4004 emit_opcode(cbuf,0x3C);
4005 emit_d8(cbuf,0x24);
4007 // Restore the rounding mode; mask the exception
4008 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4009 emit_opcode(cbuf,0x2D);
4010 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4011 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4012 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4014 // Load the converted int; adjust CPU stack
4015 emit_opcode(cbuf,0x58); // POP EAX
4017 emit_opcode(cbuf,0x5A); // POP EDX
4019 emit_opcode(cbuf,0x81); // CMP EDX,imm
4020 emit_d8 (cbuf,0xFA); // rdx
4021 emit_d32 (cbuf,0x80000000);// 0x80000000
4023 emit_opcode(cbuf,0x75); // JNE around_slow_call
4024 emit_d8 (cbuf,0x13+4); // Size of slow_call
4026 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4027 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4029 emit_opcode(cbuf,0x75); // JNE around_slow_call
4030 emit_d8 (cbuf,0x13); // Size of slow_call
4032 // Allocate a word
4033 emit_opcode(cbuf,0x83); // SUB ESP,4
4034 emit_opcode(cbuf,0xEC);
4035 emit_d8(cbuf,0x04);
4037 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4038 emit_opcode (cbuf, 0x0F );
4039 emit_opcode (cbuf, 0x11 );
4040 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4042 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4043 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4045 emit_opcode(cbuf,0x83); // ADD ESP,4
4046 emit_opcode(cbuf,0xC4);
4047 emit_d8(cbuf,0x04);
4049 // CALL directly to the runtime
4050 cbuf.set_inst_mark();
4051 emit_opcode(cbuf,0xE8); // Call into runtime
4052 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4053 // Carry on here...
4054 %}
4056 enc_class XD2L_encoding( regXD src ) %{
4057 // Allocate a word
4058 emit_opcode(cbuf,0x83); // SUB ESP,8
4059 emit_opcode(cbuf,0xEC);
4060 emit_d8(cbuf,0x08);
4062 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4063 emit_opcode (cbuf, 0x0F );
4064 emit_opcode (cbuf, 0x11 );
4065 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4067 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4068 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4070 emit_opcode(cbuf,0xD9); // FLDCW trunc
4071 emit_opcode(cbuf,0x2D);
4072 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4074 // Encoding assumes a double has been pushed into FPR0.
4075 // Store down the double as a long, popping the FPU stack
4076 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4077 emit_opcode(cbuf,0x3C);
4078 emit_d8(cbuf,0x24);
4080 // Restore the rounding mode; mask the exception
4081 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4082 emit_opcode(cbuf,0x2D);
4083 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4084 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4085 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4087 // Load the converted int; adjust CPU stack
4088 emit_opcode(cbuf,0x58); // POP EAX
4090 emit_opcode(cbuf,0x5A); // POP EDX
4092 emit_opcode(cbuf,0x81); // CMP EDX,imm
4093 emit_d8 (cbuf,0xFA); // rdx
4094 emit_d32 (cbuf,0x80000000); // 0x80000000
4096 emit_opcode(cbuf,0x75); // JNE around_slow_call
4097 emit_d8 (cbuf,0x13+4); // Size of slow_call
4099 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4100 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4102 emit_opcode(cbuf,0x75); // JNE around_slow_call
4103 emit_d8 (cbuf,0x13); // Size of slow_call
4105 // Push src onto stack slow-path
4106 // Allocate a word
4107 emit_opcode(cbuf,0x83); // SUB ESP,8
4108 emit_opcode(cbuf,0xEC);
4109 emit_d8(cbuf,0x08);
4111 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4112 emit_opcode (cbuf, 0x0F );
4113 emit_opcode (cbuf, 0x11 );
4114 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4116 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4117 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4119 emit_opcode(cbuf,0x83); // ADD ESP,8
4120 emit_opcode(cbuf,0xC4);
4121 emit_d8(cbuf,0x08);
4123 // CALL directly to the runtime
4124 cbuf.set_inst_mark();
4125 emit_opcode(cbuf,0xE8); // Call into runtime
4126 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4127 // Carry on here...
4128 %}
4130 enc_class D2X_encoding( regX dst, regD src ) %{
4131 // Allocate a word
4132 emit_opcode(cbuf,0x83); // SUB ESP,4
4133 emit_opcode(cbuf,0xEC);
4134 emit_d8(cbuf,0x04);
4135 int pop = 0x02;
4136 if ($src$$reg != FPR1L_enc) {
4137 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4138 emit_d8( cbuf, 0xC0-1+$src$$reg );
4139 pop = 0x03;
4140 }
4141 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4143 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4144 emit_opcode (cbuf, 0x0F );
4145 emit_opcode (cbuf, 0x10 );
4146 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4148 emit_opcode(cbuf,0x83); // ADD ESP,4
4149 emit_opcode(cbuf,0xC4);
4150 emit_d8(cbuf,0x04);
4151 // Carry on here...
4152 %}
4154 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4155 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4157 // Compare the result to see if we need to go to the slow path
4158 emit_opcode(cbuf,0x81); // CMP dst,imm
4159 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4160 emit_d32 (cbuf,0x80000000); // 0x80000000
4162 emit_opcode(cbuf,0x75); // JNE around_slow_call
4163 emit_d8 (cbuf,0x13); // Size of slow_call
4164 // Store xmm to a temp memory
4165 // location and push it onto stack.
4167 emit_opcode(cbuf,0x83); // SUB ESP,4
4168 emit_opcode(cbuf,0xEC);
4169 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4171 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4172 emit_opcode (cbuf, 0x0F );
4173 emit_opcode (cbuf, 0x11 );
4174 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4176 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4177 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4179 emit_opcode(cbuf,0x83); // ADD ESP,4
4180 emit_opcode(cbuf,0xC4);
4181 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4183 // CALL directly to the runtime
4184 cbuf.set_inst_mark();
4185 emit_opcode(cbuf,0xE8); // Call into runtime
4186 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4188 // Carry on here...
4189 %}
4191 enc_class X2D_encoding( regD dst, regX src ) %{
4192 // Allocate a word
4193 emit_opcode(cbuf,0x83); // SUB ESP,4
4194 emit_opcode(cbuf,0xEC);
4195 emit_d8(cbuf,0x04);
4197 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4198 emit_opcode (cbuf, 0x0F );
4199 emit_opcode (cbuf, 0x11 );
4200 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4202 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4203 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4205 emit_opcode(cbuf,0x83); // ADD ESP,4
4206 emit_opcode(cbuf,0xC4);
4207 emit_d8(cbuf,0x04);
4209 // Carry on here...
4210 %}
4212 enc_class AbsXF_encoding(regX dst) %{
4213 address signmask_address=(address)float_signmask_pool;
4214 // andpd:\tANDPS $dst,[signconst]
4215 emit_opcode(cbuf, 0x0F);
4216 emit_opcode(cbuf, 0x54);
4217 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4218 emit_d32(cbuf, (int)signmask_address);
4219 %}
4221 enc_class AbsXD_encoding(regXD dst) %{
4222 address signmask_address=(address)double_signmask_pool;
4223 // andpd:\tANDPD $dst,[signconst]
4224 emit_opcode(cbuf, 0x66);
4225 emit_opcode(cbuf, 0x0F);
4226 emit_opcode(cbuf, 0x54);
4227 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4228 emit_d32(cbuf, (int)signmask_address);
4229 %}
4231 enc_class NegXF_encoding(regX dst) %{
4232 address signmask_address=(address)float_signflip_pool;
4233 // andpd:\tXORPS $dst,[signconst]
4234 emit_opcode(cbuf, 0x0F);
4235 emit_opcode(cbuf, 0x57);
4236 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4237 emit_d32(cbuf, (int)signmask_address);
4238 %}
4240 enc_class NegXD_encoding(regXD dst) %{
4241 address signmask_address=(address)double_signflip_pool;
4242 // andpd:\tXORPD $dst,[signconst]
4243 emit_opcode(cbuf, 0x66);
4244 emit_opcode(cbuf, 0x0F);
4245 emit_opcode(cbuf, 0x57);
4246 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4247 emit_d32(cbuf, (int)signmask_address);
4248 %}
4250 enc_class FMul_ST_reg( eRegF src1 ) %{
4251 // Operand was loaded from memory into fp ST (stack top)
4252 // FMUL ST,$src /* D8 C8+i */
4253 emit_opcode(cbuf, 0xD8);
4254 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4255 %}
4257 enc_class FAdd_ST_reg( eRegF src2 ) %{
4258 // FADDP ST,src2 /* D8 C0+i */
4259 emit_opcode(cbuf, 0xD8);
4260 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4261 //could use FADDP src2,fpST /* DE C0+i */
4262 %}
4264 enc_class FAddP_reg_ST( eRegF src2 ) %{
4265 // FADDP src2,ST /* DE C0+i */
4266 emit_opcode(cbuf, 0xDE);
4267 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4268 %}
4270 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4271 // Operand has been loaded into fp ST (stack top)
4272 // FSUB ST,$src1
4273 emit_opcode(cbuf, 0xD8);
4274 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4276 // FDIV
4277 emit_opcode(cbuf, 0xD8);
4278 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4279 %}
4281 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4282 // Operand was loaded from memory into fp ST (stack top)
4283 // FADD ST,$src /* D8 C0+i */
4284 emit_opcode(cbuf, 0xD8);
4285 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4287 // FMUL ST,src2 /* D8 C*+i */
4288 emit_opcode(cbuf, 0xD8);
4289 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4290 %}
4293 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4294 // Operand was loaded from memory into fp ST (stack top)
4295 // FADD ST,$src /* D8 C0+i */
4296 emit_opcode(cbuf, 0xD8);
4297 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4299 // FMULP src2,ST /* DE C8+i */
4300 emit_opcode(cbuf, 0xDE);
4301 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4302 %}
4304 enc_class enc_membar_acquire %{
4305 // Doug Lea believes this is not needed with current Sparcs and TSO.
4306 // MacroAssembler masm(&cbuf);
4307 // masm.membar();
4308 %}
4310 enc_class enc_membar_release %{
4311 // Doug Lea believes this is not needed with current Sparcs and TSO.
4312 // MacroAssembler masm(&cbuf);
4313 // masm.membar();
4314 %}
4316 enc_class enc_membar_volatile %{
4317 MacroAssembler masm(&cbuf);
4318 masm.membar();
4319 %}
4321 // Atomically load the volatile long
4322 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4323 emit_opcode(cbuf,0xDF);
4324 int rm_byte_opcode = 0x05;
4325 int base = $mem$$base;
4326 int index = $mem$$index;
4327 int scale = $mem$$scale;
4328 int displace = $mem$$disp;
4329 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4330 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4331 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4332 %}
4334 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4335 { // Atomic long load
4336 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4337 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4338 emit_opcode(cbuf,0x0F);
4339 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4340 int base = $mem$$base;
4341 int index = $mem$$index;
4342 int scale = $mem$$scale;
4343 int displace = $mem$$disp;
4344 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4345 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4346 }
4347 { // MOVSD $dst,$tmp ! atomic long store
4348 emit_opcode(cbuf,0xF2);
4349 emit_opcode(cbuf,0x0F);
4350 emit_opcode(cbuf,0x11);
4351 int base = $dst$$base;
4352 int index = $dst$$index;
4353 int scale = $dst$$scale;
4354 int displace = $dst$$disp;
4355 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4356 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4357 }
4358 %}
4360 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4361 { // Atomic long load
4362 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4363 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4364 emit_opcode(cbuf,0x0F);
4365 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4366 int base = $mem$$base;
4367 int index = $mem$$index;
4368 int scale = $mem$$scale;
4369 int displace = $mem$$disp;
4370 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4371 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4372 }
4373 { // MOVD $dst.lo,$tmp
4374 emit_opcode(cbuf,0x66);
4375 emit_opcode(cbuf,0x0F);
4376 emit_opcode(cbuf,0x7E);
4377 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4378 }
4379 { // PSRLQ $tmp,32
4380 emit_opcode(cbuf,0x66);
4381 emit_opcode(cbuf,0x0F);
4382 emit_opcode(cbuf,0x73);
4383 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4384 emit_d8(cbuf, 0x20);
4385 }
4386 { // MOVD $dst.hi,$tmp
4387 emit_opcode(cbuf,0x66);
4388 emit_opcode(cbuf,0x0F);
4389 emit_opcode(cbuf,0x7E);
4390 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4391 }
4392 %}
4394 // Volatile Store Long. Must be atomic, so move it into
4395 // the FP TOS and then do a 64-bit FIST. Has to probe the
4396 // target address before the store (for null-ptr checks)
4397 // so the memory operand is used twice in the encoding.
4398 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4399 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4400 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4401 emit_opcode(cbuf,0xDF);
4402 int rm_byte_opcode = 0x07;
4403 int base = $mem$$base;
4404 int index = $mem$$index;
4405 int scale = $mem$$scale;
4406 int displace = $mem$$disp;
4407 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4408 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4409 %}
4411 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4412 { // Atomic long load
4413 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4414 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4415 emit_opcode(cbuf,0x0F);
4416 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4417 int base = $src$$base;
4418 int index = $src$$index;
4419 int scale = $src$$scale;
4420 int displace = $src$$disp;
4421 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4422 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4423 }
4424 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4425 { // MOVSD $mem,$tmp ! atomic long store
4426 emit_opcode(cbuf,0xF2);
4427 emit_opcode(cbuf,0x0F);
4428 emit_opcode(cbuf,0x11);
4429 int base = $mem$$base;
4430 int index = $mem$$index;
4431 int scale = $mem$$scale;
4432 int displace = $mem$$disp;
4433 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4434 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4435 }
4436 %}
4438 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4439 { // MOVD $tmp,$src.lo
4440 emit_opcode(cbuf,0x66);
4441 emit_opcode(cbuf,0x0F);
4442 emit_opcode(cbuf,0x6E);
4443 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4444 }
4445 { // MOVD $tmp2,$src.hi
4446 emit_opcode(cbuf,0x66);
4447 emit_opcode(cbuf,0x0F);
4448 emit_opcode(cbuf,0x6E);
4449 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4450 }
4451 { // PUNPCKLDQ $tmp,$tmp2
4452 emit_opcode(cbuf,0x66);
4453 emit_opcode(cbuf,0x0F);
4454 emit_opcode(cbuf,0x62);
4455 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4456 }
4457 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4458 { // MOVSD $mem,$tmp ! atomic long store
4459 emit_opcode(cbuf,0xF2);
4460 emit_opcode(cbuf,0x0F);
4461 emit_opcode(cbuf,0x11);
4462 int base = $mem$$base;
4463 int index = $mem$$index;
4464 int scale = $mem$$scale;
4465 int displace = $mem$$disp;
4466 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4467 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4468 }
4469 %}
4471 // Safepoint Poll. This polls the safepoint page, and causes an
4472 // exception if it is not readable. Unfortunately, it kills the condition code
4473 // in the process
4474 // We current use TESTL [spp],EDI
4475 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4477 enc_class Safepoint_Poll() %{
4478 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4479 emit_opcode(cbuf,0x85);
4480 emit_rm (cbuf, 0x0, 0x7, 0x5);
4481 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4482 %}
4483 %}
4486 //----------FRAME--------------------------------------------------------------
4487 // Definition of frame structure and management information.
4488 //
4489 // S T A C K L A Y O U T Allocators stack-slot number
4490 // | (to get allocators register number
4491 // G Owned by | | v add OptoReg::stack0())
4492 // r CALLER | |
4493 // o | +--------+ pad to even-align allocators stack-slot
4494 // w V | pad0 | numbers; owned by CALLER
4495 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4496 // h ^ | in | 5
4497 // | | args | 4 Holes in incoming args owned by SELF
4498 // | | | | 3
4499 // | | +--------+
4500 // V | | old out| Empty on Intel, window on Sparc
4501 // | old |preserve| Must be even aligned.
4502 // | SP-+--------+----> Matcher::_old_SP, even aligned
4503 // | | in | 3 area for Intel ret address
4504 // Owned by |preserve| Empty on Sparc.
4505 // SELF +--------+
4506 // | | pad2 | 2 pad to align old SP
4507 // | +--------+ 1
4508 // | | locks | 0
4509 // | +--------+----> OptoReg::stack0(), even aligned
4510 // | | pad1 | 11 pad to align new SP
4511 // | +--------+
4512 // | | | 10
4513 // | | spills | 9 spills
4514 // V | | 8 (pad0 slot for callee)
4515 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4516 // ^ | out | 7
4517 // | | args | 6 Holes in outgoing args owned by CALLEE
4518 // Owned by +--------+
4519 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4520 // | new |preserve| Must be even-aligned.
4521 // | SP-+--------+----> Matcher::_new_SP, even aligned
4522 // | | |
4523 //
4524 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4525 // known from SELF's arguments and the Java calling convention.
4526 // Region 6-7 is determined per call site.
4527 // Note 2: If the calling convention leaves holes in the incoming argument
4528 // area, those holes are owned by SELF. Holes in the outgoing area
4529 // are owned by the CALLEE. Holes should not be nessecary in the
4530 // incoming area, as the Java calling convention is completely under
4531 // the control of the AD file. Doubles can be sorted and packed to
4532 // avoid holes. Holes in the outgoing arguments may be nessecary for
4533 // varargs C calling conventions.
4534 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4535 // even aligned with pad0 as needed.
4536 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4537 // region 6-11 is even aligned; it may be padded out more so that
4538 // the region from SP to FP meets the minimum stack alignment.
4540 frame %{
4541 // What direction does stack grow in (assumed to be same for C & Java)
4542 stack_direction(TOWARDS_LOW);
4544 // These three registers define part of the calling convention
4545 // between compiled code and the interpreter.
4546 inline_cache_reg(EAX); // Inline Cache Register
4547 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4549 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4550 cisc_spilling_operand_name(indOffset32);
4552 // Number of stack slots consumed by locking an object
4553 sync_stack_slots(1);
4555 // Compiled code's Frame Pointer
4556 frame_pointer(ESP);
4557 // Interpreter stores its frame pointer in a register which is
4558 // stored to the stack by I2CAdaptors.
4559 // I2CAdaptors convert from interpreted java to compiled java.
4560 interpreter_frame_pointer(EBP);
4562 // Stack alignment requirement
4563 // Alignment size in bytes (128-bit -> 16 bytes)
4564 stack_alignment(StackAlignmentInBytes);
4566 // Number of stack slots between incoming argument block and the start of
4567 // a new frame. The PROLOG must add this many slots to the stack. The
4568 // EPILOG must remove this many slots. Intel needs one slot for
4569 // return address and one for rbp, (must save rbp)
4570 in_preserve_stack_slots(2+VerifyStackAtCalls);
4572 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4573 // for calls to C. Supports the var-args backing area for register parms.
4574 varargs_C_out_slots_killed(0);
4576 // The after-PROLOG location of the return address. Location of
4577 // return address specifies a type (REG or STACK) and a number
4578 // representing the register number (i.e. - use a register name) or
4579 // stack slot.
4580 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4581 // Otherwise, it is above the locks and verification slot and alignment word
4582 return_addr(STACK - 1 +
4583 round_to(1+VerifyStackAtCalls+
4584 Compile::current()->fixed_slots(),
4585 (StackAlignmentInBytes/wordSize)));
4587 // Body of function which returns an integer array locating
4588 // arguments either in registers or in stack slots. Passed an array
4589 // of ideal registers called "sig" and a "length" count. Stack-slot
4590 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4591 // arguments for a CALLEE. Incoming stack arguments are
4592 // automatically biased by the preserve_stack_slots field above.
4593 calling_convention %{
4594 // No difference between ingoing/outgoing just pass false
4595 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4596 %}
4599 // Body of function which returns an integer array locating
4600 // arguments either in registers or in stack slots. Passed an array
4601 // of ideal registers called "sig" and a "length" count. Stack-slot
4602 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4603 // arguments for a CALLEE. Incoming stack arguments are
4604 // automatically biased by the preserve_stack_slots field above.
4605 c_calling_convention %{
4606 // This is obviously always outgoing
4607 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4608 %}
4610 // Location of C & interpreter return values
4611 c_return_value %{
4612 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4613 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4614 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4616 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4617 // that C functions return float and double results in XMM0.
4618 if( ideal_reg == Op_RegD && UseSSE>=2 )
4619 return OptoRegPair(XMM0b_num,XMM0a_num);
4620 if( ideal_reg == Op_RegF && UseSSE>=2 )
4621 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4623 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4624 %}
4626 // Location of return values
4627 return_value %{
4628 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4629 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4630 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4631 if( ideal_reg == Op_RegD && UseSSE>=2 )
4632 return OptoRegPair(XMM0b_num,XMM0a_num);
4633 if( ideal_reg == Op_RegF && UseSSE>=1 )
4634 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4635 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4636 %}
4638 %}
4640 //----------ATTRIBUTES---------------------------------------------------------
4641 //----------Operand Attributes-------------------------------------------------
4642 op_attrib op_cost(0); // Required cost attribute
4644 //----------Instruction Attributes---------------------------------------------
4645 ins_attrib ins_cost(100); // Required cost attribute
4646 ins_attrib ins_size(8); // Required size attribute (in bits)
4647 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4648 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4649 // non-matching short branch variant of some
4650 // long branch?
4651 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4652 // specifies the alignment that some part of the instruction (not
4653 // necessarily the start) requires. If > 1, a compute_padding()
4654 // function must be provided for the instruction
4656 //----------OPERANDS-----------------------------------------------------------
4657 // Operand definitions must precede instruction definitions for correct parsing
4658 // in the ADLC because operands constitute user defined types which are used in
4659 // instruction definitions.
4661 //----------Simple Operands----------------------------------------------------
4662 // Immediate Operands
4663 // Integer Immediate
4664 operand immI() %{
4665 match(ConI);
4667 op_cost(10);
4668 format %{ %}
4669 interface(CONST_INTER);
4670 %}
4672 // Constant for test vs zero
4673 operand immI0() %{
4674 predicate(n->get_int() == 0);
4675 match(ConI);
4677 op_cost(0);
4678 format %{ %}
4679 interface(CONST_INTER);
4680 %}
4682 // Constant for increment
4683 operand immI1() %{
4684 predicate(n->get_int() == 1);
4685 match(ConI);
4687 op_cost(0);
4688 format %{ %}
4689 interface(CONST_INTER);
4690 %}
4692 // Constant for decrement
4693 operand immI_M1() %{
4694 predicate(n->get_int() == -1);
4695 match(ConI);
4697 op_cost(0);
4698 format %{ %}
4699 interface(CONST_INTER);
4700 %}
4702 // Valid scale values for addressing modes
4703 operand immI2() %{
4704 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4705 match(ConI);
4707 format %{ %}
4708 interface(CONST_INTER);
4709 %}
4711 operand immI8() %{
4712 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4713 match(ConI);
4715 op_cost(5);
4716 format %{ %}
4717 interface(CONST_INTER);
4718 %}
4720 operand immI16() %{
4721 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4722 match(ConI);
4724 op_cost(10);
4725 format %{ %}
4726 interface(CONST_INTER);
4727 %}
4729 // Constant for long shifts
4730 operand immI_32() %{
4731 predicate( n->get_int() == 32 );
4732 match(ConI);
4734 op_cost(0);
4735 format %{ %}
4736 interface(CONST_INTER);
4737 %}
4739 operand immI_1_31() %{
4740 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4741 match(ConI);
4743 op_cost(0);
4744 format %{ %}
4745 interface(CONST_INTER);
4746 %}
4748 operand immI_32_63() %{
4749 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4750 match(ConI);
4751 op_cost(0);
4753 format %{ %}
4754 interface(CONST_INTER);
4755 %}
4757 // Pointer Immediate
4758 operand immP() %{
4759 match(ConP);
4761 op_cost(10);
4762 format %{ %}
4763 interface(CONST_INTER);
4764 %}
4766 // NULL Pointer Immediate
4767 operand immP0() %{
4768 predicate( n->get_ptr() == 0 );
4769 match(ConP);
4770 op_cost(0);
4772 format %{ %}
4773 interface(CONST_INTER);
4774 %}
4776 // Long Immediate
4777 operand immL() %{
4778 match(ConL);
4780 op_cost(20);
4781 format %{ %}
4782 interface(CONST_INTER);
4783 %}
4785 // Long Immediate zero
4786 operand immL0() %{
4787 predicate( n->get_long() == 0L );
4788 match(ConL);
4789 op_cost(0);
4791 format %{ %}
4792 interface(CONST_INTER);
4793 %}
4795 // Long immediate from 0 to 127.
4796 // Used for a shorter form of long mul by 10.
4797 operand immL_127() %{
4798 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4799 match(ConL);
4800 op_cost(0);
4802 format %{ %}
4803 interface(CONST_INTER);
4804 %}
4806 // Long Immediate: low 32-bit mask
4807 operand immL_32bits() %{
4808 predicate(n->get_long() == 0xFFFFFFFFL);
4809 match(ConL);
4810 op_cost(0);
4812 format %{ %}
4813 interface(CONST_INTER);
4814 %}
4816 // Long Immediate: low 32-bit mask
4817 operand immL32() %{
4818 predicate(n->get_long() == (int)(n->get_long()));
4819 match(ConL);
4820 op_cost(20);
4822 format %{ %}
4823 interface(CONST_INTER);
4824 %}
4826 //Double Immediate zero
4827 operand immD0() %{
4828 // Do additional (and counter-intuitive) test against NaN to work around VC++
4829 // bug that generates code such that NaNs compare equal to 0.0
4830 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4831 match(ConD);
4833 op_cost(5);
4834 format %{ %}
4835 interface(CONST_INTER);
4836 %}
4838 // Double Immediate
4839 operand immD1() %{
4840 predicate( UseSSE<=1 && n->getd() == 1.0 );
4841 match(ConD);
4843 op_cost(5);
4844 format %{ %}
4845 interface(CONST_INTER);
4846 %}
4848 // Double Immediate
4849 operand immD() %{
4850 predicate(UseSSE<=1);
4851 match(ConD);
4853 op_cost(5);
4854 format %{ %}
4855 interface(CONST_INTER);
4856 %}
4858 operand immXD() %{
4859 predicate(UseSSE>=2);
4860 match(ConD);
4862 op_cost(5);
4863 format %{ %}
4864 interface(CONST_INTER);
4865 %}
4867 // Double Immediate zero
4868 operand immXD0() %{
4869 // Do additional (and counter-intuitive) test against NaN to work around VC++
4870 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4871 // compare equal to -0.0.
4872 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4873 match(ConD);
4875 format %{ %}
4876 interface(CONST_INTER);
4877 %}
4879 // Float Immediate zero
4880 operand immF0() %{
4881 predicate( UseSSE == 0 && n->getf() == 0.0 );
4882 match(ConF);
4884 op_cost(5);
4885 format %{ %}
4886 interface(CONST_INTER);
4887 %}
4889 // Float Immediate
4890 operand immF() %{
4891 predicate( UseSSE == 0 );
4892 match(ConF);
4894 op_cost(5);
4895 format %{ %}
4896 interface(CONST_INTER);
4897 %}
4899 // Float Immediate
4900 operand immXF() %{
4901 predicate(UseSSE >= 1);
4902 match(ConF);
4904 op_cost(5);
4905 format %{ %}
4906 interface(CONST_INTER);
4907 %}
4909 // Float Immediate zero. Zero and not -0.0
4910 operand immXF0() %{
4911 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4912 match(ConF);
4914 op_cost(5);
4915 format %{ %}
4916 interface(CONST_INTER);
4917 %}
4919 // Immediates for special shifts (sign extend)
4921 // Constants for increment
4922 operand immI_16() %{
4923 predicate( n->get_int() == 16 );
4924 match(ConI);
4926 format %{ %}
4927 interface(CONST_INTER);
4928 %}
4930 operand immI_24() %{
4931 predicate( n->get_int() == 24 );
4932 match(ConI);
4934 format %{ %}
4935 interface(CONST_INTER);
4936 %}
4938 // Constant for byte-wide masking
4939 operand immI_255() %{
4940 predicate( n->get_int() == 255 );
4941 match(ConI);
4943 format %{ %}
4944 interface(CONST_INTER);
4945 %}
4947 // Register Operands
4948 // Integer Register
4949 operand eRegI() %{
4950 constraint(ALLOC_IN_RC(e_reg));
4951 match(RegI);
4952 match(xRegI);
4953 match(eAXRegI);
4954 match(eBXRegI);
4955 match(eCXRegI);
4956 match(eDXRegI);
4957 match(eDIRegI);
4958 match(eSIRegI);
4960 format %{ %}
4961 interface(REG_INTER);
4962 %}
4964 // Subset of Integer Register
4965 operand xRegI(eRegI reg) %{
4966 constraint(ALLOC_IN_RC(x_reg));
4967 match(reg);
4968 match(eAXRegI);
4969 match(eBXRegI);
4970 match(eCXRegI);
4971 match(eDXRegI);
4973 format %{ %}
4974 interface(REG_INTER);
4975 %}
4977 // Special Registers
4978 operand eAXRegI(xRegI reg) %{
4979 constraint(ALLOC_IN_RC(eax_reg));
4980 match(reg);
4981 match(eRegI);
4983 format %{ "EAX" %}
4984 interface(REG_INTER);
4985 %}
4987 // Special Registers
4988 operand eBXRegI(xRegI reg) %{
4989 constraint(ALLOC_IN_RC(ebx_reg));
4990 match(reg);
4991 match(eRegI);
4993 format %{ "EBX" %}
4994 interface(REG_INTER);
4995 %}
4997 operand eCXRegI(xRegI reg) %{
4998 constraint(ALLOC_IN_RC(ecx_reg));
4999 match(reg);
5000 match(eRegI);
5002 format %{ "ECX" %}
5003 interface(REG_INTER);
5004 %}
5006 operand eDXRegI(xRegI reg) %{
5007 constraint(ALLOC_IN_RC(edx_reg));
5008 match(reg);
5009 match(eRegI);
5011 format %{ "EDX" %}
5012 interface(REG_INTER);
5013 %}
5015 operand eDIRegI(xRegI reg) %{
5016 constraint(ALLOC_IN_RC(edi_reg));
5017 match(reg);
5018 match(eRegI);
5020 format %{ "EDI" %}
5021 interface(REG_INTER);
5022 %}
5024 operand naxRegI() %{
5025 constraint(ALLOC_IN_RC(nax_reg));
5026 match(RegI);
5027 match(eCXRegI);
5028 match(eDXRegI);
5029 match(eSIRegI);
5030 match(eDIRegI);
5032 format %{ %}
5033 interface(REG_INTER);
5034 %}
5036 operand nadxRegI() %{
5037 constraint(ALLOC_IN_RC(nadx_reg));
5038 match(RegI);
5039 match(eBXRegI);
5040 match(eCXRegI);
5041 match(eSIRegI);
5042 match(eDIRegI);
5044 format %{ %}
5045 interface(REG_INTER);
5046 %}
5048 operand ncxRegI() %{
5049 constraint(ALLOC_IN_RC(ncx_reg));
5050 match(RegI);
5051 match(eAXRegI);
5052 match(eDXRegI);
5053 match(eSIRegI);
5054 match(eDIRegI);
5056 format %{ %}
5057 interface(REG_INTER);
5058 %}
5060 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5061 // //
5062 operand eSIRegI(xRegI reg) %{
5063 constraint(ALLOC_IN_RC(esi_reg));
5064 match(reg);
5065 match(eRegI);
5067 format %{ "ESI" %}
5068 interface(REG_INTER);
5069 %}
5071 // Pointer Register
5072 operand anyRegP() %{
5073 constraint(ALLOC_IN_RC(any_reg));
5074 match(RegP);
5075 match(eAXRegP);
5076 match(eBXRegP);
5077 match(eCXRegP);
5078 match(eDIRegP);
5079 match(eRegP);
5081 format %{ %}
5082 interface(REG_INTER);
5083 %}
5085 operand eRegP() %{
5086 constraint(ALLOC_IN_RC(e_reg));
5087 match(RegP);
5088 match(eAXRegP);
5089 match(eBXRegP);
5090 match(eCXRegP);
5091 match(eDIRegP);
5093 format %{ %}
5094 interface(REG_INTER);
5095 %}
5097 // On windows95, EBP is not safe to use for implicit null tests.
5098 operand eRegP_no_EBP() %{
5099 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5100 match(RegP);
5101 match(eAXRegP);
5102 match(eBXRegP);
5103 match(eCXRegP);
5104 match(eDIRegP);
5106 op_cost(100);
5107 format %{ %}
5108 interface(REG_INTER);
5109 %}
5111 operand naxRegP() %{
5112 constraint(ALLOC_IN_RC(nax_reg));
5113 match(RegP);
5114 match(eBXRegP);
5115 match(eDXRegP);
5116 match(eCXRegP);
5117 match(eSIRegP);
5118 match(eDIRegP);
5120 format %{ %}
5121 interface(REG_INTER);
5122 %}
5124 operand nabxRegP() %{
5125 constraint(ALLOC_IN_RC(nabx_reg));
5126 match(RegP);
5127 match(eCXRegP);
5128 match(eDXRegP);
5129 match(eSIRegP);
5130 match(eDIRegP);
5132 format %{ %}
5133 interface(REG_INTER);
5134 %}
5136 operand pRegP() %{
5137 constraint(ALLOC_IN_RC(p_reg));
5138 match(RegP);
5139 match(eBXRegP);
5140 match(eDXRegP);
5141 match(eSIRegP);
5142 match(eDIRegP);
5144 format %{ %}
5145 interface(REG_INTER);
5146 %}
5148 // Special Registers
5149 // Return a pointer value
5150 operand eAXRegP(eRegP reg) %{
5151 constraint(ALLOC_IN_RC(eax_reg));
5152 match(reg);
5153 format %{ "EAX" %}
5154 interface(REG_INTER);
5155 %}
5157 // Used in AtomicAdd
5158 operand eBXRegP(eRegP reg) %{
5159 constraint(ALLOC_IN_RC(ebx_reg));
5160 match(reg);
5161 format %{ "EBX" %}
5162 interface(REG_INTER);
5163 %}
5165 // Tail-call (interprocedural jump) to interpreter
5166 operand eCXRegP(eRegP reg) %{
5167 constraint(ALLOC_IN_RC(ecx_reg));
5168 match(reg);
5169 format %{ "ECX" %}
5170 interface(REG_INTER);
5171 %}
5173 operand eSIRegP(eRegP reg) %{
5174 constraint(ALLOC_IN_RC(esi_reg));
5175 match(reg);
5176 format %{ "ESI" %}
5177 interface(REG_INTER);
5178 %}
5180 // Used in rep stosw
5181 operand eDIRegP(eRegP reg) %{
5182 constraint(ALLOC_IN_RC(edi_reg));
5183 match(reg);
5184 format %{ "EDI" %}
5185 interface(REG_INTER);
5186 %}
5188 operand eBPRegP() %{
5189 constraint(ALLOC_IN_RC(ebp_reg));
5190 match(RegP);
5191 format %{ "EBP" %}
5192 interface(REG_INTER);
5193 %}
5195 operand eRegL() %{
5196 constraint(ALLOC_IN_RC(long_reg));
5197 match(RegL);
5198 match(eADXRegL);
5200 format %{ %}
5201 interface(REG_INTER);
5202 %}
5204 operand eADXRegL( eRegL reg ) %{
5205 constraint(ALLOC_IN_RC(eadx_reg));
5206 match(reg);
5208 format %{ "EDX:EAX" %}
5209 interface(REG_INTER);
5210 %}
5212 operand eBCXRegL( eRegL reg ) %{
5213 constraint(ALLOC_IN_RC(ebcx_reg));
5214 match(reg);
5216 format %{ "EBX:ECX" %}
5217 interface(REG_INTER);
5218 %}
5220 // Special case for integer high multiply
5221 operand eADXRegL_low_only() %{
5222 constraint(ALLOC_IN_RC(eadx_reg));
5223 match(RegL);
5225 format %{ "EAX" %}
5226 interface(REG_INTER);
5227 %}
5229 // Flags register, used as output of compare instructions
5230 operand eFlagsReg() %{
5231 constraint(ALLOC_IN_RC(int_flags));
5232 match(RegFlags);
5234 format %{ "EFLAGS" %}
5235 interface(REG_INTER);
5236 %}
5238 // Flags register, used as output of FLOATING POINT compare instructions
5239 operand eFlagsRegU() %{
5240 constraint(ALLOC_IN_RC(int_flags));
5241 match(RegFlags);
5243 format %{ "EFLAGS_U" %}
5244 interface(REG_INTER);
5245 %}
5247 // Condition Code Register used by long compare
5248 operand flagsReg_long_LTGE() %{
5249 constraint(ALLOC_IN_RC(int_flags));
5250 match(RegFlags);
5251 format %{ "FLAGS_LTGE" %}
5252 interface(REG_INTER);
5253 %}
5254 operand flagsReg_long_EQNE() %{
5255 constraint(ALLOC_IN_RC(int_flags));
5256 match(RegFlags);
5257 format %{ "FLAGS_EQNE" %}
5258 interface(REG_INTER);
5259 %}
5260 operand flagsReg_long_LEGT() %{
5261 constraint(ALLOC_IN_RC(int_flags));
5262 match(RegFlags);
5263 format %{ "FLAGS_LEGT" %}
5264 interface(REG_INTER);
5265 %}
5267 // Float register operands
5268 operand regD() %{
5269 predicate( UseSSE < 2 );
5270 constraint(ALLOC_IN_RC(dbl_reg));
5271 match(RegD);
5272 match(regDPR1);
5273 match(regDPR2);
5274 format %{ %}
5275 interface(REG_INTER);
5276 %}
5278 operand regDPR1(regD reg) %{
5279 predicate( UseSSE < 2 );
5280 constraint(ALLOC_IN_RC(dbl_reg0));
5281 match(reg);
5282 format %{ "FPR1" %}
5283 interface(REG_INTER);
5284 %}
5286 operand regDPR2(regD reg) %{
5287 predicate( UseSSE < 2 );
5288 constraint(ALLOC_IN_RC(dbl_reg1));
5289 match(reg);
5290 format %{ "FPR2" %}
5291 interface(REG_INTER);
5292 %}
5294 operand regnotDPR1(regD reg) %{
5295 predicate( UseSSE < 2 );
5296 constraint(ALLOC_IN_RC(dbl_notreg0));
5297 match(reg);
5298 format %{ %}
5299 interface(REG_INTER);
5300 %}
5302 // XMM Double register operands
5303 operand regXD() %{
5304 predicate( UseSSE>=2 );
5305 constraint(ALLOC_IN_RC(xdb_reg));
5306 match(RegD);
5307 match(regXD6);
5308 match(regXD7);
5309 format %{ %}
5310 interface(REG_INTER);
5311 %}
5313 // XMM6 double register operands
5314 operand regXD6(regXD reg) %{
5315 predicate( UseSSE>=2 );
5316 constraint(ALLOC_IN_RC(xdb_reg6));
5317 match(reg);
5318 format %{ "XMM6" %}
5319 interface(REG_INTER);
5320 %}
5322 // XMM7 double register operands
5323 operand regXD7(regXD reg) %{
5324 predicate( UseSSE>=2 );
5325 constraint(ALLOC_IN_RC(xdb_reg7));
5326 match(reg);
5327 format %{ "XMM7" %}
5328 interface(REG_INTER);
5329 %}
5331 // Float register operands
5332 operand regF() %{
5333 predicate( UseSSE < 2 );
5334 constraint(ALLOC_IN_RC(flt_reg));
5335 match(RegF);
5336 match(regFPR1);
5337 format %{ %}
5338 interface(REG_INTER);
5339 %}
5341 // Float register operands
5342 operand regFPR1(regF reg) %{
5343 predicate( UseSSE < 2 );
5344 constraint(ALLOC_IN_RC(flt_reg0));
5345 match(reg);
5346 format %{ "FPR1" %}
5347 interface(REG_INTER);
5348 %}
5350 // XMM register operands
5351 operand regX() %{
5352 predicate( UseSSE>=1 );
5353 constraint(ALLOC_IN_RC(xmm_reg));
5354 match(RegF);
5355 format %{ %}
5356 interface(REG_INTER);
5357 %}
5360 //----------Memory Operands----------------------------------------------------
5361 // Direct Memory Operand
5362 operand direct(immP addr) %{
5363 match(addr);
5365 format %{ "[$addr]" %}
5366 interface(MEMORY_INTER) %{
5367 base(0xFFFFFFFF);
5368 index(0x4);
5369 scale(0x0);
5370 disp($addr);
5371 %}
5372 %}
5374 // Indirect Memory Operand
5375 operand indirect(eRegP reg) %{
5376 constraint(ALLOC_IN_RC(e_reg));
5377 match(reg);
5379 format %{ "[$reg]" %}
5380 interface(MEMORY_INTER) %{
5381 base($reg);
5382 index(0x4);
5383 scale(0x0);
5384 disp(0x0);
5385 %}
5386 %}
5388 // Indirect Memory Plus Short Offset Operand
5389 operand indOffset8(eRegP reg, immI8 off) %{
5390 match(AddP reg off);
5392 format %{ "[$reg + $off]" %}
5393 interface(MEMORY_INTER) %{
5394 base($reg);
5395 index(0x4);
5396 scale(0x0);
5397 disp($off);
5398 %}
5399 %}
5401 // Indirect Memory Plus Long Offset Operand
5402 operand indOffset32(eRegP reg, immI off) %{
5403 match(AddP reg off);
5405 format %{ "[$reg + $off]" %}
5406 interface(MEMORY_INTER) %{
5407 base($reg);
5408 index(0x4);
5409 scale(0x0);
5410 disp($off);
5411 %}
5412 %}
5414 // Indirect Memory Plus Long Offset Operand
5415 operand indOffset32X(eRegI reg, immP off) %{
5416 match(AddP off reg);
5418 format %{ "[$reg + $off]" %}
5419 interface(MEMORY_INTER) %{
5420 base($reg);
5421 index(0x4);
5422 scale(0x0);
5423 disp($off);
5424 %}
5425 %}
5427 // Indirect Memory Plus Index Register Plus Offset Operand
5428 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5429 match(AddP (AddP reg ireg) off);
5431 op_cost(10);
5432 format %{"[$reg + $off + $ireg]" %}
5433 interface(MEMORY_INTER) %{
5434 base($reg);
5435 index($ireg);
5436 scale(0x0);
5437 disp($off);
5438 %}
5439 %}
5441 // Indirect Memory Plus Index Register Plus Offset Operand
5442 operand indIndex(eRegP reg, eRegI ireg) %{
5443 match(AddP reg ireg);
5445 op_cost(10);
5446 format %{"[$reg + $ireg]" %}
5447 interface(MEMORY_INTER) %{
5448 base($reg);
5449 index($ireg);
5450 scale(0x0);
5451 disp(0x0);
5452 %}
5453 %}
5455 // // -------------------------------------------------------------------------
5456 // // 486 architecture doesn't support "scale * index + offset" with out a base
5457 // // -------------------------------------------------------------------------
5458 // // Scaled Memory Operands
5459 // // Indirect Memory Times Scale Plus Offset Operand
5460 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5461 // match(AddP off (LShiftI ireg scale));
5462 //
5463 // op_cost(10);
5464 // format %{"[$off + $ireg << $scale]" %}
5465 // interface(MEMORY_INTER) %{
5466 // base(0x4);
5467 // index($ireg);
5468 // scale($scale);
5469 // disp($off);
5470 // %}
5471 // %}
5473 // Indirect Memory Times Scale Plus Index Register
5474 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5475 match(AddP reg (LShiftI ireg scale));
5477 op_cost(10);
5478 format %{"[$reg + $ireg << $scale]" %}
5479 interface(MEMORY_INTER) %{
5480 base($reg);
5481 index($ireg);
5482 scale($scale);
5483 disp(0x0);
5484 %}
5485 %}
5487 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5488 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5489 match(AddP (AddP reg (LShiftI ireg scale)) off);
5491 op_cost(10);
5492 format %{"[$reg + $off + $ireg << $scale]" %}
5493 interface(MEMORY_INTER) %{
5494 base($reg);
5495 index($ireg);
5496 scale($scale);
5497 disp($off);
5498 %}
5499 %}
5501 //----------Load Long Memory Operands------------------------------------------
5502 // The load-long idiom will use it's address expression again after loading
5503 // the first word of the long. If the load-long destination overlaps with
5504 // registers used in the addressing expression, the 2nd half will be loaded
5505 // from a clobbered address. Fix this by requiring that load-long use
5506 // address registers that do not overlap with the load-long target.
5508 // load-long support
5509 operand load_long_RegP() %{
5510 constraint(ALLOC_IN_RC(esi_reg));
5511 match(RegP);
5512 match(eSIRegP);
5513 op_cost(100);
5514 format %{ %}
5515 interface(REG_INTER);
5516 %}
5518 // Indirect Memory Operand Long
5519 operand load_long_indirect(load_long_RegP reg) %{
5520 constraint(ALLOC_IN_RC(esi_reg));
5521 match(reg);
5523 format %{ "[$reg]" %}
5524 interface(MEMORY_INTER) %{
5525 base($reg);
5526 index(0x4);
5527 scale(0x0);
5528 disp(0x0);
5529 %}
5530 %}
5532 // Indirect Memory Plus Long Offset Operand
5533 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5534 match(AddP reg off);
5536 format %{ "[$reg + $off]" %}
5537 interface(MEMORY_INTER) %{
5538 base($reg);
5539 index(0x4);
5540 scale(0x0);
5541 disp($off);
5542 %}
5543 %}
5545 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5548 //----------Special Memory Operands--------------------------------------------
5549 // Stack Slot Operand - This operand is used for loading and storing temporary
5550 // values on the stack where a match requires a value to
5551 // flow through memory.
5552 operand stackSlotP(sRegP reg) %{
5553 constraint(ALLOC_IN_RC(stack_slots));
5554 // No match rule because this operand is only generated in matching
5555 format %{ "[$reg]" %}
5556 interface(MEMORY_INTER) %{
5557 base(0x4); // ESP
5558 index(0x4); // No Index
5559 scale(0x0); // No Scale
5560 disp($reg); // Stack Offset
5561 %}
5562 %}
5564 operand stackSlotI(sRegI reg) %{
5565 constraint(ALLOC_IN_RC(stack_slots));
5566 // No match rule because this operand is only generated in matching
5567 format %{ "[$reg]" %}
5568 interface(MEMORY_INTER) %{
5569 base(0x4); // ESP
5570 index(0x4); // No Index
5571 scale(0x0); // No Scale
5572 disp($reg); // Stack Offset
5573 %}
5574 %}
5576 operand stackSlotF(sRegF reg) %{
5577 constraint(ALLOC_IN_RC(stack_slots));
5578 // No match rule because this operand is only generated in matching
5579 format %{ "[$reg]" %}
5580 interface(MEMORY_INTER) %{
5581 base(0x4); // ESP
5582 index(0x4); // No Index
5583 scale(0x0); // No Scale
5584 disp($reg); // Stack Offset
5585 %}
5586 %}
5588 operand stackSlotD(sRegD reg) %{
5589 constraint(ALLOC_IN_RC(stack_slots));
5590 // No match rule because this operand is only generated in matching
5591 format %{ "[$reg]" %}
5592 interface(MEMORY_INTER) %{
5593 base(0x4); // ESP
5594 index(0x4); // No Index
5595 scale(0x0); // No Scale
5596 disp($reg); // Stack Offset
5597 %}
5598 %}
5600 operand stackSlotL(sRegL reg) %{
5601 constraint(ALLOC_IN_RC(stack_slots));
5602 // No match rule because this operand is only generated in matching
5603 format %{ "[$reg]" %}
5604 interface(MEMORY_INTER) %{
5605 base(0x4); // ESP
5606 index(0x4); // No Index
5607 scale(0x0); // No Scale
5608 disp($reg); // Stack Offset
5609 %}
5610 %}
5612 //----------Memory Operands - Win95 Implicit Null Variants----------------
5613 // Indirect Memory Operand
5614 operand indirect_win95_safe(eRegP_no_EBP reg)
5615 %{
5616 constraint(ALLOC_IN_RC(e_reg));
5617 match(reg);
5619 op_cost(100);
5620 format %{ "[$reg]" %}
5621 interface(MEMORY_INTER) %{
5622 base($reg);
5623 index(0x4);
5624 scale(0x0);
5625 disp(0x0);
5626 %}
5627 %}
5629 // Indirect Memory Plus Short Offset Operand
5630 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5631 %{
5632 match(AddP reg off);
5634 op_cost(100);
5635 format %{ "[$reg + $off]" %}
5636 interface(MEMORY_INTER) %{
5637 base($reg);
5638 index(0x4);
5639 scale(0x0);
5640 disp($off);
5641 %}
5642 %}
5644 // Indirect Memory Plus Long Offset Operand
5645 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5646 %{
5647 match(AddP reg off);
5649 op_cost(100);
5650 format %{ "[$reg + $off]" %}
5651 interface(MEMORY_INTER) %{
5652 base($reg);
5653 index(0x4);
5654 scale(0x0);
5655 disp($off);
5656 %}
5657 %}
5659 // Indirect Memory Plus Index Register Plus Offset Operand
5660 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5661 %{
5662 match(AddP (AddP reg ireg) off);
5664 op_cost(100);
5665 format %{"[$reg + $off + $ireg]" %}
5666 interface(MEMORY_INTER) %{
5667 base($reg);
5668 index($ireg);
5669 scale(0x0);
5670 disp($off);
5671 %}
5672 %}
5674 // Indirect Memory Times Scale Plus Index Register
5675 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5676 %{
5677 match(AddP reg (LShiftI ireg scale));
5679 op_cost(100);
5680 format %{"[$reg + $ireg << $scale]" %}
5681 interface(MEMORY_INTER) %{
5682 base($reg);
5683 index($ireg);
5684 scale($scale);
5685 disp(0x0);
5686 %}
5687 %}
5689 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5690 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5691 %{
5692 match(AddP (AddP reg (LShiftI ireg scale)) off);
5694 op_cost(100);
5695 format %{"[$reg + $off + $ireg << $scale]" %}
5696 interface(MEMORY_INTER) %{
5697 base($reg);
5698 index($ireg);
5699 scale($scale);
5700 disp($off);
5701 %}
5702 %}
5704 //----------Conditional Branch Operands----------------------------------------
5705 // Comparison Op - This is the operation of the comparison, and is limited to
5706 // the following set of codes:
5707 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5708 //
5709 // Other attributes of the comparison, such as unsignedness, are specified
5710 // by the comparison instruction that sets a condition code flags register.
5711 // That result is represented by a flags operand whose subtype is appropriate
5712 // to the unsignedness (etc.) of the comparison.
5713 //
5714 // Later, the instruction which matches both the Comparison Op (a Bool) and
5715 // the flags (produced by the Cmp) specifies the coding of the comparison op
5716 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5718 // Comparision Code
5719 operand cmpOp() %{
5720 match(Bool);
5722 format %{ "" %}
5723 interface(COND_INTER) %{
5724 equal(0x4);
5725 not_equal(0x5);
5726 less(0xC);
5727 greater_equal(0xD);
5728 less_equal(0xE);
5729 greater(0xF);
5730 %}
5731 %}
5733 // Comparison Code, unsigned compare. Used by FP also, with
5734 // C2 (unordered) turned into GT or LT already. The other bits
5735 // C0 and C3 are turned into Carry & Zero flags.
5736 operand cmpOpU() %{
5737 match(Bool);
5739 format %{ "" %}
5740 interface(COND_INTER) %{
5741 equal(0x4);
5742 not_equal(0x5);
5743 less(0x2);
5744 greater_equal(0x3);
5745 less_equal(0x6);
5746 greater(0x7);
5747 %}
5748 %}
5750 // Comparison Code for FP conditional move
5751 operand cmpOp_fcmov() %{
5752 match(Bool);
5754 format %{ "" %}
5755 interface(COND_INTER) %{
5756 equal (0x0C8);
5757 not_equal (0x1C8);
5758 less (0x0C0);
5759 greater_equal(0x1C0);
5760 less_equal (0x0D0);
5761 greater (0x1D0);
5762 %}
5763 %}
5765 // Comparision Code used in long compares
5766 operand cmpOp_commute() %{
5767 match(Bool);
5769 format %{ "" %}
5770 interface(COND_INTER) %{
5771 equal(0x4);
5772 not_equal(0x5);
5773 less(0xF);
5774 greater_equal(0xE);
5775 less_equal(0xD);
5776 greater(0xC);
5777 %}
5778 %}
5780 //----------OPERAND CLASSES----------------------------------------------------
5781 // Operand Classes are groups of operands that are used as to simplify
5782 // instruction definitions by not requiring the AD writer to specify seperate
5783 // instructions for every form of operand when the instruction accepts
5784 // multiple operand types with the same basic encoding and format. The classic
5785 // case of this is memory operands.
5787 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5788 indIndex, indIndexScale, indIndexScaleOffset);
5790 // Long memory operations are encoded in 2 instructions and a +4 offset.
5791 // This means some kind of offset is always required and you cannot use
5792 // an oop as the offset (done when working on static globals).
5793 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5794 indIndex, indIndexScale, indIndexScaleOffset);
5797 //----------PIPELINE-----------------------------------------------------------
5798 // Rules which define the behavior of the target architectures pipeline.
5799 pipeline %{
5801 //----------ATTRIBUTES---------------------------------------------------------
5802 attributes %{
5803 variable_size_instructions; // Fixed size instructions
5804 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5805 instruction_unit_size = 1; // An instruction is 1 bytes long
5806 instruction_fetch_unit_size = 16; // The processor fetches one line
5807 instruction_fetch_units = 1; // of 16 bytes
5809 // List of nop instructions
5810 nops( MachNop );
5811 %}
5813 //----------RESOURCES----------------------------------------------------------
5814 // Resources are the functional units available to the machine
5816 // Generic P2/P3 pipeline
5817 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5818 // 3 instructions decoded per cycle.
5819 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5820 // 2 ALU op, only ALU0 handles mul/div instructions.
5821 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5822 MS0, MS1, MEM = MS0 | MS1,
5823 BR, FPU,
5824 ALU0, ALU1, ALU = ALU0 | ALU1 );
5826 //----------PIPELINE DESCRIPTION-----------------------------------------------
5827 // Pipeline Description specifies the stages in the machine's pipeline
5829 // Generic P2/P3 pipeline
5830 pipe_desc(S0, S1, S2, S3, S4, S5);
5832 //----------PIPELINE CLASSES---------------------------------------------------
5833 // Pipeline Classes describe the stages in which input and output are
5834 // referenced by the hardware pipeline.
5836 // Naming convention: ialu or fpu
5837 // Then: _reg
5838 // Then: _reg if there is a 2nd register
5839 // Then: _long if it's a pair of instructions implementing a long
5840 // Then: _fat if it requires the big decoder
5841 // Or: _mem if it requires the big decoder and a memory unit.
5843 // Integer ALU reg operation
5844 pipe_class ialu_reg(eRegI dst) %{
5845 single_instruction;
5846 dst : S4(write);
5847 dst : S3(read);
5848 DECODE : S0; // any decoder
5849 ALU : S3; // any alu
5850 %}
5852 // Long ALU reg operation
5853 pipe_class ialu_reg_long(eRegL dst) %{
5854 instruction_count(2);
5855 dst : S4(write);
5856 dst : S3(read);
5857 DECODE : S0(2); // any 2 decoders
5858 ALU : S3(2); // both alus
5859 %}
5861 // Integer ALU reg operation using big decoder
5862 pipe_class ialu_reg_fat(eRegI dst) %{
5863 single_instruction;
5864 dst : S4(write);
5865 dst : S3(read);
5866 D0 : S0; // big decoder only
5867 ALU : S3; // any alu
5868 %}
5870 // Long ALU reg operation using big decoder
5871 pipe_class ialu_reg_long_fat(eRegL dst) %{
5872 instruction_count(2);
5873 dst : S4(write);
5874 dst : S3(read);
5875 D0 : S0(2); // big decoder only; twice
5876 ALU : S3(2); // any 2 alus
5877 %}
5879 // Integer ALU reg-reg operation
5880 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5881 single_instruction;
5882 dst : S4(write);
5883 src : S3(read);
5884 DECODE : S0; // any decoder
5885 ALU : S3; // any alu
5886 %}
5888 // Long ALU reg-reg operation
5889 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5890 instruction_count(2);
5891 dst : S4(write);
5892 src : S3(read);
5893 DECODE : S0(2); // any 2 decoders
5894 ALU : S3(2); // both alus
5895 %}
5897 // Integer ALU reg-reg operation
5898 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5899 single_instruction;
5900 dst : S4(write);
5901 src : S3(read);
5902 D0 : S0; // big decoder only
5903 ALU : S3; // any alu
5904 %}
5906 // Long ALU reg-reg operation
5907 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5908 instruction_count(2);
5909 dst : S4(write);
5910 src : S3(read);
5911 D0 : S0(2); // big decoder only; twice
5912 ALU : S3(2); // both alus
5913 %}
5915 // Integer ALU reg-mem operation
5916 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5917 single_instruction;
5918 dst : S5(write);
5919 mem : S3(read);
5920 D0 : S0; // big decoder only
5921 ALU : S4; // any alu
5922 MEM : S3; // any mem
5923 %}
5925 // Long ALU reg-mem operation
5926 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5927 instruction_count(2);
5928 dst : S5(write);
5929 mem : S3(read);
5930 D0 : S0(2); // big decoder only; twice
5931 ALU : S4(2); // any 2 alus
5932 MEM : S3(2); // both mems
5933 %}
5935 // Integer mem operation (prefetch)
5936 pipe_class ialu_mem(memory mem)
5937 %{
5938 single_instruction;
5939 mem : S3(read);
5940 D0 : S0; // big decoder only
5941 MEM : S3; // any mem
5942 %}
5944 // Integer Store to Memory
5945 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5946 single_instruction;
5947 mem : S3(read);
5948 src : S5(read);
5949 D0 : S0; // big decoder only
5950 ALU : S4; // any alu
5951 MEM : S3;
5952 %}
5954 // Long Store to Memory
5955 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5956 instruction_count(2);
5957 mem : S3(read);
5958 src : S5(read);
5959 D0 : S0(2); // big decoder only; twice
5960 ALU : S4(2); // any 2 alus
5961 MEM : S3(2); // Both mems
5962 %}
5964 // Integer Store to Memory
5965 pipe_class ialu_mem_imm(memory mem) %{
5966 single_instruction;
5967 mem : S3(read);
5968 D0 : S0; // big decoder only
5969 ALU : S4; // any alu
5970 MEM : S3;
5971 %}
5973 // Integer ALU0 reg-reg operation
5974 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5975 single_instruction;
5976 dst : S4(write);
5977 src : S3(read);
5978 D0 : S0; // Big decoder only
5979 ALU0 : S3; // only alu0
5980 %}
5982 // Integer ALU0 reg-mem operation
5983 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5984 single_instruction;
5985 dst : S5(write);
5986 mem : S3(read);
5987 D0 : S0; // big decoder only
5988 ALU0 : S4; // ALU0 only
5989 MEM : S3; // any mem
5990 %}
5992 // Integer ALU reg-reg operation
5993 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5994 single_instruction;
5995 cr : S4(write);
5996 src1 : S3(read);
5997 src2 : S3(read);
5998 DECODE : S0; // any decoder
5999 ALU : S3; // any alu
6000 %}
6002 // Integer ALU reg-imm operation
6003 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6004 single_instruction;
6005 cr : S4(write);
6006 src1 : S3(read);
6007 DECODE : S0; // any decoder
6008 ALU : S3; // any alu
6009 %}
6011 // Integer ALU reg-mem operation
6012 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6013 single_instruction;
6014 cr : S4(write);
6015 src1 : S3(read);
6016 src2 : S3(read);
6017 D0 : S0; // big decoder only
6018 ALU : S4; // any alu
6019 MEM : S3;
6020 %}
6022 // Conditional move reg-reg
6023 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6024 instruction_count(4);
6025 y : S4(read);
6026 q : S3(read);
6027 p : S3(read);
6028 DECODE : S0(4); // any decoder
6029 %}
6031 // Conditional move reg-reg
6032 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6033 single_instruction;
6034 dst : S4(write);
6035 src : S3(read);
6036 cr : S3(read);
6037 DECODE : S0; // any decoder
6038 %}
6040 // Conditional move reg-mem
6041 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6042 single_instruction;
6043 dst : S4(write);
6044 src : S3(read);
6045 cr : S3(read);
6046 DECODE : S0; // any decoder
6047 MEM : S3;
6048 %}
6050 // Conditional move reg-reg long
6051 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6052 single_instruction;
6053 dst : S4(write);
6054 src : S3(read);
6055 cr : S3(read);
6056 DECODE : S0(2); // any 2 decoders
6057 %}
6059 // Conditional move double reg-reg
6060 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6061 single_instruction;
6062 dst : S4(write);
6063 src : S3(read);
6064 cr : S3(read);
6065 DECODE : S0; // any decoder
6066 %}
6068 // Float reg-reg operation
6069 pipe_class fpu_reg(regD dst) %{
6070 instruction_count(2);
6071 dst : S3(read);
6072 DECODE : S0(2); // any 2 decoders
6073 FPU : S3;
6074 %}
6076 // Float reg-reg operation
6077 pipe_class fpu_reg_reg(regD dst, regD src) %{
6078 instruction_count(2);
6079 dst : S4(write);
6080 src : S3(read);
6081 DECODE : S0(2); // any 2 decoders
6082 FPU : S3;
6083 %}
6085 // Float reg-reg operation
6086 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6087 instruction_count(3);
6088 dst : S4(write);
6089 src1 : S3(read);
6090 src2 : S3(read);
6091 DECODE : S0(3); // any 3 decoders
6092 FPU : S3(2);
6093 %}
6095 // Float reg-reg operation
6096 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6097 instruction_count(4);
6098 dst : S4(write);
6099 src1 : S3(read);
6100 src2 : S3(read);
6101 src3 : S3(read);
6102 DECODE : S0(4); // any 3 decoders
6103 FPU : S3(2);
6104 %}
6106 // Float reg-reg operation
6107 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6108 instruction_count(4);
6109 dst : S4(write);
6110 src1 : S3(read);
6111 src2 : S3(read);
6112 src3 : S3(read);
6113 DECODE : S1(3); // any 3 decoders
6114 D0 : S0; // Big decoder only
6115 FPU : S3(2);
6116 MEM : S3;
6117 %}
6119 // Float reg-mem operation
6120 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6121 instruction_count(2);
6122 dst : S5(write);
6123 mem : S3(read);
6124 D0 : S0; // big decoder only
6125 DECODE : S1; // any decoder for FPU POP
6126 FPU : S4;
6127 MEM : S3; // any mem
6128 %}
6130 // Float reg-mem operation
6131 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6132 instruction_count(3);
6133 dst : S5(write);
6134 src1 : S3(read);
6135 mem : S3(read);
6136 D0 : S0; // big decoder only
6137 DECODE : S1(2); // any decoder for FPU POP
6138 FPU : S4;
6139 MEM : S3; // any mem
6140 %}
6142 // Float mem-reg operation
6143 pipe_class fpu_mem_reg(memory mem, regD src) %{
6144 instruction_count(2);
6145 src : S5(read);
6146 mem : S3(read);
6147 DECODE : S0; // any decoder for FPU PUSH
6148 D0 : S1; // big decoder only
6149 FPU : S4;
6150 MEM : S3; // any mem
6151 %}
6153 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6154 instruction_count(3);
6155 src1 : S3(read);
6156 src2 : S3(read);
6157 mem : S3(read);
6158 DECODE : S0(2); // any decoder for FPU PUSH
6159 D0 : S1; // big decoder only
6160 FPU : S4;
6161 MEM : S3; // any mem
6162 %}
6164 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6165 instruction_count(3);
6166 src1 : S3(read);
6167 src2 : S3(read);
6168 mem : S4(read);
6169 DECODE : S0; // any decoder for FPU PUSH
6170 D0 : S0(2); // big decoder only
6171 FPU : S4;
6172 MEM : S3(2); // any mem
6173 %}
6175 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6176 instruction_count(2);
6177 src1 : S3(read);
6178 dst : S4(read);
6179 D0 : S0(2); // big decoder only
6180 MEM : S3(2); // any mem
6181 %}
6183 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6184 instruction_count(3);
6185 src1 : S3(read);
6186 src2 : S3(read);
6187 dst : S4(read);
6188 D0 : S0(3); // big decoder only
6189 FPU : S4;
6190 MEM : S3(3); // any mem
6191 %}
6193 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6194 instruction_count(3);
6195 src1 : S4(read);
6196 mem : S4(read);
6197 DECODE : S0; // any decoder for FPU PUSH
6198 D0 : S0(2); // big decoder only
6199 FPU : S4;
6200 MEM : S3(2); // any mem
6201 %}
6203 // Float load constant
6204 pipe_class fpu_reg_con(regD dst) %{
6205 instruction_count(2);
6206 dst : S5(write);
6207 D0 : S0; // big decoder only for the load
6208 DECODE : S1; // any decoder for FPU POP
6209 FPU : S4;
6210 MEM : S3; // any mem
6211 %}
6213 // Float load constant
6214 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6215 instruction_count(3);
6216 dst : S5(write);
6217 src : S3(read);
6218 D0 : S0; // big decoder only for the load
6219 DECODE : S1(2); // any decoder for FPU POP
6220 FPU : S4;
6221 MEM : S3; // any mem
6222 %}
6224 // UnConditional branch
6225 pipe_class pipe_jmp( label labl ) %{
6226 single_instruction;
6227 BR : S3;
6228 %}
6230 // Conditional branch
6231 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6232 single_instruction;
6233 cr : S1(read);
6234 BR : S3;
6235 %}
6237 // Allocation idiom
6238 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6239 instruction_count(1); force_serialization;
6240 fixed_latency(6);
6241 heap_ptr : S3(read);
6242 DECODE : S0(3);
6243 D0 : S2;
6244 MEM : S3;
6245 ALU : S3(2);
6246 dst : S5(write);
6247 BR : S5;
6248 %}
6250 // Generic big/slow expanded idiom
6251 pipe_class pipe_slow( ) %{
6252 instruction_count(10); multiple_bundles; force_serialization;
6253 fixed_latency(100);
6254 D0 : S0(2);
6255 MEM : S3(2);
6256 %}
6258 // The real do-nothing guy
6259 pipe_class empty( ) %{
6260 instruction_count(0);
6261 %}
6263 // Define the class for the Nop node
6264 define %{
6265 MachNop = empty;
6266 %}
6268 %}
6270 //----------INSTRUCTIONS-------------------------------------------------------
6271 //
6272 // match -- States which machine-independent subtree may be replaced
6273 // by this instruction.
6274 // ins_cost -- The estimated cost of this instruction is used by instruction
6275 // selection to identify a minimum cost tree of machine
6276 // instructions that matches a tree of machine-independent
6277 // instructions.
6278 // format -- A string providing the disassembly for this instruction.
6279 // The value of an instruction's operand may be inserted
6280 // by referring to it with a '$' prefix.
6281 // opcode -- Three instruction opcodes may be provided. These are referred
6282 // to within an encode class as $primary, $secondary, and $tertiary
6283 // respectively. The primary opcode is commonly used to
6284 // indicate the type of machine instruction, while secondary
6285 // and tertiary are often used for prefix options or addressing
6286 // modes.
6287 // ins_encode -- A list of encode classes with parameters. The encode class
6288 // name must have been defined in an 'enc_class' specification
6289 // in the encode section of the architecture description.
6291 //----------BSWAP-Instruction--------------------------------------------------
6292 instruct bytes_reverse_int(eRegI dst) %{
6293 match(Set dst (ReverseBytesI dst));
6295 format %{ "BSWAP $dst" %}
6296 opcode(0x0F, 0xC8);
6297 ins_encode( OpcP, OpcSReg(dst) );
6298 ins_pipe( ialu_reg );
6299 %}
6301 instruct bytes_reverse_long(eRegL dst) %{
6302 match(Set dst (ReverseBytesL dst));
6304 format %{ "BSWAP $dst.lo\n\t"
6305 "BSWAP $dst.hi\n\t"
6306 "XCHG $dst.lo $dst.hi" %}
6308 ins_cost(125);
6309 ins_encode( bswap_long_bytes(dst) );
6310 ins_pipe( ialu_reg_reg);
6311 %}
6314 //----------Load/Store/Move Instructions---------------------------------------
6315 //----------Load Instructions--------------------------------------------------
6316 // Load Byte (8bit signed)
6317 instruct loadB(xRegI dst, memory mem) %{
6318 match(Set dst (LoadB mem));
6320 ins_cost(125);
6321 format %{ "MOVSX8 $dst,$mem" %}
6322 opcode(0xBE, 0x0F);
6323 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6324 ins_pipe( ialu_reg_mem );
6325 %}
6327 // Load Byte (8bit UNsigned)
6328 instruct loadUB(xRegI dst, memory mem, immI_255 bytemask) %{
6329 match(Set dst (AndI (LoadB mem) bytemask));
6331 ins_cost(125);
6332 format %{ "MOVZX8 $dst,$mem" %}
6333 opcode(0xB6, 0x0F);
6334 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6335 ins_pipe( ialu_reg_mem );
6336 %}
6338 // Load Char (16bit unsigned)
6339 instruct loadC(eRegI dst, memory mem) %{
6340 match(Set dst (LoadC mem));
6342 ins_cost(125);
6343 format %{ "MOVZX $dst,$mem" %}
6344 opcode(0xB7, 0x0F);
6345 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6346 ins_pipe( ialu_reg_mem );
6347 %}
6349 // Load Integer
6350 instruct loadI(eRegI dst, memory mem) %{
6351 match(Set dst (LoadI mem));
6353 ins_cost(125);
6354 format %{ "MOV $dst,$mem" %}
6355 opcode(0x8B);
6356 ins_encode( OpcP, RegMem(dst,mem));
6357 ins_pipe( ialu_reg_mem );
6358 %}
6360 // Load Long. Cannot clobber address while loading, so restrict address
6361 // register to ESI
6362 instruct loadL(eRegL dst, load_long_memory mem) %{
6363 predicate(!((LoadLNode*)n)->require_atomic_access());
6364 match(Set dst (LoadL mem));
6366 ins_cost(250);
6367 format %{ "MOV $dst.lo,$mem\n\t"
6368 "MOV $dst.hi,$mem+4" %}
6369 opcode(0x8B, 0x8B);
6370 ins_encode( OpcP, RegMem(dst,mem), OpcS, RegMem_Hi(dst,mem));
6371 ins_pipe( ialu_reg_long_mem );
6372 %}
6374 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6375 // then store it down to the stack and reload on the int
6376 // side.
6377 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6378 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6379 match(Set dst (LoadL mem));
6381 ins_cost(200);
6382 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6383 "FISTp $dst" %}
6384 ins_encode(enc_loadL_volatile(mem,dst));
6385 ins_pipe( fpu_reg_mem );
6386 %}
6388 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6389 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6390 match(Set dst (LoadL mem));
6391 effect(TEMP tmp);
6392 ins_cost(180);
6393 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6394 "MOVSD $dst,$tmp" %}
6395 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6396 ins_pipe( pipe_slow );
6397 %}
6399 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6400 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6401 match(Set dst (LoadL mem));
6402 effect(TEMP tmp);
6403 ins_cost(160);
6404 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6405 "MOVD $dst.lo,$tmp\n\t"
6406 "PSRLQ $tmp,32\n\t"
6407 "MOVD $dst.hi,$tmp" %}
6408 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6409 ins_pipe( pipe_slow );
6410 %}
6412 // Load Range
6413 instruct loadRange(eRegI dst, memory mem) %{
6414 match(Set dst (LoadRange mem));
6416 ins_cost(125);
6417 format %{ "MOV $dst,$mem" %}
6418 opcode(0x8B);
6419 ins_encode( OpcP, RegMem(dst,mem));
6420 ins_pipe( ialu_reg_mem );
6421 %}
6424 // Load Pointer
6425 instruct loadP(eRegP dst, memory mem) %{
6426 match(Set dst (LoadP mem));
6428 ins_cost(125);
6429 format %{ "MOV $dst,$mem" %}
6430 opcode(0x8B);
6431 ins_encode( OpcP, RegMem(dst,mem));
6432 ins_pipe( ialu_reg_mem );
6433 %}
6435 // Load Klass Pointer
6436 instruct loadKlass(eRegP dst, memory mem) %{
6437 match(Set dst (LoadKlass mem));
6439 ins_cost(125);
6440 format %{ "MOV $dst,$mem" %}
6441 opcode(0x8B);
6442 ins_encode( OpcP, RegMem(dst,mem));
6443 ins_pipe( ialu_reg_mem );
6444 %}
6446 // Load Short (16bit signed)
6447 instruct loadS(eRegI dst, memory mem) %{
6448 match(Set dst (LoadS mem));
6450 ins_cost(125);
6451 format %{ "MOVSX $dst,$mem" %}
6452 opcode(0xBF, 0x0F);
6453 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6454 ins_pipe( ialu_reg_mem );
6455 %}
6457 // Load Double
6458 instruct loadD(regD dst, memory mem) %{
6459 predicate(UseSSE<=1);
6460 match(Set dst (LoadD mem));
6462 ins_cost(150);
6463 format %{ "FLD_D ST,$mem\n\t"
6464 "FSTP $dst" %}
6465 opcode(0xDD); /* DD /0 */
6466 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6467 Pop_Reg_D(dst) );
6468 ins_pipe( fpu_reg_mem );
6469 %}
6471 // Load Double to XMM
6472 instruct loadXD(regXD dst, memory mem) %{
6473 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6474 match(Set dst (LoadD mem));
6475 ins_cost(145);
6476 format %{ "MOVSD $dst,$mem" %}
6477 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6478 ins_pipe( pipe_slow );
6479 %}
6481 instruct loadXD_partial(regXD dst, memory mem) %{
6482 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6483 match(Set dst (LoadD mem));
6484 ins_cost(145);
6485 format %{ "MOVLPD $dst,$mem" %}
6486 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6487 ins_pipe( pipe_slow );
6488 %}
6490 // Load to XMM register (single-precision floating point)
6491 // MOVSS instruction
6492 instruct loadX(regX dst, memory mem) %{
6493 predicate(UseSSE>=1);
6494 match(Set dst (LoadF mem));
6495 ins_cost(145);
6496 format %{ "MOVSS $dst,$mem" %}
6497 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6498 ins_pipe( pipe_slow );
6499 %}
6501 // Load Float
6502 instruct loadF(regF dst, memory mem) %{
6503 predicate(UseSSE==0);
6504 match(Set dst (LoadF mem));
6506 ins_cost(150);
6507 format %{ "FLD_S ST,$mem\n\t"
6508 "FSTP $dst" %}
6509 opcode(0xD9); /* D9 /0 */
6510 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6511 Pop_Reg_F(dst) );
6512 ins_pipe( fpu_reg_mem );
6513 %}
6515 // Load Aligned Packed Byte to XMM register
6516 instruct loadA8B(regXD dst, memory mem) %{
6517 predicate(UseSSE>=1);
6518 match(Set dst (Load8B mem));
6519 ins_cost(125);
6520 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6521 ins_encode( movq_ld(dst, mem));
6522 ins_pipe( pipe_slow );
6523 %}
6525 // Load Aligned Packed Short to XMM register
6526 instruct loadA4S(regXD dst, memory mem) %{
6527 predicate(UseSSE>=1);
6528 match(Set dst (Load4S mem));
6529 ins_cost(125);
6530 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6531 ins_encode( movq_ld(dst, mem));
6532 ins_pipe( pipe_slow );
6533 %}
6535 // Load Aligned Packed Char to XMM register
6536 instruct loadA4C(regXD dst, memory mem) %{
6537 predicate(UseSSE>=1);
6538 match(Set dst (Load4C mem));
6539 ins_cost(125);
6540 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6541 ins_encode( movq_ld(dst, mem));
6542 ins_pipe( pipe_slow );
6543 %}
6545 // Load Aligned Packed Integer to XMM register
6546 instruct load2IU(regXD dst, memory mem) %{
6547 predicate(UseSSE>=1);
6548 match(Set dst (Load2I mem));
6549 ins_cost(125);
6550 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6551 ins_encode( movq_ld(dst, mem));
6552 ins_pipe( pipe_slow );
6553 %}
6555 // Load Aligned Packed Single to XMM
6556 instruct loadA2F(regXD dst, memory mem) %{
6557 predicate(UseSSE>=1);
6558 match(Set dst (Load2F mem));
6559 ins_cost(145);
6560 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6561 ins_encode( movq_ld(dst, mem));
6562 ins_pipe( pipe_slow );
6563 %}
6565 // Load Effective Address
6566 instruct leaP8(eRegP dst, indOffset8 mem) %{
6567 match(Set dst mem);
6569 ins_cost(110);
6570 format %{ "LEA $dst,$mem" %}
6571 opcode(0x8D);
6572 ins_encode( OpcP, RegMem(dst,mem));
6573 ins_pipe( ialu_reg_reg_fat );
6574 %}
6576 instruct leaP32(eRegP dst, indOffset32 mem) %{
6577 match(Set dst mem);
6579 ins_cost(110);
6580 format %{ "LEA $dst,$mem" %}
6581 opcode(0x8D);
6582 ins_encode( OpcP, RegMem(dst,mem));
6583 ins_pipe( ialu_reg_reg_fat );
6584 %}
6586 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6587 match(Set dst mem);
6589 ins_cost(110);
6590 format %{ "LEA $dst,$mem" %}
6591 opcode(0x8D);
6592 ins_encode( OpcP, RegMem(dst,mem));
6593 ins_pipe( ialu_reg_reg_fat );
6594 %}
6596 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6597 match(Set dst mem);
6599 ins_cost(110);
6600 format %{ "LEA $dst,$mem" %}
6601 opcode(0x8D);
6602 ins_encode( OpcP, RegMem(dst,mem));
6603 ins_pipe( ialu_reg_reg_fat );
6604 %}
6606 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6607 match(Set dst mem);
6609 ins_cost(110);
6610 format %{ "LEA $dst,$mem" %}
6611 opcode(0x8D);
6612 ins_encode( OpcP, RegMem(dst,mem));
6613 ins_pipe( ialu_reg_reg_fat );
6614 %}
6616 // Load Constant
6617 instruct loadConI(eRegI dst, immI src) %{
6618 match(Set dst src);
6620 format %{ "MOV $dst,$src" %}
6621 ins_encode( LdImmI(dst, src) );
6622 ins_pipe( ialu_reg_fat );
6623 %}
6625 // Load Constant zero
6626 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6627 match(Set dst src);
6628 effect(KILL cr);
6630 ins_cost(50);
6631 format %{ "XOR $dst,$dst" %}
6632 opcode(0x33); /* + rd */
6633 ins_encode( OpcP, RegReg( dst, dst ) );
6634 ins_pipe( ialu_reg );
6635 %}
6637 instruct loadConP(eRegP dst, immP src) %{
6638 match(Set dst src);
6640 format %{ "MOV $dst,$src" %}
6641 opcode(0xB8); /* + rd */
6642 ins_encode( LdImmP(dst, src) );
6643 ins_pipe( ialu_reg_fat );
6644 %}
6646 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6647 match(Set dst src);
6648 effect(KILL cr);
6649 ins_cost(200);
6650 format %{ "MOV $dst.lo,$src.lo\n\t"
6651 "MOV $dst.hi,$src.hi" %}
6652 opcode(0xB8);
6653 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6654 ins_pipe( ialu_reg_long_fat );
6655 %}
6657 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6658 match(Set dst src);
6659 effect(KILL cr);
6660 ins_cost(150);
6661 format %{ "XOR $dst.lo,$dst.lo\n\t"
6662 "XOR $dst.hi,$dst.hi" %}
6663 opcode(0x33,0x33);
6664 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6665 ins_pipe( ialu_reg_long );
6666 %}
6668 // The instruction usage is guarded by predicate in operand immF().
6669 instruct loadConF(regF dst, immF src) %{
6670 match(Set dst src);
6671 ins_cost(125);
6673 format %{ "FLD_S ST,$src\n\t"
6674 "FSTP $dst" %}
6675 opcode(0xD9, 0x00); /* D9 /0 */
6676 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
6677 ins_pipe( fpu_reg_con );
6678 %}
6680 // The instruction usage is guarded by predicate in operand immXF().
6681 instruct loadConX(regX dst, immXF con) %{
6682 match(Set dst con);
6683 ins_cost(125);
6684 format %{ "MOVSS $dst,[$con]" %}
6685 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
6686 ins_pipe( pipe_slow );
6687 %}
6689 // The instruction usage is guarded by predicate in operand immXF0().
6690 instruct loadConX0(regX dst, immXF0 src) %{
6691 match(Set dst src);
6692 ins_cost(100);
6693 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6694 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6695 ins_pipe( pipe_slow );
6696 %}
6698 // The instruction usage is guarded by predicate in operand immD().
6699 instruct loadConD(regD dst, immD src) %{
6700 match(Set dst src);
6701 ins_cost(125);
6703 format %{ "FLD_D ST,$src\n\t"
6704 "FSTP $dst" %}
6705 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
6706 ins_pipe( fpu_reg_con );
6707 %}
6709 // The instruction usage is guarded by predicate in operand immXD().
6710 instruct loadConXD(regXD dst, immXD con) %{
6711 match(Set dst con);
6712 ins_cost(125);
6713 format %{ "MOVSD $dst,[$con]" %}
6714 ins_encode(load_conXD(dst, con));
6715 ins_pipe( pipe_slow );
6716 %}
6718 // The instruction usage is guarded by predicate in operand immXD0().
6719 instruct loadConXD0(regXD dst, immXD0 src) %{
6720 match(Set dst src);
6721 ins_cost(100);
6722 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6723 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6724 ins_pipe( pipe_slow );
6725 %}
6727 // Load Stack Slot
6728 instruct loadSSI(eRegI dst, stackSlotI src) %{
6729 match(Set dst src);
6730 ins_cost(125);
6732 format %{ "MOV $dst,$src" %}
6733 opcode(0x8B);
6734 ins_encode( OpcP, RegMem(dst,src));
6735 ins_pipe( ialu_reg_mem );
6736 %}
6738 instruct loadSSL(eRegL dst, stackSlotL src) %{
6739 match(Set dst src);
6741 ins_cost(200);
6742 format %{ "MOV $dst,$src.lo\n\t"
6743 "MOV $dst+4,$src.hi" %}
6744 opcode(0x8B, 0x8B);
6745 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6746 ins_pipe( ialu_mem_long_reg );
6747 %}
6749 // Load Stack Slot
6750 instruct loadSSP(eRegP dst, stackSlotP src) %{
6751 match(Set dst src);
6752 ins_cost(125);
6754 format %{ "MOV $dst,$src" %}
6755 opcode(0x8B);
6756 ins_encode( OpcP, RegMem(dst,src));
6757 ins_pipe( ialu_reg_mem );
6758 %}
6760 // Load Stack Slot
6761 instruct loadSSF(regF dst, stackSlotF src) %{
6762 match(Set dst src);
6763 ins_cost(125);
6765 format %{ "FLD_S $src\n\t"
6766 "FSTP $dst" %}
6767 opcode(0xD9); /* D9 /0, FLD m32real */
6768 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6769 Pop_Reg_F(dst) );
6770 ins_pipe( fpu_reg_mem );
6771 %}
6773 // Load Stack Slot
6774 instruct loadSSD(regD dst, stackSlotD src) %{
6775 match(Set dst src);
6776 ins_cost(125);
6778 format %{ "FLD_D $src\n\t"
6779 "FSTP $dst" %}
6780 opcode(0xDD); /* DD /0, FLD m64real */
6781 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6782 Pop_Reg_D(dst) );
6783 ins_pipe( fpu_reg_mem );
6784 %}
6786 // Prefetch instructions.
6787 // Must be safe to execute with invalid address (cannot fault).
6789 instruct prefetchr0( memory mem ) %{
6790 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
6791 match(PrefetchRead mem);
6792 ins_cost(0);
6793 size(0);
6794 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6795 ins_encode();
6796 ins_pipe(empty);
6797 %}
6799 instruct prefetchr( memory mem ) %{
6800 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
6801 match(PrefetchRead mem);
6802 ins_cost(100);
6804 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6805 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
6806 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6807 ins_pipe(ialu_mem);
6808 %}
6810 instruct prefetchrNTA( memory mem ) %{
6811 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6812 match(PrefetchRead mem);
6813 ins_cost(100);
6815 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6816 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6817 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6818 ins_pipe(ialu_mem);
6819 %}
6821 instruct prefetchrT0( memory mem ) %{
6822 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6823 match(PrefetchRead mem);
6824 ins_cost(100);
6826 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6827 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6828 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6829 ins_pipe(ialu_mem);
6830 %}
6832 instruct prefetchrT2( memory mem ) %{
6833 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6834 match(PrefetchRead mem);
6835 ins_cost(100);
6837 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6838 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6839 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
6840 ins_pipe(ialu_mem);
6841 %}
6843 instruct prefetchw0( memory mem ) %{
6844 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
6845 match(PrefetchWrite mem);
6846 ins_cost(0);
6847 size(0);
6848 format %{ "Prefetch (non-SSE is empty encoding)" %}
6849 ins_encode();
6850 ins_pipe(empty);
6851 %}
6853 instruct prefetchw( memory mem ) %{
6854 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
6855 match( PrefetchWrite mem );
6856 ins_cost(100);
6858 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6859 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6860 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6861 ins_pipe(ialu_mem);
6862 %}
6864 instruct prefetchwNTA( memory mem ) %{
6865 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6866 match(PrefetchWrite mem);
6867 ins_cost(100);
6869 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6870 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6871 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6872 ins_pipe(ialu_mem);
6873 %}
6875 instruct prefetchwT0( memory mem ) %{
6876 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6877 match(PrefetchWrite mem);
6878 ins_cost(100);
6880 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
6881 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6882 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6883 ins_pipe(ialu_mem);
6884 %}
6886 instruct prefetchwT2( memory mem ) %{
6887 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6888 match(PrefetchWrite mem);
6889 ins_cost(100);
6891 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
6892 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6893 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
6894 ins_pipe(ialu_mem);
6895 %}
6897 //----------Store Instructions-------------------------------------------------
6899 // Store Byte
6900 instruct storeB(memory mem, xRegI src) %{
6901 match(Set mem (StoreB mem src));
6903 ins_cost(125);
6904 format %{ "MOV8 $mem,$src" %}
6905 opcode(0x88);
6906 ins_encode( OpcP, RegMem( src, mem ) );
6907 ins_pipe( ialu_mem_reg );
6908 %}
6910 // Store Char/Short
6911 instruct storeC(memory mem, eRegI src) %{
6912 match(Set mem (StoreC mem src));
6914 ins_cost(125);
6915 format %{ "MOV16 $mem,$src" %}
6916 opcode(0x89, 0x66);
6917 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6918 ins_pipe( ialu_mem_reg );
6919 %}
6921 // Store Integer
6922 instruct storeI(memory mem, eRegI src) %{
6923 match(Set mem (StoreI mem src));
6925 ins_cost(125);
6926 format %{ "MOV $mem,$src" %}
6927 opcode(0x89);
6928 ins_encode( OpcP, RegMem( src, mem ) );
6929 ins_pipe( ialu_mem_reg );
6930 %}
6932 // Store Long
6933 instruct storeL(long_memory mem, eRegL src) %{
6934 predicate(!((StoreLNode*)n)->require_atomic_access());
6935 match(Set mem (StoreL mem src));
6937 ins_cost(200);
6938 format %{ "MOV $mem,$src.lo\n\t"
6939 "MOV $mem+4,$src.hi" %}
6940 opcode(0x89, 0x89);
6941 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6942 ins_pipe( ialu_mem_long_reg );
6943 %}
6945 // Volatile Store Long. Must be atomic, so move it into
6946 // the FP TOS and then do a 64-bit FIST. Has to probe the
6947 // target address before the store (for null-ptr checks)
6948 // so the memory operand is used twice in the encoding.
6949 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6950 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6951 match(Set mem (StoreL mem src));
6952 effect( KILL cr );
6953 ins_cost(400);
6954 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6955 "FILD $src\n\t"
6956 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6957 opcode(0x3B);
6958 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6959 ins_pipe( fpu_reg_mem );
6960 %}
6962 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
6963 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6964 match(Set mem (StoreL mem src));
6965 effect( TEMP tmp, KILL cr );
6966 ins_cost(380);
6967 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6968 "MOVSD $tmp,$src\n\t"
6969 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6970 opcode(0x3B);
6971 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
6972 ins_pipe( pipe_slow );
6973 %}
6975 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
6976 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6977 match(Set mem (StoreL mem src));
6978 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6979 ins_cost(360);
6980 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6981 "MOVD $tmp,$src.lo\n\t"
6982 "MOVD $tmp2,$src.hi\n\t"
6983 "PUNPCKLDQ $tmp,$tmp2\n\t"
6984 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6985 opcode(0x3B);
6986 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
6987 ins_pipe( pipe_slow );
6988 %}
6990 // Store Pointer; for storing unknown oops and raw pointers
6991 instruct storeP(memory mem, anyRegP src) %{
6992 match(Set mem (StoreP mem src));
6994 ins_cost(125);
6995 format %{ "MOV $mem,$src" %}
6996 opcode(0x89);
6997 ins_encode( OpcP, RegMem( src, mem ) );
6998 ins_pipe( ialu_mem_reg );
6999 %}
7001 // Store Integer Immediate
7002 instruct storeImmI(memory mem, immI src) %{
7003 match(Set mem (StoreI mem src));
7005 ins_cost(150);
7006 format %{ "MOV $mem,$src" %}
7007 opcode(0xC7); /* C7 /0 */
7008 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7009 ins_pipe( ialu_mem_imm );
7010 %}
7012 // Store Short/Char Immediate
7013 instruct storeImmI16(memory mem, immI16 src) %{
7014 predicate(UseStoreImmI16);
7015 match(Set mem (StoreC mem src));
7017 ins_cost(150);
7018 format %{ "MOV16 $mem,$src" %}
7019 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7020 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7021 ins_pipe( ialu_mem_imm );
7022 %}
7024 // Store Pointer Immediate; null pointers or constant oops that do not
7025 // need card-mark barriers.
7026 instruct storeImmP(memory mem, immP src) %{
7027 match(Set mem (StoreP mem src));
7029 ins_cost(150);
7030 format %{ "MOV $mem,$src" %}
7031 opcode(0xC7); /* C7 /0 */
7032 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7033 ins_pipe( ialu_mem_imm );
7034 %}
7036 // Store Byte Immediate
7037 instruct storeImmB(memory mem, immI8 src) %{
7038 match(Set mem (StoreB mem src));
7040 ins_cost(150);
7041 format %{ "MOV8 $mem,$src" %}
7042 opcode(0xC6); /* C6 /0 */
7043 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7044 ins_pipe( ialu_mem_imm );
7045 %}
7047 // Store Aligned Packed Byte XMM register to memory
7048 instruct storeA8B(memory mem, regXD src) %{
7049 predicate(UseSSE>=1);
7050 match(Set mem (Store8B mem src));
7051 ins_cost(145);
7052 format %{ "MOVQ $mem,$src\t! packed8B" %}
7053 ins_encode( movq_st(mem, src));
7054 ins_pipe( pipe_slow );
7055 %}
7057 // Store Aligned Packed Char/Short XMM register to memory
7058 instruct storeA4C(memory mem, regXD src) %{
7059 predicate(UseSSE>=1);
7060 match(Set mem (Store4C mem src));
7061 ins_cost(145);
7062 format %{ "MOVQ $mem,$src\t! packed4C" %}
7063 ins_encode( movq_st(mem, src));
7064 ins_pipe( pipe_slow );
7065 %}
7067 // Store Aligned Packed Integer XMM register to memory
7068 instruct storeA2I(memory mem, regXD src) %{
7069 predicate(UseSSE>=1);
7070 match(Set mem (Store2I mem src));
7071 ins_cost(145);
7072 format %{ "MOVQ $mem,$src\t! packed2I" %}
7073 ins_encode( movq_st(mem, src));
7074 ins_pipe( pipe_slow );
7075 %}
7077 // Store CMS card-mark Immediate
7078 instruct storeImmCM(memory mem, immI8 src) %{
7079 match(Set mem (StoreCM mem src));
7081 ins_cost(150);
7082 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7083 opcode(0xC6); /* C6 /0 */
7084 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7085 ins_pipe( ialu_mem_imm );
7086 %}
7088 // Store Double
7089 instruct storeD( memory mem, regDPR1 src) %{
7090 predicate(UseSSE<=1);
7091 match(Set mem (StoreD mem src));
7093 ins_cost(100);
7094 format %{ "FST_D $mem,$src" %}
7095 opcode(0xDD); /* DD /2 */
7096 ins_encode( enc_FP_store(mem,src) );
7097 ins_pipe( fpu_mem_reg );
7098 %}
7100 // Store double does rounding on x86
7101 instruct storeD_rounded( memory mem, regDPR1 src) %{
7102 predicate(UseSSE<=1);
7103 match(Set mem (StoreD mem (RoundDouble src)));
7105 ins_cost(100);
7106 format %{ "FST_D $mem,$src\t# round" %}
7107 opcode(0xDD); /* DD /2 */
7108 ins_encode( enc_FP_store(mem,src) );
7109 ins_pipe( fpu_mem_reg );
7110 %}
7112 // Store XMM register to memory (double-precision floating points)
7113 // MOVSD instruction
7114 instruct storeXD(memory mem, regXD src) %{
7115 predicate(UseSSE>=2);
7116 match(Set mem (StoreD mem src));
7117 ins_cost(95);
7118 format %{ "MOVSD $mem,$src" %}
7119 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7120 ins_pipe( pipe_slow );
7121 %}
7123 // Store XMM register to memory (single-precision floating point)
7124 // MOVSS instruction
7125 instruct storeX(memory mem, regX src) %{
7126 predicate(UseSSE>=1);
7127 match(Set mem (StoreF mem src));
7128 ins_cost(95);
7129 format %{ "MOVSS $mem,$src" %}
7130 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7131 ins_pipe( pipe_slow );
7132 %}
7134 // Store Aligned Packed Single Float XMM register to memory
7135 instruct storeA2F(memory mem, regXD src) %{
7136 predicate(UseSSE>=1);
7137 match(Set mem (Store2F mem src));
7138 ins_cost(145);
7139 format %{ "MOVQ $mem,$src\t! packed2F" %}
7140 ins_encode( movq_st(mem, src));
7141 ins_pipe( pipe_slow );
7142 %}
7144 // Store Float
7145 instruct storeF( memory mem, regFPR1 src) %{
7146 predicate(UseSSE==0);
7147 match(Set mem (StoreF mem src));
7149 ins_cost(100);
7150 format %{ "FST_S $mem,$src" %}
7151 opcode(0xD9); /* D9 /2 */
7152 ins_encode( enc_FP_store(mem,src) );
7153 ins_pipe( fpu_mem_reg );
7154 %}
7156 // Store Float does rounding on x86
7157 instruct storeF_rounded( memory mem, regFPR1 src) %{
7158 predicate(UseSSE==0);
7159 match(Set mem (StoreF mem (RoundFloat src)));
7161 ins_cost(100);
7162 format %{ "FST_S $mem,$src\t# round" %}
7163 opcode(0xD9); /* D9 /2 */
7164 ins_encode( enc_FP_store(mem,src) );
7165 ins_pipe( fpu_mem_reg );
7166 %}
7168 // Store Float does rounding on x86
7169 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7170 predicate(UseSSE<=1);
7171 match(Set mem (StoreF mem (ConvD2F src)));
7173 ins_cost(100);
7174 format %{ "FST_S $mem,$src\t# D-round" %}
7175 opcode(0xD9); /* D9 /2 */
7176 ins_encode( enc_FP_store(mem,src) );
7177 ins_pipe( fpu_mem_reg );
7178 %}
7180 // Store immediate Float value (it is faster than store from FPU register)
7181 // The instruction usage is guarded by predicate in operand immF().
7182 instruct storeF_imm( memory mem, immF src) %{
7183 match(Set mem (StoreF mem src));
7185 ins_cost(50);
7186 format %{ "MOV $mem,$src\t# store float" %}
7187 opcode(0xC7); /* C7 /0 */
7188 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7189 ins_pipe( ialu_mem_imm );
7190 %}
7192 // Store immediate Float value (it is faster than store from XMM register)
7193 // The instruction usage is guarded by predicate in operand immXF().
7194 instruct storeX_imm( memory mem, immXF src) %{
7195 match(Set mem (StoreF mem src));
7197 ins_cost(50);
7198 format %{ "MOV $mem,$src\t# store float" %}
7199 opcode(0xC7); /* C7 /0 */
7200 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7201 ins_pipe( ialu_mem_imm );
7202 %}
7204 // Store Integer to stack slot
7205 instruct storeSSI(stackSlotI dst, eRegI src) %{
7206 match(Set dst src);
7208 ins_cost(100);
7209 format %{ "MOV $dst,$src" %}
7210 opcode(0x89);
7211 ins_encode( OpcPRegSS( dst, src ) );
7212 ins_pipe( ialu_mem_reg );
7213 %}
7215 // Store Integer to stack slot
7216 instruct storeSSP(stackSlotP dst, eRegP src) %{
7217 match(Set dst src);
7219 ins_cost(100);
7220 format %{ "MOV $dst,$src" %}
7221 opcode(0x89);
7222 ins_encode( OpcPRegSS( dst, src ) );
7223 ins_pipe( ialu_mem_reg );
7224 %}
7226 // Store Long to stack slot
7227 instruct storeSSL(stackSlotL dst, eRegL src) %{
7228 match(Set dst src);
7230 ins_cost(200);
7231 format %{ "MOV $dst,$src.lo\n\t"
7232 "MOV $dst+4,$src.hi" %}
7233 opcode(0x89, 0x89);
7234 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7235 ins_pipe( ialu_mem_long_reg );
7236 %}
7238 //----------MemBar Instructions-----------------------------------------------
7239 // Memory barrier flavors
7241 instruct membar_acquire() %{
7242 match(MemBarAcquire);
7243 ins_cost(400);
7245 size(0);
7246 format %{ "MEMBAR-acquire" %}
7247 ins_encode( enc_membar_acquire );
7248 ins_pipe(pipe_slow);
7249 %}
7251 instruct membar_acquire_lock() %{
7252 match(MemBarAcquire);
7253 predicate(Matcher::prior_fast_lock(n));
7254 ins_cost(0);
7256 size(0);
7257 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7258 ins_encode( );
7259 ins_pipe(empty);
7260 %}
7262 instruct membar_release() %{
7263 match(MemBarRelease);
7264 ins_cost(400);
7266 size(0);
7267 format %{ "MEMBAR-release" %}
7268 ins_encode( enc_membar_release );
7269 ins_pipe(pipe_slow);
7270 %}
7272 instruct membar_release_lock() %{
7273 match(MemBarRelease);
7274 predicate(Matcher::post_fast_unlock(n));
7275 ins_cost(0);
7277 size(0);
7278 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7279 ins_encode( );
7280 ins_pipe(empty);
7281 %}
7283 instruct membar_volatile() %{
7284 match(MemBarVolatile);
7285 ins_cost(400);
7287 format %{ "MEMBAR-volatile" %}
7288 ins_encode( enc_membar_volatile );
7289 ins_pipe(pipe_slow);
7290 %}
7292 instruct unnecessary_membar_volatile() %{
7293 match(MemBarVolatile);
7294 predicate(Matcher::post_store_load_barrier(n));
7295 ins_cost(0);
7297 size(0);
7298 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7299 ins_encode( );
7300 ins_pipe(empty);
7301 %}
7303 //----------Move Instructions--------------------------------------------------
7304 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7305 match(Set dst (CastX2P src));
7306 format %{ "# X2P $dst, $src" %}
7307 ins_encode( /*empty encoding*/ );
7308 ins_cost(0);
7309 ins_pipe(empty);
7310 %}
7312 instruct castP2X(eRegI dst, eRegP src ) %{
7313 match(Set dst (CastP2X src));
7314 ins_cost(50);
7315 format %{ "MOV $dst, $src\t# CastP2X" %}
7316 ins_encode( enc_Copy( dst, src) );
7317 ins_pipe( ialu_reg_reg );
7318 %}
7320 //----------Conditional Move---------------------------------------------------
7321 // Conditional move
7322 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7323 predicate(VM_Version::supports_cmov() );
7324 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7325 ins_cost(200);
7326 format %{ "CMOV$cop $dst,$src" %}
7327 opcode(0x0F,0x40);
7328 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7329 ins_pipe( pipe_cmov_reg );
7330 %}
7332 instruct cmovI_regU( eRegI dst, eRegI src, eFlagsRegU cr, cmpOpU cop ) %{
7333 predicate(VM_Version::supports_cmov() );
7334 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7335 ins_cost(200);
7336 format %{ "CMOV$cop $dst,$src" %}
7337 opcode(0x0F,0x40);
7338 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7339 ins_pipe( pipe_cmov_reg );
7340 %}
7342 // Conditional move
7343 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7344 predicate(VM_Version::supports_cmov() );
7345 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7346 ins_cost(250);
7347 format %{ "CMOV$cop $dst,$src" %}
7348 opcode(0x0F,0x40);
7349 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7350 ins_pipe( pipe_cmov_mem );
7351 %}
7353 // Conditional move
7354 instruct cmovI_memu(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7355 predicate(VM_Version::supports_cmov() );
7356 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7357 ins_cost(250);
7358 format %{ "CMOV$cop $dst,$src" %}
7359 opcode(0x0F,0x40);
7360 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7361 ins_pipe( pipe_cmov_mem );
7362 %}
7364 // Conditional move
7365 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7366 predicate(VM_Version::supports_cmov() );
7367 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7368 ins_cost(200);
7369 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7370 opcode(0x0F,0x40);
7371 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7372 ins_pipe( pipe_cmov_reg );
7373 %}
7375 // Conditional move (non-P6 version)
7376 // Note: a CMoveP is generated for stubs and native wrappers
7377 // regardless of whether we are on a P6, so we
7378 // emulate a cmov here
7379 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7380 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7381 ins_cost(300);
7382 format %{ "Jn$cop skip\n\t"
7383 "MOV $dst,$src\t# pointer\n"
7384 "skip:" %}
7385 opcode(0x8b);
7386 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7387 ins_pipe( pipe_cmov_reg );
7388 %}
7390 // Conditional move
7391 instruct cmovP_regU(eRegP dst, eRegP src, eFlagsRegU cr, cmpOpU cop ) %{
7392 predicate(VM_Version::supports_cmov() );
7393 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7394 ins_cost(200);
7395 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7396 opcode(0x0F,0x40);
7397 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7398 ins_pipe( pipe_cmov_reg );
7399 %}
7401 // DISABLED: Requires the ADLC to emit a bottom_type call that
7402 // correctly meets the two pointer arguments; one is an incoming
7403 // register but the other is a memory operand. ALSO appears to
7404 // be buggy with implicit null checks.
7405 //
7406 //// Conditional move
7407 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7408 // predicate(VM_Version::supports_cmov() );
7409 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7410 // ins_cost(250);
7411 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7412 // opcode(0x0F,0x40);
7413 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7414 // ins_pipe( pipe_cmov_mem );
7415 //%}
7416 //
7417 //// Conditional move
7418 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7419 // predicate(VM_Version::supports_cmov() );
7420 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7421 // ins_cost(250);
7422 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7423 // opcode(0x0F,0x40);
7424 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7425 // ins_pipe( pipe_cmov_mem );
7426 //%}
7428 // Conditional move
7429 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7430 predicate(UseSSE<=1);
7431 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7432 ins_cost(200);
7433 format %{ "FCMOV$cop $dst,$src\t# double" %}
7434 opcode(0xDA);
7435 ins_encode( enc_cmov_d(cop,src) );
7436 ins_pipe( pipe_cmovD_reg );
7437 %}
7439 // Conditional move
7440 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7441 predicate(UseSSE==0);
7442 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7443 ins_cost(200);
7444 format %{ "FCMOV$cop $dst,$src\t# float" %}
7445 opcode(0xDA);
7446 ins_encode( enc_cmov_d(cop,src) );
7447 ins_pipe( pipe_cmovD_reg );
7448 %}
7450 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7451 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7452 predicate(UseSSE<=1);
7453 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7454 ins_cost(200);
7455 format %{ "Jn$cop skip\n\t"
7456 "MOV $dst,$src\t# double\n"
7457 "skip:" %}
7458 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7459 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7460 ins_pipe( pipe_cmovD_reg );
7461 %}
7463 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7464 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7465 predicate(UseSSE==0);
7466 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7467 ins_cost(200);
7468 format %{ "Jn$cop skip\n\t"
7469 "MOV $dst,$src\t# float\n"
7470 "skip:" %}
7471 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7472 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7473 ins_pipe( pipe_cmovD_reg );
7474 %}
7476 // No CMOVE with SSE/SSE2
7477 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7478 predicate (UseSSE>=1);
7479 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7480 ins_cost(200);
7481 format %{ "Jn$cop skip\n\t"
7482 "MOVSS $dst,$src\t# float\n"
7483 "skip:" %}
7484 ins_encode %{
7485 Label skip;
7486 // Invert sense of branch from sense of CMOV
7487 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7488 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7489 __ bind(skip);
7490 %}
7491 ins_pipe( pipe_slow );
7492 %}
7494 // No CMOVE with SSE/SSE2
7495 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7496 predicate (UseSSE>=2);
7497 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7498 ins_cost(200);
7499 format %{ "Jn$cop skip\n\t"
7500 "MOVSD $dst,$src\t# float\n"
7501 "skip:" %}
7502 ins_encode %{
7503 Label skip;
7504 // Invert sense of branch from sense of CMOV
7505 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7506 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7507 __ bind(skip);
7508 %}
7509 ins_pipe( pipe_slow );
7510 %}
7512 // unsigned version
7513 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7514 predicate (UseSSE>=1);
7515 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7516 ins_cost(200);
7517 format %{ "Jn$cop skip\n\t"
7518 "MOVSS $dst,$src\t# float\n"
7519 "skip:" %}
7520 ins_encode %{
7521 Label skip;
7522 // Invert sense of branch from sense of CMOV
7523 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7524 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7525 __ bind(skip);
7526 %}
7527 ins_pipe( pipe_slow );
7528 %}
7530 // unsigned version
7531 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7532 predicate (UseSSE>=2);
7533 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7534 ins_cost(200);
7535 format %{ "Jn$cop skip\n\t"
7536 "MOVSD $dst,$src\t# float\n"
7537 "skip:" %}
7538 ins_encode %{
7539 Label skip;
7540 // Invert sense of branch from sense of CMOV
7541 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7542 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7543 __ bind(skip);
7544 %}
7545 ins_pipe( pipe_slow );
7546 %}
7548 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7549 predicate(VM_Version::supports_cmov() );
7550 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7551 ins_cost(200);
7552 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7553 "CMOV$cop $dst.hi,$src.hi" %}
7554 opcode(0x0F,0x40);
7555 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7556 ins_pipe( pipe_cmov_reg_long );
7557 %}
7559 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7560 predicate(VM_Version::supports_cmov() );
7561 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7562 ins_cost(200);
7563 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7564 "CMOV$cop $dst.hi,$src.hi" %}
7565 opcode(0x0F,0x40);
7566 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7567 ins_pipe( pipe_cmov_reg_long );
7568 %}
7570 //----------Arithmetic Instructions--------------------------------------------
7571 //----------Addition Instructions----------------------------------------------
7572 // Integer Addition Instructions
7573 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7574 match(Set dst (AddI dst src));
7575 effect(KILL cr);
7577 size(2);
7578 format %{ "ADD $dst,$src" %}
7579 opcode(0x03);
7580 ins_encode( OpcP, RegReg( dst, src) );
7581 ins_pipe( ialu_reg_reg );
7582 %}
7584 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7585 match(Set dst (AddI dst src));
7586 effect(KILL cr);
7588 format %{ "ADD $dst,$src" %}
7589 opcode(0x81, 0x00); /* /0 id */
7590 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7591 ins_pipe( ialu_reg );
7592 %}
7594 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7595 predicate(UseIncDec);
7596 match(Set dst (AddI dst src));
7597 effect(KILL cr);
7599 size(1);
7600 format %{ "INC $dst" %}
7601 opcode(0x40); /* */
7602 ins_encode( Opc_plus( primary, dst ) );
7603 ins_pipe( ialu_reg );
7604 %}
7606 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7607 match(Set dst (AddI src0 src1));
7608 ins_cost(110);
7610 format %{ "LEA $dst,[$src0 + $src1]" %}
7611 opcode(0x8D); /* 0x8D /r */
7612 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7613 ins_pipe( ialu_reg_reg );
7614 %}
7616 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7617 match(Set dst (AddP src0 src1));
7618 ins_cost(110);
7620 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7621 opcode(0x8D); /* 0x8D /r */
7622 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7623 ins_pipe( ialu_reg_reg );
7624 %}
7626 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7627 predicate(UseIncDec);
7628 match(Set dst (AddI dst src));
7629 effect(KILL cr);
7631 size(1);
7632 format %{ "DEC $dst" %}
7633 opcode(0x48); /* */
7634 ins_encode( Opc_plus( primary, dst ) );
7635 ins_pipe( ialu_reg );
7636 %}
7638 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7639 match(Set dst (AddP dst src));
7640 effect(KILL cr);
7642 size(2);
7643 format %{ "ADD $dst,$src" %}
7644 opcode(0x03);
7645 ins_encode( OpcP, RegReg( dst, src) );
7646 ins_pipe( ialu_reg_reg );
7647 %}
7649 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7650 match(Set dst (AddP dst src));
7651 effect(KILL cr);
7653 format %{ "ADD $dst,$src" %}
7654 opcode(0x81,0x00); /* Opcode 81 /0 id */
7655 // ins_encode( RegImm( dst, src) );
7656 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7657 ins_pipe( ialu_reg );
7658 %}
7660 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7661 match(Set dst (AddI dst (LoadI src)));
7662 effect(KILL cr);
7664 ins_cost(125);
7665 format %{ "ADD $dst,$src" %}
7666 opcode(0x03);
7667 ins_encode( OpcP, RegMem( dst, src) );
7668 ins_pipe( ialu_reg_mem );
7669 %}
7671 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7672 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7673 effect(KILL cr);
7675 ins_cost(150);
7676 format %{ "ADD $dst,$src" %}
7677 opcode(0x01); /* Opcode 01 /r */
7678 ins_encode( OpcP, RegMem( src, dst ) );
7679 ins_pipe( ialu_mem_reg );
7680 %}
7682 // Add Memory with Immediate
7683 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7684 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7685 effect(KILL cr);
7687 ins_cost(125);
7688 format %{ "ADD $dst,$src" %}
7689 opcode(0x81); /* Opcode 81 /0 id */
7690 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7691 ins_pipe( ialu_mem_imm );
7692 %}
7694 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7695 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7696 effect(KILL cr);
7698 ins_cost(125);
7699 format %{ "INC $dst" %}
7700 opcode(0xFF); /* Opcode FF /0 */
7701 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7702 ins_pipe( ialu_mem_imm );
7703 %}
7705 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7706 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7707 effect(KILL cr);
7709 ins_cost(125);
7710 format %{ "DEC $dst" %}
7711 opcode(0xFF); /* Opcode FF /1 */
7712 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7713 ins_pipe( ialu_mem_imm );
7714 %}
7717 instruct checkCastPP( eRegP dst ) %{
7718 match(Set dst (CheckCastPP dst));
7720 size(0);
7721 format %{ "#checkcastPP of $dst" %}
7722 ins_encode( /*empty encoding*/ );
7723 ins_pipe( empty );
7724 %}
7726 instruct castPP( eRegP dst ) %{
7727 match(Set dst (CastPP dst));
7728 format %{ "#castPP of $dst" %}
7729 ins_encode( /*empty encoding*/ );
7730 ins_pipe( empty );
7731 %}
7733 instruct castII( eRegI dst ) %{
7734 match(Set dst (CastII dst));
7735 format %{ "#castII of $dst" %}
7736 ins_encode( /*empty encoding*/ );
7737 ins_cost(0);
7738 ins_pipe( empty );
7739 %}
7742 // Load-locked - same as a regular pointer load when used with compare-swap
7743 instruct loadPLocked(eRegP dst, memory mem) %{
7744 match(Set dst (LoadPLocked mem));
7746 ins_cost(125);
7747 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7748 opcode(0x8B);
7749 ins_encode( OpcP, RegMem(dst,mem));
7750 ins_pipe( ialu_reg_mem );
7751 %}
7753 // LoadLong-locked - same as a volatile long load when used with compare-swap
7754 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
7755 predicate(UseSSE<=1);
7756 match(Set dst (LoadLLocked mem));
7758 ins_cost(200);
7759 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7760 "FISTp $dst" %}
7761 ins_encode(enc_loadL_volatile(mem,dst));
7762 ins_pipe( fpu_reg_mem );
7763 %}
7765 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
7766 predicate(UseSSE>=2);
7767 match(Set dst (LoadLLocked mem));
7768 effect(TEMP tmp);
7769 ins_cost(180);
7770 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7771 "MOVSD $dst,$tmp" %}
7772 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
7773 ins_pipe( pipe_slow );
7774 %}
7776 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
7777 predicate(UseSSE>=2);
7778 match(Set dst (LoadLLocked mem));
7779 effect(TEMP tmp);
7780 ins_cost(160);
7781 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7782 "MOVD $dst.lo,$tmp\n\t"
7783 "PSRLQ $tmp,32\n\t"
7784 "MOVD $dst.hi,$tmp" %}
7785 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
7786 ins_pipe( pipe_slow );
7787 %}
7789 // Conditional-store of the updated heap-top.
7790 // Used during allocation of the shared heap.
7791 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7792 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7793 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7794 // EAX is killed if there is contention, but then it's also unused.
7795 // In the common case of no contention, EAX holds the new oop address.
7796 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7797 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7798 ins_pipe( pipe_cmpxchg );
7799 %}
7801 // Conditional-store of a long value
7802 // Returns a boolean value (0/1) on success. Implemented with a CMPXCHG8 on Intel.
7803 // mem_ptr can actually be in either ESI or EDI
7804 instruct storeLConditional( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7805 match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
7806 effect(KILL cr);
7807 // EDX:EAX is killed if there is contention, but then it's also unused.
7808 // In the common case of no contention, EDX:EAX holds the new oop address.
7809 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7810 "MOV $res,0\n\t"
7811 "JNE,s fail\n\t"
7812 "MOV $res,1\n"
7813 "fail:" %}
7814 ins_encode( enc_cmpxchg8(mem_ptr),
7815 enc_flags_ne_to_boolean(res) );
7816 ins_pipe( pipe_cmpxchg );
7817 %}
7819 // Conditional-store of a long value
7820 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7821 // mem_ptr can actually be in either ESI or EDI
7822 instruct storeLConditional_flags( eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr, immI0 zero ) %{
7823 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
7824 // EDX:EAX is killed if there is contention, but then it's also unused.
7825 // In the common case of no contention, EDX:EAX holds the new oop address.
7826 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" %}
7827 ins_encode( enc_cmpxchg8(mem_ptr) );
7828 ins_pipe( pipe_cmpxchg );
7829 %}
7831 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7833 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7834 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7835 effect(KILL cr, KILL oldval);
7836 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7837 "MOV $res,0\n\t"
7838 "JNE,s fail\n\t"
7839 "MOV $res,1\n"
7840 "fail:" %}
7841 ins_encode( enc_cmpxchg8(mem_ptr),
7842 enc_flags_ne_to_boolean(res) );
7843 ins_pipe( pipe_cmpxchg );
7844 %}
7846 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7847 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7848 effect(KILL cr, KILL oldval);
7849 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7850 "MOV $res,0\n\t"
7851 "JNE,s fail\n\t"
7852 "MOV $res,1\n"
7853 "fail:" %}
7854 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7855 ins_pipe( pipe_cmpxchg );
7856 %}
7858 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7859 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7860 effect(KILL cr, KILL oldval);
7861 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7862 "MOV $res,0\n\t"
7863 "JNE,s fail\n\t"
7864 "MOV $res,1\n"
7865 "fail:" %}
7866 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7867 ins_pipe( pipe_cmpxchg );
7868 %}
7870 //----------Subtraction Instructions-------------------------------------------
7871 // Integer Subtraction Instructions
7872 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7873 match(Set dst (SubI dst src));
7874 effect(KILL cr);
7876 size(2);
7877 format %{ "SUB $dst,$src" %}
7878 opcode(0x2B);
7879 ins_encode( OpcP, RegReg( dst, src) );
7880 ins_pipe( ialu_reg_reg );
7881 %}
7883 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7884 match(Set dst (SubI dst src));
7885 effect(KILL cr);
7887 format %{ "SUB $dst,$src" %}
7888 opcode(0x81,0x05); /* Opcode 81 /5 */
7889 // ins_encode( RegImm( dst, src) );
7890 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7891 ins_pipe( ialu_reg );
7892 %}
7894 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7895 match(Set dst (SubI dst (LoadI src)));
7896 effect(KILL cr);
7898 ins_cost(125);
7899 format %{ "SUB $dst,$src" %}
7900 opcode(0x2B);
7901 ins_encode( OpcP, RegMem( dst, src) );
7902 ins_pipe( ialu_reg_mem );
7903 %}
7905 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7906 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7907 effect(KILL cr);
7909 ins_cost(150);
7910 format %{ "SUB $dst,$src" %}
7911 opcode(0x29); /* Opcode 29 /r */
7912 ins_encode( OpcP, RegMem( src, dst ) );
7913 ins_pipe( ialu_mem_reg );
7914 %}
7916 // Subtract from a pointer
7917 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
7918 match(Set dst (AddP dst (SubI zero src)));
7919 effect(KILL cr);
7921 size(2);
7922 format %{ "SUB $dst,$src" %}
7923 opcode(0x2B);
7924 ins_encode( OpcP, RegReg( dst, src) );
7925 ins_pipe( ialu_reg_reg );
7926 %}
7928 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
7929 match(Set dst (SubI zero dst));
7930 effect(KILL cr);
7932 size(2);
7933 format %{ "NEG $dst" %}
7934 opcode(0xF7,0x03); // Opcode F7 /3
7935 ins_encode( OpcP, RegOpc( dst ) );
7936 ins_pipe( ialu_reg );
7937 %}
7940 //----------Multiplication/Division Instructions-------------------------------
7941 // Integer Multiplication Instructions
7942 // Multiply Register
7943 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7944 match(Set dst (MulI dst src));
7945 effect(KILL cr);
7947 size(3);
7948 ins_cost(300);
7949 format %{ "IMUL $dst,$src" %}
7950 opcode(0xAF, 0x0F);
7951 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7952 ins_pipe( ialu_reg_reg_alu0 );
7953 %}
7955 // Multiply 32-bit Immediate
7956 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
7957 match(Set dst (MulI src imm));
7958 effect(KILL cr);
7960 ins_cost(300);
7961 format %{ "IMUL $dst,$src,$imm" %}
7962 opcode(0x69); /* 69 /r id */
7963 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7964 ins_pipe( ialu_reg_reg_alu0 );
7965 %}
7967 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7968 match(Set dst src);
7969 effect(KILL cr);
7971 // Note that this is artificially increased to make it more expensive than loadConL
7972 ins_cost(250);
7973 format %{ "MOV EAX,$src\t// low word only" %}
7974 opcode(0xB8);
7975 ins_encode( LdImmL_Lo(dst, src) );
7976 ins_pipe( ialu_reg_fat );
7977 %}
7979 // Multiply by 32-bit Immediate, taking the shifted high order results
7980 // (special case for shift by 32)
7981 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7982 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7983 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7984 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7985 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7986 effect(USE src1, KILL cr);
7988 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7989 ins_cost(0*100 + 1*400 - 150);
7990 format %{ "IMUL EDX:EAX,$src1" %}
7991 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7992 ins_pipe( pipe_slow );
7993 %}
7995 // Multiply by 32-bit Immediate, taking the shifted high order results
7996 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7997 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7998 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7999 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8000 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8001 effect(USE src1, KILL cr);
8003 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8004 ins_cost(1*100 + 1*400 - 150);
8005 format %{ "IMUL EDX:EAX,$src1\n\t"
8006 "SAR EDX,$cnt-32" %}
8007 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8008 ins_pipe( pipe_slow );
8009 %}
8011 // Multiply Memory 32-bit Immediate
8012 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8013 match(Set dst (MulI (LoadI src) imm));
8014 effect(KILL cr);
8016 ins_cost(300);
8017 format %{ "IMUL $dst,$src,$imm" %}
8018 opcode(0x69); /* 69 /r id */
8019 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8020 ins_pipe( ialu_reg_mem_alu0 );
8021 %}
8023 // Multiply Memory
8024 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8025 match(Set dst (MulI dst (LoadI src)));
8026 effect(KILL cr);
8028 ins_cost(350);
8029 format %{ "IMUL $dst,$src" %}
8030 opcode(0xAF, 0x0F);
8031 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8032 ins_pipe( ialu_reg_mem_alu0 );
8033 %}
8035 // Multiply Register Int to Long
8036 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8037 // Basic Idea: long = (long)int * (long)int
8038 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8039 effect(DEF dst, USE src, USE src1, KILL flags);
8041 ins_cost(300);
8042 format %{ "IMUL $dst,$src1" %}
8044 ins_encode( long_int_multiply( dst, src1 ) );
8045 ins_pipe( ialu_reg_reg_alu0 );
8046 %}
8048 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8049 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8050 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8051 effect(KILL flags);
8053 ins_cost(300);
8054 format %{ "MUL $dst,$src1" %}
8056 ins_encode( long_uint_multiply(dst, src1) );
8057 ins_pipe( ialu_reg_reg_alu0 );
8058 %}
8060 // Multiply Register Long
8061 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8062 match(Set dst (MulL dst src));
8063 effect(KILL cr, TEMP tmp);
8064 ins_cost(4*100+3*400);
8065 // Basic idea: lo(result) = lo(x_lo * y_lo)
8066 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8067 format %{ "MOV $tmp,$src.lo\n\t"
8068 "IMUL $tmp,EDX\n\t"
8069 "MOV EDX,$src.hi\n\t"
8070 "IMUL EDX,EAX\n\t"
8071 "ADD $tmp,EDX\n\t"
8072 "MUL EDX:EAX,$src.lo\n\t"
8073 "ADD EDX,$tmp" %}
8074 ins_encode( long_multiply( dst, src, tmp ) );
8075 ins_pipe( pipe_slow );
8076 %}
8078 // Multiply Register Long by small constant
8079 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8080 match(Set dst (MulL dst src));
8081 effect(KILL cr, TEMP tmp);
8082 ins_cost(2*100+2*400);
8083 size(12);
8084 // Basic idea: lo(result) = lo(src * EAX)
8085 // hi(result) = hi(src * EAX) + lo(src * EDX)
8086 format %{ "IMUL $tmp,EDX,$src\n\t"
8087 "MOV EDX,$src\n\t"
8088 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8089 "ADD EDX,$tmp" %}
8090 ins_encode( long_multiply_con( dst, src, tmp ) );
8091 ins_pipe( pipe_slow );
8092 %}
8094 // Integer DIV with Register
8095 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8096 match(Set rax (DivI rax div));
8097 effect(KILL rdx, KILL cr);
8098 size(26);
8099 ins_cost(30*100+10*100);
8100 format %{ "CMP EAX,0x80000000\n\t"
8101 "JNE,s normal\n\t"
8102 "XOR EDX,EDX\n\t"
8103 "CMP ECX,-1\n\t"
8104 "JE,s done\n"
8105 "normal: CDQ\n\t"
8106 "IDIV $div\n\t"
8107 "done:" %}
8108 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8109 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8110 ins_pipe( ialu_reg_reg_alu0 );
8111 %}
8113 // Divide Register Long
8114 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8115 match(Set dst (DivL src1 src2));
8116 effect( KILL cr, KILL cx, KILL bx );
8117 ins_cost(10000);
8118 format %{ "PUSH $src1.hi\n\t"
8119 "PUSH $src1.lo\n\t"
8120 "PUSH $src2.hi\n\t"
8121 "PUSH $src2.lo\n\t"
8122 "CALL SharedRuntime::ldiv\n\t"
8123 "ADD ESP,16" %}
8124 ins_encode( long_div(src1,src2) );
8125 ins_pipe( pipe_slow );
8126 %}
8128 // Integer DIVMOD with Register, both quotient and mod results
8129 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8130 match(DivModI rax div);
8131 effect(KILL cr);
8132 size(26);
8133 ins_cost(30*100+10*100);
8134 format %{ "CMP EAX,0x80000000\n\t"
8135 "JNE,s normal\n\t"
8136 "XOR EDX,EDX\n\t"
8137 "CMP ECX,-1\n\t"
8138 "JE,s done\n"
8139 "normal: CDQ\n\t"
8140 "IDIV $div\n\t"
8141 "done:" %}
8142 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8143 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8144 ins_pipe( pipe_slow );
8145 %}
8147 // Integer MOD with Register
8148 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8149 match(Set rdx (ModI rax div));
8150 effect(KILL rax, KILL cr);
8152 size(26);
8153 ins_cost(300);
8154 format %{ "CDQ\n\t"
8155 "IDIV $div" %}
8156 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8157 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8158 ins_pipe( ialu_reg_reg_alu0 );
8159 %}
8161 // Remainder Register Long
8162 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8163 match(Set dst (ModL src1 src2));
8164 effect( KILL cr, KILL cx, KILL bx );
8165 ins_cost(10000);
8166 format %{ "PUSH $src1.hi\n\t"
8167 "PUSH $src1.lo\n\t"
8168 "PUSH $src2.hi\n\t"
8169 "PUSH $src2.lo\n\t"
8170 "CALL SharedRuntime::lrem\n\t"
8171 "ADD ESP,16" %}
8172 ins_encode( long_mod(src1,src2) );
8173 ins_pipe( pipe_slow );
8174 %}
8176 // Integer Shift Instructions
8177 // Shift Left by one
8178 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8179 match(Set dst (LShiftI dst shift));
8180 effect(KILL cr);
8182 size(2);
8183 format %{ "SHL $dst,$shift" %}
8184 opcode(0xD1, 0x4); /* D1 /4 */
8185 ins_encode( OpcP, RegOpc( dst ) );
8186 ins_pipe( ialu_reg );
8187 %}
8189 // Shift Left by 8-bit immediate
8190 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8191 match(Set dst (LShiftI dst shift));
8192 effect(KILL cr);
8194 size(3);
8195 format %{ "SHL $dst,$shift" %}
8196 opcode(0xC1, 0x4); /* C1 /4 ib */
8197 ins_encode( RegOpcImm( dst, shift) );
8198 ins_pipe( ialu_reg );
8199 %}
8201 // Shift Left by variable
8202 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8203 match(Set dst (LShiftI dst shift));
8204 effect(KILL cr);
8206 size(2);
8207 format %{ "SHL $dst,$shift" %}
8208 opcode(0xD3, 0x4); /* D3 /4 */
8209 ins_encode( OpcP, RegOpc( dst ) );
8210 ins_pipe( ialu_reg_reg );
8211 %}
8213 // Arithmetic shift right by one
8214 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8215 match(Set dst (RShiftI dst shift));
8216 effect(KILL cr);
8218 size(2);
8219 format %{ "SAR $dst,$shift" %}
8220 opcode(0xD1, 0x7); /* D1 /7 */
8221 ins_encode( OpcP, RegOpc( dst ) );
8222 ins_pipe( ialu_reg );
8223 %}
8225 // Arithmetic shift right by one
8226 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8227 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8228 effect(KILL cr);
8229 format %{ "SAR $dst,$shift" %}
8230 opcode(0xD1, 0x7); /* D1 /7 */
8231 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8232 ins_pipe( ialu_mem_imm );
8233 %}
8235 // Arithmetic Shift Right by 8-bit immediate
8236 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8237 match(Set dst (RShiftI dst shift));
8238 effect(KILL cr);
8240 size(3);
8241 format %{ "SAR $dst,$shift" %}
8242 opcode(0xC1, 0x7); /* C1 /7 ib */
8243 ins_encode( RegOpcImm( dst, shift ) );
8244 ins_pipe( ialu_mem_imm );
8245 %}
8247 // Arithmetic Shift Right by 8-bit immediate
8248 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8249 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8250 effect(KILL cr);
8252 format %{ "SAR $dst,$shift" %}
8253 opcode(0xC1, 0x7); /* C1 /7 ib */
8254 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8255 ins_pipe( ialu_mem_imm );
8256 %}
8258 // Arithmetic Shift Right by variable
8259 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8260 match(Set dst (RShiftI dst shift));
8261 effect(KILL cr);
8263 size(2);
8264 format %{ "SAR $dst,$shift" %}
8265 opcode(0xD3, 0x7); /* D3 /7 */
8266 ins_encode( OpcP, RegOpc( dst ) );
8267 ins_pipe( ialu_reg_reg );
8268 %}
8270 // Logical shift right by one
8271 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8272 match(Set dst (URShiftI dst shift));
8273 effect(KILL cr);
8275 size(2);
8276 format %{ "SHR $dst,$shift" %}
8277 opcode(0xD1, 0x5); /* D1 /5 */
8278 ins_encode( OpcP, RegOpc( dst ) );
8279 ins_pipe( ialu_reg );
8280 %}
8282 // Logical Shift Right by 8-bit immediate
8283 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8284 match(Set dst (URShiftI dst shift));
8285 effect(KILL cr);
8287 size(3);
8288 format %{ "SHR $dst,$shift" %}
8289 opcode(0xC1, 0x5); /* C1 /5 ib */
8290 ins_encode( RegOpcImm( dst, shift) );
8291 ins_pipe( ialu_reg );
8292 %}
8294 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8295 // This idiom is used by the compiler for the i2b bytecode.
8296 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
8297 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8298 effect(KILL cr);
8300 size(3);
8301 format %{ "MOVSX $dst,$src :8" %}
8302 opcode(0xBE, 0x0F);
8303 ins_encode( OpcS, OpcP, RegReg( dst, src));
8304 ins_pipe( ialu_reg_reg );
8305 %}
8307 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8308 // This idiom is used by the compiler the i2s bytecode.
8309 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
8310 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8311 effect(KILL cr);
8313 size(3);
8314 format %{ "MOVSX $dst,$src :16" %}
8315 opcode(0xBF, 0x0F);
8316 ins_encode( OpcS, OpcP, RegReg( dst, src));
8317 ins_pipe( ialu_reg_reg );
8318 %}
8321 // Logical Shift Right by variable
8322 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8323 match(Set dst (URShiftI dst shift));
8324 effect(KILL cr);
8326 size(2);
8327 format %{ "SHR $dst,$shift" %}
8328 opcode(0xD3, 0x5); /* D3 /5 */
8329 ins_encode( OpcP, RegOpc( dst ) );
8330 ins_pipe( ialu_reg_reg );
8331 %}
8334 //----------Logical Instructions-----------------------------------------------
8335 //----------Integer Logical Instructions---------------------------------------
8336 // And Instructions
8337 // And Register with Register
8338 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8339 match(Set dst (AndI dst src));
8340 effect(KILL cr);
8342 size(2);
8343 format %{ "AND $dst,$src" %}
8344 opcode(0x23);
8345 ins_encode( OpcP, RegReg( dst, src) );
8346 ins_pipe( ialu_reg_reg );
8347 %}
8349 // And Register with Immediate
8350 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8351 match(Set dst (AndI dst src));
8352 effect(KILL cr);
8354 format %{ "AND $dst,$src" %}
8355 opcode(0x81,0x04); /* Opcode 81 /4 */
8356 // ins_encode( RegImm( dst, src) );
8357 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8358 ins_pipe( ialu_reg );
8359 %}
8361 // And Register with Memory
8362 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8363 match(Set dst (AndI dst (LoadI src)));
8364 effect(KILL cr);
8366 ins_cost(125);
8367 format %{ "AND $dst,$src" %}
8368 opcode(0x23);
8369 ins_encode( OpcP, RegMem( dst, src) );
8370 ins_pipe( ialu_reg_mem );
8371 %}
8373 // And Memory with Register
8374 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8375 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8376 effect(KILL cr);
8378 ins_cost(150);
8379 format %{ "AND $dst,$src" %}
8380 opcode(0x21); /* Opcode 21 /r */
8381 ins_encode( OpcP, RegMem( src, dst ) );
8382 ins_pipe( ialu_mem_reg );
8383 %}
8385 // And Memory with Immediate
8386 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8387 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8388 effect(KILL cr);
8390 ins_cost(125);
8391 format %{ "AND $dst,$src" %}
8392 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8393 // ins_encode( MemImm( dst, src) );
8394 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8395 ins_pipe( ialu_mem_imm );
8396 %}
8398 // Or Instructions
8399 // Or Register with Register
8400 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8401 match(Set dst (OrI dst src));
8402 effect(KILL cr);
8404 size(2);
8405 format %{ "OR $dst,$src" %}
8406 opcode(0x0B);
8407 ins_encode( OpcP, RegReg( dst, src) );
8408 ins_pipe( ialu_reg_reg );
8409 %}
8411 // Or Register with Immediate
8412 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8413 match(Set dst (OrI dst src));
8414 effect(KILL cr);
8416 format %{ "OR $dst,$src" %}
8417 opcode(0x81,0x01); /* Opcode 81 /1 id */
8418 // ins_encode( RegImm( dst, src) );
8419 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8420 ins_pipe( ialu_reg );
8421 %}
8423 // Or Register with Memory
8424 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8425 match(Set dst (OrI dst (LoadI src)));
8426 effect(KILL cr);
8428 ins_cost(125);
8429 format %{ "OR $dst,$src" %}
8430 opcode(0x0B);
8431 ins_encode( OpcP, RegMem( dst, src) );
8432 ins_pipe( ialu_reg_mem );
8433 %}
8435 // Or Memory with Register
8436 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8437 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8438 effect(KILL cr);
8440 ins_cost(150);
8441 format %{ "OR $dst,$src" %}
8442 opcode(0x09); /* Opcode 09 /r */
8443 ins_encode( OpcP, RegMem( src, dst ) );
8444 ins_pipe( ialu_mem_reg );
8445 %}
8447 // Or Memory with Immediate
8448 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8449 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8450 effect(KILL cr);
8452 ins_cost(125);
8453 format %{ "OR $dst,$src" %}
8454 opcode(0x81,0x1); /* Opcode 81 /1 id */
8455 // ins_encode( MemImm( dst, src) );
8456 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8457 ins_pipe( ialu_mem_imm );
8458 %}
8460 // ROL/ROR
8461 // ROL expand
8462 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8463 effect(USE_DEF dst, USE shift, KILL cr);
8465 format %{ "ROL $dst, $shift" %}
8466 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8467 ins_encode( OpcP, RegOpc( dst ));
8468 ins_pipe( ialu_reg );
8469 %}
8471 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8472 effect(USE_DEF dst, USE shift, KILL cr);
8474 format %{ "ROL $dst, $shift" %}
8475 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8476 ins_encode( RegOpcImm(dst, shift) );
8477 ins_pipe(ialu_reg);
8478 %}
8480 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8481 effect(USE_DEF dst, USE shift, KILL cr);
8483 format %{ "ROL $dst, $shift" %}
8484 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8485 ins_encode(OpcP, RegOpc(dst));
8486 ins_pipe( ialu_reg_reg );
8487 %}
8488 // end of ROL expand
8490 // ROL 32bit by one once
8491 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8492 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8494 expand %{
8495 rolI_eReg_imm1(dst, lshift, cr);
8496 %}
8497 %}
8499 // ROL 32bit var by imm8 once
8500 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8501 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8502 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8504 expand %{
8505 rolI_eReg_imm8(dst, lshift, cr);
8506 %}
8507 %}
8509 // ROL 32bit var by var once
8510 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8511 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8513 expand %{
8514 rolI_eReg_CL(dst, shift, cr);
8515 %}
8516 %}
8518 // ROL 32bit var by var once
8519 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8520 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8522 expand %{
8523 rolI_eReg_CL(dst, shift, cr);
8524 %}
8525 %}
8527 // ROR expand
8528 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8529 effect(USE_DEF dst, USE shift, KILL cr);
8531 format %{ "ROR $dst, $shift" %}
8532 opcode(0xD1,0x1); /* Opcode D1 /1 */
8533 ins_encode( OpcP, RegOpc( dst ) );
8534 ins_pipe( ialu_reg );
8535 %}
8537 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8538 effect (USE_DEF dst, USE shift, KILL cr);
8540 format %{ "ROR $dst, $shift" %}
8541 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8542 ins_encode( RegOpcImm(dst, shift) );
8543 ins_pipe( ialu_reg );
8544 %}
8546 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8547 effect(USE_DEF dst, USE shift, KILL cr);
8549 format %{ "ROR $dst, $shift" %}
8550 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8551 ins_encode(OpcP, RegOpc(dst));
8552 ins_pipe( ialu_reg_reg );
8553 %}
8554 // end of ROR expand
8556 // ROR right once
8557 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8558 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8560 expand %{
8561 rorI_eReg_imm1(dst, rshift, cr);
8562 %}
8563 %}
8565 // ROR 32bit by immI8 once
8566 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8567 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8568 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8570 expand %{
8571 rorI_eReg_imm8(dst, rshift, cr);
8572 %}
8573 %}
8575 // ROR 32bit var by var once
8576 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8577 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8579 expand %{
8580 rorI_eReg_CL(dst, shift, cr);
8581 %}
8582 %}
8584 // ROR 32bit var by var once
8585 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8586 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8588 expand %{
8589 rorI_eReg_CL(dst, shift, cr);
8590 %}
8591 %}
8593 // Xor Instructions
8594 // Xor Register with Register
8595 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8596 match(Set dst (XorI dst src));
8597 effect(KILL cr);
8599 size(2);
8600 format %{ "XOR $dst,$src" %}
8601 opcode(0x33);
8602 ins_encode( OpcP, RegReg( dst, src) );
8603 ins_pipe( ialu_reg_reg );
8604 %}
8606 // Xor Register with Immediate
8607 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8608 match(Set dst (XorI dst src));
8609 effect(KILL cr);
8611 format %{ "XOR $dst,$src" %}
8612 opcode(0x81,0x06); /* Opcode 81 /6 id */
8613 // ins_encode( RegImm( dst, src) );
8614 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8615 ins_pipe( ialu_reg );
8616 %}
8618 // Xor Register with Memory
8619 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8620 match(Set dst (XorI dst (LoadI src)));
8621 effect(KILL cr);
8623 ins_cost(125);
8624 format %{ "XOR $dst,$src" %}
8625 opcode(0x33);
8626 ins_encode( OpcP, RegMem(dst, src) );
8627 ins_pipe( ialu_reg_mem );
8628 %}
8630 // Xor Memory with Register
8631 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8632 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8633 effect(KILL cr);
8635 ins_cost(150);
8636 format %{ "XOR $dst,$src" %}
8637 opcode(0x31); /* Opcode 31 /r */
8638 ins_encode( OpcP, RegMem( src, dst ) );
8639 ins_pipe( ialu_mem_reg );
8640 %}
8642 // Xor Memory with Immediate
8643 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8644 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8645 effect(KILL cr);
8647 ins_cost(125);
8648 format %{ "XOR $dst,$src" %}
8649 opcode(0x81,0x6); /* Opcode 81 /6 id */
8650 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8651 ins_pipe( ialu_mem_imm );
8652 %}
8654 //----------Convert Int to Boolean---------------------------------------------
8656 instruct movI_nocopy(eRegI dst, eRegI src) %{
8657 effect( DEF dst, USE src );
8658 format %{ "MOV $dst,$src" %}
8659 ins_encode( enc_Copy( dst, src) );
8660 ins_pipe( ialu_reg_reg );
8661 %}
8663 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
8664 effect( USE_DEF dst, USE src, KILL cr );
8666 size(4);
8667 format %{ "NEG $dst\n\t"
8668 "ADC $dst,$src" %}
8669 ins_encode( neg_reg(dst),
8670 OpcRegReg(0x13,dst,src) );
8671 ins_pipe( ialu_reg_reg_long );
8672 %}
8674 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
8675 match(Set dst (Conv2B src));
8677 expand %{
8678 movI_nocopy(dst,src);
8679 ci2b(dst,src,cr);
8680 %}
8681 %}
8683 instruct movP_nocopy(eRegI dst, eRegP src) %{
8684 effect( DEF dst, USE src );
8685 format %{ "MOV $dst,$src" %}
8686 ins_encode( enc_Copy( dst, src) );
8687 ins_pipe( ialu_reg_reg );
8688 %}
8690 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
8691 effect( USE_DEF dst, USE src, KILL cr );
8692 format %{ "NEG $dst\n\t"
8693 "ADC $dst,$src" %}
8694 ins_encode( neg_reg(dst),
8695 OpcRegReg(0x13,dst,src) );
8696 ins_pipe( ialu_reg_reg_long );
8697 %}
8699 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
8700 match(Set dst (Conv2B src));
8702 expand %{
8703 movP_nocopy(dst,src);
8704 cp2b(dst,src,cr);
8705 %}
8706 %}
8708 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8709 match(Set dst (CmpLTMask p q));
8710 effect( KILL cr );
8711 ins_cost(400);
8713 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8714 format %{ "XOR $dst,$dst\n\t"
8715 "CMP $p,$q\n\t"
8716 "SETlt $dst\n\t"
8717 "NEG $dst" %}
8718 ins_encode( OpcRegReg(0x33,dst,dst),
8719 OpcRegReg(0x3B,p,q),
8720 setLT_reg(dst), neg_reg(dst) );
8721 ins_pipe( pipe_slow );
8722 %}
8724 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
8725 match(Set dst (CmpLTMask dst zero));
8726 effect( DEF dst, KILL cr );
8727 ins_cost(100);
8729 format %{ "SAR $dst,31" %}
8730 opcode(0xC1, 0x7); /* C1 /7 ib */
8731 ins_encode( RegOpcImm( dst, 0x1F ) );
8732 ins_pipe( ialu_reg );
8733 %}
8736 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8737 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8738 effect( KILL tmp, KILL cr );
8739 ins_cost(400);
8740 // annoyingly, $tmp has no edges so you cant ask for it in
8741 // any format or encoding
8742 format %{ "SUB $p,$q\n\t"
8743 "SBB ECX,ECX\n\t"
8744 "AND ECX,$y\n\t"
8745 "ADD $p,ECX" %}
8746 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8747 ins_pipe( pipe_cmplt );
8748 %}
8750 /* If I enable this, I encourage spilling in the inner loop of compress.
8751 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8752 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8753 effect( USE_KILL tmp, KILL cr );
8754 ins_cost(400);
8756 format %{ "SUB $p,$q\n\t"
8757 "SBB ECX,ECX\n\t"
8758 "AND ECX,$y\n\t"
8759 "ADD $p,ECX" %}
8760 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8761 %}
8762 */
8764 //----------Long Instructions------------------------------------------------
8765 // Add Long Register with Register
8766 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8767 match(Set dst (AddL dst src));
8768 effect(KILL cr);
8769 ins_cost(200);
8770 format %{ "ADD $dst.lo,$src.lo\n\t"
8771 "ADC $dst.hi,$src.hi" %}
8772 opcode(0x03, 0x13);
8773 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8774 ins_pipe( ialu_reg_reg_long );
8775 %}
8777 // Add Long Register with Immediate
8778 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8779 match(Set dst (AddL dst src));
8780 effect(KILL cr);
8781 format %{ "ADD $dst.lo,$src.lo\n\t"
8782 "ADC $dst.hi,$src.hi" %}
8783 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8784 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8785 ins_pipe( ialu_reg_long );
8786 %}
8788 // Add Long Register with Memory
8789 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8790 match(Set dst (AddL dst (LoadL mem)));
8791 effect(KILL cr);
8792 ins_cost(125);
8793 format %{ "ADD $dst.lo,$mem\n\t"
8794 "ADC $dst.hi,$mem+4" %}
8795 opcode(0x03, 0x13);
8796 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8797 ins_pipe( ialu_reg_long_mem );
8798 %}
8800 // Subtract Long Register with Register.
8801 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8802 match(Set dst (SubL dst src));
8803 effect(KILL cr);
8804 ins_cost(200);
8805 format %{ "SUB $dst.lo,$src.lo\n\t"
8806 "SBB $dst.hi,$src.hi" %}
8807 opcode(0x2B, 0x1B);
8808 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8809 ins_pipe( ialu_reg_reg_long );
8810 %}
8812 // Subtract Long Register with Immediate
8813 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8814 match(Set dst (SubL dst src));
8815 effect(KILL cr);
8816 format %{ "SUB $dst.lo,$src.lo\n\t"
8817 "SBB $dst.hi,$src.hi" %}
8818 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8819 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8820 ins_pipe( ialu_reg_long );
8821 %}
8823 // Subtract Long Register with Memory
8824 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8825 match(Set dst (SubL dst (LoadL mem)));
8826 effect(KILL cr);
8827 ins_cost(125);
8828 format %{ "SUB $dst.lo,$mem\n\t"
8829 "SBB $dst.hi,$mem+4" %}
8830 opcode(0x2B, 0x1B);
8831 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8832 ins_pipe( ialu_reg_long_mem );
8833 %}
8835 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8836 match(Set dst (SubL zero dst));
8837 effect(KILL cr);
8838 ins_cost(300);
8839 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8840 ins_encode( neg_long(dst) );
8841 ins_pipe( ialu_reg_reg_long );
8842 %}
8844 // And Long Register with Register
8845 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8846 match(Set dst (AndL dst src));
8847 effect(KILL cr);
8848 format %{ "AND $dst.lo,$src.lo\n\t"
8849 "AND $dst.hi,$src.hi" %}
8850 opcode(0x23,0x23);
8851 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8852 ins_pipe( ialu_reg_reg_long );
8853 %}
8855 // And Long Register with Immediate
8856 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8857 match(Set dst (AndL dst src));
8858 effect(KILL cr);
8859 format %{ "AND $dst.lo,$src.lo\n\t"
8860 "AND $dst.hi,$src.hi" %}
8861 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8862 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8863 ins_pipe( ialu_reg_long );
8864 %}
8866 // And Long Register with Memory
8867 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8868 match(Set dst (AndL dst (LoadL mem)));
8869 effect(KILL cr);
8870 ins_cost(125);
8871 format %{ "AND $dst.lo,$mem\n\t"
8872 "AND $dst.hi,$mem+4" %}
8873 opcode(0x23, 0x23);
8874 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8875 ins_pipe( ialu_reg_long_mem );
8876 %}
8878 // Or Long Register with Register
8879 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8880 match(Set dst (OrL dst src));
8881 effect(KILL cr);
8882 format %{ "OR $dst.lo,$src.lo\n\t"
8883 "OR $dst.hi,$src.hi" %}
8884 opcode(0x0B,0x0B);
8885 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8886 ins_pipe( ialu_reg_reg_long );
8887 %}
8889 // Or Long Register with Immediate
8890 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8891 match(Set dst (OrL dst src));
8892 effect(KILL cr);
8893 format %{ "OR $dst.lo,$src.lo\n\t"
8894 "OR $dst.hi,$src.hi" %}
8895 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
8896 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8897 ins_pipe( ialu_reg_long );
8898 %}
8900 // Or Long Register with Memory
8901 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8902 match(Set dst (OrL dst (LoadL mem)));
8903 effect(KILL cr);
8904 ins_cost(125);
8905 format %{ "OR $dst.lo,$mem\n\t"
8906 "OR $dst.hi,$mem+4" %}
8907 opcode(0x0B,0x0B);
8908 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8909 ins_pipe( ialu_reg_long_mem );
8910 %}
8912 // Xor Long Register with Register
8913 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8914 match(Set dst (XorL dst src));
8915 effect(KILL cr);
8916 format %{ "XOR $dst.lo,$src.lo\n\t"
8917 "XOR $dst.hi,$src.hi" %}
8918 opcode(0x33,0x33);
8919 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8920 ins_pipe( ialu_reg_reg_long );
8921 %}
8923 // Xor Long Register with Immediate
8924 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8925 match(Set dst (XorL dst src));
8926 effect(KILL cr);
8927 format %{ "XOR $dst.lo,$src.lo\n\t"
8928 "XOR $dst.hi,$src.hi" %}
8929 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
8930 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8931 ins_pipe( ialu_reg_long );
8932 %}
8934 // Xor Long Register with Memory
8935 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8936 match(Set dst (XorL dst (LoadL mem)));
8937 effect(KILL cr);
8938 ins_cost(125);
8939 format %{ "XOR $dst.lo,$mem\n\t"
8940 "XOR $dst.hi,$mem+4" %}
8941 opcode(0x33,0x33);
8942 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8943 ins_pipe( ialu_reg_long_mem );
8944 %}
8946 // Shift Left Long by 1-31
8947 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
8948 match(Set dst (LShiftL dst cnt));
8949 effect(KILL cr);
8950 ins_cost(200);
8951 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
8952 "SHL $dst.lo,$cnt" %}
8953 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
8954 ins_encode( move_long_small_shift(dst,cnt) );
8955 ins_pipe( ialu_reg_long );
8956 %}
8958 // Shift Left Long by 32-63
8959 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
8960 match(Set dst (LShiftL dst cnt));
8961 effect(KILL cr);
8962 ins_cost(300);
8963 format %{ "MOV $dst.hi,$dst.lo\n"
8964 "\tSHL $dst.hi,$cnt-32\n"
8965 "\tXOR $dst.lo,$dst.lo" %}
8966 opcode(0xC1, 0x4); /* C1 /4 ib */
8967 ins_encode( move_long_big_shift_clr(dst,cnt) );
8968 ins_pipe( ialu_reg_long );
8969 %}
8971 // Shift Left Long by variable
8972 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
8973 match(Set dst (LShiftL dst shift));
8974 effect(KILL cr);
8975 ins_cost(500+200);
8976 size(17);
8977 format %{ "TEST $shift,32\n\t"
8978 "JEQ,s small\n\t"
8979 "MOV $dst.hi,$dst.lo\n\t"
8980 "XOR $dst.lo,$dst.lo\n"
8981 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
8982 "SHL $dst.lo,$shift" %}
8983 ins_encode( shift_left_long( dst, shift ) );
8984 ins_pipe( pipe_slow );
8985 %}
8987 // Shift Right Long by 1-31
8988 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
8989 match(Set dst (URShiftL dst cnt));
8990 effect(KILL cr);
8991 ins_cost(200);
8992 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
8993 "SHR $dst.hi,$cnt" %}
8994 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
8995 ins_encode( move_long_small_shift(dst,cnt) );
8996 ins_pipe( ialu_reg_long );
8997 %}
8999 // Shift Right Long by 32-63
9000 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9001 match(Set dst (URShiftL dst cnt));
9002 effect(KILL cr);
9003 ins_cost(300);
9004 format %{ "MOV $dst.lo,$dst.hi\n"
9005 "\tSHR $dst.lo,$cnt-32\n"
9006 "\tXOR $dst.hi,$dst.hi" %}
9007 opcode(0xC1, 0x5); /* C1 /5 ib */
9008 ins_encode( move_long_big_shift_clr(dst,cnt) );
9009 ins_pipe( ialu_reg_long );
9010 %}
9012 // Shift Right Long by variable
9013 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9014 match(Set dst (URShiftL dst shift));
9015 effect(KILL cr);
9016 ins_cost(600);
9017 size(17);
9018 format %{ "TEST $shift,32\n\t"
9019 "JEQ,s small\n\t"
9020 "MOV $dst.lo,$dst.hi\n\t"
9021 "XOR $dst.hi,$dst.hi\n"
9022 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9023 "SHR $dst.hi,$shift" %}
9024 ins_encode( shift_right_long( dst, shift ) );
9025 ins_pipe( pipe_slow );
9026 %}
9028 // Shift Right Long by 1-31
9029 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9030 match(Set dst (RShiftL dst cnt));
9031 effect(KILL cr);
9032 ins_cost(200);
9033 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9034 "SAR $dst.hi,$cnt" %}
9035 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9036 ins_encode( move_long_small_shift(dst,cnt) );
9037 ins_pipe( ialu_reg_long );
9038 %}
9040 // Shift Right Long by 32-63
9041 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9042 match(Set dst (RShiftL dst cnt));
9043 effect(KILL cr);
9044 ins_cost(300);
9045 format %{ "MOV $dst.lo,$dst.hi\n"
9046 "\tSAR $dst.lo,$cnt-32\n"
9047 "\tSAR $dst.hi,31" %}
9048 opcode(0xC1, 0x7); /* C1 /7 ib */
9049 ins_encode( move_long_big_shift_sign(dst,cnt) );
9050 ins_pipe( ialu_reg_long );
9051 %}
9053 // Shift Right arithmetic Long by variable
9054 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9055 match(Set dst (RShiftL dst shift));
9056 effect(KILL cr);
9057 ins_cost(600);
9058 size(18);
9059 format %{ "TEST $shift,32\n\t"
9060 "JEQ,s small\n\t"
9061 "MOV $dst.lo,$dst.hi\n\t"
9062 "SAR $dst.hi,31\n"
9063 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9064 "SAR $dst.hi,$shift" %}
9065 ins_encode( shift_right_arith_long( dst, shift ) );
9066 ins_pipe( pipe_slow );
9067 %}
9070 //----------Double Instructions------------------------------------------------
9071 // Double Math
9073 // Compare & branch
9075 // P6 version of float compare, sets condition codes in EFLAGS
9076 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9077 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9078 match(Set cr (CmpD src1 src2));
9079 effect(KILL rax);
9080 ins_cost(150);
9081 format %{ "FLD $src1\n\t"
9082 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9083 "JNP exit\n\t"
9084 "MOV ah,1 // saw a NaN, set CF\n\t"
9085 "SAHF\n"
9086 "exit:\tNOP // avoid branch to branch" %}
9087 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9088 ins_encode( Push_Reg_D(src1),
9089 OpcP, RegOpc(src2),
9090 cmpF_P6_fixup );
9091 ins_pipe( pipe_slow );
9092 %}
9094 // Compare & branch
9095 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9096 predicate(UseSSE<=1);
9097 match(Set cr (CmpD src1 src2));
9098 effect(KILL rax);
9099 ins_cost(200);
9100 format %{ "FLD $src1\n\t"
9101 "FCOMp $src2\n\t"
9102 "FNSTSW AX\n\t"
9103 "TEST AX,0x400\n\t"
9104 "JZ,s flags\n\t"
9105 "MOV AH,1\t# unordered treat as LT\n"
9106 "flags:\tSAHF" %}
9107 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9108 ins_encode( Push_Reg_D(src1),
9109 OpcP, RegOpc(src2),
9110 fpu_flags);
9111 ins_pipe( pipe_slow );
9112 %}
9114 // Compare vs zero into -1,0,1
9115 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9116 predicate(UseSSE<=1);
9117 match(Set dst (CmpD3 src1 zero));
9118 effect(KILL cr, KILL rax);
9119 ins_cost(280);
9120 format %{ "FTSTD $dst,$src1" %}
9121 opcode(0xE4, 0xD9);
9122 ins_encode( Push_Reg_D(src1),
9123 OpcS, OpcP, PopFPU,
9124 CmpF_Result(dst));
9125 ins_pipe( pipe_slow );
9126 %}
9128 // Compare into -1,0,1
9129 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9130 predicate(UseSSE<=1);
9131 match(Set dst (CmpD3 src1 src2));
9132 effect(KILL cr, KILL rax);
9133 ins_cost(300);
9134 format %{ "FCMPD $dst,$src1,$src2" %}
9135 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9136 ins_encode( Push_Reg_D(src1),
9137 OpcP, RegOpc(src2),
9138 CmpF_Result(dst));
9139 ins_pipe( pipe_slow );
9140 %}
9142 // float compare and set condition codes in EFLAGS by XMM regs
9143 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9144 predicate(UseSSE>=2);
9145 match(Set cr (CmpD dst src));
9146 effect(KILL rax);
9147 ins_cost(125);
9148 format %{ "COMISD $dst,$src\n"
9149 "\tJNP exit\n"
9150 "\tMOV ah,1 // saw a NaN, set CF\n"
9151 "\tSAHF\n"
9152 "exit:\tNOP // avoid branch to branch" %}
9153 opcode(0x66, 0x0F, 0x2F);
9154 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9155 ins_pipe( pipe_slow );
9156 %}
9158 // float compare and set condition codes in EFLAGS by XMM regs
9159 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9160 predicate(UseSSE>=2);
9161 match(Set cr (CmpD dst (LoadD src)));
9162 effect(KILL rax);
9163 ins_cost(145);
9164 format %{ "COMISD $dst,$src\n"
9165 "\tJNP exit\n"
9166 "\tMOV ah,1 // saw a NaN, set CF\n"
9167 "\tSAHF\n"
9168 "exit:\tNOP // avoid branch to branch" %}
9169 opcode(0x66, 0x0F, 0x2F);
9170 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9171 ins_pipe( pipe_slow );
9172 %}
9174 // Compare into -1,0,1 in XMM
9175 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9176 predicate(UseSSE>=2);
9177 match(Set dst (CmpD3 src1 src2));
9178 effect(KILL cr);
9179 ins_cost(255);
9180 format %{ "XOR $dst,$dst\n"
9181 "\tCOMISD $src1,$src2\n"
9182 "\tJP,s nan\n"
9183 "\tJEQ,s exit\n"
9184 "\tJA,s inc\n"
9185 "nan:\tDEC $dst\n"
9186 "\tJMP,s exit\n"
9187 "inc:\tINC $dst\n"
9188 "exit:"
9189 %}
9190 opcode(0x66, 0x0F, 0x2F);
9191 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9192 CmpX_Result(dst));
9193 ins_pipe( pipe_slow );
9194 %}
9196 // Compare into -1,0,1 in XMM and memory
9197 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9198 predicate(UseSSE>=2);
9199 match(Set dst (CmpD3 src1 (LoadD mem)));
9200 effect(KILL cr);
9201 ins_cost(275);
9202 format %{ "COMISD $src1,$mem\n"
9203 "\tMOV $dst,0\t\t# do not blow flags\n"
9204 "\tJP,s nan\n"
9205 "\tJEQ,s exit\n"
9206 "\tJA,s inc\n"
9207 "nan:\tDEC $dst\n"
9208 "\tJMP,s exit\n"
9209 "inc:\tINC $dst\n"
9210 "exit:"
9211 %}
9212 opcode(0x66, 0x0F, 0x2F);
9213 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9214 LdImmI(dst,0x0), CmpX_Result(dst));
9215 ins_pipe( pipe_slow );
9216 %}
9219 instruct subD_reg(regD dst, regD src) %{
9220 predicate (UseSSE <=1);
9221 match(Set dst (SubD dst src));
9223 format %{ "FLD $src\n\t"
9224 "DSUBp $dst,ST" %}
9225 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9226 ins_cost(150);
9227 ins_encode( Push_Reg_D(src),
9228 OpcP, RegOpc(dst) );
9229 ins_pipe( fpu_reg_reg );
9230 %}
9232 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9233 predicate (UseSSE <=1);
9234 match(Set dst (RoundDouble (SubD src1 src2)));
9235 ins_cost(250);
9237 format %{ "FLD $src2\n\t"
9238 "DSUB ST,$src1\n\t"
9239 "FSTP_D $dst\t# D-round" %}
9240 opcode(0xD8, 0x5);
9241 ins_encode( Push_Reg_D(src2),
9242 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9243 ins_pipe( fpu_mem_reg_reg );
9244 %}
9247 instruct subD_reg_mem(regD dst, memory src) %{
9248 predicate (UseSSE <=1);
9249 match(Set dst (SubD dst (LoadD src)));
9250 ins_cost(150);
9252 format %{ "FLD $src\n\t"
9253 "DSUBp $dst,ST" %}
9254 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9255 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9256 OpcP, RegOpc(dst) );
9257 ins_pipe( fpu_reg_mem );
9258 %}
9260 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9261 predicate (UseSSE<=1);
9262 match(Set dst (AbsD src));
9263 ins_cost(100);
9264 format %{ "FABS" %}
9265 opcode(0xE1, 0xD9);
9266 ins_encode( OpcS, OpcP );
9267 ins_pipe( fpu_reg_reg );
9268 %}
9270 instruct absXD_reg( regXD dst ) %{
9271 predicate(UseSSE>=2);
9272 match(Set dst (AbsD dst));
9273 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9274 ins_encode( AbsXD_encoding(dst));
9275 ins_pipe( pipe_slow );
9276 %}
9278 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9279 predicate(UseSSE<=1);
9280 match(Set dst (NegD src));
9281 ins_cost(100);
9282 format %{ "FCHS" %}
9283 opcode(0xE0, 0xD9);
9284 ins_encode( OpcS, OpcP );
9285 ins_pipe( fpu_reg_reg );
9286 %}
9288 instruct negXD_reg( regXD dst ) %{
9289 predicate(UseSSE>=2);
9290 match(Set dst (NegD dst));
9291 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9292 ins_encode %{
9293 __ xorpd($dst$$XMMRegister,
9294 ExternalAddress((address)double_signflip_pool));
9295 %}
9296 ins_pipe( pipe_slow );
9297 %}
9299 instruct addD_reg(regD dst, regD src) %{
9300 predicate(UseSSE<=1);
9301 match(Set dst (AddD dst src));
9302 format %{ "FLD $src\n\t"
9303 "DADD $dst,ST" %}
9304 size(4);
9305 ins_cost(150);
9306 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9307 ins_encode( Push_Reg_D(src),
9308 OpcP, RegOpc(dst) );
9309 ins_pipe( fpu_reg_reg );
9310 %}
9313 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9314 predicate(UseSSE<=1);
9315 match(Set dst (RoundDouble (AddD src1 src2)));
9316 ins_cost(250);
9318 format %{ "FLD $src2\n\t"
9319 "DADD ST,$src1\n\t"
9320 "FSTP_D $dst\t# D-round" %}
9321 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9322 ins_encode( Push_Reg_D(src2),
9323 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9324 ins_pipe( fpu_mem_reg_reg );
9325 %}
9328 instruct addD_reg_mem(regD dst, memory src) %{
9329 predicate(UseSSE<=1);
9330 match(Set dst (AddD dst (LoadD src)));
9331 ins_cost(150);
9333 format %{ "FLD $src\n\t"
9334 "DADDp $dst,ST" %}
9335 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9336 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9337 OpcP, RegOpc(dst) );
9338 ins_pipe( fpu_reg_mem );
9339 %}
9341 // add-to-memory
9342 instruct addD_mem_reg(memory dst, regD src) %{
9343 predicate(UseSSE<=1);
9344 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9345 ins_cost(150);
9347 format %{ "FLD_D $dst\n\t"
9348 "DADD ST,$src\n\t"
9349 "FST_D $dst" %}
9350 opcode(0xDD, 0x0);
9351 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9352 Opcode(0xD8), RegOpc(src),
9353 set_instruction_start,
9354 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9355 ins_pipe( fpu_reg_mem );
9356 %}
9358 instruct addD_reg_imm1(regD dst, immD1 src) %{
9359 predicate(UseSSE<=1);
9360 match(Set dst (AddD dst src));
9361 ins_cost(125);
9362 format %{ "FLD1\n\t"
9363 "DADDp $dst,ST" %}
9364 opcode(0xDE, 0x00);
9365 ins_encode( LdImmD(src),
9366 OpcP, RegOpc(dst) );
9367 ins_pipe( fpu_reg );
9368 %}
9370 instruct addD_reg_imm(regD dst, immD src) %{
9371 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9372 match(Set dst (AddD dst src));
9373 ins_cost(200);
9374 format %{ "FLD_D [$src]\n\t"
9375 "DADDp $dst,ST" %}
9376 opcode(0xDE, 0x00); /* DE /0 */
9377 ins_encode( LdImmD(src),
9378 OpcP, RegOpc(dst));
9379 ins_pipe( fpu_reg_mem );
9380 %}
9382 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9383 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9384 match(Set dst (RoundDouble (AddD src con)));
9385 ins_cost(200);
9386 format %{ "FLD_D [$con]\n\t"
9387 "DADD ST,$src\n\t"
9388 "FSTP_D $dst\t# D-round" %}
9389 opcode(0xD8, 0x00); /* D8 /0 */
9390 ins_encode( LdImmD(con),
9391 OpcP, RegOpc(src), Pop_Mem_D(dst));
9392 ins_pipe( fpu_mem_reg_con );
9393 %}
9395 // Add two double precision floating point values in xmm
9396 instruct addXD_reg(regXD dst, regXD src) %{
9397 predicate(UseSSE>=2);
9398 match(Set dst (AddD dst src));
9399 format %{ "ADDSD $dst,$src" %}
9400 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
9401 ins_pipe( pipe_slow );
9402 %}
9404 instruct addXD_imm(regXD dst, immXD con) %{
9405 predicate(UseSSE>=2);
9406 match(Set dst (AddD dst con));
9407 format %{ "ADDSD $dst,[$con]" %}
9408 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
9409 ins_pipe( pipe_slow );
9410 %}
9412 instruct addXD_mem(regXD dst, memory mem) %{
9413 predicate(UseSSE>=2);
9414 match(Set dst (AddD dst (LoadD mem)));
9415 format %{ "ADDSD $dst,$mem" %}
9416 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
9417 ins_pipe( pipe_slow );
9418 %}
9420 // Sub two double precision floating point values in xmm
9421 instruct subXD_reg(regXD dst, regXD src) %{
9422 predicate(UseSSE>=2);
9423 match(Set dst (SubD dst src));
9424 format %{ "SUBSD $dst,$src" %}
9425 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
9426 ins_pipe( pipe_slow );
9427 %}
9429 instruct subXD_imm(regXD dst, immXD con) %{
9430 predicate(UseSSE>=2);
9431 match(Set dst (SubD dst con));
9432 format %{ "SUBSD $dst,[$con]" %}
9433 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
9434 ins_pipe( pipe_slow );
9435 %}
9437 instruct subXD_mem(regXD dst, memory mem) %{
9438 predicate(UseSSE>=2);
9439 match(Set dst (SubD dst (LoadD mem)));
9440 format %{ "SUBSD $dst,$mem" %}
9441 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
9442 ins_pipe( pipe_slow );
9443 %}
9445 // Mul two double precision floating point values in xmm
9446 instruct mulXD_reg(regXD dst, regXD src) %{
9447 predicate(UseSSE>=2);
9448 match(Set dst (MulD dst src));
9449 format %{ "MULSD $dst,$src" %}
9450 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
9451 ins_pipe( pipe_slow );
9452 %}
9454 instruct mulXD_imm(regXD dst, immXD con) %{
9455 predicate(UseSSE>=2);
9456 match(Set dst (MulD dst con));
9457 format %{ "MULSD $dst,[$con]" %}
9458 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
9459 ins_pipe( pipe_slow );
9460 %}
9462 instruct mulXD_mem(regXD dst, memory mem) %{
9463 predicate(UseSSE>=2);
9464 match(Set dst (MulD dst (LoadD mem)));
9465 format %{ "MULSD $dst,$mem" %}
9466 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
9467 ins_pipe( pipe_slow );
9468 %}
9470 // Div two double precision floating point values in xmm
9471 instruct divXD_reg(regXD dst, regXD src) %{
9472 predicate(UseSSE>=2);
9473 match(Set dst (DivD dst src));
9474 format %{ "DIVSD $dst,$src" %}
9475 opcode(0xF2, 0x0F, 0x5E);
9476 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
9477 ins_pipe( pipe_slow );
9478 %}
9480 instruct divXD_imm(regXD dst, immXD con) %{
9481 predicate(UseSSE>=2);
9482 match(Set dst (DivD dst con));
9483 format %{ "DIVSD $dst,[$con]" %}
9484 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
9485 ins_pipe( pipe_slow );
9486 %}
9488 instruct divXD_mem(regXD dst, memory mem) %{
9489 predicate(UseSSE>=2);
9490 match(Set dst (DivD dst (LoadD mem)));
9491 format %{ "DIVSD $dst,$mem" %}
9492 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
9493 ins_pipe( pipe_slow );
9494 %}
9497 instruct mulD_reg(regD dst, regD src) %{
9498 predicate(UseSSE<=1);
9499 match(Set dst (MulD dst src));
9500 format %{ "FLD $src\n\t"
9501 "DMULp $dst,ST" %}
9502 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9503 ins_cost(150);
9504 ins_encode( Push_Reg_D(src),
9505 OpcP, RegOpc(dst) );
9506 ins_pipe( fpu_reg_reg );
9507 %}
9509 // Strict FP instruction biases argument before multiply then
9510 // biases result to avoid double rounding of subnormals.
9511 //
9512 // scale arg1 by multiplying arg1 by 2^(-15360)
9513 // load arg2
9514 // multiply scaled arg1 by arg2
9515 // rescale product by 2^(15360)
9516 //
9517 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
9518 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9519 match(Set dst (MulD dst src));
9520 ins_cost(1); // Select this instruction for all strict FP double multiplies
9522 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9523 "DMULp $dst,ST\n\t"
9524 "FLD $src\n\t"
9525 "DMULp $dst,ST\n\t"
9526 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9527 "DMULp $dst,ST\n\t" %}
9528 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9529 ins_encode( strictfp_bias1(dst),
9530 Push_Reg_D(src),
9531 OpcP, RegOpc(dst),
9532 strictfp_bias2(dst) );
9533 ins_pipe( fpu_reg_reg );
9534 %}
9536 instruct mulD_reg_imm(regD dst, immD src) %{
9537 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9538 match(Set dst (MulD dst src));
9539 ins_cost(200);
9540 format %{ "FLD_D [$src]\n\t"
9541 "DMULp $dst,ST" %}
9542 opcode(0xDE, 0x1); /* DE /1 */
9543 ins_encode( LdImmD(src),
9544 OpcP, RegOpc(dst) );
9545 ins_pipe( fpu_reg_mem );
9546 %}
9549 instruct mulD_reg_mem(regD dst, memory src) %{
9550 predicate( UseSSE<=1 );
9551 match(Set dst (MulD dst (LoadD src)));
9552 ins_cost(200);
9553 format %{ "FLD_D $src\n\t"
9554 "DMULp $dst,ST" %}
9555 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9556 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9557 OpcP, RegOpc(dst) );
9558 ins_pipe( fpu_reg_mem );
9559 %}
9561 //
9562 // Cisc-alternate to reg-reg multiply
9563 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
9564 predicate( UseSSE<=1 );
9565 match(Set dst (MulD src (LoadD mem)));
9566 ins_cost(250);
9567 format %{ "FLD_D $mem\n\t"
9568 "DMUL ST,$src\n\t"
9569 "FSTP_D $dst" %}
9570 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9571 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9572 OpcReg_F(src),
9573 Pop_Reg_D(dst) );
9574 ins_pipe( fpu_reg_reg_mem );
9575 %}
9578 // MACRO3 -- addD a mulD
9579 // This instruction is a '2-address' instruction in that the result goes
9580 // back to src2. This eliminates a move from the macro; possibly the
9581 // register allocator will have to add it back (and maybe not).
9582 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
9583 predicate( UseSSE<=1 );
9584 match(Set src2 (AddD (MulD src0 src1) src2));
9585 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9586 "DMUL ST,$src1\n\t"
9587 "DADDp $src2,ST" %}
9588 ins_cost(250);
9589 opcode(0xDD); /* LoadD DD /0 */
9590 ins_encode( Push_Reg_F(src0),
9591 FMul_ST_reg(src1),
9592 FAddP_reg_ST(src2) );
9593 ins_pipe( fpu_reg_reg_reg );
9594 %}
9597 // MACRO3 -- subD a mulD
9598 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
9599 predicate( UseSSE<=1 );
9600 match(Set src2 (SubD (MulD src0 src1) src2));
9601 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9602 "DMUL ST,$src1\n\t"
9603 "DSUBRp $src2,ST" %}
9604 ins_cost(250);
9605 ins_encode( Push_Reg_F(src0),
9606 FMul_ST_reg(src1),
9607 Opcode(0xDE), Opc_plus(0xE0,src2));
9608 ins_pipe( fpu_reg_reg_reg );
9609 %}
9612 instruct divD_reg(regD dst, regD src) %{
9613 predicate( UseSSE<=1 );
9614 match(Set dst (DivD dst src));
9616 format %{ "FLD $src\n\t"
9617 "FDIVp $dst,ST" %}
9618 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9619 ins_cost(150);
9620 ins_encode( Push_Reg_D(src),
9621 OpcP, RegOpc(dst) );
9622 ins_pipe( fpu_reg_reg );
9623 %}
9625 // Strict FP instruction biases argument before division then
9626 // biases result, to avoid double rounding of subnormals.
9627 //
9628 // scale dividend by multiplying dividend by 2^(-15360)
9629 // load divisor
9630 // divide scaled dividend by divisor
9631 // rescale quotient by 2^(15360)
9632 //
9633 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
9634 predicate (UseSSE<=1);
9635 match(Set dst (DivD dst src));
9636 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9637 ins_cost(01);
9639 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9640 "DMULp $dst,ST\n\t"
9641 "FLD $src\n\t"
9642 "FDIVp $dst,ST\n\t"
9643 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9644 "DMULp $dst,ST\n\t" %}
9645 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9646 ins_encode( strictfp_bias1(dst),
9647 Push_Reg_D(src),
9648 OpcP, RegOpc(dst),
9649 strictfp_bias2(dst) );
9650 ins_pipe( fpu_reg_reg );
9651 %}
9653 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9654 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9655 match(Set dst (RoundDouble (DivD src1 src2)));
9657 format %{ "FLD $src1\n\t"
9658 "FDIV ST,$src2\n\t"
9659 "FSTP_D $dst\t# D-round" %}
9660 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9661 ins_encode( Push_Reg_D(src1),
9662 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
9663 ins_pipe( fpu_mem_reg_reg );
9664 %}
9667 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
9668 predicate(UseSSE<=1);
9669 match(Set dst (ModD dst src));
9670 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
9672 format %{ "DMOD $dst,$src" %}
9673 ins_cost(250);
9674 ins_encode(Push_Reg_Mod_D(dst, src),
9675 emitModD(),
9676 Push_Result_Mod_D(src),
9677 Pop_Reg_D(dst));
9678 ins_pipe( pipe_slow );
9679 %}
9681 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
9682 predicate(UseSSE>=2);
9683 match(Set dst (ModD src0 src1));
9684 effect(KILL rax, KILL cr);
9686 format %{ "SUB ESP,8\t # DMOD\n"
9687 "\tMOVSD [ESP+0],$src1\n"
9688 "\tFLD_D [ESP+0]\n"
9689 "\tMOVSD [ESP+0],$src0\n"
9690 "\tFLD_D [ESP+0]\n"
9691 "loop:\tFPREM\n"
9692 "\tFWAIT\n"
9693 "\tFNSTSW AX\n"
9694 "\tSAHF\n"
9695 "\tJP loop\n"
9696 "\tFSTP_D [ESP+0]\n"
9697 "\tMOVSD $dst,[ESP+0]\n"
9698 "\tADD ESP,8\n"
9699 "\tFSTP ST0\t # Restore FPU Stack"
9700 %}
9701 ins_cost(250);
9702 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
9703 ins_pipe( pipe_slow );
9704 %}
9706 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
9707 predicate (UseSSE<=1);
9708 match(Set dst (SinD src));
9709 ins_cost(1800);
9710 format %{ "DSIN $dst" %}
9711 opcode(0xD9, 0xFE);
9712 ins_encode( OpcP, OpcS );
9713 ins_pipe( pipe_slow );
9714 %}
9716 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
9717 predicate (UseSSE>=2);
9718 match(Set dst (SinD dst));
9719 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9720 ins_cost(1800);
9721 format %{ "DSIN $dst" %}
9722 opcode(0xD9, 0xFE);
9723 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9724 ins_pipe( pipe_slow );
9725 %}
9727 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
9728 predicate (UseSSE<=1);
9729 match(Set dst (CosD src));
9730 ins_cost(1800);
9731 format %{ "DCOS $dst" %}
9732 opcode(0xD9, 0xFF);
9733 ins_encode( OpcP, OpcS );
9734 ins_pipe( pipe_slow );
9735 %}
9737 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
9738 predicate (UseSSE>=2);
9739 match(Set dst (CosD dst));
9740 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9741 ins_cost(1800);
9742 format %{ "DCOS $dst" %}
9743 opcode(0xD9, 0xFF);
9744 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9745 ins_pipe( pipe_slow );
9746 %}
9748 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
9749 predicate (UseSSE<=1);
9750 match(Set dst(TanD src));
9751 format %{ "DTAN $dst" %}
9752 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9753 Opcode(0xDD), Opcode(0xD8)); // fstp st
9754 ins_pipe( pipe_slow );
9755 %}
9757 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
9758 predicate (UseSSE>=2);
9759 match(Set dst(TanD dst));
9760 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9761 format %{ "DTAN $dst" %}
9762 ins_encode( Push_SrcXD(dst),
9763 Opcode(0xD9), Opcode(0xF2), // fptan
9764 Opcode(0xDD), Opcode(0xD8), // fstp st
9765 Push_ResultXD(dst) );
9766 ins_pipe( pipe_slow );
9767 %}
9769 instruct atanD_reg(regD dst, regD src) %{
9770 predicate (UseSSE<=1);
9771 match(Set dst(AtanD dst src));
9772 format %{ "DATA $dst,$src" %}
9773 opcode(0xD9, 0xF3);
9774 ins_encode( Push_Reg_D(src),
9775 OpcP, OpcS, RegOpc(dst) );
9776 ins_pipe( pipe_slow );
9777 %}
9779 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
9780 predicate (UseSSE>=2);
9781 match(Set dst(AtanD dst src));
9782 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9783 format %{ "DATA $dst,$src" %}
9784 opcode(0xD9, 0xF3);
9785 ins_encode( Push_SrcXD(src),
9786 OpcP, OpcS, Push_ResultXD(dst) );
9787 ins_pipe( pipe_slow );
9788 %}
9790 instruct sqrtD_reg(regD dst, regD src) %{
9791 predicate (UseSSE<=1);
9792 match(Set dst (SqrtD src));
9793 format %{ "DSQRT $dst,$src" %}
9794 opcode(0xFA, 0xD9);
9795 ins_encode( Push_Reg_D(src),
9796 OpcS, OpcP, Pop_Reg_D(dst) );
9797 ins_pipe( pipe_slow );
9798 %}
9800 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9801 predicate (UseSSE<=1);
9802 match(Set Y (PowD X Y)); // Raise X to the Yth power
9803 effect(KILL rax, KILL rbx, KILL rcx);
9804 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
9805 "FLD_D $X\n\t"
9806 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
9808 "FDUP \t\t\t# Q Q\n\t"
9809 "FRNDINT\t\t\t# int(Q) Q\n\t"
9810 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9811 "FISTP dword [ESP]\n\t"
9812 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9813 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9814 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9815 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9816 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9817 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9818 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9819 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9820 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9821 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9822 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9823 "MOV [ESP+0],0\n\t"
9824 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9826 "ADD ESP,8"
9827 %}
9828 ins_encode( push_stack_temp_qword,
9829 Push_Reg_D(X),
9830 Opcode(0xD9), Opcode(0xF1), // fyl2x
9831 pow_exp_core_encoding,
9832 pop_stack_temp_qword);
9833 ins_pipe( pipe_slow );
9834 %}
9836 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
9837 predicate (UseSSE>=2);
9838 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9839 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
9840 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
9841 "MOVSD [ESP],$src1\n\t"
9842 "FLD FPR1,$src1\n\t"
9843 "MOVSD [ESP],$src0\n\t"
9844 "FLD FPR1,$src0\n\t"
9845 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
9847 "FDUP \t\t\t# Q Q\n\t"
9848 "FRNDINT\t\t\t# int(Q) Q\n\t"
9849 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9850 "FISTP dword [ESP]\n\t"
9851 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9852 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9853 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9854 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9855 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9856 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9857 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9858 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9859 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9860 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9861 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9862 "MOV [ESP+0],0\n\t"
9863 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9865 "FST_D [ESP]\n\t"
9866 "MOVSD $dst,[ESP]\n\t"
9867 "ADD ESP,8"
9868 %}
9869 ins_encode( push_stack_temp_qword,
9870 push_xmm_to_fpr1(src1),
9871 push_xmm_to_fpr1(src0),
9872 Opcode(0xD9), Opcode(0xF1), // fyl2x
9873 pow_exp_core_encoding,
9874 Push_ResultXD(dst) );
9875 ins_pipe( pipe_slow );
9876 %}
9879 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9880 predicate (UseSSE<=1);
9881 match(Set dpr1 (ExpD dpr1));
9882 effect(KILL rax, KILL rbx, KILL rcx);
9883 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
9884 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
9885 "FMULP \t\t\t# Q=X*log2(e)\n\t"
9887 "FDUP \t\t\t# Q Q\n\t"
9888 "FRNDINT\t\t\t# int(Q) Q\n\t"
9889 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9890 "FISTP dword [ESP]\n\t"
9891 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9892 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9893 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9894 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9895 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9896 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9897 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9898 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9899 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9900 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9901 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9902 "MOV [ESP+0],0\n\t"
9903 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9905 "ADD ESP,8"
9906 %}
9907 ins_encode( push_stack_temp_qword,
9908 Opcode(0xD9), Opcode(0xEA), // fldl2e
9909 Opcode(0xDE), Opcode(0xC9), // fmulp
9910 pow_exp_core_encoding,
9911 pop_stack_temp_qword);
9912 ins_pipe( pipe_slow );
9913 %}
9915 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9916 predicate (UseSSE>=2);
9917 match(Set dst (ExpD src));
9918 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
9919 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
9920 "MOVSD [ESP],$src\n\t"
9921 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
9922 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
9924 "FDUP \t\t\t# Q Q\n\t"
9925 "FRNDINT\t\t\t# int(Q) Q\n\t"
9926 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9927 "FISTP dword [ESP]\n\t"
9928 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9929 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9930 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9931 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9932 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9933 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9934 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9935 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9936 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9937 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9938 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9939 "MOV [ESP+0],0\n\t"
9940 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9942 "FST_D [ESP]\n\t"
9943 "MOVSD $dst,[ESP]\n\t"
9944 "ADD ESP,8"
9945 %}
9946 ins_encode( Push_SrcXD(src),
9947 Opcode(0xD9), Opcode(0xEA), // fldl2e
9948 Opcode(0xDE), Opcode(0xC9), // fmulp
9949 pow_exp_core_encoding,
9950 Push_ResultXD(dst) );
9951 ins_pipe( pipe_slow );
9952 %}
9956 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
9957 predicate (UseSSE<=1);
9958 // The source Double operand on FPU stack
9959 match(Set dst (Log10D src));
9960 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9961 // fxch ; swap ST(0) with ST(1)
9962 // fyl2x ; compute log_10(2) * log_2(x)
9963 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9964 "FXCH \n\t"
9965 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9966 %}
9967 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9968 Opcode(0xD9), Opcode(0xC9), // fxch
9969 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9971 ins_pipe( pipe_slow );
9972 %}
9974 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
9975 predicate (UseSSE>=2);
9976 effect(KILL cr);
9977 match(Set dst (Log10D src));
9978 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9979 // fyl2x ; compute log_10(2) * log_2(x)
9980 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9981 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9982 %}
9983 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9984 Push_SrcXD(src),
9985 Opcode(0xD9), Opcode(0xF1), // fyl2x
9986 Push_ResultXD(dst));
9988 ins_pipe( pipe_slow );
9989 %}
9991 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
9992 predicate (UseSSE<=1);
9993 // The source Double operand on FPU stack
9994 match(Set dst (LogD src));
9995 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9996 // fxch ; swap ST(0) with ST(1)
9997 // fyl2x ; compute log_e(2) * log_2(x)
9998 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9999 "FXCH \n\t"
10000 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10001 %}
10002 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10003 Opcode(0xD9), Opcode(0xC9), // fxch
10004 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10006 ins_pipe( pipe_slow );
10007 %}
10009 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10010 predicate (UseSSE>=2);
10011 effect(KILL cr);
10012 // The source and result Double operands in XMM registers
10013 match(Set dst (LogD src));
10014 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10015 // fyl2x ; compute log_e(2) * log_2(x)
10016 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10017 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10018 %}
10019 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10020 Push_SrcXD(src),
10021 Opcode(0xD9), Opcode(0xF1), // fyl2x
10022 Push_ResultXD(dst));
10023 ins_pipe( pipe_slow );
10024 %}
10026 //-------------Float Instructions-------------------------------
10027 // Float Math
10029 // Code for float compare:
10030 // fcompp();
10031 // fwait(); fnstsw_ax();
10032 // sahf();
10033 // movl(dst, unordered_result);
10034 // jcc(Assembler::parity, exit);
10035 // movl(dst, less_result);
10036 // jcc(Assembler::below, exit);
10037 // movl(dst, equal_result);
10038 // jcc(Assembler::equal, exit);
10039 // movl(dst, greater_result);
10040 // exit:
10042 // P6 version of float compare, sets condition codes in EFLAGS
10043 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10044 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10045 match(Set cr (CmpF src1 src2));
10046 effect(KILL rax);
10047 ins_cost(150);
10048 format %{ "FLD $src1\n\t"
10049 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10050 "JNP exit\n\t"
10051 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10052 "SAHF\n"
10053 "exit:\tNOP // avoid branch to branch" %}
10054 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10055 ins_encode( Push_Reg_D(src1),
10056 OpcP, RegOpc(src2),
10057 cmpF_P6_fixup );
10058 ins_pipe( pipe_slow );
10059 %}
10062 // Compare & branch
10063 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10064 predicate(UseSSE == 0);
10065 match(Set cr (CmpF src1 src2));
10066 effect(KILL rax);
10067 ins_cost(200);
10068 format %{ "FLD $src1\n\t"
10069 "FCOMp $src2\n\t"
10070 "FNSTSW AX\n\t"
10071 "TEST AX,0x400\n\t"
10072 "JZ,s flags\n\t"
10073 "MOV AH,1\t# unordered treat as LT\n"
10074 "flags:\tSAHF" %}
10075 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10076 ins_encode( Push_Reg_D(src1),
10077 OpcP, RegOpc(src2),
10078 fpu_flags);
10079 ins_pipe( pipe_slow );
10080 %}
10082 // Compare vs zero into -1,0,1
10083 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10084 predicate(UseSSE == 0);
10085 match(Set dst (CmpF3 src1 zero));
10086 effect(KILL cr, KILL rax);
10087 ins_cost(280);
10088 format %{ "FTSTF $dst,$src1" %}
10089 opcode(0xE4, 0xD9);
10090 ins_encode( Push_Reg_D(src1),
10091 OpcS, OpcP, PopFPU,
10092 CmpF_Result(dst));
10093 ins_pipe( pipe_slow );
10094 %}
10096 // Compare into -1,0,1
10097 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10098 predicate(UseSSE == 0);
10099 match(Set dst (CmpF3 src1 src2));
10100 effect(KILL cr, KILL rax);
10101 ins_cost(300);
10102 format %{ "FCMPF $dst,$src1,$src2" %}
10103 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10104 ins_encode( Push_Reg_D(src1),
10105 OpcP, RegOpc(src2),
10106 CmpF_Result(dst));
10107 ins_pipe( pipe_slow );
10108 %}
10110 // float compare and set condition codes in EFLAGS by XMM regs
10111 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10112 predicate(UseSSE>=1);
10113 match(Set cr (CmpF dst src));
10114 effect(KILL rax);
10115 ins_cost(145);
10116 format %{ "COMISS $dst,$src\n"
10117 "\tJNP exit\n"
10118 "\tMOV ah,1 // saw a NaN, set CF\n"
10119 "\tSAHF\n"
10120 "exit:\tNOP // avoid branch to branch" %}
10121 opcode(0x0F, 0x2F);
10122 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10123 ins_pipe( pipe_slow );
10124 %}
10126 // float compare and set condition codes in EFLAGS by XMM regs
10127 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10128 predicate(UseSSE>=1);
10129 match(Set cr (CmpF dst (LoadF src)));
10130 effect(KILL rax);
10131 ins_cost(165);
10132 format %{ "COMISS $dst,$src\n"
10133 "\tJNP exit\n"
10134 "\tMOV ah,1 // saw a NaN, set CF\n"
10135 "\tSAHF\n"
10136 "exit:\tNOP // avoid branch to branch" %}
10137 opcode(0x0F, 0x2F);
10138 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10139 ins_pipe( pipe_slow );
10140 %}
10142 // Compare into -1,0,1 in XMM
10143 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10144 predicate(UseSSE>=1);
10145 match(Set dst (CmpF3 src1 src2));
10146 effect(KILL cr);
10147 ins_cost(255);
10148 format %{ "XOR $dst,$dst\n"
10149 "\tCOMISS $src1,$src2\n"
10150 "\tJP,s nan\n"
10151 "\tJEQ,s exit\n"
10152 "\tJA,s inc\n"
10153 "nan:\tDEC $dst\n"
10154 "\tJMP,s exit\n"
10155 "inc:\tINC $dst\n"
10156 "exit:"
10157 %}
10158 opcode(0x0F, 0x2F);
10159 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10160 ins_pipe( pipe_slow );
10161 %}
10163 // Compare into -1,0,1 in XMM and memory
10164 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10165 predicate(UseSSE>=1);
10166 match(Set dst (CmpF3 src1 (LoadF mem)));
10167 effect(KILL cr);
10168 ins_cost(275);
10169 format %{ "COMISS $src1,$mem\n"
10170 "\tMOV $dst,0\t\t# do not blow flags\n"
10171 "\tJP,s nan\n"
10172 "\tJEQ,s exit\n"
10173 "\tJA,s inc\n"
10174 "nan:\tDEC $dst\n"
10175 "\tJMP,s exit\n"
10176 "inc:\tINC $dst\n"
10177 "exit:"
10178 %}
10179 opcode(0x0F, 0x2F);
10180 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10181 ins_pipe( pipe_slow );
10182 %}
10184 // Spill to obtain 24-bit precision
10185 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10186 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10187 match(Set dst (SubF src1 src2));
10189 format %{ "FSUB $dst,$src1 - $src2" %}
10190 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10191 ins_encode( Push_Reg_F(src1),
10192 OpcReg_F(src2),
10193 Pop_Mem_F(dst) );
10194 ins_pipe( fpu_mem_reg_reg );
10195 %}
10196 //
10197 // This instruction does not round to 24-bits
10198 instruct subF_reg(regF dst, regF src) %{
10199 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10200 match(Set dst (SubF dst src));
10202 format %{ "FSUB $dst,$src" %}
10203 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10204 ins_encode( Push_Reg_F(src),
10205 OpcP, RegOpc(dst) );
10206 ins_pipe( fpu_reg_reg );
10207 %}
10209 // Spill to obtain 24-bit precision
10210 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10211 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10212 match(Set dst (AddF src1 src2));
10214 format %{ "FADD $dst,$src1,$src2" %}
10215 opcode(0xD8, 0x0); /* D8 C0+i */
10216 ins_encode( Push_Reg_F(src2),
10217 OpcReg_F(src1),
10218 Pop_Mem_F(dst) );
10219 ins_pipe( fpu_mem_reg_reg );
10220 %}
10221 //
10222 // This instruction does not round to 24-bits
10223 instruct addF_reg(regF dst, regF src) %{
10224 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10225 match(Set dst (AddF dst src));
10227 format %{ "FLD $src\n\t"
10228 "FADDp $dst,ST" %}
10229 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10230 ins_encode( Push_Reg_F(src),
10231 OpcP, RegOpc(dst) );
10232 ins_pipe( fpu_reg_reg );
10233 %}
10235 // Add two single precision floating point values in xmm
10236 instruct addX_reg(regX dst, regX src) %{
10237 predicate(UseSSE>=1);
10238 match(Set dst (AddF dst src));
10239 format %{ "ADDSS $dst,$src" %}
10240 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10241 ins_pipe( pipe_slow );
10242 %}
10244 instruct addX_imm(regX dst, immXF con) %{
10245 predicate(UseSSE>=1);
10246 match(Set dst (AddF dst con));
10247 format %{ "ADDSS $dst,[$con]" %}
10248 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10249 ins_pipe( pipe_slow );
10250 %}
10252 instruct addX_mem(regX dst, memory mem) %{
10253 predicate(UseSSE>=1);
10254 match(Set dst (AddF dst (LoadF mem)));
10255 format %{ "ADDSS $dst,$mem" %}
10256 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10257 ins_pipe( pipe_slow );
10258 %}
10260 // Subtract two single precision floating point values in xmm
10261 instruct subX_reg(regX dst, regX src) %{
10262 predicate(UseSSE>=1);
10263 match(Set dst (SubF dst src));
10264 format %{ "SUBSS $dst,$src" %}
10265 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10266 ins_pipe( pipe_slow );
10267 %}
10269 instruct subX_imm(regX dst, immXF con) %{
10270 predicate(UseSSE>=1);
10271 match(Set dst (SubF dst con));
10272 format %{ "SUBSS $dst,[$con]" %}
10273 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10274 ins_pipe( pipe_slow );
10275 %}
10277 instruct subX_mem(regX dst, memory mem) %{
10278 predicate(UseSSE>=1);
10279 match(Set dst (SubF dst (LoadF mem)));
10280 format %{ "SUBSS $dst,$mem" %}
10281 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10282 ins_pipe( pipe_slow );
10283 %}
10285 // Multiply two single precision floating point values in xmm
10286 instruct mulX_reg(regX dst, regX src) %{
10287 predicate(UseSSE>=1);
10288 match(Set dst (MulF dst src));
10289 format %{ "MULSS $dst,$src" %}
10290 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10291 ins_pipe( pipe_slow );
10292 %}
10294 instruct mulX_imm(regX dst, immXF con) %{
10295 predicate(UseSSE>=1);
10296 match(Set dst (MulF dst con));
10297 format %{ "MULSS $dst,[$con]" %}
10298 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10299 ins_pipe( pipe_slow );
10300 %}
10302 instruct mulX_mem(regX dst, memory mem) %{
10303 predicate(UseSSE>=1);
10304 match(Set dst (MulF dst (LoadF mem)));
10305 format %{ "MULSS $dst,$mem" %}
10306 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10307 ins_pipe( pipe_slow );
10308 %}
10310 // Divide two single precision floating point values in xmm
10311 instruct divX_reg(regX dst, regX src) %{
10312 predicate(UseSSE>=1);
10313 match(Set dst (DivF dst src));
10314 format %{ "DIVSS $dst,$src" %}
10315 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10316 ins_pipe( pipe_slow );
10317 %}
10319 instruct divX_imm(regX dst, immXF con) %{
10320 predicate(UseSSE>=1);
10321 match(Set dst (DivF dst con));
10322 format %{ "DIVSS $dst,[$con]" %}
10323 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
10324 ins_pipe( pipe_slow );
10325 %}
10327 instruct divX_mem(regX dst, memory mem) %{
10328 predicate(UseSSE>=1);
10329 match(Set dst (DivF dst (LoadF mem)));
10330 format %{ "DIVSS $dst,$mem" %}
10331 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10332 ins_pipe( pipe_slow );
10333 %}
10335 // Get the square root of a single precision floating point values in xmm
10336 instruct sqrtX_reg(regX dst, regX src) %{
10337 predicate(UseSSE>=1);
10338 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10339 format %{ "SQRTSS $dst,$src" %}
10340 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10341 ins_pipe( pipe_slow );
10342 %}
10344 instruct sqrtX_mem(regX dst, memory mem) %{
10345 predicate(UseSSE>=1);
10346 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10347 format %{ "SQRTSS $dst,$mem" %}
10348 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10349 ins_pipe( pipe_slow );
10350 %}
10352 // Get the square root of a double precision floating point values in xmm
10353 instruct sqrtXD_reg(regXD dst, regXD src) %{
10354 predicate(UseSSE>=2);
10355 match(Set dst (SqrtD src));
10356 format %{ "SQRTSD $dst,$src" %}
10357 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10358 ins_pipe( pipe_slow );
10359 %}
10361 instruct sqrtXD_mem(regXD dst, memory mem) %{
10362 predicate(UseSSE>=2);
10363 match(Set dst (SqrtD (LoadD mem)));
10364 format %{ "SQRTSD $dst,$mem" %}
10365 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10366 ins_pipe( pipe_slow );
10367 %}
10369 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
10370 predicate(UseSSE==0);
10371 match(Set dst (AbsF src));
10372 ins_cost(100);
10373 format %{ "FABS" %}
10374 opcode(0xE1, 0xD9);
10375 ins_encode( OpcS, OpcP );
10376 ins_pipe( fpu_reg_reg );
10377 %}
10379 instruct absX_reg(regX dst ) %{
10380 predicate(UseSSE>=1);
10381 match(Set dst (AbsF dst));
10382 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
10383 ins_encode( AbsXF_encoding(dst));
10384 ins_pipe( pipe_slow );
10385 %}
10387 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
10388 predicate(UseSSE==0);
10389 match(Set dst (NegF src));
10390 ins_cost(100);
10391 format %{ "FCHS" %}
10392 opcode(0xE0, 0xD9);
10393 ins_encode( OpcS, OpcP );
10394 ins_pipe( fpu_reg_reg );
10395 %}
10397 instruct negX_reg( regX dst ) %{
10398 predicate(UseSSE>=1);
10399 match(Set dst (NegF dst));
10400 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
10401 ins_encode( NegXF_encoding(dst));
10402 ins_pipe( pipe_slow );
10403 %}
10405 // Cisc-alternate to addF_reg
10406 // Spill to obtain 24-bit precision
10407 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10408 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10409 match(Set dst (AddF src1 (LoadF src2)));
10411 format %{ "FLD $src2\n\t"
10412 "FADD ST,$src1\n\t"
10413 "FSTP_S $dst" %}
10414 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10415 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10416 OpcReg_F(src1),
10417 Pop_Mem_F(dst) );
10418 ins_pipe( fpu_mem_reg_mem );
10419 %}
10420 //
10421 // Cisc-alternate to addF_reg
10422 // This instruction does not round to 24-bits
10423 instruct addF_reg_mem(regF dst, memory src) %{
10424 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10425 match(Set dst (AddF dst (LoadF src)));
10427 format %{ "FADD $dst,$src" %}
10428 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10429 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10430 OpcP, RegOpc(dst) );
10431 ins_pipe( fpu_reg_mem );
10432 %}
10434 // // Following two instructions for _222_mpegaudio
10435 // Spill to obtain 24-bit precision
10436 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
10437 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10438 match(Set dst (AddF src1 src2));
10440 format %{ "FADD $dst,$src1,$src2" %}
10441 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10442 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10443 OpcReg_F(src2),
10444 Pop_Mem_F(dst) );
10445 ins_pipe( fpu_mem_reg_mem );
10446 %}
10448 // Cisc-spill variant
10449 // Spill to obtain 24-bit precision
10450 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10451 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10452 match(Set dst (AddF src1 (LoadF src2)));
10454 format %{ "FADD $dst,$src1,$src2 cisc" %}
10455 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10456 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10457 set_instruction_start,
10458 OpcP, RMopc_Mem(secondary,src1),
10459 Pop_Mem_F(dst) );
10460 ins_pipe( fpu_mem_mem_mem );
10461 %}
10463 // Spill to obtain 24-bit precision
10464 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10465 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10466 match(Set dst (AddF src1 src2));
10468 format %{ "FADD $dst,$src1,$src2" %}
10469 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10470 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10471 set_instruction_start,
10472 OpcP, RMopc_Mem(secondary,src1),
10473 Pop_Mem_F(dst) );
10474 ins_pipe( fpu_mem_mem_mem );
10475 %}
10478 // Spill to obtain 24-bit precision
10479 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10480 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10481 match(Set dst (AddF src1 src2));
10482 format %{ "FLD $src1\n\t"
10483 "FADD $src2\n\t"
10484 "FSTP_S $dst" %}
10485 opcode(0xD8, 0x00); /* D8 /0 */
10486 ins_encode( Push_Reg_F(src1),
10487 Opc_MemImm_F(src2),
10488 Pop_Mem_F(dst));
10489 ins_pipe( fpu_mem_reg_con );
10490 %}
10491 //
10492 // This instruction does not round to 24-bits
10493 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
10494 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10495 match(Set dst (AddF src1 src2));
10496 format %{ "FLD $src1\n\t"
10497 "FADD $src2\n\t"
10498 "FSTP_S $dst" %}
10499 opcode(0xD8, 0x00); /* D8 /0 */
10500 ins_encode( Push_Reg_F(src1),
10501 Opc_MemImm_F(src2),
10502 Pop_Reg_F(dst));
10503 ins_pipe( fpu_reg_reg_con );
10504 %}
10506 // Spill to obtain 24-bit precision
10507 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
10508 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10509 match(Set dst (MulF src1 src2));
10511 format %{ "FLD $src1\n\t"
10512 "FMUL $src2\n\t"
10513 "FSTP_S $dst" %}
10514 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10515 ins_encode( Push_Reg_F(src1),
10516 OpcReg_F(src2),
10517 Pop_Mem_F(dst) );
10518 ins_pipe( fpu_mem_reg_reg );
10519 %}
10520 //
10521 // This instruction does not round to 24-bits
10522 instruct mulF_reg(regF dst, regF src1, regF src2) %{
10523 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10524 match(Set dst (MulF src1 src2));
10526 format %{ "FLD $src1\n\t"
10527 "FMUL $src2\n\t"
10528 "FSTP_S $dst" %}
10529 opcode(0xD8, 0x1); /* D8 C8+i */
10530 ins_encode( Push_Reg_F(src2),
10531 OpcReg_F(src1),
10532 Pop_Reg_F(dst) );
10533 ins_pipe( fpu_reg_reg_reg );
10534 %}
10537 // Spill to obtain 24-bit precision
10538 // Cisc-alternate to reg-reg multiply
10539 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10540 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10541 match(Set dst (MulF src1 (LoadF src2)));
10543 format %{ "FLD_S $src2\n\t"
10544 "FMUL $src1\n\t"
10545 "FSTP_S $dst" %}
10546 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10547 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10548 OpcReg_F(src1),
10549 Pop_Mem_F(dst) );
10550 ins_pipe( fpu_mem_reg_mem );
10551 %}
10552 //
10553 // This instruction does not round to 24-bits
10554 // Cisc-alternate to reg-reg multiply
10555 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
10556 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10557 match(Set dst (MulF src1 (LoadF src2)));
10559 format %{ "FMUL $dst,$src1,$src2" %}
10560 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10561 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10562 OpcReg_F(src1),
10563 Pop_Reg_F(dst) );
10564 ins_pipe( fpu_reg_reg_mem );
10565 %}
10567 // Spill to obtain 24-bit precision
10568 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10569 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10570 match(Set dst (MulF src1 src2));
10572 format %{ "FMUL $dst,$src1,$src2" %}
10573 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10574 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10575 set_instruction_start,
10576 OpcP, RMopc_Mem(secondary,src1),
10577 Pop_Mem_F(dst) );
10578 ins_pipe( fpu_mem_mem_mem );
10579 %}
10581 // Spill to obtain 24-bit precision
10582 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10583 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10584 match(Set dst (MulF src1 src2));
10586 format %{ "FMULc $dst,$src1,$src2" %}
10587 opcode(0xD8, 0x1); /* D8 /1*/
10588 ins_encode( Push_Reg_F(src1),
10589 Opc_MemImm_F(src2),
10590 Pop_Mem_F(dst));
10591 ins_pipe( fpu_mem_reg_con );
10592 %}
10593 //
10594 // This instruction does not round to 24-bits
10595 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
10596 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10597 match(Set dst (MulF src1 src2));
10599 format %{ "FMULc $dst. $src1, $src2" %}
10600 opcode(0xD8, 0x1); /* D8 /1*/
10601 ins_encode( Push_Reg_F(src1),
10602 Opc_MemImm_F(src2),
10603 Pop_Reg_F(dst));
10604 ins_pipe( fpu_reg_reg_con );
10605 %}
10608 //
10609 // MACRO1 -- subsume unshared load into mulF
10610 // This instruction does not round to 24-bits
10611 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
10612 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10613 match(Set dst (MulF (LoadF mem1) src));
10615 format %{ "FLD $mem1 ===MACRO1===\n\t"
10616 "FMUL ST,$src\n\t"
10617 "FSTP $dst" %}
10618 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10619 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10620 OpcReg_F(src),
10621 Pop_Reg_F(dst) );
10622 ins_pipe( fpu_reg_reg_mem );
10623 %}
10624 //
10625 // MACRO2 -- addF a mulF which subsumed an unshared load
10626 // This instruction does not round to 24-bits
10627 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
10628 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10629 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10630 ins_cost(95);
10632 format %{ "FLD $mem1 ===MACRO2===\n\t"
10633 "FMUL ST,$src1 subsume mulF left load\n\t"
10634 "FADD ST,$src2\n\t"
10635 "FSTP $dst" %}
10636 opcode(0xD9); /* LoadF D9 /0 */
10637 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10638 FMul_ST_reg(src1),
10639 FAdd_ST_reg(src2),
10640 Pop_Reg_F(dst) );
10641 ins_pipe( fpu_reg_mem_reg_reg );
10642 %}
10644 // MACRO3 -- addF a mulF
10645 // This instruction does not round to 24-bits. It is a '2-address'
10646 // instruction in that the result goes back to src2. This eliminates
10647 // a move from the macro; possibly the register allocator will have
10648 // to add it back (and maybe not).
10649 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
10650 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10651 match(Set src2 (AddF (MulF src0 src1) src2));
10653 format %{ "FLD $src0 ===MACRO3===\n\t"
10654 "FMUL ST,$src1\n\t"
10655 "FADDP $src2,ST" %}
10656 opcode(0xD9); /* LoadF D9 /0 */
10657 ins_encode( Push_Reg_F(src0),
10658 FMul_ST_reg(src1),
10659 FAddP_reg_ST(src2) );
10660 ins_pipe( fpu_reg_reg_reg );
10661 %}
10663 // MACRO4 -- divF subF
10664 // This instruction does not round to 24-bits
10665 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
10666 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10667 match(Set dst (DivF (SubF src2 src1) src3));
10669 format %{ "FLD $src2 ===MACRO4===\n\t"
10670 "FSUB ST,$src1\n\t"
10671 "FDIV ST,$src3\n\t"
10672 "FSTP $dst" %}
10673 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10674 ins_encode( Push_Reg_F(src2),
10675 subF_divF_encode(src1,src3),
10676 Pop_Reg_F(dst) );
10677 ins_pipe( fpu_reg_reg_reg_reg );
10678 %}
10680 // Spill to obtain 24-bit precision
10681 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
10682 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10683 match(Set dst (DivF src1 src2));
10685 format %{ "FDIV $dst,$src1,$src2" %}
10686 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10687 ins_encode( Push_Reg_F(src1),
10688 OpcReg_F(src2),
10689 Pop_Mem_F(dst) );
10690 ins_pipe( fpu_mem_reg_reg );
10691 %}
10692 //
10693 // This instruction does not round to 24-bits
10694 instruct divF_reg(regF dst, regF src) %{
10695 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10696 match(Set dst (DivF dst src));
10698 format %{ "FDIV $dst,$src" %}
10699 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10700 ins_encode( Push_Reg_F(src),
10701 OpcP, RegOpc(dst) );
10702 ins_pipe( fpu_reg_reg );
10703 %}
10706 // Spill to obtain 24-bit precision
10707 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10708 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10709 match(Set dst (ModF src1 src2));
10710 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10712 format %{ "FMOD $dst,$src1,$src2" %}
10713 ins_encode( Push_Reg_Mod_D(src1, src2),
10714 emitModD(),
10715 Push_Result_Mod_D(src2),
10716 Pop_Mem_F(dst));
10717 ins_pipe( pipe_slow );
10718 %}
10719 //
10720 // This instruction does not round to 24-bits
10721 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
10722 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10723 match(Set dst (ModF dst src));
10724 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10726 format %{ "FMOD $dst,$src" %}
10727 ins_encode(Push_Reg_Mod_D(dst, src),
10728 emitModD(),
10729 Push_Result_Mod_D(src),
10730 Pop_Reg_F(dst));
10731 ins_pipe( pipe_slow );
10732 %}
10734 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
10735 predicate(UseSSE>=1);
10736 match(Set dst (ModF src0 src1));
10737 effect(KILL rax, KILL cr);
10738 format %{ "SUB ESP,4\t # FMOD\n"
10739 "\tMOVSS [ESP+0],$src1\n"
10740 "\tFLD_S [ESP+0]\n"
10741 "\tMOVSS [ESP+0],$src0\n"
10742 "\tFLD_S [ESP+0]\n"
10743 "loop:\tFPREM\n"
10744 "\tFWAIT\n"
10745 "\tFNSTSW AX\n"
10746 "\tSAHF\n"
10747 "\tJP loop\n"
10748 "\tFSTP_S [ESP+0]\n"
10749 "\tMOVSS $dst,[ESP+0]\n"
10750 "\tADD ESP,4\n"
10751 "\tFSTP ST0\t # Restore FPU Stack"
10752 %}
10753 ins_cost(250);
10754 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
10755 ins_pipe( pipe_slow );
10756 %}
10759 //----------Arithmetic Conversion Instructions---------------------------------
10760 // The conversions operations are all Alpha sorted. Please keep it that way!
10762 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
10763 predicate(UseSSE==0);
10764 match(Set dst (RoundFloat src));
10765 ins_cost(125);
10766 format %{ "FST_S $dst,$src\t# F-round" %}
10767 ins_encode( Pop_Mem_Reg_F(dst, src) );
10768 ins_pipe( fpu_mem_reg );
10769 %}
10771 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
10772 predicate(UseSSE<=1);
10773 match(Set dst (RoundDouble src));
10774 ins_cost(125);
10775 format %{ "FST_D $dst,$src\t# D-round" %}
10776 ins_encode( Pop_Mem_Reg_D(dst, src) );
10777 ins_pipe( fpu_mem_reg );
10778 %}
10780 // Force rounding to 24-bit precision and 6-bit exponent
10781 instruct convD2F_reg(stackSlotF dst, regD src) %{
10782 predicate(UseSSE==0);
10783 match(Set dst (ConvD2F src));
10784 format %{ "FST_S $dst,$src\t# F-round" %}
10785 expand %{
10786 roundFloat_mem_reg(dst,src);
10787 %}
10788 %}
10790 // Force rounding to 24-bit precision and 6-bit exponent
10791 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
10792 predicate(UseSSE==1);
10793 match(Set dst (ConvD2F src));
10794 effect( KILL cr );
10795 format %{ "SUB ESP,4\n\t"
10796 "FST_S [ESP],$src\t# F-round\n\t"
10797 "MOVSS $dst,[ESP]\n\t"
10798 "ADD ESP,4" %}
10799 ins_encode( D2X_encoding(dst, src) );
10800 ins_pipe( pipe_slow );
10801 %}
10803 // Force rounding double precision to single precision
10804 instruct convXD2X_reg(regX dst, regXD src) %{
10805 predicate(UseSSE>=2);
10806 match(Set dst (ConvD2F src));
10807 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10808 opcode(0xF2, 0x0F, 0x5A);
10809 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10810 ins_pipe( pipe_slow );
10811 %}
10813 instruct convF2D_reg_reg(regD dst, regF src) %{
10814 predicate(UseSSE==0);
10815 match(Set dst (ConvF2D src));
10816 format %{ "FST_S $dst,$src\t# D-round" %}
10817 ins_encode( Pop_Reg_Reg_D(dst, src));
10818 ins_pipe( fpu_reg_reg );
10819 %}
10821 instruct convF2D_reg(stackSlotD dst, regF src) %{
10822 predicate(UseSSE==1);
10823 match(Set dst (ConvF2D src));
10824 format %{ "FST_D $dst,$src\t# D-round" %}
10825 expand %{
10826 roundDouble_mem_reg(dst,src);
10827 %}
10828 %}
10830 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
10831 predicate(UseSSE==1);
10832 match(Set dst (ConvF2D src));
10833 effect( KILL cr );
10834 format %{ "SUB ESP,4\n\t"
10835 "MOVSS [ESP] $src\n\t"
10836 "FLD_S [ESP]\n\t"
10837 "ADD ESP,4\n\t"
10838 "FSTP $dst\t# D-round" %}
10839 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
10840 ins_pipe( pipe_slow );
10841 %}
10843 instruct convX2XD_reg(regXD dst, regX src) %{
10844 predicate(UseSSE>=2);
10845 match(Set dst (ConvF2D src));
10846 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10847 opcode(0xF3, 0x0F, 0x5A);
10848 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10849 ins_pipe( pipe_slow );
10850 %}
10852 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10853 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10854 predicate(UseSSE<=1);
10855 match(Set dst (ConvD2I src));
10856 effect( KILL tmp, KILL cr );
10857 format %{ "FLD $src\t# Convert double to int \n\t"
10858 "FLDCW trunc mode\n\t"
10859 "SUB ESP,4\n\t"
10860 "FISTp [ESP + #0]\n\t"
10861 "FLDCW std/24-bit mode\n\t"
10862 "POP EAX\n\t"
10863 "CMP EAX,0x80000000\n\t"
10864 "JNE,s fast\n\t"
10865 "FLD_D $src\n\t"
10866 "CALL d2i_wrapper\n"
10867 "fast:" %}
10868 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
10869 ins_pipe( pipe_slow );
10870 %}
10872 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10873 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
10874 predicate(UseSSE>=2);
10875 match(Set dst (ConvD2I src));
10876 effect( KILL tmp, KILL cr );
10877 format %{ "CVTTSD2SI $dst, $src\n\t"
10878 "CMP $dst,0x80000000\n\t"
10879 "JNE,s fast\n\t"
10880 "SUB ESP, 8\n\t"
10881 "MOVSD [ESP], $src\n\t"
10882 "FLD_D [ESP]\n\t"
10883 "ADD ESP, 8\n\t"
10884 "CALL d2i_wrapper\n"
10885 "fast:" %}
10886 opcode(0x1); // double-precision conversion
10887 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
10888 ins_pipe( pipe_slow );
10889 %}
10891 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10892 predicate(UseSSE<=1);
10893 match(Set dst (ConvD2L src));
10894 effect( KILL cr );
10895 format %{ "FLD $src\t# Convert double to long\n\t"
10896 "FLDCW trunc mode\n\t"
10897 "SUB ESP,8\n\t"
10898 "FISTp [ESP + #0]\n\t"
10899 "FLDCW std/24-bit mode\n\t"
10900 "POP EAX\n\t"
10901 "POP EDX\n\t"
10902 "CMP EDX,0x80000000\n\t"
10903 "JNE,s fast\n\t"
10904 "TEST EAX,EAX\n\t"
10905 "JNE,s fast\n\t"
10906 "FLD $src\n\t"
10907 "CALL d2l_wrapper\n"
10908 "fast:" %}
10909 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
10910 ins_pipe( pipe_slow );
10911 %}
10913 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10914 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
10915 predicate (UseSSE>=2);
10916 match(Set dst (ConvD2L src));
10917 effect( KILL cr );
10918 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10919 "MOVSD [ESP],$src\n\t"
10920 "FLD_D [ESP]\n\t"
10921 "FLDCW trunc mode\n\t"
10922 "FISTp [ESP + #0]\n\t"
10923 "FLDCW std/24-bit mode\n\t"
10924 "POP EAX\n\t"
10925 "POP EDX\n\t"
10926 "CMP EDX,0x80000000\n\t"
10927 "JNE,s fast\n\t"
10928 "TEST EAX,EAX\n\t"
10929 "JNE,s fast\n\t"
10930 "SUB ESP,8\n\t"
10931 "MOVSD [ESP],$src\n\t"
10932 "FLD_D [ESP]\n\t"
10933 "CALL d2l_wrapper\n"
10934 "fast:" %}
10935 ins_encode( XD2L_encoding(src) );
10936 ins_pipe( pipe_slow );
10937 %}
10939 // Convert a double to an int. Java semantics require we do complex
10940 // manglations in the corner cases. So we set the rounding mode to
10941 // 'zero', store the darned double down as an int, and reset the
10942 // rounding mode to 'nearest'. The hardware stores a flag value down
10943 // if we would overflow or converted a NAN; we check for this and
10944 // and go the slow path if needed.
10945 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10946 predicate(UseSSE==0);
10947 match(Set dst (ConvF2I src));
10948 effect( KILL tmp, KILL cr );
10949 format %{ "FLD $src\t# Convert float to int \n\t"
10950 "FLDCW trunc mode\n\t"
10951 "SUB ESP,4\n\t"
10952 "FISTp [ESP + #0]\n\t"
10953 "FLDCW std/24-bit mode\n\t"
10954 "POP EAX\n\t"
10955 "CMP EAX,0x80000000\n\t"
10956 "JNE,s fast\n\t"
10957 "FLD $src\n\t"
10958 "CALL d2i_wrapper\n"
10959 "fast:" %}
10960 // D2I_encoding works for F2I
10961 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
10962 ins_pipe( pipe_slow );
10963 %}
10965 // Convert a float in xmm to an int reg.
10966 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
10967 predicate(UseSSE>=1);
10968 match(Set dst (ConvF2I src));
10969 effect( KILL tmp, KILL cr );
10970 format %{ "CVTTSS2SI $dst, $src\n\t"
10971 "CMP $dst,0x80000000\n\t"
10972 "JNE,s fast\n\t"
10973 "SUB ESP, 4\n\t"
10974 "MOVSS [ESP], $src\n\t"
10975 "FLD [ESP]\n\t"
10976 "ADD ESP, 4\n\t"
10977 "CALL d2i_wrapper\n"
10978 "fast:" %}
10979 opcode(0x0); // single-precision conversion
10980 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
10981 ins_pipe( pipe_slow );
10982 %}
10984 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10985 predicate(UseSSE==0);
10986 match(Set dst (ConvF2L src));
10987 effect( KILL cr );
10988 format %{ "FLD $src\t# Convert float to long\n\t"
10989 "FLDCW trunc mode\n\t"
10990 "SUB ESP,8\n\t"
10991 "FISTp [ESP + #0]\n\t"
10992 "FLDCW std/24-bit mode\n\t"
10993 "POP EAX\n\t"
10994 "POP EDX\n\t"
10995 "CMP EDX,0x80000000\n\t"
10996 "JNE,s fast\n\t"
10997 "TEST EAX,EAX\n\t"
10998 "JNE,s fast\n\t"
10999 "FLD $src\n\t"
11000 "CALL d2l_wrapper\n"
11001 "fast:" %}
11002 // D2L_encoding works for F2L
11003 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11004 ins_pipe( pipe_slow );
11005 %}
11007 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11008 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11009 predicate (UseSSE>=1);
11010 match(Set dst (ConvF2L src));
11011 effect( KILL cr );
11012 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11013 "MOVSS [ESP],$src\n\t"
11014 "FLD_S [ESP]\n\t"
11015 "FLDCW trunc mode\n\t"
11016 "FISTp [ESP + #0]\n\t"
11017 "FLDCW std/24-bit mode\n\t"
11018 "POP EAX\n\t"
11019 "POP EDX\n\t"
11020 "CMP EDX,0x80000000\n\t"
11021 "JNE,s fast\n\t"
11022 "TEST EAX,EAX\n\t"
11023 "JNE,s fast\n\t"
11024 "SUB ESP,4\t# Convert float to long\n\t"
11025 "MOVSS [ESP],$src\n\t"
11026 "FLD_S [ESP]\n\t"
11027 "ADD ESP,4\n\t"
11028 "CALL d2l_wrapper\n"
11029 "fast:" %}
11030 ins_encode( X2L_encoding(src) );
11031 ins_pipe( pipe_slow );
11032 %}
11034 instruct convI2D_reg(regD dst, stackSlotI src) %{
11035 predicate( UseSSE<=1 );
11036 match(Set dst (ConvI2D src));
11037 format %{ "FILD $src\n\t"
11038 "FSTP $dst" %}
11039 opcode(0xDB, 0x0); /* DB /0 */
11040 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11041 ins_pipe( fpu_reg_mem );
11042 %}
11044 instruct convI2XD_reg(regXD dst, eRegI src) %{
11045 predicate( UseSSE>=2 && !UseXmmI2D );
11046 match(Set dst (ConvI2D src));
11047 format %{ "CVTSI2SD $dst,$src" %}
11048 opcode(0xF2, 0x0F, 0x2A);
11049 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11050 ins_pipe( pipe_slow );
11051 %}
11053 instruct convI2XD_mem(regXD dst, memory mem) %{
11054 predicate( UseSSE>=2 );
11055 match(Set dst (ConvI2D (LoadI mem)));
11056 format %{ "CVTSI2SD $dst,$mem" %}
11057 opcode(0xF2, 0x0F, 0x2A);
11058 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11059 ins_pipe( pipe_slow );
11060 %}
11062 instruct convXI2XD_reg(regXD dst, eRegI src)
11063 %{
11064 predicate( UseSSE>=2 && UseXmmI2D );
11065 match(Set dst (ConvI2D src));
11067 format %{ "MOVD $dst,$src\n\t"
11068 "CVTDQ2PD $dst,$dst\t# i2d" %}
11069 ins_encode %{
11070 __ movd($dst$$XMMRegister, $src$$Register);
11071 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11072 %}
11073 ins_pipe(pipe_slow); // XXX
11074 %}
11076 instruct convI2D_mem(regD dst, memory mem) %{
11077 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11078 match(Set dst (ConvI2D (LoadI mem)));
11079 format %{ "FILD $mem\n\t"
11080 "FSTP $dst" %}
11081 opcode(0xDB); /* DB /0 */
11082 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11083 Pop_Reg_D(dst));
11084 ins_pipe( fpu_reg_mem );
11085 %}
11087 // Convert a byte to a float; no rounding step needed.
11088 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11089 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11090 match(Set dst (ConvI2F src));
11091 format %{ "FILD $src\n\t"
11092 "FSTP $dst" %}
11094 opcode(0xDB, 0x0); /* DB /0 */
11095 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11096 ins_pipe( fpu_reg_mem );
11097 %}
11099 // In 24-bit mode, force exponent rounding by storing back out
11100 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11101 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11102 match(Set dst (ConvI2F src));
11103 ins_cost(200);
11104 format %{ "FILD $src\n\t"
11105 "FSTP_S $dst" %}
11106 opcode(0xDB, 0x0); /* DB /0 */
11107 ins_encode( Push_Mem_I(src),
11108 Pop_Mem_F(dst));
11109 ins_pipe( fpu_mem_mem );
11110 %}
11112 // In 24-bit mode, force exponent rounding by storing back out
11113 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11114 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11115 match(Set dst (ConvI2F (LoadI mem)));
11116 ins_cost(200);
11117 format %{ "FILD $mem\n\t"
11118 "FSTP_S $dst" %}
11119 opcode(0xDB); /* DB /0 */
11120 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11121 Pop_Mem_F(dst));
11122 ins_pipe( fpu_mem_mem );
11123 %}
11125 // This instruction does not round to 24-bits
11126 instruct convI2F_reg(regF dst, stackSlotI src) %{
11127 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11128 match(Set dst (ConvI2F src));
11129 format %{ "FILD $src\n\t"
11130 "FSTP $dst" %}
11131 opcode(0xDB, 0x0); /* DB /0 */
11132 ins_encode( Push_Mem_I(src),
11133 Pop_Reg_F(dst));
11134 ins_pipe( fpu_reg_mem );
11135 %}
11137 // This instruction does not round to 24-bits
11138 instruct convI2F_mem(regF dst, memory mem) %{
11139 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11140 match(Set dst (ConvI2F (LoadI mem)));
11141 format %{ "FILD $mem\n\t"
11142 "FSTP $dst" %}
11143 opcode(0xDB); /* DB /0 */
11144 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11145 Pop_Reg_F(dst));
11146 ins_pipe( fpu_reg_mem );
11147 %}
11149 // Convert an int to a float in xmm; no rounding step needed.
11150 instruct convI2X_reg(regX dst, eRegI src) %{
11151 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11152 match(Set dst (ConvI2F src));
11153 format %{ "CVTSI2SS $dst, $src" %}
11155 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11156 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11157 ins_pipe( pipe_slow );
11158 %}
11160 instruct convXI2X_reg(regX dst, eRegI src)
11161 %{
11162 predicate( UseSSE>=2 && UseXmmI2F );
11163 match(Set dst (ConvI2F src));
11165 format %{ "MOVD $dst,$src\n\t"
11166 "CVTDQ2PS $dst,$dst\t# i2f" %}
11167 ins_encode %{
11168 __ movd($dst$$XMMRegister, $src$$Register);
11169 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11170 %}
11171 ins_pipe(pipe_slow); // XXX
11172 %}
11174 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11175 match(Set dst (ConvI2L src));
11176 effect(KILL cr);
11177 format %{ "MOV $dst.lo,$src\n\t"
11178 "MOV $dst.hi,$src\n\t"
11179 "SAR $dst.hi,31" %}
11180 ins_encode(convert_int_long(dst,src));
11181 ins_pipe( ialu_reg_reg_long );
11182 %}
11184 // Zero-extend convert int to long
11185 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11186 match(Set dst (AndL (ConvI2L src) mask) );
11187 effect( KILL flags );
11188 format %{ "MOV $dst.lo,$src\n\t"
11189 "XOR $dst.hi,$dst.hi" %}
11190 opcode(0x33); // XOR
11191 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11192 ins_pipe( ialu_reg_reg_long );
11193 %}
11195 // Zero-extend long
11196 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11197 match(Set dst (AndL src mask) );
11198 effect( KILL flags );
11199 format %{ "MOV $dst.lo,$src.lo\n\t"
11200 "XOR $dst.hi,$dst.hi\n\t" %}
11201 opcode(0x33); // XOR
11202 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11203 ins_pipe( ialu_reg_reg_long );
11204 %}
11206 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11207 predicate (UseSSE<=1);
11208 match(Set dst (ConvL2D src));
11209 effect( KILL cr );
11210 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11211 "PUSH $src.lo\n\t"
11212 "FILD ST,[ESP + #0]\n\t"
11213 "ADD ESP,8\n\t"
11214 "FSTP_D $dst\t# D-round" %}
11215 opcode(0xDF, 0x5); /* DF /5 */
11216 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11217 ins_pipe( pipe_slow );
11218 %}
11220 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11221 predicate (UseSSE>=2);
11222 match(Set dst (ConvL2D src));
11223 effect( KILL cr );
11224 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11225 "PUSH $src.lo\n\t"
11226 "FILD_D [ESP]\n\t"
11227 "FSTP_D [ESP]\n\t"
11228 "MOVSD $dst,[ESP]\n\t"
11229 "ADD ESP,8" %}
11230 opcode(0xDF, 0x5); /* DF /5 */
11231 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11232 ins_pipe( pipe_slow );
11233 %}
11235 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11236 predicate (UseSSE>=1);
11237 match(Set dst (ConvL2F src));
11238 effect( KILL cr );
11239 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11240 "PUSH $src.lo\n\t"
11241 "FILD_D [ESP]\n\t"
11242 "FSTP_S [ESP]\n\t"
11243 "MOVSS $dst,[ESP]\n\t"
11244 "ADD ESP,8" %}
11245 opcode(0xDF, 0x5); /* DF /5 */
11246 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11247 ins_pipe( pipe_slow );
11248 %}
11250 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11251 match(Set dst (ConvL2F src));
11252 effect( KILL cr );
11253 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11254 "PUSH $src.lo\n\t"
11255 "FILD ST,[ESP + #0]\n\t"
11256 "ADD ESP,8\n\t"
11257 "FSTP_S $dst\t# F-round" %}
11258 opcode(0xDF, 0x5); /* DF /5 */
11259 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11260 ins_pipe( pipe_slow );
11261 %}
11263 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11264 match(Set dst (ConvL2I src));
11265 effect( DEF dst, USE src );
11266 format %{ "MOV $dst,$src.lo" %}
11267 ins_encode(enc_CopyL_Lo(dst,src));
11268 ins_pipe( ialu_reg_reg );
11269 %}
11272 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11273 match(Set dst (MoveF2I src));
11274 effect( DEF dst, USE src );
11275 ins_cost(100);
11276 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11277 opcode(0x8B);
11278 ins_encode( OpcP, RegMem(dst,src));
11279 ins_pipe( ialu_reg_mem );
11280 %}
11282 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11283 predicate(UseSSE==0);
11284 match(Set dst (MoveF2I src));
11285 effect( DEF dst, USE src );
11287 ins_cost(125);
11288 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11289 ins_encode( Pop_Mem_Reg_F(dst, src) );
11290 ins_pipe( fpu_mem_reg );
11291 %}
11293 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11294 predicate(UseSSE>=1);
11295 match(Set dst (MoveF2I src));
11296 effect( DEF dst, USE src );
11298 ins_cost(95);
11299 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11300 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11301 ins_pipe( pipe_slow );
11302 %}
11304 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11305 predicate(UseSSE>=2);
11306 match(Set dst (MoveF2I src));
11307 effect( DEF dst, USE src );
11308 ins_cost(85);
11309 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11310 ins_encode( MovX2I_reg(dst, src));
11311 ins_pipe( pipe_slow );
11312 %}
11314 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11315 match(Set dst (MoveI2F src));
11316 effect( DEF dst, USE src );
11318 ins_cost(100);
11319 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11320 opcode(0x89);
11321 ins_encode( OpcPRegSS( dst, src ) );
11322 ins_pipe( ialu_mem_reg );
11323 %}
11326 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11327 predicate(UseSSE==0);
11328 match(Set dst (MoveI2F src));
11329 effect(DEF dst, USE src);
11331 ins_cost(125);
11332 format %{ "FLD_S $src\n\t"
11333 "FSTP $dst\t# MoveI2F_stack_reg" %}
11334 opcode(0xD9); /* D9 /0, FLD m32real */
11335 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11336 Pop_Reg_F(dst) );
11337 ins_pipe( fpu_reg_mem );
11338 %}
11340 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
11341 predicate(UseSSE>=1);
11342 match(Set dst (MoveI2F src));
11343 effect( DEF dst, USE src );
11345 ins_cost(95);
11346 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11347 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11348 ins_pipe( pipe_slow );
11349 %}
11351 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
11352 predicate(UseSSE>=2);
11353 match(Set dst (MoveI2F src));
11354 effect( DEF dst, USE src );
11356 ins_cost(85);
11357 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11358 ins_encode( MovI2X_reg(dst, src) );
11359 ins_pipe( pipe_slow );
11360 %}
11362 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11363 match(Set dst (MoveD2L src));
11364 effect(DEF dst, USE src);
11366 ins_cost(250);
11367 format %{ "MOV $dst.lo,$src\n\t"
11368 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11369 opcode(0x8B, 0x8B);
11370 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11371 ins_pipe( ialu_mem_long_reg );
11372 %}
11374 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11375 predicate(UseSSE<=1);
11376 match(Set dst (MoveD2L src));
11377 effect(DEF dst, USE src);
11379 ins_cost(125);
11380 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11381 ins_encode( Pop_Mem_Reg_D(dst, src) );
11382 ins_pipe( fpu_mem_reg );
11383 %}
11385 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
11386 predicate(UseSSE>=2);
11387 match(Set dst (MoveD2L src));
11388 effect(DEF dst, USE src);
11389 ins_cost(95);
11391 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11392 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
11393 ins_pipe( pipe_slow );
11394 %}
11396 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
11397 predicate(UseSSE>=2);
11398 match(Set dst (MoveD2L src));
11399 effect(DEF dst, USE src, TEMP tmp);
11400 ins_cost(85);
11401 format %{ "MOVD $dst.lo,$src\n\t"
11402 "PSHUFLW $tmp,$src,0x4E\n\t"
11403 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11404 ins_encode( MovXD2L_reg(dst, src, tmp) );
11405 ins_pipe( pipe_slow );
11406 %}
11408 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11409 match(Set dst (MoveL2D src));
11410 effect(DEF dst, USE src);
11412 ins_cost(200);
11413 format %{ "MOV $dst,$src.lo\n\t"
11414 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11415 opcode(0x89, 0x89);
11416 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11417 ins_pipe( ialu_mem_long_reg );
11418 %}
11421 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11422 predicate(UseSSE<=1);
11423 match(Set dst (MoveL2D src));
11424 effect(DEF dst, USE src);
11425 ins_cost(125);
11427 format %{ "FLD_D $src\n\t"
11428 "FSTP $dst\t# MoveL2D_stack_reg" %}
11429 opcode(0xDD); /* DD /0, FLD m64real */
11430 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11431 Pop_Reg_D(dst) );
11432 ins_pipe( fpu_reg_mem );
11433 %}
11436 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
11437 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11438 match(Set dst (MoveL2D src));
11439 effect(DEF dst, USE src);
11441 ins_cost(95);
11442 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11443 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11444 ins_pipe( pipe_slow );
11445 %}
11447 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
11448 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11449 match(Set dst (MoveL2D src));
11450 effect(DEF dst, USE src);
11452 ins_cost(95);
11453 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11454 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
11455 ins_pipe( pipe_slow );
11456 %}
11458 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
11459 predicate(UseSSE>=2);
11460 match(Set dst (MoveL2D src));
11461 effect(TEMP dst, USE src, TEMP tmp);
11462 ins_cost(85);
11463 format %{ "MOVD $dst,$src.lo\n\t"
11464 "MOVD $tmp,$src.hi\n\t"
11465 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11466 ins_encode( MovL2XD_reg(dst, src, tmp) );
11467 ins_pipe( pipe_slow );
11468 %}
11470 // Replicate scalar to packed byte (1 byte) values in xmm
11471 instruct Repl8B_reg(regXD dst, regXD src) %{
11472 predicate(UseSSE>=2);
11473 match(Set dst (Replicate8B src));
11474 format %{ "MOVDQA $dst,$src\n\t"
11475 "PUNPCKLBW $dst,$dst\n\t"
11476 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11477 ins_encode( pshufd_8x8(dst, src));
11478 ins_pipe( pipe_slow );
11479 %}
11481 // Replicate scalar to packed byte (1 byte) values in xmm
11482 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
11483 predicate(UseSSE>=2);
11484 match(Set dst (Replicate8B src));
11485 format %{ "MOVD $dst,$src\n\t"
11486 "PUNPCKLBW $dst,$dst\n\t"
11487 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11488 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11489 ins_pipe( pipe_slow );
11490 %}
11492 // Replicate scalar zero to packed byte (1 byte) values in xmm
11493 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
11494 predicate(UseSSE>=2);
11495 match(Set dst (Replicate8B zero));
11496 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11497 ins_encode( pxor(dst, dst));
11498 ins_pipe( fpu_reg_reg );
11499 %}
11501 // Replicate scalar to packed shore (2 byte) values in xmm
11502 instruct Repl4S_reg(regXD dst, regXD src) %{
11503 predicate(UseSSE>=2);
11504 match(Set dst (Replicate4S src));
11505 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11506 ins_encode( pshufd_4x16(dst, src));
11507 ins_pipe( fpu_reg_reg );
11508 %}
11510 // Replicate scalar to packed shore (2 byte) values in xmm
11511 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
11512 predicate(UseSSE>=2);
11513 match(Set dst (Replicate4S src));
11514 format %{ "MOVD $dst,$src\n\t"
11515 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11516 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11517 ins_pipe( fpu_reg_reg );
11518 %}
11520 // Replicate scalar zero to packed short (2 byte) values in xmm
11521 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
11522 predicate(UseSSE>=2);
11523 match(Set dst (Replicate4S zero));
11524 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11525 ins_encode( pxor(dst, dst));
11526 ins_pipe( fpu_reg_reg );
11527 %}
11529 // Replicate scalar to packed char (2 byte) values in xmm
11530 instruct Repl4C_reg(regXD dst, regXD src) %{
11531 predicate(UseSSE>=2);
11532 match(Set dst (Replicate4C src));
11533 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11534 ins_encode( pshufd_4x16(dst, src));
11535 ins_pipe( fpu_reg_reg );
11536 %}
11538 // Replicate scalar to packed char (2 byte) values in xmm
11539 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
11540 predicate(UseSSE>=2);
11541 match(Set dst (Replicate4C src));
11542 format %{ "MOVD $dst,$src\n\t"
11543 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11544 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11545 ins_pipe( fpu_reg_reg );
11546 %}
11548 // Replicate scalar zero to packed char (2 byte) values in xmm
11549 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
11550 predicate(UseSSE>=2);
11551 match(Set dst (Replicate4C zero));
11552 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11553 ins_encode( pxor(dst, dst));
11554 ins_pipe( fpu_reg_reg );
11555 %}
11557 // Replicate scalar to packed integer (4 byte) values in xmm
11558 instruct Repl2I_reg(regXD dst, regXD src) %{
11559 predicate(UseSSE>=2);
11560 match(Set dst (Replicate2I src));
11561 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11562 ins_encode( pshufd(dst, src, 0x00));
11563 ins_pipe( fpu_reg_reg );
11564 %}
11566 // Replicate scalar to packed integer (4 byte) values in xmm
11567 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
11568 predicate(UseSSE>=2);
11569 match(Set dst (Replicate2I src));
11570 format %{ "MOVD $dst,$src\n\t"
11571 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11572 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
11573 ins_pipe( fpu_reg_reg );
11574 %}
11576 // Replicate scalar zero to packed integer (2 byte) values in xmm
11577 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
11578 predicate(UseSSE>=2);
11579 match(Set dst (Replicate2I zero));
11580 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11581 ins_encode( pxor(dst, dst));
11582 ins_pipe( fpu_reg_reg );
11583 %}
11585 // Replicate scalar to packed single precision floating point values in xmm
11586 instruct Repl2F_reg(regXD dst, regXD src) %{
11587 predicate(UseSSE>=2);
11588 match(Set dst (Replicate2F src));
11589 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11590 ins_encode( pshufd(dst, src, 0xe0));
11591 ins_pipe( fpu_reg_reg );
11592 %}
11594 // Replicate scalar to packed single precision floating point values in xmm
11595 instruct Repl2F_regX(regXD dst, regX src) %{
11596 predicate(UseSSE>=2);
11597 match(Set dst (Replicate2F src));
11598 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11599 ins_encode( pshufd(dst, src, 0xe0));
11600 ins_pipe( fpu_reg_reg );
11601 %}
11603 // Replicate scalar to packed single precision floating point values in xmm
11604 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
11605 predicate(UseSSE>=2);
11606 match(Set dst (Replicate2F zero));
11607 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11608 ins_encode( pxor(dst, dst));
11609 ins_pipe( fpu_reg_reg );
11610 %}
11614 // =======================================================================
11615 // fast clearing of an array
11617 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11618 match(Set dummy (ClearArray cnt base));
11619 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11620 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11621 "XOR EAX,EAX\n\t"
11622 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11623 opcode(0,0x4);
11624 ins_encode( Opcode(0xD1), RegOpc(ECX),
11625 OpcRegReg(0x33,EAX,EAX),
11626 Opcode(0xF3), Opcode(0xAB) );
11627 ins_pipe( pipe_slow );
11628 %}
11630 instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
11631 match(Set result (StrComp str1 str2));
11632 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
11633 //ins_cost(300);
11635 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
11636 ins_encode( enc_String_Compare() );
11637 ins_pipe( pipe_slow );
11638 %}
11640 // fast array equals
11641 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
11642 match(Set result (AryEq ary1 ary2));
11643 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr);
11644 //ins_cost(300);
11646 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EAX, EBX" %}
11647 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) );
11648 ins_pipe( pipe_slow );
11649 %}
11651 //----------Control Flow Instructions------------------------------------------
11652 // Signed compare Instructions
11653 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
11654 match(Set cr (CmpI op1 op2));
11655 effect( DEF cr, USE op1, USE op2 );
11656 format %{ "CMP $op1,$op2" %}
11657 opcode(0x3B); /* Opcode 3B /r */
11658 ins_encode( OpcP, RegReg( op1, op2) );
11659 ins_pipe( ialu_cr_reg_reg );
11660 %}
11662 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
11663 match(Set cr (CmpI op1 op2));
11664 effect( DEF cr, USE op1 );
11665 format %{ "CMP $op1,$op2" %}
11666 opcode(0x81,0x07); /* Opcode 81 /7 */
11667 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11668 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11669 ins_pipe( ialu_cr_reg_imm );
11670 %}
11672 // Cisc-spilled version of cmpI_eReg
11673 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
11674 match(Set cr (CmpI op1 (LoadI op2)));
11676 format %{ "CMP $op1,$op2" %}
11677 ins_cost(500);
11678 opcode(0x3B); /* Opcode 3B /r */
11679 ins_encode( OpcP, RegMem( op1, op2) );
11680 ins_pipe( ialu_cr_reg_mem );
11681 %}
11683 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
11684 match(Set cr (CmpI src zero));
11685 effect( DEF cr, USE src );
11687 format %{ "TEST $src,$src" %}
11688 opcode(0x85);
11689 ins_encode( OpcP, RegReg( src, src ) );
11690 ins_pipe( ialu_cr_reg_imm );
11691 %}
11693 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
11694 match(Set cr (CmpI (AndI src con) zero));
11696 format %{ "TEST $src,$con" %}
11697 opcode(0xF7,0x00);
11698 ins_encode( OpcP, RegOpc(src), Con32(con) );
11699 ins_pipe( ialu_cr_reg_imm );
11700 %}
11702 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
11703 match(Set cr (CmpI (AndI src mem) zero));
11705 format %{ "TEST $src,$mem" %}
11706 opcode(0x85);
11707 ins_encode( OpcP, RegMem( src, mem ) );
11708 ins_pipe( ialu_cr_reg_mem );
11709 %}
11711 // Unsigned compare Instructions; really, same as signed except they
11712 // produce an eFlagsRegU instead of eFlagsReg.
11713 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
11714 match(Set cr (CmpU op1 op2));
11716 format %{ "CMPu $op1,$op2" %}
11717 opcode(0x3B); /* Opcode 3B /r */
11718 ins_encode( OpcP, RegReg( op1, op2) );
11719 ins_pipe( ialu_cr_reg_reg );
11720 %}
11722 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
11723 match(Set cr (CmpU op1 op2));
11725 format %{ "CMPu $op1,$op2" %}
11726 opcode(0x81,0x07); /* Opcode 81 /7 */
11727 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11728 ins_pipe( ialu_cr_reg_imm );
11729 %}
11731 // // Cisc-spilled version of cmpU_eReg
11732 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
11733 match(Set cr (CmpU op1 (LoadI op2)));
11735 format %{ "CMPu $op1,$op2" %}
11736 ins_cost(500);
11737 opcode(0x3B); /* Opcode 3B /r */
11738 ins_encode( OpcP, RegMem( op1, op2) );
11739 ins_pipe( ialu_cr_reg_mem );
11740 %}
11742 // // Cisc-spilled version of cmpU_eReg
11743 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
11744 // match(Set cr (CmpU (LoadI op1) op2));
11745 //
11746 // format %{ "CMPu $op1,$op2" %}
11747 // ins_cost(500);
11748 // opcode(0x39); /* Opcode 39 /r */
11749 // ins_encode( OpcP, RegMem( op1, op2) );
11750 //%}
11752 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
11753 match(Set cr (CmpU src zero));
11755 format %{ "TESTu $src,$src" %}
11756 opcode(0x85);
11757 ins_encode( OpcP, RegReg( src, src ) );
11758 ins_pipe( ialu_cr_reg_imm );
11759 %}
11761 // Unsigned pointer compare Instructions
11762 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11763 match(Set cr (CmpP op1 op2));
11765 format %{ "CMPu $op1,$op2" %}
11766 opcode(0x3B); /* Opcode 3B /r */
11767 ins_encode( OpcP, RegReg( op1, op2) );
11768 ins_pipe( ialu_cr_reg_reg );
11769 %}
11771 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11772 match(Set cr (CmpP op1 op2));
11774 format %{ "CMPu $op1,$op2" %}
11775 opcode(0x81,0x07); /* Opcode 81 /7 */
11776 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11777 ins_pipe( ialu_cr_reg_imm );
11778 %}
11780 // // Cisc-spilled version of cmpP_eReg
11781 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11782 match(Set cr (CmpP op1 (LoadP op2)));
11784 format %{ "CMPu $op1,$op2" %}
11785 ins_cost(500);
11786 opcode(0x3B); /* Opcode 3B /r */
11787 ins_encode( OpcP, RegMem( op1, op2) );
11788 ins_pipe( ialu_cr_reg_mem );
11789 %}
11791 // // Cisc-spilled version of cmpP_eReg
11792 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11793 // match(Set cr (CmpP (LoadP op1) op2));
11794 //
11795 // format %{ "CMPu $op1,$op2" %}
11796 // ins_cost(500);
11797 // opcode(0x39); /* Opcode 39 /r */
11798 // ins_encode( OpcP, RegMem( op1, op2) );
11799 //%}
11801 // Compare raw pointer (used in out-of-heap check).
11802 // Only works because non-oop pointers must be raw pointers
11803 // and raw pointers have no anti-dependencies.
11804 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11805 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11806 match(Set cr (CmpP op1 (LoadP op2)));
11808 format %{ "CMPu $op1,$op2" %}
11809 opcode(0x3B); /* Opcode 3B /r */
11810 ins_encode( OpcP, RegMem( op1, op2) );
11811 ins_pipe( ialu_cr_reg_mem );
11812 %}
11814 //
11815 // This will generate a signed flags result. This should be ok
11816 // since any compare to a zero should be eq/neq.
11817 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11818 match(Set cr (CmpP src zero));
11820 format %{ "TEST $src,$src" %}
11821 opcode(0x85);
11822 ins_encode( OpcP, RegReg( src, src ) );
11823 ins_pipe( ialu_cr_reg_imm );
11824 %}
11826 // Cisc-spilled version of testP_reg
11827 // This will generate a signed flags result. This should be ok
11828 // since any compare to a zero should be eq/neq.
11829 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11830 match(Set cr (CmpP (LoadP op) zero));
11832 format %{ "TEST $op,0xFFFFFFFF" %}
11833 ins_cost(500);
11834 opcode(0xF7); /* Opcode F7 /0 */
11835 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11836 ins_pipe( ialu_cr_reg_imm );
11837 %}
11839 // Yanked all unsigned pointer compare operations.
11840 // Pointer compares are done with CmpP which is already unsigned.
11842 //----------Max and Min--------------------------------------------------------
11843 // Min Instructions
11844 ////
11845 // *** Min and Max using the conditional move are slower than the
11846 // *** branch version on a Pentium III.
11847 // // Conditional move for min
11848 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
11849 // effect( USE_DEF op2, USE op1, USE cr );
11850 // format %{ "CMOVlt $op2,$op1\t! min" %}
11851 // opcode(0x4C,0x0F);
11852 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11853 // ins_pipe( pipe_cmov_reg );
11854 //%}
11855 //
11856 //// Min Register with Register (P6 version)
11857 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
11858 // predicate(VM_Version::supports_cmov() );
11859 // match(Set op2 (MinI op1 op2));
11860 // ins_cost(200);
11861 // expand %{
11862 // eFlagsReg cr;
11863 // compI_eReg(cr,op1,op2);
11864 // cmovI_reg_lt(op2,op1,cr);
11865 // %}
11866 //%}
11868 // Min Register with Register (generic version)
11869 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
11870 match(Set dst (MinI dst src));
11871 effect(KILL flags);
11872 ins_cost(300);
11874 format %{ "MIN $dst,$src" %}
11875 opcode(0xCC);
11876 ins_encode( min_enc(dst,src) );
11877 ins_pipe( pipe_slow );
11878 %}
11880 // Max Register with Register
11881 // *** Min and Max using the conditional move are slower than the
11882 // *** branch version on a Pentium III.
11883 // // Conditional move for max
11884 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
11885 // effect( USE_DEF op2, USE op1, USE cr );
11886 // format %{ "CMOVgt $op2,$op1\t! max" %}
11887 // opcode(0x4F,0x0F);
11888 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11889 // ins_pipe( pipe_cmov_reg );
11890 //%}
11891 //
11892 // // Max Register with Register (P6 version)
11893 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
11894 // predicate(VM_Version::supports_cmov() );
11895 // match(Set op2 (MaxI op1 op2));
11896 // ins_cost(200);
11897 // expand %{
11898 // eFlagsReg cr;
11899 // compI_eReg(cr,op1,op2);
11900 // cmovI_reg_gt(op2,op1,cr);
11901 // %}
11902 //%}
11904 // Max Register with Register (generic version)
11905 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
11906 match(Set dst (MaxI dst src));
11907 effect(KILL flags);
11908 ins_cost(300);
11910 format %{ "MAX $dst,$src" %}
11911 opcode(0xCC);
11912 ins_encode( max_enc(dst,src) );
11913 ins_pipe( pipe_slow );
11914 %}
11916 // ============================================================================
11917 // Branch Instructions
11918 // Jump Table
11919 instruct jumpXtnd(eRegI switch_val) %{
11920 match(Jump switch_val);
11921 ins_cost(350);
11923 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
11925 ins_encode %{
11926 address table_base = __ address_table_constant(_index2label);
11928 // Jump to Address(table_base + switch_reg)
11929 InternalAddress table(table_base);
11930 Address index(noreg, $switch_val$$Register, Address::times_1);
11931 __ jump(ArrayAddress(table, index));
11932 %}
11933 ins_pc_relative(1);
11934 ins_pipe(pipe_jmp);
11935 %}
11937 // Jump Direct - Label defines a relative address from JMP+1
11938 instruct jmpDir(label labl) %{
11939 match(Goto);
11940 effect(USE labl);
11942 ins_cost(300);
11943 format %{ "JMP $labl" %}
11944 size(5);
11945 opcode(0xE9);
11946 ins_encode( OpcP, Lbl( labl ) );
11947 ins_pipe( pipe_jmp );
11948 ins_pc_relative(1);
11949 %}
11951 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11952 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11953 match(If cop cr);
11954 effect(USE labl);
11956 ins_cost(300);
11957 format %{ "J$cop $labl" %}
11958 size(6);
11959 opcode(0x0F, 0x80);
11960 ins_encode( Jcc( cop, labl) );
11961 ins_pipe( pipe_jcc );
11962 ins_pc_relative(1);
11963 %}
11965 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11966 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
11967 match(CountedLoopEnd cop cr);
11968 effect(USE labl);
11970 ins_cost(300);
11971 format %{ "J$cop $labl\t# Loop end" %}
11972 size(6);
11973 opcode(0x0F, 0x80);
11974 ins_encode( Jcc( cop, labl) );
11975 ins_pipe( pipe_jcc );
11976 ins_pc_relative(1);
11977 %}
11979 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11980 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11981 match(CountedLoopEnd cop cmp);
11982 effect(USE labl);
11984 ins_cost(300);
11985 format %{ "J$cop,u $labl\t# Loop end" %}
11986 size(6);
11987 opcode(0x0F, 0x80);
11988 ins_encode( Jcc( cop, labl) );
11989 ins_pipe( pipe_jcc );
11990 ins_pc_relative(1);
11991 %}
11993 // Jump Direct Conditional - using unsigned comparison
11994 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11995 match(If cop cmp);
11996 effect(USE labl);
11998 ins_cost(300);
11999 format %{ "J$cop,u $labl" %}
12000 size(6);
12001 opcode(0x0F, 0x80);
12002 ins_encode( Jcc( cop, labl) );
12003 ins_pipe( pipe_jcc );
12004 ins_pc_relative(1);
12005 %}
12007 // ============================================================================
12008 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12009 // array for an instance of the superklass. Set a hidden internal cache on a
12010 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12011 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12012 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12013 match(Set result (PartialSubtypeCheck sub super));
12014 effect( KILL rcx, KILL cr );
12016 ins_cost(1100); // slightly larger than the next version
12017 format %{ "CMPL EAX,ESI\n\t"
12018 "JEQ,s hit\n\t"
12019 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12020 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12021 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12022 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12023 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12024 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12025 "hit:\n\t"
12026 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12027 "miss:\t" %}
12029 opcode(0x1); // Force a XOR of EDI
12030 ins_encode( enc_PartialSubtypeCheck() );
12031 ins_pipe( pipe_slow );
12032 %}
12034 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12035 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12036 effect( KILL rcx, KILL result );
12038 ins_cost(1000);
12039 format %{ "CMPL EAX,ESI\n\t"
12040 "JEQ,s miss\t# Actually a hit; we are done.\n\t"
12041 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12042 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12043 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12044 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12045 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12046 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12047 "miss:\t" %}
12049 opcode(0x0); // No need to XOR EDI
12050 ins_encode( enc_PartialSubtypeCheck() );
12051 ins_pipe( pipe_slow );
12052 %}
12054 // ============================================================================
12055 // Branch Instructions -- short offset versions
12056 //
12057 // These instructions are used to replace jumps of a long offset (the default
12058 // match) with jumps of a shorter offset. These instructions are all tagged
12059 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12060 // match rules in general matching. Instead, the ADLC generates a conversion
12061 // method in the MachNode which can be used to do in-place replacement of the
12062 // long variant with the shorter variant. The compiler will determine if a
12063 // branch can be taken by the is_short_branch_offset() predicate in the machine
12064 // specific code section of the file.
12066 // Jump Direct - Label defines a relative address from JMP+1
12067 instruct jmpDir_short(label labl) %{
12068 match(Goto);
12069 effect(USE labl);
12071 ins_cost(300);
12072 format %{ "JMP,s $labl" %}
12073 size(2);
12074 opcode(0xEB);
12075 ins_encode( OpcP, LblShort( labl ) );
12076 ins_pipe( pipe_jmp );
12077 ins_pc_relative(1);
12078 ins_short_branch(1);
12079 %}
12081 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12082 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12083 match(If cop cr);
12084 effect(USE labl);
12086 ins_cost(300);
12087 format %{ "J$cop,s $labl" %}
12088 size(2);
12089 opcode(0x70);
12090 ins_encode( JccShort( cop, labl) );
12091 ins_pipe( pipe_jcc );
12092 ins_pc_relative(1);
12093 ins_short_branch(1);
12094 %}
12096 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12097 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12098 match(CountedLoopEnd cop cr);
12099 effect(USE labl);
12101 ins_cost(300);
12102 format %{ "J$cop,s $labl" %}
12103 size(2);
12104 opcode(0x70);
12105 ins_encode( JccShort( cop, labl) );
12106 ins_pipe( pipe_jcc );
12107 ins_pc_relative(1);
12108 ins_short_branch(1);
12109 %}
12111 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12112 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12113 match(CountedLoopEnd cop cmp);
12114 effect(USE labl);
12116 ins_cost(300);
12117 format %{ "J$cop,us $labl" %}
12118 size(2);
12119 opcode(0x70);
12120 ins_encode( JccShort( cop, labl) );
12121 ins_pipe( pipe_jcc );
12122 ins_pc_relative(1);
12123 ins_short_branch(1);
12124 %}
12126 // Jump Direct Conditional - using unsigned comparison
12127 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12128 match(If cop cmp);
12129 effect(USE labl);
12131 ins_cost(300);
12132 format %{ "J$cop,us $labl" %}
12133 size(2);
12134 opcode(0x70);
12135 ins_encode( JccShort( cop, labl) );
12136 ins_pipe( pipe_jcc );
12137 ins_pc_relative(1);
12138 ins_short_branch(1);
12139 %}
12141 // ============================================================================
12142 // Long Compare
12143 //
12144 // Currently we hold longs in 2 registers. Comparing such values efficiently
12145 // is tricky. The flavor of compare used depends on whether we are testing
12146 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12147 // The GE test is the negated LT test. The LE test can be had by commuting
12148 // the operands (yielding a GE test) and then negating; negate again for the
12149 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12150 // NE test is negated from that.
12152 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12153 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12154 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12155 // are collapsed internally in the ADLC's dfa-gen code. The match for
12156 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12157 // foo match ends up with the wrong leaf. One fix is to not match both
12158 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12159 // both forms beat the trinary form of long-compare and both are very useful
12160 // on Intel which has so few registers.
12162 // Manifest a CmpL result in an integer register. Very painful.
12163 // This is the test to avoid.
12164 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12165 match(Set dst (CmpL3 src1 src2));
12166 effect( KILL flags );
12167 ins_cost(1000);
12168 format %{ "XOR $dst,$dst\n\t"
12169 "CMP $src1.hi,$src2.hi\n\t"
12170 "JLT,s m_one\n\t"
12171 "JGT,s p_one\n\t"
12172 "CMP $src1.lo,$src2.lo\n\t"
12173 "JB,s m_one\n\t"
12174 "JEQ,s done\n"
12175 "p_one:\tINC $dst\n\t"
12176 "JMP,s done\n"
12177 "m_one:\tDEC $dst\n"
12178 "done:" %}
12179 ins_encode %{
12180 Label p_one, m_one, done;
12181 __ xorl($dst$$Register, $dst$$Register);
12182 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12183 __ jccb(Assembler::less, m_one);
12184 __ jccb(Assembler::greater, p_one);
12185 __ cmpl($src1$$Register, $src2$$Register);
12186 __ jccb(Assembler::below, m_one);
12187 __ jccb(Assembler::equal, done);
12188 __ bind(p_one);
12189 __ increment($dst$$Register);
12190 __ jmpb(done);
12191 __ bind(m_one);
12192 __ decrement($dst$$Register);
12193 __ bind(done);
12194 %}
12195 ins_pipe( pipe_slow );
12196 %}
12198 //======
12199 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12200 // compares. Can be used for LE or GT compares by reversing arguments.
12201 // NOT GOOD FOR EQ/NE tests.
12202 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12203 match( Set flags (CmpL src zero ));
12204 ins_cost(100);
12205 format %{ "TEST $src.hi,$src.hi" %}
12206 opcode(0x85);
12207 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12208 ins_pipe( ialu_cr_reg_reg );
12209 %}
12211 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12212 // compares. Can be used for LE or GT compares by reversing arguments.
12213 // NOT GOOD FOR EQ/NE tests.
12214 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12215 match( Set flags (CmpL src1 src2 ));
12216 effect( TEMP tmp );
12217 ins_cost(300);
12218 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12219 "MOV $tmp,$src1.hi\n\t"
12220 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12221 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12222 ins_pipe( ialu_cr_reg_reg );
12223 %}
12225 // Long compares reg < zero/req OR reg >= zero/req.
12226 // Just a wrapper for a normal branch, plus the predicate test.
12227 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12228 match(If cmp flags);
12229 effect(USE labl);
12230 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12231 expand %{
12232 jmpCon(cmp,flags,labl); // JLT or JGE...
12233 %}
12234 %}
12236 // Compare 2 longs and CMOVE longs.
12237 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12238 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12239 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12240 ins_cost(400);
12241 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12242 "CMOV$cmp $dst.hi,$src.hi" %}
12243 opcode(0x0F,0x40);
12244 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12245 ins_pipe( pipe_cmov_reg_long );
12246 %}
12248 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12249 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12250 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12251 ins_cost(500);
12252 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12253 "CMOV$cmp $dst.hi,$src.hi" %}
12254 opcode(0x0F,0x40);
12255 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12256 ins_pipe( pipe_cmov_reg_long );
12257 %}
12259 // Compare 2 longs and CMOVE ints.
12260 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12261 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12262 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12263 ins_cost(200);
12264 format %{ "CMOV$cmp $dst,$src" %}
12265 opcode(0x0F,0x40);
12266 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12267 ins_pipe( pipe_cmov_reg );
12268 %}
12270 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12271 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12272 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12273 ins_cost(250);
12274 format %{ "CMOV$cmp $dst,$src" %}
12275 opcode(0x0F,0x40);
12276 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12277 ins_pipe( pipe_cmov_mem );
12278 %}
12280 // Compare 2 longs and CMOVE ints.
12281 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12282 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12283 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12284 ins_cost(200);
12285 format %{ "CMOV$cmp $dst,$src" %}
12286 opcode(0x0F,0x40);
12287 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12288 ins_pipe( pipe_cmov_reg );
12289 %}
12291 // Compare 2 longs and CMOVE doubles
12292 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12293 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12294 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12295 ins_cost(200);
12296 expand %{
12297 fcmovD_regS(cmp,flags,dst,src);
12298 %}
12299 %}
12301 // Compare 2 longs and CMOVE doubles
12302 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
12303 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12304 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12305 ins_cost(200);
12306 expand %{
12307 fcmovXD_regS(cmp,flags,dst,src);
12308 %}
12309 %}
12311 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12312 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12313 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12314 ins_cost(200);
12315 expand %{
12316 fcmovF_regS(cmp,flags,dst,src);
12317 %}
12318 %}
12320 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
12321 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12322 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12323 ins_cost(200);
12324 expand %{
12325 fcmovX_regS(cmp,flags,dst,src);
12326 %}
12327 %}
12329 //======
12330 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12331 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12332 match( Set flags (CmpL src zero ));
12333 effect(TEMP tmp);
12334 ins_cost(200);
12335 format %{ "MOV $tmp,$src.lo\n\t"
12336 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12337 ins_encode( long_cmp_flags0( src, tmp ) );
12338 ins_pipe( ialu_reg_reg_long );
12339 %}
12341 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12342 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12343 match( Set flags (CmpL src1 src2 ));
12344 ins_cost(200+300);
12345 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12346 "JNE,s skip\n\t"
12347 "CMP $src1.hi,$src2.hi\n\t"
12348 "skip:\t" %}
12349 ins_encode( long_cmp_flags1( src1, src2 ) );
12350 ins_pipe( ialu_cr_reg_reg );
12351 %}
12353 // Long compare reg == zero/reg OR reg != zero/reg
12354 // Just a wrapper for a normal branch, plus the predicate test.
12355 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12356 match(If cmp flags);
12357 effect(USE labl);
12358 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12359 expand %{
12360 jmpCon(cmp,flags,labl); // JEQ or JNE...
12361 %}
12362 %}
12364 // Compare 2 longs and CMOVE longs.
12365 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12366 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12367 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12368 ins_cost(400);
12369 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12370 "CMOV$cmp $dst.hi,$src.hi" %}
12371 opcode(0x0F,0x40);
12372 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12373 ins_pipe( pipe_cmov_reg_long );
12374 %}
12376 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12377 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12378 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12379 ins_cost(500);
12380 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12381 "CMOV$cmp $dst.hi,$src.hi" %}
12382 opcode(0x0F,0x40);
12383 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12384 ins_pipe( pipe_cmov_reg_long );
12385 %}
12387 // Compare 2 longs and CMOVE ints.
12388 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12389 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12390 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12391 ins_cost(200);
12392 format %{ "CMOV$cmp $dst,$src" %}
12393 opcode(0x0F,0x40);
12394 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12395 ins_pipe( pipe_cmov_reg );
12396 %}
12398 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
12399 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12400 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12401 ins_cost(250);
12402 format %{ "CMOV$cmp $dst,$src" %}
12403 opcode(0x0F,0x40);
12404 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12405 ins_pipe( pipe_cmov_mem );
12406 %}
12408 // Compare 2 longs and CMOVE ints.
12409 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12410 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12411 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12412 ins_cost(200);
12413 format %{ "CMOV$cmp $dst,$src" %}
12414 opcode(0x0F,0x40);
12415 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12416 ins_pipe( pipe_cmov_reg );
12417 %}
12419 // Compare 2 longs and CMOVE doubles
12420 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12421 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12422 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12423 ins_cost(200);
12424 expand %{
12425 fcmovD_regS(cmp,flags,dst,src);
12426 %}
12427 %}
12429 // Compare 2 longs and CMOVE doubles
12430 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
12431 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12432 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12433 ins_cost(200);
12434 expand %{
12435 fcmovXD_regS(cmp,flags,dst,src);
12436 %}
12437 %}
12439 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12440 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12441 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12442 ins_cost(200);
12443 expand %{
12444 fcmovF_regS(cmp,flags,dst,src);
12445 %}
12446 %}
12448 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
12449 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12450 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12451 ins_cost(200);
12452 expand %{
12453 fcmovX_regS(cmp,flags,dst,src);
12454 %}
12455 %}
12457 //======
12458 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12459 // Same as cmpL_reg_flags_LEGT except must negate src
12460 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
12461 match( Set flags (CmpL src zero ));
12462 effect( TEMP tmp );
12463 ins_cost(300);
12464 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12465 "CMP $tmp,$src.lo\n\t"
12466 "SBB $tmp,$src.hi\n\t" %}
12467 ins_encode( long_cmp_flags3(src, tmp) );
12468 ins_pipe( ialu_reg_reg_long );
12469 %}
12471 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12472 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12473 // requires a commuted test to get the same result.
12474 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12475 match( Set flags (CmpL src1 src2 ));
12476 effect( TEMP tmp );
12477 ins_cost(300);
12478 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12479 "MOV $tmp,$src2.hi\n\t"
12480 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12481 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12482 ins_pipe( ialu_cr_reg_reg );
12483 %}
12485 // Long compares reg < zero/req OR reg >= zero/req.
12486 // Just a wrapper for a normal branch, plus the predicate test
12487 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12488 match(If cmp flags);
12489 effect(USE labl);
12490 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12491 ins_cost(300);
12492 expand %{
12493 jmpCon(cmp,flags,labl); // JGT or JLE...
12494 %}
12495 %}
12497 // Compare 2 longs and CMOVE longs.
12498 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12499 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12500 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12501 ins_cost(400);
12502 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12503 "CMOV$cmp $dst.hi,$src.hi" %}
12504 opcode(0x0F,0x40);
12505 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12506 ins_pipe( pipe_cmov_reg_long );
12507 %}
12509 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12510 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12511 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12512 ins_cost(500);
12513 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12514 "CMOV$cmp $dst.hi,$src.hi+4" %}
12515 opcode(0x0F,0x40);
12516 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12517 ins_pipe( pipe_cmov_reg_long );
12518 %}
12520 // Compare 2 longs and CMOVE ints.
12521 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
12522 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12523 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12524 ins_cost(200);
12525 format %{ "CMOV$cmp $dst,$src" %}
12526 opcode(0x0F,0x40);
12527 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12528 ins_pipe( pipe_cmov_reg );
12529 %}
12531 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
12532 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12533 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12534 ins_cost(250);
12535 format %{ "CMOV$cmp $dst,$src" %}
12536 opcode(0x0F,0x40);
12537 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12538 ins_pipe( pipe_cmov_mem );
12539 %}
12541 // Compare 2 longs and CMOVE ptrs.
12542 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12543 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12544 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12545 ins_cost(200);
12546 format %{ "CMOV$cmp $dst,$src" %}
12547 opcode(0x0F,0x40);
12548 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12549 ins_pipe( pipe_cmov_reg );
12550 %}
12552 // Compare 2 longs and CMOVE doubles
12553 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12554 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12555 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12556 ins_cost(200);
12557 expand %{
12558 fcmovD_regS(cmp,flags,dst,src);
12559 %}
12560 %}
12562 // Compare 2 longs and CMOVE doubles
12563 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
12564 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12565 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12566 ins_cost(200);
12567 expand %{
12568 fcmovXD_regS(cmp,flags,dst,src);
12569 %}
12570 %}
12572 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12573 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12574 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12575 ins_cost(200);
12576 expand %{
12577 fcmovF_regS(cmp,flags,dst,src);
12578 %}
12579 %}
12582 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
12583 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12584 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12585 ins_cost(200);
12586 expand %{
12587 fcmovX_regS(cmp,flags,dst,src);
12588 %}
12589 %}
12592 // ============================================================================
12593 // Procedure Call/Return Instructions
12594 // Call Java Static Instruction
12595 // Note: If this code changes, the corresponding ret_addr_offset() and
12596 // compute_padding() functions will have to be adjusted.
12597 instruct CallStaticJavaDirect(method meth) %{
12598 match(CallStaticJava);
12599 effect(USE meth);
12601 ins_cost(300);
12602 format %{ "CALL,static " %}
12603 opcode(0xE8); /* E8 cd */
12604 ins_encode( pre_call_FPU,
12605 Java_Static_Call( meth ),
12606 call_epilog,
12607 post_call_FPU );
12608 ins_pipe( pipe_slow );
12609 ins_pc_relative(1);
12610 ins_alignment(4);
12611 %}
12613 // Call Java Dynamic Instruction
12614 // Note: If this code changes, the corresponding ret_addr_offset() and
12615 // compute_padding() functions will have to be adjusted.
12616 instruct CallDynamicJavaDirect(method meth) %{
12617 match(CallDynamicJava);
12618 effect(USE meth);
12620 ins_cost(300);
12621 format %{ "MOV EAX,(oop)-1\n\t"
12622 "CALL,dynamic" %}
12623 opcode(0xE8); /* E8 cd */
12624 ins_encode( pre_call_FPU,
12625 Java_Dynamic_Call( meth ),
12626 call_epilog,
12627 post_call_FPU );
12628 ins_pipe( pipe_slow );
12629 ins_pc_relative(1);
12630 ins_alignment(4);
12631 %}
12633 // Call Runtime Instruction
12634 instruct CallRuntimeDirect(method meth) %{
12635 match(CallRuntime );
12636 effect(USE meth);
12638 ins_cost(300);
12639 format %{ "CALL,runtime " %}
12640 opcode(0xE8); /* E8 cd */
12641 // Use FFREEs to clear entries in float stack
12642 ins_encode( pre_call_FPU,
12643 FFree_Float_Stack_All,
12644 Java_To_Runtime( meth ),
12645 post_call_FPU );
12646 ins_pipe( pipe_slow );
12647 ins_pc_relative(1);
12648 %}
12650 // Call runtime without safepoint
12651 instruct CallLeafDirect(method meth) %{
12652 match(CallLeaf);
12653 effect(USE meth);
12655 ins_cost(300);
12656 format %{ "CALL_LEAF,runtime " %}
12657 opcode(0xE8); /* E8 cd */
12658 ins_encode( pre_call_FPU,
12659 FFree_Float_Stack_All,
12660 Java_To_Runtime( meth ),
12661 Verify_FPU_For_Leaf, post_call_FPU );
12662 ins_pipe( pipe_slow );
12663 ins_pc_relative(1);
12664 %}
12666 instruct CallLeafNoFPDirect(method meth) %{
12667 match(CallLeafNoFP);
12668 effect(USE meth);
12670 ins_cost(300);
12671 format %{ "CALL_LEAF_NOFP,runtime " %}
12672 opcode(0xE8); /* E8 cd */
12673 ins_encode(Java_To_Runtime(meth));
12674 ins_pipe( pipe_slow );
12675 ins_pc_relative(1);
12676 %}
12679 // Return Instruction
12680 // Remove the return address & jump to it.
12681 instruct Ret() %{
12682 match(Return);
12683 format %{ "RET" %}
12684 opcode(0xC3);
12685 ins_encode(OpcP);
12686 ins_pipe( pipe_jmp );
12687 %}
12689 // Tail Call; Jump from runtime stub to Java code.
12690 // Also known as an 'interprocedural jump'.
12691 // Target of jump will eventually return to caller.
12692 // TailJump below removes the return address.
12693 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12694 match(TailCall jump_target method_oop );
12695 ins_cost(300);
12696 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12697 opcode(0xFF, 0x4); /* Opcode FF /4 */
12698 ins_encode( OpcP, RegOpc(jump_target) );
12699 ins_pipe( pipe_jmp );
12700 %}
12703 // Tail Jump; remove the return address; jump to target.
12704 // TailCall above leaves the return address around.
12705 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12706 match( TailJump jump_target ex_oop );
12707 ins_cost(300);
12708 format %{ "POP EDX\t# pop return address into dummy\n\t"
12709 "JMP $jump_target " %}
12710 opcode(0xFF, 0x4); /* Opcode FF /4 */
12711 ins_encode( enc_pop_rdx,
12712 OpcP, RegOpc(jump_target) );
12713 ins_pipe( pipe_jmp );
12714 %}
12716 // Create exception oop: created by stack-crawling runtime code.
12717 // Created exception is now available to this handler, and is setup
12718 // just prior to jumping to this handler. No code emitted.
12719 instruct CreateException( eAXRegP ex_oop )
12720 %{
12721 match(Set ex_oop (CreateEx));
12723 size(0);
12724 // use the following format syntax
12725 format %{ "# exception oop is in EAX; no code emitted" %}
12726 ins_encode();
12727 ins_pipe( empty );
12728 %}
12731 // Rethrow exception:
12732 // The exception oop will come in the first argument position.
12733 // Then JUMP (not call) to the rethrow stub code.
12734 instruct RethrowException()
12735 %{
12736 match(Rethrow);
12738 // use the following format syntax
12739 format %{ "JMP rethrow_stub" %}
12740 ins_encode(enc_rethrow);
12741 ins_pipe( pipe_jmp );
12742 %}
12744 // inlined locking and unlocking
12747 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
12748 match( Set cr (FastLock object box) );
12749 effect( TEMP tmp, TEMP scr );
12750 ins_cost(300);
12751 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
12752 ins_encode( Fast_Lock(object,box,tmp,scr) );
12753 ins_pipe( pipe_slow );
12754 ins_pc_relative(1);
12755 %}
12757 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12758 match( Set cr (FastUnlock object box) );
12759 effect( TEMP tmp );
12760 ins_cost(300);
12761 format %{ "FASTUNLOCK $object, $box, $tmp" %}
12762 ins_encode( Fast_Unlock(object,box,tmp) );
12763 ins_pipe( pipe_slow );
12764 ins_pc_relative(1);
12765 %}
12769 // ============================================================================
12770 // Safepoint Instruction
12771 instruct safePoint_poll(eFlagsReg cr) %{
12772 match(SafePoint);
12773 effect(KILL cr);
12775 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12776 // On SPARC that might be acceptable as we can generate the address with
12777 // just a sethi, saving an or. By polling at offset 0 we can end up
12778 // putting additional pressure on the index-0 in the D$. Because of
12779 // alignment (just like the situation at hand) the lower indices tend
12780 // to see more traffic. It'd be better to change the polling address
12781 // to offset 0 of the last $line in the polling page.
12783 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12784 ins_cost(125);
12785 size(6) ;
12786 ins_encode( Safepoint_Poll() );
12787 ins_pipe( ialu_reg_mem );
12788 %}
12790 //----------PEEPHOLE RULES-----------------------------------------------------
12791 // These must follow all instruction definitions as they use the names
12792 // defined in the instructions definitions.
12793 //
12794 // peepmatch ( root_instr_name [preceeding_instruction]* );
12795 //
12796 // peepconstraint %{
12797 // (instruction_number.operand_name relational_op instruction_number.operand_name
12798 // [, ...] );
12799 // // instruction numbers are zero-based using left to right order in peepmatch
12800 //
12801 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12802 // // provide an instruction_number.operand_name for each operand that appears
12803 // // in the replacement instruction's match rule
12804 //
12805 // ---------VM FLAGS---------------------------------------------------------
12806 //
12807 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12808 //
12809 // Each peephole rule is given an identifying number starting with zero and
12810 // increasing by one in the order seen by the parser. An individual peephole
12811 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12812 // on the command-line.
12813 //
12814 // ---------CURRENT LIMITATIONS----------------------------------------------
12815 //
12816 // Only match adjacent instructions in same basic block
12817 // Only equality constraints
12818 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12819 // Only one replacement instruction
12820 //
12821 // ---------EXAMPLE----------------------------------------------------------
12822 //
12823 // // pertinent parts of existing instructions in architecture description
12824 // instruct movI(eRegI dst, eRegI src) %{
12825 // match(Set dst (CopyI src));
12826 // %}
12827 //
12828 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12829 // match(Set dst (AddI dst src));
12830 // effect(KILL cr);
12831 // %}
12832 //
12833 // // Change (inc mov) to lea
12834 // peephole %{
12835 // // increment preceeded by register-register move
12836 // peepmatch ( incI_eReg movI );
12837 // // require that the destination register of the increment
12838 // // match the destination register of the move
12839 // peepconstraint ( 0.dst == 1.dst );
12840 // // construct a replacement instruction that sets
12841 // // the destination to ( move's source register + one )
12842 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12843 // %}
12844 //
12845 // Implementation no longer uses movX instructions since
12846 // machine-independent system no longer uses CopyX nodes.
12847 //
12848 // peephole %{
12849 // peepmatch ( incI_eReg movI );
12850 // peepconstraint ( 0.dst == 1.dst );
12851 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12852 // %}
12853 //
12854 // peephole %{
12855 // peepmatch ( decI_eReg movI );
12856 // peepconstraint ( 0.dst == 1.dst );
12857 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12858 // %}
12859 //
12860 // peephole %{
12861 // peepmatch ( addI_eReg_imm movI );
12862 // peepconstraint ( 0.dst == 1.dst );
12863 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12864 // %}
12865 //
12866 // peephole %{
12867 // peepmatch ( addP_eReg_imm movP );
12868 // peepconstraint ( 0.dst == 1.dst );
12869 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12870 // %}
12872 // // Change load of spilled value to only a spill
12873 // instruct storeI(memory mem, eRegI src) %{
12874 // match(Set mem (StoreI mem src));
12875 // %}
12876 //
12877 // instruct loadI(eRegI dst, memory mem) %{
12878 // match(Set dst (LoadI mem));
12879 // %}
12880 //
12881 peephole %{
12882 peepmatch ( loadI storeI );
12883 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12884 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12885 %}
12887 //----------SMARTSPILL RULES---------------------------------------------------
12888 // These must follow all instruction definitions as they use the names
12889 // defined in the instructions definitions.