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src/cpu/x86/vm/globals_x86.hpp@8c95980d0b66
src/cpu/x86/vm/globals_x86.hpp
Sat, 07 Nov 2020 10:30:02 +0800
- author
- aoqi
- date
- Sat, 07 Nov 2020 10:30:02 +0800
- changeset 10026
- 8c95980d0b66
- parent 9852
- 70aa912cebe5
- permissions
- -rw-r--r--
Added tag mips-jdk8u275-b01 for changeset d3b4d62f391f
1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_GLOBALS_X86_HPP
26 #define CPU_X86_VM_GLOBALS_X86_HPP
28 #include "utilities/globalDefinitions.hpp"
29 #include "utilities/macros.hpp"
31 // Sets the default values for platform dependent flags used by the runtime system.
32 // (see globals.hpp)
34 define_pd_global(bool, ConvertSleepToYield, true);
35 define_pd_global(bool, CountInterpCalls, true);
36 define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this
38 define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
39 define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86.
40 define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast
42 // See 4827828 for this change. There is no globals_core_i486.hpp. I can't
43 // assign a different value for C2 without touching a number of files. Use
44 // #ifdef to minimize the change as it's late in Mantis. -- FIXME.
45 // c1 doesn't have this problem because the fix to 4858033 assures us
46 // the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
47 // the uep and the vep doesn't get real alignment but just slops on by
48 // only assured that the entry instruction meets the 5 byte size requirement.
49 #ifdef COMPILER2
50 define_pd_global(intx, CodeEntryAlignment, 32);
51 #else
52 define_pd_global(intx, CodeEntryAlignment, 16);
53 #endif // COMPILER2
54 define_pd_global(intx, OptoLoopAlignment, 16);
55 define_pd_global(intx, InlineFrequencyCount, 100);
56 define_pd_global(intx, InlineSmallCode, 1000);
58 define_pd_global(intx, StackYellowPages, NOT_WINDOWS(2) WINDOWS_ONLY(3));
59 define_pd_global(intx, StackRedPages, 1);
60 #ifdef AMD64
61 // Very large C++ stack frames using solaris-amd64 optimized builds
62 // due to lack of optimization caused by C++ compiler bugs
63 define_pd_global(intx, StackShadowPages, NOT_WIN64(20) WIN64_ONLY(6) DEBUG_ONLY(+2));
64 #else
65 define_pd_global(intx, StackShadowPages, 4 DEBUG_ONLY(+5));
66 #endif // AMD64
68 define_pd_global(intx, PreInflateSpin, 10);
70 define_pd_global(bool, RewriteBytecodes, true);
71 define_pd_global(bool, RewriteFrequentPairs, true);
73 #ifdef _ALLBSD_SOURCE
74 define_pd_global(bool, UseMembar, true);
75 #else
76 define_pd_global(bool, UseMembar, false);
77 #endif
79 // GC Ergo Flags
80 define_pd_global(uintx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread
82 define_pd_global(uintx, TypeProfileLevel, 111);
84 define_pd_global(bool, PreserveFramePointer, false);
86 #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \
87 \
88 develop(bool, IEEEPrecision, true, \
89 "Enables IEEE precision (for INTEL only)") \
90 \
91 product(intx, FenceInstruction, 0, \
92 "(Unsafe,Unstable) Experimental") \
93 \
94 product(intx, ReadPrefetchInstr, 0, \
95 "Prefetch instruction to prefetch ahead") \
96 \
97 product(bool, UseStoreImmI16, true, \
98 "Use store immediate 16-bits value instruction on x86") \
99 \
100 product(intx, UseAVX, 99, \
101 "Highest supported AVX instructions set on x86/x64") \
102 \
103 product(bool, UseCLMUL, false, \
104 "Control whether CLMUL instructions can be used on x86/x64") \
105 \
106 diagnostic(bool, UseIncDec, true, \
107 "Use INC, DEC instructions on x86") \
108 \
109 product(bool, UseNewLongLShift, false, \
110 "Use optimized bitwise shift left") \
111 \
112 product(bool, UseAddressNop, false, \
113 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \
114 \
115 product(bool, UseXmmLoadAndClearUpper, true, \
116 "Load low part of XMM register and clear upper part") \
117 \
118 product(bool, UseXmmRegToRegMoveAll, false, \
119 "Copy all XMM register bits when moving value between registers") \
120 \
121 product(bool, UseXmmI2D, false, \
122 "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \
123 \
124 product(bool, UseXmmI2F, false, \
125 "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \
126 \
127 product(bool, UseUnalignedLoadStores, false, \
128 "Use SSE2 MOVDQU instruction for Arraycopy") \
129 \
130 product(bool, UseFastStosb, false, \
131 "Use fast-string operation for zeroing: rep stosb") \
132 \
133 /* Use Restricted Transactional Memory for lock eliding */ \
134 product(bool, UseRTMLocking, false, \
135 "Enable RTM lock eliding for inflated locks in compiled code") \
136 \
137 experimental(bool, UseRTMForStackLocks, false, \
138 "Enable RTM lock eliding for stack locks in compiled code") \
139 \
140 product(bool, UseRTMDeopt, false, \
141 "Perform deopt and recompilation based on RTM abort ratio") \
142 \
143 product(uintx, RTMRetryCount, 5, \
144 "Number of RTM retries on lock abort or busy") \
145 \
146 experimental(intx, RTMSpinLoopCount, 100, \
147 "Spin count for lock to become free before RTM retry") \
148 \
149 experimental(intx, RTMAbortThreshold, 1000, \
150 "Calculate abort ratio after this number of aborts") \
151 \
152 experimental(intx, RTMLockingThreshold, 10000, \
153 "Lock count at which to do RTM lock eliding without " \
154 "abort ratio calculation") \
155 \
156 experimental(intx, RTMAbortRatio, 50, \
157 "Lock abort ratio at which to stop use RTM lock eliding") \
158 \
159 experimental(intx, RTMTotalCountIncrRate, 64, \
160 "Increment total RTM attempted lock count once every n times") \
161 \
162 experimental(intx, RTMLockingCalculationDelay, 0, \
163 "Number of milliseconds to wait before start calculating aborts " \
164 "for RTM locking") \
165 \
166 experimental(bool, UseRTMXendForLockBusy, true, \
167 "Use RTM Xend instead of Xabort when lock busy") \
168 \
169 /* assembler */ \
170 product(bool, Use486InstrsOnly, false, \
171 "Use 80486 Compliant instruction subset") \
172 \
173 product(bool, UseCountLeadingZerosInstruction, false, \
174 "Use count leading zeros instruction") \
175 \
176 product(bool, UseCountTrailingZerosInstruction, false, \
177 "Use count trailing zeros instruction") \
178 \
179 product(bool, UseBMI1Instructions, false, \
180 "Use BMI1 instructions") \
181 \
182 product(bool, UseBMI2Instructions, false, \
183 "Use BMI2 instructions")
184 #endif // CPU_X86_VM_GLOBALS_X86_HPP
