Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/x86/vm/vm_version_x86.cpp@8a8ff6b577ed
src/cpu/x86/vm/vm_version_x86.cpp
Wed, 12 Mar 2014 11:24:26 -0700
- author
- iveresov
- date
- Wed, 12 Mar 2014 11:24:26 -0700
- changeset 6378
- 8a8ff6b577ed
- parent 5353
- b800986664f4
- child 6388
- 98af1e198e73
- permissions
- -rw-r--r--
8031321: Support Intel bit manipulation instructions
Summary: Add support for BMI1 instructions
Reviewed-by: kvn, roland
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/stubCodeGenerator.hpp"
31 #include "vm_version_x86.hpp"
32 #ifdef TARGET_OS_FAMILY_linux
33 # include "os_linux.inline.hpp"
34 #endif
35 #ifdef TARGET_OS_FAMILY_solaris
36 # include "os_solaris.inline.hpp"
37 #endif
38 #ifdef TARGET_OS_FAMILY_windows
39 # include "os_windows.inline.hpp"
40 #endif
41 #ifdef TARGET_OS_FAMILY_bsd
42 # include "os_bsd.inline.hpp"
43 #endif
46 int VM_Version::_cpu;
47 int VM_Version::_model;
48 int VM_Version::_stepping;
49 int VM_Version::_cpuFeatures;
50 const char* VM_Version::_features_str = "";
51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
53 static BufferBlob* stub_blob;
54 static const int stub_size = 550;
56 extern "C" {
57 typedef void (*getPsrInfo_stub_t)(void*);
58 }
59 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
62 class VM_Version_StubGenerator: public StubCodeGenerator {
63 public:
65 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
67 address generate_getPsrInfo() {
68 // Flags to test CPU type.
69 const uint32_t HS_EFL_AC = 0x40000;
70 const uint32_t HS_EFL_ID = 0x200000;
71 // Values for when we don't have a CPUID instruction.
72 const int CPU_FAMILY_SHIFT = 8;
73 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
74 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
76 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
77 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
79 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
80 # define __ _masm->
82 address start = __ pc();
84 //
85 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
86 //
87 // LP64: rcx and rdx are first and second argument registers on windows
89 __ push(rbp);
90 #ifdef _LP64
91 __ mov(rbp, c_rarg0); // cpuid_info address
92 #else
93 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
94 #endif
95 __ push(rbx);
96 __ push(rsi);
97 __ pushf(); // preserve rbx, and flags
98 __ pop(rax);
99 __ push(rax);
100 __ mov(rcx, rax);
101 //
102 // if we are unable to change the AC flag, we have a 386
103 //
104 __ xorl(rax, HS_EFL_AC);
105 __ push(rax);
106 __ popf();
107 __ pushf();
108 __ pop(rax);
109 __ cmpptr(rax, rcx);
110 __ jccb(Assembler::notEqual, detect_486);
112 __ movl(rax, CPU_FAMILY_386);
113 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
114 __ jmp(done);
116 //
117 // If we are unable to change the ID flag, we have a 486 which does
118 // not support the "cpuid" instruction.
119 //
120 __ bind(detect_486);
121 __ mov(rax, rcx);
122 __ xorl(rax, HS_EFL_ID);
123 __ push(rax);
124 __ popf();
125 __ pushf();
126 __ pop(rax);
127 __ cmpptr(rcx, rax);
128 __ jccb(Assembler::notEqual, detect_586);
130 __ bind(cpu486);
131 __ movl(rax, CPU_FAMILY_486);
132 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
133 __ jmp(done);
135 //
136 // At this point, we have a chip which supports the "cpuid" instruction
137 //
138 __ bind(detect_586);
139 __ xorl(rax, rax);
140 __ cpuid();
141 __ orl(rax, rax);
142 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
143 // value of at least 1, we give up and
144 // assume a 486
145 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
146 __ movl(Address(rsi, 0), rax);
147 __ movl(Address(rsi, 4), rbx);
148 __ movl(Address(rsi, 8), rcx);
149 __ movl(Address(rsi,12), rdx);
151 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
152 __ jccb(Assembler::belowEqual, std_cpuid4);
154 //
155 // cpuid(0xB) Processor Topology
156 //
157 __ movl(rax, 0xb);
158 __ xorl(rcx, rcx); // Threads level
159 __ cpuid();
161 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
162 __ movl(Address(rsi, 0), rax);
163 __ movl(Address(rsi, 4), rbx);
164 __ movl(Address(rsi, 8), rcx);
165 __ movl(Address(rsi,12), rdx);
167 __ movl(rax, 0xb);
168 __ movl(rcx, 1); // Cores level
169 __ cpuid();
170 __ push(rax);
171 __ andl(rax, 0x1f); // Determine if valid topology level
172 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
173 __ andl(rax, 0xffff);
174 __ pop(rax);
175 __ jccb(Assembler::equal, std_cpuid4);
177 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
178 __ movl(Address(rsi, 0), rax);
179 __ movl(Address(rsi, 4), rbx);
180 __ movl(Address(rsi, 8), rcx);
181 __ movl(Address(rsi,12), rdx);
183 __ movl(rax, 0xb);
184 __ movl(rcx, 2); // Packages level
185 __ cpuid();
186 __ push(rax);
187 __ andl(rax, 0x1f); // Determine if valid topology level
188 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
189 __ andl(rax, 0xffff);
190 __ pop(rax);
191 __ jccb(Assembler::equal, std_cpuid4);
193 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
194 __ movl(Address(rsi, 0), rax);
195 __ movl(Address(rsi, 4), rbx);
196 __ movl(Address(rsi, 8), rcx);
197 __ movl(Address(rsi,12), rdx);
199 //
200 // cpuid(0x4) Deterministic cache params
201 //
202 __ bind(std_cpuid4);
203 __ movl(rax, 4);
204 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
205 __ jccb(Assembler::greater, std_cpuid1);
207 __ xorl(rcx, rcx); // L1 cache
208 __ cpuid();
209 __ push(rax);
210 __ andl(rax, 0x1f); // Determine if valid cache parameters used
211 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
212 __ pop(rax);
213 __ jccb(Assembler::equal, std_cpuid1);
215 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
216 __ movl(Address(rsi, 0), rax);
217 __ movl(Address(rsi, 4), rbx);
218 __ movl(Address(rsi, 8), rcx);
219 __ movl(Address(rsi,12), rdx);
221 //
222 // Standard cpuid(0x1)
223 //
224 __ bind(std_cpuid1);
225 __ movl(rax, 1);
226 __ cpuid();
227 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
228 __ movl(Address(rsi, 0), rax);
229 __ movl(Address(rsi, 4), rbx);
230 __ movl(Address(rsi, 8), rcx);
231 __ movl(Address(rsi,12), rdx);
233 //
234 // Check if OS has enabled XGETBV instruction to access XCR0
235 // (OSXSAVE feature flag) and CPU supports AVX
236 //
237 __ andl(rcx, 0x18000000);
238 __ cmpl(rcx, 0x18000000);
239 __ jccb(Assembler::notEqual, sef_cpuid);
241 //
242 // XCR0, XFEATURE_ENABLED_MASK register
243 //
244 __ xorl(rcx, rcx); // zero for XCR0 register
245 __ xgetbv();
246 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
247 __ movl(Address(rsi, 0), rax);
248 __ movl(Address(rsi, 4), rdx);
250 //
251 // cpuid(0x7) Structured Extended Features
252 //
253 __ bind(sef_cpuid);
254 __ movl(rax, 7);
255 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
256 __ jccb(Assembler::greater, ext_cpuid);
258 __ xorl(rcx, rcx);
259 __ cpuid();
260 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
261 __ movl(Address(rsi, 0), rax);
262 __ movl(Address(rsi, 4), rbx);
264 //
265 // Extended cpuid(0x80000000)
266 //
267 __ bind(ext_cpuid);
268 __ movl(rax, 0x80000000);
269 __ cpuid();
270 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
271 __ jcc(Assembler::belowEqual, done);
272 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
273 __ jccb(Assembler::belowEqual, ext_cpuid1);
274 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
275 __ jccb(Assembler::belowEqual, ext_cpuid5);
276 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
277 __ jccb(Assembler::belowEqual, ext_cpuid7);
278 //
279 // Extended cpuid(0x80000008)
280 //
281 __ movl(rax, 0x80000008);
282 __ cpuid();
283 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
284 __ movl(Address(rsi, 0), rax);
285 __ movl(Address(rsi, 4), rbx);
286 __ movl(Address(rsi, 8), rcx);
287 __ movl(Address(rsi,12), rdx);
289 //
290 // Extended cpuid(0x80000007)
291 //
292 __ bind(ext_cpuid7);
293 __ movl(rax, 0x80000007);
294 __ cpuid();
295 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
296 __ movl(Address(rsi, 0), rax);
297 __ movl(Address(rsi, 4), rbx);
298 __ movl(Address(rsi, 8), rcx);
299 __ movl(Address(rsi,12), rdx);
301 //
302 // Extended cpuid(0x80000005)
303 //
304 __ bind(ext_cpuid5);
305 __ movl(rax, 0x80000005);
306 __ cpuid();
307 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
308 __ movl(Address(rsi, 0), rax);
309 __ movl(Address(rsi, 4), rbx);
310 __ movl(Address(rsi, 8), rcx);
311 __ movl(Address(rsi,12), rdx);
313 //
314 // Extended cpuid(0x80000001)
315 //
316 __ bind(ext_cpuid1);
317 __ movl(rax, 0x80000001);
318 __ cpuid();
319 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
320 __ movl(Address(rsi, 0), rax);
321 __ movl(Address(rsi, 4), rbx);
322 __ movl(Address(rsi, 8), rcx);
323 __ movl(Address(rsi,12), rdx);
325 //
326 // return
327 //
328 __ bind(done);
329 __ popf();
330 __ pop(rsi);
331 __ pop(rbx);
332 __ pop(rbp);
333 __ ret(0);
335 # undef __
337 return start;
338 };
339 };
342 void VM_Version::get_processor_features() {
344 _cpu = 4; // 486 by default
345 _model = 0;
346 _stepping = 0;
347 _cpuFeatures = 0;
348 _logical_processors_per_package = 1;
350 if (!Use486InstrsOnly) {
351 // Get raw processor info
352 getPsrInfo_stub(&_cpuid_info);
353 assert_is_initialized();
354 _cpu = extended_cpu_family();
355 _model = extended_cpu_model();
356 _stepping = cpu_stepping();
358 if (cpu_family() > 4) { // it supports CPUID
359 _cpuFeatures = feature_flags();
360 // Logical processors are only available on P4s and above,
361 // and only if hyperthreading is available.
362 _logical_processors_per_package = logical_processor_count();
363 }
364 }
366 _supports_cx8 = supports_cmpxchg8();
367 // xchg and xadd instructions
368 _supports_atomic_getset4 = true;
369 _supports_atomic_getadd4 = true;
370 LP64_ONLY(_supports_atomic_getset8 = true);
371 LP64_ONLY(_supports_atomic_getadd8 = true);
373 #ifdef _LP64
374 // OS should support SSE for x64 and hardware should support at least SSE2.
375 if (!VM_Version::supports_sse2()) {
376 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
377 }
378 // in 64 bit the use of SSE2 is the minimum
379 if (UseSSE < 2) UseSSE = 2;
380 #endif
382 #ifdef AMD64
383 // flush_icache_stub have to be generated first.
384 // That is why Icache line size is hard coded in ICache class,
385 // see icache_x86.hpp. It is also the reason why we can't use
386 // clflush instruction in 32-bit VM since it could be running
387 // on CPU which does not support it.
388 //
389 // The only thing we can do is to verify that flushed
390 // ICache::line_size has correct value.
391 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
392 // clflush_size is size in quadwords (8 bytes).
393 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
394 #endif
396 // If the OS doesn't support SSE, we can't use this feature even if the HW does
397 if (!os::supports_sse())
398 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
400 if (UseSSE < 4) {
401 _cpuFeatures &= ~CPU_SSE4_1;
402 _cpuFeatures &= ~CPU_SSE4_2;
403 }
405 if (UseSSE < 3) {
406 _cpuFeatures &= ~CPU_SSE3;
407 _cpuFeatures &= ~CPU_SSSE3;
408 _cpuFeatures &= ~CPU_SSE4A;
409 }
411 if (UseSSE < 2)
412 _cpuFeatures &= ~CPU_SSE2;
414 if (UseSSE < 1)
415 _cpuFeatures &= ~CPU_SSE;
417 if (UseAVX < 2)
418 _cpuFeatures &= ~CPU_AVX2;
420 if (UseAVX < 1)
421 _cpuFeatures &= ~CPU_AVX;
423 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
424 _cpuFeatures &= ~CPU_AES;
426 if (logical_processors_per_package() == 1) {
427 // HT processor could be installed on a system which doesn't support HT.
428 _cpuFeatures &= ~CPU_HT;
429 }
431 char buf[256];
432 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
433 cores_per_cpu(), threads_per_core(),
434 cpu_family(), _model, _stepping,
435 (supports_cmov() ? ", cmov" : ""),
436 (supports_cmpxchg8() ? ", cx8" : ""),
437 (supports_fxsr() ? ", fxsr" : ""),
438 (supports_mmx() ? ", mmx" : ""),
439 (supports_sse() ? ", sse" : ""),
440 (supports_sse2() ? ", sse2" : ""),
441 (supports_sse3() ? ", sse3" : ""),
442 (supports_ssse3()? ", ssse3": ""),
443 (supports_sse4_1() ? ", sse4.1" : ""),
444 (supports_sse4_2() ? ", sse4.2" : ""),
445 (supports_popcnt() ? ", popcnt" : ""),
446 (supports_avx() ? ", avx" : ""),
447 (supports_avx2() ? ", avx2" : ""),
448 (supports_aes() ? ", aes" : ""),
449 (supports_clmul() ? ", clmul" : ""),
450 (supports_erms() ? ", erms" : ""),
451 (supports_mmx_ext() ? ", mmxext" : ""),
452 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
453 (supports_lzcnt() ? ", lzcnt": ""),
454 (supports_sse4a() ? ", sse4a": ""),
455 (supports_ht() ? ", ht": ""),
456 (supports_tsc() ? ", tsc": ""),
457 (supports_tscinv_bit() ? ", tscinvbit": ""),
458 (supports_tscinv() ? ", tscinv": ""),
459 (supports_bmi1() ? ", bmi1" : ""),
460 (supports_bmi2() ? ", bmi2" : ""));
461 _features_str = strdup(buf);
463 // UseSSE is set to the smaller of what hardware supports and what
464 // the command line requires. I.e., you cannot set UseSSE to 2 on
465 // older Pentiums which do not support it.
466 if (UseSSE > 4) UseSSE=4;
467 if (UseSSE < 0) UseSSE=0;
468 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
469 UseSSE = MIN2((intx)3,UseSSE);
470 if (!supports_sse3()) // Drop to 2 if no SSE3 support
471 UseSSE = MIN2((intx)2,UseSSE);
472 if (!supports_sse2()) // Drop to 1 if no SSE2 support
473 UseSSE = MIN2((intx)1,UseSSE);
474 if (!supports_sse ()) // Drop to 0 if no SSE support
475 UseSSE = 0;
477 if (UseAVX > 2) UseAVX=2;
478 if (UseAVX < 0) UseAVX=0;
479 if (!supports_avx2()) // Drop to 1 if no AVX2 support
480 UseAVX = MIN2((intx)1,UseAVX);
481 if (!supports_avx ()) // Drop to 0 if no AVX support
482 UseAVX = 0;
484 // Use AES instructions if available.
485 if (supports_aes()) {
486 if (FLAG_IS_DEFAULT(UseAES)) {
487 UseAES = true;
488 }
489 } else if (UseAES) {
490 if (!FLAG_IS_DEFAULT(UseAES))
491 warning("AES instructions not available on this CPU");
492 FLAG_SET_DEFAULT(UseAES, false);
493 }
495 // Use CLMUL instructions if available.
496 if (supports_clmul()) {
497 if (FLAG_IS_DEFAULT(UseCLMUL)) {
498 UseCLMUL = true;
499 }
500 } else if (UseCLMUL) {
501 if (!FLAG_IS_DEFAULT(UseCLMUL))
502 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
503 FLAG_SET_DEFAULT(UseCLMUL, false);
504 }
506 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) {
507 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
508 UseCRC32Intrinsics = true;
509 }
510 } else if (UseCRC32Intrinsics) {
511 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
512 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
513 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
514 }
516 // The AES intrinsic stubs require AES instruction support (of course)
517 // but also require sse3 mode for instructions it use.
518 if (UseAES && (UseSSE > 2)) {
519 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
520 UseAESIntrinsics = true;
521 }
522 } else if (UseAESIntrinsics) {
523 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
524 warning("AES intrinsics not available on this CPU");
525 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
526 }
528 #ifdef COMPILER2
529 if (UseFPUForSpilling) {
530 if (UseSSE < 2) {
531 // Only supported with SSE2+
532 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
533 }
534 }
535 if (MaxVectorSize > 0) {
536 if (!is_power_of_2(MaxVectorSize)) {
537 warning("MaxVectorSize must be a power of 2");
538 FLAG_SET_DEFAULT(MaxVectorSize, 32);
539 }
540 if (MaxVectorSize > 32) {
541 FLAG_SET_DEFAULT(MaxVectorSize, 32);
542 }
543 if (MaxVectorSize > 16 && UseAVX == 0) {
544 // Only supported with AVX+
545 FLAG_SET_DEFAULT(MaxVectorSize, 16);
546 }
547 if (UseSSE < 2) {
548 // Only supported with SSE2+
549 FLAG_SET_DEFAULT(MaxVectorSize, 0);
550 }
551 }
552 #endif
554 // On new cpus instructions which update whole XMM register should be used
555 // to prevent partial register stall due to dependencies on high half.
556 //
557 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
558 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
559 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
560 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
562 if( is_amd() ) { // AMD cpus specific settings
563 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
564 // Use it on new AMD cpus starting from Opteron.
565 UseAddressNop = true;
566 }
567 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
568 // Use it on new AMD cpus starting from Opteron.
569 UseNewLongLShift = true;
570 }
571 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
572 if( supports_sse4a() ) {
573 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
574 } else {
575 UseXmmLoadAndClearUpper = false;
576 }
577 }
578 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
579 if( supports_sse4a() ) {
580 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
581 } else {
582 UseXmmRegToRegMoveAll = false;
583 }
584 }
585 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
586 if( supports_sse4a() ) {
587 UseXmmI2F = true;
588 } else {
589 UseXmmI2F = false;
590 }
591 }
592 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
593 if( supports_sse4a() ) {
594 UseXmmI2D = true;
595 } else {
596 UseXmmI2D = false;
597 }
598 }
599 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
600 if( supports_sse4_2() && UseSSE >= 4 ) {
601 UseSSE42Intrinsics = true;
602 }
603 }
605 // some defaults for AMD family 15h
606 if ( cpu_family() == 0x15 ) {
607 // On family 15h processors default is no sw prefetch
608 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
609 AllocatePrefetchStyle = 0;
610 }
611 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
612 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
613 AllocatePrefetchInstr = 3;
614 }
615 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
616 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
617 UseXMMForArrayCopy = true;
618 }
619 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
620 UseUnalignedLoadStores = true;
621 }
622 }
624 #ifdef COMPILER2
625 if (MaxVectorSize > 16) {
626 // Limit vectors size to 16 bytes on current AMD cpus.
627 FLAG_SET_DEFAULT(MaxVectorSize, 16);
628 }
629 #endif // COMPILER2
630 }
632 if( is_intel() ) { // Intel cpus specific settings
633 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
634 UseStoreImmI16 = false; // don't use it on Intel cpus
635 }
636 if( cpu_family() == 6 || cpu_family() == 15 ) {
637 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
638 // Use it on all Intel cpus starting from PentiumPro
639 UseAddressNop = true;
640 }
641 }
642 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
643 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
644 }
645 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
646 if( supports_sse3() ) {
647 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
648 } else {
649 UseXmmRegToRegMoveAll = false;
650 }
651 }
652 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
653 #ifdef COMPILER2
654 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
655 // For new Intel cpus do the next optimization:
656 // don't align the beginning of a loop if there are enough instructions
657 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
658 // in current fetch line (OptoLoopAlignment) or the padding
659 // is big (> MaxLoopPad).
660 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
661 // generated NOP instructions. 11 is the largest size of one
662 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
663 MaxLoopPad = 11;
664 }
665 #endif // COMPILER2
666 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
667 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
668 }
669 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
670 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
671 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
672 }
673 }
674 if (supports_sse4_2() && UseSSE >= 4) {
675 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
676 UseSSE42Intrinsics = true;
677 }
678 }
679 }
680 }
681 #if defined(COMPILER2) && defined(_ALLBSD_SOURCE)
682 if (MaxVectorSize > 16) {
683 // Limit vectors size to 16 bytes on BSD until it fixes
684 // restoring upper 128bit of YMM registers on return
685 // from signal handler.
686 FLAG_SET_DEFAULT(MaxVectorSize, 16);
687 }
688 #endif // COMPILER2
690 // Use count leading zeros count instruction if available.
691 if (supports_lzcnt()) {
692 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
693 UseCountLeadingZerosInstruction = true;
694 }
695 } else if (UseCountLeadingZerosInstruction) {
696 warning("lzcnt instruction is not available on this CPU");
697 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
698 }
700 if (supports_bmi1()) {
701 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
702 UseBMI1Instructions = true;
703 }
704 } else if (UseBMI1Instructions) {
705 warning("BMI1 instructions are not available on this CPU");
706 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
707 }
709 // Use count trailing zeros instruction if available
710 if (supports_bmi1()) {
711 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
712 UseCountTrailingZerosInstruction = UseBMI1Instructions;
713 }
714 } else if (UseCountTrailingZerosInstruction) {
715 warning("tzcnt instruction is not available on this CPU");
716 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
717 }
719 // Use population count instruction if available.
720 if (supports_popcnt()) {
721 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
722 UsePopCountInstruction = true;
723 }
724 } else if (UsePopCountInstruction) {
725 warning("POPCNT instruction is not available on this CPU");
726 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
727 }
729 // Use fast-string operations if available.
730 if (supports_erms()) {
731 if (FLAG_IS_DEFAULT(UseFastStosb)) {
732 UseFastStosb = true;
733 }
734 } else if (UseFastStosb) {
735 warning("fast-string operations are not available on this CPU");
736 FLAG_SET_DEFAULT(UseFastStosb, false);
737 }
739 #ifdef COMPILER2
740 if (FLAG_IS_DEFAULT(AlignVector)) {
741 // Modern processors allow misaligned memory operations for vectors.
742 AlignVector = !UseUnalignedLoadStores;
743 }
744 #endif // COMPILER2
746 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
747 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
749 // set valid Prefetch instruction
750 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
751 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
752 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
753 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
755 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
756 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
757 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
758 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
760 // Allocation prefetch settings
761 intx cache_line_size = prefetch_data_size();
762 if( cache_line_size > AllocatePrefetchStepSize )
763 AllocatePrefetchStepSize = cache_line_size;
765 assert(AllocatePrefetchLines > 0, "invalid value");
766 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
767 AllocatePrefetchLines = 3;
768 assert(AllocateInstancePrefetchLines > 0, "invalid value");
769 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
770 AllocateInstancePrefetchLines = 1;
772 AllocatePrefetchDistance = allocate_prefetch_distance();
773 AllocatePrefetchStyle = allocate_prefetch_style();
775 if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
776 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
777 #ifdef _LP64
778 AllocatePrefetchDistance = 384;
779 #else
780 AllocatePrefetchDistance = 320;
781 #endif
782 }
783 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
784 AllocatePrefetchDistance = 192;
785 AllocatePrefetchLines = 4;
786 #ifdef COMPILER2
787 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
788 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
789 }
790 #endif
791 }
792 }
793 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
795 #ifdef _LP64
796 // Prefetch settings
797 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
798 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
799 PrefetchFieldsAhead = prefetch_fields_ahead();
800 #endif
802 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
803 (cache_line_size > ContendedPaddingWidth))
804 ContendedPaddingWidth = cache_line_size;
806 #ifndef PRODUCT
807 if (PrintMiscellaneous && Verbose) {
808 tty->print_cr("Logical CPUs per core: %u",
809 logical_processors_per_package());
810 tty->print("UseSSE=%d",UseSSE);
811 if (UseAVX > 0) {
812 tty->print(" UseAVX=%d",UseAVX);
813 }
814 if (UseAES) {
815 tty->print(" UseAES=1");
816 }
817 tty->cr();
818 tty->print("Allocation");
819 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
820 tty->print_cr(": no prefetching");
821 } else {
822 tty->print(" prefetching: ");
823 if (UseSSE == 0 && supports_3dnow_prefetch()) {
824 tty->print("PREFETCHW");
825 } else if (UseSSE >= 1) {
826 if (AllocatePrefetchInstr == 0) {
827 tty->print("PREFETCHNTA");
828 } else if (AllocatePrefetchInstr == 1) {
829 tty->print("PREFETCHT0");
830 } else if (AllocatePrefetchInstr == 2) {
831 tty->print("PREFETCHT2");
832 } else if (AllocatePrefetchInstr == 3) {
833 tty->print("PREFETCHW");
834 }
835 }
836 if (AllocatePrefetchLines > 1) {
837 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
838 } else {
839 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
840 }
841 }
843 if (PrefetchCopyIntervalInBytes > 0) {
844 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
845 }
846 if (PrefetchScanIntervalInBytes > 0) {
847 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
848 }
849 if (PrefetchFieldsAhead > 0) {
850 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
851 }
852 if (ContendedPaddingWidth > 0) {
853 tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth);
854 }
855 }
856 #endif // !PRODUCT
857 }
859 void VM_Version::initialize() {
860 ResourceMark rm;
861 // Making this stub must be FIRST use of assembler
863 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
864 if (stub_blob == NULL) {
865 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
866 }
867 CodeBuffer c(stub_blob);
868 VM_Version_StubGenerator g(&c);
869 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
870 g.generate_getPsrInfo());
872 get_processor_features();
873 }
