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src/share/vm/c1/c1_LIR.cpp@87b64980e2f1
src/share/vm/c1/c1_LIR.cpp
Wed, 22 Sep 2010 21:10:46 -0700
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- never
- date
- Wed, 22 Sep 2010 21:10:46 -0700
- changeset 2171
- 87b64980e2f1
- parent 2146
- 3a294e483abc
- child 2174
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6972540: sun/nio/ch/SocketChannelImpl compilation crashed when executing CompileTheWorld
Reviewed-by: kvn
1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIR.cpp.incl"
28 Register LIR_OprDesc::as_register() const {
29 return FrameMap::cpu_rnr2reg(cpu_regnr());
30 }
32 Register LIR_OprDesc::as_register_lo() const {
33 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
34 }
36 Register LIR_OprDesc::as_register_hi() const {
37 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
38 }
40 #if defined(X86)
42 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
43 return FrameMap::nr2xmmreg(xmm_regnr());
44 }
46 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
47 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
48 return FrameMap::nr2xmmreg(xmm_regnrLo());
49 }
51 #endif // X86
53 #if defined(SPARC) || defined(PPC)
55 FloatRegister LIR_OprDesc::as_float_reg() const {
56 return FrameMap::nr2floatreg(fpu_regnr());
57 }
59 FloatRegister LIR_OprDesc::as_double_reg() const {
60 return FrameMap::nr2floatreg(fpu_regnrHi());
61 }
63 #endif
65 #ifdef ARM
67 FloatRegister LIR_OprDesc::as_float_reg() const {
68 return as_FloatRegister(fpu_regnr());
69 }
71 FloatRegister LIR_OprDesc::as_double_reg() const {
72 return as_FloatRegister(fpu_regnrLo());
73 }
75 #endif
78 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
80 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
81 ValueTag tag = type->tag();
82 switch (tag) {
83 case objectTag : {
84 ClassConstant* c = type->as_ClassConstant();
85 if (c != NULL && !c->value()->is_loaded()) {
86 return LIR_OprFact::oopConst(NULL);
87 } else {
88 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
89 }
90 }
91 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
92 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
93 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
94 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
95 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
96 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
97 }
98 }
101 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
102 switch (type->tag()) {
103 case objectTag: return LIR_OprFact::oopConst(NULL);
104 case addressTag:return LIR_OprFact::addressConst(0);
105 case intTag: return LIR_OprFact::intConst(0);
106 case floatTag: return LIR_OprFact::floatConst(0.0);
107 case longTag: return LIR_OprFact::longConst(0);
108 case doubleTag: return LIR_OprFact::doubleConst(0.0);
109 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
110 }
111 return illegalOpr;
112 }
116 //---------------------------------------------------
119 LIR_Address::Scale LIR_Address::scale(BasicType type) {
120 int elem_size = type2aelembytes(type);
121 switch (elem_size) {
122 case 1: return LIR_Address::times_1;
123 case 2: return LIR_Address::times_2;
124 case 4: return LIR_Address::times_4;
125 case 8: return LIR_Address::times_8;
126 }
127 ShouldNotReachHere();
128 return LIR_Address::times_1;
129 }
132 #ifndef PRODUCT
133 void LIR_Address::verify() const {
134 #if defined(SPARC) || defined(PPC)
135 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
136 assert(disp() == 0 || index()->is_illegal(), "can't have both");
137 #endif
138 #ifdef ARM
139 assert(disp() == 0 || index()->is_illegal(), "can't have both");
140 assert(-4096 < disp() && disp() < 4096, "architecture constraint");
141 #endif
142 #ifdef _LP64
143 assert(base()->is_cpu_register(), "wrong base operand");
144 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
145 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
146 "wrong type for addresses");
147 #else
148 assert(base()->is_single_cpu(), "wrong base operand");
149 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
150 assert(base()->type() == T_OBJECT || base()->type() == T_INT,
151 "wrong type for addresses");
152 #endif
153 }
154 #endif
157 //---------------------------------------------------
159 char LIR_OprDesc::type_char(BasicType t) {
160 switch (t) {
161 case T_ARRAY:
162 t = T_OBJECT;
163 case T_BOOLEAN:
164 case T_CHAR:
165 case T_FLOAT:
166 case T_DOUBLE:
167 case T_BYTE:
168 case T_SHORT:
169 case T_INT:
170 case T_LONG:
171 case T_OBJECT:
172 case T_ADDRESS:
173 case T_VOID:
174 return ::type2char(t);
176 case T_ILLEGAL:
177 return '?';
179 default:
180 ShouldNotReachHere();
181 return '?';
182 }
183 }
185 #ifndef PRODUCT
186 void LIR_OprDesc::validate_type() const {
188 #ifdef ASSERT
189 if (!is_pointer() && !is_illegal()) {
190 switch (as_BasicType(type_field())) {
191 case T_LONG:
192 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
193 size_field() == double_size, "must match");
194 break;
195 case T_FLOAT:
196 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
197 assert((kind_field() == fpu_register || kind_field() == stack_value
198 ARM_ONLY(|| kind_field() == cpu_register)
199 PPC_ONLY(|| kind_field() == cpu_register) ) &&
200 size_field() == single_size, "must match");
201 break;
202 case T_DOUBLE:
203 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
204 assert((kind_field() == fpu_register || kind_field() == stack_value
205 ARM_ONLY(|| kind_field() == cpu_register)
206 PPC_ONLY(|| kind_field() == cpu_register) ) &&
207 size_field() == double_size, "must match");
208 break;
209 case T_BOOLEAN:
210 case T_CHAR:
211 case T_BYTE:
212 case T_SHORT:
213 case T_INT:
214 case T_ADDRESS:
215 case T_OBJECT:
216 case T_ARRAY:
217 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
218 size_field() == single_size, "must match");
219 break;
221 case T_ILLEGAL:
222 // XXX TKR also means unknown right now
223 // assert(is_illegal(), "must match");
224 break;
226 default:
227 ShouldNotReachHere();
228 }
229 }
230 #endif
232 }
233 #endif // PRODUCT
236 bool LIR_OprDesc::is_oop() const {
237 if (is_pointer()) {
238 return pointer()->is_oop_pointer();
239 } else {
240 OprType t= type_field();
241 assert(t != unknown_type, "not set");
242 return t == object_type;
243 }
244 }
248 void LIR_Op2::verify() const {
249 #ifdef ASSERT
250 switch (code()) {
251 case lir_cmove:
252 break;
254 default:
255 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
256 "can't produce oops from arith");
257 }
259 if (TwoOperandLIRForm) {
260 switch (code()) {
261 case lir_add:
262 case lir_sub:
263 case lir_mul:
264 case lir_mul_strictfp:
265 case lir_div:
266 case lir_div_strictfp:
267 case lir_rem:
268 case lir_logic_and:
269 case lir_logic_or:
270 case lir_logic_xor:
271 case lir_shl:
272 case lir_shr:
273 assert(in_opr1() == result_opr(), "opr1 and result must match");
274 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
275 break;
277 // special handling for lir_ushr because of write barriers
278 case lir_ushr:
279 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
280 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
281 break;
283 }
284 }
285 #endif
286 }
289 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
290 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
291 , _cond(cond)
292 , _type(type)
293 , _label(block->label())
294 , _block(block)
295 , _ublock(NULL)
296 , _stub(NULL) {
297 }
299 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
300 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
301 , _cond(cond)
302 , _type(type)
303 , _label(stub->entry())
304 , _block(NULL)
305 , _ublock(NULL)
306 , _stub(stub) {
307 }
309 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
310 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
311 , _cond(cond)
312 , _type(type)
313 , _label(block->label())
314 , _block(block)
315 , _ublock(ublock)
316 , _stub(NULL)
317 {
318 }
320 void LIR_OpBranch::change_block(BlockBegin* b) {
321 assert(_block != NULL, "must have old block");
322 assert(_block->label() == label(), "must be equal");
324 _block = b;
325 _label = b->label();
326 }
328 void LIR_OpBranch::change_ublock(BlockBegin* b) {
329 assert(_ublock != NULL, "must have old block");
330 _ublock = b;
331 }
333 void LIR_OpBranch::negate_cond() {
334 switch (_cond) {
335 case lir_cond_equal: _cond = lir_cond_notEqual; break;
336 case lir_cond_notEqual: _cond = lir_cond_equal; break;
337 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
338 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
339 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
340 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
341 default: ShouldNotReachHere();
342 }
343 }
346 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
347 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
348 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
349 CodeStub* stub)
351 : LIR_Op(code, result, NULL)
352 , _object(object)
353 , _array(LIR_OprFact::illegalOpr)
354 , _klass(klass)
355 , _tmp1(tmp1)
356 , _tmp2(tmp2)
357 , _tmp3(tmp3)
358 , _fast_check(fast_check)
359 , _stub(stub)
360 , _info_for_patch(info_for_patch)
361 , _info_for_exception(info_for_exception)
362 , _profiled_method(NULL)
363 , _profiled_bci(-1)
364 , _should_profile(false)
365 {
366 if (code == lir_checkcast) {
367 assert(info_for_exception != NULL, "checkcast throws exceptions");
368 } else if (code == lir_instanceof) {
369 assert(info_for_exception == NULL, "instanceof throws no exceptions");
370 } else {
371 ShouldNotReachHere();
372 }
373 }
377 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
378 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
379 , _object(object)
380 , _array(array)
381 , _klass(NULL)
382 , _tmp1(tmp1)
383 , _tmp2(tmp2)
384 , _tmp3(tmp3)
385 , _fast_check(false)
386 , _stub(NULL)
387 , _info_for_patch(NULL)
388 , _info_for_exception(info_for_exception)
389 , _profiled_method(NULL)
390 , _profiled_bci(-1)
391 , _should_profile(false)
392 {
393 if (code == lir_store_check) {
394 _stub = new ArrayStoreExceptionStub(info_for_exception);
395 assert(info_for_exception != NULL, "store_check throws exceptions");
396 } else {
397 ShouldNotReachHere();
398 }
399 }
402 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
403 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
404 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
405 , _tmp(tmp)
406 , _src(src)
407 , _src_pos(src_pos)
408 , _dst(dst)
409 , _dst_pos(dst_pos)
410 , _flags(flags)
411 , _expected_type(expected_type)
412 , _length(length) {
413 _stub = new ArrayCopyStub(this);
414 }
417 //-------------------verify--------------------------
419 void LIR_Op1::verify() const {
420 switch(code()) {
421 case lir_move:
422 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
423 break;
424 case lir_null_check:
425 assert(in_opr()->is_register(), "must be");
426 break;
427 case lir_return:
428 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
429 break;
430 }
431 }
433 void LIR_OpRTCall::verify() const {
434 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
435 }
437 //-------------------visits--------------------------
439 // complete rework of LIR instruction visitor.
440 // The virtual calls for each instruction type is replaced by a big
441 // switch that adds the operands for each instruction
443 void LIR_OpVisitState::visit(LIR_Op* op) {
444 // copy information from the LIR_Op
445 reset();
446 set_op(op);
448 switch (op->code()) {
450 // LIR_Op0
451 case lir_word_align: // result and info always invalid
452 case lir_backwardbranch_target: // result and info always invalid
453 case lir_build_frame: // result and info always invalid
454 case lir_fpop_raw: // result and info always invalid
455 case lir_24bit_FPU: // result and info always invalid
456 case lir_reset_FPU: // result and info always invalid
457 case lir_breakpoint: // result and info always invalid
458 case lir_membar: // result and info always invalid
459 case lir_membar_acquire: // result and info always invalid
460 case lir_membar_release: // result and info always invalid
461 {
462 assert(op->as_Op0() != NULL, "must be");
463 assert(op->_info == NULL, "info not used by this instruction");
464 assert(op->_result->is_illegal(), "not used");
465 break;
466 }
468 case lir_nop: // may have info, result always invalid
469 case lir_std_entry: // may have result, info always invalid
470 case lir_osr_entry: // may have result, info always invalid
471 case lir_get_thread: // may have result, info always invalid
472 {
473 assert(op->as_Op0() != NULL, "must be");
474 if (op->_info != NULL) do_info(op->_info);
475 if (op->_result->is_valid()) do_output(op->_result);
476 break;
477 }
480 // LIR_OpLabel
481 case lir_label: // result and info always invalid
482 {
483 assert(op->as_OpLabel() != NULL, "must be");
484 assert(op->_info == NULL, "info not used by this instruction");
485 assert(op->_result->is_illegal(), "not used");
486 break;
487 }
490 // LIR_Op1
491 case lir_fxch: // input always valid, result and info always invalid
492 case lir_fld: // input always valid, result and info always invalid
493 case lir_ffree: // input always valid, result and info always invalid
494 case lir_push: // input always valid, result and info always invalid
495 case lir_pop: // input always valid, result and info always invalid
496 case lir_return: // input always valid, result and info always invalid
497 case lir_leal: // input and result always valid, info always invalid
498 case lir_neg: // input and result always valid, info always invalid
499 case lir_monaddr: // input and result always valid, info always invalid
500 case lir_null_check: // input and info always valid, result always invalid
501 case lir_move: // input and result always valid, may have info
502 case lir_pack64: // input and result always valid
503 case lir_unpack64: // input and result always valid
504 case lir_prefetchr: // input always valid, result and info always invalid
505 case lir_prefetchw: // input always valid, result and info always invalid
506 {
507 assert(op->as_Op1() != NULL, "must be");
508 LIR_Op1* op1 = (LIR_Op1*)op;
510 if (op1->_info) do_info(op1->_info);
511 if (op1->_opr->is_valid()) do_input(op1->_opr);
512 if (op1->_result->is_valid()) do_output(op1->_result);
514 break;
515 }
517 case lir_safepoint:
518 {
519 assert(op->as_Op1() != NULL, "must be");
520 LIR_Op1* op1 = (LIR_Op1*)op;
522 assert(op1->_info != NULL, ""); do_info(op1->_info);
523 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
524 assert(op1->_result->is_illegal(), "safepoint does not produce value");
526 break;
527 }
529 // LIR_OpConvert;
530 case lir_convert: // input and result always valid, info always invalid
531 {
532 assert(op->as_OpConvert() != NULL, "must be");
533 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
535 assert(opConvert->_info == NULL, "must be");
536 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
537 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
538 #ifdef PPC
539 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
540 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
541 #endif
542 do_stub(opConvert->_stub);
544 break;
545 }
547 // LIR_OpBranch;
548 case lir_branch: // may have info, input and result register always invalid
549 case lir_cond_float_branch: // may have info, input and result register always invalid
550 {
551 assert(op->as_OpBranch() != NULL, "must be");
552 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
554 if (opBranch->_info != NULL) do_info(opBranch->_info);
555 assert(opBranch->_result->is_illegal(), "not used");
556 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
558 break;
559 }
562 // LIR_OpAllocObj
563 case lir_alloc_object:
564 {
565 assert(op->as_OpAllocObj() != NULL, "must be");
566 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
568 if (opAllocObj->_info) do_info(opAllocObj->_info);
569 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
570 do_temp(opAllocObj->_opr);
571 }
572 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
573 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
574 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
575 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
576 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
577 do_stub(opAllocObj->_stub);
578 break;
579 }
582 // LIR_OpRoundFP;
583 case lir_roundfp: {
584 assert(op->as_OpRoundFP() != NULL, "must be");
585 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
587 assert(op->_info == NULL, "info not used by this instruction");
588 assert(opRoundFP->_tmp->is_illegal(), "not used");
589 do_input(opRoundFP->_opr);
590 do_output(opRoundFP->_result);
592 break;
593 }
596 // LIR_Op2
597 case lir_cmp:
598 case lir_cmp_l2i:
599 case lir_ucmp_fd2i:
600 case lir_cmp_fd2i:
601 case lir_add:
602 case lir_sub:
603 case lir_mul:
604 case lir_div:
605 case lir_rem:
606 case lir_sqrt:
607 case lir_abs:
608 case lir_logic_and:
609 case lir_logic_or:
610 case lir_logic_xor:
611 case lir_shl:
612 case lir_shr:
613 case lir_ushr:
614 {
615 assert(op->as_Op2() != NULL, "must be");
616 LIR_Op2* op2 = (LIR_Op2*)op;
618 if (op2->_info) do_info(op2->_info);
619 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
620 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
621 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
622 if (op2->_result->is_valid()) do_output(op2->_result);
624 break;
625 }
627 // special handling for cmove: right input operand must not be equal
628 // to the result operand, otherwise the backend fails
629 case lir_cmove:
630 {
631 assert(op->as_Op2() != NULL, "must be");
632 LIR_Op2* op2 = (LIR_Op2*)op;
634 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used");
635 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
637 do_input(op2->_opr1);
638 do_input(op2->_opr2);
639 do_temp(op2->_opr2);
640 do_output(op2->_result);
642 break;
643 }
645 // vspecial handling for strict operations: register input operands
646 // as temp to guarantee that they do not overlap with other
647 // registers
648 case lir_mul_strictfp:
649 case lir_div_strictfp:
650 {
651 assert(op->as_Op2() != NULL, "must be");
652 LIR_Op2* op2 = (LIR_Op2*)op;
654 assert(op2->_info == NULL, "not used");
655 assert(op2->_opr1->is_valid(), "used");
656 assert(op2->_opr2->is_valid(), "used");
657 assert(op2->_result->is_valid(), "used");
659 do_input(op2->_opr1); do_temp(op2->_opr1);
660 do_input(op2->_opr2); do_temp(op2->_opr2);
661 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
662 do_output(op2->_result);
664 break;
665 }
667 case lir_throw: {
668 assert(op->as_Op2() != NULL, "must be");
669 LIR_Op2* op2 = (LIR_Op2*)op;
671 if (op2->_info) do_info(op2->_info);
672 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
673 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
674 assert(op2->_result->is_illegal(), "no result");
676 break;
677 }
679 case lir_unwind: {
680 assert(op->as_Op1() != NULL, "must be");
681 LIR_Op1* op1 = (LIR_Op1*)op;
683 assert(op1->_info == NULL, "no info");
684 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
685 assert(op1->_result->is_illegal(), "no result");
687 break;
688 }
691 case lir_tan:
692 case lir_sin:
693 case lir_cos:
694 case lir_log:
695 case lir_log10: {
696 assert(op->as_Op2() != NULL, "must be");
697 LIR_Op2* op2 = (LIR_Op2*)op;
699 // On x86 tan/sin/cos need two temporary fpu stack slots and
700 // log/log10 need one so handle opr2 and tmp as temp inputs.
701 // Register input operand as temp to guarantee that it doesn't
702 // overlap with the input.
703 assert(op2->_info == NULL, "not used");
704 assert(op2->_opr1->is_valid(), "used");
705 do_input(op2->_opr1); do_temp(op2->_opr1);
707 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
708 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
709 if (op2->_result->is_valid()) do_output(op2->_result);
711 break;
712 }
715 // LIR_Op3
716 case lir_idiv:
717 case lir_irem: {
718 assert(op->as_Op3() != NULL, "must be");
719 LIR_Op3* op3= (LIR_Op3*)op;
721 if (op3->_info) do_info(op3->_info);
722 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
724 // second operand is input and temp, so ensure that second operand
725 // and third operand get not the same register
726 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
727 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
728 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
730 if (op3->_result->is_valid()) do_output(op3->_result);
732 break;
733 }
736 // LIR_OpJavaCall
737 case lir_static_call:
738 case lir_optvirtual_call:
739 case lir_icvirtual_call:
740 case lir_virtual_call:
741 case lir_dynamic_call: {
742 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
743 assert(opJavaCall != NULL, "must be");
745 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
747 // only visit register parameters
748 int n = opJavaCall->_arguments->length();
749 for (int i = 0; i < n; i++) {
750 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
751 do_input(*opJavaCall->_arguments->adr_at(i));
752 }
753 }
755 if (opJavaCall->_info) do_info(opJavaCall->_info);
756 if (opJavaCall->is_method_handle_invoke()) {
757 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
758 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
759 }
760 do_call();
761 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
763 break;
764 }
767 // LIR_OpRTCall
768 case lir_rtcall: {
769 assert(op->as_OpRTCall() != NULL, "must be");
770 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
772 // only visit register parameters
773 int n = opRTCall->_arguments->length();
774 for (int i = 0; i < n; i++) {
775 if (!opRTCall->_arguments->at(i)->is_pointer()) {
776 do_input(*opRTCall->_arguments->adr_at(i));
777 }
778 }
779 if (opRTCall->_info) do_info(opRTCall->_info);
780 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
781 do_call();
782 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
784 break;
785 }
788 // LIR_OpArrayCopy
789 case lir_arraycopy: {
790 assert(op->as_OpArrayCopy() != NULL, "must be");
791 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
793 assert(opArrayCopy->_result->is_illegal(), "unused");
794 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
795 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
796 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
797 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
798 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
799 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
800 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
802 // the implementation of arraycopy always has a call into the runtime
803 do_call();
805 break;
806 }
809 // LIR_OpLock
810 case lir_lock:
811 case lir_unlock: {
812 assert(op->as_OpLock() != NULL, "must be");
813 LIR_OpLock* opLock = (LIR_OpLock*)op;
815 if (opLock->_info) do_info(opLock->_info);
817 // TODO: check if these operands really have to be temp
818 // (or if input is sufficient). This may have influence on the oop map!
819 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
820 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
821 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
823 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
824 assert(opLock->_result->is_illegal(), "unused");
826 do_stub(opLock->_stub);
828 break;
829 }
832 // LIR_OpDelay
833 case lir_delay_slot: {
834 assert(op->as_OpDelay() != NULL, "must be");
835 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
837 visit(opDelay->delay_op());
838 break;
839 }
841 // LIR_OpTypeCheck
842 case lir_instanceof:
843 case lir_checkcast:
844 case lir_store_check: {
845 assert(op->as_OpTypeCheck() != NULL, "must be");
846 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
848 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
849 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
850 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
851 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
852 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
853 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
854 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
855 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
856 do_stub(opTypeCheck->_stub);
857 break;
858 }
860 // LIR_OpCompareAndSwap
861 case lir_cas_long:
862 case lir_cas_obj:
863 case lir_cas_int: {
864 assert(op->as_OpCompareAndSwap() != NULL, "must be");
865 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
867 assert(opCompareAndSwap->_addr->is_valid(), "used");
868 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
869 assert(opCompareAndSwap->_new_value->is_valid(), "used");
870 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
871 do_input(opCompareAndSwap->_addr);
872 do_temp(opCompareAndSwap->_addr);
873 do_input(opCompareAndSwap->_cmp_value);
874 do_temp(opCompareAndSwap->_cmp_value);
875 do_input(opCompareAndSwap->_new_value);
876 do_temp(opCompareAndSwap->_new_value);
877 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
878 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
879 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
881 break;
882 }
885 // LIR_OpAllocArray;
886 case lir_alloc_array: {
887 assert(op->as_OpAllocArray() != NULL, "must be");
888 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
890 if (opAllocArray->_info) do_info(opAllocArray->_info);
891 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
892 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
893 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
894 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
895 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
896 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
897 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
898 do_stub(opAllocArray->_stub);
899 break;
900 }
902 // LIR_OpProfileCall:
903 case lir_profile_call: {
904 assert(op->as_OpProfileCall() != NULL, "must be");
905 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
907 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
908 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
909 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
910 break;
911 }
912 default:
913 ShouldNotReachHere();
914 }
915 }
918 void LIR_OpVisitState::do_stub(CodeStub* stub) {
919 if (stub != NULL) {
920 stub->visit(this);
921 }
922 }
924 XHandlers* LIR_OpVisitState::all_xhandler() {
925 XHandlers* result = NULL;
927 int i;
928 for (i = 0; i < info_count(); i++) {
929 if (info_at(i)->exception_handlers() != NULL) {
930 result = info_at(i)->exception_handlers();
931 break;
932 }
933 }
935 #ifdef ASSERT
936 for (i = 0; i < info_count(); i++) {
937 assert(info_at(i)->exception_handlers() == NULL ||
938 info_at(i)->exception_handlers() == result,
939 "only one xhandler list allowed per LIR-operation");
940 }
941 #endif
943 if (result != NULL) {
944 return result;
945 } else {
946 return new XHandlers();
947 }
949 return result;
950 }
953 #ifdef ASSERT
954 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
955 visit(op);
957 return opr_count(inputMode) == 0 &&
958 opr_count(outputMode) == 0 &&
959 opr_count(tempMode) == 0 &&
960 info_count() == 0 &&
961 !has_call() &&
962 !has_slow_case();
963 }
964 #endif
966 //---------------------------------------------------
969 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
970 masm->emit_call(this);
971 }
973 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
974 masm->emit_rtcall(this);
975 }
977 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
978 masm->emit_opLabel(this);
979 }
981 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
982 masm->emit_arraycopy(this);
983 masm->emit_code_stub(stub());
984 }
986 void LIR_Op0::emit_code(LIR_Assembler* masm) {
987 masm->emit_op0(this);
988 }
990 void LIR_Op1::emit_code(LIR_Assembler* masm) {
991 masm->emit_op1(this);
992 }
994 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
995 masm->emit_alloc_obj(this);
996 masm->emit_code_stub(stub());
997 }
999 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1000 masm->emit_opBranch(this);
1001 if (stub()) {
1002 masm->emit_code_stub(stub());
1003 }
1004 }
1006 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1007 masm->emit_opConvert(this);
1008 if (stub() != NULL) {
1009 masm->emit_code_stub(stub());
1010 }
1011 }
1013 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1014 masm->emit_op2(this);
1015 }
1017 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1018 masm->emit_alloc_array(this);
1019 masm->emit_code_stub(stub());
1020 }
1022 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1023 masm->emit_opTypeCheck(this);
1024 if (stub()) {
1025 masm->emit_code_stub(stub());
1026 }
1027 }
1029 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1030 masm->emit_compare_and_swap(this);
1031 }
1033 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1034 masm->emit_op3(this);
1035 }
1037 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1038 masm->emit_lock(this);
1039 if (stub()) {
1040 masm->emit_code_stub(stub());
1041 }
1042 }
1045 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1046 masm->emit_delay(this);
1047 }
1049 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1050 masm->emit_profile_call(this);
1051 }
1053 // LIR_List
1054 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1055 : _operations(8)
1056 , _compilation(compilation)
1057 #ifndef PRODUCT
1058 , _block(block)
1059 #endif
1060 #ifdef ASSERT
1061 , _file(NULL)
1062 , _line(0)
1063 #endif
1064 { }
1067 #ifdef ASSERT
1068 void LIR_List::set_file_and_line(const char * file, int line) {
1069 const char * f = strrchr(file, '/');
1070 if (f == NULL) f = strrchr(file, '\\');
1071 if (f == NULL) {
1072 f = file;
1073 } else {
1074 f++;
1075 }
1076 _file = f;
1077 _line = line;
1078 }
1079 #endif
1082 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1083 assert(this == buffer->lir_list(), "wrong lir list");
1084 const int n = _operations.length();
1086 if (buffer->number_of_ops() > 0) {
1087 // increase size of instructions list
1088 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1089 // insert ops from buffer into instructions list
1090 int op_index = buffer->number_of_ops() - 1;
1091 int ip_index = buffer->number_of_insertion_points() - 1;
1092 int from_index = n - 1;
1093 int to_index = _operations.length() - 1;
1094 for (; ip_index >= 0; ip_index --) {
1095 int index = buffer->index_at(ip_index);
1096 // make room after insertion point
1097 while (index < from_index) {
1098 _operations.at_put(to_index --, _operations.at(from_index --));
1099 }
1100 // insert ops from buffer
1101 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1102 _operations.at_put(to_index --, buffer->op_at(op_index --));
1103 }
1104 }
1105 }
1107 buffer->finish();
1108 }
1111 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1112 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1113 }
1116 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1117 append(new LIR_Op1(
1118 lir_move,
1119 LIR_OprFact::address(addr),
1120 src,
1121 addr->type(),
1122 patch_code,
1123 info));
1124 }
1127 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1128 append(new LIR_Op1(
1129 lir_move,
1130 LIR_OprFact::address(address),
1131 dst,
1132 address->type(),
1133 patch_code,
1134 info, lir_move_volatile));
1135 }
1137 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1138 append(new LIR_Op1(
1139 lir_move,
1140 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1141 dst,
1142 type,
1143 patch_code,
1144 info, lir_move_volatile));
1145 }
1148 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1149 append(new LIR_Op1(
1150 is_store ? lir_prefetchw : lir_prefetchr,
1151 LIR_OprFact::address(addr)));
1152 }
1155 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1156 append(new LIR_Op1(
1157 lir_move,
1158 LIR_OprFact::intConst(v),
1159 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1160 type,
1161 patch_code,
1162 info));
1163 }
1166 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1167 append(new LIR_Op1(
1168 lir_move,
1169 LIR_OprFact::oopConst(o),
1170 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1171 type,
1172 patch_code,
1173 info));
1174 }
1177 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1178 append(new LIR_Op1(
1179 lir_move,
1180 src,
1181 LIR_OprFact::address(addr),
1182 addr->type(),
1183 patch_code,
1184 info));
1185 }
1188 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1189 append(new LIR_Op1(
1190 lir_move,
1191 src,
1192 LIR_OprFact::address(addr),
1193 addr->type(),
1194 patch_code,
1195 info,
1196 lir_move_volatile));
1197 }
1199 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1200 append(new LIR_Op1(
1201 lir_move,
1202 src,
1203 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1204 type,
1205 patch_code,
1206 info, lir_move_volatile));
1207 }
1210 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1211 append(new LIR_Op3(
1212 lir_idiv,
1213 left,
1214 right,
1215 tmp,
1216 res,
1217 info));
1218 }
1221 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1222 append(new LIR_Op3(
1223 lir_idiv,
1224 left,
1225 LIR_OprFact::intConst(right),
1226 tmp,
1227 res,
1228 info));
1229 }
1232 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1233 append(new LIR_Op3(
1234 lir_irem,
1235 left,
1236 right,
1237 tmp,
1238 res,
1239 info));
1240 }
1243 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1244 append(new LIR_Op3(
1245 lir_irem,
1246 left,
1247 LIR_OprFact::intConst(right),
1248 tmp,
1249 res,
1250 info));
1251 }
1254 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1255 append(new LIR_Op2(
1256 lir_cmp,
1257 condition,
1258 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1259 LIR_OprFact::intConst(c),
1260 info));
1261 }
1264 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1265 append(new LIR_Op2(
1266 lir_cmp,
1267 condition,
1268 reg,
1269 LIR_OprFact::address(addr),
1270 info));
1271 }
1273 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1274 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1275 append(new LIR_OpAllocObj(
1276 klass,
1277 dst,
1278 t1,
1279 t2,
1280 t3,
1281 t4,
1282 header_size,
1283 object_size,
1284 init_check,
1285 stub));
1286 }
1288 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1289 append(new LIR_OpAllocArray(
1290 klass,
1291 len,
1292 dst,
1293 t1,
1294 t2,
1295 t3,
1296 t4,
1297 type,
1298 stub));
1299 }
1301 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1302 append(new LIR_Op2(
1303 lir_shl,
1304 value,
1305 count,
1306 dst,
1307 tmp));
1308 }
1310 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1311 append(new LIR_Op2(
1312 lir_shr,
1313 value,
1314 count,
1315 dst,
1316 tmp));
1317 }
1320 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1321 append(new LIR_Op2(
1322 lir_ushr,
1323 value,
1324 count,
1325 dst,
1326 tmp));
1327 }
1329 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1330 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1331 left,
1332 right,
1333 dst));
1334 }
1336 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1337 append(new LIR_OpLock(
1338 lir_lock,
1339 hdr,
1340 obj,
1341 lock,
1342 scratch,
1343 stub,
1344 info));
1345 }
1347 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1348 append(new LIR_OpLock(
1349 lir_unlock,
1350 hdr,
1351 obj,
1352 lock,
1353 scratch,
1354 stub,
1355 NULL));
1356 }
1359 void check_LIR() {
1360 // cannot do the proper checking as PRODUCT and other modes return different results
1361 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1362 }
1366 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1367 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1368 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1369 ciMethod* profiled_method, int profiled_bci) {
1370 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1371 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1372 if (profiled_method != NULL) {
1373 c->set_profiled_method(profiled_method);
1374 c->set_profiled_bci(profiled_bci);
1375 c->set_should_profile(true);
1376 }
1377 append(c);
1378 }
1380 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1381 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1382 if (profiled_method != NULL) {
1383 c->set_profiled_method(profiled_method);
1384 c->set_profiled_bci(profiled_bci);
1385 c->set_should_profile(true);
1386 }
1387 append(c);
1388 }
1391 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) {
1392 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception));
1393 }
1396 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1397 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1398 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1399 }
1401 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1402 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1403 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1404 }
1406 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1407 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1408 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1409 }
1412 #ifdef PRODUCT
1414 void print_LIR(BlockList* blocks) {
1415 }
1417 #else
1418 // LIR_OprDesc
1419 void LIR_OprDesc::print() const {
1420 print(tty);
1421 }
1423 void LIR_OprDesc::print(outputStream* out) const {
1424 if (is_illegal()) {
1425 return;
1426 }
1428 out->print("[");
1429 if (is_pointer()) {
1430 pointer()->print_value_on(out);
1431 } else if (is_single_stack()) {
1432 out->print("stack:%d", single_stack_ix());
1433 } else if (is_double_stack()) {
1434 out->print("dbl_stack:%d",double_stack_ix());
1435 } else if (is_virtual()) {
1436 out->print("R%d", vreg_number());
1437 } else if (is_single_cpu()) {
1438 out->print(as_register()->name());
1439 } else if (is_double_cpu()) {
1440 out->print(as_register_hi()->name());
1441 out->print(as_register_lo()->name());
1442 #if defined(X86)
1443 } else if (is_single_xmm()) {
1444 out->print(as_xmm_float_reg()->name());
1445 } else if (is_double_xmm()) {
1446 out->print(as_xmm_double_reg()->name());
1447 } else if (is_single_fpu()) {
1448 out->print("fpu%d", fpu_regnr());
1449 } else if (is_double_fpu()) {
1450 out->print("fpu%d", fpu_regnrLo());
1451 #elif defined(ARM)
1452 } else if (is_single_fpu()) {
1453 out->print("s%d", fpu_regnr());
1454 } else if (is_double_fpu()) {
1455 out->print("d%d", fpu_regnrLo() >> 1);
1456 #else
1457 } else if (is_single_fpu()) {
1458 out->print(as_float_reg()->name());
1459 } else if (is_double_fpu()) {
1460 out->print(as_double_reg()->name());
1461 #endif
1463 } else if (is_illegal()) {
1464 out->print("-");
1465 } else {
1466 out->print("Unknown Operand");
1467 }
1468 if (!is_illegal()) {
1469 out->print("|%c", type_char());
1470 }
1471 if (is_register() && is_last_use()) {
1472 out->print("(last_use)");
1473 }
1474 out->print("]");
1475 }
1478 // LIR_Address
1479 void LIR_Const::print_value_on(outputStream* out) const {
1480 switch (type()) {
1481 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1482 case T_INT: out->print("int:%d", as_jint()); break;
1483 case T_LONG: out->print("lng:%lld", as_jlong()); break;
1484 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1485 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1486 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1487 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1488 }
1489 }
1491 // LIR_Address
1492 void LIR_Address::print_value_on(outputStream* out) const {
1493 out->print("Base:"); _base->print(out);
1494 if (!_index->is_illegal()) {
1495 out->print(" Index:"); _index->print(out);
1496 switch (scale()) {
1497 case times_1: break;
1498 case times_2: out->print(" * 2"); break;
1499 case times_4: out->print(" * 4"); break;
1500 case times_8: out->print(" * 8"); break;
1501 }
1502 }
1503 out->print(" Disp: %d", _disp);
1504 }
1506 // debug output of block header without InstructionPrinter
1507 // (because phi functions are not necessary for LIR)
1508 static void print_block(BlockBegin* x) {
1509 // print block id
1510 BlockEnd* end = x->end();
1511 tty->print("B%d ", x->block_id());
1513 // print flags
1514 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1515 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1516 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1517 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1518 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1519 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1520 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1522 // print block bci range
1523 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->bci()));
1525 // print predecessors and successors
1526 if (x->number_of_preds() > 0) {
1527 tty->print("preds: ");
1528 for (int i = 0; i < x->number_of_preds(); i ++) {
1529 tty->print("B%d ", x->pred_at(i)->block_id());
1530 }
1531 }
1533 if (x->number_of_sux() > 0) {
1534 tty->print("sux: ");
1535 for (int i = 0; i < x->number_of_sux(); i ++) {
1536 tty->print("B%d ", x->sux_at(i)->block_id());
1537 }
1538 }
1540 // print exception handlers
1541 if (x->number_of_exception_handlers() > 0) {
1542 tty->print("xhandler: ");
1543 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1544 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1545 }
1546 }
1548 tty->cr();
1549 }
1551 void print_LIR(BlockList* blocks) {
1552 tty->print_cr("LIR:");
1553 int i;
1554 for (i = 0; i < blocks->length(); i++) {
1555 BlockBegin* bb = blocks->at(i);
1556 print_block(bb);
1557 tty->print("__id_Instruction___________________________________________"); tty->cr();
1558 bb->lir()->print_instructions();
1559 }
1560 }
1562 void LIR_List::print_instructions() {
1563 for (int i = 0; i < _operations.length(); i++) {
1564 _operations.at(i)->print(); tty->cr();
1565 }
1566 tty->cr();
1567 }
1569 // LIR_Ops printing routines
1570 // LIR_Op
1571 void LIR_Op::print_on(outputStream* out) const {
1572 if (id() != -1 || PrintCFGToFile) {
1573 out->print("%4d ", id());
1574 } else {
1575 out->print(" ");
1576 }
1577 out->print(name()); out->print(" ");
1578 print_instr(out);
1579 if (info() != NULL) out->print(" [bci:%d]", info()->bci());
1580 #ifdef ASSERT
1581 if (Verbose && _file != NULL) {
1582 out->print(" (%s:%d)", _file, _line);
1583 }
1584 #endif
1585 }
1587 const char * LIR_Op::name() const {
1588 const char* s = NULL;
1589 switch(code()) {
1590 // LIR_Op0
1591 case lir_membar: s = "membar"; break;
1592 case lir_membar_acquire: s = "membar_acquire"; break;
1593 case lir_membar_release: s = "membar_release"; break;
1594 case lir_word_align: s = "word_align"; break;
1595 case lir_label: s = "label"; break;
1596 case lir_nop: s = "nop"; break;
1597 case lir_backwardbranch_target: s = "backbranch"; break;
1598 case lir_std_entry: s = "std_entry"; break;
1599 case lir_osr_entry: s = "osr_entry"; break;
1600 case lir_build_frame: s = "build_frm"; break;
1601 case lir_fpop_raw: s = "fpop_raw"; break;
1602 case lir_24bit_FPU: s = "24bit_FPU"; break;
1603 case lir_reset_FPU: s = "reset_FPU"; break;
1604 case lir_breakpoint: s = "breakpoint"; break;
1605 case lir_get_thread: s = "get_thread"; break;
1606 // LIR_Op1
1607 case lir_fxch: s = "fxch"; break;
1608 case lir_fld: s = "fld"; break;
1609 case lir_ffree: s = "ffree"; break;
1610 case lir_push: s = "push"; break;
1611 case lir_pop: s = "pop"; break;
1612 case lir_null_check: s = "null_check"; break;
1613 case lir_return: s = "return"; break;
1614 case lir_safepoint: s = "safepoint"; break;
1615 case lir_neg: s = "neg"; break;
1616 case lir_leal: s = "leal"; break;
1617 case lir_branch: s = "branch"; break;
1618 case lir_cond_float_branch: s = "flt_cond_br"; break;
1619 case lir_move: s = "move"; break;
1620 case lir_roundfp: s = "roundfp"; break;
1621 case lir_rtcall: s = "rtcall"; break;
1622 case lir_throw: s = "throw"; break;
1623 case lir_unwind: s = "unwind"; break;
1624 case lir_convert: s = "convert"; break;
1625 case lir_alloc_object: s = "alloc_obj"; break;
1626 case lir_monaddr: s = "mon_addr"; break;
1627 case lir_pack64: s = "pack64"; break;
1628 case lir_unpack64: s = "unpack64"; break;
1629 // LIR_Op2
1630 case lir_cmp: s = "cmp"; break;
1631 case lir_cmp_l2i: s = "cmp_l2i"; break;
1632 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1633 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1634 case lir_cmove: s = "cmove"; break;
1635 case lir_add: s = "add"; break;
1636 case lir_sub: s = "sub"; break;
1637 case lir_mul: s = "mul"; break;
1638 case lir_mul_strictfp: s = "mul_strictfp"; break;
1639 case lir_div: s = "div"; break;
1640 case lir_div_strictfp: s = "div_strictfp"; break;
1641 case lir_rem: s = "rem"; break;
1642 case lir_abs: s = "abs"; break;
1643 case lir_sqrt: s = "sqrt"; break;
1644 case lir_sin: s = "sin"; break;
1645 case lir_cos: s = "cos"; break;
1646 case lir_tan: s = "tan"; break;
1647 case lir_log: s = "log"; break;
1648 case lir_log10: s = "log10"; break;
1649 case lir_logic_and: s = "logic_and"; break;
1650 case lir_logic_or: s = "logic_or"; break;
1651 case lir_logic_xor: s = "logic_xor"; break;
1652 case lir_shl: s = "shift_left"; break;
1653 case lir_shr: s = "shift_right"; break;
1654 case lir_ushr: s = "ushift_right"; break;
1655 case lir_alloc_array: s = "alloc_array"; break;
1656 // LIR_Op3
1657 case lir_idiv: s = "idiv"; break;
1658 case lir_irem: s = "irem"; break;
1659 // LIR_OpJavaCall
1660 case lir_static_call: s = "static"; break;
1661 case lir_optvirtual_call: s = "optvirtual"; break;
1662 case lir_icvirtual_call: s = "icvirtual"; break;
1663 case lir_virtual_call: s = "virtual"; break;
1664 case lir_dynamic_call: s = "dynamic"; break;
1665 // LIR_OpArrayCopy
1666 case lir_arraycopy: s = "arraycopy"; break;
1667 // LIR_OpLock
1668 case lir_lock: s = "lock"; break;
1669 case lir_unlock: s = "unlock"; break;
1670 // LIR_OpDelay
1671 case lir_delay_slot: s = "delay"; break;
1672 // LIR_OpTypeCheck
1673 case lir_instanceof: s = "instanceof"; break;
1674 case lir_checkcast: s = "checkcast"; break;
1675 case lir_store_check: s = "store_check"; break;
1676 // LIR_OpCompareAndSwap
1677 case lir_cas_long: s = "cas_long"; break;
1678 case lir_cas_obj: s = "cas_obj"; break;
1679 case lir_cas_int: s = "cas_int"; break;
1680 // LIR_OpProfileCall
1681 case lir_profile_call: s = "profile_call"; break;
1682 case lir_none: ShouldNotReachHere();break;
1683 default: s = "illegal_op"; break;
1684 }
1685 return s;
1686 }
1688 // LIR_OpJavaCall
1689 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1690 out->print("call: ");
1691 out->print("[addr: 0x%x]", address());
1692 if (receiver()->is_valid()) {
1693 out->print(" [recv: "); receiver()->print(out); out->print("]");
1694 }
1695 if (result_opr()->is_valid()) {
1696 out->print(" [result: "); result_opr()->print(out); out->print("]");
1697 }
1698 }
1700 // LIR_OpLabel
1701 void LIR_OpLabel::print_instr(outputStream* out) const {
1702 out->print("[label:0x%x]", _label);
1703 }
1705 // LIR_OpArrayCopy
1706 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1707 src()->print(out); out->print(" ");
1708 src_pos()->print(out); out->print(" ");
1709 dst()->print(out); out->print(" ");
1710 dst_pos()->print(out); out->print(" ");
1711 length()->print(out); out->print(" ");
1712 tmp()->print(out); out->print(" ");
1713 }
1715 // LIR_OpCompareAndSwap
1716 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1717 addr()->print(out); out->print(" ");
1718 cmp_value()->print(out); out->print(" ");
1719 new_value()->print(out); out->print(" ");
1720 tmp1()->print(out); out->print(" ");
1721 tmp2()->print(out); out->print(" ");
1723 }
1725 // LIR_Op0
1726 void LIR_Op0::print_instr(outputStream* out) const {
1727 result_opr()->print(out);
1728 }
1730 // LIR_Op1
1731 const char * LIR_Op1::name() const {
1732 if (code() == lir_move) {
1733 switch (move_kind()) {
1734 case lir_move_normal:
1735 return "move";
1736 case lir_move_unaligned:
1737 return "unaligned move";
1738 case lir_move_volatile:
1739 return "volatile_move";
1740 default:
1741 ShouldNotReachHere();
1742 return "illegal_op";
1743 }
1744 } else {
1745 return LIR_Op::name();
1746 }
1747 }
1750 void LIR_Op1::print_instr(outputStream* out) const {
1751 _opr->print(out); out->print(" ");
1752 result_opr()->print(out); out->print(" ");
1753 print_patch_code(out, patch_code());
1754 }
1757 // LIR_Op1
1758 void LIR_OpRTCall::print_instr(outputStream* out) const {
1759 intx a = (intx)addr();
1760 out->print(Runtime1::name_for_address(addr()));
1761 out->print(" ");
1762 tmp()->print(out);
1763 }
1765 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1766 switch(code) {
1767 case lir_patch_none: break;
1768 case lir_patch_low: out->print("[patch_low]"); break;
1769 case lir_patch_high: out->print("[patch_high]"); break;
1770 case lir_patch_normal: out->print("[patch_normal]"); break;
1771 default: ShouldNotReachHere();
1772 }
1773 }
1775 // LIR_OpBranch
1776 void LIR_OpBranch::print_instr(outputStream* out) const {
1777 print_condition(out, cond()); out->print(" ");
1778 if (block() != NULL) {
1779 out->print("[B%d] ", block()->block_id());
1780 } else if (stub() != NULL) {
1781 out->print("[");
1782 stub()->print_name(out);
1783 out->print(": 0x%x]", stub());
1784 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->bci());
1785 } else {
1786 out->print("[label:0x%x] ", label());
1787 }
1788 if (ublock() != NULL) {
1789 out->print("unordered: [B%d] ", ublock()->block_id());
1790 }
1791 }
1793 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1794 switch(cond) {
1795 case lir_cond_equal: out->print("[EQ]"); break;
1796 case lir_cond_notEqual: out->print("[NE]"); break;
1797 case lir_cond_less: out->print("[LT]"); break;
1798 case lir_cond_lessEqual: out->print("[LE]"); break;
1799 case lir_cond_greaterEqual: out->print("[GE]"); break;
1800 case lir_cond_greater: out->print("[GT]"); break;
1801 case lir_cond_belowEqual: out->print("[BE]"); break;
1802 case lir_cond_aboveEqual: out->print("[AE]"); break;
1803 case lir_cond_always: out->print("[AL]"); break;
1804 default: out->print("[%d]",cond); break;
1805 }
1806 }
1808 // LIR_OpConvert
1809 void LIR_OpConvert::print_instr(outputStream* out) const {
1810 print_bytecode(out, bytecode());
1811 in_opr()->print(out); out->print(" ");
1812 result_opr()->print(out); out->print(" ");
1813 #ifdef PPC
1814 if(tmp1()->is_valid()) {
1815 tmp1()->print(out); out->print(" ");
1816 tmp2()->print(out); out->print(" ");
1817 }
1818 #endif
1819 }
1821 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1822 switch(code) {
1823 case Bytecodes::_d2f: out->print("[d2f] "); break;
1824 case Bytecodes::_d2i: out->print("[d2i] "); break;
1825 case Bytecodes::_d2l: out->print("[d2l] "); break;
1826 case Bytecodes::_f2d: out->print("[f2d] "); break;
1827 case Bytecodes::_f2i: out->print("[f2i] "); break;
1828 case Bytecodes::_f2l: out->print("[f2l] "); break;
1829 case Bytecodes::_i2b: out->print("[i2b] "); break;
1830 case Bytecodes::_i2c: out->print("[i2c] "); break;
1831 case Bytecodes::_i2d: out->print("[i2d] "); break;
1832 case Bytecodes::_i2f: out->print("[i2f] "); break;
1833 case Bytecodes::_i2l: out->print("[i2l] "); break;
1834 case Bytecodes::_i2s: out->print("[i2s] "); break;
1835 case Bytecodes::_l2i: out->print("[l2i] "); break;
1836 case Bytecodes::_l2f: out->print("[l2f] "); break;
1837 case Bytecodes::_l2d: out->print("[l2d] "); break;
1838 default:
1839 out->print("[?%d]",code);
1840 break;
1841 }
1842 }
1844 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1845 klass()->print(out); out->print(" ");
1846 obj()->print(out); out->print(" ");
1847 tmp1()->print(out); out->print(" ");
1848 tmp2()->print(out); out->print(" ");
1849 tmp3()->print(out); out->print(" ");
1850 tmp4()->print(out); out->print(" ");
1851 out->print("[hdr:%d]", header_size()); out->print(" ");
1852 out->print("[obj:%d]", object_size()); out->print(" ");
1853 out->print("[lbl:0x%x]", stub()->entry());
1854 }
1856 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1857 _opr->print(out); out->print(" ");
1858 tmp()->print(out); out->print(" ");
1859 result_opr()->print(out); out->print(" ");
1860 }
1862 // LIR_Op2
1863 void LIR_Op2::print_instr(outputStream* out) const {
1864 if (code() == lir_cmove) {
1865 print_condition(out, condition()); out->print(" ");
1866 }
1867 in_opr1()->print(out); out->print(" ");
1868 in_opr2()->print(out); out->print(" ");
1869 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); }
1870 result_opr()->print(out);
1871 }
1873 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1874 klass()->print(out); out->print(" ");
1875 len()->print(out); out->print(" ");
1876 obj()->print(out); out->print(" ");
1877 tmp1()->print(out); out->print(" ");
1878 tmp2()->print(out); out->print(" ");
1879 tmp3()->print(out); out->print(" ");
1880 tmp4()->print(out); out->print(" ");
1881 out->print("[type:0x%x]", type()); out->print(" ");
1882 out->print("[label:0x%x]", stub()->entry());
1883 }
1886 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1887 object()->print(out); out->print(" ");
1888 if (code() == lir_store_check) {
1889 array()->print(out); out->print(" ");
1890 }
1891 if (code() != lir_store_check) {
1892 klass()->print_name_on(out); out->print(" ");
1893 if (fast_check()) out->print("fast_check ");
1894 }
1895 tmp1()->print(out); out->print(" ");
1896 tmp2()->print(out); out->print(" ");
1897 tmp3()->print(out); out->print(" ");
1898 result_opr()->print(out); out->print(" ");
1899 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->bci());
1900 }
1903 // LIR_Op3
1904 void LIR_Op3::print_instr(outputStream* out) const {
1905 in_opr1()->print(out); out->print(" ");
1906 in_opr2()->print(out); out->print(" ");
1907 in_opr3()->print(out); out->print(" ");
1908 result_opr()->print(out);
1909 }
1912 void LIR_OpLock::print_instr(outputStream* out) const {
1913 hdr_opr()->print(out); out->print(" ");
1914 obj_opr()->print(out); out->print(" ");
1915 lock_opr()->print(out); out->print(" ");
1916 if (_scratch->is_valid()) {
1917 _scratch->print(out); out->print(" ");
1918 }
1919 out->print("[lbl:0x%x]", stub()->entry());
1920 }
1923 void LIR_OpDelay::print_instr(outputStream* out) const {
1924 _op->print_on(out);
1925 }
1928 // LIR_OpProfileCall
1929 void LIR_OpProfileCall::print_instr(outputStream* out) const {
1930 profiled_method()->name()->print_symbol_on(out);
1931 out->print(".");
1932 profiled_method()->holder()->name()->print_symbol_on(out);
1933 out->print(" @ %d ", profiled_bci());
1934 mdo()->print(out); out->print(" ");
1935 recv()->print(out); out->print(" ");
1936 tmp1()->print(out); out->print(" ");
1937 }
1939 #endif // PRODUCT
1941 // Implementation of LIR_InsertionBuffer
1943 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
1944 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
1946 int i = number_of_insertion_points() - 1;
1947 if (i < 0 || index_at(i) < index) {
1948 append_new(index, 1);
1949 } else {
1950 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
1951 assert(count_at(i) > 0, "check");
1952 set_count_at(i, count_at(i) + 1);
1953 }
1954 _ops.push(op);
1956 DEBUG_ONLY(verify());
1957 }
1959 #ifdef ASSERT
1960 void LIR_InsertionBuffer::verify() {
1961 int sum = 0;
1962 int prev_idx = -1;
1964 for (int i = 0; i < number_of_insertion_points(); i++) {
1965 assert(prev_idx < index_at(i), "index must be ordered ascending");
1966 sum += count_at(i);
1967 }
1968 assert(sum == number_of_ops(), "wrong total sum");
1969 }
1970 #endif
