Mercurial > jdk8-mips64-public > hotspot / file revision
src/share/vm/c1/c1_LIR.cpp@87a6f2df28e2
src/share/vm/c1/c1_LIR.cpp
Mon, 17 Jun 2013 12:35:53 -0400
- author
- drchase
- date
- Mon, 17 Jun 2013 12:35:53 -0400
- changeset 5290
- 87a6f2df28e2
- parent 4947
- acadb114c818
- child 5353
- b800986664f4
- permissions
- -rw-r--r--
8002160: Compilation issue with adlc using latest SunStudio compilers
Summary: modify declaration of 'swap' overloading; dodge optimizer bug in c1_LIR.cpp
Reviewed-by: kvn, jrose
1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
45 #if defined(X86)
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
56 #endif // X86
58 #if defined(SPARC) || defined(PPC)
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
68 #endif
70 #ifdef ARM
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
80 #endif
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::metadataConst(NULL);
92 } else if (c != NULL) {
93 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
94 } else {
95 MethodConstant* m = type->as_MethodConstant();
96 assert (m != NULL, "not a class or a method?");
97 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
98 }
99 }
100 case objectTag : {
101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
102 }
103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
109 }
110 }
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
114 switch (type->tag()) {
115 case objectTag: return LIR_OprFact::oopConst(NULL);
116 case addressTag:return LIR_OprFact::addressConst(0);
117 case intTag: return LIR_OprFact::intConst(0);
118 case floatTag: return LIR_OprFact::floatConst(0.0);
119 case longTag: return LIR_OprFact::longConst(0);
120 case doubleTag: return LIR_OprFact::doubleConst(0.0);
121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
122 }
123 return illegalOpr;
124 }
128 //---------------------------------------------------
131 LIR_Address::Scale LIR_Address::scale(BasicType type) {
132 int elem_size = type2aelembytes(type);
133 switch (elem_size) {
134 case 1: return LIR_Address::times_1;
135 case 2: return LIR_Address::times_2;
136 case 4: return LIR_Address::times_4;
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
144 #ifndef PRODUCT
145 void LIR_Address::verify() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef ARM
151 assert(disp() == 0 || index()->is_illegal(), "can't have both");
152 // Note: offsets higher than 4096 must not be rejected here. They can
153 // be handled by the back-end or will be rejected if not.
154 #endif
155 #ifdef _LP64
156 assert(base()->is_cpu_register(), "wrong base operand");
157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
159 "wrong type for addresses");
160 #else
161 assert(base()->is_single_cpu(), "wrong base operand");
162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
164 "wrong type for addresses");
165 #endif
166 }
167 #endif
170 //---------------------------------------------------
172 char LIR_OprDesc::type_char(BasicType t) {
173 switch (t) {
174 case T_ARRAY:
175 t = T_OBJECT;
176 case T_BOOLEAN:
177 case T_CHAR:
178 case T_FLOAT:
179 case T_DOUBLE:
180 case T_BYTE:
181 case T_SHORT:
182 case T_INT:
183 case T_LONG:
184 case T_OBJECT:
185 case T_ADDRESS:
186 case T_METADATA:
187 case T_VOID:
188 return ::type2char(t);
190 case T_ILLEGAL:
191 return '?';
193 default:
194 ShouldNotReachHere();
195 return '?';
196 }
197 }
199 #ifndef PRODUCT
200 void LIR_OprDesc::validate_type() const {
202 #ifdef ASSERT
203 if (!is_pointer() && !is_illegal()) {
204 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
205 switch (as_BasicType(type_field())) {
206 case T_LONG:
207 assert((kindfield == cpu_register || kindfield == stack_value) &&
208 size_field() == double_size, "must match");
209 break;
210 case T_FLOAT:
211 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
212 assert((kindfield == fpu_register || kindfield == stack_value
213 ARM_ONLY(|| kindfield == cpu_register)
214 PPC_ONLY(|| kindfield == cpu_register) ) &&
215 size_field() == single_size, "must match");
216 break;
217 case T_DOUBLE:
218 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
219 assert((kindfield == fpu_register || kindfield == stack_value
220 ARM_ONLY(|| kindfield == cpu_register)
221 PPC_ONLY(|| kindfield == cpu_register) ) &&
222 size_field() == double_size, "must match");
223 break;
224 case T_BOOLEAN:
225 case T_CHAR:
226 case T_BYTE:
227 case T_SHORT:
228 case T_INT:
229 case T_ADDRESS:
230 case T_OBJECT:
231 case T_METADATA:
232 case T_ARRAY:
233 assert((kindfield == cpu_register || kindfield == stack_value) &&
234 size_field() == single_size, "must match");
235 break;
237 case T_ILLEGAL:
238 // XXX TKR also means unknown right now
239 // assert(is_illegal(), "must match");
240 break;
242 default:
243 ShouldNotReachHere();
244 }
245 }
246 #endif
248 }
249 #endif // PRODUCT
252 bool LIR_OprDesc::is_oop() const {
253 if (is_pointer()) {
254 return pointer()->is_oop_pointer();
255 } else {
256 OprType t= type_field();
257 assert(t != unknown_type, "not set");
258 return t == object_type;
259 }
260 }
264 void LIR_Op2::verify() const {
265 #ifdef ASSERT
266 switch (code()) {
267 case lir_cmove:
268 case lir_xchg:
269 break;
271 default:
272 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
273 "can't produce oops from arith");
274 }
276 if (TwoOperandLIRForm) {
277 switch (code()) {
278 case lir_add:
279 case lir_sub:
280 case lir_mul:
281 case lir_mul_strictfp:
282 case lir_div:
283 case lir_div_strictfp:
284 case lir_rem:
285 case lir_logic_and:
286 case lir_logic_or:
287 case lir_logic_xor:
288 case lir_shl:
289 case lir_shr:
290 assert(in_opr1() == result_opr(), "opr1 and result must match");
291 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
292 break;
294 // special handling for lir_ushr because of write barriers
295 case lir_ushr:
296 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
297 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
298 break;
300 }
301 }
302 #endif
303 }
306 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
307 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
308 , _cond(cond)
309 , _type(type)
310 , _label(block->label())
311 , _block(block)
312 , _ublock(NULL)
313 , _stub(NULL) {
314 }
316 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
317 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
318 , _cond(cond)
319 , _type(type)
320 , _label(stub->entry())
321 , _block(NULL)
322 , _ublock(NULL)
323 , _stub(stub) {
324 }
326 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
327 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
328 , _cond(cond)
329 , _type(type)
330 , _label(block->label())
331 , _block(block)
332 , _ublock(ublock)
333 , _stub(NULL)
334 {
335 }
337 void LIR_OpBranch::change_block(BlockBegin* b) {
338 assert(_block != NULL, "must have old block");
339 assert(_block->label() == label(), "must be equal");
341 _block = b;
342 _label = b->label();
343 }
345 void LIR_OpBranch::change_ublock(BlockBegin* b) {
346 assert(_ublock != NULL, "must have old block");
347 _ublock = b;
348 }
350 void LIR_OpBranch::negate_cond() {
351 switch (_cond) {
352 case lir_cond_equal: _cond = lir_cond_notEqual; break;
353 case lir_cond_notEqual: _cond = lir_cond_equal; break;
354 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
355 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
356 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
357 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
358 default: ShouldNotReachHere();
359 }
360 }
363 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
364 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
365 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
366 CodeStub* stub)
368 : LIR_Op(code, result, NULL)
369 , _object(object)
370 , _array(LIR_OprFact::illegalOpr)
371 , _klass(klass)
372 , _tmp1(tmp1)
373 , _tmp2(tmp2)
374 , _tmp3(tmp3)
375 , _fast_check(fast_check)
376 , _stub(stub)
377 , _info_for_patch(info_for_patch)
378 , _info_for_exception(info_for_exception)
379 , _profiled_method(NULL)
380 , _profiled_bci(-1)
381 , _should_profile(false)
382 {
383 if (code == lir_checkcast) {
384 assert(info_for_exception != NULL, "checkcast throws exceptions");
385 } else if (code == lir_instanceof) {
386 assert(info_for_exception == NULL, "instanceof throws no exceptions");
387 } else {
388 ShouldNotReachHere();
389 }
390 }
394 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
395 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
396 , _object(object)
397 , _array(array)
398 , _klass(NULL)
399 , _tmp1(tmp1)
400 , _tmp2(tmp2)
401 , _tmp3(tmp3)
402 , _fast_check(false)
403 , _stub(NULL)
404 , _info_for_patch(NULL)
405 , _info_for_exception(info_for_exception)
406 , _profiled_method(NULL)
407 , _profiled_bci(-1)
408 , _should_profile(false)
409 {
410 if (code == lir_store_check) {
411 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
412 assert(info_for_exception != NULL, "store_check throws exceptions");
413 } else {
414 ShouldNotReachHere();
415 }
416 }
419 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
420 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
421 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
422 , _tmp(tmp)
423 , _src(src)
424 , _src_pos(src_pos)
425 , _dst(dst)
426 , _dst_pos(dst_pos)
427 , _flags(flags)
428 , _expected_type(expected_type)
429 , _length(length) {
430 _stub = new ArrayCopyStub(this);
431 }
434 //-------------------verify--------------------------
436 void LIR_Op1::verify() const {
437 switch(code()) {
438 case lir_move:
439 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
440 break;
441 case lir_null_check:
442 assert(in_opr()->is_register(), "must be");
443 break;
444 case lir_return:
445 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
446 break;
447 }
448 }
450 void LIR_OpRTCall::verify() const {
451 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
452 }
454 //-------------------visits--------------------------
456 // complete rework of LIR instruction visitor.
457 // The virtual calls for each instruction type is replaced by a big
458 // switch that adds the operands for each instruction
460 void LIR_OpVisitState::visit(LIR_Op* op) {
461 // copy information from the LIR_Op
462 reset();
463 set_op(op);
465 switch (op->code()) {
467 // LIR_Op0
468 case lir_word_align: // result and info always invalid
469 case lir_backwardbranch_target: // result and info always invalid
470 case lir_build_frame: // result and info always invalid
471 case lir_fpop_raw: // result and info always invalid
472 case lir_24bit_FPU: // result and info always invalid
473 case lir_reset_FPU: // result and info always invalid
474 case lir_breakpoint: // result and info always invalid
475 case lir_membar: // result and info always invalid
476 case lir_membar_acquire: // result and info always invalid
477 case lir_membar_release: // result and info always invalid
478 case lir_membar_loadload: // result and info always invalid
479 case lir_membar_storestore: // result and info always invalid
480 case lir_membar_loadstore: // result and info always invalid
481 case lir_membar_storeload: // result and info always invalid
482 {
483 assert(op->as_Op0() != NULL, "must be");
484 assert(op->_info == NULL, "info not used by this instruction");
485 assert(op->_result->is_illegal(), "not used");
486 break;
487 }
489 case lir_nop: // may have info, result always invalid
490 case lir_std_entry: // may have result, info always invalid
491 case lir_osr_entry: // may have result, info always invalid
492 case lir_get_thread: // may have result, info always invalid
493 {
494 assert(op->as_Op0() != NULL, "must be");
495 if (op->_info != NULL) do_info(op->_info);
496 if (op->_result->is_valid()) do_output(op->_result);
497 break;
498 }
501 // LIR_OpLabel
502 case lir_label: // result and info always invalid
503 {
504 assert(op->as_OpLabel() != NULL, "must be");
505 assert(op->_info == NULL, "info not used by this instruction");
506 assert(op->_result->is_illegal(), "not used");
507 break;
508 }
511 // LIR_Op1
512 case lir_fxch: // input always valid, result and info always invalid
513 case lir_fld: // input always valid, result and info always invalid
514 case lir_ffree: // input always valid, result and info always invalid
515 case lir_push: // input always valid, result and info always invalid
516 case lir_pop: // input always valid, result and info always invalid
517 case lir_return: // input always valid, result and info always invalid
518 case lir_leal: // input and result always valid, info always invalid
519 case lir_neg: // input and result always valid, info always invalid
520 case lir_monaddr: // input and result always valid, info always invalid
521 case lir_null_check: // input and info always valid, result always invalid
522 case lir_move: // input and result always valid, may have info
523 case lir_pack64: // input and result always valid
524 case lir_unpack64: // input and result always valid
525 case lir_prefetchr: // input always valid, result and info always invalid
526 case lir_prefetchw: // input always valid, result and info always invalid
527 {
528 assert(op->as_Op1() != NULL, "must be");
529 LIR_Op1* op1 = (LIR_Op1*)op;
531 if (op1->_info) do_info(op1->_info);
532 if (op1->_opr->is_valid()) do_input(op1->_opr);
533 if (op1->_result->is_valid()) do_output(op1->_result);
535 break;
536 }
538 case lir_safepoint:
539 {
540 assert(op->as_Op1() != NULL, "must be");
541 LIR_Op1* op1 = (LIR_Op1*)op;
543 assert(op1->_info != NULL, ""); do_info(op1->_info);
544 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
545 assert(op1->_result->is_illegal(), "safepoint does not produce value");
547 break;
548 }
550 // LIR_OpConvert;
551 case lir_convert: // input and result always valid, info always invalid
552 {
553 assert(op->as_OpConvert() != NULL, "must be");
554 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
556 assert(opConvert->_info == NULL, "must be");
557 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
558 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
559 #ifdef PPC
560 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
561 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
562 #endif
563 do_stub(opConvert->_stub);
565 break;
566 }
568 // LIR_OpBranch;
569 case lir_branch: // may have info, input and result register always invalid
570 case lir_cond_float_branch: // may have info, input and result register always invalid
571 {
572 assert(op->as_OpBranch() != NULL, "must be");
573 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
575 if (opBranch->_info != NULL) do_info(opBranch->_info);
576 assert(opBranch->_result->is_illegal(), "not used");
577 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
579 break;
580 }
583 // LIR_OpAllocObj
584 case lir_alloc_object:
585 {
586 assert(op->as_OpAllocObj() != NULL, "must be");
587 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
589 if (opAllocObj->_info) do_info(opAllocObj->_info);
590 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
591 do_temp(opAllocObj->_opr);
592 }
593 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
594 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
595 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
596 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
597 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
598 do_stub(opAllocObj->_stub);
599 break;
600 }
603 // LIR_OpRoundFP;
604 case lir_roundfp: {
605 assert(op->as_OpRoundFP() != NULL, "must be");
606 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
608 assert(op->_info == NULL, "info not used by this instruction");
609 assert(opRoundFP->_tmp->is_illegal(), "not used");
610 do_input(opRoundFP->_opr);
611 do_output(opRoundFP->_result);
613 break;
614 }
617 // LIR_Op2
618 case lir_cmp:
619 case lir_cmp_l2i:
620 case lir_ucmp_fd2i:
621 case lir_cmp_fd2i:
622 case lir_add:
623 case lir_sub:
624 case lir_mul:
625 case lir_div:
626 case lir_rem:
627 case lir_sqrt:
628 case lir_abs:
629 case lir_logic_and:
630 case lir_logic_or:
631 case lir_logic_xor:
632 case lir_shl:
633 case lir_shr:
634 case lir_ushr:
635 case lir_xadd:
636 case lir_xchg:
637 case lir_assert:
638 {
639 assert(op->as_Op2() != NULL, "must be");
640 LIR_Op2* op2 = (LIR_Op2*)op;
641 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
642 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
644 if (op2->_info) do_info(op2->_info);
645 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
646 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
647 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
648 if (op2->_result->is_valid()) do_output(op2->_result);
649 if (op->code() == lir_xchg || op->code() == lir_xadd) {
650 // on ARM and PPC, return value is loaded first so could
651 // destroy inputs. On other platforms that implement those
652 // (x86, sparc), the extra constrainsts are harmless.
653 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
654 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
655 }
657 break;
658 }
660 // special handling for cmove: right input operand must not be equal
661 // to the result operand, otherwise the backend fails
662 case lir_cmove:
663 {
664 assert(op->as_Op2() != NULL, "must be");
665 LIR_Op2* op2 = (LIR_Op2*)op;
667 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
668 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
669 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
671 do_input(op2->_opr1);
672 do_input(op2->_opr2);
673 do_temp(op2->_opr2);
674 do_output(op2->_result);
676 break;
677 }
679 // vspecial handling for strict operations: register input operands
680 // as temp to guarantee that they do not overlap with other
681 // registers
682 case lir_mul_strictfp:
683 case lir_div_strictfp:
684 {
685 assert(op->as_Op2() != NULL, "must be");
686 LIR_Op2* op2 = (LIR_Op2*)op;
688 assert(op2->_info == NULL, "not used");
689 assert(op2->_opr1->is_valid(), "used");
690 assert(op2->_opr2->is_valid(), "used");
691 assert(op2->_result->is_valid(), "used");
692 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
693 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
695 do_input(op2->_opr1); do_temp(op2->_opr1);
696 do_input(op2->_opr2); do_temp(op2->_opr2);
697 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
698 do_output(op2->_result);
700 break;
701 }
703 case lir_throw: {
704 assert(op->as_Op2() != NULL, "must be");
705 LIR_Op2* op2 = (LIR_Op2*)op;
707 if (op2->_info) do_info(op2->_info);
708 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
709 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
710 assert(op2->_result->is_illegal(), "no result");
711 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
712 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
714 break;
715 }
717 case lir_unwind: {
718 assert(op->as_Op1() != NULL, "must be");
719 LIR_Op1* op1 = (LIR_Op1*)op;
721 assert(op1->_info == NULL, "no info");
722 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
723 assert(op1->_result->is_illegal(), "no result");
725 break;
726 }
729 case lir_tan:
730 case lir_sin:
731 case lir_cos:
732 case lir_log:
733 case lir_log10:
734 case lir_exp: {
735 assert(op->as_Op2() != NULL, "must be");
736 LIR_Op2* op2 = (LIR_Op2*)op;
738 // On x86 tan/sin/cos need two temporary fpu stack slots and
739 // log/log10 need one so handle opr2 and tmp as temp inputs.
740 // Register input operand as temp to guarantee that it doesn't
741 // overlap with the input.
742 assert(op2->_info == NULL, "not used");
743 assert(op2->_tmp5->is_illegal(), "not used");
744 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
745 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
746 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
747 assert(op2->_opr1->is_valid(), "used");
748 do_input(op2->_opr1); do_temp(op2->_opr1);
750 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
751 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
752 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
753 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
754 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
755 if (op2->_result->is_valid()) do_output(op2->_result);
757 break;
758 }
760 case lir_pow: {
761 assert(op->as_Op2() != NULL, "must be");
762 LIR_Op2* op2 = (LIR_Op2*)op;
764 // On x86 pow needs two temporary fpu stack slots: tmp1 and
765 // tmp2. Register input operands as temps to guarantee that it
766 // doesn't overlap with the temporary slots.
767 assert(op2->_info == NULL, "not used");
768 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
769 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
770 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
771 assert(op2->_result->is_valid(), "used");
773 do_input(op2->_opr1); do_temp(op2->_opr1);
774 do_input(op2->_opr2); do_temp(op2->_opr2);
775 do_temp(op2->_tmp1);
776 do_temp(op2->_tmp2);
777 do_temp(op2->_tmp3);
778 do_temp(op2->_tmp4);
779 do_temp(op2->_tmp5);
780 do_output(op2->_result);
782 break;
783 }
785 // LIR_Op3
786 case lir_idiv:
787 case lir_irem: {
788 assert(op->as_Op3() != NULL, "must be");
789 LIR_Op3* op3= (LIR_Op3*)op;
791 if (op3->_info) do_info(op3->_info);
792 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
794 // second operand is input and temp, so ensure that second operand
795 // and third operand get not the same register
796 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
797 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
798 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
800 if (op3->_result->is_valid()) do_output(op3->_result);
802 break;
803 }
806 // LIR_OpJavaCall
807 case lir_static_call:
808 case lir_optvirtual_call:
809 case lir_icvirtual_call:
810 case lir_virtual_call:
811 case lir_dynamic_call: {
812 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
813 assert(opJavaCall != NULL, "must be");
815 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
817 // only visit register parameters
818 int n = opJavaCall->_arguments->length();
819 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
820 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
821 do_input(*opJavaCall->_arguments->adr_at(i));
822 }
823 }
825 if (opJavaCall->_info) do_info(opJavaCall->_info);
826 if (opJavaCall->is_method_handle_invoke()) {
827 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
828 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
829 }
830 do_call();
831 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
833 break;
834 }
837 // LIR_OpRTCall
838 case lir_rtcall: {
839 assert(op->as_OpRTCall() != NULL, "must be");
840 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
842 // only visit register parameters
843 int n = opRTCall->_arguments->length();
844 for (int i = 0; i < n; i++) {
845 if (!opRTCall->_arguments->at(i)->is_pointer()) {
846 do_input(*opRTCall->_arguments->adr_at(i));
847 }
848 }
849 if (opRTCall->_info) do_info(opRTCall->_info);
850 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
851 do_call();
852 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
854 break;
855 }
858 // LIR_OpArrayCopy
859 case lir_arraycopy: {
860 assert(op->as_OpArrayCopy() != NULL, "must be");
861 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
863 assert(opArrayCopy->_result->is_illegal(), "unused");
864 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
865 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
866 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
867 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
868 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
869 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
870 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
872 // the implementation of arraycopy always has a call into the runtime
873 do_call();
875 break;
876 }
879 // LIR_OpLock
880 case lir_lock:
881 case lir_unlock: {
882 assert(op->as_OpLock() != NULL, "must be");
883 LIR_OpLock* opLock = (LIR_OpLock*)op;
885 if (opLock->_info) do_info(opLock->_info);
887 // TODO: check if these operands really have to be temp
888 // (or if input is sufficient). This may have influence on the oop map!
889 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
890 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
891 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
893 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
894 assert(opLock->_result->is_illegal(), "unused");
896 do_stub(opLock->_stub);
898 break;
899 }
902 // LIR_OpDelay
903 case lir_delay_slot: {
904 assert(op->as_OpDelay() != NULL, "must be");
905 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
907 visit(opDelay->delay_op());
908 break;
909 }
911 // LIR_OpTypeCheck
912 case lir_instanceof:
913 case lir_checkcast:
914 case lir_store_check: {
915 assert(op->as_OpTypeCheck() != NULL, "must be");
916 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
918 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
919 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
920 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
921 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
922 do_temp(opTypeCheck->_object);
923 }
924 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
925 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
926 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
927 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
928 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
929 do_stub(opTypeCheck->_stub);
930 break;
931 }
933 // LIR_OpCompareAndSwap
934 case lir_cas_long:
935 case lir_cas_obj:
936 case lir_cas_int: {
937 assert(op->as_OpCompareAndSwap() != NULL, "must be");
938 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
940 assert(opCompareAndSwap->_addr->is_valid(), "used");
941 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
942 assert(opCompareAndSwap->_new_value->is_valid(), "used");
943 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
944 do_input(opCompareAndSwap->_addr);
945 do_temp(opCompareAndSwap->_addr);
946 do_input(opCompareAndSwap->_cmp_value);
947 do_temp(opCompareAndSwap->_cmp_value);
948 do_input(opCompareAndSwap->_new_value);
949 do_temp(opCompareAndSwap->_new_value);
950 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
951 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
952 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
954 break;
955 }
958 // LIR_OpAllocArray;
959 case lir_alloc_array: {
960 assert(op->as_OpAllocArray() != NULL, "must be");
961 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
963 if (opAllocArray->_info) do_info(opAllocArray->_info);
964 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
965 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
966 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
967 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
968 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
969 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
970 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
971 do_stub(opAllocArray->_stub);
972 break;
973 }
975 // LIR_OpProfileCall:
976 case lir_profile_call: {
977 assert(op->as_OpProfileCall() != NULL, "must be");
978 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
980 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
981 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
982 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
983 break;
984 }
985 default:
986 ShouldNotReachHere();
987 }
988 }
991 void LIR_OpVisitState::do_stub(CodeStub* stub) {
992 if (stub != NULL) {
993 stub->visit(this);
994 }
995 }
997 XHandlers* LIR_OpVisitState::all_xhandler() {
998 XHandlers* result = NULL;
1000 int i;
1001 for (i = 0; i < info_count(); i++) {
1002 if (info_at(i)->exception_handlers() != NULL) {
1003 result = info_at(i)->exception_handlers();
1004 break;
1005 }
1006 }
1008 #ifdef ASSERT
1009 for (i = 0; i < info_count(); i++) {
1010 assert(info_at(i)->exception_handlers() == NULL ||
1011 info_at(i)->exception_handlers() == result,
1012 "only one xhandler list allowed per LIR-operation");
1013 }
1014 #endif
1016 if (result != NULL) {
1017 return result;
1018 } else {
1019 return new XHandlers();
1020 }
1022 return result;
1023 }
1026 #ifdef ASSERT
1027 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1028 visit(op);
1030 return opr_count(inputMode) == 0 &&
1031 opr_count(outputMode) == 0 &&
1032 opr_count(tempMode) == 0 &&
1033 info_count() == 0 &&
1034 !has_call() &&
1035 !has_slow_case();
1036 }
1037 #endif
1039 //---------------------------------------------------
1042 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1043 masm->emit_call(this);
1044 }
1046 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1047 masm->emit_rtcall(this);
1048 }
1050 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1051 masm->emit_opLabel(this);
1052 }
1054 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1055 masm->emit_arraycopy(this);
1056 masm->emit_code_stub(stub());
1057 }
1059 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1060 masm->emit_op0(this);
1061 }
1063 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1064 masm->emit_op1(this);
1065 }
1067 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1068 masm->emit_alloc_obj(this);
1069 masm->emit_code_stub(stub());
1070 }
1072 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1073 masm->emit_opBranch(this);
1074 if (stub()) {
1075 masm->emit_code_stub(stub());
1076 }
1077 }
1079 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1080 masm->emit_opConvert(this);
1081 if (stub() != NULL) {
1082 masm->emit_code_stub(stub());
1083 }
1084 }
1086 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1087 masm->emit_op2(this);
1088 }
1090 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1091 masm->emit_alloc_array(this);
1092 masm->emit_code_stub(stub());
1093 }
1095 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1096 masm->emit_opTypeCheck(this);
1097 if (stub()) {
1098 masm->emit_code_stub(stub());
1099 }
1100 }
1102 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1103 masm->emit_compare_and_swap(this);
1104 }
1106 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1107 masm->emit_op3(this);
1108 }
1110 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1111 masm->emit_lock(this);
1112 if (stub()) {
1113 masm->emit_code_stub(stub());
1114 }
1115 }
1117 #ifdef ASSERT
1118 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1119 masm->emit_assert(this);
1120 }
1121 #endif
1123 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1124 masm->emit_delay(this);
1125 }
1127 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1128 masm->emit_profile_call(this);
1129 }
1131 // LIR_List
1132 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1133 : _operations(8)
1134 , _compilation(compilation)
1135 #ifndef PRODUCT
1136 , _block(block)
1137 #endif
1138 #ifdef ASSERT
1139 , _file(NULL)
1140 , _line(0)
1141 #endif
1142 { }
1145 #ifdef ASSERT
1146 void LIR_List::set_file_and_line(const char * file, int line) {
1147 const char * f = strrchr(file, '/');
1148 if (f == NULL) f = strrchr(file, '\\');
1149 if (f == NULL) {
1150 f = file;
1151 } else {
1152 f++;
1153 }
1154 _file = f;
1155 _line = line;
1156 }
1157 #endif
1160 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1161 assert(this == buffer->lir_list(), "wrong lir list");
1162 const int n = _operations.length();
1164 if (buffer->number_of_ops() > 0) {
1165 // increase size of instructions list
1166 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1167 // insert ops from buffer into instructions list
1168 int op_index = buffer->number_of_ops() - 1;
1169 int ip_index = buffer->number_of_insertion_points() - 1;
1170 int from_index = n - 1;
1171 int to_index = _operations.length() - 1;
1172 for (; ip_index >= 0; ip_index --) {
1173 int index = buffer->index_at(ip_index);
1174 // make room after insertion point
1175 while (index < from_index) {
1176 _operations.at_put(to_index --, _operations.at(from_index --));
1177 }
1178 // insert ops from buffer
1179 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1180 _operations.at_put(to_index --, buffer->op_at(op_index --));
1181 }
1182 }
1183 }
1185 buffer->finish();
1186 }
1189 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1190 assert(reg->type() == T_OBJECT, "bad reg");
1191 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1192 }
1194 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1195 assert(reg->type() == T_METADATA, "bad reg");
1196 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1197 }
1199 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1200 append(new LIR_Op1(
1201 lir_move,
1202 LIR_OprFact::address(addr),
1203 src,
1204 addr->type(),
1205 patch_code,
1206 info));
1207 }
1210 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1211 append(new LIR_Op1(
1212 lir_move,
1213 LIR_OprFact::address(address),
1214 dst,
1215 address->type(),
1216 patch_code,
1217 info, lir_move_volatile));
1218 }
1220 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1221 append(new LIR_Op1(
1222 lir_move,
1223 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1224 dst,
1225 type,
1226 patch_code,
1227 info, lir_move_volatile));
1228 }
1231 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1232 append(new LIR_Op1(
1233 is_store ? lir_prefetchw : lir_prefetchr,
1234 LIR_OprFact::address(addr)));
1235 }
1238 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1239 append(new LIR_Op1(
1240 lir_move,
1241 LIR_OprFact::intConst(v),
1242 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1243 type,
1244 patch_code,
1245 info));
1246 }
1249 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1250 append(new LIR_Op1(
1251 lir_move,
1252 LIR_OprFact::oopConst(o),
1253 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1254 type,
1255 patch_code,
1256 info));
1257 }
1260 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1261 append(new LIR_Op1(
1262 lir_move,
1263 src,
1264 LIR_OprFact::address(addr),
1265 addr->type(),
1266 patch_code,
1267 info));
1268 }
1271 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1272 append(new LIR_Op1(
1273 lir_move,
1274 src,
1275 LIR_OprFact::address(addr),
1276 addr->type(),
1277 patch_code,
1278 info,
1279 lir_move_volatile));
1280 }
1282 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1283 append(new LIR_Op1(
1284 lir_move,
1285 src,
1286 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1287 type,
1288 patch_code,
1289 info, lir_move_volatile));
1290 }
1293 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1294 append(new LIR_Op3(
1295 lir_idiv,
1296 left,
1297 right,
1298 tmp,
1299 res,
1300 info));
1301 }
1304 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1305 append(new LIR_Op3(
1306 lir_idiv,
1307 left,
1308 LIR_OprFact::intConst(right),
1309 tmp,
1310 res,
1311 info));
1312 }
1315 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1316 append(new LIR_Op3(
1317 lir_irem,
1318 left,
1319 right,
1320 tmp,
1321 res,
1322 info));
1323 }
1326 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1327 append(new LIR_Op3(
1328 lir_irem,
1329 left,
1330 LIR_OprFact::intConst(right),
1331 tmp,
1332 res,
1333 info));
1334 }
1337 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1338 append(new LIR_Op2(
1339 lir_cmp,
1340 condition,
1341 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1342 LIR_OprFact::intConst(c),
1343 info));
1344 }
1347 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1348 append(new LIR_Op2(
1349 lir_cmp,
1350 condition,
1351 reg,
1352 LIR_OprFact::address(addr),
1353 info));
1354 }
1356 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1357 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1358 append(new LIR_OpAllocObj(
1359 klass,
1360 dst,
1361 t1,
1362 t2,
1363 t3,
1364 t4,
1365 header_size,
1366 object_size,
1367 init_check,
1368 stub));
1369 }
1371 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1372 append(new LIR_OpAllocArray(
1373 klass,
1374 len,
1375 dst,
1376 t1,
1377 t2,
1378 t3,
1379 t4,
1380 type,
1381 stub));
1382 }
1384 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1385 append(new LIR_Op2(
1386 lir_shl,
1387 value,
1388 count,
1389 dst,
1390 tmp));
1391 }
1393 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1394 append(new LIR_Op2(
1395 lir_shr,
1396 value,
1397 count,
1398 dst,
1399 tmp));
1400 }
1403 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1404 append(new LIR_Op2(
1405 lir_ushr,
1406 value,
1407 count,
1408 dst,
1409 tmp));
1410 }
1412 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1413 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1414 left,
1415 right,
1416 dst));
1417 }
1419 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1420 append(new LIR_OpLock(
1421 lir_lock,
1422 hdr,
1423 obj,
1424 lock,
1425 scratch,
1426 stub,
1427 info));
1428 }
1430 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1431 append(new LIR_OpLock(
1432 lir_unlock,
1433 hdr,
1434 obj,
1435 lock,
1436 scratch,
1437 stub,
1438 NULL));
1439 }
1442 void check_LIR() {
1443 // cannot do the proper checking as PRODUCT and other modes return different results
1444 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1445 }
1449 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1450 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1451 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1452 ciMethod* profiled_method, int profiled_bci) {
1453 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1454 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1455 if (profiled_method != NULL) {
1456 c->set_profiled_method(profiled_method);
1457 c->set_profiled_bci(profiled_bci);
1458 c->set_should_profile(true);
1459 }
1460 append(c);
1461 }
1463 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1464 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1465 if (profiled_method != NULL) {
1466 c->set_profiled_method(profiled_method);
1467 c->set_profiled_bci(profiled_bci);
1468 c->set_should_profile(true);
1469 }
1470 append(c);
1471 }
1474 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1475 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1476 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1477 if (profiled_method != NULL) {
1478 c->set_profiled_method(profiled_method);
1479 c->set_profiled_bci(profiled_bci);
1480 c->set_should_profile(true);
1481 }
1482 append(c);
1483 }
1486 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1487 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1488 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1489 }
1491 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1492 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1493 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1494 }
1496 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1497 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1498 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1499 }
1502 #ifdef PRODUCT
1504 void print_LIR(BlockList* blocks) {
1505 }
1507 #else
1508 // LIR_OprDesc
1509 void LIR_OprDesc::print() const {
1510 print(tty);
1511 }
1513 void LIR_OprDesc::print(outputStream* out) const {
1514 if (is_illegal()) {
1515 return;
1516 }
1518 out->print("[");
1519 if (is_pointer()) {
1520 pointer()->print_value_on(out);
1521 } else if (is_single_stack()) {
1522 out->print("stack:%d", single_stack_ix());
1523 } else if (is_double_stack()) {
1524 out->print("dbl_stack:%d",double_stack_ix());
1525 } else if (is_virtual()) {
1526 out->print("R%d", vreg_number());
1527 } else if (is_single_cpu()) {
1528 out->print(as_register()->name());
1529 } else if (is_double_cpu()) {
1530 out->print(as_register_hi()->name());
1531 out->print(as_register_lo()->name());
1532 #if defined(X86)
1533 } else if (is_single_xmm()) {
1534 out->print(as_xmm_float_reg()->name());
1535 } else if (is_double_xmm()) {
1536 out->print(as_xmm_double_reg()->name());
1537 } else if (is_single_fpu()) {
1538 out->print("fpu%d", fpu_regnr());
1539 } else if (is_double_fpu()) {
1540 out->print("fpu%d", fpu_regnrLo());
1541 #elif defined(ARM)
1542 } else if (is_single_fpu()) {
1543 out->print("s%d", fpu_regnr());
1544 } else if (is_double_fpu()) {
1545 out->print("d%d", fpu_regnrLo() >> 1);
1546 #else
1547 } else if (is_single_fpu()) {
1548 out->print(as_float_reg()->name());
1549 } else if (is_double_fpu()) {
1550 out->print(as_double_reg()->name());
1551 #endif
1553 } else if (is_illegal()) {
1554 out->print("-");
1555 } else {
1556 out->print("Unknown Operand");
1557 }
1558 if (!is_illegal()) {
1559 out->print("|%c", type_char());
1560 }
1561 if (is_register() && is_last_use()) {
1562 out->print("(last_use)");
1563 }
1564 out->print("]");
1565 }
1568 // LIR_Address
1569 void LIR_Const::print_value_on(outputStream* out) const {
1570 switch (type()) {
1571 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1572 case T_INT: out->print("int:%d", as_jint()); break;
1573 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1574 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1575 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1576 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1577 case T_METADATA: out->print("metadata:0x%x", as_metadata());break;
1578 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1579 }
1580 }
1582 // LIR_Address
1583 void LIR_Address::print_value_on(outputStream* out) const {
1584 out->print("Base:"); _base->print(out);
1585 if (!_index->is_illegal()) {
1586 out->print(" Index:"); _index->print(out);
1587 switch (scale()) {
1588 case times_1: break;
1589 case times_2: out->print(" * 2"); break;
1590 case times_4: out->print(" * 4"); break;
1591 case times_8: out->print(" * 8"); break;
1592 }
1593 }
1594 out->print(" Disp: %d", _disp);
1595 }
1597 // debug output of block header without InstructionPrinter
1598 // (because phi functions are not necessary for LIR)
1599 static void print_block(BlockBegin* x) {
1600 // print block id
1601 BlockEnd* end = x->end();
1602 tty->print("B%d ", x->block_id());
1604 // print flags
1605 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1606 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1607 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1608 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1609 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1610 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1611 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1613 // print block bci range
1614 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1616 // print predecessors and successors
1617 if (x->number_of_preds() > 0) {
1618 tty->print("preds: ");
1619 for (int i = 0; i < x->number_of_preds(); i ++) {
1620 tty->print("B%d ", x->pred_at(i)->block_id());
1621 }
1622 }
1624 if (x->number_of_sux() > 0) {
1625 tty->print("sux: ");
1626 for (int i = 0; i < x->number_of_sux(); i ++) {
1627 tty->print("B%d ", x->sux_at(i)->block_id());
1628 }
1629 }
1631 // print exception handlers
1632 if (x->number_of_exception_handlers() > 0) {
1633 tty->print("xhandler: ");
1634 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1635 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1636 }
1637 }
1639 tty->cr();
1640 }
1642 void print_LIR(BlockList* blocks) {
1643 tty->print_cr("LIR:");
1644 int i;
1645 for (i = 0; i < blocks->length(); i++) {
1646 BlockBegin* bb = blocks->at(i);
1647 print_block(bb);
1648 tty->print("__id_Instruction___________________________________________"); tty->cr();
1649 bb->lir()->print_instructions();
1650 }
1651 }
1653 void LIR_List::print_instructions() {
1654 for (int i = 0; i < _operations.length(); i++) {
1655 _operations.at(i)->print(); tty->cr();
1656 }
1657 tty->cr();
1658 }
1660 // LIR_Ops printing routines
1661 // LIR_Op
1662 void LIR_Op::print_on(outputStream* out) const {
1663 if (id() != -1 || PrintCFGToFile) {
1664 out->print("%4d ", id());
1665 } else {
1666 out->print(" ");
1667 }
1668 out->print(name()); out->print(" ");
1669 print_instr(out);
1670 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1671 #ifdef ASSERT
1672 if (Verbose && _file != NULL) {
1673 out->print(" (%s:%d)", _file, _line);
1674 }
1675 #endif
1676 }
1678 const char * LIR_Op::name() const {
1679 const char* s = NULL;
1680 switch(code()) {
1681 // LIR_Op0
1682 case lir_membar: s = "membar"; break;
1683 case lir_membar_acquire: s = "membar_acquire"; break;
1684 case lir_membar_release: s = "membar_release"; break;
1685 case lir_membar_loadload: s = "membar_loadload"; break;
1686 case lir_membar_storestore: s = "membar_storestore"; break;
1687 case lir_membar_loadstore: s = "membar_loadstore"; break;
1688 case lir_membar_storeload: s = "membar_storeload"; break;
1689 case lir_word_align: s = "word_align"; break;
1690 case lir_label: s = "label"; break;
1691 case lir_nop: s = "nop"; break;
1692 case lir_backwardbranch_target: s = "backbranch"; break;
1693 case lir_std_entry: s = "std_entry"; break;
1694 case lir_osr_entry: s = "osr_entry"; break;
1695 case lir_build_frame: s = "build_frm"; break;
1696 case lir_fpop_raw: s = "fpop_raw"; break;
1697 case lir_24bit_FPU: s = "24bit_FPU"; break;
1698 case lir_reset_FPU: s = "reset_FPU"; break;
1699 case lir_breakpoint: s = "breakpoint"; break;
1700 case lir_get_thread: s = "get_thread"; break;
1701 // LIR_Op1
1702 case lir_fxch: s = "fxch"; break;
1703 case lir_fld: s = "fld"; break;
1704 case lir_ffree: s = "ffree"; break;
1705 case lir_push: s = "push"; break;
1706 case lir_pop: s = "pop"; break;
1707 case lir_null_check: s = "null_check"; break;
1708 case lir_return: s = "return"; break;
1709 case lir_safepoint: s = "safepoint"; break;
1710 case lir_neg: s = "neg"; break;
1711 case lir_leal: s = "leal"; break;
1712 case lir_branch: s = "branch"; break;
1713 case lir_cond_float_branch: s = "flt_cond_br"; break;
1714 case lir_move: s = "move"; break;
1715 case lir_roundfp: s = "roundfp"; break;
1716 case lir_rtcall: s = "rtcall"; break;
1717 case lir_throw: s = "throw"; break;
1718 case lir_unwind: s = "unwind"; break;
1719 case lir_convert: s = "convert"; break;
1720 case lir_alloc_object: s = "alloc_obj"; break;
1721 case lir_monaddr: s = "mon_addr"; break;
1722 case lir_pack64: s = "pack64"; break;
1723 case lir_unpack64: s = "unpack64"; break;
1724 // LIR_Op2
1725 case lir_cmp: s = "cmp"; break;
1726 case lir_cmp_l2i: s = "cmp_l2i"; break;
1727 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1728 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1729 case lir_cmove: s = "cmove"; break;
1730 case lir_add: s = "add"; break;
1731 case lir_sub: s = "sub"; break;
1732 case lir_mul: s = "mul"; break;
1733 case lir_mul_strictfp: s = "mul_strictfp"; break;
1734 case lir_div: s = "div"; break;
1735 case lir_div_strictfp: s = "div_strictfp"; break;
1736 case lir_rem: s = "rem"; break;
1737 case lir_abs: s = "abs"; break;
1738 case lir_sqrt: s = "sqrt"; break;
1739 case lir_sin: s = "sin"; break;
1740 case lir_cos: s = "cos"; break;
1741 case lir_tan: s = "tan"; break;
1742 case lir_log: s = "log"; break;
1743 case lir_log10: s = "log10"; break;
1744 case lir_exp: s = "exp"; break;
1745 case lir_pow: s = "pow"; break;
1746 case lir_logic_and: s = "logic_and"; break;
1747 case lir_logic_or: s = "logic_or"; break;
1748 case lir_logic_xor: s = "logic_xor"; break;
1749 case lir_shl: s = "shift_left"; break;
1750 case lir_shr: s = "shift_right"; break;
1751 case lir_ushr: s = "ushift_right"; break;
1752 case lir_alloc_array: s = "alloc_array"; break;
1753 case lir_xadd: s = "xadd"; break;
1754 case lir_xchg: s = "xchg"; break;
1755 // LIR_Op3
1756 case lir_idiv: s = "idiv"; break;
1757 case lir_irem: s = "irem"; break;
1758 // LIR_OpJavaCall
1759 case lir_static_call: s = "static"; break;
1760 case lir_optvirtual_call: s = "optvirtual"; break;
1761 case lir_icvirtual_call: s = "icvirtual"; break;
1762 case lir_virtual_call: s = "virtual"; break;
1763 case lir_dynamic_call: s = "dynamic"; break;
1764 // LIR_OpArrayCopy
1765 case lir_arraycopy: s = "arraycopy"; break;
1766 // LIR_OpLock
1767 case lir_lock: s = "lock"; break;
1768 case lir_unlock: s = "unlock"; break;
1769 // LIR_OpDelay
1770 case lir_delay_slot: s = "delay"; break;
1771 // LIR_OpTypeCheck
1772 case lir_instanceof: s = "instanceof"; break;
1773 case lir_checkcast: s = "checkcast"; break;
1774 case lir_store_check: s = "store_check"; break;
1775 // LIR_OpCompareAndSwap
1776 case lir_cas_long: s = "cas_long"; break;
1777 case lir_cas_obj: s = "cas_obj"; break;
1778 case lir_cas_int: s = "cas_int"; break;
1779 // LIR_OpProfileCall
1780 case lir_profile_call: s = "profile_call"; break;
1781 // LIR_OpAssert
1782 #ifdef ASSERT
1783 case lir_assert: s = "assert"; break;
1784 #endif
1785 case lir_none: ShouldNotReachHere();break;
1786 default: s = "illegal_op"; break;
1787 }
1788 return s;
1789 }
1791 // LIR_OpJavaCall
1792 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1793 out->print("call: ");
1794 out->print("[addr: 0x%x]", address());
1795 if (receiver()->is_valid()) {
1796 out->print(" [recv: "); receiver()->print(out); out->print("]");
1797 }
1798 if (result_opr()->is_valid()) {
1799 out->print(" [result: "); result_opr()->print(out); out->print("]");
1800 }
1801 }
1803 // LIR_OpLabel
1804 void LIR_OpLabel::print_instr(outputStream* out) const {
1805 out->print("[label:0x%x]", _label);
1806 }
1808 // LIR_OpArrayCopy
1809 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1810 src()->print(out); out->print(" ");
1811 src_pos()->print(out); out->print(" ");
1812 dst()->print(out); out->print(" ");
1813 dst_pos()->print(out); out->print(" ");
1814 length()->print(out); out->print(" ");
1815 tmp()->print(out); out->print(" ");
1816 }
1818 // LIR_OpCompareAndSwap
1819 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1820 addr()->print(out); out->print(" ");
1821 cmp_value()->print(out); out->print(" ");
1822 new_value()->print(out); out->print(" ");
1823 tmp1()->print(out); out->print(" ");
1824 tmp2()->print(out); out->print(" ");
1826 }
1828 // LIR_Op0
1829 void LIR_Op0::print_instr(outputStream* out) const {
1830 result_opr()->print(out);
1831 }
1833 // LIR_Op1
1834 const char * LIR_Op1::name() const {
1835 if (code() == lir_move) {
1836 switch (move_kind()) {
1837 case lir_move_normal:
1838 return "move";
1839 case lir_move_unaligned:
1840 return "unaligned move";
1841 case lir_move_volatile:
1842 return "volatile_move";
1843 case lir_move_wide:
1844 return "wide_move";
1845 default:
1846 ShouldNotReachHere();
1847 return "illegal_op";
1848 }
1849 } else {
1850 return LIR_Op::name();
1851 }
1852 }
1855 void LIR_Op1::print_instr(outputStream* out) const {
1856 _opr->print(out); out->print(" ");
1857 result_opr()->print(out); out->print(" ");
1858 print_patch_code(out, patch_code());
1859 }
1862 // LIR_Op1
1863 void LIR_OpRTCall::print_instr(outputStream* out) const {
1864 intx a = (intx)addr();
1865 out->print(Runtime1::name_for_address(addr()));
1866 out->print(" ");
1867 tmp()->print(out);
1868 }
1870 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1871 switch(code) {
1872 case lir_patch_none: break;
1873 case lir_patch_low: out->print("[patch_low]"); break;
1874 case lir_patch_high: out->print("[patch_high]"); break;
1875 case lir_patch_normal: out->print("[patch_normal]"); break;
1876 default: ShouldNotReachHere();
1877 }
1878 }
1880 // LIR_OpBranch
1881 void LIR_OpBranch::print_instr(outputStream* out) const {
1882 print_condition(out, cond()); out->print(" ");
1883 if (block() != NULL) {
1884 out->print("[B%d] ", block()->block_id());
1885 } else if (stub() != NULL) {
1886 out->print("[");
1887 stub()->print_name(out);
1888 out->print(": 0x%x]", stub());
1889 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1890 } else {
1891 out->print("[label:0x%x] ", label());
1892 }
1893 if (ublock() != NULL) {
1894 out->print("unordered: [B%d] ", ublock()->block_id());
1895 }
1896 }
1898 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1899 switch(cond) {
1900 case lir_cond_equal: out->print("[EQ]"); break;
1901 case lir_cond_notEqual: out->print("[NE]"); break;
1902 case lir_cond_less: out->print("[LT]"); break;
1903 case lir_cond_lessEqual: out->print("[LE]"); break;
1904 case lir_cond_greaterEqual: out->print("[GE]"); break;
1905 case lir_cond_greater: out->print("[GT]"); break;
1906 case lir_cond_belowEqual: out->print("[BE]"); break;
1907 case lir_cond_aboveEqual: out->print("[AE]"); break;
1908 case lir_cond_always: out->print("[AL]"); break;
1909 default: out->print("[%d]",cond); break;
1910 }
1911 }
1913 // LIR_OpConvert
1914 void LIR_OpConvert::print_instr(outputStream* out) const {
1915 print_bytecode(out, bytecode());
1916 in_opr()->print(out); out->print(" ");
1917 result_opr()->print(out); out->print(" ");
1918 #ifdef PPC
1919 if(tmp1()->is_valid()) {
1920 tmp1()->print(out); out->print(" ");
1921 tmp2()->print(out); out->print(" ");
1922 }
1923 #endif
1924 }
1926 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1927 switch(code) {
1928 case Bytecodes::_d2f: out->print("[d2f] "); break;
1929 case Bytecodes::_d2i: out->print("[d2i] "); break;
1930 case Bytecodes::_d2l: out->print("[d2l] "); break;
1931 case Bytecodes::_f2d: out->print("[f2d] "); break;
1932 case Bytecodes::_f2i: out->print("[f2i] "); break;
1933 case Bytecodes::_f2l: out->print("[f2l] "); break;
1934 case Bytecodes::_i2b: out->print("[i2b] "); break;
1935 case Bytecodes::_i2c: out->print("[i2c] "); break;
1936 case Bytecodes::_i2d: out->print("[i2d] "); break;
1937 case Bytecodes::_i2f: out->print("[i2f] "); break;
1938 case Bytecodes::_i2l: out->print("[i2l] "); break;
1939 case Bytecodes::_i2s: out->print("[i2s] "); break;
1940 case Bytecodes::_l2i: out->print("[l2i] "); break;
1941 case Bytecodes::_l2f: out->print("[l2f] "); break;
1942 case Bytecodes::_l2d: out->print("[l2d] "); break;
1943 default:
1944 out->print("[?%d]",code);
1945 break;
1946 }
1947 }
1949 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1950 klass()->print(out); out->print(" ");
1951 obj()->print(out); out->print(" ");
1952 tmp1()->print(out); out->print(" ");
1953 tmp2()->print(out); out->print(" ");
1954 tmp3()->print(out); out->print(" ");
1955 tmp4()->print(out); out->print(" ");
1956 out->print("[hdr:%d]", header_size()); out->print(" ");
1957 out->print("[obj:%d]", object_size()); out->print(" ");
1958 out->print("[lbl:0x%x]", stub()->entry());
1959 }
1961 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1962 _opr->print(out); out->print(" ");
1963 tmp()->print(out); out->print(" ");
1964 result_opr()->print(out); out->print(" ");
1965 }
1967 // LIR_Op2
1968 void LIR_Op2::print_instr(outputStream* out) const {
1969 if (code() == lir_cmove) {
1970 print_condition(out, condition()); out->print(" ");
1971 }
1972 in_opr1()->print(out); out->print(" ");
1973 in_opr2()->print(out); out->print(" ");
1974 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
1975 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
1976 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
1977 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
1978 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
1979 result_opr()->print(out);
1980 }
1982 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1983 klass()->print(out); out->print(" ");
1984 len()->print(out); out->print(" ");
1985 obj()->print(out); out->print(" ");
1986 tmp1()->print(out); out->print(" ");
1987 tmp2()->print(out); out->print(" ");
1988 tmp3()->print(out); out->print(" ");
1989 tmp4()->print(out); out->print(" ");
1990 out->print("[type:0x%x]", type()); out->print(" ");
1991 out->print("[label:0x%x]", stub()->entry());
1992 }
1995 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1996 object()->print(out); out->print(" ");
1997 if (code() == lir_store_check) {
1998 array()->print(out); out->print(" ");
1999 }
2000 if (code() != lir_store_check) {
2001 klass()->print_name_on(out); out->print(" ");
2002 if (fast_check()) out->print("fast_check ");
2003 }
2004 tmp1()->print(out); out->print(" ");
2005 tmp2()->print(out); out->print(" ");
2006 tmp3()->print(out); out->print(" ");
2007 result_opr()->print(out); out->print(" ");
2008 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2009 }
2012 // LIR_Op3
2013 void LIR_Op3::print_instr(outputStream* out) const {
2014 in_opr1()->print(out); out->print(" ");
2015 in_opr2()->print(out); out->print(" ");
2016 in_opr3()->print(out); out->print(" ");
2017 result_opr()->print(out);
2018 }
2021 void LIR_OpLock::print_instr(outputStream* out) const {
2022 hdr_opr()->print(out); out->print(" ");
2023 obj_opr()->print(out); out->print(" ");
2024 lock_opr()->print(out); out->print(" ");
2025 if (_scratch->is_valid()) {
2026 _scratch->print(out); out->print(" ");
2027 }
2028 out->print("[lbl:0x%x]", stub()->entry());
2029 }
2031 #ifdef ASSERT
2032 void LIR_OpAssert::print_instr(outputStream* out) const {
2033 print_condition(out, condition()); out->print(" ");
2034 in_opr1()->print(out); out->print(" ");
2035 in_opr2()->print(out); out->print(", \"");
2036 out->print(msg()); out->print("\"");
2037 }
2038 #endif
2041 void LIR_OpDelay::print_instr(outputStream* out) const {
2042 _op->print_on(out);
2043 }
2046 // LIR_OpProfileCall
2047 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2048 profiled_method()->name()->print_symbol_on(out);
2049 out->print(".");
2050 profiled_method()->holder()->name()->print_symbol_on(out);
2051 out->print(" @ %d ", profiled_bci());
2052 mdo()->print(out); out->print(" ");
2053 recv()->print(out); out->print(" ");
2054 tmp1()->print(out); out->print(" ");
2055 }
2057 #endif // PRODUCT
2059 // Implementation of LIR_InsertionBuffer
2061 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2062 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2064 int i = number_of_insertion_points() - 1;
2065 if (i < 0 || index_at(i) < index) {
2066 append_new(index, 1);
2067 } else {
2068 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2069 assert(count_at(i) > 0, "check");
2070 set_count_at(i, count_at(i) + 1);
2071 }
2072 _ops.push(op);
2074 DEBUG_ONLY(verify());
2075 }
2077 #ifdef ASSERT
2078 void LIR_InsertionBuffer::verify() {
2079 int sum = 0;
2080 int prev_idx = -1;
2082 for (int i = 0; i < number_of_insertion_points(); i++) {
2083 assert(prev_idx < index_at(i), "index must be ordered ascending");
2084 sum += count_at(i);
2085 }
2086 assert(sum == number_of_ops(), "wrong total sum");
2087 }
2088 #endif
