Fri, 25 Mar 2011 09:35:39 +0100
7029017: Additional architecture support for c2 compiler
Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it.
Reviewed-by: kvn, never
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25 #ifndef CPU_SPARC_VM_ICACHE_SPARC_HPP
26 #define CPU_SPARC_VM_ICACHE_SPARC_HPP
28 // Interface for updating the instruction cache. Whenever the VM modifies
29 // code, part of the processor instruction cache potentially has to be flushed.
32 class ICache : public AbstractICache {
33 public:
34 enum {
35 stub_size = 160, // Size of the icache flush stub in bytes
36 line_size = 8, // flush instruction affects a dword
37 log2_line_size = 3 // log2(line_size)
38 };
40 // Use default implementation
41 };
43 #endif // CPU_SPARC_VM_ICACHE_SPARC_HPP