Sun, 01 Jan 2012 11:17:59 -0500
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
Summary: Add rdtsc detection and inline generation.
Reviewed-by: kamg, dholmes
Contributed-by: karen.kinnear@oracle.com
1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
31 class VM_Version : public Abstract_VM_Version {
32 public:
33 // cpuid result register layouts. These are all unions of a uint32_t
34 // (in case anyone wants access to the register as a whole) and a bitfield.
36 union StdCpuid1Eax {
37 uint32_t value;
38 struct {
39 uint32_t stepping : 4,
40 model : 4,
41 family : 4,
42 proc_type : 2,
43 : 2,
44 ext_model : 4,
45 ext_family : 8,
46 : 4;
47 } bits;
48 };
50 union StdCpuid1Ebx { // example, unused
51 uint32_t value;
52 struct {
53 uint32_t brand_id : 8,
54 clflush_size : 8,
55 threads_per_cpu : 8,
56 apic_id : 8;
57 } bits;
58 };
60 union StdCpuid1Ecx {
61 uint32_t value;
62 struct {
63 uint32_t sse3 : 1,
64 : 2,
65 monitor : 1,
66 : 1,
67 vmx : 1,
68 : 1,
69 est : 1,
70 : 1,
71 ssse3 : 1,
72 cid : 1,
73 : 2,
74 cmpxchg16: 1,
75 : 4,
76 dca : 1,
77 sse4_1 : 1,
78 sse4_2 : 1,
79 : 2,
80 popcnt : 1,
81 : 8;
82 } bits;
83 };
85 union StdCpuid1Edx {
86 uint32_t value;
87 struct {
88 uint32_t : 4,
89 tsc : 1,
90 : 3,
91 cmpxchg8 : 1,
92 : 6,
93 cmov : 1,
94 : 3,
95 clflush : 1,
96 : 3,
97 mmx : 1,
98 fxsr : 1,
99 sse : 1,
100 sse2 : 1,
101 : 1,
102 ht : 1,
103 : 3;
104 } bits;
105 };
107 union DcpCpuid4Eax {
108 uint32_t value;
109 struct {
110 uint32_t cache_type : 5,
111 : 21,
112 cores_per_cpu : 6;
113 } bits;
114 };
116 union DcpCpuid4Ebx {
117 uint32_t value;
118 struct {
119 uint32_t L1_line_size : 12,
120 partitions : 10,
121 associativity : 10;
122 } bits;
123 };
125 union TplCpuidBEbx {
126 uint32_t value;
127 struct {
128 uint32_t logical_cpus : 16,
129 : 16;
130 } bits;
131 };
133 union ExtCpuid1Ecx {
134 uint32_t value;
135 struct {
136 uint32_t LahfSahf : 1,
137 CmpLegacy : 1,
138 : 4,
139 lzcnt : 1,
140 sse4a : 1,
141 misalignsse : 1,
142 prefetchw : 1,
143 : 22;
144 } bits;
145 };
147 union ExtCpuid1Edx {
148 uint32_t value;
149 struct {
150 uint32_t : 22,
151 mmx_amd : 1,
152 mmx : 1,
153 fxsr : 1,
154 : 4,
155 long_mode : 1,
156 tdnow2 : 1,
157 tdnow : 1;
158 } bits;
159 };
161 union ExtCpuid5Ex {
162 uint32_t value;
163 struct {
164 uint32_t L1_line_size : 8,
165 L1_tag_lines : 8,
166 L1_assoc : 8,
167 L1_size : 8;
168 } bits;
169 };
171 union ExtCpuid8Ecx {
172 uint32_t value;
173 struct {
174 uint32_t cores_per_cpu : 8,
175 : 24;
176 } bits;
177 };
179 union ExtCpuid7Edx {
180 uint32_t value;
181 struct {
182 uint32_t : 8,
183 tsc_invariance : 1,
184 : 23;
185 } bits;
186 };
188 protected:
189 static int _cpu;
190 static int _model;
191 static int _stepping;
192 static int _cpuFeatures; // features returned by the "cpuid" instruction
193 // 0 if this instruction is not available
194 static const char* _features_str;
196 enum {
197 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
198 CPU_CMOV = (1 << 1),
199 CPU_FXSR = (1 << 2),
200 CPU_HT = (1 << 3),
201 CPU_MMX = (1 << 4),
202 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
203 // may not necessarily support other 3dnow instructions
204 CPU_SSE = (1 << 6),
205 CPU_SSE2 = (1 << 7),
206 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
207 CPU_SSSE3 = (1 << 9),
208 CPU_SSE4A = (1 << 10),
209 CPU_SSE4_1 = (1 << 11),
210 CPU_SSE4_2 = (1 << 12),
211 CPU_POPCNT = (1 << 13),
212 CPU_LZCNT = (1 << 14),
213 CPU_TSC = (1 << 15),
214 CPU_TSCINV = (1 << 16)
215 } cpuFeatureFlags;
217 enum {
218 // AMD
219 CPU_FAMILY_AMD_11H = 17,
220 // Intel
221 CPU_FAMILY_INTEL_CORE = 6,
222 CPU_MODEL_NEHALEM_EP = 26,
223 CPU_MODEL_WESTMERE_EP = 44,
224 // CPU_MODEL_IVYBRIDGE_EP = ??, TODO - get real value
225 CPU_MODEL_SANDYBRIDGE_EP = 45
226 } cpuExtendedFamily;
228 // cpuid information block. All info derived from executing cpuid with
229 // various function numbers is stored here. Intel and AMD info is
230 // merged in this block: accessor methods disentangle it.
231 //
232 // The info block is laid out in subblocks of 4 dwords corresponding to
233 // eax, ebx, ecx and edx, whether or not they contain anything useful.
234 struct CpuidInfo {
235 // cpuid function 0
236 uint32_t std_max_function;
237 uint32_t std_vendor_name_0;
238 uint32_t std_vendor_name_1;
239 uint32_t std_vendor_name_2;
241 // cpuid function 1
242 StdCpuid1Eax std_cpuid1_eax;
243 StdCpuid1Ebx std_cpuid1_ebx;
244 StdCpuid1Ecx std_cpuid1_ecx;
245 StdCpuid1Edx std_cpuid1_edx;
247 // cpuid function 4 (deterministic cache parameters)
248 DcpCpuid4Eax dcp_cpuid4_eax;
249 DcpCpuid4Ebx dcp_cpuid4_ebx;
250 uint32_t dcp_cpuid4_ecx; // unused currently
251 uint32_t dcp_cpuid4_edx; // unused currently
253 // cpuid function 0xB (processor topology)
254 // ecx = 0
255 uint32_t tpl_cpuidB0_eax;
256 TplCpuidBEbx tpl_cpuidB0_ebx;
257 uint32_t tpl_cpuidB0_ecx; // unused currently
258 uint32_t tpl_cpuidB0_edx; // unused currently
260 // ecx = 1
261 uint32_t tpl_cpuidB1_eax;
262 TplCpuidBEbx tpl_cpuidB1_ebx;
263 uint32_t tpl_cpuidB1_ecx; // unused currently
264 uint32_t tpl_cpuidB1_edx; // unused currently
266 // ecx = 2
267 uint32_t tpl_cpuidB2_eax;
268 TplCpuidBEbx tpl_cpuidB2_ebx;
269 uint32_t tpl_cpuidB2_ecx; // unused currently
270 uint32_t tpl_cpuidB2_edx; // unused currently
272 // cpuid function 0x80000000 // example, unused
273 uint32_t ext_max_function;
274 uint32_t ext_vendor_name_0;
275 uint32_t ext_vendor_name_1;
276 uint32_t ext_vendor_name_2;
278 // cpuid function 0x80000001
279 uint32_t ext_cpuid1_eax; // reserved
280 uint32_t ext_cpuid1_ebx; // reserved
281 ExtCpuid1Ecx ext_cpuid1_ecx;
282 ExtCpuid1Edx ext_cpuid1_edx;
284 // cpuid functions 0x80000002 thru 0x80000004: example, unused
285 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
286 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
287 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
289 // cpuid function 0x80000005 //AMD L1, Intel reserved
290 uint32_t ext_cpuid5_eax; // unused currently
291 uint32_t ext_cpuid5_ebx; // reserved
292 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
293 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
295 // cpuid function 0x80000007
296 uint32_t ext_cpuid7_eax; // reserved
297 uint32_t ext_cpuid7_ebx; // reserved
298 uint32_t ext_cpuid7_ecx; // reserved
299 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
301 // cpuid function 0x80000008
302 uint32_t ext_cpuid8_eax; // unused currently
303 uint32_t ext_cpuid8_ebx; // reserved
304 ExtCpuid8Ecx ext_cpuid8_ecx;
305 uint32_t ext_cpuid8_edx; // reserved
306 };
308 // The actual cpuid info block
309 static CpuidInfo _cpuid_info;
311 // Extractors and predicates
312 static uint32_t extended_cpu_family() {
313 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
314 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
315 return result;
316 }
318 static uint32_t extended_cpu_model() {
319 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
320 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
321 return result;
322 }
324 static uint32_t cpu_stepping() {
325 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
326 return result;
327 }
329 static uint logical_processor_count() {
330 uint result = threads_per_core();
331 return result;
332 }
334 static uint32_t feature_flags() {
335 uint32_t result = 0;
336 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
337 result |= CPU_CX8;
338 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
339 result |= CPU_CMOV;
340 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
341 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
342 result |= CPU_FXSR;
343 // HT flag is set for multi-core processors also.
344 if (threads_per_core() > 1)
345 result |= CPU_HT;
346 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
347 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
348 result |= CPU_MMX;
349 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
350 result |= CPU_SSE;
351 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
352 result |= CPU_SSE2;
353 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
354 result |= CPU_SSE3;
355 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
356 result |= CPU_SSSE3;
357 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
358 result |= CPU_SSE4_1;
359 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
360 result |= CPU_SSE4_2;
361 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
362 result |= CPU_POPCNT;
363 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
364 result |= CPU_TSC;
365 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
366 result |= CPU_TSCINV;
368 // AMD features.
369 if (is_amd()) {
370 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
371 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
372 result |= CPU_3DNOW_PREFETCH;
373 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
374 result |= CPU_LZCNT;
375 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
376 result |= CPU_SSE4A;
377 }
379 return result;
380 }
382 static void get_processor_features();
384 public:
385 // Offsets for cpuid asm stub
386 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
387 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
388 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
389 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
390 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
391 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
392 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
393 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
394 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
395 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
397 // Initialization
398 static void initialize();
400 // Asserts
401 static void assert_is_initialized() {
402 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
403 }
405 //
406 // Processor family:
407 // 3 - 386
408 // 4 - 486
409 // 5 - Pentium
410 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
411 // Pentium M, Core Solo, Core Duo, Core2 Duo
412 // family 6 model: 9, 13, 14, 15
413 // 0x0f - Pentium 4, Opteron
414 //
415 // Note: The cpu family should be used to select between
416 // instruction sequences which are valid on all Intel
417 // processors. Use the feature test functions below to
418 // determine whether a particular instruction is supported.
419 //
420 static int cpu_family() { return _cpu;}
421 static bool is_P6() { return cpu_family() >= 6; }
422 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
423 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
425 static bool supports_processor_topology() {
426 return (_cpuid_info.std_max_function >= 0xB) &&
427 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
428 // Some cpus have max cpuid >= 0xB but do not support processor topology.
429 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
430 }
432 static uint cores_per_cpu() {
433 uint result = 1;
434 if (is_intel()) {
435 if (supports_processor_topology()) {
436 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
437 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
438 } else {
439 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
440 }
441 } else if (is_amd()) {
442 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
443 }
444 return result;
445 }
447 static uint threads_per_core() {
448 uint result = 1;
449 if (is_intel() && supports_processor_topology()) {
450 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
451 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
452 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
453 cores_per_cpu();
454 }
455 return result;
456 }
458 static intx prefetch_data_size() {
459 intx result = 0;
460 if (is_intel()) {
461 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
462 } else if (is_amd()) {
463 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
464 }
465 if (result < 32) // not defined ?
466 result = 32; // 32 bytes by default on x86 and other x64
467 return result;
468 }
470 //
471 // Feature identification
472 //
473 static bool supports_cpuid() { return _cpuFeatures != 0; }
474 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
475 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
476 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
477 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
478 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
479 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
480 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
481 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
482 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
483 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
484 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
485 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
486 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
488 // Intel features
489 static bool is_intel_family_core() { return is_intel() &&
490 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
492 static bool is_intel_tsc_synched_at_init() {
493 if (is_intel_family_core()) {
494 uint32_t ext_model = extended_cpu_model();
495 if (ext_model == CPU_MODEL_NEHALEM_EP ||
496 ext_model == CPU_MODEL_WESTMERE_EP ||
497 // TODO ext_model == CPU_MODEL_IVYBRIDGE_EP ||
498 ext_model == CPU_MODEL_SANDYBRIDGE_EP) {
499 // 2-socket invtsc support. EX versions with 4 sockets are not
500 // guaranteed to synchronize tscs at initialization via a double
501 // handshake. The tscs can be explicitly set in software. Code
502 // that uses tsc values must be prepared for them to arbitrarily
503 // jump backward or forward.
504 return true;
505 }
506 }
507 return false;
508 }
510 // AMD features
511 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
512 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
513 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
514 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
516 static bool is_amd_Barcelona() { return is_amd() &&
517 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
519 // Intel and AMD newer cores support fast timestamps well
520 static bool supports_tscinv_bit() {
521 return (_cpuFeatures & CPU_TSCINV) != 0;
522 }
523 static bool supports_tscinv() {
524 return supports_tscinv_bit() &&
525 ( (is_amd() && !is_amd_Barcelona()) ||
526 is_intel_tsc_synched_at_init() );
527 }
529 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
530 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
531 supports_sse3() && _model != 0x1C; }
533 static bool supports_compare_and_exchange() { return true; }
535 static const char* cpu_features() { return _features_str; }
537 static intx allocate_prefetch_distance() {
538 // This method should be called before allocate_prefetch_style().
539 //
540 // Hardware prefetching (distance/size in bytes):
541 // Pentium 3 - 64 / 32
542 // Pentium 4 - 256 / 128
543 // Athlon - 64 / 32 ????
544 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
545 // Core - 128 / 64
546 //
547 // Software prefetching (distance in bytes / instruction with best score):
548 // Pentium 3 - 128 / prefetchnta
549 // Pentium 4 - 512 / prefetchnta
550 // Athlon - 128 / prefetchnta
551 // Opteron - 256 / prefetchnta
552 // Core - 256 / prefetchnta
553 // It will be used only when AllocatePrefetchStyle > 0
555 intx count = AllocatePrefetchDistance;
556 if (count < 0) { // default ?
557 if (is_amd()) { // AMD
558 if (supports_sse2())
559 count = 256; // Opteron
560 else
561 count = 128; // Athlon
562 } else { // Intel
563 if (supports_sse2())
564 if (cpu_family() == 6) {
565 count = 256; // Pentium M, Core, Core2
566 } else {
567 count = 512; // Pentium 4
568 }
569 else
570 count = 128; // Pentium 3 (and all other old CPUs)
571 }
572 }
573 return count;
574 }
575 static intx allocate_prefetch_style() {
576 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
577 // Return 0 if AllocatePrefetchDistance was not defined.
578 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
579 }
581 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
582 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
583 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
584 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
586 // gc copy/scan is disabled if prefetchw isn't supported, because
587 // Prefetch::write emits an inlined prefetchw on Linux.
588 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
589 // The used prefetcht0 instruction works for both amd64 and em64t.
590 static intx prefetch_copy_interval_in_bytes() {
591 intx interval = PrefetchCopyIntervalInBytes;
592 return interval >= 0 ? interval : 576;
593 }
594 static intx prefetch_scan_interval_in_bytes() {
595 intx interval = PrefetchScanIntervalInBytes;
596 return interval >= 0 ? interval : 576;
597 }
598 static intx prefetch_fields_ahead() {
599 intx count = PrefetchFieldsAhead;
600 return count >= 0 ? count : 1;
601 }
602 };
604 #endif // CPU_X86_VM_VM_VERSION_X86_HPP