Mon, 12 Aug 2013 17:37:02 +0200
8015107: NPG: Use consistent naming for metaspace concepts
Reviewed-by: coleenp, mgerdin, hseigel
1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 extern bool use_block_zeroing(Node* count);
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
471 %}
473 source %{
474 #define __ _masm.
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
532 // ****************************************************************************
534 // REQUIRED FUNCTIONALITY
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedClassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
563 } else {
564 klass_load_size = 1*BytesPerInstWord;
565 }
566 if (Assembler::is_simm13(v_off)) {
567 return klass_load_size +
568 (2*BytesPerInstWord + // ld_ptr, ld_ptr
569 NativeCall::instruction_size); // call; delay slot
570 } else {
571 return klass_load_size +
572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
573 NativeCall::instruction_size); // call; delay slot
574 }
575 }
576 }
578 int MachCallRuntimeNode::ret_addr_offset() {
579 #ifdef _LP64
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 #else
586 return NativeCall::instruction_size; // call; delay slot
587 #endif
588 }
590 // Indicate if the safepoint node needs the polling page as an input.
591 // Since Sparc does not have absolute addressing, it does.
592 bool SafePointNode::needs_polling_address_input() {
593 return true;
594 }
596 // emit an interrupt that is caught by the debugger (for debugging compiler)
597 void emit_break(CodeBuffer &cbuf) {
598 MacroAssembler _masm(&cbuf);
599 __ breakpoint_trap();
600 }
602 #ifndef PRODUCT
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
604 st->print("TA");
605 }
606 #endif
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
609 emit_break(cbuf);
610 }
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
613 return MachNode::size(ra_);
614 }
616 // Traceable jump
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
618 MacroAssembler _masm(&cbuf);
619 Register rdest = reg_to_register_object(jump_target);
620 __ JMP(rdest, 0);
621 __ delayed()->nop();
622 }
624 // Traceable jump and set exception pc
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
626 MacroAssembler _masm(&cbuf);
627 Register rdest = reg_to_register_object(jump_target);
628 __ JMP(rdest, 0);
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
630 }
632 void emit_nop(CodeBuffer &cbuf) {
633 MacroAssembler _masm(&cbuf);
634 __ nop();
635 }
637 void emit_illtrap(CodeBuffer &cbuf) {
638 MacroAssembler _masm(&cbuf);
639 __ illtrap(0);
640 }
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
644 assert(n->rule() != loadUB_rule, "");
646 intptr_t offset = 0;
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
648 const Node* addr = n->get_base_and_disp(offset, adr_type);
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 atype = atype->add_offset(offset);
653 assert(disp32 == offset, "wrong disp32");
654 return atype->_offset;
655 }
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
659 assert(n->rule() != loadUB_rule, "");
661 intptr_t offset = 0;
662 Node* addr = n->in(2);
663 assert(addr->bottom_type()->isa_oopptr() == atype, "");
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
665 Node* a = addr->in(2/*AddPNode::Address*/);
666 Node* o = addr->in(3/*AddPNode::Offset*/);
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
668 atype = a->bottom_type()->is_ptr()->add_offset(offset);
669 assert(atype->isa_oop_ptr(), "still an oop");
670 }
671 offset = atype->is_ptr()->_offset;
672 if (offset != Type::OffsetBot) offset += disp32;
673 return offset;
674 }
676 static inline jdouble replicate_immI(int con, int count, int width) {
677 // Load a constant replicated "count" times with width "width"
678 assert(count*width == 8 && width <= 4, "sanity");
679 int bit_width = width * 8;
680 jlong val = con;
681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
682 for (int i = 0; i < count - 1; i++) {
683 val |= (val << bit_width);
684 }
685 jdouble dval = *((jdouble*) &val); // coerce to double type
686 return dval;
687 }
689 static inline jdouble replicate_immF(float con) {
690 // Replicate float con 2 times and pack into vector.
691 int val = *((int*)&con);
692 jlong lval = val;
693 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
694 jdouble dval = *((jdouble*) &lval); // coerce to double type
695 return dval;
696 }
698 // Standard Sparc opcode form2 field breakdown
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits
701 int op = (f30 << 30) |
702 (f29 << 29) |
703 (f25 << 25) |
704 (f22 << 22) |
705 (f20 << 20) |
706 (f19 << 19) |
707 (f0 << 0);
708 cbuf.insts()->emit_int32(op);
709 }
711 // Standard Sparc opcode form2 field breakdown
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
713 f0 >>= 10; // Drop 10 bits
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits
715 int op = (f30 << 30) |
716 (f25 << 25) |
717 (f22 << 22) |
718 (f0 << 0);
719 cbuf.insts()->emit_int32(op);
720 }
722 // Standard Sparc opcode form3 field breakdown
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
724 int op = (f30 << 30) |
725 (f25 << 25) |
726 (f19 << 19) |
727 (f14 << 14) |
728 (f5 << 5) |
729 (f0 << 0);
730 cbuf.insts()->emit_int32(op);
731 }
733 // Standard Sparc opcode form3 field breakdown
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
735 simm13 &= (1<<13)-1; // Mask to 13 bits
736 int op = (f30 << 30) |
737 (f25 << 25) |
738 (f19 << 19) |
739 (f14 << 14) |
740 (1 << 13) | // bit to indicate immediate-mode
741 (simm13<<0);
742 cbuf.insts()->emit_int32(op);
743 }
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
746 simm10 &= (1<<10)-1; // Mask to 10 bits
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
748 }
750 #ifdef ASSERT
751 // Helper function for VerifyOops in emit_form3_mem_reg
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
753 warning("VerifyOops encountered unexpected instruction:");
754 n->dump(2);
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 }
757 #endif
760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of
766 // the current method activation. +VerifyOops complements techniques
767 // like ScavengeALot, because it eagerly inspects oops in transit,
768 // as they enter or leave the stack, as opposed to ScavengeALot,
769 // which inspects oops "at rest", in the stack or heap, at safepoints.
770 // For this reason, +VerifyOops can sometimes detect bugs very close
771 // to their point of creation. It can also serve as a cross-check
772 // on the validity of oop maps, when used toegether with ScavengeALot.
774 // It would be good to verify oops at other points, especially
775 // when an oop is used as a base pointer for a load or store.
776 // This is presently difficult, because it is hard to know when
777 // a base address is biased or not. (If we had such information,
778 // it would be easy and useful to make a two-argument version of
779 // verify_oop which unbiases the base, and performs verification.)
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
782 bool is_verified_oop_base = false;
783 bool is_verified_oop_load = false;
784 bool is_verified_oop_store = false;
785 int tmp_enc = -1;
786 if (VerifyOops && src1_enc != R_SP_enc) {
787 // classify the op, mainly for an assert check
788 int st_op = 0, ld_op = 0;
789 switch (primary) {
790 case Assembler::stb_op3: st_op = Op_StoreB; break;
791 case Assembler::sth_op3: st_op = Op_StoreC; break;
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
793 case Assembler::stw_op3: st_op = Op_StoreI; break;
794 case Assembler::std_op3: st_op = Op_StoreL; break;
795 case Assembler::stf_op3: st_op = Op_StoreF; break;
796 case Assembler::stdf_op3: st_op = Op_StoreD; break;
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
810 default: ShouldNotReachHere();
811 }
812 if (tertiary == REGP_OP) {
813 if (st_op == Op_StoreI) st_op = Op_StoreP;
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
815 else ShouldNotReachHere();
816 if (st_op) {
817 // a store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 Node* n2 = n->in(3);
820 if (n2 != NULL) {
821 const Type* t = n2->bottom_type();
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 } else {
825 // a load
826 const Type* t = n->bottom_type();
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
828 }
829 }
831 if (ld_op) {
832 // a Load
833 // inputs are (0:control, 1:memory, 2:address)
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
849 !(n->rule() == loadUB_rule)) {
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
851 }
852 } else if (st_op) {
853 // a Store
854 // inputs are (0:control, 1:memory, 2:address, 3:value)
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
912 uint index = src2_enc;
913 int disp = disp32;
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
916 disp += STACK_BIAS;
918 // We should have a compiler bailout here rather than a guarantee.
919 // Better yet would be some mechanism to handle variable-size matches correctly.
920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
922 if( disp == 0 ) {
923 // use reg-reg form
924 // bit 13 is already zero
925 instr |= index;
926 } else {
927 // use reg-imm form
928 instr |= 0x00002000; // set bit 13 to one
929 instr |= disp & 0x1FFF;
930 }
932 cbuf.insts()->emit_int32(instr);
934 #ifdef ASSERT
935 {
936 MacroAssembler _masm(&cbuf);
937 if (is_verified_oop_base) {
938 __ verify_oop(reg_to_register_object(src1_enc));
939 }
940 if (is_verified_oop_store) {
941 __ verify_oop(reg_to_register_object(dst_enc));
942 }
943 if (tmp_enc != -1) {
944 __ mov(O7, reg_to_register_object(tmp_enc));
945 }
946 if (is_verified_oop_load) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 }
950 #endif
951 }
953 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
954 // The method which records debug information at every safepoint
955 // expects the call to be the first instruction in the snippet as
956 // it creates a PcDesc structure which tracks the offset of a call
957 // from the start of the codeBlob. This offset is computed as
958 // code_end() - code_begin() of the code which has been emitted
959 // so far.
960 // In this particular case we have skirted around the problem by
961 // putting the "mov" instruction in the delay slot but the problem
962 // may bite us again at some other point and a cleaner/generic
963 // solution using relocations would be needed.
964 MacroAssembler _masm(&cbuf);
965 __ set_inst_mark();
967 // We flush the current window just so that there is a valid stack copy
968 // the fact that the current window becomes active again instantly is
969 // not a problem there is nothing live in it.
971 #ifdef ASSERT
972 int startpos = __ offset();
973 #endif /* ASSERT */
975 __ call((address)entry_point, rtype);
977 if (preserve_g2) __ delayed()->mov(G2, L7);
978 else __ delayed()->nop();
980 if (preserve_g2) __ mov(L7, G2);
982 #ifdef ASSERT
983 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
984 #ifdef _LP64
985 // Trash argument dump slots.
986 __ set(0xb0b8ac0db0b8ac0d, G1);
987 __ mov(G1, G5);
988 __ stx(G1, SP, STACK_BIAS + 0x80);
989 __ stx(G1, SP, STACK_BIAS + 0x88);
990 __ stx(G1, SP, STACK_BIAS + 0x90);
991 __ stx(G1, SP, STACK_BIAS + 0x98);
992 __ stx(G1, SP, STACK_BIAS + 0xA0);
993 __ stx(G1, SP, STACK_BIAS + 0xA8);
994 #else // _LP64
995 // this is also a native call, so smash the first 7 stack locations,
996 // and the various registers
998 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
999 // while [SP+0x44..0x58] are the argument dump slots.
1000 __ set((intptr_t)0xbaadf00d, G1);
1001 __ mov(G1, G5);
1002 __ sllx(G1, 32, G1);
1003 __ or3(G1, G5, G1);
1004 __ mov(G1, G5);
1005 __ stx(G1, SP, 0x40);
1006 __ stx(G1, SP, 0x48);
1007 __ stx(G1, SP, 0x50);
1008 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1009 #endif // _LP64
1010 }
1011 #endif /*ASSERT*/
1012 }
1014 //=============================================================================
1015 // REQUIRED FUNCTIONALITY for encoding
1016 void emit_lo(CodeBuffer &cbuf, int val) { }
1017 void emit_hi(CodeBuffer &cbuf, int val) { }
1020 //=============================================================================
1021 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1023 int Compile::ConstantTable::calculate_table_base_offset() const {
1024 if (UseRDPCForConstantTableBase) {
1025 // The table base offset might be less but then it fits into
1026 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1027 return Assembler::min_simm13();
1028 } else {
1029 int offset = -(size() / 2);
1030 if (!Assembler::is_simm13(offset)) {
1031 offset = Assembler::min_simm13();
1032 }
1033 return offset;
1034 }
1035 }
1037 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1038 Compile* C = ra_->C;
1039 Compile::ConstantTable& constant_table = C->constant_table();
1040 MacroAssembler _masm(&cbuf);
1042 Register r = as_Register(ra_->get_encode(this));
1043 CodeSection* consts_section = __ code()->consts();
1044 int consts_size = consts_section->align_at_start(consts_section->size());
1045 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1047 if (UseRDPCForConstantTableBase) {
1048 // For the following RDPC logic to work correctly the consts
1049 // section must be allocated right before the insts section. This
1050 // assert checks for that. The layout and the SECT_* constants
1051 // are defined in src/share/vm/asm/codeBuffer.hpp.
1052 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1053 int insts_offset = __ offset();
1055 // Layout:
1056 //
1057 // |----------- consts section ------------|----------- insts section -----------...
1058 // |------ constant table -----|- padding -|------------------x----
1059 // \ current PC (RDPC instruction)
1060 // |<------------- consts_size ----------->|<- insts_offset ->|
1061 // \ table base
1062 // The table base offset is later added to the load displacement
1063 // so it has to be negative.
1064 int table_base_offset = -(consts_size + insts_offset);
1065 int disp;
1067 // If the displacement from the current PC to the constant table
1068 // base fits into simm13 we set the constant table base to the
1069 // current PC.
1070 if (Assembler::is_simm13(table_base_offset)) {
1071 constant_table.set_table_base_offset(table_base_offset);
1072 disp = 0;
1073 } else {
1074 // Otherwise we set the constant table base offset to the
1075 // maximum negative displacement of load instructions to keep
1076 // the disp as small as possible:
1077 //
1078 // |<------------- consts_size ----------->|<- insts_offset ->|
1079 // |<--------- min_simm13 --------->|<-------- disp --------->|
1080 // \ table base
1081 table_base_offset = Assembler::min_simm13();
1082 constant_table.set_table_base_offset(table_base_offset);
1083 disp = (consts_size + insts_offset) + table_base_offset;
1084 }
1086 __ rdpc(r);
1088 if (disp != 0) {
1089 assert(r != O7, "need temporary");
1090 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1091 }
1092 }
1093 else {
1094 // Materialize the constant table base.
1095 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1096 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1097 AddressLiteral base(baseaddr, rspec);
1098 __ set(base, r);
1099 }
1100 }
1102 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1103 if (UseRDPCForConstantTableBase) {
1104 // This is really the worst case but generally it's only 1 instruction.
1105 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1106 } else {
1107 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1108 }
1109 }
1111 #ifndef PRODUCT
1112 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1113 char reg[128];
1114 ra_->dump_register(this, reg);
1115 if (UseRDPCForConstantTableBase) {
1116 st->print("RDPC %s\t! constant table base", reg);
1117 } else {
1118 st->print("SET &constanttable,%s\t! constant table base", reg);
1119 }
1120 }
1121 #endif
1124 //=============================================================================
1126 #ifndef PRODUCT
1127 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1128 Compile* C = ra_->C;
1130 for (int i = 0; i < OptoPrologueNops; i++) {
1131 st->print_cr("NOP"); st->print("\t");
1132 }
1134 if( VerifyThread ) {
1135 st->print_cr("Verify_Thread"); st->print("\t");
1136 }
1138 size_t framesize = C->frame_slots() << LogBytesPerInt;
1140 // Calls to C2R adapters often do not accept exceptional returns.
1141 // We require that their callers must bang for them. But be careful, because
1142 // some VM calls (such as call site linkage) can use several kilobytes of
1143 // stack. But the stack safety zone should account for that.
1144 // See bugs 4446381, 4468289, 4497237.
1145 if (C->need_stack_bang(framesize)) {
1146 st->print_cr("! stack bang"); st->print("\t");
1147 }
1149 if (Assembler::is_simm13(-framesize)) {
1150 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1151 } else {
1152 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1153 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1154 st->print ("SAVE R_SP,R_G3,R_SP");
1155 }
1157 }
1158 #endif
1160 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1161 Compile* C = ra_->C;
1162 MacroAssembler _masm(&cbuf);
1164 for (int i = 0; i < OptoPrologueNops; i++) {
1165 __ nop();
1166 }
1168 __ verify_thread();
1170 size_t framesize = C->frame_slots() << LogBytesPerInt;
1171 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1172 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1174 // Calls to C2R adapters often do not accept exceptional returns.
1175 // We require that their callers must bang for them. But be careful, because
1176 // some VM calls (such as call site linkage) can use several kilobytes of
1177 // stack. But the stack safety zone should account for that.
1178 // See bugs 4446381, 4468289, 4497237.
1179 if (C->need_stack_bang(framesize)) {
1180 __ generate_stack_overflow_check(framesize);
1181 }
1183 if (Assembler::is_simm13(-framesize)) {
1184 __ save(SP, -framesize, SP);
1185 } else {
1186 __ sethi(-framesize & ~0x3ff, G3);
1187 __ add(G3, -framesize & 0x3ff, G3);
1188 __ save(SP, G3, SP);
1189 }
1190 C->set_frame_complete( __ offset() );
1192 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1193 // NOTE: We set the table base offset here because users might be
1194 // emitted before MachConstantBaseNode.
1195 Compile::ConstantTable& constant_table = C->constant_table();
1196 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1197 }
1198 }
1200 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1201 return MachNode::size(ra_);
1202 }
1204 int MachPrologNode::reloc() const {
1205 return 10; // a large enough number
1206 }
1208 //=============================================================================
1209 #ifndef PRODUCT
1210 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1211 Compile* C = ra_->C;
1213 if( do_polling() && ra_->C->is_method_compilation() ) {
1214 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1215 #ifdef _LP64
1216 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1217 #else
1218 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1219 #endif
1220 }
1222 if( do_polling() )
1223 st->print("RET\n\t");
1225 st->print("RESTORE");
1226 }
1227 #endif
1229 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1230 MacroAssembler _masm(&cbuf);
1231 Compile* C = ra_->C;
1233 __ verify_thread();
1235 // If this does safepoint polling, then do it here
1236 if( do_polling() && ra_->C->is_method_compilation() ) {
1237 AddressLiteral polling_page(os::get_polling_page());
1238 __ sethi(polling_page, L0);
1239 __ relocate(relocInfo::poll_return_type);
1240 __ ld_ptr( L0, 0, G0 );
1241 }
1243 // If this is a return, then stuff the restore in the delay slot
1244 if( do_polling() ) {
1245 __ ret();
1246 __ delayed()->restore();
1247 } else {
1248 __ restore();
1249 }
1250 }
1252 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1253 return MachNode::size(ra_);
1254 }
1256 int MachEpilogNode::reloc() const {
1257 return 16; // a large enough number
1258 }
1260 const Pipeline * MachEpilogNode::pipeline() const {
1261 return MachNode::pipeline_class();
1262 }
1264 int MachEpilogNode::safepoint_offset() const {
1265 assert( do_polling(), "no return for this epilog node");
1266 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1267 }
1269 //=============================================================================
1271 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1272 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1273 static enum RC rc_class( OptoReg::Name reg ) {
1274 if( !OptoReg::is_valid(reg) ) return rc_bad;
1275 if (OptoReg::is_stack(reg)) return rc_stack;
1276 VMReg r = OptoReg::as_VMReg(reg);
1277 if (r->is_Register()) return rc_int;
1278 assert(r->is_FloatRegister(), "must be");
1279 return rc_float;
1280 }
1282 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1283 if( cbuf ) {
1284 // Better yet would be some mechanism to handle variable-size matches correctly
1285 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1286 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1287 } else {
1288 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1289 }
1290 }
1291 #ifndef PRODUCT
1292 else if( !do_size ) {
1293 if( size != 0 ) st->print("\n\t");
1294 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1295 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1296 }
1297 #endif
1298 return size+4;
1299 }
1301 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1302 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1303 #ifndef PRODUCT
1304 else if( !do_size ) {
1305 if( size != 0 ) st->print("\n\t");
1306 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1307 }
1308 #endif
1309 return size+4;
1310 }
1312 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1313 PhaseRegAlloc *ra_,
1314 bool do_size,
1315 outputStream* st ) const {
1316 // Get registers to move
1317 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1318 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1319 OptoReg::Name dst_second = ra_->get_reg_second(this );
1320 OptoReg::Name dst_first = ra_->get_reg_first(this );
1322 enum RC src_second_rc = rc_class(src_second);
1323 enum RC src_first_rc = rc_class(src_first);
1324 enum RC dst_second_rc = rc_class(dst_second);
1325 enum RC dst_first_rc = rc_class(dst_first);
1327 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1329 // Generate spill code!
1330 int size = 0;
1332 if( src_first == dst_first && src_second == dst_second )
1333 return size; // Self copy, no move
1335 // --------------------------------------
1336 // Check for mem-mem move. Load into unused float registers and fall into
1337 // the float-store case.
1338 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1339 int offset = ra_->reg2offset(src_first);
1340 // Further check for aligned-adjacent pair, so we can use a double load
1341 if( (src_first&1)==0 && src_first+1 == src_second ) {
1342 src_second = OptoReg::Name(R_F31_num);
1343 src_second_rc = rc_float;
1344 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1345 } else {
1346 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1347 }
1348 src_first = OptoReg::Name(R_F30_num);
1349 src_first_rc = rc_float;
1350 }
1352 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1353 int offset = ra_->reg2offset(src_second);
1354 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1355 src_second = OptoReg::Name(R_F31_num);
1356 src_second_rc = rc_float;
1357 }
1359 // --------------------------------------
1360 // Check for float->int copy; requires a trip through memory
1361 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1362 int offset = frame::register_save_words*wordSize;
1363 if (cbuf) {
1364 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1365 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1366 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1368 }
1369 #ifndef PRODUCT
1370 else if (!do_size) {
1371 if (size != 0) st->print("\n\t");
1372 st->print( "SUB R_SP,16,R_SP\n");
1373 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1374 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1375 st->print("\tADD R_SP,16,R_SP\n");
1376 }
1377 #endif
1378 size += 16;
1379 }
1381 // Check for float->int copy on T4
1382 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1383 // Further check for aligned-adjacent pair, so we can use a double move
1384 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1385 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1386 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1387 }
1388 // Check for int->float copy on T4
1389 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1390 // Further check for aligned-adjacent pair, so we can use a double move
1391 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1392 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1393 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1394 }
1396 // --------------------------------------
1397 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1398 // In such cases, I have to do the big-endian swap. For aligned targets, the
1399 // hardware does the flop for me. Doubles are always aligned, so no problem
1400 // there. Misaligned sources only come from native-long-returns (handled
1401 // special below).
1402 #ifndef _LP64
1403 if( src_first_rc == rc_int && // source is already big-endian
1404 src_second_rc != rc_bad && // 64-bit move
1405 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1406 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1407 // Do the big-endian flop.
1408 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1409 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1410 }
1411 #endif
1413 // --------------------------------------
1414 // Check for integer reg-reg copy
1415 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1416 #ifndef _LP64
1417 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1418 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1419 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1420 // operand contains the least significant word of the 64-bit value and vice versa.
1421 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1422 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1423 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1424 if( cbuf ) {
1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1428 #ifndef PRODUCT
1429 } else if( !do_size ) {
1430 if( size != 0 ) st->print("\n\t");
1431 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1432 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1433 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1434 #endif
1435 }
1436 return size+12;
1437 }
1438 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1439 // returning a long value in I0/I1
1440 // a SpillCopy must be able to target a return instruction's reg_class
1441 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1442 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1443 // operand contains the least significant word of the 64-bit value and vice versa.
1444 OptoReg::Name tdest = dst_first;
1446 if (src_first == dst_first) {
1447 tdest = OptoReg::Name(R_O7_num);
1448 size += 4;
1449 }
1451 if( cbuf ) {
1452 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1453 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1454 // ShrL_reg_imm6
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1456 // ShrR_reg_imm6 src, 0, dst
1457 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1458 if (tdest != dst_first) {
1459 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1460 }
1461 }
1462 #ifndef PRODUCT
1463 else if( !do_size ) {
1464 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1465 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1466 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1467 if (tdest != dst_first) {
1468 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1469 }
1470 }
1471 #endif // PRODUCT
1472 return size+8;
1473 }
1474 #endif // !_LP64
1475 // Else normal reg-reg copy
1476 assert( src_second != dst_first, "smashed second before evacuating it" );
1477 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1478 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1479 // This moves an aligned adjacent pair.
1480 // See if we are done.
1481 if( src_first+1 == src_second && dst_first+1 == dst_second )
1482 return size;
1483 }
1485 // Check for integer store
1486 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1487 int offset = ra_->reg2offset(dst_first);
1488 // Further check for aligned-adjacent pair, so we can use a double store
1489 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1490 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1491 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1492 }
1494 // Check for integer load
1495 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1496 int offset = ra_->reg2offset(src_first);
1497 // Further check for aligned-adjacent pair, so we can use a double load
1498 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1499 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1500 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1501 }
1503 // Check for float reg-reg copy
1504 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1505 // Further check for aligned-adjacent pair, so we can use a double move
1506 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1507 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1508 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1509 }
1511 // Check for float store
1512 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1513 int offset = ra_->reg2offset(dst_first);
1514 // Further check for aligned-adjacent pair, so we can use a double store
1515 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1516 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1517 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1518 }
1520 // Check for float load
1521 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1522 int offset = ra_->reg2offset(src_first);
1523 // Further check for aligned-adjacent pair, so we can use a double load
1524 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1525 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1526 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1527 }
1529 // --------------------------------------------------------------------
1530 // Check for hi bits still needing moving. Only happens for misaligned
1531 // arguments to native calls.
1532 if( src_second == dst_second )
1533 return size; // Self copy; no move
1534 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1536 #ifndef _LP64
1537 // In the LP64 build, all registers can be moved as aligned/adjacent
1538 // pairs, so there's never any need to move the high bits separately.
1539 // The 32-bit builds have to deal with the 32-bit ABI which can force
1540 // all sorts of silly alignment problems.
1542 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1543 // 32-bits of a 64-bit register, but are needed in low bits of another
1544 // register (else it's a hi-bits-to-hi-bits copy which should have
1545 // happened already as part of a 64-bit move)
1546 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1547 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1548 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1549 // Shift src_second down to dst_second's low bits.
1550 if( cbuf ) {
1551 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1552 #ifndef PRODUCT
1553 } else if( !do_size ) {
1554 if( size != 0 ) st->print("\n\t");
1555 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1556 #endif
1557 }
1558 return size+4;
1559 }
1561 // Check for high word integer store. Must down-shift the hi bits
1562 // into a temp register, then fall into the case of storing int bits.
1563 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1564 // Shift src_second down to dst_second's low bits.
1565 if( cbuf ) {
1566 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1567 #ifndef PRODUCT
1568 } else if( !do_size ) {
1569 if( size != 0 ) st->print("\n\t");
1570 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1571 #endif
1572 }
1573 size+=4;
1574 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1575 }
1577 // Check for high word integer load
1578 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1579 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1581 // Check for high word integer store
1582 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1583 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1585 // Check for high word float store
1586 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1587 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1589 #endif // !_LP64
1591 Unimplemented();
1592 }
1594 #ifndef PRODUCT
1595 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1596 implementation( NULL, ra_, false, st );
1597 }
1598 #endif
1600 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1601 implementation( &cbuf, ra_, false, NULL );
1602 }
1604 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1605 return implementation( NULL, ra_, true, NULL );
1606 }
1608 //=============================================================================
1609 #ifndef PRODUCT
1610 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1611 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1612 }
1613 #endif
1615 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1616 MacroAssembler _masm(&cbuf);
1617 for(int i = 0; i < _count; i += 1) {
1618 __ nop();
1619 }
1620 }
1622 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1623 return 4 * _count;
1624 }
1627 //=============================================================================
1628 #ifndef PRODUCT
1629 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1630 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1631 int reg = ra_->get_reg_first(this);
1632 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1633 }
1634 #endif
1636 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1637 MacroAssembler _masm(&cbuf);
1638 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1639 int reg = ra_->get_encode(this);
1641 if (Assembler::is_simm13(offset)) {
1642 __ add(SP, offset, reg_to_register_object(reg));
1643 } else {
1644 __ set(offset, O7);
1645 __ add(SP, O7, reg_to_register_object(reg));
1646 }
1647 }
1649 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1650 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1651 assert(ra_ == ra_->C->regalloc(), "sanity");
1652 return ra_->C->scratch_emit_size(this);
1653 }
1655 //=============================================================================
1656 #ifndef PRODUCT
1657 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 st->print_cr("\nUEP:");
1659 #ifdef _LP64
1660 if (UseCompressedClassPointers) {
1661 assert(Universe::heap() != NULL, "java heap should be initialized");
1662 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1663 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1664 if (Universe::narrow_klass_shift() != 0) {
1665 st->print_cr("\tSLL R_G5,3,R_G5");
1666 }
1667 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1668 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1669 } else {
1670 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1671 }
1672 st->print_cr("\tCMP R_G5,R_G3" );
1673 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1674 #else // _LP64
1675 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1676 st->print_cr("\tCMP R_G5,R_G3" );
1677 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1678 #endif // _LP64
1679 }
1680 #endif
1682 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1683 MacroAssembler _masm(&cbuf);
1684 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1685 Register temp_reg = G3;
1686 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1688 // Load klass from receiver
1689 __ load_klass(O0, temp_reg);
1690 // Compare against expected klass
1691 __ cmp(temp_reg, G5_ic_reg);
1692 // Branch to miss code, checks xcc or icc depending
1693 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1694 }
1696 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1697 return MachNode::size(ra_);
1698 }
1701 //=============================================================================
1703 uint size_exception_handler() {
1704 if (TraceJumps) {
1705 return (400); // just a guess
1706 }
1707 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1708 }
1710 uint size_deopt_handler() {
1711 if (TraceJumps) {
1712 return (400); // just a guess
1713 }
1714 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1715 }
1717 // Emit exception handler code.
1718 int emit_exception_handler(CodeBuffer& cbuf) {
1719 Register temp_reg = G3;
1720 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1721 MacroAssembler _masm(&cbuf);
1723 address base =
1724 __ start_a_stub(size_exception_handler());
1725 if (base == NULL) return 0; // CodeBuffer::expand failed
1727 int offset = __ offset();
1729 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1730 __ delayed()->nop();
1732 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1734 __ end_a_stub();
1736 return offset;
1737 }
1739 int emit_deopt_handler(CodeBuffer& cbuf) {
1740 // Can't use any of the current frame's registers as we may have deopted
1741 // at a poll and everything (including G3) can be live.
1742 Register temp_reg = L0;
1743 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1744 MacroAssembler _masm(&cbuf);
1746 address base =
1747 __ start_a_stub(size_deopt_handler());
1748 if (base == NULL) return 0; // CodeBuffer::expand failed
1750 int offset = __ offset();
1751 __ save_frame(0);
1752 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1753 __ delayed()->restore();
1755 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1757 __ end_a_stub();
1758 return offset;
1760 }
1762 // Given a register encoding, produce a Integer Register object
1763 static Register reg_to_register_object(int register_encoding) {
1764 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1765 return as_Register(register_encoding);
1766 }
1768 // Given a register encoding, produce a single-precision Float Register object
1769 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1770 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1771 return as_SingleFloatRegister(register_encoding);
1772 }
1774 // Given a register encoding, produce a double-precision Float Register object
1775 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1776 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1777 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1778 return as_DoubleFloatRegister(register_encoding);
1779 }
1781 const bool Matcher::match_rule_supported(int opcode) {
1782 if (!has_match_rule(opcode))
1783 return false;
1785 switch (opcode) {
1786 case Op_CountLeadingZerosI:
1787 case Op_CountLeadingZerosL:
1788 case Op_CountTrailingZerosI:
1789 case Op_CountTrailingZerosL:
1790 case Op_PopCountI:
1791 case Op_PopCountL:
1792 if (!UsePopCountInstruction)
1793 return false;
1794 case Op_CompareAndSwapL:
1795 #ifdef _LP64
1796 case Op_CompareAndSwapP:
1797 #endif
1798 if (!VM_Version::supports_cx8())
1799 return false;
1800 break;
1801 }
1803 return true; // Per default match rules are supported.
1804 }
1806 int Matcher::regnum_to_fpu_offset(int regnum) {
1807 return regnum - 32; // The FP registers are in the second chunk
1808 }
1810 #ifdef ASSERT
1811 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1812 #endif
1814 // Vector width in bytes
1815 const int Matcher::vector_width_in_bytes(BasicType bt) {
1816 assert(MaxVectorSize == 8, "");
1817 return 8;
1818 }
1820 // Vector ideal reg
1821 const int Matcher::vector_ideal_reg(int size) {
1822 assert(MaxVectorSize == 8, "");
1823 return Op_RegD;
1824 }
1826 const int Matcher::vector_shift_count_ideal_reg(int size) {
1827 fatal("vector shift is not supported");
1828 return Node::NotAMachineReg;
1829 }
1831 // Limits on vector size (number of elements) loaded into vector.
1832 const int Matcher::max_vector_size(const BasicType bt) {
1833 assert(is_java_primitive(bt), "only primitive type vectors");
1834 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1835 }
1837 const int Matcher::min_vector_size(const BasicType bt) {
1838 return max_vector_size(bt); // Same as max.
1839 }
1841 // SPARC doesn't support misaligned vectors store/load.
1842 const bool Matcher::misaligned_vectors_ok() {
1843 return false;
1844 }
1846 // USII supports fxtof through the whole range of number, USIII doesn't
1847 const bool Matcher::convL2FSupported(void) {
1848 return VM_Version::has_fast_fxtof();
1849 }
1851 // Is this branch offset short enough that a short branch can be used?
1852 //
1853 // NOTE: If the platform does not provide any short branch variants, then
1854 // this method should return false for offset 0.
1855 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1856 // The passed offset is relative to address of the branch.
1857 // Don't need to adjust the offset.
1858 return UseCBCond && Assembler::is_simm12(offset);
1859 }
1861 const bool Matcher::isSimpleConstant64(jlong value) {
1862 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1863 // Depends on optimizations in MacroAssembler::setx.
1864 int hi = (int)(value >> 32);
1865 int lo = (int)(value & ~0);
1866 return (hi == 0) || (hi == -1) || (lo == 0);
1867 }
1869 // No scaling for the parameter the ClearArray node.
1870 const bool Matcher::init_array_count_is_in_bytes = true;
1872 // Threshold size for cleararray.
1873 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1875 // No additional cost for CMOVL.
1876 const int Matcher::long_cmove_cost() { return 0; }
1878 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1879 const int Matcher::float_cmove_cost() {
1880 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1881 }
1883 // Should the Matcher clone shifts on addressing modes, expecting them to
1884 // be subsumed into complex addressing expressions or compute them into
1885 // registers? True for Intel but false for most RISCs
1886 const bool Matcher::clone_shift_expressions = false;
1888 // Do we need to mask the count passed to shift instructions or does
1889 // the cpu only look at the lower 5/6 bits anyway?
1890 const bool Matcher::need_masked_shift_count = false;
1892 bool Matcher::narrow_oop_use_complex_address() {
1893 NOT_LP64(ShouldNotCallThis());
1894 assert(UseCompressedOops, "only for compressed oops code");
1895 return false;
1896 }
1898 bool Matcher::narrow_klass_use_complex_address() {
1899 NOT_LP64(ShouldNotCallThis());
1900 assert(UseCompressedClassPointers, "only for compressed klass code");
1901 return false;
1902 }
1904 // Is it better to copy float constants, or load them directly from memory?
1905 // Intel can load a float constant from a direct address, requiring no
1906 // extra registers. Most RISCs will have to materialize an address into a
1907 // register first, so they would do better to copy the constant from stack.
1908 const bool Matcher::rematerialize_float_constants = false;
1910 // If CPU can load and store mis-aligned doubles directly then no fixup is
1911 // needed. Else we split the double into 2 integer pieces and move it
1912 // piece-by-piece. Only happens when passing doubles into C code as the
1913 // Java calling convention forces doubles to be aligned.
1914 #ifdef _LP64
1915 const bool Matcher::misaligned_doubles_ok = true;
1916 #else
1917 const bool Matcher::misaligned_doubles_ok = false;
1918 #endif
1920 // No-op on SPARC.
1921 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1922 }
1924 // Advertise here if the CPU requires explicit rounding operations
1925 // to implement the UseStrictFP mode.
1926 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1928 // Are floats conerted to double when stored to stack during deoptimization?
1929 // Sparc does not handle callee-save floats.
1930 bool Matcher::float_in_double() { return false; }
1932 // Do ints take an entire long register or just half?
1933 // Note that we if-def off of _LP64.
1934 // The relevant question is how the int is callee-saved. In _LP64
1935 // the whole long is written but de-opt'ing will have to extract
1936 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1937 #ifdef _LP64
1938 const bool Matcher::int_in_long = true;
1939 #else
1940 const bool Matcher::int_in_long = false;
1941 #endif
1943 // Return whether or not this register is ever used as an argument. This
1944 // function is used on startup to build the trampoline stubs in generateOptoStub.
1945 // Registers not mentioned will be killed by the VM call in the trampoline, and
1946 // arguments in those registers not be available to the callee.
1947 bool Matcher::can_be_java_arg( int reg ) {
1948 // Standard sparc 6 args in registers
1949 if( reg == R_I0_num ||
1950 reg == R_I1_num ||
1951 reg == R_I2_num ||
1952 reg == R_I3_num ||
1953 reg == R_I4_num ||
1954 reg == R_I5_num ) return true;
1955 #ifdef _LP64
1956 // 64-bit builds can pass 64-bit pointers and longs in
1957 // the high I registers
1958 if( reg == R_I0H_num ||
1959 reg == R_I1H_num ||
1960 reg == R_I2H_num ||
1961 reg == R_I3H_num ||
1962 reg == R_I4H_num ||
1963 reg == R_I5H_num ) return true;
1965 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1966 return true;
1967 }
1969 #else
1970 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1971 // Longs cannot be passed in O regs, because O regs become I regs
1972 // after a 'save' and I regs get their high bits chopped off on
1973 // interrupt.
1974 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1975 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1976 #endif
1977 // A few float args in registers
1978 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1980 return false;
1981 }
1983 bool Matcher::is_spillable_arg( int reg ) {
1984 return can_be_java_arg(reg);
1985 }
1987 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1988 // Use hardware SDIVX instruction when it is
1989 // faster than a code which use multiply.
1990 return VM_Version::has_fast_idiv();
1991 }
1993 // Register for DIVI projection of divmodI
1994 RegMask Matcher::divI_proj_mask() {
1995 ShouldNotReachHere();
1996 return RegMask();
1997 }
1999 // Register for MODI projection of divmodI
2000 RegMask Matcher::modI_proj_mask() {
2001 ShouldNotReachHere();
2002 return RegMask();
2003 }
2005 // Register for DIVL projection of divmodL
2006 RegMask Matcher::divL_proj_mask() {
2007 ShouldNotReachHere();
2008 return RegMask();
2009 }
2011 // Register for MODL projection of divmodL
2012 RegMask Matcher::modL_proj_mask() {
2013 ShouldNotReachHere();
2014 return RegMask();
2015 }
2017 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2018 return L7_REGP_mask();
2019 }
2021 %}
2024 // The intptr_t operand types, defined by textual substitution.
2025 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2026 #ifdef _LP64
2027 #define immX immL
2028 #define immX13 immL13
2029 #define immX13m7 immL13m7
2030 #define iRegX iRegL
2031 #define g1RegX g1RegL
2032 #else
2033 #define immX immI
2034 #define immX13 immI13
2035 #define immX13m7 immI13m7
2036 #define iRegX iRegI
2037 #define g1RegX g1RegI
2038 #endif
2040 //----------ENCODING BLOCK-----------------------------------------------------
2041 // This block specifies the encoding classes used by the compiler to output
2042 // byte streams. Encoding classes are parameterized macros used by
2043 // Machine Instruction Nodes in order to generate the bit encoding of the
2044 // instruction. Operands specify their base encoding interface with the
2045 // interface keyword. There are currently supported four interfaces,
2046 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2047 // operand to generate a function which returns its register number when
2048 // queried. CONST_INTER causes an operand to generate a function which
2049 // returns the value of the constant when queried. MEMORY_INTER causes an
2050 // operand to generate four functions which return the Base Register, the
2051 // Index Register, the Scale Value, and the Offset Value of the operand when
2052 // queried. COND_INTER causes an operand to generate six functions which
2053 // return the encoding code (ie - encoding bits for the instruction)
2054 // associated with each basic boolean condition for a conditional instruction.
2055 //
2056 // Instructions specify two basic values for encoding. Again, a function
2057 // is available to check if the constant displacement is an oop. They use the
2058 // ins_encode keyword to specify their encoding classes (which must be
2059 // a sequence of enc_class names, and their parameters, specified in
2060 // the encoding block), and they use the
2061 // opcode keyword to specify, in order, their primary, secondary, and
2062 // tertiary opcode. Only the opcode sections which a particular instruction
2063 // needs for encoding need to be specified.
2064 encode %{
2065 enc_class enc_untested %{
2066 #ifdef ASSERT
2067 MacroAssembler _masm(&cbuf);
2068 __ untested("encoding");
2069 #endif
2070 %}
2072 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2073 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2074 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2075 %}
2077 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2078 emit_form3_mem_reg(cbuf, this, $primary, -1,
2079 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2080 %}
2082 enc_class form3_mem_prefetch_read( memory mem ) %{
2083 emit_form3_mem_reg(cbuf, this, $primary, -1,
2084 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2085 %}
2087 enc_class form3_mem_prefetch_write( memory mem ) %{
2088 emit_form3_mem_reg(cbuf, this, $primary, -1,
2089 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2090 %}
2092 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2093 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2094 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2095 guarantee($mem$$index == R_G0_enc, "double index?");
2096 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2097 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2098 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2099 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2100 %}
2102 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2103 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2104 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2105 guarantee($mem$$index == R_G0_enc, "double index?");
2106 // Load long with 2 instructions
2107 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2108 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2109 %}
2111 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2112 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2113 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2114 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2115 %}
2117 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2118 // Encode a reg-reg copy. If it is useless, then empty encoding.
2119 if( $rs2$$reg != $rd$$reg )
2120 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2121 %}
2123 // Target lo half of long
2124 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2125 // Encode a reg-reg copy. If it is useless, then empty encoding.
2126 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2127 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2128 %}
2130 // Source lo half of long
2131 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2132 // Encode a reg-reg copy. If it is useless, then empty encoding.
2133 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2134 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2135 %}
2137 // Target hi half of long
2138 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2139 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2140 %}
2142 // Source lo half of long, and leave it sign extended.
2143 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2144 // Sign extend low half
2145 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2146 %}
2148 // Source hi half of long, and leave it sign extended.
2149 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2150 // Shift high half to low half
2151 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2152 %}
2154 // Source hi half of long
2155 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2156 // Encode a reg-reg copy. If it is useless, then empty encoding.
2157 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2158 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2159 %}
2161 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2162 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2163 %}
2165 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2166 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2167 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2168 %}
2170 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2171 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2172 // clear if nothing else is happening
2173 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2174 // blt,a,pn done
2175 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2176 // mov dst,-1 in delay slot
2177 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2178 %}
2180 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2181 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2182 %}
2184 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2185 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2186 %}
2188 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2189 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2190 %}
2192 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2193 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2194 %}
2196 enc_class move_return_pc_to_o1() %{
2197 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2198 %}
2200 #ifdef _LP64
2201 /* %%% merge with enc_to_bool */
2202 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2203 MacroAssembler _masm(&cbuf);
2205 Register src_reg = reg_to_register_object($src$$reg);
2206 Register dst_reg = reg_to_register_object($dst$$reg);
2207 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2208 %}
2209 #endif
2211 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2212 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2213 MacroAssembler _masm(&cbuf);
2215 Register p_reg = reg_to_register_object($p$$reg);
2216 Register q_reg = reg_to_register_object($q$$reg);
2217 Register y_reg = reg_to_register_object($y$$reg);
2218 Register tmp_reg = reg_to_register_object($tmp$$reg);
2220 __ subcc( p_reg, q_reg, p_reg );
2221 __ add ( p_reg, y_reg, tmp_reg );
2222 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2223 %}
2225 enc_class form_d2i_helper(regD src, regF dst) %{
2226 // fcmp %fcc0,$src,$src
2227 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2228 // branch %fcc0 not-nan, predict taken
2229 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2230 // fdtoi $src,$dst
2231 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2232 // fitos $dst,$dst (if nan)
2233 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2234 // clear $dst (if nan)
2235 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2236 // carry on here...
2237 %}
2239 enc_class form_d2l_helper(regD src, regD dst) %{
2240 // fcmp %fcc0,$src,$src check for NAN
2241 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2242 // branch %fcc0 not-nan, predict taken
2243 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2244 // fdtox $src,$dst convert in delay slot
2245 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2246 // fxtod $dst,$dst (if nan)
2247 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2248 // clear $dst (if nan)
2249 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2250 // carry on here...
2251 %}
2253 enc_class form_f2i_helper(regF src, regF dst) %{
2254 // fcmps %fcc0,$src,$src
2255 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2256 // branch %fcc0 not-nan, predict taken
2257 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2258 // fstoi $src,$dst
2259 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2260 // fitos $dst,$dst (if nan)
2261 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2262 // clear $dst (if nan)
2263 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2264 // carry on here...
2265 %}
2267 enc_class form_f2l_helper(regF src, regD dst) %{
2268 // fcmps %fcc0,$src,$src
2269 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2270 // branch %fcc0 not-nan, predict taken
2271 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2272 // fstox $src,$dst
2273 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2274 // fxtod $dst,$dst (if nan)
2275 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2276 // clear $dst (if nan)
2277 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2278 // carry on here...
2279 %}
2281 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2282 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2283 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2284 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2286 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2288 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2289 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2291 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2292 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2293 %}
2295 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2296 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2297 %}
2299 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2300 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2301 %}
2303 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2304 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2305 %}
2307 enc_class form3_convI2F(regF rs2, regF rd) %{
2308 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2309 %}
2311 // Encloding class for traceable jumps
2312 enc_class form_jmpl(g3RegP dest) %{
2313 emit_jmpl(cbuf, $dest$$reg);
2314 %}
2316 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2317 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2318 %}
2320 enc_class form2_nop() %{
2321 emit_nop(cbuf);
2322 %}
2324 enc_class form2_illtrap() %{
2325 emit_illtrap(cbuf);
2326 %}
2329 // Compare longs and convert into -1, 0, 1.
2330 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2331 // CMP $src1,$src2
2332 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2333 // blt,a,pn done
2334 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2335 // mov dst,-1 in delay slot
2336 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2337 // bgt,a,pn done
2338 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2339 // mov dst,1 in delay slot
2340 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2341 // CLR $dst
2342 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2343 %}
2345 enc_class enc_PartialSubtypeCheck() %{
2346 MacroAssembler _masm(&cbuf);
2347 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2348 __ delayed()->nop();
2349 %}
2351 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2352 MacroAssembler _masm(&cbuf);
2353 Label* L = $labl$$label;
2354 Assembler::Predict predict_taken =
2355 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2357 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2358 __ delayed()->nop();
2359 %}
2361 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2362 MacroAssembler _masm(&cbuf);
2363 Label* L = $labl$$label;
2364 Assembler::Predict predict_taken =
2365 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2367 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2368 __ delayed()->nop();
2369 %}
2371 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2372 int op = (Assembler::arith_op << 30) |
2373 ($dst$$reg << 25) |
2374 (Assembler::movcc_op3 << 19) |
2375 (1 << 18) | // cc2 bit for 'icc'
2376 ($cmp$$cmpcode << 14) |
2377 (0 << 13) | // select register move
2378 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2379 ($src$$reg << 0);
2380 cbuf.insts()->emit_int32(op);
2381 %}
2383 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2384 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2385 int op = (Assembler::arith_op << 30) |
2386 ($dst$$reg << 25) |
2387 (Assembler::movcc_op3 << 19) |
2388 (1 << 18) | // cc2 bit for 'icc'
2389 ($cmp$$cmpcode << 14) |
2390 (1 << 13) | // select immediate move
2391 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2392 (simm11 << 0);
2393 cbuf.insts()->emit_int32(op);
2394 %}
2396 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2397 int op = (Assembler::arith_op << 30) |
2398 ($dst$$reg << 25) |
2399 (Assembler::movcc_op3 << 19) |
2400 (0 << 18) | // cc2 bit for 'fccX'
2401 ($cmp$$cmpcode << 14) |
2402 (0 << 13) | // select register move
2403 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2404 ($src$$reg << 0);
2405 cbuf.insts()->emit_int32(op);
2406 %}
2408 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2409 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2410 int op = (Assembler::arith_op << 30) |
2411 ($dst$$reg << 25) |
2412 (Assembler::movcc_op3 << 19) |
2413 (0 << 18) | // cc2 bit for 'fccX'
2414 ($cmp$$cmpcode << 14) |
2415 (1 << 13) | // select immediate move
2416 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2417 (simm11 << 0);
2418 cbuf.insts()->emit_int32(op);
2419 %}
2421 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2422 int op = (Assembler::arith_op << 30) |
2423 ($dst$$reg << 25) |
2424 (Assembler::fpop2_op3 << 19) |
2425 (0 << 18) |
2426 ($cmp$$cmpcode << 14) |
2427 (1 << 13) | // select register move
2428 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2429 ($primary << 5) | // select single, double or quad
2430 ($src$$reg << 0);
2431 cbuf.insts()->emit_int32(op);
2432 %}
2434 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2435 int op = (Assembler::arith_op << 30) |
2436 ($dst$$reg << 25) |
2437 (Assembler::fpop2_op3 << 19) |
2438 (0 << 18) |
2439 ($cmp$$cmpcode << 14) |
2440 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2441 ($primary << 5) | // select single, double or quad
2442 ($src$$reg << 0);
2443 cbuf.insts()->emit_int32(op);
2444 %}
2446 // Used by the MIN/MAX encodings. Same as a CMOV, but
2447 // the condition comes from opcode-field instead of an argument.
2448 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2449 int op = (Assembler::arith_op << 30) |
2450 ($dst$$reg << 25) |
2451 (Assembler::movcc_op3 << 19) |
2452 (1 << 18) | // cc2 bit for 'icc'
2453 ($primary << 14) |
2454 (0 << 13) | // select register move
2455 (0 << 11) | // cc1, cc0 bits for 'icc'
2456 ($src$$reg << 0);
2457 cbuf.insts()->emit_int32(op);
2458 %}
2460 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2461 int op = (Assembler::arith_op << 30) |
2462 ($dst$$reg << 25) |
2463 (Assembler::movcc_op3 << 19) |
2464 (6 << 16) | // cc2 bit for 'xcc'
2465 ($primary << 14) |
2466 (0 << 13) | // select register move
2467 (0 << 11) | // cc1, cc0 bits for 'icc'
2468 ($src$$reg << 0);
2469 cbuf.insts()->emit_int32(op);
2470 %}
2472 enc_class Set13( immI13 src, iRegI rd ) %{
2473 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2474 %}
2476 enc_class SetHi22( immI src, iRegI rd ) %{
2477 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2478 %}
2480 enc_class Set32( immI src, iRegI rd ) %{
2481 MacroAssembler _masm(&cbuf);
2482 __ set($src$$constant, reg_to_register_object($rd$$reg));
2483 %}
2485 enc_class call_epilog %{
2486 if( VerifyStackAtCalls ) {
2487 MacroAssembler _masm(&cbuf);
2488 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2489 Register temp_reg = G3;
2490 __ add(SP, framesize, temp_reg);
2491 __ cmp(temp_reg, FP);
2492 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2493 }
2494 %}
2496 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2497 // to G1 so the register allocator will not have to deal with the misaligned register
2498 // pair.
2499 enc_class adjust_long_from_native_call %{
2500 #ifndef _LP64
2501 if (returns_long()) {
2502 // sllx O0,32,O0
2503 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2504 // srl O1,0,O1
2505 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2506 // or O0,O1,G1
2507 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2508 }
2509 #endif
2510 %}
2512 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2513 // CALL directly to the runtime
2514 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2515 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2516 /*preserve_g2=*/true);
2517 %}
2519 enc_class preserve_SP %{
2520 MacroAssembler _masm(&cbuf);
2521 __ mov(SP, L7_mh_SP_save);
2522 %}
2524 enc_class restore_SP %{
2525 MacroAssembler _masm(&cbuf);
2526 __ mov(L7_mh_SP_save, SP);
2527 %}
2529 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2530 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2531 // who we intended to call.
2532 if (!_method) {
2533 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2534 } else if (_optimized_virtual) {
2535 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2536 } else {
2537 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2538 }
2539 if (_method) { // Emit stub for static call.
2540 CompiledStaticCall::emit_to_interp_stub(cbuf);
2541 }
2542 %}
2544 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2545 MacroAssembler _masm(&cbuf);
2546 __ set_inst_mark();
2547 int vtable_index = this->_vtable_index;
2548 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2549 if (vtable_index < 0) {
2550 // must be invalid_vtable_index, not nonvirtual_vtable_index
2551 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2552 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2553 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2554 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2555 __ ic_call((address)$meth$$method);
2556 } else {
2557 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2558 // Just go thru the vtable
2559 // get receiver klass (receiver already checked for non-null)
2560 // If we end up going thru a c2i adapter interpreter expects method in G5
2561 int off = __ offset();
2562 __ load_klass(O0, G3_scratch);
2563 int klass_load_size;
2564 if (UseCompressedClassPointers) {
2565 assert(Universe::heap() != NULL, "java heap should be initialized");
2566 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2567 } else {
2568 klass_load_size = 1*BytesPerInstWord;
2569 }
2570 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2571 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2572 if (Assembler::is_simm13(v_off)) {
2573 __ ld_ptr(G3, v_off, G5_method);
2574 } else {
2575 // Generate 2 instructions
2576 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2577 __ or3(G5_method, v_off & 0x3ff, G5_method);
2578 // ld_ptr, set_hi, set
2579 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2580 "Unexpected instruction size(s)");
2581 __ ld_ptr(G3, G5_method, G5_method);
2582 }
2583 // NOTE: for vtable dispatches, the vtable entry will never be null.
2584 // However it may very well end up in handle_wrong_method if the
2585 // method is abstract for the particular class.
2586 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2587 // jump to target (either compiled code or c2iadapter)
2588 __ jmpl(G3_scratch, G0, O7);
2589 __ delayed()->nop();
2590 }
2591 %}
2593 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2594 MacroAssembler _masm(&cbuf);
2596 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2597 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2598 // we might be calling a C2I adapter which needs it.
2600 assert(temp_reg != G5_ic_reg, "conflicting registers");
2601 // Load nmethod
2602 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2604 // CALL to compiled java, indirect the contents of G3
2605 __ set_inst_mark();
2606 __ callr(temp_reg, G0);
2607 __ delayed()->nop();
2608 %}
2610 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2611 MacroAssembler _masm(&cbuf);
2612 Register Rdividend = reg_to_register_object($src1$$reg);
2613 Register Rdivisor = reg_to_register_object($src2$$reg);
2614 Register Rresult = reg_to_register_object($dst$$reg);
2616 __ sra(Rdivisor, 0, Rdivisor);
2617 __ sra(Rdividend, 0, Rdividend);
2618 __ sdivx(Rdividend, Rdivisor, Rresult);
2619 %}
2621 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2622 MacroAssembler _masm(&cbuf);
2624 Register Rdividend = reg_to_register_object($src1$$reg);
2625 int divisor = $imm$$constant;
2626 Register Rresult = reg_to_register_object($dst$$reg);
2628 __ sra(Rdividend, 0, Rdividend);
2629 __ sdivx(Rdividend, divisor, Rresult);
2630 %}
2632 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2633 MacroAssembler _masm(&cbuf);
2634 Register Rsrc1 = reg_to_register_object($src1$$reg);
2635 Register Rsrc2 = reg_to_register_object($src2$$reg);
2636 Register Rdst = reg_to_register_object($dst$$reg);
2638 __ sra( Rsrc1, 0, Rsrc1 );
2639 __ sra( Rsrc2, 0, Rsrc2 );
2640 __ mulx( Rsrc1, Rsrc2, Rdst );
2641 __ srlx( Rdst, 32, Rdst );
2642 %}
2644 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2645 MacroAssembler _masm(&cbuf);
2646 Register Rdividend = reg_to_register_object($src1$$reg);
2647 Register Rdivisor = reg_to_register_object($src2$$reg);
2648 Register Rresult = reg_to_register_object($dst$$reg);
2649 Register Rscratch = reg_to_register_object($scratch$$reg);
2651 assert(Rdividend != Rscratch, "");
2652 assert(Rdivisor != Rscratch, "");
2654 __ sra(Rdividend, 0, Rdividend);
2655 __ sra(Rdivisor, 0, Rdivisor);
2656 __ sdivx(Rdividend, Rdivisor, Rscratch);
2657 __ mulx(Rscratch, Rdivisor, Rscratch);
2658 __ sub(Rdividend, Rscratch, Rresult);
2659 %}
2661 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2662 MacroAssembler _masm(&cbuf);
2664 Register Rdividend = reg_to_register_object($src1$$reg);
2665 int divisor = $imm$$constant;
2666 Register Rresult = reg_to_register_object($dst$$reg);
2667 Register Rscratch = reg_to_register_object($scratch$$reg);
2669 assert(Rdividend != Rscratch, "");
2671 __ sra(Rdividend, 0, Rdividend);
2672 __ sdivx(Rdividend, divisor, Rscratch);
2673 __ mulx(Rscratch, divisor, Rscratch);
2674 __ sub(Rdividend, Rscratch, Rresult);
2675 %}
2677 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2678 MacroAssembler _masm(&cbuf);
2680 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2681 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2683 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2684 %}
2686 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2687 MacroAssembler _masm(&cbuf);
2689 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2690 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2692 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2693 %}
2695 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2696 MacroAssembler _masm(&cbuf);
2698 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2699 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2701 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2702 %}
2704 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2705 MacroAssembler _masm(&cbuf);
2707 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2708 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2710 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2711 %}
2713 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2714 MacroAssembler _masm(&cbuf);
2716 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2717 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2719 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2720 %}
2722 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2723 MacroAssembler _masm(&cbuf);
2725 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2726 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2728 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2729 %}
2731 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2732 MacroAssembler _masm(&cbuf);
2734 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2735 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2737 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2738 %}
2740 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2741 MacroAssembler _masm(&cbuf);
2743 Register Roop = reg_to_register_object($oop$$reg);
2744 Register Rbox = reg_to_register_object($box$$reg);
2745 Register Rscratch = reg_to_register_object($scratch$$reg);
2746 Register Rmark = reg_to_register_object($scratch2$$reg);
2748 assert(Roop != Rscratch, "");
2749 assert(Roop != Rmark, "");
2750 assert(Rbox != Rscratch, "");
2751 assert(Rbox != Rmark, "");
2753 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2754 %}
2756 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2757 MacroAssembler _masm(&cbuf);
2759 Register Roop = reg_to_register_object($oop$$reg);
2760 Register Rbox = reg_to_register_object($box$$reg);
2761 Register Rscratch = reg_to_register_object($scratch$$reg);
2762 Register Rmark = reg_to_register_object($scratch2$$reg);
2764 assert(Roop != Rscratch, "");
2765 assert(Roop != Rmark, "");
2766 assert(Rbox != Rscratch, "");
2767 assert(Rbox != Rmark, "");
2769 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2770 %}
2772 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2773 MacroAssembler _masm(&cbuf);
2774 Register Rmem = reg_to_register_object($mem$$reg);
2775 Register Rold = reg_to_register_object($old$$reg);
2776 Register Rnew = reg_to_register_object($new$$reg);
2778 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2779 __ cmp( Rold, Rnew );
2780 %}
2782 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2783 Register Rmem = reg_to_register_object($mem$$reg);
2784 Register Rold = reg_to_register_object($old$$reg);
2785 Register Rnew = reg_to_register_object($new$$reg);
2787 MacroAssembler _masm(&cbuf);
2788 __ mov(Rnew, O7);
2789 __ casx(Rmem, Rold, O7);
2790 __ cmp( Rold, O7 );
2791 %}
2793 // raw int cas, used for compareAndSwap
2794 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2795 Register Rmem = reg_to_register_object($mem$$reg);
2796 Register Rold = reg_to_register_object($old$$reg);
2797 Register Rnew = reg_to_register_object($new$$reg);
2799 MacroAssembler _masm(&cbuf);
2800 __ mov(Rnew, O7);
2801 __ cas(Rmem, Rold, O7);
2802 __ cmp( Rold, O7 );
2803 %}
2805 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2806 Register Rres = reg_to_register_object($res$$reg);
2808 MacroAssembler _masm(&cbuf);
2809 __ mov(1, Rres);
2810 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2811 %}
2813 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2814 Register Rres = reg_to_register_object($res$$reg);
2816 MacroAssembler _masm(&cbuf);
2817 __ mov(1, Rres);
2818 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2819 %}
2821 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2822 MacroAssembler _masm(&cbuf);
2823 Register Rdst = reg_to_register_object($dst$$reg);
2824 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2825 : reg_to_DoubleFloatRegister_object($src1$$reg);
2826 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2827 : reg_to_DoubleFloatRegister_object($src2$$reg);
2829 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2830 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2831 %}
2834 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2835 Label Ldone, Lloop;
2836 MacroAssembler _masm(&cbuf);
2838 Register str1_reg = reg_to_register_object($str1$$reg);
2839 Register str2_reg = reg_to_register_object($str2$$reg);
2840 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2841 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2842 Register result_reg = reg_to_register_object($result$$reg);
2844 assert(result_reg != str1_reg &&
2845 result_reg != str2_reg &&
2846 result_reg != cnt1_reg &&
2847 result_reg != cnt2_reg ,
2848 "need different registers");
2850 // Compute the minimum of the string lengths(str1_reg) and the
2851 // difference of the string lengths (stack)
2853 // See if the lengths are different, and calculate min in str1_reg.
2854 // Stash diff in O7 in case we need it for a tie-breaker.
2855 Label Lskip;
2856 __ subcc(cnt1_reg, cnt2_reg, O7);
2857 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2858 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2859 // cnt2 is shorter, so use its count:
2860 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2861 __ bind(Lskip);
2863 // reallocate cnt1_reg, cnt2_reg, result_reg
2864 // Note: limit_reg holds the string length pre-scaled by 2
2865 Register limit_reg = cnt1_reg;
2866 Register chr2_reg = cnt2_reg;
2867 Register chr1_reg = result_reg;
2868 // str{12} are the base pointers
2870 // Is the minimum length zero?
2871 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2872 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2873 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2875 // Load first characters
2876 __ lduh(str1_reg, 0, chr1_reg);
2877 __ lduh(str2_reg, 0, chr2_reg);
2879 // Compare first characters
2880 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2881 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2882 assert(chr1_reg == result_reg, "result must be pre-placed");
2883 __ delayed()->nop();
2885 {
2886 // Check after comparing first character to see if strings are equivalent
2887 Label LSkip2;
2888 // Check if the strings start at same location
2889 __ cmp(str1_reg, str2_reg);
2890 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2891 __ delayed()->nop();
2893 // Check if the length difference is zero (in O7)
2894 __ cmp(G0, O7);
2895 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2896 __ delayed()->mov(G0, result_reg); // result is zero
2898 // Strings might not be equal
2899 __ bind(LSkip2);
2900 }
2902 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2903 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2904 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2906 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2907 __ add(str1_reg, limit_reg, str1_reg);
2908 __ add(str2_reg, limit_reg, str2_reg);
2909 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2911 // Compare the rest of the characters
2912 __ lduh(str1_reg, limit_reg, chr1_reg);
2913 __ bind(Lloop);
2914 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2915 __ lduh(str2_reg, limit_reg, chr2_reg);
2916 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2917 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2918 assert(chr1_reg == result_reg, "result must be pre-placed");
2919 __ delayed()->inccc(limit_reg, sizeof(jchar));
2920 // annul LDUH if branch is not taken to prevent access past end of string
2921 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2922 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2924 // If strings are equal up to min length, return the length difference.
2925 __ mov(O7, result_reg);
2927 // Otherwise, return the difference between the first mismatched chars.
2928 __ bind(Ldone);
2929 %}
2931 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2932 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2933 MacroAssembler _masm(&cbuf);
2935 Register str1_reg = reg_to_register_object($str1$$reg);
2936 Register str2_reg = reg_to_register_object($str2$$reg);
2937 Register cnt_reg = reg_to_register_object($cnt$$reg);
2938 Register tmp1_reg = O7;
2939 Register result_reg = reg_to_register_object($result$$reg);
2941 assert(result_reg != str1_reg &&
2942 result_reg != str2_reg &&
2943 result_reg != cnt_reg &&
2944 result_reg != tmp1_reg ,
2945 "need different registers");
2947 __ cmp(str1_reg, str2_reg); //same char[] ?
2948 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2949 __ delayed()->add(G0, 1, result_reg);
2951 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2952 __ delayed()->add(G0, 1, result_reg); // count == 0
2954 //rename registers
2955 Register limit_reg = cnt_reg;
2956 Register chr1_reg = result_reg;
2957 Register chr2_reg = tmp1_reg;
2959 //check for alignment and position the pointers to the ends
2960 __ or3(str1_reg, str2_reg, chr1_reg);
2961 __ andcc(chr1_reg, 0x3, chr1_reg);
2962 // notZero means at least one not 4-byte aligned.
2963 // We could optimize the case when both arrays are not aligned
2964 // but it is not frequent case and it requires additional checks.
2965 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2966 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2968 // Compare char[] arrays aligned to 4 bytes.
2969 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2970 chr1_reg, chr2_reg, Ldone);
2971 __ ba(Ldone);
2972 __ delayed()->add(G0, 1, result_reg);
2974 // char by char compare
2975 __ bind(Lchar);
2976 __ add(str1_reg, limit_reg, str1_reg);
2977 __ add(str2_reg, limit_reg, str2_reg);
2978 __ neg(limit_reg); //negate count
2980 __ lduh(str1_reg, limit_reg, chr1_reg);
2981 // Lchar_loop
2982 __ bind(Lchar_loop);
2983 __ lduh(str2_reg, limit_reg, chr2_reg);
2984 __ cmp(chr1_reg, chr2_reg);
2985 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2986 __ delayed()->mov(G0, result_reg); //not equal
2987 __ inccc(limit_reg, sizeof(jchar));
2988 // annul LDUH if branch is not taken to prevent access past end of string
2989 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2990 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2992 __ add(G0, 1, result_reg); //equal
2994 __ bind(Ldone);
2995 %}
2997 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2998 Label Lvector, Ldone, Lloop;
2999 MacroAssembler _masm(&cbuf);
3001 Register ary1_reg = reg_to_register_object($ary1$$reg);
3002 Register ary2_reg = reg_to_register_object($ary2$$reg);
3003 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3004 Register tmp2_reg = O7;
3005 Register result_reg = reg_to_register_object($result$$reg);
3007 int length_offset = arrayOopDesc::length_offset_in_bytes();
3008 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3010 // return true if the same array
3011 __ cmp(ary1_reg, ary2_reg);
3012 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3013 __ delayed()->add(G0, 1, result_reg); // equal
3015 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3016 __ delayed()->mov(G0, result_reg); // not equal
3018 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3019 __ delayed()->mov(G0, result_reg); // not equal
3021 //load the lengths of arrays
3022 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3023 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3025 // return false if the two arrays are not equal length
3026 __ cmp(tmp1_reg, tmp2_reg);
3027 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3028 __ delayed()->mov(G0, result_reg); // not equal
3030 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3031 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3033 // load array addresses
3034 __ add(ary1_reg, base_offset, ary1_reg);
3035 __ add(ary2_reg, base_offset, ary2_reg);
3037 // renaming registers
3038 Register chr1_reg = result_reg; // for characters in ary1
3039 Register chr2_reg = tmp2_reg; // for characters in ary2
3040 Register limit_reg = tmp1_reg; // length
3042 // set byte count
3043 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3045 // Compare char[] arrays aligned to 4 bytes.
3046 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3047 chr1_reg, chr2_reg, Ldone);
3048 __ add(G0, 1, result_reg); // equals
3050 __ bind(Ldone);
3051 %}
3053 enc_class enc_rethrow() %{
3054 cbuf.set_insts_mark();
3055 Register temp_reg = G3;
3056 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3057 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3058 MacroAssembler _masm(&cbuf);
3059 #ifdef ASSERT
3060 __ save_frame(0);
3061 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3062 __ sethi(last_rethrow_addrlit, L1);
3063 Address addr(L1, last_rethrow_addrlit.low10());
3064 __ rdpc(L2);
3065 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3066 __ st_ptr(L2, addr);
3067 __ restore();
3068 #endif
3069 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3070 __ delayed()->nop();
3071 %}
3073 enc_class emit_mem_nop() %{
3074 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3075 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3076 %}
3078 enc_class emit_fadd_nop() %{
3079 // Generates the instruction FMOVS f31,f31
3080 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3081 %}
3083 enc_class emit_br_nop() %{
3084 // Generates the instruction BPN,PN .
3085 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3086 %}
3088 enc_class enc_membar_acquire %{
3089 MacroAssembler _masm(&cbuf);
3090 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3091 %}
3093 enc_class enc_membar_release %{
3094 MacroAssembler _masm(&cbuf);
3095 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3096 %}
3098 enc_class enc_membar_volatile %{
3099 MacroAssembler _masm(&cbuf);
3100 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3101 %}
3103 %}
3105 //----------FRAME--------------------------------------------------------------
3106 // Definition of frame structure and management information.
3107 //
3108 // S T A C K L A Y O U T Allocators stack-slot number
3109 // | (to get allocators register number
3110 // G Owned by | | v add VMRegImpl::stack0)
3111 // r CALLER | |
3112 // o | +--------+ pad to even-align allocators stack-slot
3113 // w V | pad0 | numbers; owned by CALLER
3114 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3115 // h ^ | in | 5
3116 // | | args | 4 Holes in incoming args owned by SELF
3117 // | | | | 3
3118 // | | +--------+
3119 // V | | old out| Empty on Intel, window on Sparc
3120 // | old |preserve| Must be even aligned.
3121 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3122 // | | in | 3 area for Intel ret address
3123 // Owned by |preserve| Empty on Sparc.
3124 // SELF +--------+
3125 // | | pad2 | 2 pad to align old SP
3126 // | +--------+ 1
3127 // | | locks | 0
3128 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3129 // | | pad1 | 11 pad to align new SP
3130 // | +--------+
3131 // | | | 10
3132 // | | spills | 9 spills
3133 // V | | 8 (pad0 slot for callee)
3134 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3135 // ^ | out | 7
3136 // | | args | 6 Holes in outgoing args owned by CALLEE
3137 // Owned by +--------+
3138 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3139 // | new |preserve| Must be even-aligned.
3140 // | SP-+--------+----> Matcher::_new_SP, even aligned
3141 // | | |
3142 //
3143 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3144 // known from SELF's arguments and the Java calling convention.
3145 // Region 6-7 is determined per call site.
3146 // Note 2: If the calling convention leaves holes in the incoming argument
3147 // area, those holes are owned by SELF. Holes in the outgoing area
3148 // are owned by the CALLEE. Holes should not be nessecary in the
3149 // incoming area, as the Java calling convention is completely under
3150 // the control of the AD file. Doubles can be sorted and packed to
3151 // avoid holes. Holes in the outgoing arguments may be nessecary for
3152 // varargs C calling conventions.
3153 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3154 // even aligned with pad0 as needed.
3155 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3156 // region 6-11 is even aligned; it may be padded out more so that
3157 // the region from SP to FP meets the minimum stack alignment.
3159 frame %{
3160 // What direction does stack grow in (assumed to be same for native & Java)
3161 stack_direction(TOWARDS_LOW);
3163 // These two registers define part of the calling convention
3164 // between compiled code and the interpreter.
3165 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3166 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3168 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3169 cisc_spilling_operand_name(indOffset);
3171 // Number of stack slots consumed by a Monitor enter
3172 #ifdef _LP64
3173 sync_stack_slots(2);
3174 #else
3175 sync_stack_slots(1);
3176 #endif
3178 // Compiled code's Frame Pointer
3179 frame_pointer(R_SP);
3181 // Stack alignment requirement
3182 stack_alignment(StackAlignmentInBytes);
3183 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3184 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3186 // Number of stack slots between incoming argument block and the start of
3187 // a new frame. The PROLOG must add this many slots to the stack. The
3188 // EPILOG must remove this many slots.
3189 in_preserve_stack_slots(0);
3191 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3192 // for calls to C. Supports the var-args backing area for register parms.
3193 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3194 #ifdef _LP64
3195 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3196 varargs_C_out_slots_killed(12);
3197 #else
3198 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3199 varargs_C_out_slots_killed( 7);
3200 #endif
3202 // The after-PROLOG location of the return address. Location of
3203 // return address specifies a type (REG or STACK) and a number
3204 // representing the register number (i.e. - use a register name) or
3205 // stack slot.
3206 return_addr(REG R_I7); // Ret Addr is in register I7
3208 // Body of function which returns an OptoRegs array locating
3209 // arguments either in registers or in stack slots for calling
3210 // java
3211 calling_convention %{
3212 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3214 %}
3216 // Body of function which returns an OptoRegs array locating
3217 // arguments either in registers or in stack slots for callin
3218 // C.
3219 c_calling_convention %{
3220 // This is obviously always outgoing
3221 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3222 %}
3224 // Location of native (C/C++) and interpreter return values. This is specified to
3225 // be the same as Java. In the 32-bit VM, long values are actually returned from
3226 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3227 // to and from the register pairs is done by the appropriate call and epilog
3228 // opcodes. This simplifies the register allocator.
3229 c_return_value %{
3230 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3231 #ifdef _LP64
3232 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3233 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3234 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3235 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3236 #else // !_LP64
3237 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3238 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3239 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3240 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3241 #endif
3242 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3243 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3244 %}
3246 // Location of compiled Java return values. Same as C
3247 return_value %{
3248 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3249 #ifdef _LP64
3250 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3251 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3252 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3253 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3254 #else // !_LP64
3255 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3256 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3257 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3258 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3259 #endif
3260 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3261 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3262 %}
3264 %}
3267 //----------ATTRIBUTES---------------------------------------------------------
3268 //----------Operand Attributes-------------------------------------------------
3269 op_attrib op_cost(1); // Required cost attribute
3271 //----------Instruction Attributes---------------------------------------------
3272 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3273 ins_attrib ins_size(32); // Required size attribute (in bits)
3274 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3275 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3276 // non-matching short branch variant of some
3277 // long branch?
3279 //----------OPERANDS-----------------------------------------------------------
3280 // Operand definitions must precede instruction definitions for correct parsing
3281 // in the ADLC because operands constitute user defined types which are used in
3282 // instruction definitions.
3284 //----------Simple Operands----------------------------------------------------
3285 // Immediate Operands
3286 // Integer Immediate: 32-bit
3287 operand immI() %{
3288 match(ConI);
3290 op_cost(0);
3291 // formats are generated automatically for constants and base registers
3292 format %{ %}
3293 interface(CONST_INTER);
3294 %}
3296 // Integer Immediate: 8-bit
3297 operand immI8() %{
3298 predicate(Assembler::is_simm8(n->get_int()));
3299 match(ConI);
3300 op_cost(0);
3301 format %{ %}
3302 interface(CONST_INTER);
3303 %}
3305 // Integer Immediate: 13-bit
3306 operand immI13() %{
3307 predicate(Assembler::is_simm13(n->get_int()));
3308 match(ConI);
3309 op_cost(0);
3311 format %{ %}
3312 interface(CONST_INTER);
3313 %}
3315 // Integer Immediate: 13-bit minus 7
3316 operand immI13m7() %{
3317 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3318 match(ConI);
3319 op_cost(0);
3321 format %{ %}
3322 interface(CONST_INTER);
3323 %}
3325 // Integer Immediate: 16-bit
3326 operand immI16() %{
3327 predicate(Assembler::is_simm16(n->get_int()));
3328 match(ConI);
3329 op_cost(0);
3330 format %{ %}
3331 interface(CONST_INTER);
3332 %}
3334 // Unsigned (positive) Integer Immediate: 13-bit
3335 operand immU13() %{
3336 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3337 match(ConI);
3338 op_cost(0);
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3344 // Integer Immediate: 6-bit
3345 operand immU6() %{
3346 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3347 match(ConI);
3348 op_cost(0);
3349 format %{ %}
3350 interface(CONST_INTER);
3351 %}
3353 // Integer Immediate: 11-bit
3354 operand immI11() %{
3355 predicate(Assembler::is_simm11(n->get_int()));
3356 match(ConI);
3357 op_cost(0);
3358 format %{ %}
3359 interface(CONST_INTER);
3360 %}
3362 // Integer Immediate: 5-bit
3363 operand immI5() %{
3364 predicate(Assembler::is_simm5(n->get_int()));
3365 match(ConI);
3366 op_cost(0);
3367 format %{ %}
3368 interface(CONST_INTER);
3369 %}
3371 // Integer Immediate: 0-bit
3372 operand immI0() %{
3373 predicate(n->get_int() == 0);
3374 match(ConI);
3375 op_cost(0);
3377 format %{ %}
3378 interface(CONST_INTER);
3379 %}
3381 // Integer Immediate: the value 10
3382 operand immI10() %{
3383 predicate(n->get_int() == 10);
3384 match(ConI);
3385 op_cost(0);
3387 format %{ %}
3388 interface(CONST_INTER);
3389 %}
3391 // Integer Immediate: the values 0-31
3392 operand immU5() %{
3393 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3394 match(ConI);
3395 op_cost(0);
3397 format %{ %}
3398 interface(CONST_INTER);
3399 %}
3401 // Integer Immediate: the values 1-31
3402 operand immI_1_31() %{
3403 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3404 match(ConI);
3405 op_cost(0);
3407 format %{ %}
3408 interface(CONST_INTER);
3409 %}
3411 // Integer Immediate: the values 32-63
3412 operand immI_32_63() %{
3413 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3414 match(ConI);
3415 op_cost(0);
3417 format %{ %}
3418 interface(CONST_INTER);
3419 %}
3421 // Immediates for special shifts (sign extend)
3423 // Integer Immediate: the value 16
3424 operand immI_16() %{
3425 predicate(n->get_int() == 16);
3426 match(ConI);
3427 op_cost(0);
3429 format %{ %}
3430 interface(CONST_INTER);
3431 %}
3433 // Integer Immediate: the value 24
3434 operand immI_24() %{
3435 predicate(n->get_int() == 24);
3436 match(ConI);
3437 op_cost(0);
3439 format %{ %}
3440 interface(CONST_INTER);
3441 %}
3443 // Integer Immediate: the value 255
3444 operand immI_255() %{
3445 predicate( n->get_int() == 255 );
3446 match(ConI);
3447 op_cost(0);
3449 format %{ %}
3450 interface(CONST_INTER);
3451 %}
3453 // Integer Immediate: the value 65535
3454 operand immI_65535() %{
3455 predicate(n->get_int() == 65535);
3456 match(ConI);
3457 op_cost(0);
3459 format %{ %}
3460 interface(CONST_INTER);
3461 %}
3463 // Long Immediate: the value FF
3464 operand immL_FF() %{
3465 predicate( n->get_long() == 0xFFL );
3466 match(ConL);
3467 op_cost(0);
3469 format %{ %}
3470 interface(CONST_INTER);
3471 %}
3473 // Long Immediate: the value FFFF
3474 operand immL_FFFF() %{
3475 predicate( n->get_long() == 0xFFFFL );
3476 match(ConL);
3477 op_cost(0);
3479 format %{ %}
3480 interface(CONST_INTER);
3481 %}
3483 // Pointer Immediate: 32 or 64-bit
3484 operand immP() %{
3485 match(ConP);
3487 op_cost(5);
3488 // formats are generated automatically for constants and base registers
3489 format %{ %}
3490 interface(CONST_INTER);
3491 %}
3493 #ifdef _LP64
3494 // Pointer Immediate: 64-bit
3495 operand immP_set() %{
3496 predicate(!VM_Version::is_niagara_plus());
3497 match(ConP);
3499 op_cost(5);
3500 // formats are generated automatically for constants and base registers
3501 format %{ %}
3502 interface(CONST_INTER);
3503 %}
3505 // Pointer Immediate: 64-bit
3506 // From Niagara2 processors on a load should be better than materializing.
3507 operand immP_load() %{
3508 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3509 match(ConP);
3511 op_cost(5);
3512 // formats are generated automatically for constants and base registers
3513 format %{ %}
3514 interface(CONST_INTER);
3515 %}
3517 // Pointer Immediate: 64-bit
3518 operand immP_no_oop_cheap() %{
3519 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3520 match(ConP);
3522 op_cost(5);
3523 // formats are generated automatically for constants and base registers
3524 format %{ %}
3525 interface(CONST_INTER);
3526 %}
3527 #endif
3529 operand immP13() %{
3530 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3531 match(ConP);
3532 op_cost(0);
3534 format %{ %}
3535 interface(CONST_INTER);
3536 %}
3538 operand immP0() %{
3539 predicate(n->get_ptr() == 0);
3540 match(ConP);
3541 op_cost(0);
3543 format %{ %}
3544 interface(CONST_INTER);
3545 %}
3547 operand immP_poll() %{
3548 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3549 match(ConP);
3551 // formats are generated automatically for constants and base registers
3552 format %{ %}
3553 interface(CONST_INTER);
3554 %}
3556 // Pointer Immediate
3557 operand immN()
3558 %{
3559 match(ConN);
3561 op_cost(10);
3562 format %{ %}
3563 interface(CONST_INTER);
3564 %}
3566 operand immNKlass()
3567 %{
3568 match(ConNKlass);
3570 op_cost(10);
3571 format %{ %}
3572 interface(CONST_INTER);
3573 %}
3575 // NULL Pointer Immediate
3576 operand immN0()
3577 %{
3578 predicate(n->get_narrowcon() == 0);
3579 match(ConN);
3581 op_cost(0);
3582 format %{ %}
3583 interface(CONST_INTER);
3584 %}
3586 operand immL() %{
3587 match(ConL);
3588 op_cost(40);
3589 // formats are generated automatically for constants and base registers
3590 format %{ %}
3591 interface(CONST_INTER);
3592 %}
3594 operand immL0() %{
3595 predicate(n->get_long() == 0L);
3596 match(ConL);
3597 op_cost(0);
3598 // formats are generated automatically for constants and base registers
3599 format %{ %}
3600 interface(CONST_INTER);
3601 %}
3603 // Integer Immediate: 5-bit
3604 operand immL5() %{
3605 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3606 match(ConL);
3607 op_cost(0);
3608 format %{ %}
3609 interface(CONST_INTER);
3610 %}
3612 // Long Immediate: 13-bit
3613 operand immL13() %{
3614 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3615 match(ConL);
3616 op_cost(0);
3618 format %{ %}
3619 interface(CONST_INTER);
3620 %}
3622 // Long Immediate: 13-bit minus 7
3623 operand immL13m7() %{
3624 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3625 match(ConL);
3626 op_cost(0);
3628 format %{ %}
3629 interface(CONST_INTER);
3630 %}
3632 // Long Immediate: low 32-bit mask
3633 operand immL_32bits() %{
3634 predicate(n->get_long() == 0xFFFFFFFFL);
3635 match(ConL);
3636 op_cost(0);
3638 format %{ %}
3639 interface(CONST_INTER);
3640 %}
3642 // Long Immediate: cheap (materialize in <= 3 instructions)
3643 operand immL_cheap() %{
3644 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3645 match(ConL);
3646 op_cost(0);
3648 format %{ %}
3649 interface(CONST_INTER);
3650 %}
3652 // Long Immediate: expensive (materialize in > 3 instructions)
3653 operand immL_expensive() %{
3654 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3655 match(ConL);
3656 op_cost(0);
3658 format %{ %}
3659 interface(CONST_INTER);
3660 %}
3662 // Double Immediate
3663 operand immD() %{
3664 match(ConD);
3666 op_cost(40);
3667 format %{ %}
3668 interface(CONST_INTER);
3669 %}
3671 operand immD0() %{
3672 #ifdef _LP64
3673 // on 64-bit architectures this comparision is faster
3674 predicate(jlong_cast(n->getd()) == 0);
3675 #else
3676 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3677 #endif
3678 match(ConD);
3680 op_cost(0);
3681 format %{ %}
3682 interface(CONST_INTER);
3683 %}
3685 // Float Immediate
3686 operand immF() %{
3687 match(ConF);
3689 op_cost(20);
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3694 // Float Immediate: 0
3695 operand immF0() %{
3696 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3697 match(ConF);
3699 op_cost(0);
3700 format %{ %}
3701 interface(CONST_INTER);
3702 %}
3704 // Integer Register Operands
3705 // Integer Register
3706 operand iRegI() %{
3707 constraint(ALLOC_IN_RC(int_reg));
3708 match(RegI);
3710 match(notemp_iRegI);
3711 match(g1RegI);
3712 match(o0RegI);
3713 match(iRegIsafe);
3715 format %{ %}
3716 interface(REG_INTER);
3717 %}
3719 operand notemp_iRegI() %{
3720 constraint(ALLOC_IN_RC(notemp_int_reg));
3721 match(RegI);
3723 match(o0RegI);
3725 format %{ %}
3726 interface(REG_INTER);
3727 %}
3729 operand o0RegI() %{
3730 constraint(ALLOC_IN_RC(o0_regI));
3731 match(iRegI);
3733 format %{ %}
3734 interface(REG_INTER);
3735 %}
3737 // Pointer Register
3738 operand iRegP() %{
3739 constraint(ALLOC_IN_RC(ptr_reg));
3740 match(RegP);
3742 match(lock_ptr_RegP);
3743 match(g1RegP);
3744 match(g2RegP);
3745 match(g3RegP);
3746 match(g4RegP);
3747 match(i0RegP);
3748 match(o0RegP);
3749 match(o1RegP);
3750 match(l7RegP);
3752 format %{ %}
3753 interface(REG_INTER);
3754 %}
3756 operand sp_ptr_RegP() %{
3757 constraint(ALLOC_IN_RC(sp_ptr_reg));
3758 match(RegP);
3759 match(iRegP);
3761 format %{ %}
3762 interface(REG_INTER);
3763 %}
3765 operand lock_ptr_RegP() %{
3766 constraint(ALLOC_IN_RC(lock_ptr_reg));
3767 match(RegP);
3768 match(i0RegP);
3769 match(o0RegP);
3770 match(o1RegP);
3771 match(l7RegP);
3773 format %{ %}
3774 interface(REG_INTER);
3775 %}
3777 operand g1RegP() %{
3778 constraint(ALLOC_IN_RC(g1_regP));
3779 match(iRegP);
3781 format %{ %}
3782 interface(REG_INTER);
3783 %}
3785 operand g2RegP() %{
3786 constraint(ALLOC_IN_RC(g2_regP));
3787 match(iRegP);
3789 format %{ %}
3790 interface(REG_INTER);
3791 %}
3793 operand g3RegP() %{
3794 constraint(ALLOC_IN_RC(g3_regP));
3795 match(iRegP);
3797 format %{ %}
3798 interface(REG_INTER);
3799 %}
3801 operand g1RegI() %{
3802 constraint(ALLOC_IN_RC(g1_regI));
3803 match(iRegI);
3805 format %{ %}
3806 interface(REG_INTER);
3807 %}
3809 operand g3RegI() %{
3810 constraint(ALLOC_IN_RC(g3_regI));
3811 match(iRegI);
3813 format %{ %}
3814 interface(REG_INTER);
3815 %}
3817 operand g4RegI() %{
3818 constraint(ALLOC_IN_RC(g4_regI));
3819 match(iRegI);
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3825 operand g4RegP() %{
3826 constraint(ALLOC_IN_RC(g4_regP));
3827 match(iRegP);
3829 format %{ %}
3830 interface(REG_INTER);
3831 %}
3833 operand i0RegP() %{
3834 constraint(ALLOC_IN_RC(i0_regP));
3835 match(iRegP);
3837 format %{ %}
3838 interface(REG_INTER);
3839 %}
3841 operand o0RegP() %{
3842 constraint(ALLOC_IN_RC(o0_regP));
3843 match(iRegP);
3845 format %{ %}
3846 interface(REG_INTER);
3847 %}
3849 operand o1RegP() %{
3850 constraint(ALLOC_IN_RC(o1_regP));
3851 match(iRegP);
3853 format %{ %}
3854 interface(REG_INTER);
3855 %}
3857 operand o2RegP() %{
3858 constraint(ALLOC_IN_RC(o2_regP));
3859 match(iRegP);
3861 format %{ %}
3862 interface(REG_INTER);
3863 %}
3865 operand o7RegP() %{
3866 constraint(ALLOC_IN_RC(o7_regP));
3867 match(iRegP);
3869 format %{ %}
3870 interface(REG_INTER);
3871 %}
3873 operand l7RegP() %{
3874 constraint(ALLOC_IN_RC(l7_regP));
3875 match(iRegP);
3877 format %{ %}
3878 interface(REG_INTER);
3879 %}
3881 operand o7RegI() %{
3882 constraint(ALLOC_IN_RC(o7_regI));
3883 match(iRegI);
3885 format %{ %}
3886 interface(REG_INTER);
3887 %}
3889 operand iRegN() %{
3890 constraint(ALLOC_IN_RC(int_reg));
3891 match(RegN);
3893 format %{ %}
3894 interface(REG_INTER);
3895 %}
3897 // Long Register
3898 operand iRegL() %{
3899 constraint(ALLOC_IN_RC(long_reg));
3900 match(RegL);
3902 format %{ %}
3903 interface(REG_INTER);
3904 %}
3906 operand o2RegL() %{
3907 constraint(ALLOC_IN_RC(o2_regL));
3908 match(iRegL);
3910 format %{ %}
3911 interface(REG_INTER);
3912 %}
3914 operand o7RegL() %{
3915 constraint(ALLOC_IN_RC(o7_regL));
3916 match(iRegL);
3918 format %{ %}
3919 interface(REG_INTER);
3920 %}
3922 operand g1RegL() %{
3923 constraint(ALLOC_IN_RC(g1_regL));
3924 match(iRegL);
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3930 operand g3RegL() %{
3931 constraint(ALLOC_IN_RC(g3_regL));
3932 match(iRegL);
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3938 // Int Register safe
3939 // This is 64bit safe
3940 operand iRegIsafe() %{
3941 constraint(ALLOC_IN_RC(long_reg));
3943 match(iRegI);
3945 format %{ %}
3946 interface(REG_INTER);
3947 %}
3949 // Condition Code Flag Register
3950 operand flagsReg() %{
3951 constraint(ALLOC_IN_RC(int_flags));
3952 match(RegFlags);
3954 format %{ "ccr" %} // both ICC and XCC
3955 interface(REG_INTER);
3956 %}
3958 // Condition Code Register, unsigned comparisons.
3959 operand flagsRegU() %{
3960 constraint(ALLOC_IN_RC(int_flags));
3961 match(RegFlags);
3963 format %{ "icc_U" %}
3964 interface(REG_INTER);
3965 %}
3967 // Condition Code Register, pointer comparisons.
3968 operand flagsRegP() %{
3969 constraint(ALLOC_IN_RC(int_flags));
3970 match(RegFlags);
3972 #ifdef _LP64
3973 format %{ "xcc_P" %}
3974 #else
3975 format %{ "icc_P" %}
3976 #endif
3977 interface(REG_INTER);
3978 %}
3980 // Condition Code Register, long comparisons.
3981 operand flagsRegL() %{
3982 constraint(ALLOC_IN_RC(int_flags));
3983 match(RegFlags);
3985 format %{ "xcc_L" %}
3986 interface(REG_INTER);
3987 %}
3989 // Condition Code Register, floating comparisons, unordered same as "less".
3990 operand flagsRegF() %{
3991 constraint(ALLOC_IN_RC(float_flags));
3992 match(RegFlags);
3993 match(flagsRegF0);
3995 format %{ %}
3996 interface(REG_INTER);
3997 %}
3999 operand flagsRegF0() %{
4000 constraint(ALLOC_IN_RC(float_flag0));
4001 match(RegFlags);
4003 format %{ %}
4004 interface(REG_INTER);
4005 %}
4008 // Condition Code Flag Register used by long compare
4009 operand flagsReg_long_LTGE() %{
4010 constraint(ALLOC_IN_RC(int_flags));
4011 match(RegFlags);
4012 format %{ "icc_LTGE" %}
4013 interface(REG_INTER);
4014 %}
4015 operand flagsReg_long_EQNE() %{
4016 constraint(ALLOC_IN_RC(int_flags));
4017 match(RegFlags);
4018 format %{ "icc_EQNE" %}
4019 interface(REG_INTER);
4020 %}
4021 operand flagsReg_long_LEGT() %{
4022 constraint(ALLOC_IN_RC(int_flags));
4023 match(RegFlags);
4024 format %{ "icc_LEGT" %}
4025 interface(REG_INTER);
4026 %}
4029 operand regD() %{
4030 constraint(ALLOC_IN_RC(dflt_reg));
4031 match(RegD);
4033 match(regD_low);
4035 format %{ %}
4036 interface(REG_INTER);
4037 %}
4039 operand regF() %{
4040 constraint(ALLOC_IN_RC(sflt_reg));
4041 match(RegF);
4043 format %{ %}
4044 interface(REG_INTER);
4045 %}
4047 operand regD_low() %{
4048 constraint(ALLOC_IN_RC(dflt_low_reg));
4049 match(regD);
4051 format %{ %}
4052 interface(REG_INTER);
4053 %}
4055 // Special Registers
4057 // Method Register
4058 operand inline_cache_regP(iRegP reg) %{
4059 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4060 match(reg);
4061 format %{ %}
4062 interface(REG_INTER);
4063 %}
4065 operand interpreter_method_oop_regP(iRegP reg) %{
4066 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4067 match(reg);
4068 format %{ %}
4069 interface(REG_INTER);
4070 %}
4073 //----------Complex Operands---------------------------------------------------
4074 // Indirect Memory Reference
4075 operand indirect(sp_ptr_RegP reg) %{
4076 constraint(ALLOC_IN_RC(sp_ptr_reg));
4077 match(reg);
4079 op_cost(100);
4080 format %{ "[$reg]" %}
4081 interface(MEMORY_INTER) %{
4082 base($reg);
4083 index(0x0);
4084 scale(0x0);
4085 disp(0x0);
4086 %}
4087 %}
4089 // Indirect with simm13 Offset
4090 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4091 constraint(ALLOC_IN_RC(sp_ptr_reg));
4092 match(AddP reg offset);
4094 op_cost(100);
4095 format %{ "[$reg + $offset]" %}
4096 interface(MEMORY_INTER) %{
4097 base($reg);
4098 index(0x0);
4099 scale(0x0);
4100 disp($offset);
4101 %}
4102 %}
4104 // Indirect with simm13 Offset minus 7
4105 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4106 constraint(ALLOC_IN_RC(sp_ptr_reg));
4107 match(AddP reg offset);
4109 op_cost(100);
4110 format %{ "[$reg + $offset]" %}
4111 interface(MEMORY_INTER) %{
4112 base($reg);
4113 index(0x0);
4114 scale(0x0);
4115 disp($offset);
4116 %}
4117 %}
4119 // Note: Intel has a swapped version also, like this:
4120 //operand indOffsetX(iRegI reg, immP offset) %{
4121 // constraint(ALLOC_IN_RC(int_reg));
4122 // match(AddP offset reg);
4123 //
4124 // op_cost(100);
4125 // format %{ "[$reg + $offset]" %}
4126 // interface(MEMORY_INTER) %{
4127 // base($reg);
4128 // index(0x0);
4129 // scale(0x0);
4130 // disp($offset);
4131 // %}
4132 //%}
4133 //// However, it doesn't make sense for SPARC, since
4134 // we have no particularly good way to embed oops in
4135 // single instructions.
4137 // Indirect with Register Index
4138 operand indIndex(iRegP addr, iRegX index) %{
4139 constraint(ALLOC_IN_RC(ptr_reg));
4140 match(AddP addr index);
4142 op_cost(100);
4143 format %{ "[$addr + $index]" %}
4144 interface(MEMORY_INTER) %{
4145 base($addr);
4146 index($index);
4147 scale(0x0);
4148 disp(0x0);
4149 %}
4150 %}
4152 //----------Special Memory Operands--------------------------------------------
4153 // Stack Slot Operand - This operand is used for loading and storing temporary
4154 // values on the stack where a match requires a value to
4155 // flow through memory.
4156 operand stackSlotI(sRegI reg) %{
4157 constraint(ALLOC_IN_RC(stack_slots));
4158 op_cost(100);
4159 //match(RegI);
4160 format %{ "[$reg]" %}
4161 interface(MEMORY_INTER) %{
4162 base(0xE); // R_SP
4163 index(0x0);
4164 scale(0x0);
4165 disp($reg); // Stack Offset
4166 %}
4167 %}
4169 operand stackSlotP(sRegP reg) %{
4170 constraint(ALLOC_IN_RC(stack_slots));
4171 op_cost(100);
4172 //match(RegP);
4173 format %{ "[$reg]" %}
4174 interface(MEMORY_INTER) %{
4175 base(0xE); // R_SP
4176 index(0x0);
4177 scale(0x0);
4178 disp($reg); // Stack Offset
4179 %}
4180 %}
4182 operand stackSlotF(sRegF reg) %{
4183 constraint(ALLOC_IN_RC(stack_slots));
4184 op_cost(100);
4185 //match(RegF);
4186 format %{ "[$reg]" %}
4187 interface(MEMORY_INTER) %{
4188 base(0xE); // R_SP
4189 index(0x0);
4190 scale(0x0);
4191 disp($reg); // Stack Offset
4192 %}
4193 %}
4194 operand stackSlotD(sRegD reg) %{
4195 constraint(ALLOC_IN_RC(stack_slots));
4196 op_cost(100);
4197 //match(RegD);
4198 format %{ "[$reg]" %}
4199 interface(MEMORY_INTER) %{
4200 base(0xE); // R_SP
4201 index(0x0);
4202 scale(0x0);
4203 disp($reg); // Stack Offset
4204 %}
4205 %}
4206 operand stackSlotL(sRegL reg) %{
4207 constraint(ALLOC_IN_RC(stack_slots));
4208 op_cost(100);
4209 //match(RegL);
4210 format %{ "[$reg]" %}
4211 interface(MEMORY_INTER) %{
4212 base(0xE); // R_SP
4213 index(0x0);
4214 scale(0x0);
4215 disp($reg); // Stack Offset
4216 %}
4217 %}
4219 // Operands for expressing Control Flow
4220 // NOTE: Label is a predefined operand which should not be redefined in
4221 // the AD file. It is generically handled within the ADLC.
4223 //----------Conditional Branch Operands----------------------------------------
4224 // Comparison Op - This is the operation of the comparison, and is limited to
4225 // the following set of codes:
4226 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4227 //
4228 // Other attributes of the comparison, such as unsignedness, are specified
4229 // by the comparison instruction that sets a condition code flags register.
4230 // That result is represented by a flags operand whose subtype is appropriate
4231 // to the unsignedness (etc.) of the comparison.
4232 //
4233 // Later, the instruction which matches both the Comparison Op (a Bool) and
4234 // the flags (produced by the Cmp) specifies the coding of the comparison op
4235 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4237 operand cmpOp() %{
4238 match(Bool);
4240 format %{ "" %}
4241 interface(COND_INTER) %{
4242 equal(0x1);
4243 not_equal(0x9);
4244 less(0x3);
4245 greater_equal(0xB);
4246 less_equal(0x2);
4247 greater(0xA);
4248 %}
4249 %}
4251 // Comparison Op, unsigned
4252 operand cmpOpU() %{
4253 match(Bool);
4255 format %{ "u" %}
4256 interface(COND_INTER) %{
4257 equal(0x1);
4258 not_equal(0x9);
4259 less(0x5);
4260 greater_equal(0xD);
4261 less_equal(0x4);
4262 greater(0xC);
4263 %}
4264 %}
4266 // Comparison Op, pointer (same as unsigned)
4267 operand cmpOpP() %{
4268 match(Bool);
4270 format %{ "p" %}
4271 interface(COND_INTER) %{
4272 equal(0x1);
4273 not_equal(0x9);
4274 less(0x5);
4275 greater_equal(0xD);
4276 less_equal(0x4);
4277 greater(0xC);
4278 %}
4279 %}
4281 // Comparison Op, branch-register encoding
4282 operand cmpOp_reg() %{
4283 match(Bool);
4285 format %{ "" %}
4286 interface(COND_INTER) %{
4287 equal (0x1);
4288 not_equal (0x5);
4289 less (0x3);
4290 greater_equal(0x7);
4291 less_equal (0x2);
4292 greater (0x6);
4293 %}
4294 %}
4296 // Comparison Code, floating, unordered same as less
4297 operand cmpOpF() %{
4298 match(Bool);
4300 format %{ "fl" %}
4301 interface(COND_INTER) %{
4302 equal(0x9);
4303 not_equal(0x1);
4304 less(0x3);
4305 greater_equal(0xB);
4306 less_equal(0xE);
4307 greater(0x6);
4308 %}
4309 %}
4311 // Used by long compare
4312 operand cmpOp_commute() %{
4313 match(Bool);
4315 format %{ "" %}
4316 interface(COND_INTER) %{
4317 equal(0x1);
4318 not_equal(0x9);
4319 less(0xA);
4320 greater_equal(0x2);
4321 less_equal(0xB);
4322 greater(0x3);
4323 %}
4324 %}
4326 //----------OPERAND CLASSES----------------------------------------------------
4327 // Operand Classes are groups of operands that are used to simplify
4328 // instruction definitions by not requiring the AD writer to specify separate
4329 // instructions for every form of operand when the instruction accepts
4330 // multiple operand types with the same basic encoding and format. The classic
4331 // case of this is memory operands.
4332 opclass memory( indirect, indOffset13, indIndex );
4333 opclass indIndexMemory( indIndex );
4335 //----------PIPELINE-----------------------------------------------------------
4336 pipeline %{
4338 //----------ATTRIBUTES---------------------------------------------------------
4339 attributes %{
4340 fixed_size_instructions; // Fixed size instructions
4341 branch_has_delay_slot; // Branch has delay slot following
4342 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4343 instruction_unit_size = 4; // An instruction is 4 bytes long
4344 instruction_fetch_unit_size = 16; // The processor fetches one line
4345 instruction_fetch_units = 1; // of 16 bytes
4347 // List of nop instructions
4348 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4349 %}
4351 //----------RESOURCES----------------------------------------------------------
4352 // Resources are the functional units available to the machine
4353 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4355 //----------PIPELINE DESCRIPTION-----------------------------------------------
4356 // Pipeline Description specifies the stages in the machine's pipeline
4358 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4360 //----------PIPELINE CLASSES---------------------------------------------------
4361 // Pipeline Classes describe the stages in which input and output are
4362 // referenced by the hardware pipeline.
4364 // Integer ALU reg-reg operation
4365 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4366 single_instruction;
4367 dst : E(write);
4368 src1 : R(read);
4369 src2 : R(read);
4370 IALU : R;
4371 %}
4373 // Integer ALU reg-reg long operation
4374 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4375 instruction_count(2);
4376 dst : E(write);
4377 src1 : R(read);
4378 src2 : R(read);
4379 IALU : R;
4380 IALU : R;
4381 %}
4383 // Integer ALU reg-reg long dependent operation
4384 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4385 instruction_count(1); multiple_bundles;
4386 dst : E(write);
4387 src1 : R(read);
4388 src2 : R(read);
4389 cr : E(write);
4390 IALU : R(2);
4391 %}
4393 // Integer ALU reg-imm operaion
4394 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4395 single_instruction;
4396 dst : E(write);
4397 src1 : R(read);
4398 IALU : R;
4399 %}
4401 // Integer ALU reg-reg operation with condition code
4402 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4403 single_instruction;
4404 dst : E(write);
4405 cr : E(write);
4406 src1 : R(read);
4407 src2 : R(read);
4408 IALU : R;
4409 %}
4411 // Integer ALU reg-imm operation with condition code
4412 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4413 single_instruction;
4414 dst : E(write);
4415 cr : E(write);
4416 src1 : R(read);
4417 IALU : R;
4418 %}
4420 // Integer ALU zero-reg operation
4421 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4422 single_instruction;
4423 dst : E(write);
4424 src2 : R(read);
4425 IALU : R;
4426 %}
4428 // Integer ALU zero-reg operation with condition code only
4429 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4430 single_instruction;
4431 cr : E(write);
4432 src : R(read);
4433 IALU : R;
4434 %}
4436 // Integer ALU reg-reg operation with condition code only
4437 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4438 single_instruction;
4439 cr : E(write);
4440 src1 : R(read);
4441 src2 : R(read);
4442 IALU : R;
4443 %}
4445 // Integer ALU reg-imm operation with condition code only
4446 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4447 single_instruction;
4448 cr : E(write);
4449 src1 : R(read);
4450 IALU : R;
4451 %}
4453 // Integer ALU reg-reg-zero operation with condition code only
4454 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4455 single_instruction;
4456 cr : E(write);
4457 src1 : R(read);
4458 src2 : R(read);
4459 IALU : R;
4460 %}
4462 // Integer ALU reg-imm-zero operation with condition code only
4463 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4464 single_instruction;
4465 cr : E(write);
4466 src1 : R(read);
4467 IALU : R;
4468 %}
4470 // Integer ALU reg-reg operation with condition code, src1 modified
4471 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4472 single_instruction;
4473 cr : E(write);
4474 src1 : E(write);
4475 src1 : R(read);
4476 src2 : R(read);
4477 IALU : R;
4478 %}
4480 // Integer ALU reg-imm operation with condition code, src1 modified
4481 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4482 single_instruction;
4483 cr : E(write);
4484 src1 : E(write);
4485 src1 : R(read);
4486 IALU : R;
4487 %}
4489 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4490 multiple_bundles;
4491 dst : E(write)+4;
4492 cr : E(write);
4493 src1 : R(read);
4494 src2 : R(read);
4495 IALU : R(3);
4496 BR : R(2);
4497 %}
4499 // Integer ALU operation
4500 pipe_class ialu_none(iRegI dst) %{
4501 single_instruction;
4502 dst : E(write);
4503 IALU : R;
4504 %}
4506 // Integer ALU reg operation
4507 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4508 single_instruction; may_have_no_code;
4509 dst : E(write);
4510 src : R(read);
4511 IALU : R;
4512 %}
4514 // Integer ALU reg conditional operation
4515 // This instruction has a 1 cycle stall, and cannot execute
4516 // in the same cycle as the instruction setting the condition
4517 // code. We kludge this by pretending to read the condition code
4518 // 1 cycle earlier, and by marking the functional units as busy
4519 // for 2 cycles with the result available 1 cycle later than
4520 // is really the case.
4521 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4522 single_instruction;
4523 op2_out : C(write);
4524 op1 : R(read);
4525 cr : R(read); // This is really E, with a 1 cycle stall
4526 BR : R(2);
4527 MS : R(2);
4528 %}
4530 #ifdef _LP64
4531 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4532 instruction_count(1); multiple_bundles;
4533 dst : C(write)+1;
4534 src : R(read)+1;
4535 IALU : R(1);
4536 BR : E(2);
4537 MS : E(2);
4538 %}
4539 #endif
4541 // Integer ALU reg operation
4542 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4543 single_instruction; may_have_no_code;
4544 dst : E(write);
4545 src : R(read);
4546 IALU : R;
4547 %}
4548 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4549 single_instruction; may_have_no_code;
4550 dst : E(write);
4551 src : R(read);
4552 IALU : R;
4553 %}
4555 // Two integer ALU reg operations
4556 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4557 instruction_count(2);
4558 dst : E(write);
4559 src : R(read);
4560 A0 : R;
4561 A1 : R;
4562 %}
4564 // Two integer ALU reg operations
4565 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4566 instruction_count(2); may_have_no_code;
4567 dst : E(write);
4568 src : R(read);
4569 A0 : R;
4570 A1 : R;
4571 %}
4573 // Integer ALU imm operation
4574 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4575 single_instruction;
4576 dst : E(write);
4577 IALU : R;
4578 %}
4580 // Integer ALU reg-reg with carry operation
4581 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4582 single_instruction;
4583 dst : E(write);
4584 src1 : R(read);
4585 src2 : R(read);
4586 IALU : R;
4587 %}
4589 // Integer ALU cc operation
4590 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4591 single_instruction;
4592 dst : E(write);
4593 cc : R(read);
4594 IALU : R;
4595 %}
4597 // Integer ALU cc / second IALU operation
4598 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4599 instruction_count(1); multiple_bundles;
4600 dst : E(write)+1;
4601 src : R(read);
4602 IALU : R;
4603 %}
4605 // Integer ALU cc / second IALU operation
4606 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4607 instruction_count(1); multiple_bundles;
4608 dst : E(write)+1;
4609 p : R(read);
4610 q : R(read);
4611 IALU : R;
4612 %}
4614 // Integer ALU hi-lo-reg operation
4615 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4616 instruction_count(1); multiple_bundles;
4617 dst : E(write)+1;
4618 IALU : R(2);
4619 %}
4621 // Float ALU hi-lo-reg operation (with temp)
4622 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4623 instruction_count(1); multiple_bundles;
4624 dst : E(write)+1;
4625 IALU : R(2);
4626 %}
4628 // Long Constant
4629 pipe_class loadConL( iRegL dst, immL src ) %{
4630 instruction_count(2); multiple_bundles;
4631 dst : E(write)+1;
4632 IALU : R(2);
4633 IALU : R(2);
4634 %}
4636 // Pointer Constant
4637 pipe_class loadConP( iRegP dst, immP src ) %{
4638 instruction_count(0); multiple_bundles;
4639 fixed_latency(6);
4640 %}
4642 // Polling Address
4643 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4644 #ifdef _LP64
4645 instruction_count(0); multiple_bundles;
4646 fixed_latency(6);
4647 #else
4648 dst : E(write);
4649 IALU : R;
4650 #endif
4651 %}
4653 // Long Constant small
4654 pipe_class loadConLlo( iRegL dst, immL src ) %{
4655 instruction_count(2);
4656 dst : E(write);
4657 IALU : R;
4658 IALU : R;
4659 %}
4661 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4662 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4663 instruction_count(1); multiple_bundles;
4664 src : R(read);
4665 dst : M(write)+1;
4666 IALU : R;
4667 MS : E;
4668 %}
4670 // Integer ALU nop operation
4671 pipe_class ialu_nop() %{
4672 single_instruction;
4673 IALU : R;
4674 %}
4676 // Integer ALU nop operation
4677 pipe_class ialu_nop_A0() %{
4678 single_instruction;
4679 A0 : R;
4680 %}
4682 // Integer ALU nop operation
4683 pipe_class ialu_nop_A1() %{
4684 single_instruction;
4685 A1 : R;
4686 %}
4688 // Integer Multiply reg-reg operation
4689 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4690 single_instruction;
4691 dst : E(write);
4692 src1 : R(read);
4693 src2 : R(read);
4694 MS : R(5);
4695 %}
4697 // Integer Multiply reg-imm operation
4698 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4699 single_instruction;
4700 dst : E(write);
4701 src1 : R(read);
4702 MS : R(5);
4703 %}
4705 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4706 single_instruction;
4707 dst : E(write)+4;
4708 src1 : R(read);
4709 src2 : R(read);
4710 MS : R(6);
4711 %}
4713 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4714 single_instruction;
4715 dst : E(write)+4;
4716 src1 : R(read);
4717 MS : R(6);
4718 %}
4720 // Integer Divide reg-reg
4721 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4722 instruction_count(1); multiple_bundles;
4723 dst : E(write);
4724 temp : E(write);
4725 src1 : R(read);
4726 src2 : R(read);
4727 temp : R(read);
4728 MS : R(38);
4729 %}
4731 // Integer Divide reg-imm
4732 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4733 instruction_count(1); multiple_bundles;
4734 dst : E(write);
4735 temp : E(write);
4736 src1 : R(read);
4737 temp : R(read);
4738 MS : R(38);
4739 %}
4741 // Long Divide
4742 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4743 dst : E(write)+71;
4744 src1 : R(read);
4745 src2 : R(read)+1;
4746 MS : R(70);
4747 %}
4749 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4750 dst : E(write)+71;
4751 src1 : R(read);
4752 MS : R(70);
4753 %}
4755 // Floating Point Add Float
4756 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4757 single_instruction;
4758 dst : X(write);
4759 src1 : E(read);
4760 src2 : E(read);
4761 FA : R;
4762 %}
4764 // Floating Point Add Double
4765 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4766 single_instruction;
4767 dst : X(write);
4768 src1 : E(read);
4769 src2 : E(read);
4770 FA : R;
4771 %}
4773 // Floating Point Conditional Move based on integer flags
4774 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4775 single_instruction;
4776 dst : X(write);
4777 src : E(read);
4778 cr : R(read);
4779 FA : R(2);
4780 BR : R(2);
4781 %}
4783 // Floating Point Conditional Move based on integer flags
4784 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4785 single_instruction;
4786 dst : X(write);
4787 src : E(read);
4788 cr : R(read);
4789 FA : R(2);
4790 BR : R(2);
4791 %}
4793 // Floating Point Multiply Float
4794 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4795 single_instruction;
4796 dst : X(write);
4797 src1 : E(read);
4798 src2 : E(read);
4799 FM : R;
4800 %}
4802 // Floating Point Multiply Double
4803 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4804 single_instruction;
4805 dst : X(write);
4806 src1 : E(read);
4807 src2 : E(read);
4808 FM : R;
4809 %}
4811 // Floating Point Divide Float
4812 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4813 single_instruction;
4814 dst : X(write);
4815 src1 : E(read);
4816 src2 : E(read);
4817 FM : R;
4818 FDIV : C(14);
4819 %}
4821 // Floating Point Divide Double
4822 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4823 single_instruction;
4824 dst : X(write);
4825 src1 : E(read);
4826 src2 : E(read);
4827 FM : R;
4828 FDIV : C(17);
4829 %}
4831 // Floating Point Move/Negate/Abs Float
4832 pipe_class faddF_reg(regF dst, regF src) %{
4833 single_instruction;
4834 dst : W(write);
4835 src : E(read);
4836 FA : R(1);
4837 %}
4839 // Floating Point Move/Negate/Abs Double
4840 pipe_class faddD_reg(regD dst, regD src) %{
4841 single_instruction;
4842 dst : W(write);
4843 src : E(read);
4844 FA : R;
4845 %}
4847 // Floating Point Convert F->D
4848 pipe_class fcvtF2D(regD dst, regF src) %{
4849 single_instruction;
4850 dst : X(write);
4851 src : E(read);
4852 FA : R;
4853 %}
4855 // Floating Point Convert I->D
4856 pipe_class fcvtI2D(regD dst, regF src) %{
4857 single_instruction;
4858 dst : X(write);
4859 src : E(read);
4860 FA : R;
4861 %}
4863 // Floating Point Convert LHi->D
4864 pipe_class fcvtLHi2D(regD dst, regD src) %{
4865 single_instruction;
4866 dst : X(write);
4867 src : E(read);
4868 FA : R;
4869 %}
4871 // Floating Point Convert L->D
4872 pipe_class fcvtL2D(regD dst, regF src) %{
4873 single_instruction;
4874 dst : X(write);
4875 src : E(read);
4876 FA : R;
4877 %}
4879 // Floating Point Convert L->F
4880 pipe_class fcvtL2F(regD dst, regF src) %{
4881 single_instruction;
4882 dst : X(write);
4883 src : E(read);
4884 FA : R;
4885 %}
4887 // Floating Point Convert D->F
4888 pipe_class fcvtD2F(regD dst, regF src) %{
4889 single_instruction;
4890 dst : X(write);
4891 src : E(read);
4892 FA : R;
4893 %}
4895 // Floating Point Convert I->L
4896 pipe_class fcvtI2L(regD dst, regF src) %{
4897 single_instruction;
4898 dst : X(write);
4899 src : E(read);
4900 FA : R;
4901 %}
4903 // Floating Point Convert D->F
4904 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4905 instruction_count(1); multiple_bundles;
4906 dst : X(write)+6;
4907 src : E(read);
4908 FA : R;
4909 %}
4911 // Floating Point Convert D->L
4912 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4913 instruction_count(1); multiple_bundles;
4914 dst : X(write)+6;
4915 src : E(read);
4916 FA : R;
4917 %}
4919 // Floating Point Convert F->I
4920 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4921 instruction_count(1); multiple_bundles;
4922 dst : X(write)+6;
4923 src : E(read);
4924 FA : R;
4925 %}
4927 // Floating Point Convert F->L
4928 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4929 instruction_count(1); multiple_bundles;
4930 dst : X(write)+6;
4931 src : E(read);
4932 FA : R;
4933 %}
4935 // Floating Point Convert I->F
4936 pipe_class fcvtI2F(regF dst, regF src) %{
4937 single_instruction;
4938 dst : X(write);
4939 src : E(read);
4940 FA : R;
4941 %}
4943 // Floating Point Compare
4944 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4945 single_instruction;
4946 cr : X(write);
4947 src1 : E(read);
4948 src2 : E(read);
4949 FA : R;
4950 %}
4952 // Floating Point Compare
4953 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4954 single_instruction;
4955 cr : X(write);
4956 src1 : E(read);
4957 src2 : E(read);
4958 FA : R;
4959 %}
4961 // Floating Add Nop
4962 pipe_class fadd_nop() %{
4963 single_instruction;
4964 FA : R;
4965 %}
4967 // Integer Store to Memory
4968 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4969 single_instruction;
4970 mem : R(read);
4971 src : C(read);
4972 MS : R;
4973 %}
4975 // Integer Store to Memory
4976 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4977 single_instruction;
4978 mem : R(read);
4979 src : C(read);
4980 MS : R;
4981 %}
4983 // Integer Store Zero to Memory
4984 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4985 single_instruction;
4986 mem : R(read);
4987 MS : R;
4988 %}
4990 // Special Stack Slot Store
4991 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4992 single_instruction;
4993 stkSlot : R(read);
4994 src : C(read);
4995 MS : R;
4996 %}
4998 // Special Stack Slot Store
4999 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5000 instruction_count(2); multiple_bundles;
5001 stkSlot : R(read);
5002 src : C(read);
5003 MS : R(2);
5004 %}
5006 // Float Store
5007 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5008 single_instruction;
5009 mem : R(read);
5010 src : C(read);
5011 MS : R;
5012 %}
5014 // Float Store
5015 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5016 single_instruction;
5017 mem : R(read);
5018 MS : R;
5019 %}
5021 // Double Store
5022 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5023 instruction_count(1);
5024 mem : R(read);
5025 src : C(read);
5026 MS : R;
5027 %}
5029 // Double Store
5030 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5031 single_instruction;
5032 mem : R(read);
5033 MS : R;
5034 %}
5036 // Special Stack Slot Float Store
5037 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5038 single_instruction;
5039 stkSlot : R(read);
5040 src : C(read);
5041 MS : R;
5042 %}
5044 // Special Stack Slot Double Store
5045 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5046 single_instruction;
5047 stkSlot : R(read);
5048 src : C(read);
5049 MS : R;
5050 %}
5052 // Integer Load (when sign bit propagation not needed)
5053 pipe_class iload_mem(iRegI dst, memory mem) %{
5054 single_instruction;
5055 mem : R(read);
5056 dst : C(write);
5057 MS : R;
5058 %}
5060 // Integer Load from stack operand
5061 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5062 single_instruction;
5063 mem : R(read);
5064 dst : C(write);
5065 MS : R;
5066 %}
5068 // Integer Load (when sign bit propagation or masking is needed)
5069 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5070 single_instruction;
5071 mem : R(read);
5072 dst : M(write);
5073 MS : R;
5074 %}
5076 // Float Load
5077 pipe_class floadF_mem(regF dst, memory mem) %{
5078 single_instruction;
5079 mem : R(read);
5080 dst : M(write);
5081 MS : R;
5082 %}
5084 // Float Load
5085 pipe_class floadD_mem(regD dst, memory mem) %{
5086 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5087 mem : R(read);
5088 dst : M(write);
5089 MS : R;
5090 %}
5092 // Float Load
5093 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5094 single_instruction;
5095 stkSlot : R(read);
5096 dst : M(write);
5097 MS : R;
5098 %}
5100 // Float Load
5101 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5102 single_instruction;
5103 stkSlot : R(read);
5104 dst : M(write);
5105 MS : R;
5106 %}
5108 // Memory Nop
5109 pipe_class mem_nop() %{
5110 single_instruction;
5111 MS : R;
5112 %}
5114 pipe_class sethi(iRegP dst, immI src) %{
5115 single_instruction;
5116 dst : E(write);
5117 IALU : R;
5118 %}
5120 pipe_class loadPollP(iRegP poll) %{
5121 single_instruction;
5122 poll : R(read);
5123 MS : R;
5124 %}
5126 pipe_class br(Universe br, label labl) %{
5127 single_instruction_with_delay_slot;
5128 BR : R;
5129 %}
5131 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5132 single_instruction_with_delay_slot;
5133 cr : E(read);
5134 BR : R;
5135 %}
5137 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5138 single_instruction_with_delay_slot;
5139 op1 : E(read);
5140 BR : R;
5141 MS : R;
5142 %}
5144 // Compare and branch
5145 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5146 instruction_count(2); has_delay_slot;
5147 cr : E(write);
5148 src1 : R(read);
5149 src2 : R(read);
5150 IALU : R;
5151 BR : R;
5152 %}
5154 // Compare and branch
5155 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5156 instruction_count(2); has_delay_slot;
5157 cr : E(write);
5158 src1 : R(read);
5159 IALU : R;
5160 BR : R;
5161 %}
5163 // Compare and branch using cbcond
5164 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5165 single_instruction;
5166 src1 : E(read);
5167 src2 : E(read);
5168 IALU : R;
5169 BR : R;
5170 %}
5172 // Compare and branch using cbcond
5173 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5174 single_instruction;
5175 src1 : E(read);
5176 IALU : R;
5177 BR : R;
5178 %}
5180 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5181 single_instruction_with_delay_slot;
5182 cr : E(read);
5183 BR : R;
5184 %}
5186 pipe_class br_nop() %{
5187 single_instruction;
5188 BR : R;
5189 %}
5191 pipe_class simple_call(method meth) %{
5192 instruction_count(2); multiple_bundles; force_serialization;
5193 fixed_latency(100);
5194 BR : R(1);
5195 MS : R(1);
5196 A0 : R(1);
5197 %}
5199 pipe_class compiled_call(method meth) %{
5200 instruction_count(1); multiple_bundles; force_serialization;
5201 fixed_latency(100);
5202 MS : R(1);
5203 %}
5205 pipe_class call(method meth) %{
5206 instruction_count(0); multiple_bundles; force_serialization;
5207 fixed_latency(100);
5208 %}
5210 pipe_class tail_call(Universe ignore, label labl) %{
5211 single_instruction; has_delay_slot;
5212 fixed_latency(100);
5213 BR : R(1);
5214 MS : R(1);
5215 %}
5217 pipe_class ret(Universe ignore) %{
5218 single_instruction; has_delay_slot;
5219 BR : R(1);
5220 MS : R(1);
5221 %}
5223 pipe_class ret_poll(g3RegP poll) %{
5224 instruction_count(3); has_delay_slot;
5225 poll : E(read);
5226 MS : R;
5227 %}
5229 // The real do-nothing guy
5230 pipe_class empty( ) %{
5231 instruction_count(0);
5232 %}
5234 pipe_class long_memory_op() %{
5235 instruction_count(0); multiple_bundles; force_serialization;
5236 fixed_latency(25);
5237 MS : R(1);
5238 %}
5240 // Check-cast
5241 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5242 array : R(read);
5243 match : R(read);
5244 IALU : R(2);
5245 BR : R(2);
5246 MS : R;
5247 %}
5249 // Convert FPU flags into +1,0,-1
5250 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5251 src1 : E(read);
5252 src2 : E(read);
5253 dst : E(write);
5254 FA : R;
5255 MS : R(2);
5256 BR : R(2);
5257 %}
5259 // Compare for p < q, and conditionally add y
5260 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5261 p : E(read);
5262 q : E(read);
5263 y : E(read);
5264 IALU : R(3)
5265 %}
5267 // Perform a compare, then move conditionally in a branch delay slot.
5268 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5269 src2 : E(read);
5270 srcdst : E(read);
5271 IALU : R;
5272 BR : R;
5273 %}
5275 // Define the class for the Nop node
5276 define %{
5277 MachNop = ialu_nop;
5278 %}
5280 %}
5282 //----------INSTRUCTIONS-------------------------------------------------------
5284 //------------Special Stack Slot instructions - no match rules-----------------
5285 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5286 // No match rule to avoid chain rule match.
5287 effect(DEF dst, USE src);
5288 ins_cost(MEMORY_REF_COST);
5289 size(4);
5290 format %{ "LDF $src,$dst\t! stkI to regF" %}
5291 opcode(Assembler::ldf_op3);
5292 ins_encode(simple_form3_mem_reg(src, dst));
5293 ins_pipe(floadF_stk);
5294 %}
5296 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5297 // No match rule to avoid chain rule match.
5298 effect(DEF dst, USE src);
5299 ins_cost(MEMORY_REF_COST);
5300 size(4);
5301 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5302 opcode(Assembler::lddf_op3);
5303 ins_encode(simple_form3_mem_reg(src, dst));
5304 ins_pipe(floadD_stk);
5305 %}
5307 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5308 // No match rule to avoid chain rule match.
5309 effect(DEF dst, USE src);
5310 ins_cost(MEMORY_REF_COST);
5311 size(4);
5312 format %{ "STF $src,$dst\t! regF to stkI" %}
5313 opcode(Assembler::stf_op3);
5314 ins_encode(simple_form3_mem_reg(dst, src));
5315 ins_pipe(fstoreF_stk_reg);
5316 %}
5318 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5319 // No match rule to avoid chain rule match.
5320 effect(DEF dst, USE src);
5321 ins_cost(MEMORY_REF_COST);
5322 size(4);
5323 format %{ "STDF $src,$dst\t! regD to stkL" %}
5324 opcode(Assembler::stdf_op3);
5325 ins_encode(simple_form3_mem_reg(dst, src));
5326 ins_pipe(fstoreD_stk_reg);
5327 %}
5329 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5330 effect(DEF dst, USE src);
5331 ins_cost(MEMORY_REF_COST*2);
5332 size(8);
5333 format %{ "STW $src,$dst.hi\t! long\n\t"
5334 "STW R_G0,$dst.lo" %}
5335 opcode(Assembler::stw_op3);
5336 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5337 ins_pipe(lstoreI_stk_reg);
5338 %}
5340 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5341 // No match rule to avoid chain rule match.
5342 effect(DEF dst, USE src);
5343 ins_cost(MEMORY_REF_COST);
5344 size(4);
5345 format %{ "STX $src,$dst\t! regL to stkD" %}
5346 opcode(Assembler::stx_op3);
5347 ins_encode(simple_form3_mem_reg( dst, src ) );
5348 ins_pipe(istore_stk_reg);
5349 %}
5351 //---------- Chain stack slots between similar types --------
5353 // Load integer from stack slot
5354 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5355 match(Set dst src);
5356 ins_cost(MEMORY_REF_COST);
5358 size(4);
5359 format %{ "LDUW $src,$dst\t!stk" %}
5360 opcode(Assembler::lduw_op3);
5361 ins_encode(simple_form3_mem_reg( src, dst ) );
5362 ins_pipe(iload_mem);
5363 %}
5365 // Store integer to stack slot
5366 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5367 match(Set dst src);
5368 ins_cost(MEMORY_REF_COST);
5370 size(4);
5371 format %{ "STW $src,$dst\t!stk" %}
5372 opcode(Assembler::stw_op3);
5373 ins_encode(simple_form3_mem_reg( dst, src ) );
5374 ins_pipe(istore_mem_reg);
5375 %}
5377 // Load long from stack slot
5378 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5379 match(Set dst src);
5381 ins_cost(MEMORY_REF_COST);
5382 size(4);
5383 format %{ "LDX $src,$dst\t! long" %}
5384 opcode(Assembler::ldx_op3);
5385 ins_encode(simple_form3_mem_reg( src, dst ) );
5386 ins_pipe(iload_mem);
5387 %}
5389 // Store long to stack slot
5390 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5391 match(Set dst src);
5393 ins_cost(MEMORY_REF_COST);
5394 size(4);
5395 format %{ "STX $src,$dst\t! long" %}
5396 opcode(Assembler::stx_op3);
5397 ins_encode(simple_form3_mem_reg( dst, src ) );
5398 ins_pipe(istore_mem_reg);
5399 %}
5401 #ifdef _LP64
5402 // Load pointer from stack slot, 64-bit encoding
5403 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5404 match(Set dst src);
5405 ins_cost(MEMORY_REF_COST);
5406 size(4);
5407 format %{ "LDX $src,$dst\t!ptr" %}
5408 opcode(Assembler::ldx_op3);
5409 ins_encode(simple_form3_mem_reg( src, dst ) );
5410 ins_pipe(iload_mem);
5411 %}
5413 // Store pointer to stack slot
5414 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5415 match(Set dst src);
5416 ins_cost(MEMORY_REF_COST);
5417 size(4);
5418 format %{ "STX $src,$dst\t!ptr" %}
5419 opcode(Assembler::stx_op3);
5420 ins_encode(simple_form3_mem_reg( dst, src ) );
5421 ins_pipe(istore_mem_reg);
5422 %}
5423 #else // _LP64
5424 // Load pointer from stack slot, 32-bit encoding
5425 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5426 match(Set dst src);
5427 ins_cost(MEMORY_REF_COST);
5428 format %{ "LDUW $src,$dst\t!ptr" %}
5429 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5430 ins_encode(simple_form3_mem_reg( src, dst ) );
5431 ins_pipe(iload_mem);
5432 %}
5434 // Store pointer to stack slot
5435 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5436 match(Set dst src);
5437 ins_cost(MEMORY_REF_COST);
5438 format %{ "STW $src,$dst\t!ptr" %}
5439 opcode(Assembler::stw_op3, Assembler::ldst_op);
5440 ins_encode(simple_form3_mem_reg( dst, src ) );
5441 ins_pipe(istore_mem_reg);
5442 %}
5443 #endif // _LP64
5445 //------------Special Nop instructions for bundling - no match rules-----------
5446 // Nop using the A0 functional unit
5447 instruct Nop_A0() %{
5448 ins_cost(0);
5450 format %{ "NOP ! Alu Pipeline" %}
5451 opcode(Assembler::or_op3, Assembler::arith_op);
5452 ins_encode( form2_nop() );
5453 ins_pipe(ialu_nop_A0);
5454 %}
5456 // Nop using the A1 functional unit
5457 instruct Nop_A1( ) %{
5458 ins_cost(0);
5460 format %{ "NOP ! Alu Pipeline" %}
5461 opcode(Assembler::or_op3, Assembler::arith_op);
5462 ins_encode( form2_nop() );
5463 ins_pipe(ialu_nop_A1);
5464 %}
5466 // Nop using the memory functional unit
5467 instruct Nop_MS( ) %{
5468 ins_cost(0);
5470 format %{ "NOP ! Memory Pipeline" %}
5471 ins_encode( emit_mem_nop );
5472 ins_pipe(mem_nop);
5473 %}
5475 // Nop using the floating add functional unit
5476 instruct Nop_FA( ) %{
5477 ins_cost(0);
5479 format %{ "NOP ! Floating Add Pipeline" %}
5480 ins_encode( emit_fadd_nop );
5481 ins_pipe(fadd_nop);
5482 %}
5484 // Nop using the branch functional unit
5485 instruct Nop_BR( ) %{
5486 ins_cost(0);
5488 format %{ "NOP ! Branch Pipeline" %}
5489 ins_encode( emit_br_nop );
5490 ins_pipe(br_nop);
5491 %}
5493 //----------Load/Store/Move Instructions---------------------------------------
5494 //----------Load Instructions--------------------------------------------------
5495 // Load Byte (8bit signed)
5496 instruct loadB(iRegI dst, memory mem) %{
5497 match(Set dst (LoadB mem));
5498 ins_cost(MEMORY_REF_COST);
5500 size(4);
5501 format %{ "LDSB $mem,$dst\t! byte" %}
5502 ins_encode %{
5503 __ ldsb($mem$$Address, $dst$$Register);
5504 %}
5505 ins_pipe(iload_mask_mem);
5506 %}
5508 // Load Byte (8bit signed) into a Long Register
5509 instruct loadB2L(iRegL dst, memory mem) %{
5510 match(Set dst (ConvI2L (LoadB mem)));
5511 ins_cost(MEMORY_REF_COST);
5513 size(4);
5514 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5515 ins_encode %{
5516 __ ldsb($mem$$Address, $dst$$Register);
5517 %}
5518 ins_pipe(iload_mask_mem);
5519 %}
5521 // Load Unsigned Byte (8bit UNsigned) into an int reg
5522 instruct loadUB(iRegI dst, memory mem) %{
5523 match(Set dst (LoadUB mem));
5524 ins_cost(MEMORY_REF_COST);
5526 size(4);
5527 format %{ "LDUB $mem,$dst\t! ubyte" %}
5528 ins_encode %{
5529 __ ldub($mem$$Address, $dst$$Register);
5530 %}
5531 ins_pipe(iload_mem);
5532 %}
5534 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5535 instruct loadUB2L(iRegL dst, memory mem) %{
5536 match(Set dst (ConvI2L (LoadUB mem)));
5537 ins_cost(MEMORY_REF_COST);
5539 size(4);
5540 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5541 ins_encode %{
5542 __ ldub($mem$$Address, $dst$$Register);
5543 %}
5544 ins_pipe(iload_mem);
5545 %}
5547 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5548 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5549 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5550 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5552 size(2*4);
5553 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5554 "AND $dst,$mask,$dst" %}
5555 ins_encode %{
5556 __ ldub($mem$$Address, $dst$$Register);
5557 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5558 %}
5559 ins_pipe(iload_mem);
5560 %}
5562 // Load Short (16bit signed)
5563 instruct loadS(iRegI dst, memory mem) %{
5564 match(Set dst (LoadS mem));
5565 ins_cost(MEMORY_REF_COST);
5567 size(4);
5568 format %{ "LDSH $mem,$dst\t! short" %}
5569 ins_encode %{
5570 __ ldsh($mem$$Address, $dst$$Register);
5571 %}
5572 ins_pipe(iload_mask_mem);
5573 %}
5575 // Load Short (16 bit signed) to Byte (8 bit signed)
5576 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5577 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5578 ins_cost(MEMORY_REF_COST);
5580 size(4);
5582 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5583 ins_encode %{
5584 __ ldsb($mem$$Address, $dst$$Register, 1);
5585 %}
5586 ins_pipe(iload_mask_mem);
5587 %}
5589 // Load Short (16bit signed) into a Long Register
5590 instruct loadS2L(iRegL dst, memory mem) %{
5591 match(Set dst (ConvI2L (LoadS mem)));
5592 ins_cost(MEMORY_REF_COST);
5594 size(4);
5595 format %{ "LDSH $mem,$dst\t! short -> long" %}
5596 ins_encode %{
5597 __ ldsh($mem$$Address, $dst$$Register);
5598 %}
5599 ins_pipe(iload_mask_mem);
5600 %}
5602 // Load Unsigned Short/Char (16bit UNsigned)
5603 instruct loadUS(iRegI dst, memory mem) %{
5604 match(Set dst (LoadUS mem));
5605 ins_cost(MEMORY_REF_COST);
5607 size(4);
5608 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5609 ins_encode %{
5610 __ lduh($mem$$Address, $dst$$Register);
5611 %}
5612 ins_pipe(iload_mem);
5613 %}
5615 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5616 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5617 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5618 ins_cost(MEMORY_REF_COST);
5620 size(4);
5621 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5622 ins_encode %{
5623 __ ldsb($mem$$Address, $dst$$Register, 1);
5624 %}
5625 ins_pipe(iload_mask_mem);
5626 %}
5628 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5629 instruct loadUS2L(iRegL dst, memory mem) %{
5630 match(Set dst (ConvI2L (LoadUS mem)));
5631 ins_cost(MEMORY_REF_COST);
5633 size(4);
5634 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5635 ins_encode %{
5636 __ lduh($mem$$Address, $dst$$Register);
5637 %}
5638 ins_pipe(iload_mem);
5639 %}
5641 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5642 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5643 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5644 ins_cost(MEMORY_REF_COST);
5646 size(4);
5647 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5648 ins_encode %{
5649 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5650 %}
5651 ins_pipe(iload_mem);
5652 %}
5654 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5655 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5656 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5657 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5659 size(2*4);
5660 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5661 "AND $dst,$mask,$dst" %}
5662 ins_encode %{
5663 Register Rdst = $dst$$Register;
5664 __ lduh($mem$$Address, Rdst);
5665 __ and3(Rdst, $mask$$constant, Rdst);
5666 %}
5667 ins_pipe(iload_mem);
5668 %}
5670 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5671 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5672 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5673 effect(TEMP dst, TEMP tmp);
5674 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5676 size((3+1)*4); // set may use two instructions.
5677 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5678 "SET $mask,$tmp\n\t"
5679 "AND $dst,$tmp,$dst" %}
5680 ins_encode %{
5681 Register Rdst = $dst$$Register;
5682 Register Rtmp = $tmp$$Register;
5683 __ lduh($mem$$Address, Rdst);
5684 __ set($mask$$constant, Rtmp);
5685 __ and3(Rdst, Rtmp, Rdst);
5686 %}
5687 ins_pipe(iload_mem);
5688 %}
5690 // Load Integer
5691 instruct loadI(iRegI dst, memory mem) %{
5692 match(Set dst (LoadI mem));
5693 ins_cost(MEMORY_REF_COST);
5695 size(4);
5696 format %{ "LDUW $mem,$dst\t! int" %}
5697 ins_encode %{
5698 __ lduw($mem$$Address, $dst$$Register);
5699 %}
5700 ins_pipe(iload_mem);
5701 %}
5703 // Load Integer to Byte (8 bit signed)
5704 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5705 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5706 ins_cost(MEMORY_REF_COST);
5708 size(4);
5710 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5711 ins_encode %{
5712 __ ldsb($mem$$Address, $dst$$Register, 3);
5713 %}
5714 ins_pipe(iload_mask_mem);
5715 %}
5717 // Load Integer to Unsigned Byte (8 bit UNsigned)
5718 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5719 match(Set dst (AndI (LoadI mem) mask));
5720 ins_cost(MEMORY_REF_COST);
5722 size(4);
5724 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5725 ins_encode %{
5726 __ ldub($mem$$Address, $dst$$Register, 3);
5727 %}
5728 ins_pipe(iload_mask_mem);
5729 %}
5731 // Load Integer to Short (16 bit signed)
5732 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5733 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5734 ins_cost(MEMORY_REF_COST);
5736 size(4);
5738 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5739 ins_encode %{
5740 __ ldsh($mem$$Address, $dst$$Register, 2);
5741 %}
5742 ins_pipe(iload_mask_mem);
5743 %}
5745 // Load Integer to Unsigned Short (16 bit UNsigned)
5746 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5747 match(Set dst (AndI (LoadI mem) mask));
5748 ins_cost(MEMORY_REF_COST);
5750 size(4);
5752 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5753 ins_encode %{
5754 __ lduh($mem$$Address, $dst$$Register, 2);
5755 %}
5756 ins_pipe(iload_mask_mem);
5757 %}
5759 // Load Integer into a Long Register
5760 instruct loadI2L(iRegL dst, memory mem) %{
5761 match(Set dst (ConvI2L (LoadI mem)));
5762 ins_cost(MEMORY_REF_COST);
5764 size(4);
5765 format %{ "LDSW $mem,$dst\t! int -> long" %}
5766 ins_encode %{
5767 __ ldsw($mem$$Address, $dst$$Register);
5768 %}
5769 ins_pipe(iload_mask_mem);
5770 %}
5772 // Load Integer with mask 0xFF into a Long Register
5773 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5774 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5775 ins_cost(MEMORY_REF_COST);
5777 size(4);
5778 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5779 ins_encode %{
5780 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5781 %}
5782 ins_pipe(iload_mem);
5783 %}
5785 // Load Integer with mask 0xFFFF into a Long Register
5786 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5787 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5788 ins_cost(MEMORY_REF_COST);
5790 size(4);
5791 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5792 ins_encode %{
5793 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5794 %}
5795 ins_pipe(iload_mem);
5796 %}
5798 // Load Integer with a 13-bit mask into a Long Register
5799 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5800 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5801 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5803 size(2*4);
5804 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5805 "AND $dst,$mask,$dst" %}
5806 ins_encode %{
5807 Register Rdst = $dst$$Register;
5808 __ lduw($mem$$Address, Rdst);
5809 __ and3(Rdst, $mask$$constant, Rdst);
5810 %}
5811 ins_pipe(iload_mem);
5812 %}
5814 // Load Integer with a 32-bit mask into a Long Register
5815 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5816 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5817 effect(TEMP dst, TEMP tmp);
5818 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5820 size((3+1)*4); // set may use two instructions.
5821 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5822 "SET $mask,$tmp\n\t"
5823 "AND $dst,$tmp,$dst" %}
5824 ins_encode %{
5825 Register Rdst = $dst$$Register;
5826 Register Rtmp = $tmp$$Register;
5827 __ lduw($mem$$Address, Rdst);
5828 __ set($mask$$constant, Rtmp);
5829 __ and3(Rdst, Rtmp, Rdst);
5830 %}
5831 ins_pipe(iload_mem);
5832 %}
5834 // Load Unsigned Integer into a Long Register
5835 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5836 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5837 ins_cost(MEMORY_REF_COST);
5839 size(4);
5840 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5841 ins_encode %{
5842 __ lduw($mem$$Address, $dst$$Register);
5843 %}
5844 ins_pipe(iload_mem);
5845 %}
5847 // Load Long - aligned
5848 instruct loadL(iRegL dst, memory mem ) %{
5849 match(Set dst (LoadL mem));
5850 ins_cost(MEMORY_REF_COST);
5852 size(4);
5853 format %{ "LDX $mem,$dst\t! long" %}
5854 ins_encode %{
5855 __ ldx($mem$$Address, $dst$$Register);
5856 %}
5857 ins_pipe(iload_mem);
5858 %}
5860 // Load Long - UNaligned
5861 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5862 match(Set dst (LoadL_unaligned mem));
5863 effect(KILL tmp);
5864 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5865 size(16);
5866 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5867 "\tLDUW $mem ,$dst\n"
5868 "\tSLLX #32, $dst, $dst\n"
5869 "\tOR $dst, R_O7, $dst" %}
5870 opcode(Assembler::lduw_op3);
5871 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5872 ins_pipe(iload_mem);
5873 %}
5875 // Load Range
5876 instruct loadRange(iRegI dst, memory mem) %{
5877 match(Set dst (LoadRange mem));
5878 ins_cost(MEMORY_REF_COST);
5880 size(4);
5881 format %{ "LDUW $mem,$dst\t! range" %}
5882 opcode(Assembler::lduw_op3);
5883 ins_encode(simple_form3_mem_reg( mem, dst ) );
5884 ins_pipe(iload_mem);
5885 %}
5887 // Load Integer into %f register (for fitos/fitod)
5888 instruct loadI_freg(regF dst, memory mem) %{
5889 match(Set dst (LoadI mem));
5890 ins_cost(MEMORY_REF_COST);
5891 size(4);
5893 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5894 opcode(Assembler::ldf_op3);
5895 ins_encode(simple_form3_mem_reg( mem, dst ) );
5896 ins_pipe(floadF_mem);
5897 %}
5899 // Load Pointer
5900 instruct loadP(iRegP dst, memory mem) %{
5901 match(Set dst (LoadP mem));
5902 ins_cost(MEMORY_REF_COST);
5903 size(4);
5905 #ifndef _LP64
5906 format %{ "LDUW $mem,$dst\t! ptr" %}
5907 ins_encode %{
5908 __ lduw($mem$$Address, $dst$$Register);
5909 %}
5910 #else
5911 format %{ "LDX $mem,$dst\t! ptr" %}
5912 ins_encode %{
5913 __ ldx($mem$$Address, $dst$$Register);
5914 %}
5915 #endif
5916 ins_pipe(iload_mem);
5917 %}
5919 // Load Compressed Pointer
5920 instruct loadN(iRegN dst, memory mem) %{
5921 match(Set dst (LoadN mem));
5922 ins_cost(MEMORY_REF_COST);
5923 size(4);
5925 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5926 ins_encode %{
5927 __ lduw($mem$$Address, $dst$$Register);
5928 %}
5929 ins_pipe(iload_mem);
5930 %}
5932 // Load Klass Pointer
5933 instruct loadKlass(iRegP dst, memory mem) %{
5934 match(Set dst (LoadKlass mem));
5935 ins_cost(MEMORY_REF_COST);
5936 size(4);
5938 #ifndef _LP64
5939 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5940 ins_encode %{
5941 __ lduw($mem$$Address, $dst$$Register);
5942 %}
5943 #else
5944 format %{ "LDX $mem,$dst\t! klass ptr" %}
5945 ins_encode %{
5946 __ ldx($mem$$Address, $dst$$Register);
5947 %}
5948 #endif
5949 ins_pipe(iload_mem);
5950 %}
5952 // Load narrow Klass Pointer
5953 instruct loadNKlass(iRegN dst, memory mem) %{
5954 match(Set dst (LoadNKlass mem));
5955 ins_cost(MEMORY_REF_COST);
5956 size(4);
5958 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5959 ins_encode %{
5960 __ lduw($mem$$Address, $dst$$Register);
5961 %}
5962 ins_pipe(iload_mem);
5963 %}
5965 // Load Double
5966 instruct loadD(regD dst, memory mem) %{
5967 match(Set dst (LoadD mem));
5968 ins_cost(MEMORY_REF_COST);
5970 size(4);
5971 format %{ "LDDF $mem,$dst" %}
5972 opcode(Assembler::lddf_op3);
5973 ins_encode(simple_form3_mem_reg( mem, dst ) );
5974 ins_pipe(floadD_mem);
5975 %}
5977 // Load Double - UNaligned
5978 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5979 match(Set dst (LoadD_unaligned mem));
5980 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5981 size(8);
5982 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5983 "\tLDF $mem+4,$dst.lo\t!" %}
5984 opcode(Assembler::ldf_op3);
5985 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5986 ins_pipe(iload_mem);
5987 %}
5989 // Load Float
5990 instruct loadF(regF dst, memory mem) %{
5991 match(Set dst (LoadF mem));
5992 ins_cost(MEMORY_REF_COST);
5994 size(4);
5995 format %{ "LDF $mem,$dst" %}
5996 opcode(Assembler::ldf_op3);
5997 ins_encode(simple_form3_mem_reg( mem, dst ) );
5998 ins_pipe(floadF_mem);
5999 %}
6001 // Load Constant
6002 instruct loadConI( iRegI dst, immI src ) %{
6003 match(Set dst src);
6004 ins_cost(DEFAULT_COST * 3/2);
6005 format %{ "SET $src,$dst" %}
6006 ins_encode( Set32(src, dst) );
6007 ins_pipe(ialu_hi_lo_reg);
6008 %}
6010 instruct loadConI13( iRegI dst, immI13 src ) %{
6011 match(Set dst src);
6013 size(4);
6014 format %{ "MOV $src,$dst" %}
6015 ins_encode( Set13( src, dst ) );
6016 ins_pipe(ialu_imm);
6017 %}
6019 #ifndef _LP64
6020 instruct loadConP(iRegP dst, immP con) %{
6021 match(Set dst con);
6022 ins_cost(DEFAULT_COST * 3/2);
6023 format %{ "SET $con,$dst\t!ptr" %}
6024 ins_encode %{
6025 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6026 intptr_t val = $con$$constant;
6027 if (constant_reloc == relocInfo::oop_type) {
6028 __ set_oop_constant((jobject) val, $dst$$Register);
6029 } else if (constant_reloc == relocInfo::metadata_type) {
6030 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6031 } else { // non-oop pointers, e.g. card mark base, heap top
6032 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6033 __ set(val, $dst$$Register);
6034 }
6035 %}
6036 ins_pipe(loadConP);
6037 %}
6038 #else
6039 instruct loadConP_set(iRegP dst, immP_set con) %{
6040 match(Set dst con);
6041 ins_cost(DEFAULT_COST * 3/2);
6042 format %{ "SET $con,$dst\t! ptr" %}
6043 ins_encode %{
6044 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6045 intptr_t val = $con$$constant;
6046 if (constant_reloc == relocInfo::oop_type) {
6047 __ set_oop_constant((jobject) val, $dst$$Register);
6048 } else if (constant_reloc == relocInfo::metadata_type) {
6049 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6050 } else { // non-oop pointers, e.g. card mark base, heap top
6051 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6052 __ set(val, $dst$$Register);
6053 }
6054 %}
6055 ins_pipe(loadConP);
6056 %}
6058 instruct loadConP_load(iRegP dst, immP_load con) %{
6059 match(Set dst con);
6060 ins_cost(MEMORY_REF_COST);
6061 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6062 ins_encode %{
6063 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6064 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6065 %}
6066 ins_pipe(loadConP);
6067 %}
6069 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6070 match(Set dst con);
6071 ins_cost(DEFAULT_COST * 3/2);
6072 format %{ "SET $con,$dst\t! non-oop ptr" %}
6073 ins_encode %{
6074 __ set($con$$constant, $dst$$Register);
6075 %}
6076 ins_pipe(loadConP);
6077 %}
6078 #endif // _LP64
6080 instruct loadConP0(iRegP dst, immP0 src) %{
6081 match(Set dst src);
6083 size(4);
6084 format %{ "CLR $dst\t!ptr" %}
6085 ins_encode %{
6086 __ clr($dst$$Register);
6087 %}
6088 ins_pipe(ialu_imm);
6089 %}
6091 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6092 match(Set dst src);
6093 ins_cost(DEFAULT_COST);
6094 format %{ "SET $src,$dst\t!ptr" %}
6095 ins_encode %{
6096 AddressLiteral polling_page(os::get_polling_page());
6097 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6098 %}
6099 ins_pipe(loadConP_poll);
6100 %}
6102 instruct loadConN0(iRegN dst, immN0 src) %{
6103 match(Set dst src);
6105 size(4);
6106 format %{ "CLR $dst\t! compressed NULL ptr" %}
6107 ins_encode %{
6108 __ clr($dst$$Register);
6109 %}
6110 ins_pipe(ialu_imm);
6111 %}
6113 instruct loadConN(iRegN dst, immN src) %{
6114 match(Set dst src);
6115 ins_cost(DEFAULT_COST * 3/2);
6116 format %{ "SET $src,$dst\t! compressed ptr" %}
6117 ins_encode %{
6118 Register dst = $dst$$Register;
6119 __ set_narrow_oop((jobject)$src$$constant, dst);
6120 %}
6121 ins_pipe(ialu_hi_lo_reg);
6122 %}
6124 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6125 match(Set dst src);
6126 ins_cost(DEFAULT_COST * 3/2);
6127 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6128 ins_encode %{
6129 Register dst = $dst$$Register;
6130 __ set_narrow_klass((Klass*)$src$$constant, dst);
6131 %}
6132 ins_pipe(ialu_hi_lo_reg);
6133 %}
6135 // Materialize long value (predicated by immL_cheap).
6136 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6137 match(Set dst con);
6138 effect(KILL tmp);
6139 ins_cost(DEFAULT_COST * 3);
6140 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6141 ins_encode %{
6142 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6143 %}
6144 ins_pipe(loadConL);
6145 %}
6147 // Load long value from constant table (predicated by immL_expensive).
6148 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6149 match(Set dst con);
6150 ins_cost(MEMORY_REF_COST);
6151 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6152 ins_encode %{
6153 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6154 __ ldx($constanttablebase, con_offset, $dst$$Register);
6155 %}
6156 ins_pipe(loadConL);
6157 %}
6159 instruct loadConL0( iRegL dst, immL0 src ) %{
6160 match(Set dst src);
6161 ins_cost(DEFAULT_COST);
6162 size(4);
6163 format %{ "CLR $dst\t! long" %}
6164 ins_encode( Set13( src, dst ) );
6165 ins_pipe(ialu_imm);
6166 %}
6168 instruct loadConL13( iRegL dst, immL13 src ) %{
6169 match(Set dst src);
6170 ins_cost(DEFAULT_COST * 2);
6172 size(4);
6173 format %{ "MOV $src,$dst\t! long" %}
6174 ins_encode( Set13( src, dst ) );
6175 ins_pipe(ialu_imm);
6176 %}
6178 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6179 match(Set dst con);
6180 effect(KILL tmp);
6181 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6182 ins_encode %{
6183 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6184 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6185 %}
6186 ins_pipe(loadConFD);
6187 %}
6189 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6190 match(Set dst con);
6191 effect(KILL tmp);
6192 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6193 ins_encode %{
6194 // XXX This is a quick fix for 6833573.
6195 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6196 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6197 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6198 %}
6199 ins_pipe(loadConFD);
6200 %}
6202 // Prefetch instructions.
6203 // Must be safe to execute with invalid address (cannot fault).
6205 instruct prefetchr( memory mem ) %{
6206 match( PrefetchRead mem );
6207 ins_cost(MEMORY_REF_COST);
6208 size(4);
6210 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6211 opcode(Assembler::prefetch_op3);
6212 ins_encode( form3_mem_prefetch_read( mem ) );
6213 ins_pipe(iload_mem);
6214 %}
6216 instruct prefetchw( memory mem ) %{
6217 match( PrefetchWrite mem );
6218 ins_cost(MEMORY_REF_COST);
6219 size(4);
6221 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6222 opcode(Assembler::prefetch_op3);
6223 ins_encode( form3_mem_prefetch_write( mem ) );
6224 ins_pipe(iload_mem);
6225 %}
6227 // Prefetch instructions for allocation.
6229 instruct prefetchAlloc( memory mem ) %{
6230 predicate(AllocatePrefetchInstr == 0);
6231 match( PrefetchAllocation mem );
6232 ins_cost(MEMORY_REF_COST);
6233 size(4);
6235 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6236 opcode(Assembler::prefetch_op3);
6237 ins_encode( form3_mem_prefetch_write( mem ) );
6238 ins_pipe(iload_mem);
6239 %}
6241 // Use BIS instruction to prefetch for allocation.
6242 // Could fault, need space at the end of TLAB.
6243 instruct prefetchAlloc_bis( iRegP dst ) %{
6244 predicate(AllocatePrefetchInstr == 1);
6245 match( PrefetchAllocation dst );
6246 ins_cost(MEMORY_REF_COST);
6247 size(4);
6249 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6250 ins_encode %{
6251 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6252 %}
6253 ins_pipe(istore_mem_reg);
6254 %}
6256 // Next code is used for finding next cache line address to prefetch.
6257 #ifndef _LP64
6258 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6259 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6260 ins_cost(DEFAULT_COST);
6261 size(4);
6263 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6264 ins_encode %{
6265 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6266 %}
6267 ins_pipe(ialu_reg_imm);
6268 %}
6269 #else
6270 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6271 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6272 ins_cost(DEFAULT_COST);
6273 size(4);
6275 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6276 ins_encode %{
6277 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6278 %}
6279 ins_pipe(ialu_reg_imm);
6280 %}
6281 #endif
6283 //----------Store Instructions-------------------------------------------------
6284 // Store Byte
6285 instruct storeB(memory mem, iRegI src) %{
6286 match(Set mem (StoreB mem src));
6287 ins_cost(MEMORY_REF_COST);
6289 size(4);
6290 format %{ "STB $src,$mem\t! byte" %}
6291 opcode(Assembler::stb_op3);
6292 ins_encode(simple_form3_mem_reg( mem, src ) );
6293 ins_pipe(istore_mem_reg);
6294 %}
6296 instruct storeB0(memory mem, immI0 src) %{
6297 match(Set mem (StoreB mem src));
6298 ins_cost(MEMORY_REF_COST);
6300 size(4);
6301 format %{ "STB $src,$mem\t! byte" %}
6302 opcode(Assembler::stb_op3);
6303 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6304 ins_pipe(istore_mem_zero);
6305 %}
6307 instruct storeCM0(memory mem, immI0 src) %{
6308 match(Set mem (StoreCM mem src));
6309 ins_cost(MEMORY_REF_COST);
6311 size(4);
6312 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6313 opcode(Assembler::stb_op3);
6314 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6315 ins_pipe(istore_mem_zero);
6316 %}
6318 // Store Char/Short
6319 instruct storeC(memory mem, iRegI src) %{
6320 match(Set mem (StoreC mem src));
6321 ins_cost(MEMORY_REF_COST);
6323 size(4);
6324 format %{ "STH $src,$mem\t! short" %}
6325 opcode(Assembler::sth_op3);
6326 ins_encode(simple_form3_mem_reg( mem, src ) );
6327 ins_pipe(istore_mem_reg);
6328 %}
6330 instruct storeC0(memory mem, immI0 src) %{
6331 match(Set mem (StoreC mem src));
6332 ins_cost(MEMORY_REF_COST);
6334 size(4);
6335 format %{ "STH $src,$mem\t! short" %}
6336 opcode(Assembler::sth_op3);
6337 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6338 ins_pipe(istore_mem_zero);
6339 %}
6341 // Store Integer
6342 instruct storeI(memory mem, iRegI src) %{
6343 match(Set mem (StoreI mem src));
6344 ins_cost(MEMORY_REF_COST);
6346 size(4);
6347 format %{ "STW $src,$mem" %}
6348 opcode(Assembler::stw_op3);
6349 ins_encode(simple_form3_mem_reg( mem, src ) );
6350 ins_pipe(istore_mem_reg);
6351 %}
6353 // Store Long
6354 instruct storeL(memory mem, iRegL src) %{
6355 match(Set mem (StoreL mem src));
6356 ins_cost(MEMORY_REF_COST);
6357 size(4);
6358 format %{ "STX $src,$mem\t! long" %}
6359 opcode(Assembler::stx_op3);
6360 ins_encode(simple_form3_mem_reg( mem, src ) );
6361 ins_pipe(istore_mem_reg);
6362 %}
6364 instruct storeI0(memory mem, immI0 src) %{
6365 match(Set mem (StoreI mem src));
6366 ins_cost(MEMORY_REF_COST);
6368 size(4);
6369 format %{ "STW $src,$mem" %}
6370 opcode(Assembler::stw_op3);
6371 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6372 ins_pipe(istore_mem_zero);
6373 %}
6375 instruct storeL0(memory mem, immL0 src) %{
6376 match(Set mem (StoreL mem src));
6377 ins_cost(MEMORY_REF_COST);
6379 size(4);
6380 format %{ "STX $src,$mem" %}
6381 opcode(Assembler::stx_op3);
6382 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6383 ins_pipe(istore_mem_zero);
6384 %}
6386 // Store Integer from float register (used after fstoi)
6387 instruct storeI_Freg(memory mem, regF src) %{
6388 match(Set mem (StoreI mem src));
6389 ins_cost(MEMORY_REF_COST);
6391 size(4);
6392 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6393 opcode(Assembler::stf_op3);
6394 ins_encode(simple_form3_mem_reg( mem, src ) );
6395 ins_pipe(fstoreF_mem_reg);
6396 %}
6398 // Store Pointer
6399 instruct storeP(memory dst, sp_ptr_RegP src) %{
6400 match(Set dst (StoreP dst src));
6401 ins_cost(MEMORY_REF_COST);
6402 size(4);
6404 #ifndef _LP64
6405 format %{ "STW $src,$dst\t! ptr" %}
6406 opcode(Assembler::stw_op3, 0, REGP_OP);
6407 #else
6408 format %{ "STX $src,$dst\t! ptr" %}
6409 opcode(Assembler::stx_op3, 0, REGP_OP);
6410 #endif
6411 ins_encode( form3_mem_reg( dst, src ) );
6412 ins_pipe(istore_mem_spORreg);
6413 %}
6415 instruct storeP0(memory dst, immP0 src) %{
6416 match(Set dst (StoreP dst src));
6417 ins_cost(MEMORY_REF_COST);
6418 size(4);
6420 #ifndef _LP64
6421 format %{ "STW $src,$dst\t! ptr" %}
6422 opcode(Assembler::stw_op3, 0, REGP_OP);
6423 #else
6424 format %{ "STX $src,$dst\t! ptr" %}
6425 opcode(Assembler::stx_op3, 0, REGP_OP);
6426 #endif
6427 ins_encode( form3_mem_reg( dst, R_G0 ) );
6428 ins_pipe(istore_mem_zero);
6429 %}
6431 // Store Compressed Pointer
6432 instruct storeN(memory dst, iRegN src) %{
6433 match(Set dst (StoreN dst src));
6434 ins_cost(MEMORY_REF_COST);
6435 size(4);
6437 format %{ "STW $src,$dst\t! compressed ptr" %}
6438 ins_encode %{
6439 Register base = as_Register($dst$$base);
6440 Register index = as_Register($dst$$index);
6441 Register src = $src$$Register;
6442 if (index != G0) {
6443 __ stw(src, base, index);
6444 } else {
6445 __ stw(src, base, $dst$$disp);
6446 }
6447 %}
6448 ins_pipe(istore_mem_spORreg);
6449 %}
6451 instruct storeNKlass(memory dst, iRegN src) %{
6452 match(Set dst (StoreNKlass dst src));
6453 ins_cost(MEMORY_REF_COST);
6454 size(4);
6456 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6457 ins_encode %{
6458 Register base = as_Register($dst$$base);
6459 Register index = as_Register($dst$$index);
6460 Register src = $src$$Register;
6461 if (index != G0) {
6462 __ stw(src, base, index);
6463 } else {
6464 __ stw(src, base, $dst$$disp);
6465 }
6466 %}
6467 ins_pipe(istore_mem_spORreg);
6468 %}
6470 instruct storeN0(memory dst, immN0 src) %{
6471 match(Set dst (StoreN dst src));
6472 ins_cost(MEMORY_REF_COST);
6473 size(4);
6475 format %{ "STW $src,$dst\t! compressed ptr" %}
6476 ins_encode %{
6477 Register base = as_Register($dst$$base);
6478 Register index = as_Register($dst$$index);
6479 if (index != G0) {
6480 __ stw(0, base, index);
6481 } else {
6482 __ stw(0, base, $dst$$disp);
6483 }
6484 %}
6485 ins_pipe(istore_mem_zero);
6486 %}
6488 // Store Double
6489 instruct storeD( memory mem, regD src) %{
6490 match(Set mem (StoreD mem src));
6491 ins_cost(MEMORY_REF_COST);
6493 size(4);
6494 format %{ "STDF $src,$mem" %}
6495 opcode(Assembler::stdf_op3);
6496 ins_encode(simple_form3_mem_reg( mem, src ) );
6497 ins_pipe(fstoreD_mem_reg);
6498 %}
6500 instruct storeD0( memory mem, immD0 src) %{
6501 match(Set mem (StoreD mem src));
6502 ins_cost(MEMORY_REF_COST);
6504 size(4);
6505 format %{ "STX $src,$mem" %}
6506 opcode(Assembler::stx_op3);
6507 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6508 ins_pipe(fstoreD_mem_zero);
6509 %}
6511 // Store Float
6512 instruct storeF( memory mem, regF src) %{
6513 match(Set mem (StoreF mem src));
6514 ins_cost(MEMORY_REF_COST);
6516 size(4);
6517 format %{ "STF $src,$mem" %}
6518 opcode(Assembler::stf_op3);
6519 ins_encode(simple_form3_mem_reg( mem, src ) );
6520 ins_pipe(fstoreF_mem_reg);
6521 %}
6523 instruct storeF0( memory mem, immF0 src) %{
6524 match(Set mem (StoreF mem src));
6525 ins_cost(MEMORY_REF_COST);
6527 size(4);
6528 format %{ "STW $src,$mem\t! storeF0" %}
6529 opcode(Assembler::stw_op3);
6530 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6531 ins_pipe(fstoreF_mem_zero);
6532 %}
6534 // Convert oop pointer into compressed form
6535 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6536 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6537 match(Set dst (EncodeP src));
6538 format %{ "encode_heap_oop $src, $dst" %}
6539 ins_encode %{
6540 __ encode_heap_oop($src$$Register, $dst$$Register);
6541 %}
6542 ins_pipe(ialu_reg);
6543 %}
6545 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6546 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6547 match(Set dst (EncodeP src));
6548 format %{ "encode_heap_oop_not_null $src, $dst" %}
6549 ins_encode %{
6550 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6551 %}
6552 ins_pipe(ialu_reg);
6553 %}
6555 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6556 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6557 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6558 match(Set dst (DecodeN src));
6559 format %{ "decode_heap_oop $src, $dst" %}
6560 ins_encode %{
6561 __ decode_heap_oop($src$$Register, $dst$$Register);
6562 %}
6563 ins_pipe(ialu_reg);
6564 %}
6566 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6567 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6568 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6569 match(Set dst (DecodeN src));
6570 format %{ "decode_heap_oop_not_null $src, $dst" %}
6571 ins_encode %{
6572 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6573 %}
6574 ins_pipe(ialu_reg);
6575 %}
6577 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6578 match(Set dst (EncodePKlass src));
6579 format %{ "encode_klass_not_null $src, $dst" %}
6580 ins_encode %{
6581 __ encode_klass_not_null($src$$Register, $dst$$Register);
6582 %}
6583 ins_pipe(ialu_reg);
6584 %}
6586 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6587 match(Set dst (DecodeNKlass src));
6588 format %{ "decode_klass_not_null $src, $dst" %}
6589 ins_encode %{
6590 __ decode_klass_not_null($src$$Register, $dst$$Register);
6591 %}
6592 ins_pipe(ialu_reg);
6593 %}
6595 //----------MemBar Instructions-----------------------------------------------
6596 // Memory barrier flavors
6598 instruct membar_acquire() %{
6599 match(MemBarAcquire);
6600 ins_cost(4*MEMORY_REF_COST);
6602 size(0);
6603 format %{ "MEMBAR-acquire" %}
6604 ins_encode( enc_membar_acquire );
6605 ins_pipe(long_memory_op);
6606 %}
6608 instruct membar_acquire_lock() %{
6609 match(MemBarAcquireLock);
6610 ins_cost(0);
6612 size(0);
6613 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6614 ins_encode( );
6615 ins_pipe(empty);
6616 %}
6618 instruct membar_release() %{
6619 match(MemBarRelease);
6620 ins_cost(4*MEMORY_REF_COST);
6622 size(0);
6623 format %{ "MEMBAR-release" %}
6624 ins_encode( enc_membar_release );
6625 ins_pipe(long_memory_op);
6626 %}
6628 instruct membar_release_lock() %{
6629 match(MemBarReleaseLock);
6630 ins_cost(0);
6632 size(0);
6633 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6634 ins_encode( );
6635 ins_pipe(empty);
6636 %}
6638 instruct membar_volatile() %{
6639 match(MemBarVolatile);
6640 ins_cost(4*MEMORY_REF_COST);
6642 size(4);
6643 format %{ "MEMBAR-volatile" %}
6644 ins_encode( enc_membar_volatile );
6645 ins_pipe(long_memory_op);
6646 %}
6648 instruct unnecessary_membar_volatile() %{
6649 match(MemBarVolatile);
6650 predicate(Matcher::post_store_load_barrier(n));
6651 ins_cost(0);
6653 size(0);
6654 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6655 ins_encode( );
6656 ins_pipe(empty);
6657 %}
6659 instruct membar_storestore() %{
6660 match(MemBarStoreStore);
6661 ins_cost(0);
6663 size(0);
6664 format %{ "!MEMBAR-storestore (empty encoding)" %}
6665 ins_encode( );
6666 ins_pipe(empty);
6667 %}
6669 //----------Register Move Instructions-----------------------------------------
6670 instruct roundDouble_nop(regD dst) %{
6671 match(Set dst (RoundDouble dst));
6672 ins_cost(0);
6673 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6674 ins_encode( );
6675 ins_pipe(empty);
6676 %}
6679 instruct roundFloat_nop(regF dst) %{
6680 match(Set dst (RoundFloat dst));
6681 ins_cost(0);
6682 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6683 ins_encode( );
6684 ins_pipe(empty);
6685 %}
6688 // Cast Index to Pointer for unsafe natives
6689 instruct castX2P(iRegX src, iRegP dst) %{
6690 match(Set dst (CastX2P src));
6692 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6693 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6694 ins_pipe(ialu_reg);
6695 %}
6697 // Cast Pointer to Index for unsafe natives
6698 instruct castP2X(iRegP src, iRegX dst) %{
6699 match(Set dst (CastP2X src));
6701 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6702 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6703 ins_pipe(ialu_reg);
6704 %}
6706 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6707 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6708 match(Set stkSlot src); // chain rule
6709 ins_cost(MEMORY_REF_COST);
6710 format %{ "STDF $src,$stkSlot\t!stk" %}
6711 opcode(Assembler::stdf_op3);
6712 ins_encode(simple_form3_mem_reg(stkSlot, src));
6713 ins_pipe(fstoreD_stk_reg);
6714 %}
6716 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6717 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6718 match(Set dst stkSlot); // chain rule
6719 ins_cost(MEMORY_REF_COST);
6720 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6721 opcode(Assembler::lddf_op3);
6722 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6723 ins_pipe(floadD_stk);
6724 %}
6726 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6727 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6728 match(Set stkSlot src); // chain rule
6729 ins_cost(MEMORY_REF_COST);
6730 format %{ "STF $src,$stkSlot\t!stk" %}
6731 opcode(Assembler::stf_op3);
6732 ins_encode(simple_form3_mem_reg(stkSlot, src));
6733 ins_pipe(fstoreF_stk_reg);
6734 %}
6736 //----------Conditional Move---------------------------------------------------
6737 // Conditional move
6738 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6739 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6740 ins_cost(150);
6741 format %{ "MOV$cmp $pcc,$src,$dst" %}
6742 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6743 ins_pipe(ialu_reg);
6744 %}
6746 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6747 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6748 ins_cost(140);
6749 format %{ "MOV$cmp $pcc,$src,$dst" %}
6750 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6751 ins_pipe(ialu_imm);
6752 %}
6754 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6755 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6756 ins_cost(150);
6757 size(4);
6758 format %{ "MOV$cmp $icc,$src,$dst" %}
6759 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6760 ins_pipe(ialu_reg);
6761 %}
6763 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6764 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6765 ins_cost(140);
6766 size(4);
6767 format %{ "MOV$cmp $icc,$src,$dst" %}
6768 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6769 ins_pipe(ialu_imm);
6770 %}
6772 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6773 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6774 ins_cost(150);
6775 size(4);
6776 format %{ "MOV$cmp $icc,$src,$dst" %}
6777 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6778 ins_pipe(ialu_reg);
6779 %}
6781 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6782 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6783 ins_cost(140);
6784 size(4);
6785 format %{ "MOV$cmp $icc,$src,$dst" %}
6786 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6787 ins_pipe(ialu_imm);
6788 %}
6790 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6791 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6792 ins_cost(150);
6793 size(4);
6794 format %{ "MOV$cmp $fcc,$src,$dst" %}
6795 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6796 ins_pipe(ialu_reg);
6797 %}
6799 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6800 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6801 ins_cost(140);
6802 size(4);
6803 format %{ "MOV$cmp $fcc,$src,$dst" %}
6804 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6805 ins_pipe(ialu_imm);
6806 %}
6808 // Conditional move for RegN. Only cmov(reg,reg).
6809 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6810 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6811 ins_cost(150);
6812 format %{ "MOV$cmp $pcc,$src,$dst" %}
6813 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6814 ins_pipe(ialu_reg);
6815 %}
6817 // This instruction also works with CmpN so we don't need cmovNN_reg.
6818 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6819 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6820 ins_cost(150);
6821 size(4);
6822 format %{ "MOV$cmp $icc,$src,$dst" %}
6823 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6824 ins_pipe(ialu_reg);
6825 %}
6827 // This instruction also works with CmpN so we don't need cmovNN_reg.
6828 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6829 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6830 ins_cost(150);
6831 size(4);
6832 format %{ "MOV$cmp $icc,$src,$dst" %}
6833 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6834 ins_pipe(ialu_reg);
6835 %}
6837 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6838 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6839 ins_cost(150);
6840 size(4);
6841 format %{ "MOV$cmp $fcc,$src,$dst" %}
6842 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6843 ins_pipe(ialu_reg);
6844 %}
6846 // Conditional move
6847 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6848 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6849 ins_cost(150);
6850 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6851 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6852 ins_pipe(ialu_reg);
6853 %}
6855 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6856 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6857 ins_cost(140);
6858 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6859 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6860 ins_pipe(ialu_imm);
6861 %}
6863 // This instruction also works with CmpN so we don't need cmovPN_reg.
6864 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6865 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6866 ins_cost(150);
6868 size(4);
6869 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6871 ins_pipe(ialu_reg);
6872 %}
6874 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6875 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6876 ins_cost(150);
6878 size(4);
6879 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6880 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6881 ins_pipe(ialu_reg);
6882 %}
6884 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6885 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6886 ins_cost(140);
6888 size(4);
6889 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6890 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6891 ins_pipe(ialu_imm);
6892 %}
6894 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6895 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6896 ins_cost(140);
6898 size(4);
6899 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6900 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6901 ins_pipe(ialu_imm);
6902 %}
6904 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6905 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6906 ins_cost(150);
6907 size(4);
6908 format %{ "MOV$cmp $fcc,$src,$dst" %}
6909 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6910 ins_pipe(ialu_imm);
6911 %}
6913 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6914 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6915 ins_cost(140);
6916 size(4);
6917 format %{ "MOV$cmp $fcc,$src,$dst" %}
6918 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6919 ins_pipe(ialu_imm);
6920 %}
6922 // Conditional move
6923 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6924 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6925 ins_cost(150);
6926 opcode(0x101);
6927 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6928 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6929 ins_pipe(int_conditional_float_move);
6930 %}
6932 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6933 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6934 ins_cost(150);
6936 size(4);
6937 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6938 opcode(0x101);
6939 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6940 ins_pipe(int_conditional_float_move);
6941 %}
6943 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6944 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6945 ins_cost(150);
6947 size(4);
6948 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6949 opcode(0x101);
6950 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6951 ins_pipe(int_conditional_float_move);
6952 %}
6954 // Conditional move,
6955 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6956 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6957 ins_cost(150);
6958 size(4);
6959 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6960 opcode(0x1);
6961 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6962 ins_pipe(int_conditional_double_move);
6963 %}
6965 // Conditional move
6966 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6967 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6968 ins_cost(150);
6969 size(4);
6970 opcode(0x102);
6971 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6972 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6973 ins_pipe(int_conditional_double_move);
6974 %}
6976 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6977 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6978 ins_cost(150);
6980 size(4);
6981 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6982 opcode(0x102);
6983 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6984 ins_pipe(int_conditional_double_move);
6985 %}
6987 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6988 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6989 ins_cost(150);
6991 size(4);
6992 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6993 opcode(0x102);
6994 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6995 ins_pipe(int_conditional_double_move);
6996 %}
6998 // Conditional move,
6999 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7000 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7001 ins_cost(150);
7002 size(4);
7003 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7004 opcode(0x2);
7005 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7006 ins_pipe(int_conditional_double_move);
7007 %}
7009 // Conditional move
7010 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7011 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7012 ins_cost(150);
7013 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7014 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7015 ins_pipe(ialu_reg);
7016 %}
7018 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7019 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7020 ins_cost(140);
7021 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7022 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7023 ins_pipe(ialu_imm);
7024 %}
7026 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7027 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7028 ins_cost(150);
7030 size(4);
7031 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7032 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7033 ins_pipe(ialu_reg);
7034 %}
7037 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7038 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7039 ins_cost(150);
7041 size(4);
7042 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7043 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7044 ins_pipe(ialu_reg);
7045 %}
7048 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7049 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7050 ins_cost(150);
7052 size(4);
7053 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7054 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7055 ins_pipe(ialu_reg);
7056 %}
7060 //----------OS and Locking Instructions----------------------------------------
7062 // This name is KNOWN by the ADLC and cannot be changed.
7063 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7064 // for this guy.
7065 instruct tlsLoadP(g2RegP dst) %{
7066 match(Set dst (ThreadLocal));
7068 size(0);
7069 ins_cost(0);
7070 format %{ "# TLS is in G2" %}
7071 ins_encode( /*empty encoding*/ );
7072 ins_pipe(ialu_none);
7073 %}
7075 instruct checkCastPP( iRegP dst ) %{
7076 match(Set dst (CheckCastPP dst));
7078 size(0);
7079 format %{ "# checkcastPP of $dst" %}
7080 ins_encode( /*empty encoding*/ );
7081 ins_pipe(empty);
7082 %}
7085 instruct castPP( iRegP dst ) %{
7086 match(Set dst (CastPP dst));
7087 format %{ "# castPP of $dst" %}
7088 ins_encode( /*empty encoding*/ );
7089 ins_pipe(empty);
7090 %}
7092 instruct castII( iRegI dst ) %{
7093 match(Set dst (CastII dst));
7094 format %{ "# castII of $dst" %}
7095 ins_encode( /*empty encoding*/ );
7096 ins_cost(0);
7097 ins_pipe(empty);
7098 %}
7100 //----------Arithmetic Instructions--------------------------------------------
7101 // Addition Instructions
7102 // Register Addition
7103 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7104 match(Set dst (AddI src1 src2));
7106 size(4);
7107 format %{ "ADD $src1,$src2,$dst" %}
7108 ins_encode %{
7109 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7110 %}
7111 ins_pipe(ialu_reg_reg);
7112 %}
7114 // Immediate Addition
7115 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7116 match(Set dst (AddI src1 src2));
7118 size(4);
7119 format %{ "ADD $src1,$src2,$dst" %}
7120 opcode(Assembler::add_op3, Assembler::arith_op);
7121 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7122 ins_pipe(ialu_reg_imm);
7123 %}
7125 // Pointer Register Addition
7126 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7127 match(Set dst (AddP src1 src2));
7129 size(4);
7130 format %{ "ADD $src1,$src2,$dst" %}
7131 opcode(Assembler::add_op3, Assembler::arith_op);
7132 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7133 ins_pipe(ialu_reg_reg);
7134 %}
7136 // Pointer Immediate Addition
7137 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7138 match(Set dst (AddP src1 src2));
7140 size(4);
7141 format %{ "ADD $src1,$src2,$dst" %}
7142 opcode(Assembler::add_op3, Assembler::arith_op);
7143 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7144 ins_pipe(ialu_reg_imm);
7145 %}
7147 // Long Addition
7148 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7149 match(Set dst (AddL src1 src2));
7151 size(4);
7152 format %{ "ADD $src1,$src2,$dst\t! long" %}
7153 opcode(Assembler::add_op3, Assembler::arith_op);
7154 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7155 ins_pipe(ialu_reg_reg);
7156 %}
7158 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7159 match(Set dst (AddL src1 con));
7161 size(4);
7162 format %{ "ADD $src1,$con,$dst" %}
7163 opcode(Assembler::add_op3, Assembler::arith_op);
7164 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7165 ins_pipe(ialu_reg_imm);
7166 %}
7168 //----------Conditional_store--------------------------------------------------
7169 // Conditional-store of the updated heap-top.
7170 // Used during allocation of the shared heap.
7171 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7173 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7174 instruct loadPLocked(iRegP dst, memory mem) %{
7175 match(Set dst (LoadPLocked mem));
7176 ins_cost(MEMORY_REF_COST);
7178 #ifndef _LP64
7179 size(4);
7180 format %{ "LDUW $mem,$dst\t! ptr" %}
7181 opcode(Assembler::lduw_op3, 0, REGP_OP);
7182 #else
7183 format %{ "LDX $mem,$dst\t! ptr" %}
7184 opcode(Assembler::ldx_op3, 0, REGP_OP);
7185 #endif
7186 ins_encode( form3_mem_reg( mem, dst ) );
7187 ins_pipe(iload_mem);
7188 %}
7190 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7191 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7192 effect( KILL newval );
7193 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7194 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7195 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7196 ins_pipe( long_memory_op );
7197 %}
7199 // Conditional-store of an int value.
7200 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7201 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7202 effect( KILL newval );
7203 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7204 "CMP $oldval,$newval\t\t! See if we made progress" %}
7205 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7206 ins_pipe( long_memory_op );
7207 %}
7209 // Conditional-store of a long value.
7210 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7211 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7212 effect( KILL newval );
7213 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7214 "CMP $oldval,$newval\t\t! See if we made progress" %}
7215 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7216 ins_pipe( long_memory_op );
7217 %}
7219 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7221 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7222 predicate(VM_Version::supports_cx8());
7223 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7224 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7225 format %{
7226 "MOV $newval,O7\n\t"
7227 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7228 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7229 "MOV 1,$res\n\t"
7230 "MOVne xcc,R_G0,$res"
7231 %}
7232 ins_encode( enc_casx(mem_ptr, oldval, newval),
7233 enc_lflags_ne_to_boolean(res) );
7234 ins_pipe( long_memory_op );
7235 %}
7238 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7239 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7240 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7241 format %{
7242 "MOV $newval,O7\n\t"
7243 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7244 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7245 "MOV 1,$res\n\t"
7246 "MOVne icc,R_G0,$res"
7247 %}
7248 ins_encode( enc_casi(mem_ptr, oldval, newval),
7249 enc_iflags_ne_to_boolean(res) );
7250 ins_pipe( long_memory_op );
7251 %}
7253 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7254 #ifdef _LP64
7255 predicate(VM_Version::supports_cx8());
7256 #endif
7257 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7258 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7259 format %{
7260 "MOV $newval,O7\n\t"
7261 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7262 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7263 "MOV 1,$res\n\t"
7264 "MOVne xcc,R_G0,$res"
7265 %}
7266 #ifdef _LP64
7267 ins_encode( enc_casx(mem_ptr, oldval, newval),
7268 enc_lflags_ne_to_boolean(res) );
7269 #else
7270 ins_encode( enc_casi(mem_ptr, oldval, newval),
7271 enc_iflags_ne_to_boolean(res) );
7272 #endif
7273 ins_pipe( long_memory_op );
7274 %}
7276 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7277 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7278 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7279 format %{
7280 "MOV $newval,O7\n\t"
7281 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7282 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7283 "MOV 1,$res\n\t"
7284 "MOVne icc,R_G0,$res"
7285 %}
7286 ins_encode( enc_casi(mem_ptr, oldval, newval),
7287 enc_iflags_ne_to_boolean(res) );
7288 ins_pipe( long_memory_op );
7289 %}
7291 instruct xchgI( memory mem, iRegI newval) %{
7292 match(Set newval (GetAndSetI mem newval));
7293 format %{ "SWAP [$mem],$newval" %}
7294 size(4);
7295 ins_encode %{
7296 __ swap($mem$$Address, $newval$$Register);
7297 %}
7298 ins_pipe( long_memory_op );
7299 %}
7301 #ifndef _LP64
7302 instruct xchgP( memory mem, iRegP newval) %{
7303 match(Set newval (GetAndSetP mem newval));
7304 format %{ "SWAP [$mem],$newval" %}
7305 size(4);
7306 ins_encode %{
7307 __ swap($mem$$Address, $newval$$Register);
7308 %}
7309 ins_pipe( long_memory_op );
7310 %}
7311 #endif
7313 instruct xchgN( memory mem, iRegN newval) %{
7314 match(Set newval (GetAndSetN mem newval));
7315 format %{ "SWAP [$mem],$newval" %}
7316 size(4);
7317 ins_encode %{
7318 __ swap($mem$$Address, $newval$$Register);
7319 %}
7320 ins_pipe( long_memory_op );
7321 %}
7323 //---------------------
7324 // Subtraction Instructions
7325 // Register Subtraction
7326 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7327 match(Set dst (SubI src1 src2));
7329 size(4);
7330 format %{ "SUB $src1,$src2,$dst" %}
7331 opcode(Assembler::sub_op3, Assembler::arith_op);
7332 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7333 ins_pipe(ialu_reg_reg);
7334 %}
7336 // Immediate Subtraction
7337 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7338 match(Set dst (SubI src1 src2));
7340 size(4);
7341 format %{ "SUB $src1,$src2,$dst" %}
7342 opcode(Assembler::sub_op3, Assembler::arith_op);
7343 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7344 ins_pipe(ialu_reg_imm);
7345 %}
7347 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7348 match(Set dst (SubI zero src2));
7350 size(4);
7351 format %{ "NEG $src2,$dst" %}
7352 opcode(Assembler::sub_op3, Assembler::arith_op);
7353 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7354 ins_pipe(ialu_zero_reg);
7355 %}
7357 // Long subtraction
7358 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7359 match(Set dst (SubL src1 src2));
7361 size(4);
7362 format %{ "SUB $src1,$src2,$dst\t! long" %}
7363 opcode(Assembler::sub_op3, Assembler::arith_op);
7364 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7365 ins_pipe(ialu_reg_reg);
7366 %}
7368 // Immediate Subtraction
7369 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7370 match(Set dst (SubL src1 con));
7372 size(4);
7373 format %{ "SUB $src1,$con,$dst\t! long" %}
7374 opcode(Assembler::sub_op3, Assembler::arith_op);
7375 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7376 ins_pipe(ialu_reg_imm);
7377 %}
7379 // Long negation
7380 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7381 match(Set dst (SubL zero src2));
7383 size(4);
7384 format %{ "NEG $src2,$dst\t! long" %}
7385 opcode(Assembler::sub_op3, Assembler::arith_op);
7386 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7387 ins_pipe(ialu_zero_reg);
7388 %}
7390 // Multiplication Instructions
7391 // Integer Multiplication
7392 // Register Multiplication
7393 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7394 match(Set dst (MulI src1 src2));
7396 size(4);
7397 format %{ "MULX $src1,$src2,$dst" %}
7398 opcode(Assembler::mulx_op3, Assembler::arith_op);
7399 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7400 ins_pipe(imul_reg_reg);
7401 %}
7403 // Immediate Multiplication
7404 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7405 match(Set dst (MulI src1 src2));
7407 size(4);
7408 format %{ "MULX $src1,$src2,$dst" %}
7409 opcode(Assembler::mulx_op3, Assembler::arith_op);
7410 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7411 ins_pipe(imul_reg_imm);
7412 %}
7414 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7415 match(Set dst (MulL src1 src2));
7416 ins_cost(DEFAULT_COST * 5);
7417 size(4);
7418 format %{ "MULX $src1,$src2,$dst\t! long" %}
7419 opcode(Assembler::mulx_op3, Assembler::arith_op);
7420 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7421 ins_pipe(mulL_reg_reg);
7422 %}
7424 // Immediate Multiplication
7425 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7426 match(Set dst (MulL src1 src2));
7427 ins_cost(DEFAULT_COST * 5);
7428 size(4);
7429 format %{ "MULX $src1,$src2,$dst" %}
7430 opcode(Assembler::mulx_op3, Assembler::arith_op);
7431 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7432 ins_pipe(mulL_reg_imm);
7433 %}
7435 // Integer Division
7436 // Register Division
7437 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7438 match(Set dst (DivI src1 src2));
7439 ins_cost((2+71)*DEFAULT_COST);
7441 format %{ "SRA $src2,0,$src2\n\t"
7442 "SRA $src1,0,$src1\n\t"
7443 "SDIVX $src1,$src2,$dst" %}
7444 ins_encode( idiv_reg( src1, src2, dst ) );
7445 ins_pipe(sdiv_reg_reg);
7446 %}
7448 // Immediate Division
7449 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7450 match(Set dst (DivI src1 src2));
7451 ins_cost((2+71)*DEFAULT_COST);
7453 format %{ "SRA $src1,0,$src1\n\t"
7454 "SDIVX $src1,$src2,$dst" %}
7455 ins_encode( idiv_imm( src1, src2, dst ) );
7456 ins_pipe(sdiv_reg_imm);
7457 %}
7459 //----------Div-By-10-Expansion------------------------------------------------
7460 // Extract hi bits of a 32x32->64 bit multiply.
7461 // Expand rule only, not matched
7462 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7463 effect( DEF dst, USE src1, USE src2 );
7464 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7465 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7466 ins_encode( enc_mul_hi(dst,src1,src2));
7467 ins_pipe(sdiv_reg_reg);
7468 %}
7470 // Magic constant, reciprocal of 10
7471 instruct loadConI_x66666667(iRegIsafe dst) %{
7472 effect( DEF dst );
7474 size(8);
7475 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7476 ins_encode( Set32(0x66666667, dst) );
7477 ins_pipe(ialu_hi_lo_reg);
7478 %}
7480 // Register Shift Right Arithmetic Long by 32-63
7481 instruct sra_31( iRegI dst, iRegI src ) %{
7482 effect( DEF dst, USE src );
7483 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7484 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7485 ins_pipe(ialu_reg_reg);
7486 %}
7488 // Arithmetic Shift Right by 8-bit immediate
7489 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7490 effect( DEF dst, USE src );
7491 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7492 opcode(Assembler::sra_op3, Assembler::arith_op);
7493 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7494 ins_pipe(ialu_reg_imm);
7495 %}
7497 // Integer DIV with 10
7498 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7499 match(Set dst (DivI src div));
7500 ins_cost((6+6)*DEFAULT_COST);
7501 expand %{
7502 iRegIsafe tmp1; // Killed temps;
7503 iRegIsafe tmp2; // Killed temps;
7504 iRegI tmp3; // Killed temps;
7505 iRegI tmp4; // Killed temps;
7506 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7507 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7508 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7509 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7510 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7511 %}
7512 %}
7514 // Register Long Division
7515 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7516 match(Set dst (DivL src1 src2));
7517 ins_cost(DEFAULT_COST*71);
7518 size(4);
7519 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7520 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7521 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7522 ins_pipe(divL_reg_reg);
7523 %}
7525 // Register Long Division
7526 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7527 match(Set dst (DivL src1 src2));
7528 ins_cost(DEFAULT_COST*71);
7529 size(4);
7530 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7531 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7532 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7533 ins_pipe(divL_reg_imm);
7534 %}
7536 // Integer Remainder
7537 // Register Remainder
7538 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7539 match(Set dst (ModI src1 src2));
7540 effect( KILL ccr, KILL temp);
7542 format %{ "SREM $src1,$src2,$dst" %}
7543 ins_encode( irem_reg(src1, src2, dst, temp) );
7544 ins_pipe(sdiv_reg_reg);
7545 %}
7547 // Immediate Remainder
7548 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7549 match(Set dst (ModI src1 src2));
7550 effect( KILL ccr, KILL temp);
7552 format %{ "SREM $src1,$src2,$dst" %}
7553 ins_encode( irem_imm(src1, src2, dst, temp) );
7554 ins_pipe(sdiv_reg_imm);
7555 %}
7557 // Register Long Remainder
7558 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7559 effect(DEF dst, USE src1, USE src2);
7560 size(4);
7561 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7562 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7563 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7564 ins_pipe(divL_reg_reg);
7565 %}
7567 // Register Long Division
7568 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7569 effect(DEF dst, USE src1, USE src2);
7570 size(4);
7571 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7572 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7573 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7574 ins_pipe(divL_reg_imm);
7575 %}
7577 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7578 effect(DEF dst, USE src1, USE src2);
7579 size(4);
7580 format %{ "MULX $src1,$src2,$dst\t! long" %}
7581 opcode(Assembler::mulx_op3, Assembler::arith_op);
7582 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7583 ins_pipe(mulL_reg_reg);
7584 %}
7586 // Immediate Multiplication
7587 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7588 effect(DEF dst, USE src1, USE src2);
7589 size(4);
7590 format %{ "MULX $src1,$src2,$dst" %}
7591 opcode(Assembler::mulx_op3, Assembler::arith_op);
7592 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7593 ins_pipe(mulL_reg_imm);
7594 %}
7596 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7597 effect(DEF dst, USE src1, USE src2);
7598 size(4);
7599 format %{ "SUB $src1,$src2,$dst\t! long" %}
7600 opcode(Assembler::sub_op3, Assembler::arith_op);
7601 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7602 ins_pipe(ialu_reg_reg);
7603 %}
7605 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7606 effect(DEF dst, USE src1, USE src2);
7607 size(4);
7608 format %{ "SUB $src1,$src2,$dst\t! long" %}
7609 opcode(Assembler::sub_op3, Assembler::arith_op);
7610 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7611 ins_pipe(ialu_reg_reg);
7612 %}
7614 // Register Long Remainder
7615 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7616 match(Set dst (ModL src1 src2));
7617 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7618 expand %{
7619 iRegL tmp1;
7620 iRegL tmp2;
7621 divL_reg_reg_1(tmp1, src1, src2);
7622 mulL_reg_reg_1(tmp2, tmp1, src2);
7623 subL_reg_reg_1(dst, src1, tmp2);
7624 %}
7625 %}
7627 // Register Long Remainder
7628 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7629 match(Set dst (ModL src1 src2));
7630 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7631 expand %{
7632 iRegL tmp1;
7633 iRegL tmp2;
7634 divL_reg_imm13_1(tmp1, src1, src2);
7635 mulL_reg_imm13_1(tmp2, tmp1, src2);
7636 subL_reg_reg_2 (dst, src1, tmp2);
7637 %}
7638 %}
7640 // Integer Shift Instructions
7641 // Register Shift Left
7642 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7643 match(Set dst (LShiftI src1 src2));
7645 size(4);
7646 format %{ "SLL $src1,$src2,$dst" %}
7647 opcode(Assembler::sll_op3, Assembler::arith_op);
7648 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7649 ins_pipe(ialu_reg_reg);
7650 %}
7652 // Register Shift Left Immediate
7653 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7654 match(Set dst (LShiftI src1 src2));
7656 size(4);
7657 format %{ "SLL $src1,$src2,$dst" %}
7658 opcode(Assembler::sll_op3, Assembler::arith_op);
7659 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7660 ins_pipe(ialu_reg_imm);
7661 %}
7663 // Register Shift Left
7664 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7665 match(Set dst (LShiftL src1 src2));
7667 size(4);
7668 format %{ "SLLX $src1,$src2,$dst" %}
7669 opcode(Assembler::sllx_op3, Assembler::arith_op);
7670 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7671 ins_pipe(ialu_reg_reg);
7672 %}
7674 // Register Shift Left Immediate
7675 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7676 match(Set dst (LShiftL src1 src2));
7678 size(4);
7679 format %{ "SLLX $src1,$src2,$dst" %}
7680 opcode(Assembler::sllx_op3, Assembler::arith_op);
7681 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7682 ins_pipe(ialu_reg_imm);
7683 %}
7685 // Register Arithmetic Shift Right
7686 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7687 match(Set dst (RShiftI src1 src2));
7688 size(4);
7689 format %{ "SRA $src1,$src2,$dst" %}
7690 opcode(Assembler::sra_op3, Assembler::arith_op);
7691 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7692 ins_pipe(ialu_reg_reg);
7693 %}
7695 // Register Arithmetic Shift Right Immediate
7696 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7697 match(Set dst (RShiftI src1 src2));
7699 size(4);
7700 format %{ "SRA $src1,$src2,$dst" %}
7701 opcode(Assembler::sra_op3, Assembler::arith_op);
7702 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7703 ins_pipe(ialu_reg_imm);
7704 %}
7706 // Register Shift Right Arithmatic Long
7707 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7708 match(Set dst (RShiftL src1 src2));
7710 size(4);
7711 format %{ "SRAX $src1,$src2,$dst" %}
7712 opcode(Assembler::srax_op3, Assembler::arith_op);
7713 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7714 ins_pipe(ialu_reg_reg);
7715 %}
7717 // Register Shift Left Immediate
7718 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7719 match(Set dst (RShiftL src1 src2));
7721 size(4);
7722 format %{ "SRAX $src1,$src2,$dst" %}
7723 opcode(Assembler::srax_op3, Assembler::arith_op);
7724 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7725 ins_pipe(ialu_reg_imm);
7726 %}
7728 // Register Shift Right
7729 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7730 match(Set dst (URShiftI src1 src2));
7732 size(4);
7733 format %{ "SRL $src1,$src2,$dst" %}
7734 opcode(Assembler::srl_op3, Assembler::arith_op);
7735 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7736 ins_pipe(ialu_reg_reg);
7737 %}
7739 // Register Shift Right Immediate
7740 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7741 match(Set dst (URShiftI src1 src2));
7743 size(4);
7744 format %{ "SRL $src1,$src2,$dst" %}
7745 opcode(Assembler::srl_op3, Assembler::arith_op);
7746 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7747 ins_pipe(ialu_reg_imm);
7748 %}
7750 // Register Shift Right
7751 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7752 match(Set dst (URShiftL src1 src2));
7754 size(4);
7755 format %{ "SRLX $src1,$src2,$dst" %}
7756 opcode(Assembler::srlx_op3, Assembler::arith_op);
7757 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7758 ins_pipe(ialu_reg_reg);
7759 %}
7761 // Register Shift Right Immediate
7762 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7763 match(Set dst (URShiftL src1 src2));
7765 size(4);
7766 format %{ "SRLX $src1,$src2,$dst" %}
7767 opcode(Assembler::srlx_op3, Assembler::arith_op);
7768 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7769 ins_pipe(ialu_reg_imm);
7770 %}
7772 // Register Shift Right Immediate with a CastP2X
7773 #ifdef _LP64
7774 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7775 match(Set dst (URShiftL (CastP2X src1) src2));
7776 size(4);
7777 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7778 opcode(Assembler::srlx_op3, Assembler::arith_op);
7779 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7780 ins_pipe(ialu_reg_imm);
7781 %}
7782 #else
7783 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7784 match(Set dst (URShiftI (CastP2X src1) src2));
7785 size(4);
7786 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7787 opcode(Assembler::srl_op3, Assembler::arith_op);
7788 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7789 ins_pipe(ialu_reg_imm);
7790 %}
7791 #endif
7794 //----------Floating Point Arithmetic Instructions-----------------------------
7796 // Add float single precision
7797 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7798 match(Set dst (AddF src1 src2));
7800 size(4);
7801 format %{ "FADDS $src1,$src2,$dst" %}
7802 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7803 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7804 ins_pipe(faddF_reg_reg);
7805 %}
7807 // Add float double precision
7808 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7809 match(Set dst (AddD src1 src2));
7811 size(4);
7812 format %{ "FADDD $src1,$src2,$dst" %}
7813 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7814 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7815 ins_pipe(faddD_reg_reg);
7816 %}
7818 // Sub float single precision
7819 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7820 match(Set dst (SubF src1 src2));
7822 size(4);
7823 format %{ "FSUBS $src1,$src2,$dst" %}
7824 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7825 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7826 ins_pipe(faddF_reg_reg);
7827 %}
7829 // Sub float double precision
7830 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7831 match(Set dst (SubD src1 src2));
7833 size(4);
7834 format %{ "FSUBD $src1,$src2,$dst" %}
7835 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7836 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7837 ins_pipe(faddD_reg_reg);
7838 %}
7840 // Mul float single precision
7841 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7842 match(Set dst (MulF src1 src2));
7844 size(4);
7845 format %{ "FMULS $src1,$src2,$dst" %}
7846 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7847 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7848 ins_pipe(fmulF_reg_reg);
7849 %}
7851 // Mul float double precision
7852 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7853 match(Set dst (MulD src1 src2));
7855 size(4);
7856 format %{ "FMULD $src1,$src2,$dst" %}
7857 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7858 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7859 ins_pipe(fmulD_reg_reg);
7860 %}
7862 // Div float single precision
7863 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7864 match(Set dst (DivF src1 src2));
7866 size(4);
7867 format %{ "FDIVS $src1,$src2,$dst" %}
7868 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7869 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7870 ins_pipe(fdivF_reg_reg);
7871 %}
7873 // Div float double precision
7874 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7875 match(Set dst (DivD src1 src2));
7877 size(4);
7878 format %{ "FDIVD $src1,$src2,$dst" %}
7879 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7880 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7881 ins_pipe(fdivD_reg_reg);
7882 %}
7884 // Absolute float double precision
7885 instruct absD_reg(regD dst, regD src) %{
7886 match(Set dst (AbsD src));
7888 format %{ "FABSd $src,$dst" %}
7889 ins_encode(fabsd(dst, src));
7890 ins_pipe(faddD_reg);
7891 %}
7893 // Absolute float single precision
7894 instruct absF_reg(regF dst, regF src) %{
7895 match(Set dst (AbsF src));
7897 format %{ "FABSs $src,$dst" %}
7898 ins_encode(fabss(dst, src));
7899 ins_pipe(faddF_reg);
7900 %}
7902 instruct negF_reg(regF dst, regF src) %{
7903 match(Set dst (NegF src));
7905 size(4);
7906 format %{ "FNEGs $src,$dst" %}
7907 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7908 ins_encode(form3_opf_rs2F_rdF(src, dst));
7909 ins_pipe(faddF_reg);
7910 %}
7912 instruct negD_reg(regD dst, regD src) %{
7913 match(Set dst (NegD src));
7915 format %{ "FNEGd $src,$dst" %}
7916 ins_encode(fnegd(dst, src));
7917 ins_pipe(faddD_reg);
7918 %}
7920 // Sqrt float double precision
7921 instruct sqrtF_reg_reg(regF dst, regF src) %{
7922 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7924 size(4);
7925 format %{ "FSQRTS $src,$dst" %}
7926 ins_encode(fsqrts(dst, src));
7927 ins_pipe(fdivF_reg_reg);
7928 %}
7930 // Sqrt float double precision
7931 instruct sqrtD_reg_reg(regD dst, regD src) %{
7932 match(Set dst (SqrtD src));
7934 size(4);
7935 format %{ "FSQRTD $src,$dst" %}
7936 ins_encode(fsqrtd(dst, src));
7937 ins_pipe(fdivD_reg_reg);
7938 %}
7940 //----------Logical Instructions-----------------------------------------------
7941 // And Instructions
7942 // Register And
7943 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7944 match(Set dst (AndI src1 src2));
7946 size(4);
7947 format %{ "AND $src1,$src2,$dst" %}
7948 opcode(Assembler::and_op3, Assembler::arith_op);
7949 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7950 ins_pipe(ialu_reg_reg);
7951 %}
7953 // Immediate And
7954 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7955 match(Set dst (AndI src1 src2));
7957 size(4);
7958 format %{ "AND $src1,$src2,$dst" %}
7959 opcode(Assembler::and_op3, Assembler::arith_op);
7960 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7961 ins_pipe(ialu_reg_imm);
7962 %}
7964 // Register And Long
7965 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7966 match(Set dst (AndL src1 src2));
7968 ins_cost(DEFAULT_COST);
7969 size(4);
7970 format %{ "AND $src1,$src2,$dst\t! long" %}
7971 opcode(Assembler::and_op3, Assembler::arith_op);
7972 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7973 ins_pipe(ialu_reg_reg);
7974 %}
7976 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7977 match(Set dst (AndL src1 con));
7979 ins_cost(DEFAULT_COST);
7980 size(4);
7981 format %{ "AND $src1,$con,$dst\t! long" %}
7982 opcode(Assembler::and_op3, Assembler::arith_op);
7983 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7984 ins_pipe(ialu_reg_imm);
7985 %}
7987 // Or Instructions
7988 // Register Or
7989 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7990 match(Set dst (OrI src1 src2));
7992 size(4);
7993 format %{ "OR $src1,$src2,$dst" %}
7994 opcode(Assembler::or_op3, Assembler::arith_op);
7995 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7996 ins_pipe(ialu_reg_reg);
7997 %}
7999 // Immediate Or
8000 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8001 match(Set dst (OrI src1 src2));
8003 size(4);
8004 format %{ "OR $src1,$src2,$dst" %}
8005 opcode(Assembler::or_op3, Assembler::arith_op);
8006 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8007 ins_pipe(ialu_reg_imm);
8008 %}
8010 // Register Or Long
8011 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8012 match(Set dst (OrL src1 src2));
8014 ins_cost(DEFAULT_COST);
8015 size(4);
8016 format %{ "OR $src1,$src2,$dst\t! long" %}
8017 opcode(Assembler::or_op3, Assembler::arith_op);
8018 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8019 ins_pipe(ialu_reg_reg);
8020 %}
8022 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8023 match(Set dst (OrL src1 con));
8024 ins_cost(DEFAULT_COST*2);
8026 ins_cost(DEFAULT_COST);
8027 size(4);
8028 format %{ "OR $src1,$con,$dst\t! long" %}
8029 opcode(Assembler::or_op3, Assembler::arith_op);
8030 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8031 ins_pipe(ialu_reg_imm);
8032 %}
8034 #ifndef _LP64
8036 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8037 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8038 match(Set dst (OrI src1 (CastP2X src2)));
8040 size(4);
8041 format %{ "OR $src1,$src2,$dst" %}
8042 opcode(Assembler::or_op3, Assembler::arith_op);
8043 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8044 ins_pipe(ialu_reg_reg);
8045 %}
8047 #else
8049 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8050 match(Set dst (OrL src1 (CastP2X src2)));
8052 ins_cost(DEFAULT_COST);
8053 size(4);
8054 format %{ "OR $src1,$src2,$dst\t! long" %}
8055 opcode(Assembler::or_op3, Assembler::arith_op);
8056 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8057 ins_pipe(ialu_reg_reg);
8058 %}
8060 #endif
8062 // Xor Instructions
8063 // Register Xor
8064 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8065 match(Set dst (XorI src1 src2));
8067 size(4);
8068 format %{ "XOR $src1,$src2,$dst" %}
8069 opcode(Assembler::xor_op3, Assembler::arith_op);
8070 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8071 ins_pipe(ialu_reg_reg);
8072 %}
8074 // Immediate Xor
8075 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8076 match(Set dst (XorI src1 src2));
8078 size(4);
8079 format %{ "XOR $src1,$src2,$dst" %}
8080 opcode(Assembler::xor_op3, Assembler::arith_op);
8081 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8082 ins_pipe(ialu_reg_imm);
8083 %}
8085 // Register Xor Long
8086 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8087 match(Set dst (XorL src1 src2));
8089 ins_cost(DEFAULT_COST);
8090 size(4);
8091 format %{ "XOR $src1,$src2,$dst\t! long" %}
8092 opcode(Assembler::xor_op3, Assembler::arith_op);
8093 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8094 ins_pipe(ialu_reg_reg);
8095 %}
8097 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8098 match(Set dst (XorL src1 con));
8100 ins_cost(DEFAULT_COST);
8101 size(4);
8102 format %{ "XOR $src1,$con,$dst\t! long" %}
8103 opcode(Assembler::xor_op3, Assembler::arith_op);
8104 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8105 ins_pipe(ialu_reg_imm);
8106 %}
8108 //----------Convert to Boolean-------------------------------------------------
8109 // Nice hack for 32-bit tests but doesn't work for
8110 // 64-bit pointers.
8111 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8112 match(Set dst (Conv2B src));
8113 effect( KILL ccr );
8114 ins_cost(DEFAULT_COST*2);
8115 format %{ "CMP R_G0,$src\n\t"
8116 "ADDX R_G0,0,$dst" %}
8117 ins_encode( enc_to_bool( src, dst ) );
8118 ins_pipe(ialu_reg_ialu);
8119 %}
8121 #ifndef _LP64
8122 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8123 match(Set dst (Conv2B src));
8124 effect( KILL ccr );
8125 ins_cost(DEFAULT_COST*2);
8126 format %{ "CMP R_G0,$src\n\t"
8127 "ADDX R_G0,0,$dst" %}
8128 ins_encode( enc_to_bool( src, dst ) );
8129 ins_pipe(ialu_reg_ialu);
8130 %}
8131 #else
8132 instruct convP2B( iRegI dst, iRegP src ) %{
8133 match(Set dst (Conv2B src));
8134 ins_cost(DEFAULT_COST*2);
8135 format %{ "MOV $src,$dst\n\t"
8136 "MOVRNZ $src,1,$dst" %}
8137 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8138 ins_pipe(ialu_clr_and_mover);
8139 %}
8140 #endif
8142 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8143 match(Set dst (CmpLTMask src zero));
8144 effect(KILL ccr);
8145 size(4);
8146 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8147 ins_encode %{
8148 __ sra($src$$Register, 31, $dst$$Register);
8149 %}
8150 ins_pipe(ialu_reg_imm);
8151 %}
8153 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8154 match(Set dst (CmpLTMask p q));
8155 effect( KILL ccr );
8156 ins_cost(DEFAULT_COST*4);
8157 format %{ "CMP $p,$q\n\t"
8158 "MOV #0,$dst\n\t"
8159 "BLT,a .+8\n\t"
8160 "MOV #-1,$dst" %}
8161 ins_encode( enc_ltmask(p,q,dst) );
8162 ins_pipe(ialu_reg_reg_ialu);
8163 %}
8165 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8166 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8167 effect(KILL ccr, TEMP tmp);
8168 ins_cost(DEFAULT_COST*3);
8170 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8171 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8172 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8173 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8174 ins_pipe(cadd_cmpltmask);
8175 %}
8177 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8178 match(Set p (AndI (CmpLTMask p q) y));
8179 effect(KILL ccr);
8180 ins_cost(DEFAULT_COST*3);
8182 format %{ "CMP $p,$q\n\t"
8183 "MOV $y,$p\n\t"
8184 "MOVge G0,$p" %}
8185 ins_encode %{
8186 __ cmp($p$$Register, $q$$Register);
8187 __ mov($y$$Register, $p$$Register);
8188 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8189 %}
8190 ins_pipe(ialu_reg_reg_ialu);
8191 %}
8193 //-----------------------------------------------------------------
8194 // Direct raw moves between float and general registers using VIS3.
8196 // ins_pipe(faddF_reg);
8197 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8198 predicate(UseVIS >= 3);
8199 match(Set dst (MoveF2I src));
8201 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8202 ins_encode %{
8203 __ movstouw($src$$FloatRegister, $dst$$Register);
8204 %}
8205 ins_pipe(ialu_reg_reg);
8206 %}
8208 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8209 predicate(UseVIS >= 3);
8210 match(Set dst (MoveI2F src));
8212 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8213 ins_encode %{
8214 __ movwtos($src$$Register, $dst$$FloatRegister);
8215 %}
8216 ins_pipe(ialu_reg_reg);
8217 %}
8219 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8220 predicate(UseVIS >= 3);
8221 match(Set dst (MoveD2L src));
8223 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8224 ins_encode %{
8225 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8226 %}
8227 ins_pipe(ialu_reg_reg);
8228 %}
8230 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8231 predicate(UseVIS >= 3);
8232 match(Set dst (MoveL2D src));
8234 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8235 ins_encode %{
8236 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8237 %}
8238 ins_pipe(ialu_reg_reg);
8239 %}
8242 // Raw moves between float and general registers using stack.
8244 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8245 match(Set dst (MoveF2I src));
8246 effect(DEF dst, USE src);
8247 ins_cost(MEMORY_REF_COST);
8249 size(4);
8250 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8251 opcode(Assembler::lduw_op3);
8252 ins_encode(simple_form3_mem_reg( src, dst ) );
8253 ins_pipe(iload_mem);
8254 %}
8256 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8257 match(Set dst (MoveI2F src));
8258 effect(DEF dst, USE src);
8259 ins_cost(MEMORY_REF_COST);
8261 size(4);
8262 format %{ "LDF $src,$dst\t! MoveI2F" %}
8263 opcode(Assembler::ldf_op3);
8264 ins_encode(simple_form3_mem_reg(src, dst));
8265 ins_pipe(floadF_stk);
8266 %}
8268 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8269 match(Set dst (MoveD2L src));
8270 effect(DEF dst, USE src);
8271 ins_cost(MEMORY_REF_COST);
8273 size(4);
8274 format %{ "LDX $src,$dst\t! MoveD2L" %}
8275 opcode(Assembler::ldx_op3);
8276 ins_encode(simple_form3_mem_reg( src, dst ) );
8277 ins_pipe(iload_mem);
8278 %}
8280 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8281 match(Set dst (MoveL2D src));
8282 effect(DEF dst, USE src);
8283 ins_cost(MEMORY_REF_COST);
8285 size(4);
8286 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8287 opcode(Assembler::lddf_op3);
8288 ins_encode(simple_form3_mem_reg(src, dst));
8289 ins_pipe(floadD_stk);
8290 %}
8292 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8293 match(Set dst (MoveF2I src));
8294 effect(DEF dst, USE src);
8295 ins_cost(MEMORY_REF_COST);
8297 size(4);
8298 format %{ "STF $src,$dst\t! MoveF2I" %}
8299 opcode(Assembler::stf_op3);
8300 ins_encode(simple_form3_mem_reg(dst, src));
8301 ins_pipe(fstoreF_stk_reg);
8302 %}
8304 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8305 match(Set dst (MoveI2F src));
8306 effect(DEF dst, USE src);
8307 ins_cost(MEMORY_REF_COST);
8309 size(4);
8310 format %{ "STW $src,$dst\t! MoveI2F" %}
8311 opcode(Assembler::stw_op3);
8312 ins_encode(simple_form3_mem_reg( dst, src ) );
8313 ins_pipe(istore_mem_reg);
8314 %}
8316 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8317 match(Set dst (MoveD2L src));
8318 effect(DEF dst, USE src);
8319 ins_cost(MEMORY_REF_COST);
8321 size(4);
8322 format %{ "STDF $src,$dst\t! MoveD2L" %}
8323 opcode(Assembler::stdf_op3);
8324 ins_encode(simple_form3_mem_reg(dst, src));
8325 ins_pipe(fstoreD_stk_reg);
8326 %}
8328 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8329 match(Set dst (MoveL2D src));
8330 effect(DEF dst, USE src);
8331 ins_cost(MEMORY_REF_COST);
8333 size(4);
8334 format %{ "STX $src,$dst\t! MoveL2D" %}
8335 opcode(Assembler::stx_op3);
8336 ins_encode(simple_form3_mem_reg( dst, src ) );
8337 ins_pipe(istore_mem_reg);
8338 %}
8341 //----------Arithmetic Conversion Instructions---------------------------------
8342 // The conversions operations are all Alpha sorted. Please keep it that way!
8344 instruct convD2F_reg(regF dst, regD src) %{
8345 match(Set dst (ConvD2F src));
8346 size(4);
8347 format %{ "FDTOS $src,$dst" %}
8348 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8349 ins_encode(form3_opf_rs2D_rdF(src, dst));
8350 ins_pipe(fcvtD2F);
8351 %}
8354 // Convert a double to an int in a float register.
8355 // If the double is a NAN, stuff a zero in instead.
8356 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8357 effect(DEF dst, USE src, KILL fcc0);
8358 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8359 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8360 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8361 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8362 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8363 "skip:" %}
8364 ins_encode(form_d2i_helper(src,dst));
8365 ins_pipe(fcvtD2I);
8366 %}
8368 instruct convD2I_stk(stackSlotI dst, regD src) %{
8369 match(Set dst (ConvD2I src));
8370 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8371 expand %{
8372 regF tmp;
8373 convD2I_helper(tmp, src);
8374 regF_to_stkI(dst, tmp);
8375 %}
8376 %}
8378 instruct convD2I_reg(iRegI dst, regD src) %{
8379 predicate(UseVIS >= 3);
8380 match(Set dst (ConvD2I src));
8381 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8382 expand %{
8383 regF tmp;
8384 convD2I_helper(tmp, src);
8385 MoveF2I_reg_reg(dst, tmp);
8386 %}
8387 %}
8390 // Convert a double to a long in a double register.
8391 // If the double is a NAN, stuff a zero in instead.
8392 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8393 effect(DEF dst, USE src, KILL fcc0);
8394 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8395 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8396 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8397 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8398 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8399 "skip:" %}
8400 ins_encode(form_d2l_helper(src,dst));
8401 ins_pipe(fcvtD2L);
8402 %}
8404 instruct convD2L_stk(stackSlotL dst, regD src) %{
8405 match(Set dst (ConvD2L src));
8406 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8407 expand %{
8408 regD tmp;
8409 convD2L_helper(tmp, src);
8410 regD_to_stkL(dst, tmp);
8411 %}
8412 %}
8414 instruct convD2L_reg(iRegL dst, regD src) %{
8415 predicate(UseVIS >= 3);
8416 match(Set dst (ConvD2L src));
8417 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8418 expand %{
8419 regD tmp;
8420 convD2L_helper(tmp, src);
8421 MoveD2L_reg_reg(dst, tmp);
8422 %}
8423 %}
8426 instruct convF2D_reg(regD dst, regF src) %{
8427 match(Set dst (ConvF2D src));
8428 format %{ "FSTOD $src,$dst" %}
8429 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8430 ins_encode(form3_opf_rs2F_rdD(src, dst));
8431 ins_pipe(fcvtF2D);
8432 %}
8435 // Convert a float to an int in a float register.
8436 // If the float is a NAN, stuff a zero in instead.
8437 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8438 effect(DEF dst, USE src, KILL fcc0);
8439 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8440 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8441 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8442 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8443 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8444 "skip:" %}
8445 ins_encode(form_f2i_helper(src,dst));
8446 ins_pipe(fcvtF2I);
8447 %}
8449 instruct convF2I_stk(stackSlotI dst, regF src) %{
8450 match(Set dst (ConvF2I src));
8451 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8452 expand %{
8453 regF tmp;
8454 convF2I_helper(tmp, src);
8455 regF_to_stkI(dst, tmp);
8456 %}
8457 %}
8459 instruct convF2I_reg(iRegI dst, regF src) %{
8460 predicate(UseVIS >= 3);
8461 match(Set dst (ConvF2I src));
8462 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8463 expand %{
8464 regF tmp;
8465 convF2I_helper(tmp, src);
8466 MoveF2I_reg_reg(dst, tmp);
8467 %}
8468 %}
8471 // Convert a float to a long in a float register.
8472 // If the float is a NAN, stuff a zero in instead.
8473 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8474 effect(DEF dst, USE src, KILL fcc0);
8475 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8476 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8477 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8478 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8479 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8480 "skip:" %}
8481 ins_encode(form_f2l_helper(src,dst));
8482 ins_pipe(fcvtF2L);
8483 %}
8485 instruct convF2L_stk(stackSlotL dst, regF src) %{
8486 match(Set dst (ConvF2L src));
8487 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8488 expand %{
8489 regD tmp;
8490 convF2L_helper(tmp, src);
8491 regD_to_stkL(dst, tmp);
8492 %}
8493 %}
8495 instruct convF2L_reg(iRegL dst, regF src) %{
8496 predicate(UseVIS >= 3);
8497 match(Set dst (ConvF2L src));
8498 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8499 expand %{
8500 regD tmp;
8501 convF2L_helper(tmp, src);
8502 MoveD2L_reg_reg(dst, tmp);
8503 %}
8504 %}
8507 instruct convI2D_helper(regD dst, regF tmp) %{
8508 effect(USE tmp, DEF dst);
8509 format %{ "FITOD $tmp,$dst" %}
8510 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8511 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8512 ins_pipe(fcvtI2D);
8513 %}
8515 instruct convI2D_stk(stackSlotI src, regD dst) %{
8516 match(Set dst (ConvI2D src));
8517 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8518 expand %{
8519 regF tmp;
8520 stkI_to_regF(tmp, src);
8521 convI2D_helper(dst, tmp);
8522 %}
8523 %}
8525 instruct convI2D_reg(regD_low dst, iRegI src) %{
8526 predicate(UseVIS >= 3);
8527 match(Set dst (ConvI2D src));
8528 expand %{
8529 regF tmp;
8530 MoveI2F_reg_reg(tmp, src);
8531 convI2D_helper(dst, tmp);
8532 %}
8533 %}
8535 instruct convI2D_mem(regD_low dst, memory mem) %{
8536 match(Set dst (ConvI2D (LoadI mem)));
8537 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8538 size(8);
8539 format %{ "LDF $mem,$dst\n\t"
8540 "FITOD $dst,$dst" %}
8541 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8542 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8543 ins_pipe(floadF_mem);
8544 %}
8547 instruct convI2F_helper(regF dst, regF tmp) %{
8548 effect(DEF dst, USE tmp);
8549 format %{ "FITOS $tmp,$dst" %}
8550 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8551 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8552 ins_pipe(fcvtI2F);
8553 %}
8555 instruct convI2F_stk(regF dst, stackSlotI src) %{
8556 match(Set dst (ConvI2F src));
8557 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8558 expand %{
8559 regF tmp;
8560 stkI_to_regF(tmp,src);
8561 convI2F_helper(dst, tmp);
8562 %}
8563 %}
8565 instruct convI2F_reg(regF dst, iRegI src) %{
8566 predicate(UseVIS >= 3);
8567 match(Set dst (ConvI2F src));
8568 ins_cost(DEFAULT_COST);
8569 expand %{
8570 regF tmp;
8571 MoveI2F_reg_reg(tmp, src);
8572 convI2F_helper(dst, tmp);
8573 %}
8574 %}
8576 instruct convI2F_mem( regF dst, memory mem ) %{
8577 match(Set dst (ConvI2F (LoadI mem)));
8578 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8579 size(8);
8580 format %{ "LDF $mem,$dst\n\t"
8581 "FITOS $dst,$dst" %}
8582 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8583 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8584 ins_pipe(floadF_mem);
8585 %}
8588 instruct convI2L_reg(iRegL dst, iRegI src) %{
8589 match(Set dst (ConvI2L src));
8590 size(4);
8591 format %{ "SRA $src,0,$dst\t! int->long" %}
8592 opcode(Assembler::sra_op3, Assembler::arith_op);
8593 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8594 ins_pipe(ialu_reg_reg);
8595 %}
8597 // Zero-extend convert int to long
8598 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8599 match(Set dst (AndL (ConvI2L src) mask) );
8600 size(4);
8601 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8602 opcode(Assembler::srl_op3, Assembler::arith_op);
8603 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8604 ins_pipe(ialu_reg_reg);
8605 %}
8607 // Zero-extend long
8608 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8609 match(Set dst (AndL src mask) );
8610 size(4);
8611 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8612 opcode(Assembler::srl_op3, Assembler::arith_op);
8613 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8614 ins_pipe(ialu_reg_reg);
8615 %}
8618 //-----------
8619 // Long to Double conversion using V8 opcodes.
8620 // Still useful because cheetah traps and becomes
8621 // amazingly slow for some common numbers.
8623 // Magic constant, 0x43300000
8624 instruct loadConI_x43300000(iRegI dst) %{
8625 effect(DEF dst);
8626 size(4);
8627 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8628 ins_encode(SetHi22(0x43300000, dst));
8629 ins_pipe(ialu_none);
8630 %}
8632 // Magic constant, 0x41f00000
8633 instruct loadConI_x41f00000(iRegI dst) %{
8634 effect(DEF dst);
8635 size(4);
8636 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8637 ins_encode(SetHi22(0x41f00000, dst));
8638 ins_pipe(ialu_none);
8639 %}
8641 // Construct a double from two float halves
8642 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8643 effect(DEF dst, USE src1, USE src2);
8644 size(8);
8645 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8646 "FMOVS $src2.lo,$dst.lo" %}
8647 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8648 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8649 ins_pipe(faddD_reg_reg);
8650 %}
8652 // Convert integer in high half of a double register (in the lower half of
8653 // the double register file) to double
8654 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8655 effect(DEF dst, USE src);
8656 size(4);
8657 format %{ "FITOD $src,$dst" %}
8658 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8659 ins_encode(form3_opf_rs2D_rdD(src, dst));
8660 ins_pipe(fcvtLHi2D);
8661 %}
8663 // Add float double precision
8664 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8665 effect(DEF dst, USE src1, USE src2);
8666 size(4);
8667 format %{ "FADDD $src1,$src2,$dst" %}
8668 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8669 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8670 ins_pipe(faddD_reg_reg);
8671 %}
8673 // Sub float double precision
8674 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8675 effect(DEF dst, USE src1, USE src2);
8676 size(4);
8677 format %{ "FSUBD $src1,$src2,$dst" %}
8678 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8679 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8680 ins_pipe(faddD_reg_reg);
8681 %}
8683 // Mul float double precision
8684 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8685 effect(DEF dst, USE src1, USE src2);
8686 size(4);
8687 format %{ "FMULD $src1,$src2,$dst" %}
8688 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8689 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8690 ins_pipe(fmulD_reg_reg);
8691 %}
8693 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8694 match(Set dst (ConvL2D src));
8695 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8697 expand %{
8698 regD_low tmpsrc;
8699 iRegI ix43300000;
8700 iRegI ix41f00000;
8701 stackSlotL lx43300000;
8702 stackSlotL lx41f00000;
8703 regD_low dx43300000;
8704 regD dx41f00000;
8705 regD tmp1;
8706 regD_low tmp2;
8707 regD tmp3;
8708 regD tmp4;
8710 stkL_to_regD(tmpsrc, src);
8712 loadConI_x43300000(ix43300000);
8713 loadConI_x41f00000(ix41f00000);
8714 regI_to_stkLHi(lx43300000, ix43300000);
8715 regI_to_stkLHi(lx41f00000, ix41f00000);
8716 stkL_to_regD(dx43300000, lx43300000);
8717 stkL_to_regD(dx41f00000, lx41f00000);
8719 convI2D_regDHi_regD(tmp1, tmpsrc);
8720 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8721 subD_regD_regD(tmp3, tmp2, dx43300000);
8722 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8723 addD_regD_regD(dst, tmp3, tmp4);
8724 %}
8725 %}
8727 // Long to Double conversion using fast fxtof
8728 instruct convL2D_helper(regD dst, regD tmp) %{
8729 effect(DEF dst, USE tmp);
8730 size(4);
8731 format %{ "FXTOD $tmp,$dst" %}
8732 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8733 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8734 ins_pipe(fcvtL2D);
8735 %}
8737 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8738 predicate(VM_Version::has_fast_fxtof());
8739 match(Set dst (ConvL2D src));
8740 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8741 expand %{
8742 regD tmp;
8743 stkL_to_regD(tmp, src);
8744 convL2D_helper(dst, tmp);
8745 %}
8746 %}
8748 instruct convL2D_reg(regD dst, iRegL src) %{
8749 predicate(UseVIS >= 3);
8750 match(Set dst (ConvL2D src));
8751 expand %{
8752 regD tmp;
8753 MoveL2D_reg_reg(tmp, src);
8754 convL2D_helper(dst, tmp);
8755 %}
8756 %}
8758 // Long to Float conversion using fast fxtof
8759 instruct convL2F_helper(regF dst, regD tmp) %{
8760 effect(DEF dst, USE tmp);
8761 size(4);
8762 format %{ "FXTOS $tmp,$dst" %}
8763 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8764 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8765 ins_pipe(fcvtL2F);
8766 %}
8768 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8769 match(Set dst (ConvL2F src));
8770 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8771 expand %{
8772 regD tmp;
8773 stkL_to_regD(tmp, src);
8774 convL2F_helper(dst, tmp);
8775 %}
8776 %}
8778 instruct convL2F_reg(regF dst, iRegL src) %{
8779 predicate(UseVIS >= 3);
8780 match(Set dst (ConvL2F src));
8781 ins_cost(DEFAULT_COST);
8782 expand %{
8783 regD tmp;
8784 MoveL2D_reg_reg(tmp, src);
8785 convL2F_helper(dst, tmp);
8786 %}
8787 %}
8789 //-----------
8791 instruct convL2I_reg(iRegI dst, iRegL src) %{
8792 match(Set dst (ConvL2I src));
8793 #ifndef _LP64
8794 format %{ "MOV $src.lo,$dst\t! long->int" %}
8795 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8796 ins_pipe(ialu_move_reg_I_to_L);
8797 #else
8798 size(4);
8799 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8800 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8801 ins_pipe(ialu_reg);
8802 #endif
8803 %}
8805 // Register Shift Right Immediate
8806 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8807 match(Set dst (ConvL2I (RShiftL src cnt)));
8809 size(4);
8810 format %{ "SRAX $src,$cnt,$dst" %}
8811 opcode(Assembler::srax_op3, Assembler::arith_op);
8812 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8813 ins_pipe(ialu_reg_imm);
8814 %}
8816 //----------Control Flow Instructions------------------------------------------
8817 // Compare Instructions
8818 // Compare Integers
8819 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8820 match(Set icc (CmpI op1 op2));
8821 effect( DEF icc, USE op1, USE op2 );
8823 size(4);
8824 format %{ "CMP $op1,$op2" %}
8825 opcode(Assembler::subcc_op3, Assembler::arith_op);
8826 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8827 ins_pipe(ialu_cconly_reg_reg);
8828 %}
8830 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8831 match(Set icc (CmpU op1 op2));
8833 size(4);
8834 format %{ "CMP $op1,$op2\t! unsigned" %}
8835 opcode(Assembler::subcc_op3, Assembler::arith_op);
8836 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8837 ins_pipe(ialu_cconly_reg_reg);
8838 %}
8840 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8841 match(Set icc (CmpI op1 op2));
8842 effect( DEF icc, USE op1 );
8844 size(4);
8845 format %{ "CMP $op1,$op2" %}
8846 opcode(Assembler::subcc_op3, Assembler::arith_op);
8847 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8848 ins_pipe(ialu_cconly_reg_imm);
8849 %}
8851 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8852 match(Set icc (CmpI (AndI op1 op2) zero));
8854 size(4);
8855 format %{ "BTST $op2,$op1" %}
8856 opcode(Assembler::andcc_op3, Assembler::arith_op);
8857 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8858 ins_pipe(ialu_cconly_reg_reg_zero);
8859 %}
8861 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8862 match(Set icc (CmpI (AndI op1 op2) zero));
8864 size(4);
8865 format %{ "BTST $op2,$op1" %}
8866 opcode(Assembler::andcc_op3, Assembler::arith_op);
8867 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8868 ins_pipe(ialu_cconly_reg_imm_zero);
8869 %}
8871 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8872 match(Set xcc (CmpL op1 op2));
8873 effect( DEF xcc, USE op1, USE op2 );
8875 size(4);
8876 format %{ "CMP $op1,$op2\t\t! long" %}
8877 opcode(Assembler::subcc_op3, Assembler::arith_op);
8878 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8879 ins_pipe(ialu_cconly_reg_reg);
8880 %}
8882 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8883 match(Set xcc (CmpL op1 con));
8884 effect( DEF xcc, USE op1, USE con );
8886 size(4);
8887 format %{ "CMP $op1,$con\t\t! long" %}
8888 opcode(Assembler::subcc_op3, Assembler::arith_op);
8889 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8890 ins_pipe(ialu_cconly_reg_reg);
8891 %}
8893 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8894 match(Set xcc (CmpL (AndL op1 op2) zero));
8895 effect( DEF xcc, USE op1, USE op2 );
8897 size(4);
8898 format %{ "BTST $op1,$op2\t\t! long" %}
8899 opcode(Assembler::andcc_op3, Assembler::arith_op);
8900 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8901 ins_pipe(ialu_cconly_reg_reg);
8902 %}
8904 // useful for checking the alignment of a pointer:
8905 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8906 match(Set xcc (CmpL (AndL op1 con) zero));
8907 effect( DEF xcc, USE op1, USE con );
8909 size(4);
8910 format %{ "BTST $op1,$con\t\t! long" %}
8911 opcode(Assembler::andcc_op3, Assembler::arith_op);
8912 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8913 ins_pipe(ialu_cconly_reg_reg);
8914 %}
8916 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8917 match(Set icc (CmpU op1 op2));
8919 size(4);
8920 format %{ "CMP $op1,$op2\t! unsigned" %}
8921 opcode(Assembler::subcc_op3, Assembler::arith_op);
8922 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8923 ins_pipe(ialu_cconly_reg_imm);
8924 %}
8926 // Compare Pointers
8927 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8928 match(Set pcc (CmpP op1 op2));
8930 size(4);
8931 format %{ "CMP $op1,$op2\t! ptr" %}
8932 opcode(Assembler::subcc_op3, Assembler::arith_op);
8933 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8934 ins_pipe(ialu_cconly_reg_reg);
8935 %}
8937 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8938 match(Set pcc (CmpP op1 op2));
8940 size(4);
8941 format %{ "CMP $op1,$op2\t! ptr" %}
8942 opcode(Assembler::subcc_op3, Assembler::arith_op);
8943 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8944 ins_pipe(ialu_cconly_reg_imm);
8945 %}
8947 // Compare Narrow oops
8948 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8949 match(Set icc (CmpN op1 op2));
8951 size(4);
8952 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8953 opcode(Assembler::subcc_op3, Assembler::arith_op);
8954 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8955 ins_pipe(ialu_cconly_reg_reg);
8956 %}
8958 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8959 match(Set icc (CmpN op1 op2));
8961 size(4);
8962 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8963 opcode(Assembler::subcc_op3, Assembler::arith_op);
8964 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8965 ins_pipe(ialu_cconly_reg_imm);
8966 %}
8968 //----------Max and Min--------------------------------------------------------
8969 // Min Instructions
8970 // Conditional move for min
8971 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8972 effect( USE_DEF op2, USE op1, USE icc );
8974 size(4);
8975 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8976 opcode(Assembler::less);
8977 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8978 ins_pipe(ialu_reg_flags);
8979 %}
8981 // Min Register with Register.
8982 instruct minI_eReg(iRegI op1, iRegI op2) %{
8983 match(Set op2 (MinI op1 op2));
8984 ins_cost(DEFAULT_COST*2);
8985 expand %{
8986 flagsReg icc;
8987 compI_iReg(icc,op1,op2);
8988 cmovI_reg_lt(op2,op1,icc);
8989 %}
8990 %}
8992 // Max Instructions
8993 // Conditional move for max
8994 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8995 effect( USE_DEF op2, USE op1, USE icc );
8996 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8997 opcode(Assembler::greater);
8998 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8999 ins_pipe(ialu_reg_flags);
9000 %}
9002 // Max Register with Register
9003 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9004 match(Set op2 (MaxI op1 op2));
9005 ins_cost(DEFAULT_COST*2);
9006 expand %{
9007 flagsReg icc;
9008 compI_iReg(icc,op1,op2);
9009 cmovI_reg_gt(op2,op1,icc);
9010 %}
9011 %}
9014 //----------Float Compares----------------------------------------------------
9015 // Compare floating, generate condition code
9016 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9017 match(Set fcc (CmpF src1 src2));
9019 size(4);
9020 format %{ "FCMPs $fcc,$src1,$src2" %}
9021 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9022 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9023 ins_pipe(faddF_fcc_reg_reg_zero);
9024 %}
9026 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9027 match(Set fcc (CmpD src1 src2));
9029 size(4);
9030 format %{ "FCMPd $fcc,$src1,$src2" %}
9031 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9032 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9033 ins_pipe(faddD_fcc_reg_reg_zero);
9034 %}
9037 // Compare floating, generate -1,0,1
9038 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9039 match(Set dst (CmpF3 src1 src2));
9040 effect(KILL fcc0);
9041 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9042 format %{ "fcmpl $dst,$src1,$src2" %}
9043 // Primary = float
9044 opcode( true );
9045 ins_encode( floating_cmp( dst, src1, src2 ) );
9046 ins_pipe( floating_cmp );
9047 %}
9049 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9050 match(Set dst (CmpD3 src1 src2));
9051 effect(KILL fcc0);
9052 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9053 format %{ "dcmpl $dst,$src1,$src2" %}
9054 // Primary = double (not float)
9055 opcode( false );
9056 ins_encode( floating_cmp( dst, src1, src2 ) );
9057 ins_pipe( floating_cmp );
9058 %}
9060 //----------Branches---------------------------------------------------------
9061 // Jump
9062 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9063 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9064 match(Jump switch_val);
9065 effect(TEMP table);
9067 ins_cost(350);
9069 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9070 "LD [O7 + $switch_val], O7\n\t"
9071 "JUMP O7" %}
9072 ins_encode %{
9073 // Calculate table address into a register.
9074 Register table_reg;
9075 Register label_reg = O7;
9076 // If we are calculating the size of this instruction don't trust
9077 // zero offsets because they might change when
9078 // MachConstantBaseNode decides to optimize the constant table
9079 // base.
9080 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9081 table_reg = $constanttablebase;
9082 } else {
9083 table_reg = O7;
9084 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9085 __ add($constanttablebase, con_offset, table_reg);
9086 }
9088 // Jump to base address + switch value
9089 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9090 __ jmp(label_reg, G0);
9091 __ delayed()->nop();
9092 %}
9093 ins_pipe(ialu_reg_reg);
9094 %}
9096 // Direct Branch. Use V8 version with longer range.
9097 instruct branch(label labl) %{
9098 match(Goto);
9099 effect(USE labl);
9101 size(8);
9102 ins_cost(BRANCH_COST);
9103 format %{ "BA $labl" %}
9104 ins_encode %{
9105 Label* L = $labl$$label;
9106 __ ba(*L);
9107 __ delayed()->nop();
9108 %}
9109 ins_pipe(br);
9110 %}
9112 // Direct Branch, short with no delay slot
9113 instruct branch_short(label labl) %{
9114 match(Goto);
9115 predicate(UseCBCond);
9116 effect(USE labl);
9118 size(4);
9119 ins_cost(BRANCH_COST);
9120 format %{ "BA $labl\t! short branch" %}
9121 ins_encode %{
9122 Label* L = $labl$$label;
9123 assert(__ use_cbcond(*L), "back to back cbcond");
9124 __ ba_short(*L);
9125 %}
9126 ins_short_branch(1);
9127 ins_avoid_back_to_back(1);
9128 ins_pipe(cbcond_reg_imm);
9129 %}
9131 // Conditional Direct Branch
9132 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9133 match(If cmp icc);
9134 effect(USE labl);
9136 size(8);
9137 ins_cost(BRANCH_COST);
9138 format %{ "BP$cmp $icc,$labl" %}
9139 // Prim = bits 24-22, Secnd = bits 31-30
9140 ins_encode( enc_bp( labl, cmp, icc ) );
9141 ins_pipe(br_cc);
9142 %}
9144 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9145 match(If cmp icc);
9146 effect(USE labl);
9148 ins_cost(BRANCH_COST);
9149 format %{ "BP$cmp $icc,$labl" %}
9150 // Prim = bits 24-22, Secnd = bits 31-30
9151 ins_encode( enc_bp( labl, cmp, icc ) );
9152 ins_pipe(br_cc);
9153 %}
9155 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9156 match(If cmp pcc);
9157 effect(USE labl);
9159 size(8);
9160 ins_cost(BRANCH_COST);
9161 format %{ "BP$cmp $pcc,$labl" %}
9162 ins_encode %{
9163 Label* L = $labl$$label;
9164 Assembler::Predict predict_taken =
9165 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9167 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9168 __ delayed()->nop();
9169 %}
9170 ins_pipe(br_cc);
9171 %}
9173 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9174 match(If cmp fcc);
9175 effect(USE labl);
9177 size(8);
9178 ins_cost(BRANCH_COST);
9179 format %{ "FBP$cmp $fcc,$labl" %}
9180 ins_encode %{
9181 Label* L = $labl$$label;
9182 Assembler::Predict predict_taken =
9183 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9185 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9186 __ delayed()->nop();
9187 %}
9188 ins_pipe(br_fcc);
9189 %}
9191 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9192 match(CountedLoopEnd cmp icc);
9193 effect(USE labl);
9195 size(8);
9196 ins_cost(BRANCH_COST);
9197 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9198 // Prim = bits 24-22, Secnd = bits 31-30
9199 ins_encode( enc_bp( labl, cmp, icc ) );
9200 ins_pipe(br_cc);
9201 %}
9203 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9204 match(CountedLoopEnd cmp icc);
9205 effect(USE labl);
9207 size(8);
9208 ins_cost(BRANCH_COST);
9209 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9210 // Prim = bits 24-22, Secnd = bits 31-30
9211 ins_encode( enc_bp( labl, cmp, icc ) );
9212 ins_pipe(br_cc);
9213 %}
9215 // Compare and branch instructions
9216 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9217 match(If cmp (CmpI op1 op2));
9218 effect(USE labl, KILL icc);
9220 size(12);
9221 ins_cost(BRANCH_COST);
9222 format %{ "CMP $op1,$op2\t! int\n\t"
9223 "BP$cmp $labl" %}
9224 ins_encode %{
9225 Label* L = $labl$$label;
9226 Assembler::Predict predict_taken =
9227 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9228 __ cmp($op1$$Register, $op2$$Register);
9229 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9230 __ delayed()->nop();
9231 %}
9232 ins_pipe(cmp_br_reg_reg);
9233 %}
9235 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9236 match(If cmp (CmpI op1 op2));
9237 effect(USE labl, KILL icc);
9239 size(12);
9240 ins_cost(BRANCH_COST);
9241 format %{ "CMP $op1,$op2\t! int\n\t"
9242 "BP$cmp $labl" %}
9243 ins_encode %{
9244 Label* L = $labl$$label;
9245 Assembler::Predict predict_taken =
9246 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9247 __ cmp($op1$$Register, $op2$$constant);
9248 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9249 __ delayed()->nop();
9250 %}
9251 ins_pipe(cmp_br_reg_imm);
9252 %}
9254 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9255 match(If cmp (CmpU op1 op2));
9256 effect(USE labl, KILL icc);
9258 size(12);
9259 ins_cost(BRANCH_COST);
9260 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9261 "BP$cmp $labl" %}
9262 ins_encode %{
9263 Label* L = $labl$$label;
9264 Assembler::Predict predict_taken =
9265 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9266 __ cmp($op1$$Register, $op2$$Register);
9267 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9268 __ delayed()->nop();
9269 %}
9270 ins_pipe(cmp_br_reg_reg);
9271 %}
9273 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9274 match(If cmp (CmpU op1 op2));
9275 effect(USE labl, KILL icc);
9277 size(12);
9278 ins_cost(BRANCH_COST);
9279 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9280 "BP$cmp $labl" %}
9281 ins_encode %{
9282 Label* L = $labl$$label;
9283 Assembler::Predict predict_taken =
9284 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9285 __ cmp($op1$$Register, $op2$$constant);
9286 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9287 __ delayed()->nop();
9288 %}
9289 ins_pipe(cmp_br_reg_imm);
9290 %}
9292 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9293 match(If cmp (CmpL op1 op2));
9294 effect(USE labl, KILL xcc);
9296 size(12);
9297 ins_cost(BRANCH_COST);
9298 format %{ "CMP $op1,$op2\t! long\n\t"
9299 "BP$cmp $labl" %}
9300 ins_encode %{
9301 Label* L = $labl$$label;
9302 Assembler::Predict predict_taken =
9303 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9304 __ cmp($op1$$Register, $op2$$Register);
9305 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9306 __ delayed()->nop();
9307 %}
9308 ins_pipe(cmp_br_reg_reg);
9309 %}
9311 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9312 match(If cmp (CmpL op1 op2));
9313 effect(USE labl, KILL xcc);
9315 size(12);
9316 ins_cost(BRANCH_COST);
9317 format %{ "CMP $op1,$op2\t! long\n\t"
9318 "BP$cmp $labl" %}
9319 ins_encode %{
9320 Label* L = $labl$$label;
9321 Assembler::Predict predict_taken =
9322 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9323 __ cmp($op1$$Register, $op2$$constant);
9324 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9325 __ delayed()->nop();
9326 %}
9327 ins_pipe(cmp_br_reg_imm);
9328 %}
9330 // Compare Pointers and branch
9331 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9332 match(If cmp (CmpP op1 op2));
9333 effect(USE labl, KILL pcc);
9335 size(12);
9336 ins_cost(BRANCH_COST);
9337 format %{ "CMP $op1,$op2\t! ptr\n\t"
9338 "B$cmp $labl" %}
9339 ins_encode %{
9340 Label* L = $labl$$label;
9341 Assembler::Predict predict_taken =
9342 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9343 __ cmp($op1$$Register, $op2$$Register);
9344 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9345 __ delayed()->nop();
9346 %}
9347 ins_pipe(cmp_br_reg_reg);
9348 %}
9350 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9351 match(If cmp (CmpP op1 null));
9352 effect(USE labl, KILL pcc);
9354 size(12);
9355 ins_cost(BRANCH_COST);
9356 format %{ "CMP $op1,0\t! ptr\n\t"
9357 "B$cmp $labl" %}
9358 ins_encode %{
9359 Label* L = $labl$$label;
9360 Assembler::Predict predict_taken =
9361 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9362 __ cmp($op1$$Register, G0);
9363 // bpr() is not used here since it has shorter distance.
9364 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9365 __ delayed()->nop();
9366 %}
9367 ins_pipe(cmp_br_reg_reg);
9368 %}
9370 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9371 match(If cmp (CmpN op1 op2));
9372 effect(USE labl, KILL icc);
9374 size(12);
9375 ins_cost(BRANCH_COST);
9376 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9377 "BP$cmp $labl" %}
9378 ins_encode %{
9379 Label* L = $labl$$label;
9380 Assembler::Predict predict_taken =
9381 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9382 __ cmp($op1$$Register, $op2$$Register);
9383 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9384 __ delayed()->nop();
9385 %}
9386 ins_pipe(cmp_br_reg_reg);
9387 %}
9389 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9390 match(If cmp (CmpN op1 null));
9391 effect(USE labl, KILL icc);
9393 size(12);
9394 ins_cost(BRANCH_COST);
9395 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9396 "BP$cmp $labl" %}
9397 ins_encode %{
9398 Label* L = $labl$$label;
9399 Assembler::Predict predict_taken =
9400 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9401 __ cmp($op1$$Register, G0);
9402 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9403 __ delayed()->nop();
9404 %}
9405 ins_pipe(cmp_br_reg_reg);
9406 %}
9408 // Loop back branch
9409 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9410 match(CountedLoopEnd cmp (CmpI op1 op2));
9411 effect(USE labl, KILL icc);
9413 size(12);
9414 ins_cost(BRANCH_COST);
9415 format %{ "CMP $op1,$op2\t! int\n\t"
9416 "BP$cmp $labl\t! Loop end" %}
9417 ins_encode %{
9418 Label* L = $labl$$label;
9419 Assembler::Predict predict_taken =
9420 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9421 __ cmp($op1$$Register, $op2$$Register);
9422 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9423 __ delayed()->nop();
9424 %}
9425 ins_pipe(cmp_br_reg_reg);
9426 %}
9428 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9429 match(CountedLoopEnd cmp (CmpI op1 op2));
9430 effect(USE labl, KILL icc);
9432 size(12);
9433 ins_cost(BRANCH_COST);
9434 format %{ "CMP $op1,$op2\t! int\n\t"
9435 "BP$cmp $labl\t! Loop end" %}
9436 ins_encode %{
9437 Label* L = $labl$$label;
9438 Assembler::Predict predict_taken =
9439 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9440 __ cmp($op1$$Register, $op2$$constant);
9441 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9442 __ delayed()->nop();
9443 %}
9444 ins_pipe(cmp_br_reg_imm);
9445 %}
9447 // Short compare and branch instructions
9448 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9449 match(If cmp (CmpI op1 op2));
9450 predicate(UseCBCond);
9451 effect(USE labl, KILL icc);
9453 size(4);
9454 ins_cost(BRANCH_COST);
9455 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9456 ins_encode %{
9457 Label* L = $labl$$label;
9458 assert(__ use_cbcond(*L), "back to back cbcond");
9459 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9460 %}
9461 ins_short_branch(1);
9462 ins_avoid_back_to_back(1);
9463 ins_pipe(cbcond_reg_reg);
9464 %}
9466 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9467 match(If cmp (CmpI op1 op2));
9468 predicate(UseCBCond);
9469 effect(USE labl, KILL icc);
9471 size(4);
9472 ins_cost(BRANCH_COST);
9473 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9474 ins_encode %{
9475 Label* L = $labl$$label;
9476 assert(__ use_cbcond(*L), "back to back cbcond");
9477 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9478 %}
9479 ins_short_branch(1);
9480 ins_avoid_back_to_back(1);
9481 ins_pipe(cbcond_reg_imm);
9482 %}
9484 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9485 match(If cmp (CmpU op1 op2));
9486 predicate(UseCBCond);
9487 effect(USE labl, KILL icc);
9489 size(4);
9490 ins_cost(BRANCH_COST);
9491 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9492 ins_encode %{
9493 Label* L = $labl$$label;
9494 assert(__ use_cbcond(*L), "back to back cbcond");
9495 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9496 %}
9497 ins_short_branch(1);
9498 ins_avoid_back_to_back(1);
9499 ins_pipe(cbcond_reg_reg);
9500 %}
9502 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9503 match(If cmp (CmpU op1 op2));
9504 predicate(UseCBCond);
9505 effect(USE labl, KILL icc);
9507 size(4);
9508 ins_cost(BRANCH_COST);
9509 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9510 ins_encode %{
9511 Label* L = $labl$$label;
9512 assert(__ use_cbcond(*L), "back to back cbcond");
9513 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9514 %}
9515 ins_short_branch(1);
9516 ins_avoid_back_to_back(1);
9517 ins_pipe(cbcond_reg_imm);
9518 %}
9520 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9521 match(If cmp (CmpL op1 op2));
9522 predicate(UseCBCond);
9523 effect(USE labl, KILL xcc);
9525 size(4);
9526 ins_cost(BRANCH_COST);
9527 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9528 ins_encode %{
9529 Label* L = $labl$$label;
9530 assert(__ use_cbcond(*L), "back to back cbcond");
9531 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9532 %}
9533 ins_short_branch(1);
9534 ins_avoid_back_to_back(1);
9535 ins_pipe(cbcond_reg_reg);
9536 %}
9538 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9539 match(If cmp (CmpL op1 op2));
9540 predicate(UseCBCond);
9541 effect(USE labl, KILL xcc);
9543 size(4);
9544 ins_cost(BRANCH_COST);
9545 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9546 ins_encode %{
9547 Label* L = $labl$$label;
9548 assert(__ use_cbcond(*L), "back to back cbcond");
9549 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9550 %}
9551 ins_short_branch(1);
9552 ins_avoid_back_to_back(1);
9553 ins_pipe(cbcond_reg_imm);
9554 %}
9556 // Compare Pointers and branch
9557 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9558 match(If cmp (CmpP op1 op2));
9559 predicate(UseCBCond);
9560 effect(USE labl, KILL pcc);
9562 size(4);
9563 ins_cost(BRANCH_COST);
9564 #ifdef _LP64
9565 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9566 #else
9567 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9568 #endif
9569 ins_encode %{
9570 Label* L = $labl$$label;
9571 assert(__ use_cbcond(*L), "back to back cbcond");
9572 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9573 %}
9574 ins_short_branch(1);
9575 ins_avoid_back_to_back(1);
9576 ins_pipe(cbcond_reg_reg);
9577 %}
9579 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9580 match(If cmp (CmpP op1 null));
9581 predicate(UseCBCond);
9582 effect(USE labl, KILL pcc);
9584 size(4);
9585 ins_cost(BRANCH_COST);
9586 #ifdef _LP64
9587 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9588 #else
9589 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9590 #endif
9591 ins_encode %{
9592 Label* L = $labl$$label;
9593 assert(__ use_cbcond(*L), "back to back cbcond");
9594 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9595 %}
9596 ins_short_branch(1);
9597 ins_avoid_back_to_back(1);
9598 ins_pipe(cbcond_reg_reg);
9599 %}
9601 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9602 match(If cmp (CmpN op1 op2));
9603 predicate(UseCBCond);
9604 effect(USE labl, KILL icc);
9606 size(4);
9607 ins_cost(BRANCH_COST);
9608 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9609 ins_encode %{
9610 Label* L = $labl$$label;
9611 assert(__ use_cbcond(*L), "back to back cbcond");
9612 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9613 %}
9614 ins_short_branch(1);
9615 ins_avoid_back_to_back(1);
9616 ins_pipe(cbcond_reg_reg);
9617 %}
9619 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9620 match(If cmp (CmpN op1 null));
9621 predicate(UseCBCond);
9622 effect(USE labl, KILL icc);
9624 size(4);
9625 ins_cost(BRANCH_COST);
9626 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9627 ins_encode %{
9628 Label* L = $labl$$label;
9629 assert(__ use_cbcond(*L), "back to back cbcond");
9630 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9631 %}
9632 ins_short_branch(1);
9633 ins_avoid_back_to_back(1);
9634 ins_pipe(cbcond_reg_reg);
9635 %}
9637 // Loop back branch
9638 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9639 match(CountedLoopEnd cmp (CmpI op1 op2));
9640 predicate(UseCBCond);
9641 effect(USE labl, KILL icc);
9643 size(4);
9644 ins_cost(BRANCH_COST);
9645 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9646 ins_encode %{
9647 Label* L = $labl$$label;
9648 assert(__ use_cbcond(*L), "back to back cbcond");
9649 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9650 %}
9651 ins_short_branch(1);
9652 ins_avoid_back_to_back(1);
9653 ins_pipe(cbcond_reg_reg);
9654 %}
9656 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9657 match(CountedLoopEnd cmp (CmpI op1 op2));
9658 predicate(UseCBCond);
9659 effect(USE labl, KILL icc);
9661 size(4);
9662 ins_cost(BRANCH_COST);
9663 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9664 ins_encode %{
9665 Label* L = $labl$$label;
9666 assert(__ use_cbcond(*L), "back to back cbcond");
9667 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9668 %}
9669 ins_short_branch(1);
9670 ins_avoid_back_to_back(1);
9671 ins_pipe(cbcond_reg_imm);
9672 %}
9674 // Branch-on-register tests all 64 bits. We assume that values
9675 // in 64-bit registers always remains zero or sign extended
9676 // unless our code munges the high bits. Interrupts can chop
9677 // the high order bits to zero or sign at any time.
9678 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9679 match(If cmp (CmpI op1 zero));
9680 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9681 effect(USE labl);
9683 size(8);
9684 ins_cost(BRANCH_COST);
9685 format %{ "BR$cmp $op1,$labl" %}
9686 ins_encode( enc_bpr( labl, cmp, op1 ) );
9687 ins_pipe(br_reg);
9688 %}
9690 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9691 match(If cmp (CmpP op1 null));
9692 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9693 effect(USE labl);
9695 size(8);
9696 ins_cost(BRANCH_COST);
9697 format %{ "BR$cmp $op1,$labl" %}
9698 ins_encode( enc_bpr( labl, cmp, op1 ) );
9699 ins_pipe(br_reg);
9700 %}
9702 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9703 match(If cmp (CmpL op1 zero));
9704 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9705 effect(USE labl);
9707 size(8);
9708 ins_cost(BRANCH_COST);
9709 format %{ "BR$cmp $op1,$labl" %}
9710 ins_encode( enc_bpr( labl, cmp, op1 ) );
9711 ins_pipe(br_reg);
9712 %}
9715 // ============================================================================
9716 // Long Compare
9717 //
9718 // Currently we hold longs in 2 registers. Comparing such values efficiently
9719 // is tricky. The flavor of compare used depends on whether we are testing
9720 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9721 // The GE test is the negated LT test. The LE test can be had by commuting
9722 // the operands (yielding a GE test) and then negating; negate again for the
9723 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9724 // NE test is negated from that.
9726 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9727 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9728 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9729 // are collapsed internally in the ADLC's dfa-gen code. The match for
9730 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9731 // foo match ends up with the wrong leaf. One fix is to not match both
9732 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9733 // both forms beat the trinary form of long-compare and both are very useful
9734 // on Intel which has so few registers.
9736 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9737 match(If cmp xcc);
9738 effect(USE labl);
9740 size(8);
9741 ins_cost(BRANCH_COST);
9742 format %{ "BP$cmp $xcc,$labl" %}
9743 ins_encode %{
9744 Label* L = $labl$$label;
9745 Assembler::Predict predict_taken =
9746 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9748 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9749 __ delayed()->nop();
9750 %}
9751 ins_pipe(br_cc);
9752 %}
9754 // Manifest a CmpL3 result in an integer register. Very painful.
9755 // This is the test to avoid.
9756 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9757 match(Set dst (CmpL3 src1 src2) );
9758 effect( KILL ccr );
9759 ins_cost(6*DEFAULT_COST);
9760 size(24);
9761 format %{ "CMP $src1,$src2\t\t! long\n"
9762 "\tBLT,a,pn done\n"
9763 "\tMOV -1,$dst\t! delay slot\n"
9764 "\tBGT,a,pn done\n"
9765 "\tMOV 1,$dst\t! delay slot\n"
9766 "\tCLR $dst\n"
9767 "done:" %}
9768 ins_encode( cmpl_flag(src1,src2,dst) );
9769 ins_pipe(cmpL_reg);
9770 %}
9772 // Conditional move
9773 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9774 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9775 ins_cost(150);
9776 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9777 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9778 ins_pipe(ialu_reg);
9779 %}
9781 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9782 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9783 ins_cost(140);
9784 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9785 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9786 ins_pipe(ialu_imm);
9787 %}
9789 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9790 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9791 ins_cost(150);
9792 format %{ "MOV$cmp $xcc,$src,$dst" %}
9793 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9794 ins_pipe(ialu_reg);
9795 %}
9797 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9798 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9799 ins_cost(140);
9800 format %{ "MOV$cmp $xcc,$src,$dst" %}
9801 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9802 ins_pipe(ialu_imm);
9803 %}
9805 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9806 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9807 ins_cost(150);
9808 format %{ "MOV$cmp $xcc,$src,$dst" %}
9809 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9810 ins_pipe(ialu_reg);
9811 %}
9813 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9814 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9815 ins_cost(150);
9816 format %{ "MOV$cmp $xcc,$src,$dst" %}
9817 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9818 ins_pipe(ialu_reg);
9819 %}
9821 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9822 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9823 ins_cost(140);
9824 format %{ "MOV$cmp $xcc,$src,$dst" %}
9825 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9826 ins_pipe(ialu_imm);
9827 %}
9829 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9830 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9831 ins_cost(150);
9832 opcode(0x101);
9833 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9834 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9835 ins_pipe(int_conditional_float_move);
9836 %}
9838 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9839 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9840 ins_cost(150);
9841 opcode(0x102);
9842 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9843 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9844 ins_pipe(int_conditional_float_move);
9845 %}
9847 // ============================================================================
9848 // Safepoint Instruction
9849 instruct safePoint_poll(iRegP poll) %{
9850 match(SafePoint poll);
9851 effect(USE poll);
9853 size(4);
9854 #ifdef _LP64
9855 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9856 #else
9857 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9858 #endif
9859 ins_encode %{
9860 __ relocate(relocInfo::poll_type);
9861 __ ld_ptr($poll$$Register, 0, G0);
9862 %}
9863 ins_pipe(loadPollP);
9864 %}
9866 // ============================================================================
9867 // Call Instructions
9868 // Call Java Static Instruction
9869 instruct CallStaticJavaDirect( method meth ) %{
9870 match(CallStaticJava);
9871 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9872 effect(USE meth);
9874 size(8);
9875 ins_cost(CALL_COST);
9876 format %{ "CALL,static ; NOP ==> " %}
9877 ins_encode( Java_Static_Call( meth ), call_epilog );
9878 ins_pipe(simple_call);
9879 %}
9881 // Call Java Static Instruction (method handle version)
9882 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9883 match(CallStaticJava);
9884 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9885 effect(USE meth, KILL l7_mh_SP_save);
9887 size(16);
9888 ins_cost(CALL_COST);
9889 format %{ "CALL,static/MethodHandle" %}
9890 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9891 ins_pipe(simple_call);
9892 %}
9894 // Call Java Dynamic Instruction
9895 instruct CallDynamicJavaDirect( method meth ) %{
9896 match(CallDynamicJava);
9897 effect(USE meth);
9899 ins_cost(CALL_COST);
9900 format %{ "SET (empty),R_G5\n\t"
9901 "CALL,dynamic ; NOP ==> " %}
9902 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9903 ins_pipe(call);
9904 %}
9906 // Call Runtime Instruction
9907 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9908 match(CallRuntime);
9909 effect(USE meth, KILL l7);
9910 ins_cost(CALL_COST);
9911 format %{ "CALL,runtime" %}
9912 ins_encode( Java_To_Runtime( meth ),
9913 call_epilog, adjust_long_from_native_call );
9914 ins_pipe(simple_call);
9915 %}
9917 // Call runtime without safepoint - same as CallRuntime
9918 instruct CallLeafDirect(method meth, l7RegP l7) %{
9919 match(CallLeaf);
9920 effect(USE meth, KILL l7);
9921 ins_cost(CALL_COST);
9922 format %{ "CALL,runtime leaf" %}
9923 ins_encode( Java_To_Runtime( meth ),
9924 call_epilog,
9925 adjust_long_from_native_call );
9926 ins_pipe(simple_call);
9927 %}
9929 // Call runtime without safepoint - same as CallLeaf
9930 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9931 match(CallLeafNoFP);
9932 effect(USE meth, KILL l7);
9933 ins_cost(CALL_COST);
9934 format %{ "CALL,runtime leaf nofp" %}
9935 ins_encode( Java_To_Runtime( meth ),
9936 call_epilog,
9937 adjust_long_from_native_call );
9938 ins_pipe(simple_call);
9939 %}
9941 // Tail Call; Jump from runtime stub to Java code.
9942 // Also known as an 'interprocedural jump'.
9943 // Target of jump will eventually return to caller.
9944 // TailJump below removes the return address.
9945 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9946 match(TailCall jump_target method_oop );
9948 ins_cost(CALL_COST);
9949 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9950 ins_encode(form_jmpl(jump_target));
9951 ins_pipe(tail_call);
9952 %}
9955 // Return Instruction
9956 instruct Ret() %{
9957 match(Return);
9959 // The epilogue node did the ret already.
9960 size(0);
9961 format %{ "! return" %}
9962 ins_encode();
9963 ins_pipe(empty);
9964 %}
9967 // Tail Jump; remove the return address; jump to target.
9968 // TailCall above leaves the return address around.
9969 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9970 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9971 // "restore" before this instruction (in Epilogue), we need to materialize it
9972 // in %i0.
9973 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9974 match( TailJump jump_target ex_oop );
9975 ins_cost(CALL_COST);
9976 format %{ "! discard R_O7\n\t"
9977 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9978 ins_encode(form_jmpl_set_exception_pc(jump_target));
9979 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9980 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9981 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9982 ins_pipe(tail_call);
9983 %}
9985 // Create exception oop: created by stack-crawling runtime code.
9986 // Created exception is now available to this handler, and is setup
9987 // just prior to jumping to this handler. No code emitted.
9988 instruct CreateException( o0RegP ex_oop )
9989 %{
9990 match(Set ex_oop (CreateEx));
9991 ins_cost(0);
9993 size(0);
9994 // use the following format syntax
9995 format %{ "! exception oop is in R_O0; no code emitted" %}
9996 ins_encode();
9997 ins_pipe(empty);
9998 %}
10001 // Rethrow exception:
10002 // The exception oop will come in the first argument position.
10003 // Then JUMP (not call) to the rethrow stub code.
10004 instruct RethrowException()
10005 %{
10006 match(Rethrow);
10007 ins_cost(CALL_COST);
10009 // use the following format syntax
10010 format %{ "Jmp rethrow_stub" %}
10011 ins_encode(enc_rethrow);
10012 ins_pipe(tail_call);
10013 %}
10016 // Die now
10017 instruct ShouldNotReachHere( )
10018 %{
10019 match(Halt);
10020 ins_cost(CALL_COST);
10022 size(4);
10023 // Use the following format syntax
10024 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10025 ins_encode( form2_illtrap() );
10026 ins_pipe(tail_call);
10027 %}
10029 // ============================================================================
10030 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10031 // array for an instance of the superklass. Set a hidden internal cache on a
10032 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10033 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10034 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10035 match(Set index (PartialSubtypeCheck sub super));
10036 effect( KILL pcc, KILL o7 );
10037 ins_cost(DEFAULT_COST*10);
10038 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10039 ins_encode( enc_PartialSubtypeCheck() );
10040 ins_pipe(partial_subtype_check_pipe);
10041 %}
10043 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10044 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10045 effect( KILL idx, KILL o7 );
10046 ins_cost(DEFAULT_COST*10);
10047 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10048 ins_encode( enc_PartialSubtypeCheck() );
10049 ins_pipe(partial_subtype_check_pipe);
10050 %}
10053 // ============================================================================
10054 // inlined locking and unlocking
10056 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10057 match(Set pcc (FastLock object box));
10059 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10060 ins_cost(100);
10062 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10063 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10064 ins_pipe(long_memory_op);
10065 %}
10068 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10069 match(Set pcc (FastUnlock object box));
10070 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10071 ins_cost(100);
10073 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10074 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10075 ins_pipe(long_memory_op);
10076 %}
10078 // The encodings are generic.
10079 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10080 predicate(!use_block_zeroing(n->in(2)) );
10081 match(Set dummy (ClearArray cnt base));
10082 effect(TEMP temp, KILL ccr);
10083 ins_cost(300);
10084 format %{ "MOV $cnt,$temp\n"
10085 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10086 " BRge loop\t\t! Clearing loop\n"
10087 " STX G0,[$base+$temp]\t! delay slot" %}
10089 ins_encode %{
10090 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10091 Register nof_bytes_arg = $cnt$$Register;
10092 Register nof_bytes_tmp = $temp$$Register;
10093 Register base_pointer_arg = $base$$Register;
10095 Label loop;
10096 __ mov(nof_bytes_arg, nof_bytes_tmp);
10098 // Loop and clear, walking backwards through the array.
10099 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10100 __ bind(loop);
10101 __ deccc(nof_bytes_tmp, 8);
10102 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10103 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10104 // %%%% this mini-loop must not cross a cache boundary!
10105 %}
10106 ins_pipe(long_memory_op);
10107 %}
10109 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10110 predicate(use_block_zeroing(n->in(2)));
10111 match(Set dummy (ClearArray cnt base));
10112 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10113 ins_cost(300);
10114 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10116 ins_encode %{
10118 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10119 Register to = $base$$Register;
10120 Register count = $cnt$$Register;
10122 Label Ldone;
10123 __ nop(); // Separate short branches
10124 // Use BIS for zeroing (temp is not used).
10125 __ bis_zeroing(to, count, G0, Ldone);
10126 __ bind(Ldone);
10128 %}
10129 ins_pipe(long_memory_op);
10130 %}
10132 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10133 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10134 match(Set dummy (ClearArray cnt base));
10135 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10136 ins_cost(300);
10137 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10139 ins_encode %{
10141 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10142 Register to = $base$$Register;
10143 Register count = $cnt$$Register;
10144 Register temp = $tmp$$Register;
10146 Label Ldone;
10147 __ nop(); // Separate short branches
10148 // Use BIS for zeroing
10149 __ bis_zeroing(to, count, temp, Ldone);
10150 __ bind(Ldone);
10152 %}
10153 ins_pipe(long_memory_op);
10154 %}
10156 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10157 o7RegI tmp, flagsReg ccr) %{
10158 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10159 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10160 ins_cost(300);
10161 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10162 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10163 ins_pipe(long_memory_op);
10164 %}
10166 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10167 o7RegI tmp, flagsReg ccr) %{
10168 match(Set result (StrEquals (Binary str1 str2) cnt));
10169 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10170 ins_cost(300);
10171 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10172 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10173 ins_pipe(long_memory_op);
10174 %}
10176 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10177 o7RegI tmp2, flagsReg ccr) %{
10178 match(Set result (AryEq ary1 ary2));
10179 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10180 ins_cost(300);
10181 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10182 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10183 ins_pipe(long_memory_op);
10184 %}
10187 //---------- Zeros Count Instructions ------------------------------------------
10189 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10190 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10191 match(Set dst (CountLeadingZerosI src));
10192 effect(TEMP dst, TEMP tmp, KILL cr);
10194 // x |= (x >> 1);
10195 // x |= (x >> 2);
10196 // x |= (x >> 4);
10197 // x |= (x >> 8);
10198 // x |= (x >> 16);
10199 // return (WORDBITS - popc(x));
10200 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10201 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10202 "OR $dst,$tmp,$dst\n\t"
10203 "SRL $dst,2,$tmp\n\t"
10204 "OR $dst,$tmp,$dst\n\t"
10205 "SRL $dst,4,$tmp\n\t"
10206 "OR $dst,$tmp,$dst\n\t"
10207 "SRL $dst,8,$tmp\n\t"
10208 "OR $dst,$tmp,$dst\n\t"
10209 "SRL $dst,16,$tmp\n\t"
10210 "OR $dst,$tmp,$dst\n\t"
10211 "POPC $dst,$dst\n\t"
10212 "MOV 32,$tmp\n\t"
10213 "SUB $tmp,$dst,$dst" %}
10214 ins_encode %{
10215 Register Rdst = $dst$$Register;
10216 Register Rsrc = $src$$Register;
10217 Register Rtmp = $tmp$$Register;
10218 __ srl(Rsrc, 1, Rtmp);
10219 __ srl(Rsrc, 0, Rdst);
10220 __ or3(Rdst, Rtmp, Rdst);
10221 __ srl(Rdst, 2, Rtmp);
10222 __ or3(Rdst, Rtmp, Rdst);
10223 __ srl(Rdst, 4, Rtmp);
10224 __ or3(Rdst, Rtmp, Rdst);
10225 __ srl(Rdst, 8, Rtmp);
10226 __ or3(Rdst, Rtmp, Rdst);
10227 __ srl(Rdst, 16, Rtmp);
10228 __ or3(Rdst, Rtmp, Rdst);
10229 __ popc(Rdst, Rdst);
10230 __ mov(BitsPerInt, Rtmp);
10231 __ sub(Rtmp, Rdst, Rdst);
10232 %}
10233 ins_pipe(ialu_reg);
10234 %}
10236 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10237 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10238 match(Set dst (CountLeadingZerosL src));
10239 effect(TEMP dst, TEMP tmp, KILL cr);
10241 // x |= (x >> 1);
10242 // x |= (x >> 2);
10243 // x |= (x >> 4);
10244 // x |= (x >> 8);
10245 // x |= (x >> 16);
10246 // x |= (x >> 32);
10247 // return (WORDBITS - popc(x));
10248 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10249 "OR $src,$tmp,$dst\n\t"
10250 "SRLX $dst,2,$tmp\n\t"
10251 "OR $dst,$tmp,$dst\n\t"
10252 "SRLX $dst,4,$tmp\n\t"
10253 "OR $dst,$tmp,$dst\n\t"
10254 "SRLX $dst,8,$tmp\n\t"
10255 "OR $dst,$tmp,$dst\n\t"
10256 "SRLX $dst,16,$tmp\n\t"
10257 "OR $dst,$tmp,$dst\n\t"
10258 "SRLX $dst,32,$tmp\n\t"
10259 "OR $dst,$tmp,$dst\n\t"
10260 "POPC $dst,$dst\n\t"
10261 "MOV 64,$tmp\n\t"
10262 "SUB $tmp,$dst,$dst" %}
10263 ins_encode %{
10264 Register Rdst = $dst$$Register;
10265 Register Rsrc = $src$$Register;
10266 Register Rtmp = $tmp$$Register;
10267 __ srlx(Rsrc, 1, Rtmp);
10268 __ or3( Rsrc, Rtmp, Rdst);
10269 __ srlx(Rdst, 2, Rtmp);
10270 __ or3( Rdst, Rtmp, Rdst);
10271 __ srlx(Rdst, 4, Rtmp);
10272 __ or3( Rdst, Rtmp, Rdst);
10273 __ srlx(Rdst, 8, Rtmp);
10274 __ or3( Rdst, Rtmp, Rdst);
10275 __ srlx(Rdst, 16, Rtmp);
10276 __ or3( Rdst, Rtmp, Rdst);
10277 __ srlx(Rdst, 32, Rtmp);
10278 __ or3( Rdst, Rtmp, Rdst);
10279 __ popc(Rdst, Rdst);
10280 __ mov(BitsPerLong, Rtmp);
10281 __ sub(Rtmp, Rdst, Rdst);
10282 %}
10283 ins_pipe(ialu_reg);
10284 %}
10286 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10287 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10288 match(Set dst (CountTrailingZerosI src));
10289 effect(TEMP dst, KILL cr);
10291 // return popc(~x & (x - 1));
10292 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10293 "ANDN $dst,$src,$dst\n\t"
10294 "SRL $dst,R_G0,$dst\n\t"
10295 "POPC $dst,$dst" %}
10296 ins_encode %{
10297 Register Rdst = $dst$$Register;
10298 Register Rsrc = $src$$Register;
10299 __ sub(Rsrc, 1, Rdst);
10300 __ andn(Rdst, Rsrc, Rdst);
10301 __ srl(Rdst, G0, Rdst);
10302 __ popc(Rdst, Rdst);
10303 %}
10304 ins_pipe(ialu_reg);
10305 %}
10307 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10308 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10309 match(Set dst (CountTrailingZerosL src));
10310 effect(TEMP dst, KILL cr);
10312 // return popc(~x & (x - 1));
10313 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10314 "ANDN $dst,$src,$dst\n\t"
10315 "POPC $dst,$dst" %}
10316 ins_encode %{
10317 Register Rdst = $dst$$Register;
10318 Register Rsrc = $src$$Register;
10319 __ sub(Rsrc, 1, Rdst);
10320 __ andn(Rdst, Rsrc, Rdst);
10321 __ popc(Rdst, Rdst);
10322 %}
10323 ins_pipe(ialu_reg);
10324 %}
10327 //---------- Population Count Instructions -------------------------------------
10329 instruct popCountI(iRegIsafe dst, iRegI src) %{
10330 predicate(UsePopCountInstruction);
10331 match(Set dst (PopCountI src));
10333 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10334 "POPC $dst, $dst" %}
10335 ins_encode %{
10336 __ srl($src$$Register, G0, $dst$$Register);
10337 __ popc($dst$$Register, $dst$$Register);
10338 %}
10339 ins_pipe(ialu_reg);
10340 %}
10342 // Note: Long.bitCount(long) returns an int.
10343 instruct popCountL(iRegIsafe dst, iRegL src) %{
10344 predicate(UsePopCountInstruction);
10345 match(Set dst (PopCountL src));
10347 format %{ "POPC $src, $dst" %}
10348 ins_encode %{
10349 __ popc($src$$Register, $dst$$Register);
10350 %}
10351 ins_pipe(ialu_reg);
10352 %}
10355 // ============================================================================
10356 //------------Bytes reverse--------------------------------------------------
10358 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10359 match(Set dst (ReverseBytesI src));
10361 // Op cost is artificially doubled to make sure that load or store
10362 // instructions are preferred over this one which requires a spill
10363 // onto a stack slot.
10364 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10365 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10367 ins_encode %{
10368 __ set($src$$disp + STACK_BIAS, O7);
10369 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10370 %}
10371 ins_pipe( iload_mem );
10372 %}
10374 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10375 match(Set dst (ReverseBytesL src));
10377 // Op cost is artificially doubled to make sure that load or store
10378 // instructions are preferred over this one which requires a spill
10379 // onto a stack slot.
10380 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10381 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10383 ins_encode %{
10384 __ set($src$$disp + STACK_BIAS, O7);
10385 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10386 %}
10387 ins_pipe( iload_mem );
10388 %}
10390 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10391 match(Set dst (ReverseBytesUS src));
10393 // Op cost is artificially doubled to make sure that load or store
10394 // instructions are preferred over this one which requires a spill
10395 // onto a stack slot.
10396 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10397 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10399 ins_encode %{
10400 // the value was spilled as an int so bias the load
10401 __ set($src$$disp + STACK_BIAS + 2, O7);
10402 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10403 %}
10404 ins_pipe( iload_mem );
10405 %}
10407 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10408 match(Set dst (ReverseBytesS src));
10410 // Op cost is artificially doubled to make sure that load or store
10411 // instructions are preferred over this one which requires a spill
10412 // onto a stack slot.
10413 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10414 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10416 ins_encode %{
10417 // the value was spilled as an int so bias the load
10418 __ set($src$$disp + STACK_BIAS + 2, O7);
10419 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10420 %}
10421 ins_pipe( iload_mem );
10422 %}
10424 // Load Integer reversed byte order
10425 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10426 match(Set dst (ReverseBytesI (LoadI src)));
10428 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10429 size(4);
10430 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10432 ins_encode %{
10433 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10434 %}
10435 ins_pipe(iload_mem);
10436 %}
10438 // Load Long - aligned and reversed
10439 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10440 match(Set dst (ReverseBytesL (LoadL src)));
10442 ins_cost(MEMORY_REF_COST);
10443 size(4);
10444 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10446 ins_encode %{
10447 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10448 %}
10449 ins_pipe(iload_mem);
10450 %}
10452 // Load unsigned short / char reversed byte order
10453 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10454 match(Set dst (ReverseBytesUS (LoadUS src)));
10456 ins_cost(MEMORY_REF_COST);
10457 size(4);
10458 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10460 ins_encode %{
10461 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10462 %}
10463 ins_pipe(iload_mem);
10464 %}
10466 // Load short reversed byte order
10467 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10468 match(Set dst (ReverseBytesS (LoadS src)));
10470 ins_cost(MEMORY_REF_COST);
10471 size(4);
10472 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10474 ins_encode %{
10475 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10476 %}
10477 ins_pipe(iload_mem);
10478 %}
10480 // Store Integer reversed byte order
10481 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10482 match(Set dst (StoreI dst (ReverseBytesI src)));
10484 ins_cost(MEMORY_REF_COST);
10485 size(4);
10486 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10488 ins_encode %{
10489 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10490 %}
10491 ins_pipe(istore_mem_reg);
10492 %}
10494 // Store Long reversed byte order
10495 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10496 match(Set dst (StoreL dst (ReverseBytesL src)));
10498 ins_cost(MEMORY_REF_COST);
10499 size(4);
10500 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10502 ins_encode %{
10503 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10504 %}
10505 ins_pipe(istore_mem_reg);
10506 %}
10508 // Store unsighed short/char reversed byte order
10509 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10510 match(Set dst (StoreC dst (ReverseBytesUS src)));
10512 ins_cost(MEMORY_REF_COST);
10513 size(4);
10514 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10516 ins_encode %{
10517 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10518 %}
10519 ins_pipe(istore_mem_reg);
10520 %}
10522 // Store short reversed byte order
10523 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10524 match(Set dst (StoreC dst (ReverseBytesS src)));
10526 ins_cost(MEMORY_REF_COST);
10527 size(4);
10528 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10530 ins_encode %{
10531 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10532 %}
10533 ins_pipe(istore_mem_reg);
10534 %}
10536 // ====================VECTOR INSTRUCTIONS=====================================
10538 // Load Aligned Packed values into a Double Register
10539 instruct loadV8(regD dst, memory mem) %{
10540 predicate(n->as_LoadVector()->memory_size() == 8);
10541 match(Set dst (LoadVector mem));
10542 ins_cost(MEMORY_REF_COST);
10543 size(4);
10544 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10545 ins_encode %{
10546 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10547 %}
10548 ins_pipe(floadD_mem);
10549 %}
10551 // Store Vector in Double register to memory
10552 instruct storeV8(memory mem, regD src) %{
10553 predicate(n->as_StoreVector()->memory_size() == 8);
10554 match(Set mem (StoreVector mem src));
10555 ins_cost(MEMORY_REF_COST);
10556 size(4);
10557 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10558 ins_encode %{
10559 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10560 %}
10561 ins_pipe(fstoreD_mem_reg);
10562 %}
10564 // Store Zero into vector in memory
10565 instruct storeV8B_zero(memory mem, immI0 zero) %{
10566 predicate(n->as_StoreVector()->memory_size() == 8);
10567 match(Set mem (StoreVector mem (ReplicateB zero)));
10568 ins_cost(MEMORY_REF_COST);
10569 size(4);
10570 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10571 ins_encode %{
10572 __ stx(G0, $mem$$Address);
10573 %}
10574 ins_pipe(fstoreD_mem_zero);
10575 %}
10577 instruct storeV4S_zero(memory mem, immI0 zero) %{
10578 predicate(n->as_StoreVector()->memory_size() == 8);
10579 match(Set mem (StoreVector mem (ReplicateS zero)));
10580 ins_cost(MEMORY_REF_COST);
10581 size(4);
10582 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10583 ins_encode %{
10584 __ stx(G0, $mem$$Address);
10585 %}
10586 ins_pipe(fstoreD_mem_zero);
10587 %}
10589 instruct storeV2I_zero(memory mem, immI0 zero) %{
10590 predicate(n->as_StoreVector()->memory_size() == 8);
10591 match(Set mem (StoreVector mem (ReplicateI zero)));
10592 ins_cost(MEMORY_REF_COST);
10593 size(4);
10594 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10595 ins_encode %{
10596 __ stx(G0, $mem$$Address);
10597 %}
10598 ins_pipe(fstoreD_mem_zero);
10599 %}
10601 instruct storeV2F_zero(memory mem, immF0 zero) %{
10602 predicate(n->as_StoreVector()->memory_size() == 8);
10603 match(Set mem (StoreVector mem (ReplicateF zero)));
10604 ins_cost(MEMORY_REF_COST);
10605 size(4);
10606 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10607 ins_encode %{
10608 __ stx(G0, $mem$$Address);
10609 %}
10610 ins_pipe(fstoreD_mem_zero);
10611 %}
10613 // Replicate scalar to packed byte values into Double register
10614 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10615 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10616 match(Set dst (ReplicateB src));
10617 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10618 format %{ "SLLX $src,56,$tmp\n\t"
10619 "SRLX $tmp, 8,$tmp2\n\t"
10620 "OR $tmp,$tmp2,$tmp\n\t"
10621 "SRLX $tmp,16,$tmp2\n\t"
10622 "OR $tmp,$tmp2,$tmp\n\t"
10623 "SRLX $tmp,32,$tmp2\n\t"
10624 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10625 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10626 ins_encode %{
10627 Register Rsrc = $src$$Register;
10628 Register Rtmp = $tmp$$Register;
10629 Register Rtmp2 = $tmp2$$Register;
10630 __ sllx(Rsrc, 56, Rtmp);
10631 __ srlx(Rtmp, 8, Rtmp2);
10632 __ or3 (Rtmp, Rtmp2, Rtmp);
10633 __ srlx(Rtmp, 16, Rtmp2);
10634 __ or3 (Rtmp, Rtmp2, Rtmp);
10635 __ srlx(Rtmp, 32, Rtmp2);
10636 __ or3 (Rtmp, Rtmp2, Rtmp);
10637 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10638 %}
10639 ins_pipe(ialu_reg);
10640 %}
10642 // Replicate scalar to packed byte values into Double stack
10643 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10644 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10645 match(Set dst (ReplicateB src));
10646 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10647 format %{ "SLLX $src,56,$tmp\n\t"
10648 "SRLX $tmp, 8,$tmp2\n\t"
10649 "OR $tmp,$tmp2,$tmp\n\t"
10650 "SRLX $tmp,16,$tmp2\n\t"
10651 "OR $tmp,$tmp2,$tmp\n\t"
10652 "SRLX $tmp,32,$tmp2\n\t"
10653 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10654 "STX $tmp,$dst\t! regL to stkD" %}
10655 ins_encode %{
10656 Register Rsrc = $src$$Register;
10657 Register Rtmp = $tmp$$Register;
10658 Register Rtmp2 = $tmp2$$Register;
10659 __ sllx(Rsrc, 56, Rtmp);
10660 __ srlx(Rtmp, 8, Rtmp2);
10661 __ or3 (Rtmp, Rtmp2, Rtmp);
10662 __ srlx(Rtmp, 16, Rtmp2);
10663 __ or3 (Rtmp, Rtmp2, Rtmp);
10664 __ srlx(Rtmp, 32, Rtmp2);
10665 __ or3 (Rtmp, Rtmp2, Rtmp);
10666 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10667 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10668 %}
10669 ins_pipe(ialu_reg);
10670 %}
10672 // Replicate scalar constant to packed byte values in Double register
10673 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10674 predicate(n->as_Vector()->length() == 8);
10675 match(Set dst (ReplicateB con));
10676 effect(KILL tmp);
10677 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10678 ins_encode %{
10679 // XXX This is a quick fix for 6833573.
10680 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10681 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10682 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10683 %}
10684 ins_pipe(loadConFD);
10685 %}
10687 // Replicate scalar to packed char/short values into Double register
10688 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10689 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10690 match(Set dst (ReplicateS src));
10691 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10692 format %{ "SLLX $src,48,$tmp\n\t"
10693 "SRLX $tmp,16,$tmp2\n\t"
10694 "OR $tmp,$tmp2,$tmp\n\t"
10695 "SRLX $tmp,32,$tmp2\n\t"
10696 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10697 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10698 ins_encode %{
10699 Register Rsrc = $src$$Register;
10700 Register Rtmp = $tmp$$Register;
10701 Register Rtmp2 = $tmp2$$Register;
10702 __ sllx(Rsrc, 48, Rtmp);
10703 __ srlx(Rtmp, 16, Rtmp2);
10704 __ or3 (Rtmp, Rtmp2, Rtmp);
10705 __ srlx(Rtmp, 32, Rtmp2);
10706 __ or3 (Rtmp, Rtmp2, Rtmp);
10707 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10708 %}
10709 ins_pipe(ialu_reg);
10710 %}
10712 // Replicate scalar to packed char/short values into Double stack
10713 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10714 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10715 match(Set dst (ReplicateS src));
10716 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10717 format %{ "SLLX $src,48,$tmp\n\t"
10718 "SRLX $tmp,16,$tmp2\n\t"
10719 "OR $tmp,$tmp2,$tmp\n\t"
10720 "SRLX $tmp,32,$tmp2\n\t"
10721 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10722 "STX $tmp,$dst\t! regL to stkD" %}
10723 ins_encode %{
10724 Register Rsrc = $src$$Register;
10725 Register Rtmp = $tmp$$Register;
10726 Register Rtmp2 = $tmp2$$Register;
10727 __ sllx(Rsrc, 48, Rtmp);
10728 __ srlx(Rtmp, 16, Rtmp2);
10729 __ or3 (Rtmp, Rtmp2, Rtmp);
10730 __ srlx(Rtmp, 32, Rtmp2);
10731 __ or3 (Rtmp, Rtmp2, Rtmp);
10732 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10733 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10734 %}
10735 ins_pipe(ialu_reg);
10736 %}
10738 // Replicate scalar constant to packed char/short values in Double register
10739 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10740 predicate(n->as_Vector()->length() == 4);
10741 match(Set dst (ReplicateS con));
10742 effect(KILL tmp);
10743 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10744 ins_encode %{
10745 // XXX This is a quick fix for 6833573.
10746 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10747 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10748 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10749 %}
10750 ins_pipe(loadConFD);
10751 %}
10753 // Replicate scalar to packed int values into Double register
10754 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10755 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10756 match(Set dst (ReplicateI src));
10757 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10758 format %{ "SLLX $src,32,$tmp\n\t"
10759 "SRLX $tmp,32,$tmp2\n\t"
10760 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10761 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10762 ins_encode %{
10763 Register Rsrc = $src$$Register;
10764 Register Rtmp = $tmp$$Register;
10765 Register Rtmp2 = $tmp2$$Register;
10766 __ sllx(Rsrc, 32, Rtmp);
10767 __ srlx(Rtmp, 32, Rtmp2);
10768 __ or3 (Rtmp, Rtmp2, Rtmp);
10769 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10770 %}
10771 ins_pipe(ialu_reg);
10772 %}
10774 // Replicate scalar to packed int values into Double stack
10775 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10776 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10777 match(Set dst (ReplicateI src));
10778 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10779 format %{ "SLLX $src,32,$tmp\n\t"
10780 "SRLX $tmp,32,$tmp2\n\t"
10781 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10782 "STX $tmp,$dst\t! regL to stkD" %}
10783 ins_encode %{
10784 Register Rsrc = $src$$Register;
10785 Register Rtmp = $tmp$$Register;
10786 Register Rtmp2 = $tmp2$$Register;
10787 __ sllx(Rsrc, 32, Rtmp);
10788 __ srlx(Rtmp, 32, Rtmp2);
10789 __ or3 (Rtmp, Rtmp2, Rtmp);
10790 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10791 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10792 %}
10793 ins_pipe(ialu_reg);
10794 %}
10796 // Replicate scalar zero constant to packed int values in Double register
10797 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10798 predicate(n->as_Vector()->length() == 2);
10799 match(Set dst (ReplicateI con));
10800 effect(KILL tmp);
10801 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10802 ins_encode %{
10803 // XXX This is a quick fix for 6833573.
10804 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10805 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10806 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10807 %}
10808 ins_pipe(loadConFD);
10809 %}
10811 // Replicate scalar to packed float values into Double stack
10812 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10813 predicate(n->as_Vector()->length() == 2);
10814 match(Set dst (ReplicateF src));
10815 ins_cost(MEMORY_REF_COST*2);
10816 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10817 "STF $src,$dst.lo" %}
10818 opcode(Assembler::stf_op3);
10819 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10820 ins_pipe(fstoreF_stk_reg);
10821 %}
10823 // Replicate scalar zero constant to packed float values in Double register
10824 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10825 predicate(n->as_Vector()->length() == 2);
10826 match(Set dst (ReplicateF con));
10827 effect(KILL tmp);
10828 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10829 ins_encode %{
10830 // XXX This is a quick fix for 6833573.
10831 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10832 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10833 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10834 %}
10835 ins_pipe(loadConFD);
10836 %}
10838 //----------PEEPHOLE RULES-----------------------------------------------------
10839 // These must follow all instruction definitions as they use the names
10840 // defined in the instructions definitions.
10841 //
10842 // peepmatch ( root_instr_name [preceding_instruction]* );
10843 //
10844 // peepconstraint %{
10845 // (instruction_number.operand_name relational_op instruction_number.operand_name
10846 // [, ...] );
10847 // // instruction numbers are zero-based using left to right order in peepmatch
10848 //
10849 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10850 // // provide an instruction_number.operand_name for each operand that appears
10851 // // in the replacement instruction's match rule
10852 //
10853 // ---------VM FLAGS---------------------------------------------------------
10854 //
10855 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10856 //
10857 // Each peephole rule is given an identifying number starting with zero and
10858 // increasing by one in the order seen by the parser. An individual peephole
10859 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10860 // on the command-line.
10861 //
10862 // ---------CURRENT LIMITATIONS----------------------------------------------
10863 //
10864 // Only match adjacent instructions in same basic block
10865 // Only equality constraints
10866 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10867 // Only one replacement instruction
10868 //
10869 // ---------EXAMPLE----------------------------------------------------------
10870 //
10871 // // pertinent parts of existing instructions in architecture description
10872 // instruct movI(eRegI dst, eRegI src) %{
10873 // match(Set dst (CopyI src));
10874 // %}
10875 //
10876 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10877 // match(Set dst (AddI dst src));
10878 // effect(KILL cr);
10879 // %}
10880 //
10881 // // Change (inc mov) to lea
10882 // peephole %{
10883 // // increment preceeded by register-register move
10884 // peepmatch ( incI_eReg movI );
10885 // // require that the destination register of the increment
10886 // // match the destination register of the move
10887 // peepconstraint ( 0.dst == 1.dst );
10888 // // construct a replacement instruction that sets
10889 // // the destination to ( move's source register + one )
10890 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10891 // %}
10892 //
10894 // // Change load of spilled value to only a spill
10895 // instruct storeI(memory mem, eRegI src) %{
10896 // match(Set mem (StoreI mem src));
10897 // %}
10898 //
10899 // instruct loadI(eRegI dst, memory mem) %{
10900 // match(Set dst (LoadI mem));
10901 // %}
10902 //
10903 // peephole %{
10904 // peepmatch ( loadI storeI );
10905 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10906 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10907 // %}
10909 //----------SMARTSPILL RULES---------------------------------------------------
10910 // These must follow all instruction definitions as they use the names
10911 // defined in the instructions definitions.
10912 //
10913 // SPARC will probably not have any of these rules due to RISC instruction set.
10915 //----------PIPELINE-----------------------------------------------------------
10916 // Rules which define the behavior of the target architectures pipeline.