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src/cpu/ppc/vm/vm_version_ppc.cpp@758c07667682
src/cpu/ppc/vm/vm_version_ppc.cpp
Tue, 04 Feb 2020 18:13:14 +0800
- author
- aoqi
- date
- Tue, 04 Feb 2020 18:13:14 +0800
- changeset 9806
- 758c07667682
- parent 9756
- 2be326848943
- parent 9788
- 44ef77ad417c
- permissions
- -rw-r--r--
Merge
1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2018 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "utilities/defaultStream.hpp"
34 #include "vm_version_ppc.hpp"
35 #ifdef TARGET_OS_FAMILY_aix
36 # include "os_aix.inline.hpp"
37 #endif
38 #ifdef TARGET_OS_FAMILY_linux
39 # include "os_linux.inline.hpp"
40 #endif
42 # include <sys/sysinfo.h>
44 int VM_Version::_features = VM_Version::unknown_m;
45 int VM_Version::_measured_cache_line_size = 128; // default value
46 const char* VM_Version::_features_str = "";
47 bool VM_Version::_is_determine_features_test_running = false;
48 uint64_t VM_Version::_dscr_val = 0;
50 #define MSG(flag) \
51 if (flag && !FLAG_IS_DEFAULT(flag)) \
52 jio_fprintf(defaultStream::error_stream(), \
53 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
54 " -XX:+" #flag " will be disabled!\n");
56 void VM_Version::initialize() {
58 // Test which instructions are supported and measure cache line size.
59 determine_features();
61 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
62 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
63 if (VM_Version::has_lqarx()) {
64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
65 } else if (VM_Version::has_popcntw()) {
66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
67 } else if (VM_Version::has_cmpb()) {
68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
69 } else if (VM_Version::has_popcntb()) {
70 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
71 } else {
72 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
73 }
74 }
75 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
76 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 ||
77 PowerArchitecturePPC64 == 8,
78 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8");
80 // Power 8: Configure Data Stream Control Register.
81 if (PowerArchitecturePPC64 >= 8) {
82 config_dscr();
83 }
85 if (!UseSIGTRAP) {
86 MSG(TrapBasedICMissChecks);
87 MSG(TrapBasedNotEntrantChecks);
88 MSG(TrapBasedNullChecks);
89 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
90 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
91 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
92 }
94 #ifdef COMPILER2
95 if (!UseSIGTRAP) {
96 MSG(TrapBasedRangeChecks);
97 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
98 }
100 // On Power6 test for section size.
101 if (PowerArchitecturePPC64 == 6) {
102 determine_section_size();
103 // TODO: PPC port } else {
104 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
105 }
107 MaxVectorSize = 8;
108 #endif
110 // Create and print feature-string.
111 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
112 jio_snprintf(buf, sizeof(buf),
113 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
114 (has_fsqrt() ? " fsqrt" : ""),
115 (has_isel() ? " isel" : ""),
116 (has_lxarxeh() ? " lxarxeh" : ""),
117 (has_cmpb() ? " cmpb" : ""),
118 //(has_mftgpr()? " mftgpr" : ""),
119 (has_popcntb() ? " popcntb" : ""),
120 (has_popcntw() ? " popcntw" : ""),
121 (has_fcfids() ? " fcfids" : ""),
122 (has_vand() ? " vand" : ""),
123 (has_lqarx() ? " lqarx" : ""),
124 (has_vcipher() ? " aes" : ""),
125 (has_vpmsumb() ? " vpmsumb" : ""),
126 (has_mfdscr() ? " mfdscr" : ""),
127 (has_vsx() ? " vsx" : ""),
128 (has_vshasig() ? " sha" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_str = strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
141 UseSSE = 0; // Only on x86 and x64
143 intx cache_line_size = _measured_cache_line_size;
145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
147 if (AllocatePrefetchStyle == 4) {
148 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
149 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
150 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
151 } else {
152 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
153 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
154 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
155 }
157 assert(AllocatePrefetchLines > 0, "invalid value");
158 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
159 AllocatePrefetchLines = 1; // Conservative value.
160 }
162 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
163 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
164 }
166 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
168 // Implementation does not use any of the vector instructions
169 // available with Power8. Their exploitation is still pending.
170 if (!UseCRC32Intrinsics) {
171 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
172 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
173 }
174 }
176 // The AES intrinsic stubs require AES instruction support.
177 if (has_vcipher()) {
178 if (FLAG_IS_DEFAULT(UseAES)) {
179 UseAES = true;
180 }
181 } else if (UseAES) {
182 if (!FLAG_IS_DEFAULT(UseAES))
183 warning("AES instructions are not available on this CPU");
184 FLAG_SET_DEFAULT(UseAES, false);
185 }
187 if (UseAES && has_vcipher()) {
188 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
189 UseAESIntrinsics = true;
190 }
191 } else if (UseAESIntrinsics) {
192 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
193 warning("AES intrinsics are not available on this CPU");
194 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
195 }
197 if (UseGHASHIntrinsics) {
198 warning("GHASH intrinsics are not available on this CPU");
199 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
200 }
202 if (has_vshasig()) {
203 if (FLAG_IS_DEFAULT(UseSHA)) {
204 UseSHA = true;
205 }
206 } else if (UseSHA) {
207 if (!FLAG_IS_DEFAULT(UseSHA))
208 warning("SHA instructions are not available on this CPU");
209 FLAG_SET_DEFAULT(UseSHA, false);
210 }
212 if (UseSHA1Intrinsics) {
213 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
214 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
215 }
217 if (UseSHA && has_vshasig()) {
218 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
219 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
220 }
221 } else if (UseSHA256Intrinsics) {
222 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
223 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
224 }
226 if (UseSHA && has_vshasig()) {
227 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
228 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
229 }
230 } else if (UseSHA512Intrinsics) {
231 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
232 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
233 }
235 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
236 FLAG_SET_DEFAULT(UseSHA, false);
237 }
239 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
240 UseMontgomeryMultiplyIntrinsic = true;
241 }
242 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
243 UseMontgomerySquareIntrinsic = true;
244 }
245 }
247 void VM_Version::print_features() {
248 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
249 }
251 #ifdef COMPILER2
252 // Determine section size on power6: If section size is 8 instructions,
253 // there should be a difference between the two testloops of ~15 %. If
254 // no difference is detected the section is assumed to be 32 instructions.
255 void VM_Version::determine_section_size() {
257 int unroll = 80;
259 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
261 // Allocate space for the code.
262 ResourceMark rm;
263 CodeBuffer cb("detect_section_size", code_size, 0);
264 MacroAssembler* a = new MacroAssembler(&cb);
266 uint32_t *code = (uint32_t *)a->pc();
267 // Emit code.
268 void (*test1)() = (void(*)())(void *)a->function_entry();
270 Label l1;
272 a->li(R4, 1);
273 a->sldi(R4, R4, 28);
274 a->b(l1);
275 a->align(CodeEntryAlignment);
277 a->bind(l1);
279 for (int i = 0; i < unroll; i++) {
280 // Schleife 1
281 // ------- sector 0 ------------
282 // ;; 0
283 a->nop(); // 1
284 a->fpnop0(); // 2
285 a->fpnop1(); // 3
286 a->addi(R4,R4, -1); // 4
288 // ;; 1
289 a->nop(); // 5
290 a->fmr(F6, F6); // 6
291 a->fmr(F7, F7); // 7
292 a->endgroup(); // 8
293 // ------- sector 8 ------------
295 // ;; 2
296 a->nop(); // 9
297 a->nop(); // 10
298 a->fmr(F8, F8); // 11
299 a->fmr(F9, F9); // 12
301 // ;; 3
302 a->nop(); // 13
303 a->fmr(F10, F10); // 14
304 a->fmr(F11, F11); // 15
305 a->endgroup(); // 16
306 // -------- sector 16 -------------
308 // ;; 4
309 a->nop(); // 17
310 a->nop(); // 18
311 a->fmr(F15, F15); // 19
312 a->fmr(F16, F16); // 20
314 // ;; 5
315 a->nop(); // 21
316 a->fmr(F17, F17); // 22
317 a->fmr(F18, F18); // 23
318 a->endgroup(); // 24
319 // ------- sector 24 ------------
321 // ;; 6
322 a->nop(); // 25
323 a->nop(); // 26
324 a->fmr(F19, F19); // 27
325 a->fmr(F20, F20); // 28
327 // ;; 7
328 a->nop(); // 29
329 a->fmr(F21, F21); // 30
330 a->fmr(F22, F22); // 31
331 a->brnop0(); // 32
333 // ------- sector 32 ------------
334 }
336 // ;; 8
337 a->cmpdi(CCR0, R4, unroll); // 33
338 a->bge(CCR0, l1); // 34
339 a->blr();
341 // Emit code.
342 void (*test2)() = (void(*)())(void *)a->function_entry();
343 // uint32_t *code = (uint32_t *)a->pc();
345 Label l2;
347 a->li(R4, 1);
348 a->sldi(R4, R4, 28);
349 a->b(l2);
350 a->align(CodeEntryAlignment);
352 a->bind(l2);
354 for (int i = 0; i < unroll; i++) {
355 // Schleife 2
356 // ------- sector 0 ------------
357 // ;; 0
358 a->brnop0(); // 1
359 a->nop(); // 2
360 //a->cmpdi(CCR0, R4, unroll);
361 a->fpnop0(); // 3
362 a->fpnop1(); // 4
363 a->addi(R4,R4, -1); // 5
365 // ;; 1
367 a->nop(); // 6
368 a->fmr(F6, F6); // 7
369 a->fmr(F7, F7); // 8
370 // ------- sector 8 ---------------
372 // ;; 2
373 a->endgroup(); // 9
375 // ;; 3
376 a->nop(); // 10
377 a->nop(); // 11
378 a->fmr(F8, F8); // 12
380 // ;; 4
381 a->fmr(F9, F9); // 13
382 a->nop(); // 14
383 a->fmr(F10, F10); // 15
385 // ;; 5
386 a->fmr(F11, F11); // 16
387 // -------- sector 16 -------------
389 // ;; 6
390 a->endgroup(); // 17
392 // ;; 7
393 a->nop(); // 18
394 a->nop(); // 19
395 a->fmr(F15, F15); // 20
397 // ;; 8
398 a->fmr(F16, F16); // 21
399 a->nop(); // 22
400 a->fmr(F17, F17); // 23
402 // ;; 9
403 a->fmr(F18, F18); // 24
404 // -------- sector 24 -------------
406 // ;; 10
407 a->endgroup(); // 25
409 // ;; 11
410 a->nop(); // 26
411 a->nop(); // 27
412 a->fmr(F19, F19); // 28
414 // ;; 12
415 a->fmr(F20, F20); // 29
416 a->nop(); // 30
417 a->fmr(F21, F21); // 31
419 // ;; 13
420 a->fmr(F22, F22); // 32
421 }
423 // -------- sector 32 -------------
424 // ;; 14
425 a->cmpdi(CCR0, R4, unroll); // 33
426 a->bge(CCR0, l2); // 34
428 a->blr();
429 uint32_t *code_end = (uint32_t *)a->pc();
430 a->flush();
432 double loop1_seconds,loop2_seconds, rel_diff;
433 uint64_t start1, stop1;
435 start1 = os::current_thread_cpu_time(false);
436 (*test1)();
437 stop1 = os::current_thread_cpu_time(false);
438 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
441 start1 = os::current_thread_cpu_time(false);
442 (*test2)();
443 stop1 = os::current_thread_cpu_time(false);
445 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
447 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
449 if (PrintAssembly) {
450 ttyLocker ttyl;
451 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
452 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
453 tty->print_cr("Time loop1 :%f", loop1_seconds);
454 tty->print_cr("Time loop2 :%f", loop2_seconds);
455 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
457 if (rel_diff > 12.0) {
458 tty->print_cr("Section Size 8 Instructions");
459 } else{
460 tty->print_cr("Section Size 32 Instructions or Power5");
461 }
462 }
464 #if 0 // TODO: PPC port
465 // Set sector size (if not set explicitly).
466 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
467 if (rel_diff > 12.0) {
468 PdScheduling::power6SectorSize = 0x20;
469 } else {
470 PdScheduling::power6SectorSize = 0x80;
471 }
472 } else if (Power6SectorSize128PPC64) {
473 PdScheduling::power6SectorSize = 0x80;
474 } else {
475 PdScheduling::power6SectorSize = 0x20;
476 }
477 #endif
478 if (UsePower6SchedulerPPC64) Unimplemented();
479 }
480 #endif // COMPILER2
482 void VM_Version::determine_features() {
483 #if defined(ABI_ELFv2)
484 const int code_size = (num_features+1+2*7)*BytesPerInstWord; // TODO(asmundak): calculation is incorrect.
485 #else
486 // 7 InstWords for each call (function descriptor + blr instruction).
487 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
488 #endif
489 int features = 0;
491 // create test area
492 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
493 char test_area[BUFFER_SIZE];
494 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
496 // Allocate space for the code.
497 ResourceMark rm;
498 CodeBuffer cb("detect_cpu_features", code_size, 0);
499 MacroAssembler* a = new MacroAssembler(&cb);
501 // Must be set to true so we can generate the test code.
502 _features = VM_Version::all_features_m;
504 // Emit code.
505 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
506 uint32_t *code = (uint32_t *)a->pc();
507 // Don't use R0 in ldarx.
508 // Keep R3_ARG1 unmodified, it contains &field (see below).
509 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
510 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
511 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
512 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
513 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
514 a->cmpb(R7, R5, R6); // code[4] -> bcmp
515 //a->mftgpr(R7, F3); // code[5] -> mftgpr
516 a->popcntb(R7, R5); // code[6] -> popcntb
517 a->popcntw(R7, R5); // code[7] -> popcntw
518 a->fcfids(F3, F4); // code[8] -> fcfids
519 a->vand(VR0, VR0, VR0); // code[9] -> vand
520 a->lqarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[10] -> lqarx_m
521 a->vcipher(VR0, VR1, VR2); // code[11] -> vcipher
522 a->vpmsumb(VR0, VR1, VR2); // code[12] -> vpmsumb
523 a->mfdscr(R0); // code[13] -> mfdscr
524 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
525 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[15] -> vshasig
526 a->blr();
528 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
529 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
530 a->dcbz(R3_ARG1); // R3_ARG1 = addr
531 a->blr();
533 uint32_t *code_end = (uint32_t *)a->pc();
534 a->flush();
535 _features = VM_Version::unknown_m;
537 // Print the detection code.
538 if (PrintAssembly) {
539 ttyLocker ttyl;
540 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
541 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
542 }
544 // Measure cache line size.
545 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
546 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
547 int count = 0; // count zeroed bytes
548 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
549 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
550 _measured_cache_line_size = count;
552 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
553 VM_Version::_is_determine_features_test_running = true;
554 (*test)((address)mid_of_test_area, (uint64_t)0);
555 VM_Version::_is_determine_features_test_running = false;
557 // determine which instructions are legal.
558 int feature_cntr = 0;
559 if (code[feature_cntr++]) features |= fsqrt_m;
560 if (code[feature_cntr++]) features |= fsqrts_m;
561 if (code[feature_cntr++]) features |= isel_m;
562 if (code[feature_cntr++]) features |= lxarxeh_m;
563 if (code[feature_cntr++]) features |= cmpb_m;
564 //if(code[feature_cntr++])features |= mftgpr_m;
565 if (code[feature_cntr++]) features |= popcntb_m;
566 if (code[feature_cntr++]) features |= popcntw_m;
567 if (code[feature_cntr++]) features |= fcfids_m;
568 if (code[feature_cntr++]) features |= vand_m;
569 if (code[feature_cntr++]) features |= lqarx_m;
570 if (code[feature_cntr++]) features |= vcipher_m;
571 if (code[feature_cntr++]) features |= vpmsumb_m;
572 if (code[feature_cntr++]) features |= mfdscr_m;
573 if (code[feature_cntr++]) features |= vsx_m;
574 if (code[feature_cntr++]) features |= vshasig_m;
576 // Print the detection code.
577 if (PrintAssembly) {
578 ttyLocker ttyl;
579 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
580 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
581 }
583 _features = features;
584 }
586 // Power 8: Configure Data Stream Control Register.
587 void VM_Version::config_dscr() {
588 assert(has_lqarx(), "Only execute on Power 8 or later!");
590 // 7 InstWords for each call (function descriptor + blr instruction).
591 const int code_size = (2+2*7)*BytesPerInstWord;
593 // Allocate space for the code.
594 ResourceMark rm;
595 CodeBuffer cb("config_dscr", code_size, 0);
596 MacroAssembler* a = new MacroAssembler(&cb);
598 // Emit code.
599 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
600 uint32_t *code = (uint32_t *)a->pc();
601 a->mfdscr(R3);
602 a->blr();
604 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
605 a->mtdscr(R3);
606 a->blr();
608 uint32_t *code_end = (uint32_t *)a->pc();
609 a->flush();
611 // Print the detection code.
612 if (PrintAssembly) {
613 ttyLocker ttyl;
614 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
615 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
616 }
618 // Apply the configuration if needed.
619 _dscr_val = (*get_dscr)();
620 if (Verbose) {
621 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
622 }
623 bool change_requested = false;
624 if (DSCR_PPC64 != (uintx)-1) {
625 _dscr_val = DSCR_PPC64;
626 change_requested = true;
627 }
628 if (DSCR_DPFD_PPC64 <= 7) {
629 uint64_t mask = 0x7;
630 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
631 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
632 change_requested = true;
633 }
634 }
635 if (DSCR_URG_PPC64 <= 7) {
636 uint64_t mask = 0x7 << 6;
637 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
638 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
639 change_requested = true;
640 }
641 }
642 if (change_requested) {
643 (*set_dscr)(_dscr_val);
644 if (Verbose) {
645 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
646 }
647 }
648 }
650 static int saved_features = 0;
652 void VM_Version::allow_all() {
653 saved_features = _features;
654 _features = all_features_m;
655 }
657 void VM_Version::revert() {
658 _features = saved_features;
659 }
