src/cpu/ppc/vm/vmreg_ppc.inline.hpp

Wed, 15 Apr 2020 11:49:55 +0800

author
aoqi
date
Wed, 15 Apr 2020 11:49:55 +0800
changeset 9852
70aa912cebe5
parent 0
f90c822e73f8
permissions
-rw-r--r--

Merge

     1 /*
     2  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
     3  * Copyright 2012, 2013 SAP AG. All rights reserved.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5  *
     6  * This code is free software; you can redistribute it and/or modify it
     7  * under the terms of the GNU General Public License version 2 only, as
     8  * published by the Free Software Foundation.
     9  *
    10  * This code is distributed in the hope that it will be useful, but WITHOUT
    11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    13  * version 2 for more details (a copy is included in the LICENSE file that
    14  * accompanied this code).
    15  *
    16  * You should have received a copy of the GNU General Public License version
    17  * 2 along with this work; if not, write to the Free Software Foundation,
    18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    19  *
    20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    21  * or visit www.oracle.com if you need additional information or have any
    22  * questions.
    23  *
    24  */
    26 #ifndef CPU_PPC_VM_VMREG_PPC_INLINE_HPP
    27 #define CPU_PPC_VM_VMREG_PPC_INLINE_HPP
    29 inline VMReg RegisterImpl::as_VMReg() {
    30   if (this == noreg) return VMRegImpl::Bad();
    31   return VMRegImpl::as_VMReg(encoding() << 1);
    32 }
    34 // Since we don't have two halfs here, don't multiply by 2.
    35 inline VMReg ConditionRegisterImpl::as_VMReg() {
    36   return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_fpr);
    37 }
    39 inline VMReg FloatRegisterImpl::as_VMReg() {
    40   return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr);
    41 }
    43 inline VMReg SpecialRegisterImpl::as_VMReg() {
    44   return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_cnd);
    45 }
    47 inline bool VMRegImpl::is_Register() {
    48   return (unsigned int)value() < (unsigned int)ConcreteRegisterImpl::max_gpr;
    49 }
    51 inline bool VMRegImpl::is_FloatRegister() {
    52   return value() >= ConcreteRegisterImpl::max_gpr &&
    53          value() < ConcreteRegisterImpl::max_fpr;
    54 }
    56 inline Register VMRegImpl::as_Register() {
    57   assert(is_Register() && is_even(value()), "even-aligned GPR name");
    58   return ::as_Register(value()>>1);
    59 }
    61 inline FloatRegister VMRegImpl::as_FloatRegister() {
    62   assert(is_FloatRegister() && is_even(value()), "must be");
    63   return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1);
    64 }
    66 inline bool VMRegImpl::is_concrete() {
    67   assert(is_reg(), "must be");
    68   return is_even(value());
    69 }
    71 #endif // CPU_PPC_VM_VMREG_PPC_INLINE_HPP

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