Tue, 28 Jun 2011 15:04:39 -0700
6990015: Incorrect Icache line size is used for 64 bit x86
Summary: correct Icache::line_size for x64 and add verification code into vm_version_x86.
Reviewed-by: never, phh
1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
28 class BiasedLockingCounters;
30 // Contains all the definitions needed for x86 assembly code generation.
32 // Calling convention
33 class Argument VALUE_OBJ_CLASS_SPEC {
34 public:
35 enum {
36 #ifdef _LP64
37 #ifdef _WIN64
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
40 #else
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
43 #endif // _WIN64
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
46 #else
47 n_register_parameters = 0 // 0 registers used to pass arguments
48 #endif // _LP64
49 };
50 };
53 #ifdef _LP64
54 // Symbolically name the register arguments used by the c calling convention.
55 // Windows is different from linux/solaris. So much for standards...
57 #ifdef _WIN64
59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
61 REGISTER_DECLARATION(Register, c_rarg2, r8);
62 REGISTER_DECLARATION(Register, c_rarg3, r9);
64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
69 #else
71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
75 REGISTER_DECLARATION(Register, c_rarg4, r8);
76 REGISTER_DECLARATION(Register, c_rarg5, r9);
78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
87 #endif // _WIN64
89 // Symbolically name the register arguments used by the Java calling convention.
90 // We have control over the convention for java so we can do what we please.
91 // What pleases us is to offset the java calling convention so that when
92 // we call a suitable jni method the arguments are lined up and we don't
93 // have to do little shuffling. A suitable jni method is non-static and a
94 // small number of arguments (two fewer args on windows)
95 //
96 // |-------------------------------------------------------|
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
98 // |-------------------------------------------------------|
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux
101 // |-------------------------------------------------------|
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
103 // |-------------------------------------------------------|
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
108 // Windows runs out of register args here
109 #ifdef _WIN64
110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
112 #else
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
115 #endif /* _WIN64 */
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
133 #else
134 // rscratch1 will apear in 32bit code that is dead but of course must compile
135 // Using noreg ensures if the dead code is incorrectly live and executed it
136 // will cause an assertion failure
137 #define rscratch1 noreg
138 #define rscratch2 noreg
140 #endif // _LP64
142 // JSR 292 fixed register usages:
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
145 // Address is an abstraction used to represent a memory location
146 // using any of the amd64 addressing modes with one object.
147 //
148 // Note: A register location is represented via a Register, not
149 // via an address for efficiency & simplicity reasons.
151 class ArrayAddress;
153 class Address VALUE_OBJ_CLASS_SPEC {
154 public:
155 enum ScaleFactor {
156 no_scale = -1,
157 times_1 = 0,
158 times_2 = 1,
159 times_4 = 2,
160 times_8 = 3,
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
162 };
163 static ScaleFactor times(int size) {
164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
165 if (size == 8) return times_8;
166 if (size == 4) return times_4;
167 if (size == 2) return times_2;
168 return times_1;
169 }
170 static int scale_size(ScaleFactor scale) {
171 assert(scale != no_scale, "");
172 assert(((1 << (int)times_1) == 1 &&
173 (1 << (int)times_2) == 2 &&
174 (1 << (int)times_4) == 4 &&
175 (1 << (int)times_8) == 8), "");
176 return (1 << (int)scale);
177 }
179 private:
180 Register _base;
181 Register _index;
182 ScaleFactor _scale;
183 int _disp;
184 RelocationHolder _rspec;
186 // Easily misused constructors make them private
187 // %%% can we make these go away?
188 NOT_LP64(Address(address loc, RelocationHolder spec);)
189 Address(int disp, address loc, relocInfo::relocType rtype);
190 Address(int disp, address loc, RelocationHolder spec);
192 public:
194 int disp() { return _disp; }
195 // creation
196 Address()
197 : _base(noreg),
198 _index(noreg),
199 _scale(no_scale),
200 _disp(0) {
201 }
203 // No default displacement otherwise Register can be implicitly
204 // converted to 0(Register) which is quite a different animal.
206 Address(Register base, int disp)
207 : _base(base),
208 _index(noreg),
209 _scale(no_scale),
210 _disp(disp) {
211 }
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
214 : _base (base),
215 _index(index),
216 _scale(scale),
217 _disp (disp) {
218 assert(!index->is_valid() == (scale == Address::no_scale),
219 "inconsistent address");
220 }
222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
223 : _base (base),
224 _index(index.register_or_noreg()),
225 _scale(scale),
226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
227 if (!index.is_register()) scale = Address::no_scale;
228 assert(!_index->is_valid() == (scale == Address::no_scale),
229 "inconsistent address");
230 }
232 Address plus_disp(int disp) const {
233 Address a = (*this);
234 a._disp += disp;
235 return a;
236 }
237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
238 Address a = (*this);
239 a._disp += disp.constant_or_zero() * scale_size(scale);
240 if (disp.is_register()) {
241 assert(!a.index()->is_valid(), "competing indexes");
242 a._index = disp.as_register();
243 a._scale = scale;
244 }
245 return a;
246 }
247 bool is_same_address(Address a) const {
248 // disregard _rspec
249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
250 }
252 // The following two overloads are used in connection with the
253 // ByteSize type (see sizes.hpp). They simplify the use of
254 // ByteSize'd arguments in assembly code. Note that their equivalent
255 // for the optimized build are the member functions with int disp
256 // argument since ByteSize is mapped to an int type in that case.
257 //
258 // Note: DO NOT introduce similar overloaded functions for WordSize
259 // arguments as in the optimized mode, both ByteSize and WordSize
260 // are mapped to the same type and thus the compiler cannot make a
261 // distinction anymore (=> compiler errors).
263 #ifdef ASSERT
264 Address(Register base, ByteSize disp)
265 : _base(base),
266 _index(noreg),
267 _scale(no_scale),
268 _disp(in_bytes(disp)) {
269 }
271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
272 : _base(base),
273 _index(index),
274 _scale(scale),
275 _disp(in_bytes(disp)) {
276 assert(!index->is_valid() == (scale == Address::no_scale),
277 "inconsistent address");
278 }
280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
281 : _base (base),
282 _index(index.register_or_noreg()),
283 _scale(scale),
284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
285 if (!index.is_register()) scale = Address::no_scale;
286 assert(!_index->is_valid() == (scale == Address::no_scale),
287 "inconsistent address");
288 }
290 #endif // ASSERT
292 // accessors
293 bool uses(Register reg) const { return _base == reg || _index == reg; }
294 Register base() const { return _base; }
295 Register index() const { return _index; }
296 ScaleFactor scale() const { return _scale; }
297 int disp() const { return _disp; }
299 // Convert the raw encoding form into the form expected by the constructor for
300 // Address. An index of 4 (rsp) corresponds to having no index, so convert
301 // that to noreg for the Address constructor.
302 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
304 static Address make_array(ArrayAddress);
306 private:
307 bool base_needs_rex() const {
308 return _base != noreg && _base->encoding() >= 8;
309 }
311 bool index_needs_rex() const {
312 return _index != noreg &&_index->encoding() >= 8;
313 }
315 relocInfo::relocType reloc() const { return _rspec.type(); }
317 friend class Assembler;
318 friend class MacroAssembler;
319 friend class LIR_Assembler; // base/index/scale/disp
320 };
322 //
323 // AddressLiteral has been split out from Address because operands of this type
324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
325 // the few instructions that need to deal with address literals are unique and the
326 // MacroAssembler does not have to implement every instruction in the Assembler
327 // in order to search for address literals that may need special handling depending
328 // on the instruction and the platform. As small step on the way to merging i486/amd64
329 // directories.
330 //
331 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
332 friend class ArrayAddress;
333 RelocationHolder _rspec;
334 // Typically we use AddressLiterals we want to use their rval
335 // However in some situations we want the lval (effect address) of the item.
336 // We provide a special factory for making those lvals.
337 bool _is_lval;
339 // If the target is far we'll need to load the ea of this to
340 // a register to reach it. Otherwise if near we can do rip
341 // relative addressing.
343 address _target;
345 protected:
346 // creation
347 AddressLiteral()
348 : _is_lval(false),
349 _target(NULL)
350 {}
352 public:
355 AddressLiteral(address target, relocInfo::relocType rtype);
357 AddressLiteral(address target, RelocationHolder const& rspec)
358 : _rspec(rspec),
359 _is_lval(false),
360 _target(target)
361 {}
363 AddressLiteral addr() {
364 AddressLiteral ret = *this;
365 ret._is_lval = true;
366 return ret;
367 }
370 private:
372 address target() { return _target; }
373 bool is_lval() { return _is_lval; }
375 relocInfo::relocType reloc() const { return _rspec.type(); }
376 const RelocationHolder& rspec() const { return _rspec; }
378 friend class Assembler;
379 friend class MacroAssembler;
380 friend class Address;
381 friend class LIR_Assembler;
382 };
384 // Convience classes
385 class RuntimeAddress: public AddressLiteral {
387 public:
389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
391 };
393 class OopAddress: public AddressLiteral {
395 public:
397 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
399 };
401 class ExternalAddress: public AddressLiteral {
402 private:
403 static relocInfo::relocType reloc_for_target(address target) {
404 // Sometimes ExternalAddress is used for values which aren't
405 // exactly addresses, like the card table base.
406 // external_word_type can't be used for values in the first page
407 // so just skip the reloc in that case.
408 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
409 }
411 public:
413 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
415 };
417 class InternalAddress: public AddressLiteral {
419 public:
421 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
423 };
425 // x86 can do array addressing as a single operation since disp can be an absolute
426 // address amd64 can't. We create a class that expresses the concept but does extra
427 // magic on amd64 to get the final result
429 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
430 private:
432 AddressLiteral _base;
433 Address _index;
435 public:
437 ArrayAddress() {};
438 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
439 AddressLiteral base() { return _base; }
440 Address index() { return _index; }
442 };
444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
448 // is what you get. The Assembler is generating code into a CodeBuffer.
450 class Assembler : public AbstractAssembler {
451 friend class AbstractAssembler; // for the non-virtual hack
452 friend class LIR_Assembler; // as_Address()
453 friend class StubGenerator;
455 public:
456 enum Condition { // The x86 condition codes used for conditional jumps/moves.
457 zero = 0x4,
458 notZero = 0x5,
459 equal = 0x4,
460 notEqual = 0x5,
461 less = 0xc,
462 lessEqual = 0xe,
463 greater = 0xf,
464 greaterEqual = 0xd,
465 below = 0x2,
466 belowEqual = 0x6,
467 above = 0x7,
468 aboveEqual = 0x3,
469 overflow = 0x0,
470 noOverflow = 0x1,
471 carrySet = 0x2,
472 carryClear = 0x3,
473 negative = 0x8,
474 positive = 0x9,
475 parity = 0xa,
476 noParity = 0xb
477 };
479 enum Prefix {
480 // segment overrides
481 CS_segment = 0x2e,
482 SS_segment = 0x36,
483 DS_segment = 0x3e,
484 ES_segment = 0x26,
485 FS_segment = 0x64,
486 GS_segment = 0x65,
488 REX = 0x40,
490 REX_B = 0x41,
491 REX_X = 0x42,
492 REX_XB = 0x43,
493 REX_R = 0x44,
494 REX_RB = 0x45,
495 REX_RX = 0x46,
496 REX_RXB = 0x47,
498 REX_W = 0x48,
500 REX_WB = 0x49,
501 REX_WX = 0x4A,
502 REX_WXB = 0x4B,
503 REX_WR = 0x4C,
504 REX_WRB = 0x4D,
505 REX_WRX = 0x4E,
506 REX_WRXB = 0x4F
507 };
509 enum WhichOperand {
510 // input to locate_operand, and format code for relocations
511 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
512 disp32_operand = 1, // embedded 32-bit displacement or address
513 call32_operand = 2, // embedded 32-bit self-relative displacement
514 #ifndef _LP64
515 _WhichOperand_limit = 3
516 #else
517 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
518 _WhichOperand_limit = 4
519 #endif
520 };
524 // NOTE: The general philopsophy of the declarations here is that 64bit versions
525 // of instructions are freely declared without the need for wrapping them an ifdef.
526 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
527 // In the .cpp file the implementations are wrapped so that they are dropped out
528 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
529 // to the size it was prior to merging up the 32bit and 64bit assemblers.
530 //
531 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
532 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
534 private:
537 // 64bit prefixes
538 int prefix_and_encode(int reg_enc, bool byteinst = false);
539 int prefixq_and_encode(int reg_enc);
541 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
542 int prefixq_and_encode(int dst_enc, int src_enc);
544 void prefix(Register reg);
545 void prefix(Address adr);
546 void prefixq(Address adr);
548 void prefix(Address adr, Register reg, bool byteinst = false);
549 void prefixq(Address adr, Register reg);
551 void prefix(Address adr, XMMRegister reg);
553 void prefetch_prefix(Address src);
555 // Helper functions for groups of instructions
556 void emit_arith_b(int op1, int op2, Register dst, int imm8);
558 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
559 // only 32bit??
560 void emit_arith(int op1, int op2, Register dst, jobject obj);
561 void emit_arith(int op1, int op2, Register dst, Register src);
563 void emit_operand(Register reg,
564 Register base, Register index, Address::ScaleFactor scale,
565 int disp,
566 RelocationHolder const& rspec,
567 int rip_relative_correction = 0);
569 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
571 // operands that only take the original 32bit registers
572 void emit_operand32(Register reg, Address adr);
574 void emit_operand(XMMRegister reg,
575 Register base, Register index, Address::ScaleFactor scale,
576 int disp,
577 RelocationHolder const& rspec);
579 void emit_operand(XMMRegister reg, Address adr);
581 void emit_operand(MMXRegister reg, Address adr);
583 // workaround gcc (3.2.1-7) bug
584 void emit_operand(Address adr, MMXRegister reg);
587 // Immediate-to-memory forms
588 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
590 void emit_farith(int b1, int b2, int i);
593 protected:
594 #ifdef ASSERT
595 void check_relocation(RelocationHolder const& rspec, int format);
596 #endif
598 inline void emit_long64(jlong x);
600 void emit_data(jint data, relocInfo::relocType rtype, int format);
601 void emit_data(jint data, RelocationHolder const& rspec, int format);
602 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
603 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
605 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
607 // These are all easily abused and hence protected
609 // 32BIT ONLY SECTION
610 #ifndef _LP64
611 // Make these disappear in 64bit mode since they would never be correct
612 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
613 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
615 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
616 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
618 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
619 #else
620 // 64BIT ONLY SECTION
621 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
623 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
624 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
626 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
627 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
628 #endif // _LP64
630 // These are unique in that we are ensured by the caller that the 32bit
631 // relative in these instructions will always be able to reach the potentially
632 // 64bit address described by entry. Since they can take a 64bit address they
633 // don't have the 32 suffix like the other instructions in this class.
635 void call_literal(address entry, RelocationHolder const& rspec);
636 void jmp_literal(address entry, RelocationHolder const& rspec);
638 // Avoid using directly section
639 // Instructions in this section are actually usable by anyone without danger
640 // of failure but have performance issues that are addressed my enhanced
641 // instructions which will do the proper thing base on the particular cpu.
642 // We protect them because we don't trust you...
644 // Don't use next inc() and dec() methods directly. INC & DEC instructions
645 // could cause a partial flag stall since they don't set CF flag.
646 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
647 // which call inc() & dec() or add() & sub() in accordance with
648 // the product flag UseIncDec value.
650 void decl(Register dst);
651 void decl(Address dst);
652 void decq(Register dst);
653 void decq(Address dst);
655 void incl(Register dst);
656 void incl(Address dst);
657 void incq(Register dst);
658 void incq(Address dst);
660 // New cpus require use of movsd and movss to avoid partial register stall
661 // when loading from memory. But for old Opteron use movlpd instead of movsd.
662 // The selection is done in MacroAssembler::movdbl() and movflt().
664 // Move Scalar Single-Precision Floating-Point Values
665 void movss(XMMRegister dst, Address src);
666 void movss(XMMRegister dst, XMMRegister src);
667 void movss(Address dst, XMMRegister src);
669 // Move Scalar Double-Precision Floating-Point Values
670 void movsd(XMMRegister dst, Address src);
671 void movsd(XMMRegister dst, XMMRegister src);
672 void movsd(Address dst, XMMRegister src);
673 void movlpd(XMMRegister dst, Address src);
675 // New cpus require use of movaps and movapd to avoid partial register stall
676 // when moving between registers.
677 void movaps(XMMRegister dst, XMMRegister src);
678 void movapd(XMMRegister dst, XMMRegister src);
680 // End avoid using directly
683 // Instruction prefixes
684 void prefix(Prefix p);
686 public:
688 // Creation
689 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
691 // Decoding
692 static address locate_operand(address inst, WhichOperand which);
693 static address locate_next_instruction(address inst);
695 // Utilities
697 #ifdef _LP64
698 static bool is_simm(int64_t x, int nbits) { return -(CONST64(1) << (nbits-1)) <= x &&
699 x < (CONST64(1) << (nbits-1)); }
700 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
701 #else
702 static bool is_simm(int32_t x, int nbits) { return -(1 << (nbits-1)) <= x &&
703 x < (1 << (nbits-1)); }
704 static bool is_simm32(int32_t x) { return true; }
705 #endif // _LP64
707 static bool is_polling_page_far() NOT_LP64({ return false;});
709 // Generic instructions
710 // Does 32bit or 64bit as needed for the platform. In some sense these
711 // belong in macro assembler but there is no need for both varieties to exist
713 void lea(Register dst, Address src);
715 void mov(Register dst, Register src);
717 void pusha();
718 void popa();
720 void pushf();
721 void popf();
723 void push(int32_t imm32);
725 void push(Register src);
727 void pop(Register dst);
729 // These are dummies to prevent surprise implicit conversions to Register
730 void push(void* v);
731 void pop(void* v);
733 // These do register sized moves/scans
734 void rep_mov();
735 void rep_set();
736 void repne_scan();
737 #ifdef _LP64
738 void repne_scanl();
739 #endif
741 // Vanilla instructions in lexical order
743 void adcl(Address dst, int32_t imm32);
744 void adcl(Address dst, Register src);
745 void adcl(Register dst, int32_t imm32);
746 void adcl(Register dst, Address src);
747 void adcl(Register dst, Register src);
749 void adcq(Register dst, int32_t imm32);
750 void adcq(Register dst, Address src);
751 void adcq(Register dst, Register src);
753 void addl(Address dst, int32_t imm32);
754 void addl(Address dst, Register src);
755 void addl(Register dst, int32_t imm32);
756 void addl(Register dst, Address src);
757 void addl(Register dst, Register src);
759 void addq(Address dst, int32_t imm32);
760 void addq(Address dst, Register src);
761 void addq(Register dst, int32_t imm32);
762 void addq(Register dst, Address src);
763 void addq(Register dst, Register src);
765 void addr_nop_4();
766 void addr_nop_5();
767 void addr_nop_7();
768 void addr_nop_8();
770 // Add Scalar Double-Precision Floating-Point Values
771 void addsd(XMMRegister dst, Address src);
772 void addsd(XMMRegister dst, XMMRegister src);
774 // Add Scalar Single-Precision Floating-Point Values
775 void addss(XMMRegister dst, Address src);
776 void addss(XMMRegister dst, XMMRegister src);
778 void andl(Register dst, int32_t imm32);
779 void andl(Register dst, Address src);
780 void andl(Register dst, Register src);
782 void andq(Address dst, int32_t imm32);
783 void andq(Register dst, int32_t imm32);
784 void andq(Register dst, Address src);
785 void andq(Register dst, Register src);
787 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
788 void andpd(XMMRegister dst, Address src);
789 void andpd(XMMRegister dst, XMMRegister src);
791 void bsfl(Register dst, Register src);
792 void bsrl(Register dst, Register src);
794 #ifdef _LP64
795 void bsfq(Register dst, Register src);
796 void bsrq(Register dst, Register src);
797 #endif
799 void bswapl(Register reg);
801 void bswapq(Register reg);
803 void call(Label& L, relocInfo::relocType rtype);
804 void call(Register reg); // push pc; pc <- reg
805 void call(Address adr); // push pc; pc <- adr
807 void cdql();
809 void cdqq();
811 void cld() { emit_byte(0xfc); }
813 void clflush(Address adr);
815 void cmovl(Condition cc, Register dst, Register src);
816 void cmovl(Condition cc, Register dst, Address src);
818 void cmovq(Condition cc, Register dst, Register src);
819 void cmovq(Condition cc, Register dst, Address src);
822 void cmpb(Address dst, int imm8);
824 void cmpl(Address dst, int32_t imm32);
826 void cmpl(Register dst, int32_t imm32);
827 void cmpl(Register dst, Register src);
828 void cmpl(Register dst, Address src);
830 void cmpq(Address dst, int32_t imm32);
831 void cmpq(Address dst, Register src);
833 void cmpq(Register dst, int32_t imm32);
834 void cmpq(Register dst, Register src);
835 void cmpq(Register dst, Address src);
837 // these are dummies used to catch attempting to convert NULL to Register
838 void cmpl(Register dst, void* junk); // dummy
839 void cmpq(Register dst, void* junk); // dummy
841 void cmpw(Address dst, int imm16);
843 void cmpxchg8 (Address adr);
845 void cmpxchgl(Register reg, Address adr);
847 void cmpxchgq(Register reg, Address adr);
849 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
850 void comisd(XMMRegister dst, Address src);
852 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
853 void comiss(XMMRegister dst, Address src);
855 // Identify processor type and features
856 void cpuid() {
857 emit_byte(0x0F);
858 emit_byte(0xA2);
859 }
861 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
862 void cvtsd2ss(XMMRegister dst, XMMRegister src);
864 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
865 void cvtsi2sdl(XMMRegister dst, Register src);
866 void cvtsi2sdq(XMMRegister dst, Register src);
868 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
869 void cvtsi2ssl(XMMRegister dst, Register src);
870 void cvtsi2ssq(XMMRegister dst, Register src);
872 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
873 void cvtdq2pd(XMMRegister dst, XMMRegister src);
875 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
876 void cvtdq2ps(XMMRegister dst, XMMRegister src);
878 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
879 void cvtss2sd(XMMRegister dst, XMMRegister src);
881 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
882 void cvttsd2sil(Register dst, Address src);
883 void cvttsd2sil(Register dst, XMMRegister src);
884 void cvttsd2siq(Register dst, XMMRegister src);
886 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
887 void cvttss2sil(Register dst, XMMRegister src);
888 void cvttss2siq(Register dst, XMMRegister src);
890 // Divide Scalar Double-Precision Floating-Point Values
891 void divsd(XMMRegister dst, Address src);
892 void divsd(XMMRegister dst, XMMRegister src);
894 // Divide Scalar Single-Precision Floating-Point Values
895 void divss(XMMRegister dst, Address src);
896 void divss(XMMRegister dst, XMMRegister src);
898 void emms();
900 void fabs();
902 void fadd(int i);
904 void fadd_d(Address src);
905 void fadd_s(Address src);
907 // "Alternate" versions of x87 instructions place result down in FPU
908 // stack instead of on TOS
910 void fadda(int i); // "alternate" fadd
911 void faddp(int i = 1);
913 void fchs();
915 void fcom(int i);
917 void fcomp(int i = 1);
918 void fcomp_d(Address src);
919 void fcomp_s(Address src);
921 void fcompp();
923 void fcos();
925 void fdecstp();
927 void fdiv(int i);
928 void fdiv_d(Address src);
929 void fdivr_s(Address src);
930 void fdiva(int i); // "alternate" fdiv
931 void fdivp(int i = 1);
933 void fdivr(int i);
934 void fdivr_d(Address src);
935 void fdiv_s(Address src);
937 void fdivra(int i); // "alternate" reversed fdiv
939 void fdivrp(int i = 1);
941 void ffree(int i = 0);
943 void fild_d(Address adr);
944 void fild_s(Address adr);
946 void fincstp();
948 void finit();
950 void fist_s (Address adr);
951 void fistp_d(Address adr);
952 void fistp_s(Address adr);
954 void fld1();
956 void fld_d(Address adr);
957 void fld_s(Address adr);
958 void fld_s(int index);
959 void fld_x(Address adr); // extended-precision (80-bit) format
961 void fldcw(Address src);
963 void fldenv(Address src);
965 void fldlg2();
967 void fldln2();
969 void fldz();
971 void flog();
972 void flog10();
974 void fmul(int i);
976 void fmul_d(Address src);
977 void fmul_s(Address src);
979 void fmula(int i); // "alternate" fmul
981 void fmulp(int i = 1);
983 void fnsave(Address dst);
985 void fnstcw(Address src);
987 void fnstsw_ax();
989 void fprem();
990 void fprem1();
992 void frstor(Address src);
994 void fsin();
996 void fsqrt();
998 void fst_d(Address adr);
999 void fst_s(Address adr);
1001 void fstp_d(Address adr);
1002 void fstp_d(int index);
1003 void fstp_s(Address adr);
1004 void fstp_x(Address adr); // extended-precision (80-bit) format
1006 void fsub(int i);
1007 void fsub_d(Address src);
1008 void fsub_s(Address src);
1010 void fsuba(int i); // "alternate" fsub
1012 void fsubp(int i = 1);
1014 void fsubr(int i);
1015 void fsubr_d(Address src);
1016 void fsubr_s(Address src);
1018 void fsubra(int i); // "alternate" reversed fsub
1020 void fsubrp(int i = 1);
1022 void ftan();
1024 void ftst();
1026 void fucomi(int i = 1);
1027 void fucomip(int i = 1);
1029 void fwait();
1031 void fxch(int i = 1);
1033 void fxrstor(Address src);
1035 void fxsave(Address dst);
1037 void fyl2x();
1039 void hlt();
1041 void idivl(Register src);
1042 void divl(Register src); // Unsigned division
1044 void idivq(Register src);
1046 void imull(Register dst, Register src);
1047 void imull(Register dst, Register src, int value);
1049 void imulq(Register dst, Register src);
1050 void imulq(Register dst, Register src, int value);
1053 // jcc is the generic conditional branch generator to run-
1054 // time routines, jcc is used for branches to labels. jcc
1055 // takes a branch opcode (cc) and a label (L) and generates
1056 // either a backward branch or a forward branch and links it
1057 // to the label fixup chain. Usage:
1058 //
1059 // Label L; // unbound label
1060 // jcc(cc, L); // forward branch to unbound label
1061 // bind(L); // bind label to the current pc
1062 // jcc(cc, L); // backward branch to bound label
1063 // bind(L); // illegal: a label may be bound only once
1064 //
1065 // Note: The same Label can be used for forward and backward branches
1066 // but it may be bound only once.
1068 void jcc(Condition cc, Label& L,
1069 relocInfo::relocType rtype = relocInfo::none);
1071 // Conditional jump to a 8-bit offset to L.
1072 // WARNING: be very careful using this for forward jumps. If the label is
1073 // not bound within an 8-bit offset of this instruction, a run-time error
1074 // will occur.
1075 void jccb(Condition cc, Label& L);
1077 void jmp(Address entry); // pc <- entry
1079 // Label operations & relative jumps (PPUM Appendix D)
1080 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
1082 void jmp(Register entry); // pc <- entry
1084 // Unconditional 8-bit offset jump to L.
1085 // WARNING: be very careful using this for forward jumps. If the label is
1086 // not bound within an 8-bit offset of this instruction, a run-time error
1087 // will occur.
1088 void jmpb(Label& L);
1090 void ldmxcsr( Address src );
1092 void leal(Register dst, Address src);
1094 void leaq(Register dst, Address src);
1096 void lfence() {
1097 emit_byte(0x0F);
1098 emit_byte(0xAE);
1099 emit_byte(0xE8);
1100 }
1102 void lock();
1104 void lzcntl(Register dst, Register src);
1106 #ifdef _LP64
1107 void lzcntq(Register dst, Register src);
1108 #endif
1110 enum Membar_mask_bits {
1111 StoreStore = 1 << 3,
1112 LoadStore = 1 << 2,
1113 StoreLoad = 1 << 1,
1114 LoadLoad = 1 << 0
1115 };
1117 // Serializes memory and blows flags
1118 void membar(Membar_mask_bits order_constraint) {
1119 if (os::is_MP()) {
1120 // We only have to handle StoreLoad
1121 if (order_constraint & StoreLoad) {
1122 // All usable chips support "locked" instructions which suffice
1123 // as barriers, and are much faster than the alternative of
1124 // using cpuid instruction. We use here a locked add [esp],0.
1125 // This is conveniently otherwise a no-op except for blowing
1126 // flags.
1127 // Any change to this code may need to revisit other places in
1128 // the code where this idiom is used, in particular the
1129 // orderAccess code.
1130 lock();
1131 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1132 }
1133 }
1134 }
1136 void mfence();
1138 // Moves
1140 void mov64(Register dst, int64_t imm64);
1142 void movb(Address dst, Register src);
1143 void movb(Address dst, int imm8);
1144 void movb(Register dst, Address src);
1146 void movdl(XMMRegister dst, Register src);
1147 void movdl(Register dst, XMMRegister src);
1148 void movdl(XMMRegister dst, Address src);
1150 // Move Double Quadword
1151 void movdq(XMMRegister dst, Register src);
1152 void movdq(Register dst, XMMRegister src);
1154 // Move Aligned Double Quadword
1155 void movdqa(Address dst, XMMRegister src);
1156 void movdqa(XMMRegister dst, Address src);
1157 void movdqa(XMMRegister dst, XMMRegister src);
1159 // Move Unaligned Double Quadword
1160 void movdqu(Address dst, XMMRegister src);
1161 void movdqu(XMMRegister dst, Address src);
1162 void movdqu(XMMRegister dst, XMMRegister src);
1164 void movl(Register dst, int32_t imm32);
1165 void movl(Address dst, int32_t imm32);
1166 void movl(Register dst, Register src);
1167 void movl(Register dst, Address src);
1168 void movl(Address dst, Register src);
1170 // These dummies prevent using movl from converting a zero (like NULL) into Register
1171 // by giving the compiler two choices it can't resolve
1173 void movl(Address dst, void* junk);
1174 void movl(Register dst, void* junk);
1176 #ifdef _LP64
1177 void movq(Register dst, Register src);
1178 void movq(Register dst, Address src);
1179 void movq(Address dst, Register src);
1180 #endif
1182 void movq(Address dst, MMXRegister src );
1183 void movq(MMXRegister dst, Address src );
1185 #ifdef _LP64
1186 // These dummies prevent using movq from converting a zero (like NULL) into Register
1187 // by giving the compiler two choices it can't resolve
1189 void movq(Address dst, void* dummy);
1190 void movq(Register dst, void* dummy);
1191 #endif
1193 // Move Quadword
1194 void movq(Address dst, XMMRegister src);
1195 void movq(XMMRegister dst, Address src);
1197 void movsbl(Register dst, Address src);
1198 void movsbl(Register dst, Register src);
1200 #ifdef _LP64
1201 void movsbq(Register dst, Address src);
1202 void movsbq(Register dst, Register src);
1204 // Move signed 32bit immediate to 64bit extending sign
1205 void movslq(Address dst, int32_t imm64);
1206 void movslq(Register dst, int32_t imm64);
1208 void movslq(Register dst, Address src);
1209 void movslq(Register dst, Register src);
1210 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1211 #endif
1213 void movswl(Register dst, Address src);
1214 void movswl(Register dst, Register src);
1216 #ifdef _LP64
1217 void movswq(Register dst, Address src);
1218 void movswq(Register dst, Register src);
1219 #endif
1221 void movw(Address dst, int imm16);
1222 void movw(Register dst, Address src);
1223 void movw(Address dst, Register src);
1225 void movzbl(Register dst, Address src);
1226 void movzbl(Register dst, Register src);
1228 #ifdef _LP64
1229 void movzbq(Register dst, Address src);
1230 void movzbq(Register dst, Register src);
1231 #endif
1233 void movzwl(Register dst, Address src);
1234 void movzwl(Register dst, Register src);
1236 #ifdef _LP64
1237 void movzwq(Register dst, Address src);
1238 void movzwq(Register dst, Register src);
1239 #endif
1241 void mull(Address src);
1242 void mull(Register src);
1244 // Multiply Scalar Double-Precision Floating-Point Values
1245 void mulsd(XMMRegister dst, Address src);
1246 void mulsd(XMMRegister dst, XMMRegister src);
1248 // Multiply Scalar Single-Precision Floating-Point Values
1249 void mulss(XMMRegister dst, Address src);
1250 void mulss(XMMRegister dst, XMMRegister src);
1252 void negl(Register dst);
1254 #ifdef _LP64
1255 void negq(Register dst);
1256 #endif
1258 void nop(int i = 1);
1260 void notl(Register dst);
1262 #ifdef _LP64
1263 void notq(Register dst);
1264 #endif
1266 void orl(Address dst, int32_t imm32);
1267 void orl(Register dst, int32_t imm32);
1268 void orl(Register dst, Address src);
1269 void orl(Register dst, Register src);
1271 void orq(Address dst, int32_t imm32);
1272 void orq(Register dst, int32_t imm32);
1273 void orq(Register dst, Address src);
1274 void orq(Register dst, Register src);
1276 // SSE4.2 string instructions
1277 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1278 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1280 #ifndef _LP64 // no 32bit push/pop on amd64
1281 void popl(Address dst);
1282 #endif
1284 #ifdef _LP64
1285 void popq(Address dst);
1286 #endif
1288 void popcntl(Register dst, Address src);
1289 void popcntl(Register dst, Register src);
1291 #ifdef _LP64
1292 void popcntq(Register dst, Address src);
1293 void popcntq(Register dst, Register src);
1294 #endif
1296 // Prefetches (SSE, SSE2, 3DNOW only)
1298 void prefetchnta(Address src);
1299 void prefetchr(Address src);
1300 void prefetcht0(Address src);
1301 void prefetcht1(Address src);
1302 void prefetcht2(Address src);
1303 void prefetchw(Address src);
1305 // POR - Bitwise logical OR
1306 void por(XMMRegister dst, XMMRegister src);
1308 // Shuffle Packed Doublewords
1309 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1310 void pshufd(XMMRegister dst, Address src, int mode);
1312 // Shuffle Packed Low Words
1313 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1314 void pshuflw(XMMRegister dst, Address src, int mode);
1316 // Shift Right by bits Logical Quadword Immediate
1317 void psrlq(XMMRegister dst, int shift);
1319 // Shift Right by bytes Logical DoubleQuadword Immediate
1320 void psrldq(XMMRegister dst, int shift);
1322 // Logical Compare Double Quadword
1323 void ptest(XMMRegister dst, XMMRegister src);
1324 void ptest(XMMRegister dst, Address src);
1326 // Interleave Low Bytes
1327 void punpcklbw(XMMRegister dst, XMMRegister src);
1329 #ifndef _LP64 // no 32bit push/pop on amd64
1330 void pushl(Address src);
1331 #endif
1333 void pushq(Address src);
1335 // Xor Packed Byte Integer Values
1336 void pxor(XMMRegister dst, Address src);
1337 void pxor(XMMRegister dst, XMMRegister src);
1339 void rcll(Register dst, int imm8);
1341 void rclq(Register dst, int imm8);
1343 void ret(int imm16);
1345 void sahf();
1347 void sarl(Register dst, int imm8);
1348 void sarl(Register dst);
1350 void sarq(Register dst, int imm8);
1351 void sarq(Register dst);
1353 void sbbl(Address dst, int32_t imm32);
1354 void sbbl(Register dst, int32_t imm32);
1355 void sbbl(Register dst, Address src);
1356 void sbbl(Register dst, Register src);
1358 void sbbq(Address dst, int32_t imm32);
1359 void sbbq(Register dst, int32_t imm32);
1360 void sbbq(Register dst, Address src);
1361 void sbbq(Register dst, Register src);
1363 void setb(Condition cc, Register dst);
1365 void shldl(Register dst, Register src);
1367 void shll(Register dst, int imm8);
1368 void shll(Register dst);
1370 void shlq(Register dst, int imm8);
1371 void shlq(Register dst);
1373 void shrdl(Register dst, Register src);
1375 void shrl(Register dst, int imm8);
1376 void shrl(Register dst);
1378 void shrq(Register dst, int imm8);
1379 void shrq(Register dst);
1381 void smovl(); // QQQ generic?
1383 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1384 void sqrtsd(XMMRegister dst, Address src);
1385 void sqrtsd(XMMRegister dst, XMMRegister src);
1387 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1388 void sqrtss(XMMRegister dst, Address src);
1389 void sqrtss(XMMRegister dst, XMMRegister src);
1391 void std() { emit_byte(0xfd); }
1393 void stmxcsr( Address dst );
1395 void subl(Address dst, int32_t imm32);
1396 void subl(Address dst, Register src);
1397 void subl(Register dst, int32_t imm32);
1398 void subl(Register dst, Address src);
1399 void subl(Register dst, Register src);
1401 void subq(Address dst, int32_t imm32);
1402 void subq(Address dst, Register src);
1403 void subq(Register dst, int32_t imm32);
1404 void subq(Register dst, Address src);
1405 void subq(Register dst, Register src);
1408 // Subtract Scalar Double-Precision Floating-Point Values
1409 void subsd(XMMRegister dst, Address src);
1410 void subsd(XMMRegister dst, XMMRegister src);
1412 // Subtract Scalar Single-Precision Floating-Point Values
1413 void subss(XMMRegister dst, Address src);
1414 void subss(XMMRegister dst, XMMRegister src);
1416 void testb(Register dst, int imm8);
1418 void testl(Register dst, int32_t imm32);
1419 void testl(Register dst, Register src);
1420 void testl(Register dst, Address src);
1422 void testq(Register dst, int32_t imm32);
1423 void testq(Register dst, Register src);
1426 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1427 void ucomisd(XMMRegister dst, Address src);
1428 void ucomisd(XMMRegister dst, XMMRegister src);
1430 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1431 void ucomiss(XMMRegister dst, Address src);
1432 void ucomiss(XMMRegister dst, XMMRegister src);
1434 void xaddl(Address dst, Register src);
1436 void xaddq(Address dst, Register src);
1438 void xchgl(Register reg, Address adr);
1439 void xchgl(Register dst, Register src);
1441 void xchgq(Register reg, Address adr);
1442 void xchgq(Register dst, Register src);
1444 void xorl(Register dst, int32_t imm32);
1445 void xorl(Register dst, Address src);
1446 void xorl(Register dst, Register src);
1448 void xorq(Register dst, Address src);
1449 void xorq(Register dst, Register src);
1451 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1452 void xorpd(XMMRegister dst, Address src);
1453 void xorpd(XMMRegister dst, XMMRegister src);
1455 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1456 void xorps(XMMRegister dst, Address src);
1457 void xorps(XMMRegister dst, XMMRegister src);
1459 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1460 };
1463 // MacroAssembler extends Assembler by frequently used macros.
1464 //
1465 // Instructions for which a 'better' code sequence exists depending
1466 // on arguments should also go in here.
1468 class MacroAssembler: public Assembler {
1469 friend class LIR_Assembler;
1470 friend class Runtime1; // as_Address()
1472 protected:
1474 Address as_Address(AddressLiteral adr);
1475 Address as_Address(ArrayAddress adr);
1477 // Support for VM calls
1478 //
1479 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1480 // may customize this version by overriding it for its purposes (e.g., to save/restore
1481 // additional registers when doing a VM call).
1482 #ifdef CC_INTERP
1483 // c++ interpreter never wants to use interp_masm version of call_VM
1484 #define VIRTUAL
1485 #else
1486 #define VIRTUAL virtual
1487 #endif
1489 VIRTUAL void call_VM_leaf_base(
1490 address entry_point, // the entry point
1491 int number_of_arguments // the number of arguments to pop after the call
1492 );
1494 // This is the base routine called by the different versions of call_VM. The interpreter
1495 // may customize this version by overriding it for its purposes (e.g., to save/restore
1496 // additional registers when doing a VM call).
1497 //
1498 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1499 // returns the register which contains the thread upon return. If a thread register has been
1500 // specified, the return value will correspond to that register. If no last_java_sp is specified
1501 // (noreg) than rsp will be used instead.
1502 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1503 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1504 Register java_thread, // the thread if computed before ; use noreg otherwise
1505 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1506 address entry_point, // the entry point
1507 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1508 bool check_exceptions // whether to check for pending exceptions after return
1509 );
1511 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1512 // The implementation is only non-empty for the InterpreterMacroAssembler,
1513 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1514 virtual void check_and_handle_popframe(Register java_thread);
1515 virtual void check_and_handle_earlyret(Register java_thread);
1517 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1519 // helpers for FPU flag access
1520 // tmp is a temporary register, if none is available use noreg
1521 void save_rax (Register tmp);
1522 void restore_rax(Register tmp);
1524 public:
1525 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1527 // Support for NULL-checks
1528 //
1529 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1530 // If the accessed location is M[reg + offset] and the offset is known, provide the
1531 // offset. No explicit code generation is needed if the offset is within a certain
1532 // range (0 <= offset <= page_size).
1534 void null_check(Register reg, int offset = -1);
1535 static bool needs_explicit_null_check(intptr_t offset);
1537 // Required platform-specific helpers for Label::patch_instructions.
1538 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1539 void pd_patch_instruction(address branch, address target);
1540 #ifndef PRODUCT
1541 static void pd_print_patched_instruction(address branch);
1542 #endif
1544 // The following 4 methods return the offset of the appropriate move instruction
1546 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1547 int load_unsigned_byte(Register dst, Address src);
1548 int load_unsigned_short(Register dst, Address src);
1550 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1551 int load_signed_byte(Register dst, Address src);
1552 int load_signed_short(Register dst, Address src);
1554 // Support for sign-extension (hi:lo = extend_sign(lo))
1555 void extend_sign(Register hi, Register lo);
1557 // Load and store values by size and signed-ness
1558 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1559 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1561 // Support for inc/dec with optimal instruction selection depending on value
1563 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1564 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1566 void decrementl(Address dst, int value = 1);
1567 void decrementl(Register reg, int value = 1);
1569 void decrementq(Register reg, int value = 1);
1570 void decrementq(Address dst, int value = 1);
1572 void incrementl(Address dst, int value = 1);
1573 void incrementl(Register reg, int value = 1);
1575 void incrementq(Register reg, int value = 1);
1576 void incrementq(Address dst, int value = 1);
1579 // Support optimal SSE move instructions.
1580 void movflt(XMMRegister dst, XMMRegister src) {
1581 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1582 else { movss (dst, src); return; }
1583 }
1584 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1585 void movflt(XMMRegister dst, AddressLiteral src);
1586 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1588 void movdbl(XMMRegister dst, XMMRegister src) {
1589 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1590 else { movsd (dst, src); return; }
1591 }
1593 void movdbl(XMMRegister dst, AddressLiteral src);
1595 void movdbl(XMMRegister dst, Address src) {
1596 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1597 else { movlpd(dst, src); return; }
1598 }
1599 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1601 void incrementl(AddressLiteral dst);
1602 void incrementl(ArrayAddress dst);
1604 // Alignment
1605 void align(int modulus);
1607 // Misc
1608 void fat_nop(); // 5 byte nop
1610 // Stack frame creation/removal
1611 void enter();
1612 void leave();
1614 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1615 // The pointer will be loaded into the thread register.
1616 void get_thread(Register thread);
1619 // Support for VM calls
1620 //
1621 // It is imperative that all calls into the VM are handled via the call_VM macros.
1622 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1623 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1626 void call_VM(Register oop_result,
1627 address entry_point,
1628 bool check_exceptions = true);
1629 void call_VM(Register oop_result,
1630 address entry_point,
1631 Register arg_1,
1632 bool check_exceptions = true);
1633 void call_VM(Register oop_result,
1634 address entry_point,
1635 Register arg_1, Register arg_2,
1636 bool check_exceptions = true);
1637 void call_VM(Register oop_result,
1638 address entry_point,
1639 Register arg_1, Register arg_2, Register arg_3,
1640 bool check_exceptions = true);
1642 // Overloadings with last_Java_sp
1643 void call_VM(Register oop_result,
1644 Register last_java_sp,
1645 address entry_point,
1646 int number_of_arguments = 0,
1647 bool check_exceptions = true);
1648 void call_VM(Register oop_result,
1649 Register last_java_sp,
1650 address entry_point,
1651 Register arg_1, bool
1652 check_exceptions = true);
1653 void call_VM(Register oop_result,
1654 Register last_java_sp,
1655 address entry_point,
1656 Register arg_1, Register arg_2,
1657 bool check_exceptions = true);
1658 void call_VM(Register oop_result,
1659 Register last_java_sp,
1660 address entry_point,
1661 Register arg_1, Register arg_2, Register arg_3,
1662 bool check_exceptions = true);
1664 // These always tightly bind to MacroAssembler::call_VM_base
1665 // bypassing the virtual implementation
1666 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1667 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1668 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1669 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1670 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1672 void call_VM_leaf(address entry_point,
1673 int number_of_arguments = 0);
1674 void call_VM_leaf(address entry_point,
1675 Register arg_1);
1676 void call_VM_leaf(address entry_point,
1677 Register arg_1, Register arg_2);
1678 void call_VM_leaf(address entry_point,
1679 Register arg_1, Register arg_2, Register arg_3);
1681 // These always tightly bind to MacroAssembler::call_VM_leaf_base
1682 // bypassing the virtual implementation
1683 void super_call_VM_leaf(address entry_point);
1684 void super_call_VM_leaf(address entry_point, Register arg_1);
1685 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1686 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
1687 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
1689 // last Java Frame (fills frame anchor)
1690 void set_last_Java_frame(Register thread,
1691 Register last_java_sp,
1692 Register last_java_fp,
1693 address last_java_pc);
1695 // thread in the default location (r15_thread on 64bit)
1696 void set_last_Java_frame(Register last_java_sp,
1697 Register last_java_fp,
1698 address last_java_pc);
1700 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1702 // thread in the default location (r15_thread on 64bit)
1703 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1705 // Stores
1706 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1707 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1709 #ifndef SERIALGC
1711 void g1_write_barrier_pre(Register obj,
1712 Register pre_val,
1713 Register thread,
1714 Register tmp,
1715 bool tosca_live,
1716 bool expand_call);
1718 void g1_write_barrier_post(Register store_addr,
1719 Register new_val,
1720 Register thread,
1721 Register tmp,
1722 Register tmp2);
1724 #endif // SERIALGC
1726 // split store_check(Register obj) to enhance instruction interleaving
1727 void store_check_part_1(Register obj);
1728 void store_check_part_2(Register obj);
1730 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1731 void c2bool(Register x);
1733 // C++ bool manipulation
1735 void movbool(Register dst, Address src);
1736 void movbool(Address dst, bool boolconst);
1737 void movbool(Address dst, Register src);
1738 void testbool(Register dst);
1740 // oop manipulations
1741 void load_klass(Register dst, Register src);
1742 void store_klass(Register dst, Register src);
1744 void load_heap_oop(Register dst, Address src);
1745 void load_heap_oop_not_null(Register dst, Address src);
1746 void store_heap_oop(Address dst, Register src);
1748 // Used for storing NULL. All other oop constants should be
1749 // stored using routines that take a jobject.
1750 void store_heap_oop_null(Address dst);
1752 void load_prototype_header(Register dst, Register src);
1754 #ifdef _LP64
1755 void store_klass_gap(Register dst, Register src);
1757 // This dummy is to prevent a call to store_heap_oop from
1758 // converting a zero (like NULL) into a Register by giving
1759 // the compiler two choices it can't resolve
1761 void store_heap_oop(Address dst, void* dummy);
1763 void encode_heap_oop(Register r);
1764 void decode_heap_oop(Register r);
1765 void encode_heap_oop_not_null(Register r);
1766 void decode_heap_oop_not_null(Register r);
1767 void encode_heap_oop_not_null(Register dst, Register src);
1768 void decode_heap_oop_not_null(Register dst, Register src);
1770 void set_narrow_oop(Register dst, jobject obj);
1771 void set_narrow_oop(Address dst, jobject obj);
1772 void cmp_narrow_oop(Register dst, jobject obj);
1773 void cmp_narrow_oop(Address dst, jobject obj);
1775 // if heap base register is used - reinit it with the correct value
1776 void reinit_heapbase();
1778 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1780 #endif // _LP64
1782 // Int division/remainder for Java
1783 // (as idivl, but checks for special case as described in JVM spec.)
1784 // returns idivl instruction offset for implicit exception handling
1785 int corrected_idivl(Register reg);
1787 // Long division/remainder for Java
1788 // (as idivq, but checks for special case as described in JVM spec.)
1789 // returns idivq instruction offset for implicit exception handling
1790 int corrected_idivq(Register reg);
1792 void int3();
1794 // Long operation macros for a 32bit cpu
1795 // Long negation for Java
1796 void lneg(Register hi, Register lo);
1798 // Long multiplication for Java
1799 // (destroys contents of eax, ebx, ecx and edx)
1800 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1802 // Long shifts for Java
1803 // (semantics as described in JVM spec.)
1804 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1805 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1807 // Long compare for Java
1808 // (semantics as described in JVM spec.)
1809 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1812 // misc
1814 // Sign extension
1815 void sign_extend_short(Register reg);
1816 void sign_extend_byte(Register reg);
1818 // Division by power of 2, rounding towards 0
1819 void division_with_shift(Register reg, int shift_value);
1821 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1822 //
1823 // CF (corresponds to C0) if x < y
1824 // PF (corresponds to C2) if unordered
1825 // ZF (corresponds to C3) if x = y
1826 //
1827 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1828 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1829 void fcmp(Register tmp);
1830 // Variant of the above which allows y to be further down the stack
1831 // and which only pops x and y if specified. If pop_right is
1832 // specified then pop_left must also be specified.
1833 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1835 // Floating-point comparison for Java
1836 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1837 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1838 // (semantics as described in JVM spec.)
1839 void fcmp2int(Register dst, bool unordered_is_less);
1840 // Variant of the above which allows y to be further down the stack
1841 // and which only pops x and y if specified. If pop_right is
1842 // specified then pop_left must also be specified.
1843 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1845 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1846 // tmp is a temporary register, if none is available use noreg
1847 void fremr(Register tmp);
1850 // same as fcmp2int, but using SSE2
1851 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1852 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1854 // Inlined sin/cos generator for Java; must not use CPU instruction
1855 // directly on Intel as it does not have high enough precision
1856 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1857 // number of FPU stack slots in use; all but the topmost will
1858 // require saving if a slow case is necessary. Assumes argument is
1859 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1860 // this code.
1861 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1863 // branch to L if FPU flag C2 is set/not set
1864 // tmp is a temporary register, if none is available use noreg
1865 void jC2 (Register tmp, Label& L);
1866 void jnC2(Register tmp, Label& L);
1868 // Pop ST (ffree & fincstp combined)
1869 void fpop();
1871 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1872 void push_fTOS();
1874 // pops double TOS element from CPU stack and pushes on FPU stack
1875 void pop_fTOS();
1877 void empty_FPU_stack();
1879 void push_IU_state();
1880 void pop_IU_state();
1882 void push_FPU_state();
1883 void pop_FPU_state();
1885 void push_CPU_state();
1886 void pop_CPU_state();
1888 // Round up to a power of two
1889 void round_to(Register reg, int modulus);
1891 // Callee saved registers handling
1892 void push_callee_saved_registers();
1893 void pop_callee_saved_registers();
1895 // allocation
1896 void eden_allocate(
1897 Register obj, // result: pointer to object after successful allocation
1898 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1899 int con_size_in_bytes, // object size in bytes if known at compile time
1900 Register t1, // temp register
1901 Label& slow_case // continuation point if fast allocation fails
1902 );
1903 void tlab_allocate(
1904 Register obj, // result: pointer to object after successful allocation
1905 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1906 int con_size_in_bytes, // object size in bytes if known at compile time
1907 Register t1, // temp register
1908 Register t2, // temp register
1909 Label& slow_case // continuation point if fast allocation fails
1910 );
1911 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
1912 void incr_allocated_bytes(Register thread,
1913 Register var_size_in_bytes, int con_size_in_bytes,
1914 Register t1 = noreg);
1916 // interface method calling
1917 void lookup_interface_method(Register recv_klass,
1918 Register intf_klass,
1919 RegisterOrConstant itable_index,
1920 Register method_result,
1921 Register scan_temp,
1922 Label& no_such_interface);
1924 // Test sub_klass against super_klass, with fast and slow paths.
1926 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1927 // One of the three labels can be NULL, meaning take the fall-through.
1928 // If super_check_offset is -1, the value is loaded up from super_klass.
1929 // No registers are killed, except temp_reg.
1930 void check_klass_subtype_fast_path(Register sub_klass,
1931 Register super_klass,
1932 Register temp_reg,
1933 Label* L_success,
1934 Label* L_failure,
1935 Label* L_slow_path,
1936 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1938 // The rest of the type check; must be wired to a corresponding fast path.
1939 // It does not repeat the fast path logic, so don't use it standalone.
1940 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1941 // Updates the sub's secondary super cache as necessary.
1942 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1943 void check_klass_subtype_slow_path(Register sub_klass,
1944 Register super_klass,
1945 Register temp_reg,
1946 Register temp2_reg,
1947 Label* L_success,
1948 Label* L_failure,
1949 bool set_cond_codes = false);
1951 // Simplified, combined version, good for typical uses.
1952 // Falls through on failure.
1953 void check_klass_subtype(Register sub_klass,
1954 Register super_klass,
1955 Register temp_reg,
1956 Label& L_success);
1958 // method handles (JSR 292)
1959 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1960 Register temp_reg,
1961 Label& wrong_method_type);
1962 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1963 Register temp_reg);
1964 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1965 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1968 //----
1969 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1971 // Debugging
1973 // only if +VerifyOops
1974 void verify_oop(Register reg, const char* s = "broken oop");
1975 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1977 // only if +VerifyFPU
1978 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1980 // prints msg, dumps registers and stops execution
1981 void stop(const char* msg);
1983 // prints msg and continues
1984 void warn(const char* msg);
1986 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1987 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1989 void os_breakpoint();
1991 void untested() { stop("untested"); }
1993 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
1995 void should_not_reach_here() { stop("should not reach here"); }
1997 void print_CPU_state();
1999 // Stack overflow checking
2000 void bang_stack_with_offset(int offset) {
2001 // stack grows down, caller passes positive offset
2002 assert(offset > 0, "must bang with negative offset");
2003 movl(Address(rsp, (-offset)), rax);
2004 }
2006 // Writes to stack successive pages until offset reached to check for
2007 // stack overflow + shadow pages. Also, clobbers tmp
2008 void bang_stack_size(Register size, Register tmp);
2010 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2011 Register tmp,
2012 int offset);
2014 // Support for serializing memory accesses between threads
2015 void serialize_memory(Register thread, Register tmp);
2017 void verify_tlab();
2019 // Biased locking support
2020 // lock_reg and obj_reg must be loaded up with the appropriate values.
2021 // swap_reg must be rax, and is killed.
2022 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2023 // be killed; if not supplied, push/pop will be used internally to
2024 // allocate a temporary (inefficient, avoid if possible).
2025 // Optional slow case is for implementations (interpreter and C1) which branch to
2026 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2027 // Returns offset of first potentially-faulting instruction for null
2028 // check info (currently consumed only by C1). If
2029 // swap_reg_contains_mark is true then returns -1 as it is assumed
2030 // the calling code has already passed any potential faults.
2031 int biased_locking_enter(Register lock_reg, Register obj_reg,
2032 Register swap_reg, Register tmp_reg,
2033 bool swap_reg_contains_mark,
2034 Label& done, Label* slow_case = NULL,
2035 BiasedLockingCounters* counters = NULL);
2036 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2039 Condition negate_condition(Condition cond);
2041 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2042 // operands. In general the names are modified to avoid hiding the instruction in Assembler
2043 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2044 // here in MacroAssembler. The major exception to this rule is call
2046 // Arithmetics
2049 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2050 void addptr(Address dst, Register src);
2052 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2053 void addptr(Register dst, int32_t src);
2054 void addptr(Register dst, Register src);
2055 void addptr(Register dst, RegisterOrConstant src) {
2056 if (src.is_constant()) addptr(dst, (int) src.as_constant());
2057 else addptr(dst, src.as_register());
2058 }
2060 void andptr(Register dst, int32_t src);
2061 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2063 void cmp8(AddressLiteral src1, int imm);
2065 // renamed to drag out the casting of address to int32_t/intptr_t
2066 void cmp32(Register src1, int32_t imm);
2068 void cmp32(AddressLiteral src1, int32_t imm);
2069 // compare reg - mem, or reg - &mem
2070 void cmp32(Register src1, AddressLiteral src2);
2072 void cmp32(Register src1, Address src2);
2074 #ifndef _LP64
2075 void cmpoop(Address dst, jobject obj);
2076 void cmpoop(Register dst, jobject obj);
2077 #endif // _LP64
2079 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2080 void cmpptr(Address src1, AddressLiteral src2);
2082 void cmpptr(Register src1, AddressLiteral src2);
2084 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2085 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2086 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2088 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2089 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2091 // cmp64 to avoild hiding cmpq
2092 void cmp64(Register src1, AddressLiteral src);
2094 void cmpxchgptr(Register reg, Address adr);
2096 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2099 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2102 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2104 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2106 void shlptr(Register dst, int32_t shift);
2107 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2109 void shrptr(Register dst, int32_t shift);
2110 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2112 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2113 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2115 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2117 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2118 void subptr(Register dst, int32_t src);
2119 void subptr(Register dst, Register src);
2120 void subptr(Register dst, RegisterOrConstant src) {
2121 if (src.is_constant()) subptr(dst, (int) src.as_constant());
2122 else subptr(dst, src.as_register());
2123 }
2125 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2126 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2128 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2129 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2131 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2135 // Helper functions for statistics gathering.
2136 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2137 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2138 // Unconditional atomic increment.
2139 void atomic_incl(AddressLiteral counter_addr);
2141 void lea(Register dst, AddressLiteral adr);
2142 void lea(Address dst, AddressLiteral adr);
2143 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2145 void leal32(Register dst, Address src) { leal(dst, src); }
2147 // Import other testl() methods from the parent class or else
2148 // they will be hidden by the following overriding declaration.
2149 using Assembler::testl;
2150 void testl(Register dst, AddressLiteral src);
2152 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2153 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2154 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2156 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2157 void testptr(Register src1, Register src2);
2159 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2160 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2162 // Calls
2164 void call(Label& L, relocInfo::relocType rtype);
2165 void call(Register entry);
2167 // NOTE: this call tranfers to the effective address of entry NOT
2168 // the address contained by entry. This is because this is more natural
2169 // for jumps/calls.
2170 void call(AddressLiteral entry);
2172 // Jumps
2174 // NOTE: these jumps tranfer to the effective address of dst NOT
2175 // the address contained by dst. This is because this is more natural
2176 // for jumps/calls.
2177 void jump(AddressLiteral dst);
2178 void jump_cc(Condition cc, AddressLiteral dst);
2180 // 32bit can do a case table jump in one instruction but we no longer allow the base
2181 // to be installed in the Address class. This jump will tranfers to the address
2182 // contained in the location described by entry (not the address of entry)
2183 void jump(ArrayAddress entry);
2185 // Floating
2187 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2188 void andpd(XMMRegister dst, AddressLiteral src);
2190 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2191 void comiss(XMMRegister dst, AddressLiteral src);
2193 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2194 void comisd(XMMRegister dst, AddressLiteral src);
2196 void fadd_s(Address src) { Assembler::fadd_s(src); }
2197 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2199 void fldcw(Address src) { Assembler::fldcw(src); }
2200 void fldcw(AddressLiteral src);
2202 void fld_s(int index) { Assembler::fld_s(index); }
2203 void fld_s(Address src) { Assembler::fld_s(src); }
2204 void fld_s(AddressLiteral src);
2206 void fld_d(Address src) { Assembler::fld_d(src); }
2207 void fld_d(AddressLiteral src);
2209 void fld_x(Address src) { Assembler::fld_x(src); }
2210 void fld_x(AddressLiteral src);
2212 void fmul_s(Address src) { Assembler::fmul_s(src); }
2213 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2215 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2216 void ldmxcsr(AddressLiteral src);
2218 private:
2219 // these are private because users should be doing movflt/movdbl
2221 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2222 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2223 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2224 void movss(XMMRegister dst, AddressLiteral src);
2226 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2227 void movlpd(XMMRegister dst, AddressLiteral src);
2229 public:
2231 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2232 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2233 void addsd(XMMRegister dst, AddressLiteral src) { Assembler::addsd(dst, as_Address(src)); }
2235 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2236 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2237 void addss(XMMRegister dst, AddressLiteral src) { Assembler::addss(dst, as_Address(src)); }
2239 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2240 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2241 void divsd(XMMRegister dst, AddressLiteral src) { Assembler::divsd(dst, as_Address(src)); }
2243 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2244 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2245 void divss(XMMRegister dst, AddressLiteral src) { Assembler::divss(dst, as_Address(src)); }
2247 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2248 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2249 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2250 void movsd(XMMRegister dst, AddressLiteral src) { Assembler::movsd(dst, as_Address(src)); }
2252 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2253 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2254 void mulsd(XMMRegister dst, AddressLiteral src) { Assembler::mulsd(dst, as_Address(src)); }
2256 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2257 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2258 void mulss(XMMRegister dst, AddressLiteral src) { Assembler::mulss(dst, as_Address(src)); }
2260 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2261 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2262 void sqrtsd(XMMRegister dst, AddressLiteral src) { Assembler::sqrtsd(dst, as_Address(src)); }
2264 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2265 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2266 void sqrtss(XMMRegister dst, AddressLiteral src) { Assembler::sqrtss(dst, as_Address(src)); }
2268 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2269 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2270 void subsd(XMMRegister dst, AddressLiteral src) { Assembler::subsd(dst, as_Address(src)); }
2272 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2273 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2274 void subss(XMMRegister dst, AddressLiteral src) { Assembler::subss(dst, as_Address(src)); }
2276 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2277 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2278 void ucomiss(XMMRegister dst, AddressLiteral src);
2280 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2281 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2282 void ucomisd(XMMRegister dst, AddressLiteral src);
2284 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2285 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2286 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2287 void xorpd(XMMRegister dst, AddressLiteral src);
2289 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2290 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2291 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2292 void xorps(XMMRegister dst, AddressLiteral src);
2294 // Data
2296 void cmov32( Condition cc, Register dst, Address src);
2297 void cmov32( Condition cc, Register dst, Register src);
2299 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2301 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2302 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2304 void movoop(Register dst, jobject obj);
2305 void movoop(Address dst, jobject obj);
2307 void movptr(ArrayAddress dst, Register src);
2308 // can this do an lea?
2309 void movptr(Register dst, ArrayAddress src);
2311 void movptr(Register dst, Address src);
2313 void movptr(Register dst, AddressLiteral src);
2315 void movptr(Register dst, intptr_t src);
2316 void movptr(Register dst, Register src);
2317 void movptr(Address dst, intptr_t src);
2319 void movptr(Address dst, Register src);
2321 void movptr(Register dst, RegisterOrConstant src) {
2322 if (src.is_constant()) movptr(dst, src.as_constant());
2323 else movptr(dst, src.as_register());
2324 }
2326 #ifdef _LP64
2327 // Generally the next two are only used for moving NULL
2328 // Although there are situations in initializing the mark word where
2329 // they could be used. They are dangerous.
2331 // They only exist on LP64 so that int32_t and intptr_t are not the same
2332 // and we have ambiguous declarations.
2334 void movptr(Address dst, int32_t imm32);
2335 void movptr(Register dst, int32_t imm32);
2336 #endif // _LP64
2338 // to avoid hiding movl
2339 void mov32(AddressLiteral dst, Register src);
2340 void mov32(Register dst, AddressLiteral src);
2342 // to avoid hiding movb
2343 void movbyte(ArrayAddress dst, int src);
2345 // Can push value or effective address
2346 void pushptr(AddressLiteral src);
2348 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2349 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2351 void pushoop(jobject obj);
2353 // sign extend as need a l to ptr sized element
2354 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2355 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2357 // IndexOf strings.
2358 // Small strings are loaded through stack if they cross page boundary.
2359 void string_indexof(Register str1, Register str2,
2360 Register cnt1, Register cnt2,
2361 int int_cnt2, Register result,
2362 XMMRegister vec, Register tmp);
2364 // IndexOf for constant substrings with size >= 8 elements
2365 // which don't need to be loaded through stack.
2366 void string_indexofC8(Register str1, Register str2,
2367 Register cnt1, Register cnt2,
2368 int int_cnt2, Register result,
2369 XMMRegister vec, Register tmp);
2371 // Smallest code: we don't need to load through stack,
2372 // check string tail.
2374 // Compare strings.
2375 void string_compare(Register str1, Register str2,
2376 Register cnt1, Register cnt2, Register result,
2377 XMMRegister vec1);
2379 // Compare char[] arrays.
2380 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2381 Register limit, Register result, Register chr,
2382 XMMRegister vec1, XMMRegister vec2);
2384 // Fill primitive arrays
2385 void generate_fill(BasicType t, bool aligned,
2386 Register to, Register value, Register count,
2387 Register rtmp, XMMRegister xtmp);
2389 #undef VIRTUAL
2391 };
2393 /**
2394 * class SkipIfEqual:
2395 *
2396 * Instantiating this class will result in assembly code being output that will
2397 * jump around any code emitted between the creation of the instance and it's
2398 * automatic destruction at the end of a scope block, depending on the value of
2399 * the flag passed to the constructor, which will be checked at run-time.
2400 */
2401 class SkipIfEqual {
2402 private:
2403 MacroAssembler* _masm;
2404 Label _label;
2406 public:
2407 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2408 ~SkipIfEqual();
2409 };
2411 #ifdef ASSERT
2412 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2413 #endif
2415 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP