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src/cpu/ppc/vm/assembler_ppc.hpp@67fa91961822
src/cpu/ppc/vm/assembler_ppc.hpp
Wed, 11 Dec 2013 00:06:11 +0100
- author
- goetz
- date
- Wed, 11 Dec 2013 00:06:11 +0100
- changeset 6495
- 67fa91961822
- parent 6458
- ec28f9c041ff
- child 6511
- 31e80afe3fed
- permissions
- -rw-r--r--
8029940: PPC64 (part 122): C2 compiler port
Reviewed-by: kvn
1 /*
2 * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2013 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP
27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP
29 #include "asm/register.hpp"
31 // Address is an abstraction used to represent a memory location
32 // as used in assembler instructions.
33 // PPC instructions grok either baseReg + indexReg or baseReg + disp.
34 // So far we do not use this as simplification by this class is low
35 // on PPC with its simple addressing mode. Use RegisterOrConstant to
36 // represent an offset.
37 class Address VALUE_OBJ_CLASS_SPEC {
38 };
40 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
41 private:
42 address _address;
43 RelocationHolder _rspec;
45 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
46 switch (rtype) {
47 case relocInfo::external_word_type:
48 return external_word_Relocation::spec(addr);
49 case relocInfo::internal_word_type:
50 return internal_word_Relocation::spec(addr);
51 case relocInfo::opt_virtual_call_type:
52 return opt_virtual_call_Relocation::spec();
53 case relocInfo::static_call_type:
54 return static_call_Relocation::spec();
55 case relocInfo::runtime_call_type:
56 return runtime_call_Relocation::spec();
57 case relocInfo::none:
58 return RelocationHolder();
59 default:
60 ShouldNotReachHere();
61 return RelocationHolder();
62 }
63 }
65 protected:
66 // creation
67 AddressLiteral() : _address(NULL), _rspec(NULL) {}
69 public:
70 AddressLiteral(address addr, RelocationHolder const& rspec)
71 : _address(addr),
72 _rspec(rspec) {}
74 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
75 : _address((address) addr),
76 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
78 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
79 : _address((address) addr),
80 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
82 intptr_t value() const { return (intptr_t) _address; }
84 const RelocationHolder& rspec() const { return _rspec; }
85 };
87 // Argument is an abstraction used to represent an outgoing
88 // actual argument or an incoming formal parameter, whether
89 // it resides in memory or in a register, in a manner consistent
90 // with the PPC Application Binary Interface, or ABI. This is
91 // often referred to as the native or C calling convention.
93 class Argument VALUE_OBJ_CLASS_SPEC {
94 private:
95 int _number; // The number of the argument.
96 public:
97 enum {
98 // Only 8 registers may contain integer parameters.
99 n_register_parameters = 8,
100 // Can have up to 8 floating registers.
101 n_float_register_parameters = 8,
103 // PPC C calling conventions.
104 // The first eight arguments are passed in int regs if they are int.
105 n_int_register_parameters_c = 8,
106 // The first thirteen float arguments are passed in float regs.
107 n_float_register_parameters_c = 13,
108 // Only the first 8 parameters are not placed on the stack. Aix disassembly
109 // shows that xlC places all float args after argument 8 on the stack AND
110 // in a register. This is not documented, but we follow this convention, too.
111 n_regs_not_on_stack_c = 8,
112 };
113 // creation
114 Argument(int number) : _number(number) {}
116 int number() const { return _number; }
118 // Locating register-based arguments:
119 bool is_register() const { return _number < n_register_parameters; }
121 Register as_register() const {
122 assert(is_register(), "must be a register argument");
123 return as_Register(number() + R3_ARG1->encoding());
124 }
125 };
127 // A ppc64 function descriptor.
128 struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC {
129 private:
130 address _entry;
131 address _toc;
132 address _env;
134 public:
135 inline address entry() const { return _entry; }
136 inline address toc() const { return _toc; }
137 inline address env() const { return _env; }
139 inline void set_entry(address entry) { _entry = entry; }
140 inline void set_toc( address toc) { _toc = toc; }
141 inline void set_env( address env) { _env = env; }
143 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
144 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); }
145 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); }
147 // Friend functions can be called without loading toc and env.
148 enum {
149 friend_toc = 0xcafe,
150 friend_env = 0xc0de
151 };
153 inline bool is_friend_function() const {
154 return (toc() == (address) friend_toc) && (env() == (address) friend_env);
155 }
157 // Constructor for stack-allocated instances.
158 FunctionDescriptor() {
159 _entry = (address) 0xbad;
160 _toc = (address) 0xbad;
161 _env = (address) 0xbad;
162 }
163 };
165 class Assembler : public AbstractAssembler {
166 protected:
167 // Displacement routines
168 static void print_instruction(int inst);
169 static int patched_branch(int dest_pos, int inst, int inst_pos);
170 static int branch_destination(int inst, int pos);
172 friend class AbstractAssembler;
174 // Code patchers need various routines like inv_wdisp()
175 friend class NativeInstruction;
176 friend class NativeGeneralJump;
177 friend class Relocation;
179 public:
181 enum shifts {
182 XO_21_29_SHIFT = 2,
183 XO_21_30_SHIFT = 1,
184 XO_27_29_SHIFT = 2,
185 XO_30_31_SHIFT = 0,
186 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15
187 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20
188 RS_SHIFT = 21u, // RS field in bits 21 -- 25
189 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31
190 };
192 enum opcdxos_masks {
193 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
194 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
195 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
196 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
197 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT),
198 // trap instructions
199 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT),
200 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT),
201 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
202 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
203 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
204 STD_OPCODE_MASK = LD_OPCODE_MASK,
205 STDU_OPCODE_MASK = STD_OPCODE_MASK,
206 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
207 STDUX_OPCODE_MASK = STDX_OPCODE_MASK,
208 STW_OPCODE_MASK = (63u << OPCODE_SHIFT),
209 STWU_OPCODE_MASK = STW_OPCODE_MASK,
210 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
211 STWUX_OPCODE_MASK = STWX_OPCODE_MASK,
212 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT),
213 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT),
214 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT),
215 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
216 };
218 enum opcdxos {
219 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1),
220 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1),
221 ADDI_OPCODE = (14u << OPCODE_SHIFT),
222 ADDIS_OPCODE = (15u << OPCODE_SHIFT),
223 ADDIC__OPCODE = (13u << OPCODE_SHIFT),
224 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1),
225 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1),
226 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1),
227 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1),
228 SUBFIC_OPCODE = (8u << OPCODE_SHIFT),
229 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
230 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1),
231 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1),
232 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1),
233 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1),
234 MULLI_OPCODE = (7u << OPCODE_SHIFT),
235 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1),
236 ANDI_OPCODE = (28u << OPCODE_SHIFT),
237 ANDIS_OPCODE = (29u << OPCODE_SHIFT),
238 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1),
239 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1),
240 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1),
241 ORI_OPCODE = (24u << OPCODE_SHIFT),
242 ORIS_OPCODE = (25u << OPCODE_SHIFT),
243 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1),
244 XORI_OPCODE = (26u << OPCODE_SHIFT),
245 XORIS_OPCODE = (27u << OPCODE_SHIFT),
247 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1),
249 RLWINM_OPCODE = (21u << OPCODE_SHIFT),
250 CLRRWI_OPCODE = RLWINM_OPCODE,
251 CLRLWI_OPCODE = RLWINM_OPCODE,
253 RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
255 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1),
256 SLWI_OPCODE = RLWINM_OPCODE,
257 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1),
258 SRWI_OPCODE = RLWINM_OPCODE,
259 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1),
260 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1),
262 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
263 CMPI_OPCODE = (11u << OPCODE_SHIFT),
264 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
265 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
267 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
269 MTLR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT),
270 MFLR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT),
272 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
273 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
274 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
276 // condition register logic instructions
277 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
278 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
279 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
280 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1),
281 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1),
282 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1),
283 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
284 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1),
286 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1),
287 BXX_OPCODE = (18u << OPCODE_SHIFT),
288 BCXX_OPCODE = (16u << OPCODE_SHIFT),
290 // CTR-related opcodes
291 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
292 MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
293 MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
296 LWZ_OPCODE = (32u << OPCODE_SHIFT),
297 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
298 LWZU_OPCODE = (33u << OPCODE_SHIFT),
300 LHA_OPCODE = (42u << OPCODE_SHIFT),
301 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1),
302 LHAU_OPCODE = (43u << OPCODE_SHIFT),
304 LHZ_OPCODE = (40u << OPCODE_SHIFT),
305 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1),
306 LHZU_OPCODE = (41u << OPCODE_SHIFT),
308 LBZ_OPCODE = (34u << OPCODE_SHIFT),
309 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1),
310 LBZU_OPCODE = (35u << OPCODE_SHIFT),
312 STW_OPCODE = (36u << OPCODE_SHIFT),
313 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1),
314 STWU_OPCODE = (37u << OPCODE_SHIFT),
315 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
317 STH_OPCODE = (44u << OPCODE_SHIFT),
318 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1),
319 STHU_OPCODE = (45u << OPCODE_SHIFT),
321 STB_OPCODE = (38u << OPCODE_SHIFT),
322 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1),
323 STBU_OPCODE = (39u << OPCODE_SHIFT),
325 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
326 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
327 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM
329 // 32 bit opcode encodings
331 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM
332 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
334 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM
336 // 64 bit opcode encodings
338 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
339 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
340 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM
342 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM
343 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM
344 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM
345 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
347 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM
348 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM
349 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM
350 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM
352 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
354 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM
355 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM
356 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM
358 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM
359 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM
360 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM
361 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM
363 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM
364 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
365 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
368 // opcodes only used for floating arithmetic
369 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1),
370 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1),
371 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1),
372 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1),
373 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1),
374 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1),
375 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
376 // on Power7. Do not use.
377 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1),
378 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1),
379 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1),
380 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1),
381 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1),
382 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1),
383 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1),
384 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1),
385 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1),
386 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1),
387 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1),
388 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1),
389 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1),
391 // PPC64-internal FPU conversion opcodes
392 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1),
393 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1),
394 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1),
395 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1),
396 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1),
397 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1),
398 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1),
400 // WARNING: using fmadd results in a non-compliant vm. Some floating
401 // point tck tests will fail.
402 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1),
403 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1),
404 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1),
405 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1),
406 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1),
407 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1),
408 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1),
409 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1),
411 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1),
412 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1),
413 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1),
414 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1),
415 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
416 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),
418 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
419 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
420 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
421 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
422 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
423 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),
425 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
426 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM
428 // Vector instruction support for >= Power6
429 // Vector Storage Access
430 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
431 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
432 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
433 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
434 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
435 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
436 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
437 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
438 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
439 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
440 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
441 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
443 // Vector Permute and Formatting
444 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
445 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
446 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
447 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
448 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
449 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
450 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
451 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
452 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
453 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
454 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
455 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
456 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
457 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
458 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
460 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
461 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
462 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ),
463 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ),
464 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ),
465 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ),
467 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ),
468 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ),
469 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ),
470 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ),
471 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
472 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
474 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
475 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
477 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ),
478 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ),
479 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ),
480 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ),
481 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ),
483 // Vector Integer
484 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ),
485 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ),
486 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ),
487 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ),
488 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
489 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
490 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
491 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
492 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
493 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
494 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ),
495 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ),
496 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ),
497 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ),
498 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ),
499 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ),
500 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ),
501 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ),
502 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ),
503 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ),
505 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ),
506 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ),
507 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ),
508 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ),
509 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ),
510 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ),
511 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ),
512 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ),
513 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ),
514 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ),
515 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ),
516 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ),
517 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ),
518 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ),
519 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ),
520 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ),
521 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ),
523 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ),
524 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ),
525 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ),
526 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ),
527 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ),
529 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ),
530 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ),
531 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ),
532 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ),
533 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ),
534 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ),
536 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ),
537 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ),
538 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ),
539 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ),
540 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ),
541 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ),
542 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ),
543 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ),
544 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ),
545 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ),
546 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ),
547 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ),
549 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ),
550 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ),
551 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ),
552 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ),
553 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ),
554 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ),
555 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ),
556 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ),
557 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ),
559 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ),
560 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ),
561 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ),
562 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ),
563 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ),
564 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ),
565 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ),
566 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ),
567 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ),
568 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ),
569 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ),
570 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ),
571 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ),
572 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ),
573 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ),
574 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ),
575 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ),
577 // Vector Floating-Point
578 // not implemented yet
580 // Vector Status and Control
581 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
582 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
584 // Icache and dcache related instructions
585 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
586 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
587 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
588 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1),
590 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
591 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
592 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
594 // Instruction synchronization
595 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
596 // Memory barriers
597 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
598 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
600 // Trap instructions
601 TDI_OPCODE = (2u << OPCODE_SHIFT),
602 TWI_OPCODE = (3u << OPCODE_SHIFT),
603 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
604 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
606 // Atomics.
607 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
608 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
609 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
610 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1)
612 };
614 // Trap instructions TO bits
615 enum trap_to_bits {
616 // single bits
617 traptoLessThanSigned = 1 << 4, // 0, left end
618 traptoGreaterThanSigned = 1 << 3,
619 traptoEqual = 1 << 2,
620 traptoLessThanUnsigned = 1 << 1,
621 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
623 // compound ones
624 traptoUnconditional = (traptoLessThanSigned |
625 traptoGreaterThanSigned |
626 traptoEqual |
627 traptoLessThanUnsigned |
628 traptoGreaterThanUnsigned)
629 };
631 // Branch hints BH field
632 enum branch_hint_bh {
633 // bclr cases:
634 bhintbhBCLRisReturn = 0,
635 bhintbhBCLRisNotReturnButSame = 1,
636 bhintbhBCLRisNotPredictable = 3,
638 // bcctr cases:
639 bhintbhBCCTRisNotReturnButSame = 0,
640 bhintbhBCCTRisNotPredictable = 3
641 };
643 // Branch prediction hints AT field
644 enum branch_hint_at {
645 bhintatNoHint = 0, // at=00
646 bhintatIsNotTaken = 2, // at=10
647 bhintatIsTaken = 3 // at=11
648 };
650 // Branch prediction hints
651 enum branch_hint_concept {
652 // Use the same encoding as branch_hint_at to simply code.
653 bhintNoHint = bhintatNoHint,
654 bhintIsNotTaken = bhintatIsNotTaken,
655 bhintIsTaken = bhintatIsTaken
656 };
658 // Used in BO field of branch instruction.
659 enum branch_condition {
660 bcondCRbiIs0 = 4, // bo=001at
661 bcondCRbiIs1 = 12, // bo=011at
662 bcondAlways = 20 // bo=10100
663 };
665 // Branch condition with combined prediction hints.
666 enum branch_condition_with_hint {
667 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint,
668 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
669 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken,
670 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint,
671 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
672 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken,
673 };
675 // Elemental Memory Barriers (>=Power 8)
676 enum Elemental_Membar_mask_bits {
677 StoreStore = 1 << 0,
678 StoreLoad = 1 << 1,
679 LoadStore = 1 << 2,
680 LoadLoad = 1 << 3
681 };
683 // Branch prediction hints.
684 inline static int add_bhint_to_boint(const int bhint, const int boint) {
685 switch (boint) {
686 case bcondCRbiIs0:
687 case bcondCRbiIs1:
688 // branch_hint and branch_hint_at have same encodings
689 assert( (int)bhintNoHint == (int)bhintatNoHint
690 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
691 && (int)bhintIsTaken == (int)bhintatIsTaken,
692 "wrong encodings");
693 assert((bhint & 0x03) == bhint, "wrong encodings");
694 return (boint & ~0x03) | bhint;
695 case bcondAlways:
696 // no branch_hint
697 return boint;
698 default:
699 ShouldNotReachHere();
700 return 0;
701 }
702 }
704 // Extract bcond from boint.
705 inline static int inv_boint_bcond(const int boint) {
706 int r_bcond = boint & ~0x03;
707 assert(r_bcond == bcondCRbiIs0 ||
708 r_bcond == bcondCRbiIs1 ||
709 r_bcond == bcondAlways,
710 "bad branch condition");
711 return r_bcond;
712 }
714 // Extract bhint from boint.
715 inline static int inv_boint_bhint(const int boint) {
716 int r_bhint = boint & 0x03;
717 assert(r_bhint == bhintatNoHint ||
718 r_bhint == bhintatIsNotTaken ||
719 r_bhint == bhintatIsTaken,
720 "bad branch hint");
721 return r_bhint;
722 }
724 // Calculate opposite of given bcond.
725 inline static int opposite_bcond(const int bcond) {
726 switch (bcond) {
727 case bcondCRbiIs0:
728 return bcondCRbiIs1;
729 case bcondCRbiIs1:
730 return bcondCRbiIs0;
731 default:
732 ShouldNotReachHere();
733 return 0;
734 }
735 }
737 // Calculate opposite of given bhint.
738 inline static int opposite_bhint(const int bhint) {
739 switch (bhint) {
740 case bhintatNoHint:
741 return bhintatNoHint;
742 case bhintatIsNotTaken:
743 return bhintatIsTaken;
744 case bhintatIsTaken:
745 return bhintatIsNotTaken;
746 default:
747 ShouldNotReachHere();
748 return 0;
749 }
750 }
752 // PPC branch instructions
753 enum ppcops {
754 b_op = 18,
755 bc_op = 16,
756 bcr_op = 19
757 };
759 enum Condition {
760 negative = 0,
761 less = 0,
762 positive = 1,
763 greater = 1,
764 zero = 2,
765 equal = 2,
766 summary_overflow = 3,
767 };
769 public:
770 // Helper functions for groups of instructions
772 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
774 // instruction must start at passed address
775 static int instr_len(unsigned char *instr) { return BytesPerInstWord; }
777 // instruction must be left-justified in argument
778 static int instr_len(unsigned long instr) { return BytesPerInstWord; }
780 // longest instructions
781 static int instr_maxlen() { return BytesPerInstWord; }
783 // Test if x is within signed immediate range for nbits.
784 static bool is_simm(int x, unsigned int nbits) {
785 assert(0 < nbits && nbits < 32, "out of bounds");
786 const int min = -( ((int)1) << nbits-1 );
787 const int maxplus1 = ( ((int)1) << nbits-1 );
788 return min <= x && x < maxplus1;
789 }
791 static bool is_simm(jlong x, unsigned int nbits) {
792 assert(0 < nbits && nbits < 64, "out of bounds");
793 const jlong min = -( ((jlong)1) << nbits-1 );
794 const jlong maxplus1 = ( ((jlong)1) << nbits-1 );
795 return min <= x && x < maxplus1;
796 }
798 // Test if x is within unsigned immediate range for nbits
799 static bool is_uimm(int x, unsigned int nbits) {
800 assert(0 < nbits && nbits < 32, "out of bounds");
801 const int maxplus1 = ( ((int)1) << nbits );
802 return 0 <= x && x < maxplus1;
803 }
805 static bool is_uimm(jlong x, unsigned int nbits) {
806 assert(0 < nbits && nbits < 64, "out of bounds");
807 const jlong maxplus1 = ( ((jlong)1) << nbits );
808 return 0 <= x && x < maxplus1;
809 }
811 protected:
812 // helpers
814 // X is supposed to fit in a field "nbits" wide
815 // and be sign-extended. Check the range.
816 static void assert_signed_range(intptr_t x, int nbits) {
817 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
818 "value out of range");
819 }
821 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
822 assert((x & 3) == 0, "not word aligned");
823 assert_signed_range(x, nbits + 2);
824 }
826 static void assert_unsigned_const(int x, int nbits) {
827 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
828 }
830 static int fmask(juint hi_bit, juint lo_bit) {
831 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
832 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
833 }
835 // inverse of u_field
836 static int inv_u_field(int x, int hi_bit, int lo_bit) {
837 juint r = juint(x) >> lo_bit;
838 r &= fmask(hi_bit, lo_bit);
839 return int(r);
840 }
842 // signed version: extract from field and sign-extend
843 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
844 x = x << (31-hi_bit);
845 x = x >> (31-hi_bit+lo_bit);
846 return x;
847 }
849 static int u_field(int x, int hi_bit, int lo_bit) {
850 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
851 int r = x << lo_bit;
852 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
853 return r;
854 }
856 // Same as u_field for signed values
857 static int s_field(int x, int hi_bit, int lo_bit) {
858 int nbits = hi_bit - lo_bit + 1;
859 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
860 "value out of range");
861 x &= fmask(hi_bit, lo_bit);
862 int r = x << lo_bit;
863 return r;
864 }
866 // inv_op for ppc instructions
867 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
869 // Determine target address from li, bd field of branch instruction.
870 static intptr_t inv_li_field(int x) {
871 intptr_t r = inv_s_field_ppc(x, 25, 2);
872 r = (r << 2);
873 return r;
874 }
875 static intptr_t inv_bd_field(int x, intptr_t pos) {
876 intptr_t r = inv_s_field_ppc(x, 15, 2);
877 r = (r << 2) + pos;
878 return r;
879 }
881 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
882 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
883 // Extract instruction fields from instruction words.
884 public:
885 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); }
886 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); }
887 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); }
888 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
889 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); }
890 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
891 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
892 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; }
893 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); }
894 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); }
895 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); }
896 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); }
897 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
898 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }
900 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
901 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
903 // instruction fields
904 static int aa( int x) { return opp_u_field(x, 30, 30); }
905 static int ba( int x) { return opp_u_field(x, 15, 11); }
906 static int bb( int x) { return opp_u_field(x, 20, 16); }
907 static int bc( int x) { return opp_u_field(x, 25, 21); }
908 static int bd( int x) { return opp_s_field(x, 29, 16); }
909 static int bf( ConditionRegister cr) { return bf(cr->encoding()); }
910 static int bf( int x) { return opp_u_field(x, 8, 6); }
911 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); }
912 static int bfa( int x) { return opp_u_field(x, 13, 11); }
913 static int bh( int x) { return opp_u_field(x, 20, 19); }
914 static int bi( int x) { return opp_u_field(x, 15, 11); }
915 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
916 static int bo( int x) { return opp_u_field(x, 10, 6); }
917 static int bt( int x) { return opp_u_field(x, 10, 6); }
918 static int d1( int x) { return opp_s_field(x, 31, 16); }
919 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
920 static int eh( int x) { return opp_u_field(x, 31, 31); }
921 static int flm( int x) { return opp_u_field(x, 14, 7); }
922 static int fra( FloatRegister r) { return fra(r->encoding());}
923 static int frb( FloatRegister r) { return frb(r->encoding());}
924 static int frc( FloatRegister r) { return frc(r->encoding());}
925 static int frs( FloatRegister r) { return frs(r->encoding());}
926 static int frt( FloatRegister r) { return frt(r->encoding());}
927 static int fra( int x) { return opp_u_field(x, 15, 11); }
928 static int frb( int x) { return opp_u_field(x, 20, 16); }
929 static int frc( int x) { return opp_u_field(x, 25, 21); }
930 static int frs( int x) { return opp_u_field(x, 10, 6); }
931 static int frt( int x) { return opp_u_field(x, 10, 6); }
932 static int fxm( int x) { return opp_u_field(x, 19, 12); }
933 static int l10( int x) { return opp_u_field(x, 10, 10); }
934 static int l15( int x) { return opp_u_field(x, 15, 15); }
935 static int l910( int x) { return opp_u_field(x, 10, 9); }
936 static int e1215( int x) { return opp_u_field(x, 15, 12); }
937 static int lev( int x) { return opp_u_field(x, 26, 20); }
938 static int li( int x) { return opp_s_field(x, 29, 6); }
939 static int lk( int x) { return opp_u_field(x, 31, 31); }
940 static int mb2125( int x) { return opp_u_field(x, 25, 21); }
941 static int me2630( int x) { return opp_u_field(x, 30, 26); }
942 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
943 static int me2126( int x) { return mb2126(x); }
944 static int nb( int x) { return opp_u_field(x, 20, 16); }
945 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes
946 static int oe( int x) { return opp_u_field(x, 21, 21); }
947 static int ra( Register r) { return ra(r->encoding()); }
948 static int ra( int x) { return opp_u_field(x, 15, 11); }
949 static int rb( Register r) { return rb(r->encoding()); }
950 static int rb( int x) { return opp_u_field(x, 20, 16); }
951 static int rc( int x) { return opp_u_field(x, 31, 31); }
952 static int rs( Register r) { return rs(r->encoding()); }
953 static int rs( int x) { return opp_u_field(x, 10, 6); }
954 // we don't want to use R0 in memory accesses, because it has value `0' then
955 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
956 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); }
958 // register r is target
959 static int rt( Register r) { return rs(r); }
960 static int rt( int x) { return rs(x); }
961 static int rta( Register r) { return ra(r); }
962 static int rta0mem( Register r) { rta(r); return ra0mem(r); }
964 static int sh1620( int x) { return opp_u_field(x, 20, 16); }
965 static int sh30( int x) { return opp_u_field(x, 30, 30); }
966 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
967 static int si( int x) { return opp_s_field(x, 31, 16); }
968 static int spr( int x) { return opp_u_field(x, 20, 11); }
969 static int sr( int x) { return opp_u_field(x, 15, 12); }
970 static int tbr( int x) { return opp_u_field(x, 20, 11); }
971 static int th( int x) { return opp_u_field(x, 10, 7); }
972 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); }
973 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
974 static int to( int x) { return opp_u_field(x, 10, 6); }
975 static int u( int x) { return opp_u_field(x, 19, 16); }
976 static int ui( int x) { return opp_u_field(x, 31, 16); }
978 // Support vector instructions for >= Power6.
979 static int vra( int x) { return opp_u_field(x, 15, 11); }
980 static int vrb( int x) { return opp_u_field(x, 20, 16); }
981 static int vrc( int x) { return opp_u_field(x, 25, 21); }
982 static int vrs( int x) { return opp_u_field(x, 10, 6); }
983 static int vrt( int x) { return opp_u_field(x, 10, 6); }
985 static int vra( VectorRegister r) { return vra(r->encoding());}
986 static int vrb( VectorRegister r) { return vrb(r->encoding());}
987 static int vrc( VectorRegister r) { return vrc(r->encoding());}
988 static int vrs( VectorRegister r) { return vrs(r->encoding());}
989 static int vrt( VectorRegister r) { return vrt(r->encoding());}
991 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
992 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
993 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
994 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions
996 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
997 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
998 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
999 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
1000 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
1001 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
1002 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes
1004 protected:
1005 // Compute relative address for branch.
1006 static intptr_t disp(intptr_t x, intptr_t off) {
1007 int xx = x - off;
1008 xx = xx >> 2;
1009 return xx;
1010 }
1012 public:
1013 // signed immediate, in low bits, nbits long
1014 static int simm(int x, int nbits) {
1015 assert_signed_range(x, nbits);
1016 return x & ((1 << nbits) - 1);
1017 }
1019 // unsigned immediate, in low bits, nbits long
1020 static int uimm(int x, int nbits) {
1021 assert_unsigned_const(x, nbits);
1022 return x & ((1 << nbits) - 1);
1023 }
1025 static void set_imm(int* instr, short s) {
1026 short* p = ((short *)instr) + 1;
1027 *p = s;
1028 }
1030 static int get_imm(address a, int instruction_number) {
1031 short imm;
1032 short *p =((short *)a)+2*instruction_number+1;
1033 imm = *p;
1034 return (int)imm;
1035 }
1037 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); }
1038 static inline int lo16_unsigned(int x) { return x & 0xffff; }
1040 protected:
1042 // Extract the top 32 bits in a 64 bit word.
1043 static int32_t hi32(int64_t x) {
1044 int32_t r = int32_t((uint64_t)x >> 32);
1045 return r;
1046 }
1048 public:
1050 static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1051 return ((addr + (a - 1)) & ~(a - 1));
1052 }
1054 static inline bool is_aligned(unsigned int addr, unsigned int a) {
1055 return (0 == addr % a);
1056 }
1058 void flush() {
1059 AbstractAssembler::flush();
1060 }
1062 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
1063 inline void emit_data(int);
1064 inline void emit_data(int, RelocationHolder const&);
1065 inline void emit_data(int, relocInfo::relocType rtype);
1067 // Emit an address.
1068 inline address emit_addr(const address addr = NULL);
1070 // Emit a function descriptor with the specified entry point, TOC,
1071 // and ENV. If the entry point is NULL, the descriptor will point
1072 // just past the descriptor.
1073 // Use values from friend functions as defaults.
1074 inline address emit_fd(address entry = NULL,
1075 address toc = (address) FunctionDescriptor::friend_toc,
1076 address env = (address) FunctionDescriptor::friend_env);
1078 /////////////////////////////////////////////////////////////////////////////////////
1079 // PPC instructions
1080 /////////////////////////////////////////////////////////////////////////////////////
1082 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1083 // immediates. The normal instruction encoders enforce that r0 is not
1084 // passed to them. Use either extended mnemonics encoders or the special ra0
1085 // versions.
1087 // Issue an illegal instruction.
1088 inline void illtrap();
1089 static inline bool is_illtrap(int x);
1091 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1092 inline void addi( Register d, Register a, int si16);
1093 inline void addis(Register d, Register a, int si16);
1094 private:
1095 inline void addi_r0ok( Register d, Register a, int si16);
1096 inline void addis_r0ok(Register d, Register a, int si16);
1097 public:
1098 inline void addic_( Register d, Register a, int si16);
1099 inline void subfic( Register d, Register a, int si16);
1100 inline void add( Register d, Register a, Register b);
1101 inline void add_( Register d, Register a, Register b);
1102 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec.
1103 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability.
1104 inline void subf_( Register d, Register a, Register b);
1105 inline void addc( Register d, Register a, Register b);
1106 inline void addc_( Register d, Register a, Register b);
1107 inline void subfc( Register d, Register a, Register b);
1108 inline void subfc_( Register d, Register a, Register b);
1109 inline void adde( Register d, Register a, Register b);
1110 inline void adde_( Register d, Register a, Register b);
1111 inline void subfe( Register d, Register a, Register b);
1112 inline void subfe_( Register d, Register a, Register b);
1113 inline void neg( Register d, Register a);
1114 inline void neg_( Register d, Register a);
1115 inline void mulli( Register d, Register a, int si16);
1116 inline void mulld( Register d, Register a, Register b);
1117 inline void mulld_( Register d, Register a, Register b);
1118 inline void mullw( Register d, Register a, Register b);
1119 inline void mullw_( Register d, Register a, Register b);
1120 inline void mulhw( Register d, Register a, Register b);
1121 inline void mulhw_( Register d, Register a, Register b);
1122 inline void mulhd( Register d, Register a, Register b);
1123 inline void mulhd_( Register d, Register a, Register b);
1124 inline void mulhdu( Register d, Register a, Register b);
1125 inline void mulhdu_(Register d, Register a, Register b);
1126 inline void divd( Register d, Register a, Register b);
1127 inline void divd_( Register d, Register a, Register b);
1128 inline void divw( Register d, Register a, Register b);
1129 inline void divw_( Register d, Register a, Register b);
1131 // extended mnemonics
1132 inline void li( Register d, int si16);
1133 inline void lis( Register d, int si16);
1134 inline void addir(Register d, int si16, Register a);
1136 static bool is_addi(int x) {
1137 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1138 }
1139 static bool is_addis(int x) {
1140 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1141 }
1142 static bool is_bxx(int x) {
1143 return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1144 }
1145 static bool is_b(int x) {
1146 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1147 }
1148 static bool is_bl(int x) {
1149 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1150 }
1151 static bool is_bcxx(int x) {
1152 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1153 }
1154 static bool is_bxx_or_bcxx(int x) {
1155 return is_bxx(x) || is_bcxx(x);
1156 }
1157 static bool is_bctrl(int x) {
1158 return x == 0x4e800421;
1159 }
1160 static bool is_bctr(int x) {
1161 return x == 0x4e800420;
1162 }
1163 static bool is_bclr(int x) {
1164 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1165 }
1166 static bool is_li(int x) {
1167 return is_addi(x) && inv_ra_field(x)==0;
1168 }
1169 static bool is_lis(int x) {
1170 return is_addis(x) && inv_ra_field(x)==0;
1171 }
1172 static bool is_mtctr(int x) {
1173 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1174 }
1175 static bool is_ld(int x) {
1176 return LD_OPCODE == (x & LD_OPCODE_MASK);
1177 }
1178 static bool is_std(int x) {
1179 return STD_OPCODE == (x & STD_OPCODE_MASK);
1180 }
1181 static bool is_stdu(int x) {
1182 return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1183 }
1184 static bool is_stdx(int x) {
1185 return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1186 }
1187 static bool is_stdux(int x) {
1188 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1189 }
1190 static bool is_stwx(int x) {
1191 return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1192 }
1193 static bool is_stwux(int x) {
1194 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1195 }
1196 static bool is_stw(int x) {
1197 return STW_OPCODE == (x & STW_OPCODE_MASK);
1198 }
1199 static bool is_stwu(int x) {
1200 return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1201 }
1202 static bool is_ori(int x) {
1203 return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1204 };
1205 static bool is_oris(int x) {
1206 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1207 };
1208 static bool is_rldicr(int x) {
1209 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1210 };
1211 static bool is_nop(int x) {
1212 return x == 0x60000000;
1213 }
1214 // endgroup opcode for Power6
1215 static bool is_endgroup(int x) {
1216 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1217 }
1220 private:
1221 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1222 inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1223 inline void cmp( ConditionRegister bf, int l, Register a, Register b);
1224 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1225 inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1227 public:
1228 // extended mnemonics of Compare Instructions
1229 inline void cmpwi( ConditionRegister crx, Register a, int si16);
1230 inline void cmpdi( ConditionRegister crx, Register a, int si16);
1231 inline void cmpw( ConditionRegister crx, Register a, Register b);
1232 inline void cmpd( ConditionRegister crx, Register a, Register b);
1233 inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1234 inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1235 inline void cmplw( ConditionRegister crx, Register a, Register b);
1236 inline void cmpld( ConditionRegister crx, Register a, Register b);
1238 inline void isel( Register d, Register a, Register b, int bc);
1239 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1240 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1241 // Set d = 0 if (cr.cc) equals 1, otherwise b.
1242 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1244 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1245 void andi( Register a, Register s, int ui16); // optimized version
1246 inline void andi_( Register a, Register s, int ui16);
1247 inline void andis_( Register a, Register s, int ui16);
1248 inline void ori( Register a, Register s, int ui16);
1249 inline void oris( Register a, Register s, int ui16);
1250 inline void xori( Register a, Register s, int ui16);
1251 inline void xoris( Register a, Register s, int ui16);
1252 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword
1253 inline void and_( Register a, Register s, Register b);
1254 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1255 // SMT-priority change instruction (see SMT instructions below).
1256 inline void or_unchecked(Register a, Register s, Register b);
1257 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword
1258 inline void or_( Register a, Register s, Register b);
1259 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword
1260 inline void xor_( Register a, Register s, Register b);
1261 inline void nand( Register a, Register s, Register b);
1262 inline void nand_( Register a, Register s, Register b);
1263 inline void nor( Register a, Register s, Register b);
1264 inline void nor_( Register a, Register s, Register b);
1265 inline void andc( Register a, Register s, Register b);
1266 inline void andc_( Register a, Register s, Register b);
1267 inline void orc( Register a, Register s, Register b);
1268 inline void orc_( Register a, Register s, Register b);
1269 inline void extsb( Register a, Register s);
1270 inline void extsh( Register a, Register s);
1271 inline void extsw( Register a, Register s);
1273 // extended mnemonics
1274 inline void nop();
1275 // NOP for FP and BR units (different versions to allow them to be in one group)
1276 inline void fpnop0();
1277 inline void fpnop1();
1278 inline void brnop0();
1279 inline void brnop1();
1280 inline void brnop2();
1282 inline void mr( Register d, Register s);
1283 inline void ori_opt( Register d, int ui16);
1284 inline void oris_opt(Register d, int ui16);
1286 // endgroup opcode for Power6
1287 inline void endgroup();
1289 // count instructions
1290 inline void cntlzw( Register a, Register s);
1291 inline void cntlzw_( Register a, Register s);
1292 inline void cntlzd( Register a, Register s);
1293 inline void cntlzd_( Register a, Register s);
1295 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1296 inline void sld( Register a, Register s, Register b);
1297 inline void sld_( Register a, Register s, Register b);
1298 inline void slw( Register a, Register s, Register b);
1299 inline void slw_( Register a, Register s, Register b);
1300 inline void srd( Register a, Register s, Register b);
1301 inline void srd_( Register a, Register s, Register b);
1302 inline void srw( Register a, Register s, Register b);
1303 inline void srw_( Register a, Register s, Register b);
1304 inline void srad( Register a, Register s, Register b);
1305 inline void srad_( Register a, Register s, Register b);
1306 inline void sraw( Register a, Register s, Register b);
1307 inline void sraw_( Register a, Register s, Register b);
1308 inline void sradi( Register a, Register s, int sh6);
1309 inline void sradi_( Register a, Register s, int sh6);
1310 inline void srawi( Register a, Register s, int sh5);
1311 inline void srawi_( Register a, Register s, int sh5);
1313 // extended mnemonics for Shift Instructions
1314 inline void sldi( Register a, Register s, int sh6);
1315 inline void sldi_( Register a, Register s, int sh6);
1316 inline void slwi( Register a, Register s, int sh5);
1317 inline void slwi_( Register a, Register s, int sh5);
1318 inline void srdi( Register a, Register s, int sh6);
1319 inline void srdi_( Register a, Register s, int sh6);
1320 inline void srwi( Register a, Register s, int sh5);
1321 inline void srwi_( Register a, Register s, int sh5);
1323 inline void clrrdi( Register a, Register s, int ui6);
1324 inline void clrrdi_( Register a, Register s, int ui6);
1325 inline void clrldi( Register a, Register s, int ui6);
1326 inline void clrldi_( Register a, Register s, int ui6);
1327 inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1328 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1329 inline void extrdi( Register a, Register s, int n, int b);
1330 // testbit with condition register
1331 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1333 // rotate instructions
1334 inline void rotldi( Register a, Register s, int n);
1335 inline void rotrdi( Register a, Register s, int n);
1336 inline void rotlwi( Register a, Register s, int n);
1337 inline void rotrwi( Register a, Register s, int n);
1339 // Rotate Instructions
1340 inline void rldic( Register a, Register s, int sh6, int mb6);
1341 inline void rldic_( Register a, Register s, int sh6, int mb6);
1342 inline void rldicr( Register a, Register s, int sh6, int mb6);
1343 inline void rldicr_( Register a, Register s, int sh6, int mb6);
1344 inline void rldicl( Register a, Register s, int sh6, int mb6);
1345 inline void rldicl_( Register a, Register s, int sh6, int mb6);
1346 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5);
1347 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1348 inline void rldimi( Register a, Register s, int sh6, int mb6);
1349 inline void rldimi_( Register a, Register s, int sh6, int mb6);
1350 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5);
1351 inline void insrdi( Register a, Register s, int n, int b);
1352 inline void insrwi( Register a, Register s, int n, int b);
1354 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1355 // 4 bytes
1356 inline void lwzx( Register d, Register s1, Register s2);
1357 inline void lwz( Register d, int si16, Register s1);
1358 inline void lwzu( Register d, int si16, Register s1);
1360 // 4 bytes
1361 inline void lwax( Register d, Register s1, Register s2);
1362 inline void lwa( Register d, int si16, Register s1);
1364 // 2 bytes
1365 inline void lhzx( Register d, Register s1, Register s2);
1366 inline void lhz( Register d, int si16, Register s1);
1367 inline void lhzu( Register d, int si16, Register s1);
1369 // 2 bytes
1370 inline void lhax( Register d, Register s1, Register s2);
1371 inline void lha( Register d, int si16, Register s1);
1372 inline void lhau( Register d, int si16, Register s1);
1374 // 1 byte
1375 inline void lbzx( Register d, Register s1, Register s2);
1376 inline void lbz( Register d, int si16, Register s1);
1377 inline void lbzu( Register d, int si16, Register s1);
1379 // 8 bytes
1380 inline void ldx( Register d, Register s1, Register s2);
1381 inline void ld( Register d, int si16, Register s1);
1382 inline void ldu( Register d, int si16, Register s1);
1384 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
1385 inline void stwx( Register d, Register s1, Register s2);
1386 inline void stw( Register d, int si16, Register s1);
1387 inline void stwu( Register d, int si16, Register s1);
1389 inline void sthx( Register d, Register s1, Register s2);
1390 inline void sth( Register d, int si16, Register s1);
1391 inline void sthu( Register d, int si16, Register s1);
1393 inline void stbx( Register d, Register s1, Register s2);
1394 inline void stb( Register d, int si16, Register s1);
1395 inline void stbu( Register d, int si16, Register s1);
1397 inline void stdx( Register d, Register s1, Register s2);
1398 inline void std( Register d, int si16, Register s1);
1399 inline void stdu( Register d, int si16, Register s1);
1400 inline void stdux(Register s, Register a, Register b);
1402 // PPC 1, section 3.3.13 Move To/From System Register Instructions
1403 inline void mtlr( Register s1);
1404 inline void mflr( Register d);
1405 inline void mtctr(Register s1);
1406 inline void mfctr(Register d);
1407 inline void mtcrf(int fxm, Register s);
1408 inline void mfcr( Register d);
1409 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1410 inline void mtcr( Register s);
1412 // PPC 1, section 2.4.1 Branch Instructions
1413 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1414 inline void b( Label& L);
1415 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1416 inline void bl( Label& L);
1417 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1418 inline void bc( int boint, int biint, Label& L);
1419 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1420 inline void bcl(int boint, int biint, Label& L);
1422 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1423 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1424 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1425 relocInfo::relocType rt = relocInfo::none);
1426 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1427 relocInfo::relocType rt = relocInfo::none);
1429 // helper function for b, bcxx
1430 inline bool is_within_range_of_b(address a, address pc);
1431 inline bool is_within_range_of_bcxx(address a, address pc);
1433 // get the destination of a bxx branch (b, bl, ba, bla)
1434 static inline address bxx_destination(address baddr);
1435 static inline address bxx_destination(int instr, address pc);
1436 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1438 // extended mnemonics for branch instructions
1439 inline void blt(ConditionRegister crx, Label& L);
1440 inline void bgt(ConditionRegister crx, Label& L);
1441 inline void beq(ConditionRegister crx, Label& L);
1442 inline void bso(ConditionRegister crx, Label& L);
1443 inline void bge(ConditionRegister crx, Label& L);
1444 inline void ble(ConditionRegister crx, Label& L);
1445 inline void bne(ConditionRegister crx, Label& L);
1446 inline void bns(ConditionRegister crx, Label& L);
1448 // Branch instructions with static prediction hints.
1449 inline void blt_predict_taken( ConditionRegister crx, Label& L);
1450 inline void bgt_predict_taken( ConditionRegister crx, Label& L);
1451 inline void beq_predict_taken( ConditionRegister crx, Label& L);
1452 inline void bso_predict_taken( ConditionRegister crx, Label& L);
1453 inline void bge_predict_taken( ConditionRegister crx, Label& L);
1454 inline void ble_predict_taken( ConditionRegister crx, Label& L);
1455 inline void bne_predict_taken( ConditionRegister crx, Label& L);
1456 inline void bns_predict_taken( ConditionRegister crx, Label& L);
1457 inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1458 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1459 inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1460 inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1461 inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1462 inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1463 inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1464 inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1466 // for use in conjunction with testbitdi:
1467 inline void btrue( ConditionRegister crx, Label& L);
1468 inline void bfalse(ConditionRegister crx, Label& L);
1470 inline void bltl(ConditionRegister crx, Label& L);
1471 inline void bgtl(ConditionRegister crx, Label& L);
1472 inline void beql(ConditionRegister crx, Label& L);
1473 inline void bsol(ConditionRegister crx, Label& L);
1474 inline void bgel(ConditionRegister crx, Label& L);
1475 inline void blel(ConditionRegister crx, Label& L);
1476 inline void bnel(ConditionRegister crx, Label& L);
1477 inline void bnsl(ConditionRegister crx, Label& L);
1479 // extended mnemonics for Branch Instructions via LR
1480 // We use `blr' for returns.
1481 inline void blr(relocInfo::relocType rt = relocInfo::none);
1483 // extended mnemonics for Branch Instructions with CTR
1484 // bdnz means `decrement CTR and jump to L if CTR is not zero'
1485 inline void bdnz(Label& L);
1486 // Decrement and branch if result is zero.
1487 inline void bdz(Label& L);
1488 // we use `bctr[l]' for jumps/calls in function descriptor glue
1489 // code, e.g. calls to runtime functions
1490 inline void bctr( relocInfo::relocType rt = relocInfo::none);
1491 inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1492 // conditional jumps/branches via CTR
1493 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1494 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1495 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1496 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1498 // condition register logic instructions
1499 inline void crand( int d, int s1, int s2);
1500 inline void crnand(int d, int s1, int s2);
1501 inline void cror( int d, int s1, int s2);
1502 inline void crxor( int d, int s1, int s2);
1503 inline void crnor( int d, int s1, int s2);
1504 inline void creqv( int d, int s1, int s2);
1505 inline void crandc(int d, int s1, int s2);
1506 inline void crorc( int d, int s1, int s2);
1508 // icache and dcache related instructions
1509 inline void icbi( Register s1, Register s2);
1510 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1511 inline void dcbz( Register s1, Register s2);
1512 inline void dcbst( Register s1, Register s2);
1513 inline void dcbf( Register s1, Register s2);
1515 enum ct_cache_specification {
1516 ct_primary_cache = 0,
1517 ct_secondary_cache = 2
1518 };
1519 // dcache read hint
1520 inline void dcbt( Register s1, Register s2);
1521 inline void dcbtct( Register s1, Register s2, int ct);
1522 inline void dcbtds( Register s1, Register s2, int ds);
1523 // dcache write hint
1524 inline void dcbtst( Register s1, Register s2);
1525 inline void dcbtstct(Register s1, Register s2, int ct);
1527 // machine barrier instructions:
1528 //
1529 // - sync two-way memory barrier, aka fence
1530 // - lwsync orders Store|Store,
1531 // Load|Store,
1532 // Load|Load,
1533 // but not Store|Load
1534 // - eieio orders memory accesses for device memory (only)
1535 // - isync invalidates speculatively executed instructions
1536 // From the Power ISA 2.06 documentation:
1537 // "[...] an isync instruction prevents the execution of
1538 // instructions following the isync until instructions
1539 // preceding the isync have completed, [...]"
1540 // From IBM's AIX assembler reference:
1541 // "The isync [...] instructions causes the processor to
1542 // refetch any instructions that might have been fetched
1543 // prior to the isync instruction. The instruction isync
1544 // causes the processor to wait for all previous instructions
1545 // to complete. Then any instructions already fetched are
1546 // discarded and instruction processing continues in the
1547 // environment established by the previous instructions."
1548 //
1549 // semantic barrier instructions:
1550 // (as defined in orderAccess.hpp)
1551 //
1552 // - release orders Store|Store, (maps to lwsync)
1553 // Load|Store
1554 // - acquire orders Load|Store, (maps to lwsync)
1555 // Load|Load
1556 // - fence orders Store|Store, (maps to sync)
1557 // Load|Store,
1558 // Load|Load,
1559 // Store|Load
1560 //
1561 private:
1562 inline void sync(int l);
1563 public:
1564 inline void sync();
1565 inline void lwsync();
1566 inline void ptesync();
1567 inline void eieio();
1568 inline void isync();
1569 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1571 // atomics
1572 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1573 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1574 inline bool lxarx_hint_exclusive_access();
1575 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1576 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1577 inline void stwcx_( Register s, Register a, Register b);
1578 inline void stdcx_( Register s, Register a, Register b);
1580 // Instructions for adjusting thread priority for simultaneous
1581 // multithreading (SMT) on Power5.
1582 private:
1583 inline void smt_prio_very_low();
1584 inline void smt_prio_medium_high();
1585 inline void smt_prio_high();
1587 public:
1588 inline void smt_prio_low();
1589 inline void smt_prio_medium_low();
1590 inline void smt_prio_medium();
1592 // trap instructions
1593 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
1594 // NOT FOR DIRECT USE!!
1595 protected:
1596 inline void tdi_unchecked(int tobits, Register a, int si16);
1597 inline void twi_unchecked(int tobits, Register a, int si16);
1598 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1599 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP
1600 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP
1601 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP
1603 static bool is_tdi(int x, int tobits, int ra, int si16) {
1604 return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
1605 && (tobits == inv_to_field(x))
1606 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1607 && (si16 == inv_si_field(x));
1608 }
1610 static bool is_twi(int x, int tobits, int ra, int si16) {
1611 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1612 && (tobits == inv_to_field(x))
1613 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1614 && (si16 == inv_si_field(x));
1615 }
1617 static bool is_twi(int x, int tobits, int ra) {
1618 return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
1619 && (tobits == inv_to_field(x))
1620 && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
1621 }
1623 static bool is_td(int x, int tobits, int ra, int rb) {
1624 return (TD_OPCODE == (x & TD_OPCODE_MASK))
1625 && (tobits == inv_to_field(x))
1626 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1627 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1628 }
1630 static bool is_tw(int x, int tobits, int ra, int rb) {
1631 return (TW_OPCODE == (x & TW_OPCODE_MASK))
1632 && (tobits == inv_to_field(x))
1633 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
1634 && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
1635 }
1637 public:
1638 // PPC floating point instructions
1639 // PPC 1, section 4.6.2 Floating-Point Load Instructions
1640 inline void lfs( FloatRegister d, int si16, Register a);
1641 inline void lfsu( FloatRegister d, int si16, Register a);
1642 inline void lfsx( FloatRegister d, Register a, Register b);
1643 inline void lfd( FloatRegister d, int si16, Register a);
1644 inline void lfdu( FloatRegister d, int si16, Register a);
1645 inline void lfdx( FloatRegister d, Register a, Register b);
1647 // PPC 1, section 4.6.3 Floating-Point Store Instructions
1648 inline void stfs( FloatRegister s, int si16, Register a);
1649 inline void stfsu( FloatRegister s, int si16, Register a);
1650 inline void stfsx( FloatRegister s, Register a, Register b);
1651 inline void stfd( FloatRegister s, int si16, Register a);
1652 inline void stfdu( FloatRegister s, int si16, Register a);
1653 inline void stfdx( FloatRegister s, Register a, Register b);
1655 // PPC 1, section 4.6.4 Floating-Point Move Instructions
1656 inline void fmr( FloatRegister d, FloatRegister b);
1657 inline void fmr_( FloatRegister d, FloatRegister b);
1659 // inline void mffgpr( FloatRegister d, Register b);
1660 // inline void mftgpr( Register d, FloatRegister b);
1661 inline void cmpb( Register a, Register s, Register b);
1662 inline void popcntb(Register a, Register s);
1663 inline void popcntw(Register a, Register s);
1664 inline void popcntd(Register a, Register s);
1666 inline void fneg( FloatRegister d, FloatRegister b);
1667 inline void fneg_( FloatRegister d, FloatRegister b);
1668 inline void fabs( FloatRegister d, FloatRegister b);
1669 inline void fabs_( FloatRegister d, FloatRegister b);
1670 inline void fnabs( FloatRegister d, FloatRegister b);
1671 inline void fnabs_(FloatRegister d, FloatRegister b);
1673 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
1674 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b);
1675 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
1676 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
1677 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
1678 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b);
1679 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
1680 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
1681 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
1682 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c);
1683 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
1684 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
1685 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
1686 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b);
1687 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
1688 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
1689 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
1691 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
1692 inline void frsp( FloatRegister d, FloatRegister b);
1693 inline void fctid( FloatRegister d, FloatRegister b);
1694 inline void fctidz(FloatRegister d, FloatRegister b);
1695 inline void fctiw( FloatRegister d, FloatRegister b);
1696 inline void fctiwz(FloatRegister d, FloatRegister b);
1697 inline void fcfid( FloatRegister d, FloatRegister b);
1698 inline void fcfids(FloatRegister d, FloatRegister b);
1700 // PPC 1, section 4.6.7 Floating-Point Compare Instructions
1701 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
1703 inline void fsqrt( FloatRegister d, FloatRegister b);
1704 inline void fsqrts(FloatRegister d, FloatRegister b);
1706 // Vector instructions for >= Power6.
1707 inline void lvebx( VectorRegister d, Register s1, Register s2);
1708 inline void lvehx( VectorRegister d, Register s1, Register s2);
1709 inline void lvewx( VectorRegister d, Register s1, Register s2);
1710 inline void lvx( VectorRegister d, Register s1, Register s2);
1711 inline void lvxl( VectorRegister d, Register s1, Register s2);
1712 inline void stvebx( VectorRegister d, Register s1, Register s2);
1713 inline void stvehx( VectorRegister d, Register s1, Register s2);
1714 inline void stvewx( VectorRegister d, Register s1, Register s2);
1715 inline void stvx( VectorRegister d, Register s1, Register s2);
1716 inline void stvxl( VectorRegister d, Register s1, Register s2);
1717 inline void lvsl( VectorRegister d, Register s1, Register s2);
1718 inline void lvsr( VectorRegister d, Register s1, Register s2);
1719 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b);
1720 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b);
1721 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b);
1722 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b);
1723 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b);
1724 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b);
1725 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b);
1726 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b);
1727 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b);
1728 inline void vupkhpx( VectorRegister d, VectorRegister b);
1729 inline void vupkhsb( VectorRegister d, VectorRegister b);
1730 inline void vupkhsh( VectorRegister d, VectorRegister b);
1731 inline void vupklpx( VectorRegister d, VectorRegister b);
1732 inline void vupklsb( VectorRegister d, VectorRegister b);
1733 inline void vupklsh( VectorRegister d, VectorRegister b);
1734 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b);
1735 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b);
1736 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b);
1737 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b);
1738 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b);
1739 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b);
1740 inline void vsplt( VectorRegister d, int ui4, VectorRegister b);
1741 inline void vsplth( VectorRegister d, int ui3, VectorRegister b);
1742 inline void vspltw( VectorRegister d, int ui2, VectorRegister b);
1743 inline void vspltisb( VectorRegister d, int si5);
1744 inline void vspltish( VectorRegister d, int si5);
1745 inline void vspltisw( VectorRegister d, int si5);
1746 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1747 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1748 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
1749 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4);
1750 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b);
1751 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b);
1752 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b);
1753 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1754 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b);
1755 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1756 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b);
1757 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
1758 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
1759 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
1760 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
1761 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
1762 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
1763 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b);
1764 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b);
1765 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b);
1766 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b);
1767 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b);
1768 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b);
1769 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b);
1770 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b);
1771 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b);
1772 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b);
1773 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b);
1774 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b);
1775 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b);
1776 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b);
1777 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b);
1778 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b);
1779 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b);
1780 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b);
1781 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1782 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
1783 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1784 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1785 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1786 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1787 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1788 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1789 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1790 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b);
1791 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
1792 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
1793 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
1794 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
1795 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b);
1796 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b);
1797 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b);
1798 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b);
1799 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b);
1800 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b);
1801 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b);
1802 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b);
1803 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b);
1804 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b);
1805 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b);
1806 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b);
1807 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b);
1808 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b);
1809 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b);
1810 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b);
1811 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b);
1812 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b);
1813 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
1814 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
1815 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
1816 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
1817 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
1818 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
1819 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
1820 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
1821 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
1822 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
1823 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
1824 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
1825 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
1826 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
1827 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
1828 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
1829 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
1830 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
1831 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b);
1832 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
1833 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
1834 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
1835 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
1836 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
1837 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b);
1838 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b);
1839 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
1840 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
1841 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
1842 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
1843 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
1844 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
1845 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
1846 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
1847 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1848 // Vector Floating-Point not implemented yet
1849 inline void mtvscr( VectorRegister b);
1850 inline void mfvscr( VectorRegister d);
1852 // The following encoders use r0 as second operand. These instructions
1853 // read r0 as '0'.
1854 inline void lwzx( Register d, Register s2);
1855 inline void lwz( Register d, int si16);
1856 inline void lwax( Register d, Register s2);
1857 inline void lwa( Register d, int si16);
1858 inline void lhzx( Register d, Register s2);
1859 inline void lhz( Register d, int si16);
1860 inline void lhax( Register d, Register s2);
1861 inline void lha( Register d, int si16);
1862 inline void lbzx( Register d, Register s2);
1863 inline void lbz( Register d, int si16);
1864 inline void ldx( Register d, Register s2);
1865 inline void ld( Register d, int si16);
1866 inline void stwx( Register d, Register s2);
1867 inline void stw( Register d, int si16);
1868 inline void sthx( Register d, Register s2);
1869 inline void sth( Register d, int si16);
1870 inline void stbx( Register d, Register s2);
1871 inline void stb( Register d, int si16);
1872 inline void stdx( Register d, Register s2);
1873 inline void std( Register d, int si16);
1875 // PPC 2, section 3.2.1 Instruction Cache Instructions
1876 inline void icbi( Register s2);
1877 // PPC 2, section 3.2.2 Data Cache Instructions
1878 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
1879 inline void dcbz( Register s2);
1880 inline void dcbst( Register s2);
1881 inline void dcbf( Register s2);
1882 // dcache read hint
1883 inline void dcbt( Register s2);
1884 inline void dcbtct( Register s2, int ct);
1885 inline void dcbtds( Register s2, int ds);
1886 // dcache write hint
1887 inline void dcbtst( Register s2);
1888 inline void dcbtstct(Register s2, int ct);
1890 // Atomics: use ra0mem to disallow R0 as base.
1891 inline void lwarx_unchecked(Register d, Register b, int eh1);
1892 inline void ldarx_unchecked(Register d, Register b, int eh1);
1893 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
1894 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
1895 inline void stwcx_(Register s, Register b);
1896 inline void stdcx_(Register s, Register b);
1897 inline void lfs( FloatRegister d, int si16);
1898 inline void lfsx( FloatRegister d, Register b);
1899 inline void lfd( FloatRegister d, int si16);
1900 inline void lfdx( FloatRegister d, Register b);
1901 inline void stfs( FloatRegister s, int si16);
1902 inline void stfsx( FloatRegister s, Register b);
1903 inline void stfd( FloatRegister s, int si16);
1904 inline void stfdx( FloatRegister s, Register b);
1905 inline void lvebx( VectorRegister d, Register s2);
1906 inline void lvehx( VectorRegister d, Register s2);
1907 inline void lvewx( VectorRegister d, Register s2);
1908 inline void lvx( VectorRegister d, Register s2);
1909 inline void lvxl( VectorRegister d, Register s2);
1910 inline void stvebx(VectorRegister d, Register s2);
1911 inline void stvehx(VectorRegister d, Register s2);
1912 inline void stvewx(VectorRegister d, Register s2);
1913 inline void stvx( VectorRegister d, Register s2);
1914 inline void stvxl( VectorRegister d, Register s2);
1915 inline void lvsl( VectorRegister d, Register s2);
1916 inline void lvsr( VectorRegister d, Register s2);
1918 // RegisterOrConstant versions.
1919 // These emitters choose between the versions using two registers and
1920 // those with register and immediate, depending on the content of roc.
1921 // If the constant is not encodable as immediate, instructions to
1922 // load the constant are emitted beforehand. Store instructions need a
1923 // tmp reg if the constant is not encodable as immediate.
1924 // Size unpredictable.
1925 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg);
1926 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
1927 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1928 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
1929 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1930 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
1931 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1932 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1933 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1934 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
1935 void add( Register d, RegisterOrConstant roc, Register s1);
1936 void subf(Register d, RegisterOrConstant roc, Register s1);
1937 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
1940 // Emit several instructions to load a 64 bit constant. This issues a fixed
1941 // instruction pattern so that the constant can be patched later on.
1942 enum {
1943 load_const_size = 5 * BytesPerInstWord
1944 };
1945 void load_const(Register d, long a, Register tmp = noreg);
1946 inline void load_const(Register d, void* a, Register tmp = noreg);
1947 inline void load_const(Register d, Label& L, Register tmp = noreg);
1948 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
1950 // Load a 64 bit constant, optimized, not identifyable.
1951 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
1952 // 16 bit immediate offset. This is useful if the offset can be encoded in
1953 // a succeeding instruction.
1954 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false);
1955 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
1956 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
1957 }
1959 // Creation
1960 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1961 #ifdef CHECK_DELAY
1962 delay_state = no_delay;
1963 #endif
1964 }
1966 // Testing
1967 #ifndef PRODUCT
1968 void test_asm();
1969 #endif
1970 };
1973 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP
