Mon, 12 Mar 2012 15:28:07 -0700
7152957: VM crashes with assert(false) failed: bad AD file
Reviewed-by: kvn, never
Contributed-by: nils.eliasson@oracle.com
1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
247 #define __ _masm.
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
283 static int preserve_SP_size() {
284 return 2; // op, rm(reg/reg)
285 }
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
301 static int sizeof_FFree_Float_Stack_All = -1;
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
314 //
315 // Compute padding required for nodes which need alignment
316 //
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
344 // EMIT_RM()
345 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
346 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
347 cbuf.insts()->emit_int8(c);
348 }
350 // EMIT_CC()
351 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
352 unsigned char c = (unsigned char)( f1 | f2 );
353 cbuf.insts()->emit_int8(c);
354 }
356 // EMIT_OPCODE()
357 void emit_opcode(CodeBuffer &cbuf, int code) {
358 cbuf.insts()->emit_int8((unsigned char) code);
359 }
361 // EMIT_OPCODE() w/ relocation information
362 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
363 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
364 emit_opcode(cbuf, code);
365 }
367 // EMIT_D8()
368 void emit_d8(CodeBuffer &cbuf, int d8) {
369 cbuf.insts()->emit_int8((unsigned char) d8);
370 }
372 // EMIT_D16()
373 void emit_d16(CodeBuffer &cbuf, int d16) {
374 cbuf.insts()->emit_int16(d16);
375 }
377 // EMIT_D32()
378 void emit_d32(CodeBuffer &cbuf, int d32) {
379 cbuf.insts()->emit_int32(d32);
380 }
382 // emit 32 bit value and construct relocation entry from relocInfo::relocType
383 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
384 int format) {
385 cbuf.relocate(cbuf.insts_mark(), reloc, format);
386 cbuf.insts()->emit_int32(d32);
387 }
389 // emit 32 bit value and construct relocation entry from RelocationHolder
390 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
391 int format) {
392 #ifdef ASSERT
393 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
394 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
395 }
396 #endif
397 cbuf.relocate(cbuf.insts_mark(), rspec, format);
398 cbuf.insts()->emit_int32(d32);
399 }
401 // Access stack slot for load or store
402 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
403 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
404 if( -128 <= disp && disp <= 127 ) {
405 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
406 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
407 emit_d8 (cbuf, disp); // Displacement // R/M byte
408 } else {
409 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
410 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
411 emit_d32(cbuf, disp); // Displacement // R/M byte
412 }
413 }
415 // eRegI ereg, memory mem) %{ // emit_reg_mem
416 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
417 // There is no index & no scale, use form without SIB byte
418 if ((index == 0x4) &&
419 (scale == 0) && (base != ESP_enc)) {
420 // If no displacement, mode is 0x0; unless base is [EBP]
421 if ( (displace == 0) && (base != EBP_enc) ) {
422 emit_rm(cbuf, 0x0, reg_encoding, base);
423 }
424 else { // If 8-bit displacement, mode 0x1
425 if ((displace >= -128) && (displace <= 127)
426 && !(displace_is_oop) ) {
427 emit_rm(cbuf, 0x1, reg_encoding, base);
428 emit_d8(cbuf, displace);
429 }
430 else { // If 32-bit displacement
431 if (base == -1) { // Special flag for absolute address
432 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
433 // (manual lies; no SIB needed here)
434 if ( displace_is_oop ) {
435 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
436 } else {
437 emit_d32 (cbuf, displace);
438 }
439 }
440 else { // Normal base + offset
441 emit_rm(cbuf, 0x2, reg_encoding, base);
442 if ( displace_is_oop ) {
443 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
444 } else {
445 emit_d32 (cbuf, displace);
446 }
447 }
448 }
449 }
450 }
451 else { // Else, encode with the SIB byte
452 // If no displacement, mode is 0x0; unless base is [EBP]
453 if (displace == 0 && (base != EBP_enc)) { // If no displacement
454 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
455 emit_rm(cbuf, scale, index, base);
456 }
457 else { // If 8-bit displacement, mode 0x1
458 if ((displace >= -128) && (displace <= 127)
459 && !(displace_is_oop) ) {
460 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
461 emit_rm(cbuf, scale, index, base);
462 emit_d8(cbuf, displace);
463 }
464 else { // If 32-bit displacement
465 if (base == 0x04 ) {
466 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
467 emit_rm(cbuf, scale, index, 0x04);
468 } else {
469 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
470 emit_rm(cbuf, scale, index, base);
471 }
472 if ( displace_is_oop ) {
473 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
474 } else {
475 emit_d32 (cbuf, displace);
476 }
477 }
478 }
479 }
480 }
483 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
484 if( dst_encoding == src_encoding ) {
485 // reg-reg copy, use an empty encoding
486 } else {
487 emit_opcode( cbuf, 0x8B );
488 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
489 }
490 }
492 void emit_cmpfp_fixup(MacroAssembler& _masm) {
493 Label exit;
494 __ jccb(Assembler::noParity, exit);
495 __ pushf();
496 //
497 // comiss/ucomiss instructions set ZF,PF,CF flags and
498 // zero OF,AF,SF for NaN values.
499 // Fixup flags by zeroing ZF,PF so that compare of NaN
500 // values returns 'less than' result (CF is set).
501 // Leave the rest of flags unchanged.
502 //
503 // 7 6 5 4 3 2 1 0
504 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
505 // 0 0 1 0 1 0 1 1 (0x2B)
506 //
507 __ andl(Address(rsp, 0), 0xffffff2b);
508 __ popf();
509 __ bind(exit);
510 }
512 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
513 Label done;
514 __ movl(dst, -1);
515 __ jcc(Assembler::parity, done);
516 __ jcc(Assembler::below, done);
517 __ setb(Assembler::notEqual, dst);
518 __ movzbl(dst, dst);
519 __ bind(done);
520 }
523 //=============================================================================
524 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
526 int Compile::ConstantTable::calculate_table_base_offset() const {
527 return 0; // absolute addressing, no offset
528 }
530 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
531 // Empty encoding
532 }
534 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
535 return 0;
536 }
538 #ifndef PRODUCT
539 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
540 st->print("# MachConstantBaseNode (empty encoding)");
541 }
542 #endif
545 //=============================================================================
546 #ifndef PRODUCT
547 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
548 Compile* C = ra_->C;
550 int framesize = C->frame_slots() << LogBytesPerInt;
551 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
552 // Remove wordSize for return addr which is already pushed.
553 framesize -= wordSize;
555 if (C->need_stack_bang(framesize)) {
556 framesize -= wordSize;
557 st->print("# stack bang");
558 st->print("\n\t");
559 st->print("PUSH EBP\t# Save EBP");
560 if (framesize) {
561 st->print("\n\t");
562 st->print("SUB ESP, #%d\t# Create frame",framesize);
563 }
564 } else {
565 st->print("SUB ESP, #%d\t# Create frame",framesize);
566 st->print("\n\t");
567 framesize -= wordSize;
568 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
569 }
571 if (VerifyStackAtCalls) {
572 st->print("\n\t");
573 framesize -= wordSize;
574 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
575 }
577 if( C->in_24_bit_fp_mode() ) {
578 st->print("\n\t");
579 st->print("FLDCW \t# load 24 bit fpu control word");
580 }
581 if (UseSSE >= 2 && VerifyFPU) {
582 st->print("\n\t");
583 st->print("# verify FPU stack (must be clean on entry)");
584 }
586 #ifdef ASSERT
587 if (VerifyStackAtCalls) {
588 st->print("\n\t");
589 st->print("# stack alignment check");
590 }
591 #endif
592 st->cr();
593 }
594 #endif
597 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
598 Compile* C = ra_->C;
599 MacroAssembler _masm(&cbuf);
601 int framesize = C->frame_slots() << LogBytesPerInt;
603 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
605 C->set_frame_complete(cbuf.insts_size());
607 if (C->has_mach_constant_base_node()) {
608 // NOTE: We set the table base offset here because users might be
609 // emitted before MachConstantBaseNode.
610 Compile::ConstantTable& constant_table = C->constant_table();
611 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
612 }
613 }
615 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_); // too many variables; just compute it the hard way
617 }
619 int MachPrologNode::reloc() const {
620 return 0; // a large enough number
621 }
623 //=============================================================================
624 #ifndef PRODUCT
625 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
626 Compile *C = ra_->C;
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
632 if( C->in_24_bit_fp_mode() ) {
633 st->print("FLDCW standard control word");
634 st->cr(); st->print("\t");
635 }
636 if( framesize ) {
637 st->print("ADD ESP,%d\t# Destroy frame",framesize);
638 st->cr(); st->print("\t");
639 }
640 st->print_cr("POPL EBP"); st->print("\t");
641 if( do_polling() && C->is_method_compilation() ) {
642 st->print("TEST PollPage,EAX\t! Poll Safepoint");
643 st->cr(); st->print("\t");
644 }
645 }
646 #endif
648 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
649 Compile *C = ra_->C;
651 // If method set FPU control word, restore to standard control word
652 if( C->in_24_bit_fp_mode() ) {
653 MacroAssembler masm(&cbuf);
654 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
655 }
657 int framesize = C->frame_slots() << LogBytesPerInt;
658 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
659 // Remove two words for return addr and rbp,
660 framesize -= 2*wordSize;
662 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
664 if( framesize >= 128 ) {
665 emit_opcode(cbuf, 0x81); // add SP, #framesize
666 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
667 emit_d32(cbuf, framesize);
668 }
669 else if( framesize ) {
670 emit_opcode(cbuf, 0x83); // add SP, #framesize
671 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
672 emit_d8(cbuf, framesize);
673 }
675 emit_opcode(cbuf, 0x58 | EBP_enc);
677 if( do_polling() && C->is_method_compilation() ) {
678 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
679 emit_opcode(cbuf,0x85);
680 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
681 emit_d32(cbuf, (intptr_t)os::get_polling_page());
682 }
683 }
685 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
686 Compile *C = ra_->C;
687 // If method set FPU control word, restore to standard control word
688 int size = C->in_24_bit_fp_mode() ? 6 : 0;
689 if( do_polling() && C->is_method_compilation() ) size += 6;
691 int framesize = C->frame_slots() << LogBytesPerInt;
692 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
693 // Remove two words for return addr and rbp,
694 framesize -= 2*wordSize;
696 size++; // popl rbp,
698 if( framesize >= 128 ) {
699 size += 6;
700 } else {
701 size += framesize ? 3 : 0;
702 }
703 return size;
704 }
706 int MachEpilogNode::reloc() const {
707 return 0; // a large enough number
708 }
710 const Pipeline * MachEpilogNode::pipeline() const {
711 return MachNode::pipeline_class();
712 }
714 int MachEpilogNode::safepoint_offset() const { return 0; }
716 //=============================================================================
718 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
719 static enum RC rc_class( OptoReg::Name reg ) {
721 if( !OptoReg::is_valid(reg) ) return rc_bad;
722 if (OptoReg::is_stack(reg)) return rc_stack;
724 VMReg r = OptoReg::as_VMReg(reg);
725 if (r->is_Register()) return rc_int;
726 if (r->is_FloatRegister()) {
727 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
728 return rc_float;
729 }
730 assert(r->is_XMMRegister(), "must be");
731 return rc_xmm;
732 }
734 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
735 int opcode, const char *op_str, int size, outputStream* st ) {
736 if( cbuf ) {
737 emit_opcode (*cbuf, opcode );
738 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
739 #ifndef PRODUCT
740 } else if( !do_size ) {
741 if( size != 0 ) st->print("\n\t");
742 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
743 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
744 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
745 } else { // FLD, FST, PUSH, POP
746 st->print("%s [ESP + #%d]",op_str,offset);
747 }
748 #endif
749 }
750 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
751 return size+3+offset_size;
752 }
754 // Helper for XMM registers. Extra opcode bits, limited syntax.
755 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
756 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
757 if (cbuf) {
758 MacroAssembler _masm(cbuf);
759 if (reg_lo+1 == reg_hi) { // double move?
760 if (is_load) {
761 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
762 } else {
763 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
764 }
765 } else {
766 if (is_load) {
767 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
768 } else {
769 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
770 }
771 }
772 #ifndef PRODUCT
773 } else if (!do_size) {
774 if (size != 0) st->print("\n\t");
775 if (reg_lo+1 == reg_hi) { // double move?
776 if (is_load) st->print("%s %s,[ESP + #%d]",
777 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
778 Matcher::regName[reg_lo], offset);
779 else st->print("MOVSD [ESP + #%d],%s",
780 offset, Matcher::regName[reg_lo]);
781 } else {
782 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
783 Matcher::regName[reg_lo], offset);
784 else st->print("MOVSS [ESP + #%d],%s",
785 offset, Matcher::regName[reg_lo]);
786 }
787 #endif
788 }
789 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
790 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes.
791 return size+5+offset_size;
792 }
795 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
796 int src_hi, int dst_hi, int size, outputStream* st ) {
797 if (cbuf) {
798 MacroAssembler _masm(cbuf);
799 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
800 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
801 as_XMMRegister(Matcher::_regEncode[src_lo]));
802 } else {
803 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
804 as_XMMRegister(Matcher::_regEncode[src_lo]));
805 }
806 #ifndef PRODUCT
807 } else if (!do_size) {
808 if (size != 0) st->print("\n\t");
809 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
810 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
811 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
812 } else {
813 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
814 }
815 } else {
816 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
817 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
818 } else {
819 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 }
821 }
822 #endif
823 }
824 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes.
825 // Only MOVAPS SSE prefix uses 1 byte.
826 int sz = 4;
827 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
828 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
829 return size + sz;
830 }
832 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
833 int src_hi, int dst_hi, int size, outputStream* st ) {
834 // 32-bit
835 if (cbuf) {
836 MacroAssembler _masm(cbuf);
837 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
838 as_Register(Matcher::_regEncode[src_lo]));
839 #ifndef PRODUCT
840 } else if (!do_size) {
841 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
842 #endif
843 }
844 return 4;
845 }
848 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
849 int src_hi, int dst_hi, int size, outputStream* st ) {
850 // 32-bit
851 if (cbuf) {
852 MacroAssembler _masm(cbuf);
853 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
854 as_XMMRegister(Matcher::_regEncode[src_lo]));
855 #ifndef PRODUCT
856 } else if (!do_size) {
857 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
858 #endif
859 }
860 return 4;
861 }
863 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
864 if( cbuf ) {
865 emit_opcode(*cbuf, 0x8B );
866 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
867 #ifndef PRODUCT
868 } else if( !do_size ) {
869 if( size != 0 ) st->print("\n\t");
870 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
871 #endif
872 }
873 return size+2;
874 }
876 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
877 int offset, int size, outputStream* st ) {
878 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
879 if( cbuf ) {
880 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
881 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
882 #ifndef PRODUCT
883 } else if( !do_size ) {
884 if( size != 0 ) st->print("\n\t");
885 st->print("FLD %s",Matcher::regName[src_lo]);
886 #endif
887 }
888 size += 2;
889 }
891 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
892 const char *op_str;
893 int op;
894 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
895 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
896 op = 0xDD;
897 } else { // 32-bit store
898 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
899 op = 0xD9;
900 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
901 }
903 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
904 }
906 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
907 // Get registers to move
908 OptoReg::Name src_second = ra_->get_reg_second(in(1));
909 OptoReg::Name src_first = ra_->get_reg_first(in(1));
910 OptoReg::Name dst_second = ra_->get_reg_second(this );
911 OptoReg::Name dst_first = ra_->get_reg_first(this );
913 enum RC src_second_rc = rc_class(src_second);
914 enum RC src_first_rc = rc_class(src_first);
915 enum RC dst_second_rc = rc_class(dst_second);
916 enum RC dst_first_rc = rc_class(dst_first);
918 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
920 // Generate spill code!
921 int size = 0;
923 if( src_first == dst_first && src_second == dst_second )
924 return size; // Self copy, no move
926 // --------------------------------------
927 // Check for mem-mem move. push/pop to move.
928 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
929 if( src_second == dst_first ) { // overlapping stack copy ranges
930 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
931 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
932 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
933 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
934 }
935 // move low bits
936 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
937 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
938 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
939 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
940 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
941 }
942 return size;
943 }
945 // --------------------------------------
946 // Check for integer reg-reg copy
947 if( src_first_rc == rc_int && dst_first_rc == rc_int )
948 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
950 // Check for integer store
951 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
952 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
954 // Check for integer load
955 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
956 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
958 // Check for integer reg-xmm reg copy
959 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
960 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
961 "no 64 bit integer-float reg moves" );
962 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
963 }
964 // --------------------------------------
965 // Check for float reg-reg copy
966 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
967 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
968 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
969 if( cbuf ) {
971 // Note the mucking with the register encode to compensate for the 0/1
972 // indexing issue mentioned in a comment in the reg_def sections
973 // for FPR registers many lines above here.
975 if( src_first != FPR1L_num ) {
976 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
977 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
978 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
979 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
980 } else {
981 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
982 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
983 }
984 #ifndef PRODUCT
985 } else if( !do_size ) {
986 if( size != 0 ) st->print("\n\t");
987 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
988 else st->print( "FST %s", Matcher::regName[dst_first]);
989 #endif
990 }
991 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
992 }
994 // Check for float store
995 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
996 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
997 }
999 // Check for float load
1000 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1001 int offset = ra_->reg2offset(src_first);
1002 const char *op_str;
1003 int op;
1004 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1005 op_str = "FLD_D";
1006 op = 0xDD;
1007 } else { // 32-bit load
1008 op_str = "FLD_S";
1009 op = 0xD9;
1010 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1011 }
1012 if( cbuf ) {
1013 emit_opcode (*cbuf, op );
1014 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1015 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1016 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1017 #ifndef PRODUCT
1018 } else if( !do_size ) {
1019 if( size != 0 ) st->print("\n\t");
1020 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1021 #endif
1022 }
1023 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1024 return size + 3+offset_size+2;
1025 }
1027 // Check for xmm reg-reg copy
1028 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1029 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1030 (src_first+1 == src_second && dst_first+1 == dst_second),
1031 "no non-adjacent float-moves" );
1032 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1033 }
1035 // Check for xmm reg-integer reg copy
1036 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1037 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1038 "no 64 bit float-integer reg moves" );
1039 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1040 }
1042 // Check for xmm store
1043 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1044 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1045 }
1047 // Check for float xmm load
1048 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1049 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1050 }
1052 // Copy from float reg to xmm reg
1053 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1054 // copy to the top of stack from floating point reg
1055 // and use LEA to preserve flags
1056 if( cbuf ) {
1057 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1058 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1059 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1060 emit_d8(*cbuf,0xF8);
1061 #ifndef PRODUCT
1062 } else if( !do_size ) {
1063 if( size != 0 ) st->print("\n\t");
1064 st->print("LEA ESP,[ESP-8]");
1065 #endif
1066 }
1067 size += 4;
1069 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1071 // Copy from the temp memory to the xmm reg.
1072 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1074 if( cbuf ) {
1075 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1076 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1077 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1078 emit_d8(*cbuf,0x08);
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 st->print("LEA ESP,[ESP+8]");
1083 #endif
1084 }
1085 size += 4;
1086 return size;
1087 }
1089 assert( size > 0, "missed a case" );
1091 // --------------------------------------------------------------------
1092 // Check for second bits still needing moving.
1093 if( src_second == dst_second )
1094 return size; // Self copy; no move
1095 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1097 // Check for second word int-int move
1098 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1099 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1101 // Check for second word integer store
1102 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1103 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1105 // Check for second word integer load
1106 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1107 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1110 Unimplemented();
1111 }
1113 #ifndef PRODUCT
1114 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1115 implementation( NULL, ra_, false, st );
1116 }
1117 #endif
1119 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1120 implementation( &cbuf, ra_, false, NULL );
1121 }
1123 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1124 return implementation( NULL, ra_, true, NULL );
1125 }
1128 //=============================================================================
1129 #ifndef PRODUCT
1130 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1131 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1132 int reg = ra_->get_reg_first(this);
1133 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1134 }
1135 #endif
1137 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1138 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1139 int reg = ra_->get_encode(this);
1140 if( offset >= 128 ) {
1141 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1142 emit_rm(cbuf, 0x2, reg, 0x04);
1143 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1144 emit_d32(cbuf, offset);
1145 }
1146 else {
1147 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1148 emit_rm(cbuf, 0x1, reg, 0x04);
1149 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1150 emit_d8(cbuf, offset);
1151 }
1152 }
1154 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1155 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1156 if( offset >= 128 ) {
1157 return 7;
1158 }
1159 else {
1160 return 4;
1161 }
1162 }
1164 //=============================================================================
1166 // emit call stub, compiled java to interpreter
1167 void emit_java_to_interp(CodeBuffer &cbuf ) {
1168 // Stub is fixed up when the corresponding call is converted from calling
1169 // compiled code to calling interpreted code.
1170 // mov rbx,0
1171 // jmp -1
1173 address mark = cbuf.insts_mark(); // get mark within main instrs section
1175 // Note that the code buffer's insts_mark is always relative to insts.
1176 // That's why we must use the macroassembler to generate a stub.
1177 MacroAssembler _masm(&cbuf);
1179 address base =
1180 __ start_a_stub(Compile::MAX_stubs_size);
1181 if (base == NULL) return; // CodeBuffer::expand failed
1182 // static stub relocation stores the instruction address of the call
1183 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1184 // static stub relocation also tags the methodOop in the code-stream.
1185 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1186 // This is recognized as unresolved by relocs/nativeInst/ic code
1187 __ jump(RuntimeAddress(__ pc()));
1189 __ end_a_stub();
1190 // Update current stubs pointer and restore insts_end.
1191 }
1192 // size of call stub, compiled java to interpretor
1193 uint size_java_to_interp() {
1194 return 10; // movl; jmp
1195 }
1196 // relocation entries for call stub, compiled java to interpretor
1197 uint reloc_java_to_interp() {
1198 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1199 }
1201 //=============================================================================
1202 #ifndef PRODUCT
1203 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1204 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1205 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1206 st->print_cr("\tNOP");
1207 st->print_cr("\tNOP");
1208 if( !OptoBreakpoint )
1209 st->print_cr("\tNOP");
1210 }
1211 #endif
1213 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1214 MacroAssembler masm(&cbuf);
1215 #ifdef ASSERT
1216 uint insts_size = cbuf.insts_size();
1217 #endif
1218 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1219 masm.jump_cc(Assembler::notEqual,
1220 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1221 /* WARNING these NOPs are critical so that verified entry point is properly
1222 aligned for patching by NativeJump::patch_verified_entry() */
1223 int nops_cnt = 2;
1224 if( !OptoBreakpoint ) // Leave space for int3
1225 nops_cnt += 1;
1226 masm.nop(nops_cnt);
1228 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1229 }
1231 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1232 return OptoBreakpoint ? 11 : 12;
1233 }
1236 //=============================================================================
1237 uint size_exception_handler() {
1238 // NativeCall instruction size is the same as NativeJump.
1239 // exception handler starts out as jump and can be patched to
1240 // a call be deoptimization. (4932387)
1241 // Note that this value is also credited (in output.cpp) to
1242 // the size of the code section.
1243 return NativeJump::instruction_size;
1244 }
1246 // Emit exception handler code. Stuff framesize into a register
1247 // and call a VM stub routine.
1248 int emit_exception_handler(CodeBuffer& cbuf) {
1250 // Note that the code buffer's insts_mark is always relative to insts.
1251 // That's why we must use the macroassembler to generate a handler.
1252 MacroAssembler _masm(&cbuf);
1253 address base =
1254 __ start_a_stub(size_exception_handler());
1255 if (base == NULL) return 0; // CodeBuffer::expand failed
1256 int offset = __ offset();
1257 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1258 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1259 __ end_a_stub();
1260 return offset;
1261 }
1263 uint size_deopt_handler() {
1264 // NativeCall instruction size is the same as NativeJump.
1265 // exception handler starts out as jump and can be patched to
1266 // a call be deoptimization. (4932387)
1267 // Note that this value is also credited (in output.cpp) to
1268 // the size of the code section.
1269 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1270 }
1272 // Emit deopt handler code.
1273 int emit_deopt_handler(CodeBuffer& cbuf) {
1275 // Note that the code buffer's insts_mark is always relative to insts.
1276 // That's why we must use the macroassembler to generate a handler.
1277 MacroAssembler _masm(&cbuf);
1278 address base =
1279 __ start_a_stub(size_exception_handler());
1280 if (base == NULL) return 0; // CodeBuffer::expand failed
1281 int offset = __ offset();
1282 InternalAddress here(__ pc());
1283 __ pushptr(here.addr());
1285 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1286 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1287 __ end_a_stub();
1288 return offset;
1289 }
1292 const bool Matcher::match_rule_supported(int opcode) {
1293 if (!has_match_rule(opcode))
1294 return false;
1296 switch (opcode) {
1297 case Op_PopCountI:
1298 case Op_PopCountL:
1299 if (!UsePopCountInstruction)
1300 return false;
1301 break;
1302 }
1304 return true; // Per default match rules are supported.
1305 }
1307 int Matcher::regnum_to_fpu_offset(int regnum) {
1308 return regnum - 32; // The FP registers are in the second chunk
1309 }
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313 return true;
1314 }
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318 return UseSSE >= 2 ? 8 : 0;
1319 }
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323 return Op_RegD;
1324 }
1326 // Is this branch offset short enough that a short branch can be used?
1327 //
1328 // NOTE: If the platform does not provide any short branch variants, then
1329 // this method should return false for offset 0.
1330 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1331 // The passed offset is relative to address of the branch.
1332 // On 86 a branch displacement is calculated relative to address
1333 // of a next instruction.
1334 offset -= br_size;
1336 // the short version of jmpConUCF2 contains multiple branches,
1337 // making the reach slightly less
1338 if (rule == jmpConUCF2_rule)
1339 return (-126 <= offset && offset <= 125);
1340 return (-128 <= offset && offset <= 127);
1341 }
1343 const bool Matcher::isSimpleConstant64(jlong value) {
1344 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1345 return false;
1346 }
1348 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1349 const bool Matcher::init_array_count_is_in_bytes = false;
1351 // Threshold size for cleararray.
1352 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1354 // Needs 2 CMOV's for longs.
1355 const int Matcher::long_cmove_cost() { return 1; }
1357 // No CMOVF/CMOVD with SSE/SSE2
1358 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1360 // Should the Matcher clone shifts on addressing modes, expecting them to
1361 // be subsumed into complex addressing expressions or compute them into
1362 // registers? True for Intel but false for most RISCs
1363 const bool Matcher::clone_shift_expressions = true;
1365 // Do we need to mask the count passed to shift instructions or does
1366 // the cpu only look at the lower 5/6 bits anyway?
1367 const bool Matcher::need_masked_shift_count = false;
1369 bool Matcher::narrow_oop_use_complex_address() {
1370 ShouldNotCallThis();
1371 return true;
1372 }
1375 // Is it better to copy float constants, or load them directly from memory?
1376 // Intel can load a float constant from a direct address, requiring no
1377 // extra registers. Most RISCs will have to materialize an address into a
1378 // register first, so they would do better to copy the constant from stack.
1379 const bool Matcher::rematerialize_float_constants = true;
1381 // If CPU can load and store mis-aligned doubles directly then no fixup is
1382 // needed. Else we split the double into 2 integer pieces and move it
1383 // piece-by-piece. Only happens when passing doubles into C code as the
1384 // Java calling convention forces doubles to be aligned.
1385 const bool Matcher::misaligned_doubles_ok = true;
1388 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1389 // Get the memory operand from the node
1390 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1391 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1392 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1393 uint opcnt = 1; // First operand
1394 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1395 while( idx >= skipped+num_edges ) {
1396 skipped += num_edges;
1397 opcnt++; // Bump operand count
1398 assert( opcnt < numopnds, "Accessing non-existent operand" );
1399 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1400 }
1402 MachOper *memory = node->_opnds[opcnt];
1403 MachOper *new_memory = NULL;
1404 switch (memory->opcode()) {
1405 case DIRECT:
1406 case INDOFFSET32X:
1407 // No transformation necessary.
1408 return;
1409 case INDIRECT:
1410 new_memory = new (C) indirect_win95_safeOper( );
1411 break;
1412 case INDOFFSET8:
1413 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1414 break;
1415 case INDOFFSET32:
1416 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1417 break;
1418 case INDINDEXOFFSET:
1419 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1420 break;
1421 case INDINDEXSCALE:
1422 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1423 break;
1424 case INDINDEXSCALEOFFSET:
1425 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1426 break;
1427 case LOAD_LONG_INDIRECT:
1428 case LOAD_LONG_INDOFFSET32:
1429 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1430 return;
1431 default:
1432 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1433 return;
1434 }
1435 node->_opnds[opcnt] = new_memory;
1436 }
1438 // Advertise here if the CPU requires explicit rounding operations
1439 // to implement the UseStrictFP mode.
1440 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1442 // Are floats conerted to double when stored to stack during deoptimization?
1443 // On x32 it is stored with convertion only when FPU is used for floats.
1444 bool Matcher::float_in_double() { return (UseSSE == 0); }
1446 // Do ints take an entire long register or just half?
1447 const bool Matcher::int_in_long = false;
1449 // Return whether or not this register is ever used as an argument. This
1450 // function is used on startup to build the trampoline stubs in generateOptoStub.
1451 // Registers not mentioned will be killed by the VM call in the trampoline, and
1452 // arguments in those registers not be available to the callee.
1453 bool Matcher::can_be_java_arg( int reg ) {
1454 if( reg == ECX_num || reg == EDX_num ) return true;
1455 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1456 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1457 return false;
1458 }
1460 bool Matcher::is_spillable_arg( int reg ) {
1461 return can_be_java_arg(reg);
1462 }
1464 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1465 // Use hardware integer DIV instruction when
1466 // it is faster than a code which use multiply.
1467 // Only when constant divisor fits into 32 bit
1468 // (min_jint is excluded to get only correct
1469 // positive 32 bit values from negative).
1470 return VM_Version::has_fast_idiv() &&
1471 (divisor == (int)divisor && divisor != min_jint);
1472 }
1474 // Register for DIVI projection of divmodI
1475 RegMask Matcher::divI_proj_mask() {
1476 return EAX_REG_mask();
1477 }
1479 // Register for MODI projection of divmodI
1480 RegMask Matcher::modI_proj_mask() {
1481 return EDX_REG_mask();
1482 }
1484 // Register for DIVL projection of divmodL
1485 RegMask Matcher::divL_proj_mask() {
1486 ShouldNotReachHere();
1487 return RegMask();
1488 }
1490 // Register for MODL projection of divmodL
1491 RegMask Matcher::modL_proj_mask() {
1492 ShouldNotReachHere();
1493 return RegMask();
1494 }
1496 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1497 return EBP_REG_mask();
1498 }
1500 // Returns true if the high 32 bits of the value is known to be zero.
1501 bool is_operand_hi32_zero(Node* n) {
1502 int opc = n->Opcode();
1503 if (opc == Op_LoadUI2L) {
1504 return true;
1505 }
1506 if (opc == Op_AndL) {
1507 Node* o2 = n->in(2);
1508 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1509 return true;
1510 }
1511 }
1512 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1513 return true;
1514 }
1515 return false;
1516 }
1518 %}
1520 //----------ENCODING BLOCK-----------------------------------------------------
1521 // This block specifies the encoding classes used by the compiler to output
1522 // byte streams. Encoding classes generate functions which are called by
1523 // Machine Instruction Nodes in order to generate the bit encoding of the
1524 // instruction. Operands specify their base encoding interface with the
1525 // interface keyword. There are currently supported four interfaces,
1526 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1527 // operand to generate a function which returns its register number when
1528 // queried. CONST_INTER causes an operand to generate a function which
1529 // returns the value of the constant when queried. MEMORY_INTER causes an
1530 // operand to generate four functions which return the Base Register, the
1531 // Index Register, the Scale Value, and the Offset Value of the operand when
1532 // queried. COND_INTER causes an operand to generate six functions which
1533 // return the encoding code (ie - encoding bits for the instruction)
1534 // associated with each basic boolean condition for a conditional instruction.
1535 // Instructions specify two basic values for encoding. They use the
1536 // ins_encode keyword to specify their encoding class (which must be one of
1537 // the class names specified in the encoding block), and they use the
1538 // opcode keyword to specify, in order, their primary, secondary, and
1539 // tertiary opcode. Only the opcode sections which a particular instruction
1540 // needs for encoding need to be specified.
1541 encode %{
1542 // Build emit functions for each basic byte or larger field in the intel
1543 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1544 // code in the enc_class source block. Emit functions will live in the
1545 // main source block for now. In future, we can generalize this by
1546 // adding a syntax that specifies the sizes of fields in an order,
1547 // so that the adlc can build the emit functions automagically
1549 // Emit primary opcode
1550 enc_class OpcP %{
1551 emit_opcode(cbuf, $primary);
1552 %}
1554 // Emit secondary opcode
1555 enc_class OpcS %{
1556 emit_opcode(cbuf, $secondary);
1557 %}
1559 // Emit opcode directly
1560 enc_class Opcode(immI d8) %{
1561 emit_opcode(cbuf, $d8$$constant);
1562 %}
1564 enc_class SizePrefix %{
1565 emit_opcode(cbuf,0x66);
1566 %}
1568 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1569 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1570 %}
1572 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1573 emit_opcode(cbuf,$opcode$$constant);
1574 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1575 %}
1577 enc_class mov_r32_imm0( eRegI dst ) %{
1578 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1579 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1580 %}
1582 enc_class cdq_enc %{
1583 // Full implementation of Java idiv and irem; checks for
1584 // special case as described in JVM spec., p.243 & p.271.
1585 //
1586 // normal case special case
1587 //
1588 // input : rax,: dividend min_int
1589 // reg: divisor -1
1590 //
1591 // output: rax,: quotient (= rax, idiv reg) min_int
1592 // rdx: remainder (= rax, irem reg) 0
1593 //
1594 // Code sequnce:
1595 //
1596 // 81 F8 00 00 00 80 cmp rax,80000000h
1597 // 0F 85 0B 00 00 00 jne normal_case
1598 // 33 D2 xor rdx,edx
1599 // 83 F9 FF cmp rcx,0FFh
1600 // 0F 84 03 00 00 00 je done
1601 // normal_case:
1602 // 99 cdq
1603 // F7 F9 idiv rax,ecx
1604 // done:
1605 //
1606 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1607 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1608 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1609 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1610 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1611 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1612 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1613 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1614 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1615 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1616 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1617 // normal_case:
1618 emit_opcode(cbuf,0x99); // cdq
1619 // idiv (note: must be emitted by the user of this rule)
1620 // normal:
1621 %}
1623 // Dense encoding for older common ops
1624 enc_class Opc_plus(immI opcode, eRegI reg) %{
1625 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1626 %}
1629 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1630 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1631 // Check for 8-bit immediate, and set sign extend bit in opcode
1632 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1633 emit_opcode(cbuf, $primary | 0x02);
1634 }
1635 else { // If 32-bit immediate
1636 emit_opcode(cbuf, $primary);
1637 }
1638 %}
1640 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1641 // Emit primary opcode and set sign-extend bit
1642 // Check for 8-bit immediate, and set sign extend bit in opcode
1643 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1644 emit_opcode(cbuf, $primary | 0x02); }
1645 else { // If 32-bit immediate
1646 emit_opcode(cbuf, $primary);
1647 }
1648 // Emit r/m byte with secondary opcode, after primary opcode.
1649 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1650 %}
1652 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1653 // Check for 8-bit immediate, and set sign extend bit in opcode
1654 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1655 $$$emit8$imm$$constant;
1656 }
1657 else { // If 32-bit immediate
1658 // Output immediate
1659 $$$emit32$imm$$constant;
1660 }
1661 %}
1663 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1664 // Emit primary opcode and set sign-extend bit
1665 // Check for 8-bit immediate, and set sign extend bit in opcode
1666 int con = (int)$imm$$constant; // Throw away top bits
1667 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1668 // Emit r/m byte with secondary opcode, after primary opcode.
1669 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1670 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1671 else emit_d32(cbuf,con);
1672 %}
1674 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1675 // Emit primary opcode and set sign-extend bit
1676 // Check for 8-bit immediate, and set sign extend bit in opcode
1677 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1678 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1679 // Emit r/m byte with tertiary opcode, after primary opcode.
1680 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1681 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1682 else emit_d32(cbuf,con);
1683 %}
1685 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1686 emit_cc(cbuf, $secondary, $dst$$reg );
1687 %}
1689 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1690 int destlo = $dst$$reg;
1691 int desthi = HIGH_FROM_LOW(destlo);
1692 // bswap lo
1693 emit_opcode(cbuf, 0x0F);
1694 emit_cc(cbuf, 0xC8, destlo);
1695 // bswap hi
1696 emit_opcode(cbuf, 0x0F);
1697 emit_cc(cbuf, 0xC8, desthi);
1698 // xchg lo and hi
1699 emit_opcode(cbuf, 0x87);
1700 emit_rm(cbuf, 0x3, destlo, desthi);
1701 %}
1703 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1704 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1705 %}
1707 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1708 $$$emit8$primary;
1709 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1710 %}
1712 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1713 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1714 emit_d8(cbuf, op >> 8 );
1715 emit_d8(cbuf, op & 255);
1716 %}
1718 // emulate a CMOV with a conditional branch around a MOV
1719 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1720 // Invert sense of branch from sense of CMOV
1721 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1722 emit_d8( cbuf, $brOffs$$constant );
1723 %}
1725 enc_class enc_PartialSubtypeCheck( ) %{
1726 Register Redi = as_Register(EDI_enc); // result register
1727 Register Reax = as_Register(EAX_enc); // super class
1728 Register Recx = as_Register(ECX_enc); // killed
1729 Register Resi = as_Register(ESI_enc); // sub class
1730 Label miss;
1732 MacroAssembler _masm(&cbuf);
1733 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1734 NULL, &miss,
1735 /*set_cond_codes:*/ true);
1736 if ($primary) {
1737 __ xorptr(Redi, Redi);
1738 }
1739 __ bind(miss);
1740 %}
1742 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1743 MacroAssembler masm(&cbuf);
1744 int start = masm.offset();
1745 if (UseSSE >= 2) {
1746 if (VerifyFPU) {
1747 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1748 }
1749 } else {
1750 // External c_calling_convention expects the FPU stack to be 'clean'.
1751 // Compiled code leaves it dirty. Do cleanup now.
1752 masm.empty_FPU_stack();
1753 }
1754 if (sizeof_FFree_Float_Stack_All == -1) {
1755 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1756 } else {
1757 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1758 }
1759 %}
1761 enc_class Verify_FPU_For_Leaf %{
1762 if( VerifyFPU ) {
1763 MacroAssembler masm(&cbuf);
1764 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1765 }
1766 %}
1768 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1769 // This is the instruction starting address for relocation info.
1770 cbuf.set_insts_mark();
1771 $$$emit8$primary;
1772 // CALL directly to the runtime
1773 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1774 runtime_call_Relocation::spec(), RELOC_IMM32 );
1776 if (UseSSE >= 2) {
1777 MacroAssembler _masm(&cbuf);
1778 BasicType rt = tf()->return_type();
1780 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1781 // A C runtime call where the return value is unused. In SSE2+
1782 // mode the result needs to be removed from the FPU stack. It's
1783 // likely that this function call could be removed by the
1784 // optimizer if the C function is a pure function.
1785 __ ffree(0);
1786 } else if (rt == T_FLOAT) {
1787 __ lea(rsp, Address(rsp, -4));
1788 __ fstp_s(Address(rsp, 0));
1789 __ movflt(xmm0, Address(rsp, 0));
1790 __ lea(rsp, Address(rsp, 4));
1791 } else if (rt == T_DOUBLE) {
1792 __ lea(rsp, Address(rsp, -8));
1793 __ fstp_d(Address(rsp, 0));
1794 __ movdbl(xmm0, Address(rsp, 0));
1795 __ lea(rsp, Address(rsp, 8));
1796 }
1797 }
1798 %}
1801 enc_class pre_call_FPU %{
1802 // If method sets FPU control word restore it here
1803 debug_only(int off0 = cbuf.insts_size());
1804 if( Compile::current()->in_24_bit_fp_mode() ) {
1805 MacroAssembler masm(&cbuf);
1806 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1807 }
1808 debug_only(int off1 = cbuf.insts_size());
1809 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1810 %}
1812 enc_class post_call_FPU %{
1813 // If method sets FPU control word do it here also
1814 if( Compile::current()->in_24_bit_fp_mode() ) {
1815 MacroAssembler masm(&cbuf);
1816 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1817 }
1818 %}
1820 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1821 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1822 // who we intended to call.
1823 cbuf.set_insts_mark();
1824 $$$emit8$primary;
1825 if ( !_method ) {
1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1827 runtime_call_Relocation::spec(), RELOC_IMM32 );
1828 } else if(_optimized_virtual) {
1829 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1830 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1831 } else {
1832 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1833 static_call_Relocation::spec(), RELOC_IMM32 );
1834 }
1835 if( _method ) { // Emit stub for static call
1836 emit_java_to_interp(cbuf);
1837 }
1838 %}
1840 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1841 // !!!!!
1842 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1843 // emit_call_dynamic_prologue( cbuf );
1844 cbuf.set_insts_mark();
1845 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1846 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1847 address virtual_call_oop_addr = cbuf.insts_mark();
1848 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1849 // who we intended to call.
1850 cbuf.set_insts_mark();
1851 $$$emit8$primary;
1852 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1853 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1854 %}
1856 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1857 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1858 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1860 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1861 cbuf.set_insts_mark();
1862 $$$emit8$primary;
1863 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1864 emit_d8(cbuf, disp); // Displacement
1866 %}
1868 // Following encoding is no longer used, but may be restored if calling
1869 // convention changes significantly.
1870 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1871 //
1872 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1873 // // int ic_reg = Matcher::inline_cache_reg();
1874 // // int ic_encode = Matcher::_regEncode[ic_reg];
1875 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1876 // // int imo_encode = Matcher::_regEncode[imo_reg];
1877 //
1878 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1879 // // // so we load it immediately before the call
1880 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1881 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1882 //
1883 // // xor rbp,ebp
1884 // emit_opcode(cbuf, 0x33);
1885 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1886 //
1887 // // CALL to interpreter.
1888 // cbuf.set_insts_mark();
1889 // $$$emit8$primary;
1890 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1891 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1892 // %}
1894 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1895 $$$emit8$primary;
1896 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1897 $$$emit8$shift$$constant;
1898 %}
1900 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1901 // Load immediate does not have a zero or sign extended version
1902 // for 8-bit immediates
1903 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1904 $$$emit32$src$$constant;
1905 %}
1907 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1908 // Load immediate does not have a zero or sign extended version
1909 // for 8-bit immediates
1910 emit_opcode(cbuf, $primary + $dst$$reg);
1911 $$$emit32$src$$constant;
1912 %}
1914 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1915 // Load immediate does not have a zero or sign extended version
1916 // for 8-bit immediates
1917 int dst_enc = $dst$$reg;
1918 int src_con = $src$$constant & 0x0FFFFFFFFL;
1919 if (src_con == 0) {
1920 // xor dst, dst
1921 emit_opcode(cbuf, 0x33);
1922 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1923 } else {
1924 emit_opcode(cbuf, $primary + dst_enc);
1925 emit_d32(cbuf, src_con);
1926 }
1927 %}
1929 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1930 // Load immediate does not have a zero or sign extended version
1931 // for 8-bit immediates
1932 int dst_enc = $dst$$reg + 2;
1933 int src_con = ((julong)($src$$constant)) >> 32;
1934 if (src_con == 0) {
1935 // xor dst, dst
1936 emit_opcode(cbuf, 0x33);
1937 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1938 } else {
1939 emit_opcode(cbuf, $primary + dst_enc);
1940 emit_d32(cbuf, src_con);
1941 }
1942 %}
1945 // Encode a reg-reg copy. If it is useless, then empty encoding.
1946 enc_class enc_Copy( eRegI dst, eRegI src ) %{
1947 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1948 %}
1950 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
1951 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1952 %}
1954 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1955 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1956 %}
1958 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1959 $$$emit8$primary;
1960 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1961 %}
1963 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1964 $$$emit8$secondary;
1965 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1966 %}
1968 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1969 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1970 %}
1972 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
1973 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1974 %}
1976 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
1977 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
1978 %}
1980 enc_class Con32 (immI src) %{ // Con32(storeImmI)
1981 // Output immediate
1982 $$$emit32$src$$constant;
1983 %}
1985 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
1986 // Output Float immediate bits
1987 jfloat jf = $src$$constant;
1988 int jf_as_bits = jint_cast( jf );
1989 emit_d32(cbuf, jf_as_bits);
1990 %}
1992 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
1993 // Output Float immediate bits
1994 jfloat jf = $src$$constant;
1995 int jf_as_bits = jint_cast( jf );
1996 emit_d32(cbuf, jf_as_bits);
1997 %}
1999 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2000 // Output immediate
2001 $$$emit16$src$$constant;
2002 %}
2004 enc_class Con_d32(immI src) %{
2005 emit_d32(cbuf,$src$$constant);
2006 %}
2008 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2009 // Output immediate memory reference
2010 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2011 emit_d32(cbuf, 0x00);
2012 %}
2014 enc_class lock_prefix( ) %{
2015 if( os::is_MP() )
2016 emit_opcode(cbuf,0xF0); // [Lock]
2017 %}
2019 // Cmp-xchg long value.
2020 // Note: we need to swap rbx, and rcx before and after the
2021 // cmpxchg8 instruction because the instruction uses
2022 // rcx as the high order word of the new value to store but
2023 // our register encoding uses rbx,.
2024 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2026 // XCHG rbx,ecx
2027 emit_opcode(cbuf,0x87);
2028 emit_opcode(cbuf,0xD9);
2029 // [Lock]
2030 if( os::is_MP() )
2031 emit_opcode(cbuf,0xF0);
2032 // CMPXCHG8 [Eptr]
2033 emit_opcode(cbuf,0x0F);
2034 emit_opcode(cbuf,0xC7);
2035 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2036 // XCHG rbx,ecx
2037 emit_opcode(cbuf,0x87);
2038 emit_opcode(cbuf,0xD9);
2039 %}
2041 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2042 // [Lock]
2043 if( os::is_MP() )
2044 emit_opcode(cbuf,0xF0);
2046 // CMPXCHG [Eptr]
2047 emit_opcode(cbuf,0x0F);
2048 emit_opcode(cbuf,0xB1);
2049 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2050 %}
2052 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2053 int res_encoding = $res$$reg;
2055 // MOV res,0
2056 emit_opcode( cbuf, 0xB8 + res_encoding);
2057 emit_d32( cbuf, 0 );
2058 // JNE,s fail
2059 emit_opcode(cbuf,0x75);
2060 emit_d8(cbuf, 5 );
2061 // MOV res,1
2062 emit_opcode( cbuf, 0xB8 + res_encoding);
2063 emit_d32( cbuf, 1 );
2064 // fail:
2065 %}
2067 enc_class set_instruction_start( ) %{
2068 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2069 %}
2071 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2072 int reg_encoding = $ereg$$reg;
2073 int base = $mem$$base;
2074 int index = $mem$$index;
2075 int scale = $mem$$scale;
2076 int displace = $mem$$disp;
2077 bool disp_is_oop = $mem->disp_is_oop();
2078 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2079 %}
2081 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2082 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2083 int base = $mem$$base;
2084 int index = $mem$$index;
2085 int scale = $mem$$scale;
2086 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2087 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2088 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2089 %}
2091 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2092 int r1, r2;
2093 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2094 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2095 emit_opcode(cbuf,0x0F);
2096 emit_opcode(cbuf,$tertiary);
2097 emit_rm(cbuf, 0x3, r1, r2);
2098 emit_d8(cbuf,$cnt$$constant);
2099 emit_d8(cbuf,$primary);
2100 emit_rm(cbuf, 0x3, $secondary, r1);
2101 emit_d8(cbuf,$cnt$$constant);
2102 %}
2104 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2105 emit_opcode( cbuf, 0x8B ); // Move
2106 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2107 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2108 emit_d8(cbuf,$primary);
2109 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2110 emit_d8(cbuf,$cnt$$constant-32);
2111 }
2112 emit_d8(cbuf,$primary);
2113 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2114 emit_d8(cbuf,31);
2115 %}
2117 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2118 int r1, r2;
2119 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2120 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2122 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2123 emit_rm(cbuf, 0x3, r1, r2);
2124 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2125 emit_opcode(cbuf,$primary);
2126 emit_rm(cbuf, 0x3, $secondary, r1);
2127 emit_d8(cbuf,$cnt$$constant-32);
2128 }
2129 emit_opcode(cbuf,0x33); // XOR r2,r2
2130 emit_rm(cbuf, 0x3, r2, r2);
2131 %}
2133 // Clone of RegMem but accepts an extra parameter to access each
2134 // half of a double in memory; it never needs relocation info.
2135 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2136 emit_opcode(cbuf,$opcode$$constant);
2137 int reg_encoding = $rm_reg$$reg;
2138 int base = $mem$$base;
2139 int index = $mem$$index;
2140 int scale = $mem$$scale;
2141 int displace = $mem$$disp + $disp_for_half$$constant;
2142 bool disp_is_oop = false;
2143 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2144 %}
2146 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2147 //
2148 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2149 // and it never needs relocation information.
2150 // Frequently used to move data between FPU's Stack Top and memory.
2151 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2152 int rm_byte_opcode = $rm_opcode$$constant;
2153 int base = $mem$$base;
2154 int index = $mem$$index;
2155 int scale = $mem$$scale;
2156 int displace = $mem$$disp;
2157 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2158 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2159 %}
2161 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2162 int rm_byte_opcode = $rm_opcode$$constant;
2163 int base = $mem$$base;
2164 int index = $mem$$index;
2165 int scale = $mem$$scale;
2166 int displace = $mem$$disp;
2167 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2168 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2169 %}
2171 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2172 int reg_encoding = $dst$$reg;
2173 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2174 int index = 0x04; // 0x04 indicates no index
2175 int scale = 0x00; // 0x00 indicates no scale
2176 int displace = $src1$$constant; // 0x00 indicates no displacement
2177 bool disp_is_oop = false;
2178 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2179 %}
2181 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2182 // Compare dst,src
2183 emit_opcode(cbuf,0x3B);
2184 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2185 // jmp dst < src around move
2186 emit_opcode(cbuf,0x7C);
2187 emit_d8(cbuf,2);
2188 // move dst,src
2189 emit_opcode(cbuf,0x8B);
2190 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2191 %}
2193 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2194 // Compare dst,src
2195 emit_opcode(cbuf,0x3B);
2196 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2197 // jmp dst > src around move
2198 emit_opcode(cbuf,0x7F);
2199 emit_d8(cbuf,2);
2200 // move dst,src
2201 emit_opcode(cbuf,0x8B);
2202 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2203 %}
2205 enc_class enc_FPR_store(memory mem, regDPR src) %{
2206 // If src is FPR1, we can just FST to store it.
2207 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2208 int reg_encoding = 0x2; // Just store
2209 int base = $mem$$base;
2210 int index = $mem$$index;
2211 int scale = $mem$$scale;
2212 int displace = $mem$$disp;
2213 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2214 if( $src$$reg != FPR1L_enc ) {
2215 reg_encoding = 0x3; // Store & pop
2216 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2217 emit_d8( cbuf, 0xC0-1+$src$$reg );
2218 }
2219 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2220 emit_opcode(cbuf,$primary);
2221 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2222 %}
2224 enc_class neg_reg(eRegI dst) %{
2225 // NEG $dst
2226 emit_opcode(cbuf,0xF7);
2227 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2228 %}
2230 enc_class setLT_reg(eCXRegI dst) %{
2231 // SETLT $dst
2232 emit_opcode(cbuf,0x0F);
2233 emit_opcode(cbuf,0x9C);
2234 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2235 %}
2237 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2238 int tmpReg = $tmp$$reg;
2240 // SUB $p,$q
2241 emit_opcode(cbuf,0x2B);
2242 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2243 // SBB $tmp,$tmp
2244 emit_opcode(cbuf,0x1B);
2245 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2246 // AND $tmp,$y
2247 emit_opcode(cbuf,0x23);
2248 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2249 // ADD $p,$tmp
2250 emit_opcode(cbuf,0x03);
2251 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2252 %}
2254 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2255 int tmpReg = $tmp$$reg;
2257 // SUB $p,$q
2258 emit_opcode(cbuf,0x2B);
2259 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2260 // SBB $tmp,$tmp
2261 emit_opcode(cbuf,0x1B);
2262 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2263 // AND $tmp,$y
2264 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2265 emit_opcode(cbuf,0x23);
2266 int reg_encoding = tmpReg;
2267 int base = $mem$$base;
2268 int index = $mem$$index;
2269 int scale = $mem$$scale;
2270 int displace = $mem$$disp;
2271 bool disp_is_oop = $mem->disp_is_oop();
2272 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2273 // ADD $p,$tmp
2274 emit_opcode(cbuf,0x03);
2275 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2276 %}
2278 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2279 // TEST shift,32
2280 emit_opcode(cbuf,0xF7);
2281 emit_rm(cbuf, 0x3, 0, ECX_enc);
2282 emit_d32(cbuf,0x20);
2283 // JEQ,s small
2284 emit_opcode(cbuf, 0x74);
2285 emit_d8(cbuf, 0x04);
2286 // MOV $dst.hi,$dst.lo
2287 emit_opcode( cbuf, 0x8B );
2288 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2289 // CLR $dst.lo
2290 emit_opcode(cbuf, 0x33);
2291 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2292 // small:
2293 // SHLD $dst.hi,$dst.lo,$shift
2294 emit_opcode(cbuf,0x0F);
2295 emit_opcode(cbuf,0xA5);
2296 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2297 // SHL $dst.lo,$shift"
2298 emit_opcode(cbuf,0xD3);
2299 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2300 %}
2302 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2303 // TEST shift,32
2304 emit_opcode(cbuf,0xF7);
2305 emit_rm(cbuf, 0x3, 0, ECX_enc);
2306 emit_d32(cbuf,0x20);
2307 // JEQ,s small
2308 emit_opcode(cbuf, 0x74);
2309 emit_d8(cbuf, 0x04);
2310 // MOV $dst.lo,$dst.hi
2311 emit_opcode( cbuf, 0x8B );
2312 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2313 // CLR $dst.hi
2314 emit_opcode(cbuf, 0x33);
2315 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2316 // small:
2317 // SHRD $dst.lo,$dst.hi,$shift
2318 emit_opcode(cbuf,0x0F);
2319 emit_opcode(cbuf,0xAD);
2320 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2321 // SHR $dst.hi,$shift"
2322 emit_opcode(cbuf,0xD3);
2323 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2324 %}
2326 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2327 // TEST shift,32
2328 emit_opcode(cbuf,0xF7);
2329 emit_rm(cbuf, 0x3, 0, ECX_enc);
2330 emit_d32(cbuf,0x20);
2331 // JEQ,s small
2332 emit_opcode(cbuf, 0x74);
2333 emit_d8(cbuf, 0x05);
2334 // MOV $dst.lo,$dst.hi
2335 emit_opcode( cbuf, 0x8B );
2336 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2337 // SAR $dst.hi,31
2338 emit_opcode(cbuf, 0xC1);
2339 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2340 emit_d8(cbuf, 0x1F );
2341 // small:
2342 // SHRD $dst.lo,$dst.hi,$shift
2343 emit_opcode(cbuf,0x0F);
2344 emit_opcode(cbuf,0xAD);
2345 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2346 // SAR $dst.hi,$shift"
2347 emit_opcode(cbuf,0xD3);
2348 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2349 %}
2352 // ----------------- Encodings for floating point unit -----------------
2353 // May leave result in FPU-TOS or FPU reg depending on opcodes
2354 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2355 $$$emit8$primary;
2356 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2357 %}
2359 // Pop argument in FPR0 with FSTP ST(0)
2360 enc_class PopFPU() %{
2361 emit_opcode( cbuf, 0xDD );
2362 emit_d8( cbuf, 0xD8 );
2363 %}
2365 // !!!!! equivalent to Pop_Reg_F
2366 enc_class Pop_Reg_DPR( regDPR dst ) %{
2367 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2368 emit_d8( cbuf, 0xD8+$dst$$reg );
2369 %}
2371 enc_class Push_Reg_DPR( regDPR dst ) %{
2372 emit_opcode( cbuf, 0xD9 );
2373 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2374 %}
2376 enc_class strictfp_bias1( regDPR dst ) %{
2377 emit_opcode( cbuf, 0xDB ); // FLD m80real
2378 emit_opcode( cbuf, 0x2D );
2379 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2380 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2381 emit_opcode( cbuf, 0xC8+$dst$$reg );
2382 %}
2384 enc_class strictfp_bias2( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xDB ); // FLD m80real
2386 emit_opcode( cbuf, 0x2D );
2387 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2388 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2389 emit_opcode( cbuf, 0xC8+$dst$$reg );
2390 %}
2392 // Special case for moving an integer register to a stack slot.
2393 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2394 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2395 %}
2397 // Special case for moving a register to a stack slot.
2398 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2399 // Opcode already emitted
2400 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2401 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2402 emit_d32(cbuf, $dst$$disp); // Displacement
2403 %}
2405 // Push the integer in stackSlot 'src' onto FP-stack
2406 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2407 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2408 %}
2410 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2411 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2412 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2413 %}
2415 // Same as Pop_Mem_F except for opcode
2416 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2417 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2418 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2419 %}
2421 enc_class Pop_Reg_FPR( regFPR dst ) %{
2422 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2423 emit_d8( cbuf, 0xD8+$dst$$reg );
2424 %}
2426 enc_class Push_Reg_FPR( regFPR dst ) %{
2427 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2428 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2429 %}
2431 // Push FPU's float to a stack-slot, and pop FPU-stack
2432 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2433 int pop = 0x02;
2434 if ($src$$reg != FPR1L_enc) {
2435 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2436 emit_d8( cbuf, 0xC0-1+$src$$reg );
2437 pop = 0x03;
2438 }
2439 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2440 %}
2442 // Push FPU's double to a stack-slot, and pop FPU-stack
2443 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2444 int pop = 0x02;
2445 if ($src$$reg != FPR1L_enc) {
2446 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2447 emit_d8( cbuf, 0xC0-1+$src$$reg );
2448 pop = 0x03;
2449 }
2450 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2451 %}
2453 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2454 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2455 int pop = 0xD0 - 1; // -1 since we skip FLD
2456 if ($src$$reg != FPR1L_enc) {
2457 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2458 emit_d8( cbuf, 0xC0-1+$src$$reg );
2459 pop = 0xD8;
2460 }
2461 emit_opcode( cbuf, 0xDD );
2462 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2463 %}
2466 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2467 // load dst in FPR0
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2470 if ($src$$reg != FPR1L_enc) {
2471 // fincstp
2472 emit_opcode (cbuf, 0xD9);
2473 emit_opcode (cbuf, 0xF7);
2474 // swap src with FPR1:
2475 // FXCH FPR1 with src
2476 emit_opcode(cbuf, 0xD9);
2477 emit_d8(cbuf, 0xC8-1+$src$$reg );
2478 // fdecstp
2479 emit_opcode (cbuf, 0xD9);
2480 emit_opcode (cbuf, 0xF6);
2481 }
2482 %}
2484 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2485 MacroAssembler _masm(&cbuf);
2486 __ subptr(rsp, 8);
2487 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2488 __ fld_d(Address(rsp, 0));
2489 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2490 __ fld_d(Address(rsp, 0));
2491 %}
2493 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2494 MacroAssembler _masm(&cbuf);
2495 __ subptr(rsp, 4);
2496 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2497 __ fld_s(Address(rsp, 0));
2498 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2499 __ fld_s(Address(rsp, 0));
2500 %}
2502 enc_class Push_ResultD(regD dst) %{
2503 MacroAssembler _masm(&cbuf);
2504 __ fstp_d(Address(rsp, 0));
2505 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2506 __ addptr(rsp, 8);
2507 %}
2509 enc_class Push_ResultF(regF dst, immI d8) %{
2510 MacroAssembler _masm(&cbuf);
2511 __ fstp_s(Address(rsp, 0));
2512 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2513 __ addptr(rsp, $d8$$constant);
2514 %}
2516 enc_class Push_SrcD(regD src) %{
2517 MacroAssembler _masm(&cbuf);
2518 __ subptr(rsp, 8);
2519 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2520 __ fld_d(Address(rsp, 0));
2521 %}
2523 enc_class push_stack_temp_qword() %{
2524 MacroAssembler _masm(&cbuf);
2525 __ subptr(rsp, 8);
2526 %}
2528 enc_class pop_stack_temp_qword() %{
2529 MacroAssembler _masm(&cbuf);
2530 __ addptr(rsp, 8);
2531 %}
2533 enc_class push_xmm_to_fpr1(regD src) %{
2534 MacroAssembler _masm(&cbuf);
2535 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2536 __ fld_d(Address(rsp, 0));
2537 %}
2539 // Compute X^Y using Intel's fast hardware instructions, if possible.
2540 // Otherwise return a NaN.
2541 enc_class pow_exp_core_encoding %{
2542 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2543 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2544 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2545 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2546 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2547 emit_opcode(cbuf,0x1C);
2548 emit_d8(cbuf,0x24);
2549 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2550 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2551 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2552 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2553 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2554 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2555 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2556 emit_d32(cbuf,0xFFFFF800);
2557 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2558 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2559 emit_d32(cbuf,1023);
2560 emit_opcode(cbuf,0x8B); // mov rbx,eax
2561 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2562 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2563 emit_rm(cbuf,0x3,0x4,EAX_enc);
2564 emit_d8(cbuf,20);
2565 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2566 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2567 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2568 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2569 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2570 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2571 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2572 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2573 emit_d32(cbuf,0);
2574 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2575 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2576 %}
2578 enc_class Push_Result_Mod_DPR( regDPR src) %{
2579 if ($src$$reg != FPR1L_enc) {
2580 // fincstp
2581 emit_opcode (cbuf, 0xD9);
2582 emit_opcode (cbuf, 0xF7);
2583 // FXCH FPR1 with src
2584 emit_opcode(cbuf, 0xD9);
2585 emit_d8(cbuf, 0xC8-1+$src$$reg );
2586 // fdecstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF6);
2589 }
2590 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2591 // // FSTP FPR$dst$$reg
2592 // emit_opcode( cbuf, 0xDD );
2593 // emit_d8( cbuf, 0xD8+$dst$$reg );
2594 %}
2596 enc_class fnstsw_sahf_skip_parity() %{
2597 // fnstsw ax
2598 emit_opcode( cbuf, 0xDF );
2599 emit_opcode( cbuf, 0xE0 );
2600 // sahf
2601 emit_opcode( cbuf, 0x9E );
2602 // jnp ::skip
2603 emit_opcode( cbuf, 0x7B );
2604 emit_opcode( cbuf, 0x05 );
2605 %}
2607 enc_class emitModDPR() %{
2608 // fprem must be iterative
2609 // :: loop
2610 // fprem
2611 emit_opcode( cbuf, 0xD9 );
2612 emit_opcode( cbuf, 0xF8 );
2613 // wait
2614 emit_opcode( cbuf, 0x9b );
2615 // fnstsw ax
2616 emit_opcode( cbuf, 0xDF );
2617 emit_opcode( cbuf, 0xE0 );
2618 // sahf
2619 emit_opcode( cbuf, 0x9E );
2620 // jp ::loop
2621 emit_opcode( cbuf, 0x0F );
2622 emit_opcode( cbuf, 0x8A );
2623 emit_opcode( cbuf, 0xF4 );
2624 emit_opcode( cbuf, 0xFF );
2625 emit_opcode( cbuf, 0xFF );
2626 emit_opcode( cbuf, 0xFF );
2627 %}
2629 enc_class fpu_flags() %{
2630 // fnstsw_ax
2631 emit_opcode( cbuf, 0xDF);
2632 emit_opcode( cbuf, 0xE0);
2633 // test ax,0x0400
2634 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2635 emit_opcode( cbuf, 0xA9 );
2636 emit_d16 ( cbuf, 0x0400 );
2637 // // // This sequence works, but stalls for 12-16 cycles on PPro
2638 // // test rax,0x0400
2639 // emit_opcode( cbuf, 0xA9 );
2640 // emit_d32 ( cbuf, 0x00000400 );
2641 //
2642 // jz exit (no unordered comparison)
2643 emit_opcode( cbuf, 0x74 );
2644 emit_d8 ( cbuf, 0x02 );
2645 // mov ah,1 - treat as LT case (set carry flag)
2646 emit_opcode( cbuf, 0xB4 );
2647 emit_d8 ( cbuf, 0x01 );
2648 // sahf
2649 emit_opcode( cbuf, 0x9E);
2650 %}
2652 enc_class cmpF_P6_fixup() %{
2653 // Fixup the integer flags in case comparison involved a NaN
2654 //
2655 // JNP exit (no unordered comparison, P-flag is set by NaN)
2656 emit_opcode( cbuf, 0x7B );
2657 emit_d8 ( cbuf, 0x03 );
2658 // MOV AH,1 - treat as LT case (set carry flag)
2659 emit_opcode( cbuf, 0xB4 );
2660 emit_d8 ( cbuf, 0x01 );
2661 // SAHF
2662 emit_opcode( cbuf, 0x9E);
2663 // NOP // target for branch to avoid branch to branch
2664 emit_opcode( cbuf, 0x90);
2665 %}
2667 // fnstsw_ax();
2668 // sahf();
2669 // movl(dst, nan_result);
2670 // jcc(Assembler::parity, exit);
2671 // movl(dst, less_result);
2672 // jcc(Assembler::below, exit);
2673 // movl(dst, equal_result);
2674 // jcc(Assembler::equal, exit);
2675 // movl(dst, greater_result);
2677 // less_result = 1;
2678 // greater_result = -1;
2679 // equal_result = 0;
2680 // nan_result = -1;
2682 enc_class CmpF_Result(eRegI dst) %{
2683 // fnstsw_ax();
2684 emit_opcode( cbuf, 0xDF);
2685 emit_opcode( cbuf, 0xE0);
2686 // sahf
2687 emit_opcode( cbuf, 0x9E);
2688 // movl(dst, nan_result);
2689 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2690 emit_d32( cbuf, -1 );
2691 // jcc(Assembler::parity, exit);
2692 emit_opcode( cbuf, 0x7A );
2693 emit_d8 ( cbuf, 0x13 );
2694 // movl(dst, less_result);
2695 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2696 emit_d32( cbuf, -1 );
2697 // jcc(Assembler::below, exit);
2698 emit_opcode( cbuf, 0x72 );
2699 emit_d8 ( cbuf, 0x0C );
2700 // movl(dst, equal_result);
2701 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2702 emit_d32( cbuf, 0 );
2703 // jcc(Assembler::equal, exit);
2704 emit_opcode( cbuf, 0x74 );
2705 emit_d8 ( cbuf, 0x05 );
2706 // movl(dst, greater_result);
2707 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2708 emit_d32( cbuf, 1 );
2709 %}
2712 // Compare the longs and set flags
2713 // BROKEN! Do Not use as-is
2714 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2715 // CMP $src1.hi,$src2.hi
2716 emit_opcode( cbuf, 0x3B );
2717 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2718 // JNE,s done
2719 emit_opcode(cbuf,0x75);
2720 emit_d8(cbuf, 2 );
2721 // CMP $src1.lo,$src2.lo
2722 emit_opcode( cbuf, 0x3B );
2723 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2724 // done:
2725 %}
2727 enc_class convert_int_long( regL dst, eRegI src ) %{
2728 // mov $dst.lo,$src
2729 int dst_encoding = $dst$$reg;
2730 int src_encoding = $src$$reg;
2731 encode_Copy( cbuf, dst_encoding , src_encoding );
2732 // mov $dst.hi,$src
2733 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2734 // sar $dst.hi,31
2735 emit_opcode( cbuf, 0xC1 );
2736 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2737 emit_d8(cbuf, 0x1F );
2738 %}
2740 enc_class convert_long_double( eRegL src ) %{
2741 // push $src.hi
2742 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2743 // push $src.lo
2744 emit_opcode(cbuf, 0x50+$src$$reg );
2745 // fild 64-bits at [SP]
2746 emit_opcode(cbuf,0xdf);
2747 emit_d8(cbuf, 0x6C);
2748 emit_d8(cbuf, 0x24);
2749 emit_d8(cbuf, 0x00);
2750 // pop stack
2751 emit_opcode(cbuf, 0x83); // add SP, #8
2752 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2753 emit_d8(cbuf, 0x8);
2754 %}
2756 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2757 // IMUL EDX:EAX,$src1
2758 emit_opcode( cbuf, 0xF7 );
2759 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2760 // SAR EDX,$cnt-32
2761 int shift_count = ((int)$cnt$$constant) - 32;
2762 if (shift_count > 0) {
2763 emit_opcode(cbuf, 0xC1);
2764 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2765 emit_d8(cbuf, shift_count);
2766 }
2767 %}
2769 // this version doesn't have add sp, 8
2770 enc_class convert_long_double2( eRegL src ) %{
2771 // push $src.hi
2772 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2773 // push $src.lo
2774 emit_opcode(cbuf, 0x50+$src$$reg );
2775 // fild 64-bits at [SP]
2776 emit_opcode(cbuf,0xdf);
2777 emit_d8(cbuf, 0x6C);
2778 emit_d8(cbuf, 0x24);
2779 emit_d8(cbuf, 0x00);
2780 %}
2782 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2783 // Basic idea: long = (long)int * (long)int
2784 // IMUL EDX:EAX, src
2785 emit_opcode( cbuf, 0xF7 );
2786 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2787 %}
2789 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2790 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2791 // MUL EDX:EAX, src
2792 emit_opcode( cbuf, 0xF7 );
2793 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2794 %}
2796 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2797 // Basic idea: lo(result) = lo(x_lo * y_lo)
2798 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2799 // MOV $tmp,$src.lo
2800 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2801 // IMUL $tmp,EDX
2802 emit_opcode( cbuf, 0x0F );
2803 emit_opcode( cbuf, 0xAF );
2804 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2805 // MOV EDX,$src.hi
2806 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2807 // IMUL EDX,EAX
2808 emit_opcode( cbuf, 0x0F );
2809 emit_opcode( cbuf, 0xAF );
2810 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2811 // ADD $tmp,EDX
2812 emit_opcode( cbuf, 0x03 );
2813 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2814 // MUL EDX:EAX,$src.lo
2815 emit_opcode( cbuf, 0xF7 );
2816 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2817 // ADD EDX,ESI
2818 emit_opcode( cbuf, 0x03 );
2819 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2820 %}
2822 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
2823 // Basic idea: lo(result) = lo(src * y_lo)
2824 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2825 // IMUL $tmp,EDX,$src
2826 emit_opcode( cbuf, 0x6B );
2827 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2828 emit_d8( cbuf, (int)$src$$constant );
2829 // MOV EDX,$src
2830 emit_opcode(cbuf, 0xB8 + EDX_enc);
2831 emit_d32( cbuf, (int)$src$$constant );
2832 // MUL EDX:EAX,EDX
2833 emit_opcode( cbuf, 0xF7 );
2834 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2835 // ADD EDX,ESI
2836 emit_opcode( cbuf, 0x03 );
2837 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2838 %}
2840 enc_class long_div( eRegL src1, eRegL src2 ) %{
2841 // PUSH src1.hi
2842 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2843 // PUSH src1.lo
2844 emit_opcode(cbuf, 0x50+$src1$$reg );
2845 // PUSH src2.hi
2846 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2847 // PUSH src2.lo
2848 emit_opcode(cbuf, 0x50+$src2$$reg );
2849 // CALL directly to the runtime
2850 cbuf.set_insts_mark();
2851 emit_opcode(cbuf,0xE8); // Call into runtime
2852 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2853 // Restore stack
2854 emit_opcode(cbuf, 0x83); // add SP, #framesize
2855 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2856 emit_d8(cbuf, 4*4);
2857 %}
2859 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2860 // PUSH src1.hi
2861 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2862 // PUSH src1.lo
2863 emit_opcode(cbuf, 0x50+$src1$$reg );
2864 // PUSH src2.hi
2865 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2866 // PUSH src2.lo
2867 emit_opcode(cbuf, 0x50+$src2$$reg );
2868 // CALL directly to the runtime
2869 cbuf.set_insts_mark();
2870 emit_opcode(cbuf,0xE8); // Call into runtime
2871 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2872 // Restore stack
2873 emit_opcode(cbuf, 0x83); // add SP, #framesize
2874 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2875 emit_d8(cbuf, 4*4);
2876 %}
2878 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
2879 // MOV $tmp,$src.lo
2880 emit_opcode(cbuf, 0x8B);
2881 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2882 // OR $tmp,$src.hi
2883 emit_opcode(cbuf, 0x0B);
2884 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2885 %}
2887 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2888 // CMP $src1.lo,$src2.lo
2889 emit_opcode( cbuf, 0x3B );
2890 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2891 // JNE,s skip
2892 emit_cc(cbuf, 0x70, 0x5);
2893 emit_d8(cbuf,2);
2894 // CMP $src1.hi,$src2.hi
2895 emit_opcode( cbuf, 0x3B );
2896 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2897 %}
2899 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
2900 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2901 emit_opcode( cbuf, 0x3B );
2902 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2903 // MOV $tmp,$src1.hi
2904 emit_opcode( cbuf, 0x8B );
2905 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2906 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2907 emit_opcode( cbuf, 0x1B );
2908 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2909 %}
2911 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
2912 // XOR $tmp,$tmp
2913 emit_opcode(cbuf,0x33); // XOR
2914 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2915 // CMP $tmp,$src.lo
2916 emit_opcode( cbuf, 0x3B );
2917 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2918 // SBB $tmp,$src.hi
2919 emit_opcode( cbuf, 0x1B );
2920 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2921 %}
2923 // Sniff, sniff... smells like Gnu Superoptimizer
2924 enc_class neg_long( eRegL dst ) %{
2925 emit_opcode(cbuf,0xF7); // NEG hi
2926 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2927 emit_opcode(cbuf,0xF7); // NEG lo
2928 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2929 emit_opcode(cbuf,0x83); // SBB hi,0
2930 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2931 emit_d8 (cbuf,0 );
2932 %}
2935 // Because the transitions from emitted code to the runtime
2936 // monitorenter/exit helper stubs are so slow it's critical that
2937 // we inline both the stack-locking fast-path and the inflated fast path.
2938 //
2939 // See also: cmpFastLock and cmpFastUnlock.
2940 //
2941 // What follows is a specialized inline transliteration of the code
2942 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2943 // another option would be to emit TrySlowEnter and TrySlowExit methods
2944 // at startup-time. These methods would accept arguments as
2945 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2946 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2947 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2948 // In practice, however, the # of lock sites is bounded and is usually small.
2949 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2950 // if the processor uses simple bimodal branch predictors keyed by EIP
2951 // Since the helper routines would be called from multiple synchronization
2952 // sites.
2953 //
2954 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2955 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2956 // to those specialized methods. That'd give us a mostly platform-independent
2957 // implementation that the JITs could optimize and inline at their pleasure.
2958 // Done correctly, the only time we'd need to cross to native could would be
2959 // to park() or unpark() threads. We'd also need a few more unsafe operators
2960 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2961 // (b) explicit barriers or fence operations.
2962 //
2963 // TODO:
2964 //
2965 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2966 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2967 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2968 // the lock operators would typically be faster than reifying Self.
2969 //
2970 // * Ideally I'd define the primitives as:
2971 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2972 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2973 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2974 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2975 // Furthermore the register assignments are overconstrained, possibly resulting in
2976 // sub-optimal code near the synchronization site.
2977 //
2978 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2979 // Alternately, use a better sp-proximity test.
2980 //
2981 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2982 // Either one is sufficient to uniquely identify a thread.
2983 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2984 //
2985 // * Intrinsify notify() and notifyAll() for the common cases where the
2986 // object is locked by the calling thread but the waitlist is empty.
2987 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2988 //
2989 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2990 // But beware of excessive branch density on AMD Opterons.
2991 //
2992 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2993 // or failure of the fast-path. If the fast-path fails then we pass
2994 // control to the slow-path, typically in C. In Fast_Lock and
2995 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2996 // will emit a conditional branch immediately after the node.
2997 // So we have branches to branches and lots of ICC.ZF games.
2998 // Instead, it might be better to have C2 pass a "FailureLabel"
2999 // into Fast_Lock and Fast_Unlock. In the case of success, control
3000 // will drop through the node. ICC.ZF is undefined at exit.
3001 // In the case of failure, the node will branch directly to the
3002 // FailureLabel
3005 // obj: object to lock
3006 // box: on-stack box address (displaced header location) - KILLED
3007 // rax,: tmp -- KILLED
3008 // scr: tmp -- KILLED
3009 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3011 Register objReg = as_Register($obj$$reg);
3012 Register boxReg = as_Register($box$$reg);
3013 Register tmpReg = as_Register($tmp$$reg);
3014 Register scrReg = as_Register($scr$$reg);
3016 // Ensure the register assignents are disjoint
3017 guarantee (objReg != boxReg, "") ;
3018 guarantee (objReg != tmpReg, "") ;
3019 guarantee (objReg != scrReg, "") ;
3020 guarantee (boxReg != tmpReg, "") ;
3021 guarantee (boxReg != scrReg, "") ;
3022 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3024 MacroAssembler masm(&cbuf);
3026 if (_counters != NULL) {
3027 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3028 }
3029 if (EmitSync & 1) {
3030 // set box->dhw = unused_mark (3)
3031 // Force all sync thru slow-path: slow_enter() and slow_exit()
3032 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3033 masm.cmpptr (rsp, (int32_t)0) ;
3034 } else
3035 if (EmitSync & 2) {
3036 Label DONE_LABEL ;
3037 if (UseBiasedLocking) {
3038 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3039 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3040 }
3042 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3043 masm.orptr (tmpReg, 0x1);
3044 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3045 if (os::is_MP()) { masm.lock(); }
3046 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3047 masm.jcc(Assembler::equal, DONE_LABEL);
3048 // Recursive locking
3049 masm.subptr(tmpReg, rsp);
3050 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3051 masm.movptr(Address(boxReg, 0), tmpReg);
3052 masm.bind(DONE_LABEL) ;
3053 } else {
3054 // Possible cases that we'll encounter in fast_lock
3055 // ------------------------------------------------
3056 // * Inflated
3057 // -- unlocked
3058 // -- Locked
3059 // = by self
3060 // = by other
3061 // * biased
3062 // -- by Self
3063 // -- by other
3064 // * neutral
3065 // * stack-locked
3066 // -- by self
3067 // = sp-proximity test hits
3068 // = sp-proximity test generates false-negative
3069 // -- by other
3070 //
3072 Label IsInflated, DONE_LABEL, PopDone ;
3074 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3075 // order to reduce the number of conditional branches in the most common cases.
3076 // Beware -- there's a subtle invariant that fetch of the markword
3077 // at [FETCH], below, will never observe a biased encoding (*101b).
3078 // If this invariant is not held we risk exclusion (safety) failure.
3079 if (UseBiasedLocking && !UseOptoBiasInlining) {
3080 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3081 }
3083 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3084 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3085 masm.jccb (Assembler::notZero, IsInflated) ;
3087 // Attempt stack-locking ...
3088 masm.orptr (tmpReg, 0x1);
3089 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3090 if (os::is_MP()) { masm.lock(); }
3091 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3092 if (_counters != NULL) {
3093 masm.cond_inc32(Assembler::equal,
3094 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3095 }
3096 masm.jccb (Assembler::equal, DONE_LABEL);
3098 // Recursive locking
3099 masm.subptr(tmpReg, rsp);
3100 masm.andptr(tmpReg, 0xFFFFF003 );
3101 masm.movptr(Address(boxReg, 0), tmpReg);
3102 if (_counters != NULL) {
3103 masm.cond_inc32(Assembler::equal,
3104 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3105 }
3106 masm.jmp (DONE_LABEL) ;
3108 masm.bind (IsInflated) ;
3110 // The object is inflated.
3111 //
3112 // TODO-FIXME: eliminate the ugly use of manifest constants:
3113 // Use markOopDesc::monitor_value instead of "2".
3114 // use markOop::unused_mark() instead of "3".
3115 // The tmpReg value is an objectMonitor reference ORed with
3116 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3117 // objectmonitor pointer by masking off the "2" bit or we can just
3118 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3119 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3120 //
3121 // I use the latter as it avoids AGI stalls.
3122 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3123 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3124 //
3125 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3127 // boxReg refers to the on-stack BasicLock in the current frame.
3128 // We'd like to write:
3129 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3130 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3131 // additional latency as we have another ST in the store buffer that must drain.
3133 if (EmitSync & 8192) {
3134 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3135 masm.get_thread (scrReg) ;
3136 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3137 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3138 if (os::is_MP()) { masm.lock(); }
3139 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3140 } else
3141 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3142 masm.movptr(scrReg, boxReg) ;
3143 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3145 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3146 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3147 // prefetchw [eax + Offset(_owner)-2]
3148 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3149 }
3151 if ((EmitSync & 64) == 0) {
3152 // Optimistic form: consider XORL tmpReg,tmpReg
3153 masm.movptr(tmpReg, NULL_WORD) ;
3154 } else {
3155 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3156 // Test-And-CAS instead of CAS
3157 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3158 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3159 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3160 }
3162 // Appears unlocked - try to swing _owner from null to non-null.
3163 // Ideally, I'd manifest "Self" with get_thread and then attempt
3164 // to CAS the register containing Self into m->Owner.
3165 // But we don't have enough registers, so instead we can either try to CAS
3166 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3167 // we later store "Self" into m->Owner. Transiently storing a stack address
3168 // (rsp or the address of the box) into m->owner is harmless.
3169 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3170 if (os::is_MP()) { masm.lock(); }
3171 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3172 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3173 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3174 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3175 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3176 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3178 // If the CAS fails we can either retry or pass control to the slow-path.
3179 // We use the latter tactic.
3180 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3181 // If the CAS was successful ...
3182 // Self has acquired the lock
3183 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3184 // Intentional fall-through into DONE_LABEL ...
3185 } else {
3186 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3187 masm.movptr(boxReg, tmpReg) ;
3189 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3190 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3191 // prefetchw [eax + Offset(_owner)-2]
3192 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3193 }
3195 if ((EmitSync & 64) == 0) {
3196 // Optimistic form
3197 masm.xorptr (tmpReg, tmpReg) ;
3198 } else {
3199 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3200 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3201 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3202 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3203 }
3205 // Appears unlocked - try to swing _owner from null to non-null.
3206 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3207 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3208 masm.get_thread (scrReg) ;
3209 if (os::is_MP()) { masm.lock(); }
3210 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3212 // If the CAS fails we can either retry or pass control to the slow-path.
3213 // We use the latter tactic.
3214 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3215 // If the CAS was successful ...
3216 // Self has acquired the lock
3217 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3218 // Intentional fall-through into DONE_LABEL ...
3219 }
3221 // DONE_LABEL is a hot target - we'd really like to place it at the
3222 // start of cache line by padding with NOPs.
3223 // See the AMD and Intel software optimization manuals for the
3224 // most efficient "long" NOP encodings.
3225 // Unfortunately none of our alignment mechanisms suffice.
3226 masm.bind(DONE_LABEL);
3228 // Avoid branch-to-branch on AMD processors
3229 // This appears to be superstition.
3230 if (EmitSync & 32) masm.nop() ;
3233 // At DONE_LABEL the icc ZFlag is set as follows ...
3234 // Fast_Unlock uses the same protocol.
3235 // ZFlag == 1 -> Success
3236 // ZFlag == 0 -> Failure - force control through the slow-path
3237 }
3238 %}
3240 // obj: object to unlock
3241 // box: box address (displaced header location), killed. Must be EAX.
3242 // rbx,: killed tmp; cannot be obj nor box.
3243 //
3244 // Some commentary on balanced locking:
3245 //
3246 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3247 // Methods that don't have provably balanced locking are forced to run in the
3248 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3249 // The interpreter provides two properties:
3250 // I1: At return-time the interpreter automatically and quietly unlocks any
3251 // objects acquired the current activation (frame). Recall that the
3252 // interpreter maintains an on-stack list of locks currently held by
3253 // a frame.
3254 // I2: If a method attempts to unlock an object that is not held by the
3255 // the frame the interpreter throws IMSX.
3256 //
3257 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3258 // B() doesn't have provably balanced locking so it runs in the interpreter.
3259 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3260 // is still locked by A().
3261 //
3262 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3263 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3264 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3265 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3267 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3269 Register objReg = as_Register($obj$$reg);
3270 Register boxReg = as_Register($box$$reg);
3271 Register tmpReg = as_Register($tmp$$reg);
3273 guarantee (objReg != boxReg, "") ;
3274 guarantee (objReg != tmpReg, "") ;
3275 guarantee (boxReg != tmpReg, "") ;
3276 guarantee (boxReg == as_Register(EAX_enc), "") ;
3277 MacroAssembler masm(&cbuf);
3279 if (EmitSync & 4) {
3280 // Disable - inhibit all inlining. Force control through the slow-path
3281 masm.cmpptr (rsp, 0) ;
3282 } else
3283 if (EmitSync & 8) {
3284 Label DONE_LABEL ;
3285 if (UseBiasedLocking) {
3286 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3287 }
3288 // classic stack-locking code ...
3289 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3290 masm.testptr(tmpReg, tmpReg) ;
3291 masm.jcc (Assembler::zero, DONE_LABEL) ;
3292 if (os::is_MP()) { masm.lock(); }
3293 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3294 masm.bind(DONE_LABEL);
3295 } else {
3296 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3298 // Critically, the biased locking test must have precedence over
3299 // and appear before the (box->dhw == 0) recursive stack-lock test.
3300 if (UseBiasedLocking && !UseOptoBiasInlining) {
3301 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3302 }
3304 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3305 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3306 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3308 masm.testptr(tmpReg, 0x02) ; // Inflated?
3309 masm.jccb (Assembler::zero, Stacked) ;
3311 masm.bind (Inflated) ;
3312 // It's inflated.
3313 // Despite our balanced locking property we still check that m->_owner == Self
3314 // as java routines or native JNI code called by this thread might
3315 // have released the lock.
3316 // Refer to the comments in synchronizer.cpp for how we might encode extra
3317 // state in _succ so we can avoid fetching EntryList|cxq.
3318 //
3319 // I'd like to add more cases in fast_lock() and fast_unlock() --
3320 // such as recursive enter and exit -- but we have to be wary of
3321 // I$ bloat, T$ effects and BP$ effects.
3322 //
3323 // If there's no contention try a 1-0 exit. That is, exit without
3324 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3325 // we detect and recover from the race that the 1-0 exit admits.
3326 //
3327 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3328 // before it STs null into _owner, releasing the lock. Updates
3329 // to data protected by the critical section must be visible before
3330 // we drop the lock (and thus before any other thread could acquire
3331 // the lock and observe the fields protected by the lock).
3332 // IA32's memory-model is SPO, so STs are ordered with respect to
3333 // each other and there's no need for an explicit barrier (fence).
3334 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3336 masm.get_thread (boxReg) ;
3337 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3338 // prefetchw [ebx + Offset(_owner)-2]
3339 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3340 }
3342 // Note that we could employ various encoding schemes to reduce
3343 // the number of loads below (currently 4) to just 2 or 3.
3344 // Refer to the comments in synchronizer.cpp.
3345 // In practice the chain of fetches doesn't seem to impact performance, however.
3346 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3347 // Attempt to reduce branch density - AMD's branch predictor.
3348 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3349 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3350 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3351 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3352 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3353 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3354 masm.jmpb (DONE_LABEL) ;
3355 } else {
3356 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3357 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3358 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3359 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3360 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3361 masm.jccb (Assembler::notZero, CheckSucc) ;
3362 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3363 masm.jmpb (DONE_LABEL) ;
3364 }
3366 // The Following code fragment (EmitSync & 65536) improves the performance of
3367 // contended applications and contended synchronization microbenchmarks.
3368 // Unfortunately the emission of the code - even though not executed - causes regressions
3369 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3370 // with an equal number of never-executed NOPs results in the same regression.
3371 // We leave it off by default.
3373 if ((EmitSync & 65536) != 0) {
3374 Label LSuccess, LGoSlowPath ;
3376 masm.bind (CheckSucc) ;
3378 // Optional pre-test ... it's safe to elide this
3379 if ((EmitSync & 16) == 0) {
3380 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3381 masm.jccb (Assembler::zero, LGoSlowPath) ;
3382 }
3384 // We have a classic Dekker-style idiom:
3385 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3386 // There are a number of ways to implement the barrier:
3387 // (1) lock:andl &m->_owner, 0
3388 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3389 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3390 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3391 // (2) If supported, an explicit MFENCE is appealing.
3392 // In older IA32 processors MFENCE is slower than lock:add or xchg
3393 // particularly if the write-buffer is full as might be the case if
3394 // if stores closely precede the fence or fence-equivalent instruction.
3395 // In more modern implementations MFENCE appears faster, however.
3396 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3397 // The $lines underlying the top-of-stack should be in M-state.
3398 // The locked add instruction is serializing, of course.
3399 // (4) Use xchg, which is serializing
3400 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3401 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3402 // The integer condition codes will tell us if succ was 0.
3403 // Since _succ and _owner should reside in the same $line and
3404 // we just stored into _owner, it's likely that the $line
3405 // remains in M-state for the lock:orl.
3406 //
3407 // We currently use (3), although it's likely that switching to (2)
3408 // is correct for the future.
3410 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3411 if (os::is_MP()) {
3412 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3413 masm.mfence();
3414 } else {
3415 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3416 }
3417 }
3418 // Ratify _succ remains non-null
3419 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3420 masm.jccb (Assembler::notZero, LSuccess) ;
3422 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3423 if (os::is_MP()) { masm.lock(); }
3424 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3425 masm.jccb (Assembler::notEqual, LSuccess) ;
3426 // Since we're low on registers we installed rsp as a placeholding in _owner.
3427 // Now install Self over rsp. This is safe as we're transitioning from
3428 // non-null to non=null
3429 masm.get_thread (boxReg) ;
3430 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3431 // Intentional fall-through into LGoSlowPath ...
3433 masm.bind (LGoSlowPath) ;
3434 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3435 masm.jmpb (DONE_LABEL) ;
3437 masm.bind (LSuccess) ;
3438 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3439 masm.jmpb (DONE_LABEL) ;
3440 }
3442 masm.bind (Stacked) ;
3443 // It's not inflated and it's not recursively stack-locked and it's not biased.
3444 // It must be stack-locked.
3445 // Try to reset the header to displaced header.
3446 // The "box" value on the stack is stable, so we can reload
3447 // and be assured we observe the same value as above.
3448 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3449 if (os::is_MP()) { masm.lock(); }
3450 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3451 // Intention fall-thru into DONE_LABEL
3454 // DONE_LABEL is a hot target - we'd really like to place it at the
3455 // start of cache line by padding with NOPs.
3456 // See the AMD and Intel software optimization manuals for the
3457 // most efficient "long" NOP encodings.
3458 // Unfortunately none of our alignment mechanisms suffice.
3459 if ((EmitSync & 65536) == 0) {
3460 masm.bind (CheckSucc) ;
3461 }
3462 masm.bind(DONE_LABEL);
3464 // Avoid branch to branch on AMD processors
3465 if (EmitSync & 32768) { masm.nop() ; }
3466 }
3467 %}
3470 enc_class enc_pop_rdx() %{
3471 emit_opcode(cbuf,0x5A);
3472 %}
3474 enc_class enc_rethrow() %{
3475 cbuf.set_insts_mark();
3476 emit_opcode(cbuf, 0xE9); // jmp entry
3477 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3478 runtime_call_Relocation::spec(), RELOC_IMM32 );
3479 %}
3482 // Convert a double to an int. Java semantics require we do complex
3483 // manglelations in the corner cases. So we set the rounding mode to
3484 // 'zero', store the darned double down as an int, and reset the
3485 // rounding mode to 'nearest'. The hardware throws an exception which
3486 // patches up the correct value directly to the stack.
3487 enc_class DPR2I_encoding( regDPR src ) %{
3488 // Flip to round-to-zero mode. We attempted to allow invalid-op
3489 // exceptions here, so that a NAN or other corner-case value will
3490 // thrown an exception (but normal values get converted at full speed).
3491 // However, I2C adapters and other float-stack manglers leave pending
3492 // invalid-op exceptions hanging. We would have to clear them before
3493 // enabling them and that is more expensive than just testing for the
3494 // invalid value Intel stores down in the corner cases.
3495 emit_opcode(cbuf,0xD9); // FLDCW trunc
3496 emit_opcode(cbuf,0x2D);
3497 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3498 // Allocate a word
3499 emit_opcode(cbuf,0x83); // SUB ESP,4
3500 emit_opcode(cbuf,0xEC);
3501 emit_d8(cbuf,0x04);
3502 // Encoding assumes a double has been pushed into FPR0.
3503 // Store down the double as an int, popping the FPU stack
3504 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3505 emit_opcode(cbuf,0x1C);
3506 emit_d8(cbuf,0x24);
3507 // Restore the rounding mode; mask the exception
3508 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3509 emit_opcode(cbuf,0x2D);
3510 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3511 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3512 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3514 // Load the converted int; adjust CPU stack
3515 emit_opcode(cbuf,0x58); // POP EAX
3516 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3517 emit_d32 (cbuf,0x80000000); // 0x80000000
3518 emit_opcode(cbuf,0x75); // JNE around_slow_call
3519 emit_d8 (cbuf,0x07); // Size of slow_call
3520 // Push src onto stack slow-path
3521 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3522 emit_d8 (cbuf,0xC0-1+$src$$reg );
3523 // CALL directly to the runtime
3524 cbuf.set_insts_mark();
3525 emit_opcode(cbuf,0xE8); // Call into runtime
3526 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3527 // Carry on here...
3528 %}
3530 enc_class DPR2L_encoding( regDPR src ) %{
3531 emit_opcode(cbuf,0xD9); // FLDCW trunc
3532 emit_opcode(cbuf,0x2D);
3533 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3534 // Allocate a word
3535 emit_opcode(cbuf,0x83); // SUB ESP,8
3536 emit_opcode(cbuf,0xEC);
3537 emit_d8(cbuf,0x08);
3538 // Encoding assumes a double has been pushed into FPR0.
3539 // Store down the double as a long, popping the FPU stack
3540 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3541 emit_opcode(cbuf,0x3C);
3542 emit_d8(cbuf,0x24);
3543 // Restore the rounding mode; mask the exception
3544 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3545 emit_opcode(cbuf,0x2D);
3546 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3547 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3548 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3550 // Load the converted int; adjust CPU stack
3551 emit_opcode(cbuf,0x58); // POP EAX
3552 emit_opcode(cbuf,0x5A); // POP EDX
3553 emit_opcode(cbuf,0x81); // CMP EDX,imm
3554 emit_d8 (cbuf,0xFA); // rdx
3555 emit_d32 (cbuf,0x80000000); // 0x80000000
3556 emit_opcode(cbuf,0x75); // JNE around_slow_call
3557 emit_d8 (cbuf,0x07+4); // Size of slow_call
3558 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3559 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3560 emit_opcode(cbuf,0x75); // JNE around_slow_call
3561 emit_d8 (cbuf,0x07); // Size of slow_call
3562 // Push src onto stack slow-path
3563 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3564 emit_d8 (cbuf,0xC0-1+$src$$reg );
3565 // CALL directly to the runtime
3566 cbuf.set_insts_mark();
3567 emit_opcode(cbuf,0xE8); // Call into runtime
3568 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3569 // Carry on here...
3570 %}
3572 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3573 // Operand was loaded from memory into fp ST (stack top)
3574 // FMUL ST,$src /* D8 C8+i */
3575 emit_opcode(cbuf, 0xD8);
3576 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3577 %}
3579 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3580 // FADDP ST,src2 /* D8 C0+i */
3581 emit_opcode(cbuf, 0xD8);
3582 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3583 //could use FADDP src2,fpST /* DE C0+i */
3584 %}
3586 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3587 // FADDP src2,ST /* DE C0+i */
3588 emit_opcode(cbuf, 0xDE);
3589 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3590 %}
3592 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3593 // Operand has been loaded into fp ST (stack top)
3594 // FSUB ST,$src1
3595 emit_opcode(cbuf, 0xD8);
3596 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3598 // FDIV
3599 emit_opcode(cbuf, 0xD8);
3600 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3601 %}
3603 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3604 // Operand was loaded from memory into fp ST (stack top)
3605 // FADD ST,$src /* D8 C0+i */
3606 emit_opcode(cbuf, 0xD8);
3607 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3609 // FMUL ST,src2 /* D8 C*+i */
3610 emit_opcode(cbuf, 0xD8);
3611 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3612 %}
3615 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3616 // Operand was loaded from memory into fp ST (stack top)
3617 // FADD ST,$src /* D8 C0+i */
3618 emit_opcode(cbuf, 0xD8);
3619 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3621 // FMULP src2,ST /* DE C8+i */
3622 emit_opcode(cbuf, 0xDE);
3623 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3624 %}
3626 // Atomically load the volatile long
3627 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3628 emit_opcode(cbuf,0xDF);
3629 int rm_byte_opcode = 0x05;
3630 int base = $mem$$base;
3631 int index = $mem$$index;
3632 int scale = $mem$$scale;
3633 int displace = $mem$$disp;
3634 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3635 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3636 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3637 %}
3639 // Volatile Store Long. Must be atomic, so move it into
3640 // the FP TOS and then do a 64-bit FIST. Has to probe the
3641 // target address before the store (for null-ptr checks)
3642 // so the memory operand is used twice in the encoding.
3643 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3644 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3645 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3646 emit_opcode(cbuf,0xDF);
3647 int rm_byte_opcode = 0x07;
3648 int base = $mem$$base;
3649 int index = $mem$$index;
3650 int scale = $mem$$scale;
3651 int displace = $mem$$disp;
3652 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3653 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3654 %}
3656 // Safepoint Poll. This polls the safepoint page, and causes an
3657 // exception if it is not readable. Unfortunately, it kills the condition code
3658 // in the process
3659 // We current use TESTL [spp],EDI
3660 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3662 enc_class Safepoint_Poll() %{
3663 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3664 emit_opcode(cbuf,0x85);
3665 emit_rm (cbuf, 0x0, 0x7, 0x5);
3666 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3667 %}
3668 %}
3671 //----------FRAME--------------------------------------------------------------
3672 // Definition of frame structure and management information.
3673 //
3674 // S T A C K L A Y O U T Allocators stack-slot number
3675 // | (to get allocators register number
3676 // G Owned by | | v add OptoReg::stack0())
3677 // r CALLER | |
3678 // o | +--------+ pad to even-align allocators stack-slot
3679 // w V | pad0 | numbers; owned by CALLER
3680 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3681 // h ^ | in | 5
3682 // | | args | 4 Holes in incoming args owned by SELF
3683 // | | | | 3
3684 // | | +--------+
3685 // V | | old out| Empty on Intel, window on Sparc
3686 // | old |preserve| Must be even aligned.
3687 // | SP-+--------+----> Matcher::_old_SP, even aligned
3688 // | | in | 3 area for Intel ret address
3689 // Owned by |preserve| Empty on Sparc.
3690 // SELF +--------+
3691 // | | pad2 | 2 pad to align old SP
3692 // | +--------+ 1
3693 // | | locks | 0
3694 // | +--------+----> OptoReg::stack0(), even aligned
3695 // | | pad1 | 11 pad to align new SP
3696 // | +--------+
3697 // | | | 10
3698 // | | spills | 9 spills
3699 // V | | 8 (pad0 slot for callee)
3700 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3701 // ^ | out | 7
3702 // | | args | 6 Holes in outgoing args owned by CALLEE
3703 // Owned by +--------+
3704 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3705 // | new |preserve| Must be even-aligned.
3706 // | SP-+--------+----> Matcher::_new_SP, even aligned
3707 // | | |
3708 //
3709 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3710 // known from SELF's arguments and the Java calling convention.
3711 // Region 6-7 is determined per call site.
3712 // Note 2: If the calling convention leaves holes in the incoming argument
3713 // area, those holes are owned by SELF. Holes in the outgoing area
3714 // are owned by the CALLEE. Holes should not be nessecary in the
3715 // incoming area, as the Java calling convention is completely under
3716 // the control of the AD file. Doubles can be sorted and packed to
3717 // avoid holes. Holes in the outgoing arguments may be nessecary for
3718 // varargs C calling conventions.
3719 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3720 // even aligned with pad0 as needed.
3721 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3722 // region 6-11 is even aligned; it may be padded out more so that
3723 // the region from SP to FP meets the minimum stack alignment.
3725 frame %{
3726 // What direction does stack grow in (assumed to be same for C & Java)
3727 stack_direction(TOWARDS_LOW);
3729 // These three registers define part of the calling convention
3730 // between compiled code and the interpreter.
3731 inline_cache_reg(EAX); // Inline Cache Register
3732 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3734 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3735 cisc_spilling_operand_name(indOffset32);
3737 // Number of stack slots consumed by locking an object
3738 sync_stack_slots(1);
3740 // Compiled code's Frame Pointer
3741 frame_pointer(ESP);
3742 // Interpreter stores its frame pointer in a register which is
3743 // stored to the stack by I2CAdaptors.
3744 // I2CAdaptors convert from interpreted java to compiled java.
3745 interpreter_frame_pointer(EBP);
3747 // Stack alignment requirement
3748 // Alignment size in bytes (128-bit -> 16 bytes)
3749 stack_alignment(StackAlignmentInBytes);
3751 // Number of stack slots between incoming argument block and the start of
3752 // a new frame. The PROLOG must add this many slots to the stack. The
3753 // EPILOG must remove this many slots. Intel needs one slot for
3754 // return address and one for rbp, (must save rbp)
3755 in_preserve_stack_slots(2+VerifyStackAtCalls);
3757 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3758 // for calls to C. Supports the var-args backing area for register parms.
3759 varargs_C_out_slots_killed(0);
3761 // The after-PROLOG location of the return address. Location of
3762 // return address specifies a type (REG or STACK) and a number
3763 // representing the register number (i.e. - use a register name) or
3764 // stack slot.
3765 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3766 // Otherwise, it is above the locks and verification slot and alignment word
3767 return_addr(STACK - 1 +
3768 round_to((Compile::current()->in_preserve_stack_slots() +
3769 Compile::current()->fixed_slots()),
3770 stack_alignment_in_slots()));
3772 // Body of function which returns an integer array locating
3773 // arguments either in registers or in stack slots. Passed an array
3774 // of ideal registers called "sig" and a "length" count. Stack-slot
3775 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3776 // arguments for a CALLEE. Incoming stack arguments are
3777 // automatically biased by the preserve_stack_slots field above.
3778 calling_convention %{
3779 // No difference between ingoing/outgoing just pass false
3780 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3781 %}
3784 // Body of function which returns an integer array locating
3785 // arguments either in registers or in stack slots. Passed an array
3786 // of ideal registers called "sig" and a "length" count. Stack-slot
3787 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3788 // arguments for a CALLEE. Incoming stack arguments are
3789 // automatically biased by the preserve_stack_slots field above.
3790 c_calling_convention %{
3791 // This is obviously always outgoing
3792 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3793 %}
3795 // Location of C & interpreter return values
3796 c_return_value %{
3797 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3798 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3799 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3801 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3802 // that C functions return float and double results in XMM0.
3803 if( ideal_reg == Op_RegD && UseSSE>=2 )
3804 return OptoRegPair(XMM0b_num,XMM0a_num);
3805 if( ideal_reg == Op_RegF && UseSSE>=2 )
3806 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3808 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3809 %}
3811 // Location of return values
3812 return_value %{
3813 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3814 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3815 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3816 if( ideal_reg == Op_RegD && UseSSE>=2 )
3817 return OptoRegPair(XMM0b_num,XMM0a_num);
3818 if( ideal_reg == Op_RegF && UseSSE>=1 )
3819 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3820 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3821 %}
3823 %}
3825 //----------ATTRIBUTES---------------------------------------------------------
3826 //----------Operand Attributes-------------------------------------------------
3827 op_attrib op_cost(0); // Required cost attribute
3829 //----------Instruction Attributes---------------------------------------------
3830 ins_attrib ins_cost(100); // Required cost attribute
3831 ins_attrib ins_size(8); // Required size attribute (in bits)
3832 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3833 // non-matching short branch variant of some
3834 // long branch?
3835 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3836 // specifies the alignment that some part of the instruction (not
3837 // necessarily the start) requires. If > 1, a compute_padding()
3838 // function must be provided for the instruction
3840 //----------OPERANDS-----------------------------------------------------------
3841 // Operand definitions must precede instruction definitions for correct parsing
3842 // in the ADLC because operands constitute user defined types which are used in
3843 // instruction definitions.
3845 //----------Simple Operands----------------------------------------------------
3846 // Immediate Operands
3847 // Integer Immediate
3848 operand immI() %{
3849 match(ConI);
3851 op_cost(10);
3852 format %{ %}
3853 interface(CONST_INTER);
3854 %}
3856 // Constant for test vs zero
3857 operand immI0() %{
3858 predicate(n->get_int() == 0);
3859 match(ConI);
3861 op_cost(0);
3862 format %{ %}
3863 interface(CONST_INTER);
3864 %}
3866 // Constant for increment
3867 operand immI1() %{
3868 predicate(n->get_int() == 1);
3869 match(ConI);
3871 op_cost(0);
3872 format %{ %}
3873 interface(CONST_INTER);
3874 %}
3876 // Constant for decrement
3877 operand immI_M1() %{
3878 predicate(n->get_int() == -1);
3879 match(ConI);
3881 op_cost(0);
3882 format %{ %}
3883 interface(CONST_INTER);
3884 %}
3886 // Valid scale values for addressing modes
3887 operand immI2() %{
3888 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3889 match(ConI);
3891 format %{ %}
3892 interface(CONST_INTER);
3893 %}
3895 operand immI8() %{
3896 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3897 match(ConI);
3899 op_cost(5);
3900 format %{ %}
3901 interface(CONST_INTER);
3902 %}
3904 operand immI16() %{
3905 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3906 match(ConI);
3908 op_cost(10);
3909 format %{ %}
3910 interface(CONST_INTER);
3911 %}
3913 // Constant for long shifts
3914 operand immI_32() %{
3915 predicate( n->get_int() == 32 );
3916 match(ConI);
3918 op_cost(0);
3919 format %{ %}
3920 interface(CONST_INTER);
3921 %}
3923 operand immI_1_31() %{
3924 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3925 match(ConI);
3927 op_cost(0);
3928 format %{ %}
3929 interface(CONST_INTER);
3930 %}
3932 operand immI_32_63() %{
3933 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3934 match(ConI);
3935 op_cost(0);
3937 format %{ %}
3938 interface(CONST_INTER);
3939 %}
3941 operand immI_1() %{
3942 predicate( n->get_int() == 1 );
3943 match(ConI);
3945 op_cost(0);
3946 format %{ %}
3947 interface(CONST_INTER);
3948 %}
3950 operand immI_2() %{
3951 predicate( n->get_int() == 2 );
3952 match(ConI);
3954 op_cost(0);
3955 format %{ %}
3956 interface(CONST_INTER);
3957 %}
3959 operand immI_3() %{
3960 predicate( n->get_int() == 3 );
3961 match(ConI);
3963 op_cost(0);
3964 format %{ %}
3965 interface(CONST_INTER);
3966 %}
3968 // Pointer Immediate
3969 operand immP() %{
3970 match(ConP);
3972 op_cost(10);
3973 format %{ %}
3974 interface(CONST_INTER);
3975 %}
3977 // NULL Pointer Immediate
3978 operand immP0() %{
3979 predicate( n->get_ptr() == 0 );
3980 match(ConP);
3981 op_cost(0);
3983 format %{ %}
3984 interface(CONST_INTER);
3985 %}
3987 // Long Immediate
3988 operand immL() %{
3989 match(ConL);
3991 op_cost(20);
3992 format %{ %}
3993 interface(CONST_INTER);
3994 %}
3996 // Long Immediate zero
3997 operand immL0() %{
3998 predicate( n->get_long() == 0L );
3999 match(ConL);
4000 op_cost(0);
4002 format %{ %}
4003 interface(CONST_INTER);
4004 %}
4006 // Long Immediate zero
4007 operand immL_M1() %{
4008 predicate( n->get_long() == -1L );
4009 match(ConL);
4010 op_cost(0);
4012 format %{ %}
4013 interface(CONST_INTER);
4014 %}
4016 // Long immediate from 0 to 127.
4017 // Used for a shorter form of long mul by 10.
4018 operand immL_127() %{
4019 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4020 match(ConL);
4021 op_cost(0);
4023 format %{ %}
4024 interface(CONST_INTER);
4025 %}
4027 // Long Immediate: low 32-bit mask
4028 operand immL_32bits() %{
4029 predicate(n->get_long() == 0xFFFFFFFFL);
4030 match(ConL);
4031 op_cost(0);
4033 format %{ %}
4034 interface(CONST_INTER);
4035 %}
4037 // Long Immediate: low 32-bit mask
4038 operand immL32() %{
4039 predicate(n->get_long() == (int)(n->get_long()));
4040 match(ConL);
4041 op_cost(20);
4043 format %{ %}
4044 interface(CONST_INTER);
4045 %}
4047 //Double Immediate zero
4048 operand immDPR0() %{
4049 // Do additional (and counter-intuitive) test against NaN to work around VC++
4050 // bug that generates code such that NaNs compare equal to 0.0
4051 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4052 match(ConD);
4054 op_cost(5);
4055 format %{ %}
4056 interface(CONST_INTER);
4057 %}
4059 // Double Immediate one
4060 operand immDPR1() %{
4061 predicate( UseSSE<=1 && n->getd() == 1.0 );
4062 match(ConD);
4064 op_cost(5);
4065 format %{ %}
4066 interface(CONST_INTER);
4067 %}
4069 // Double Immediate
4070 operand immDPR() %{
4071 predicate(UseSSE<=1);
4072 match(ConD);
4074 op_cost(5);
4075 format %{ %}
4076 interface(CONST_INTER);
4077 %}
4079 operand immD() %{
4080 predicate(UseSSE>=2);
4081 match(ConD);
4083 op_cost(5);
4084 format %{ %}
4085 interface(CONST_INTER);
4086 %}
4088 // Double Immediate zero
4089 operand immD0() %{
4090 // Do additional (and counter-intuitive) test against NaN to work around VC++
4091 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4092 // compare equal to -0.0.
4093 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4094 match(ConD);
4096 format %{ %}
4097 interface(CONST_INTER);
4098 %}
4100 // Float Immediate zero
4101 operand immFPR0() %{
4102 predicate(UseSSE == 0 && n->getf() == 0.0F);
4103 match(ConF);
4105 op_cost(5);
4106 format %{ %}
4107 interface(CONST_INTER);
4108 %}
4110 // Float Immediate one
4111 operand immFPR1() %{
4112 predicate(UseSSE == 0 && n->getf() == 1.0F);
4113 match(ConF);
4115 op_cost(5);
4116 format %{ %}
4117 interface(CONST_INTER);
4118 %}
4120 // Float Immediate
4121 operand immFPR() %{
4122 predicate( UseSSE == 0 );
4123 match(ConF);
4125 op_cost(5);
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4130 // Float Immediate
4131 operand immF() %{
4132 predicate(UseSSE >= 1);
4133 match(ConF);
4135 op_cost(5);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4140 // Float Immediate zero. Zero and not -0.0
4141 operand immF0() %{
4142 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4143 match(ConF);
4145 op_cost(5);
4146 format %{ %}
4147 interface(CONST_INTER);
4148 %}
4150 // Immediates for special shifts (sign extend)
4152 // Constants for increment
4153 operand immI_16() %{
4154 predicate( n->get_int() == 16 );
4155 match(ConI);
4157 format %{ %}
4158 interface(CONST_INTER);
4159 %}
4161 operand immI_24() %{
4162 predicate( n->get_int() == 24 );
4163 match(ConI);
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4169 // Constant for byte-wide masking
4170 operand immI_255() %{
4171 predicate( n->get_int() == 255 );
4172 match(ConI);
4174 format %{ %}
4175 interface(CONST_INTER);
4176 %}
4178 // Constant for short-wide masking
4179 operand immI_65535() %{
4180 predicate(n->get_int() == 65535);
4181 match(ConI);
4183 format %{ %}
4184 interface(CONST_INTER);
4185 %}
4187 // Register Operands
4188 // Integer Register
4189 operand eRegI() %{
4190 constraint(ALLOC_IN_RC(e_reg));
4191 match(RegI);
4192 match(xRegI);
4193 match(eAXRegI);
4194 match(eBXRegI);
4195 match(eCXRegI);
4196 match(eDXRegI);
4197 match(eDIRegI);
4198 match(eSIRegI);
4200 format %{ %}
4201 interface(REG_INTER);
4202 %}
4204 // Subset of Integer Register
4205 operand xRegI(eRegI reg) %{
4206 constraint(ALLOC_IN_RC(x_reg));
4207 match(reg);
4208 match(eAXRegI);
4209 match(eBXRegI);
4210 match(eCXRegI);
4211 match(eDXRegI);
4213 format %{ %}
4214 interface(REG_INTER);
4215 %}
4217 // Special Registers
4218 operand eAXRegI(xRegI reg) %{
4219 constraint(ALLOC_IN_RC(eax_reg));
4220 match(reg);
4221 match(eRegI);
4223 format %{ "EAX" %}
4224 interface(REG_INTER);
4225 %}
4227 // Special Registers
4228 operand eBXRegI(xRegI reg) %{
4229 constraint(ALLOC_IN_RC(ebx_reg));
4230 match(reg);
4231 match(eRegI);
4233 format %{ "EBX" %}
4234 interface(REG_INTER);
4235 %}
4237 operand eCXRegI(xRegI reg) %{
4238 constraint(ALLOC_IN_RC(ecx_reg));
4239 match(reg);
4240 match(eRegI);
4242 format %{ "ECX" %}
4243 interface(REG_INTER);
4244 %}
4246 operand eDXRegI(xRegI reg) %{
4247 constraint(ALLOC_IN_RC(edx_reg));
4248 match(reg);
4249 match(eRegI);
4251 format %{ "EDX" %}
4252 interface(REG_INTER);
4253 %}
4255 operand eDIRegI(xRegI reg) %{
4256 constraint(ALLOC_IN_RC(edi_reg));
4257 match(reg);
4258 match(eRegI);
4260 format %{ "EDI" %}
4261 interface(REG_INTER);
4262 %}
4264 operand naxRegI() %{
4265 constraint(ALLOC_IN_RC(nax_reg));
4266 match(RegI);
4267 match(eCXRegI);
4268 match(eDXRegI);
4269 match(eSIRegI);
4270 match(eDIRegI);
4272 format %{ %}
4273 interface(REG_INTER);
4274 %}
4276 operand nadxRegI() %{
4277 constraint(ALLOC_IN_RC(nadx_reg));
4278 match(RegI);
4279 match(eBXRegI);
4280 match(eCXRegI);
4281 match(eSIRegI);
4282 match(eDIRegI);
4284 format %{ %}
4285 interface(REG_INTER);
4286 %}
4288 operand ncxRegI() %{
4289 constraint(ALLOC_IN_RC(ncx_reg));
4290 match(RegI);
4291 match(eAXRegI);
4292 match(eDXRegI);
4293 match(eSIRegI);
4294 match(eDIRegI);
4296 format %{ %}
4297 interface(REG_INTER);
4298 %}
4300 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4301 // //
4302 operand eSIRegI(xRegI reg) %{
4303 constraint(ALLOC_IN_RC(esi_reg));
4304 match(reg);
4305 match(eRegI);
4307 format %{ "ESI" %}
4308 interface(REG_INTER);
4309 %}
4311 // Pointer Register
4312 operand anyRegP() %{
4313 constraint(ALLOC_IN_RC(any_reg));
4314 match(RegP);
4315 match(eAXRegP);
4316 match(eBXRegP);
4317 match(eCXRegP);
4318 match(eDIRegP);
4319 match(eRegP);
4321 format %{ %}
4322 interface(REG_INTER);
4323 %}
4325 operand eRegP() %{
4326 constraint(ALLOC_IN_RC(e_reg));
4327 match(RegP);
4328 match(eAXRegP);
4329 match(eBXRegP);
4330 match(eCXRegP);
4331 match(eDIRegP);
4333 format %{ %}
4334 interface(REG_INTER);
4335 %}
4337 // On windows95, EBP is not safe to use for implicit null tests.
4338 operand eRegP_no_EBP() %{
4339 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4340 match(RegP);
4341 match(eAXRegP);
4342 match(eBXRegP);
4343 match(eCXRegP);
4344 match(eDIRegP);
4346 op_cost(100);
4347 format %{ %}
4348 interface(REG_INTER);
4349 %}
4351 operand naxRegP() %{
4352 constraint(ALLOC_IN_RC(nax_reg));
4353 match(RegP);
4354 match(eBXRegP);
4355 match(eDXRegP);
4356 match(eCXRegP);
4357 match(eSIRegP);
4358 match(eDIRegP);
4360 format %{ %}
4361 interface(REG_INTER);
4362 %}
4364 operand nabxRegP() %{
4365 constraint(ALLOC_IN_RC(nabx_reg));
4366 match(RegP);
4367 match(eCXRegP);
4368 match(eDXRegP);
4369 match(eSIRegP);
4370 match(eDIRegP);
4372 format %{ %}
4373 interface(REG_INTER);
4374 %}
4376 operand pRegP() %{
4377 constraint(ALLOC_IN_RC(p_reg));
4378 match(RegP);
4379 match(eBXRegP);
4380 match(eDXRegP);
4381 match(eSIRegP);
4382 match(eDIRegP);
4384 format %{ %}
4385 interface(REG_INTER);
4386 %}
4388 // Special Registers
4389 // Return a pointer value
4390 operand eAXRegP(eRegP reg) %{
4391 constraint(ALLOC_IN_RC(eax_reg));
4392 match(reg);
4393 format %{ "EAX" %}
4394 interface(REG_INTER);
4395 %}
4397 // Used in AtomicAdd
4398 operand eBXRegP(eRegP reg) %{
4399 constraint(ALLOC_IN_RC(ebx_reg));
4400 match(reg);
4401 format %{ "EBX" %}
4402 interface(REG_INTER);
4403 %}
4405 // Tail-call (interprocedural jump) to interpreter
4406 operand eCXRegP(eRegP reg) %{
4407 constraint(ALLOC_IN_RC(ecx_reg));
4408 match(reg);
4409 format %{ "ECX" %}
4410 interface(REG_INTER);
4411 %}
4413 operand eSIRegP(eRegP reg) %{
4414 constraint(ALLOC_IN_RC(esi_reg));
4415 match(reg);
4416 format %{ "ESI" %}
4417 interface(REG_INTER);
4418 %}
4420 // Used in rep stosw
4421 operand eDIRegP(eRegP reg) %{
4422 constraint(ALLOC_IN_RC(edi_reg));
4423 match(reg);
4424 format %{ "EDI" %}
4425 interface(REG_INTER);
4426 %}
4428 operand eBPRegP() %{
4429 constraint(ALLOC_IN_RC(ebp_reg));
4430 match(RegP);
4431 format %{ "EBP" %}
4432 interface(REG_INTER);
4433 %}
4435 operand eRegL() %{
4436 constraint(ALLOC_IN_RC(long_reg));
4437 match(RegL);
4438 match(eADXRegL);
4440 format %{ %}
4441 interface(REG_INTER);
4442 %}
4444 operand eADXRegL( eRegL reg ) %{
4445 constraint(ALLOC_IN_RC(eadx_reg));
4446 match(reg);
4448 format %{ "EDX:EAX" %}
4449 interface(REG_INTER);
4450 %}
4452 operand eBCXRegL( eRegL reg ) %{
4453 constraint(ALLOC_IN_RC(ebcx_reg));
4454 match(reg);
4456 format %{ "EBX:ECX" %}
4457 interface(REG_INTER);
4458 %}
4460 // Special case for integer high multiply
4461 operand eADXRegL_low_only() %{
4462 constraint(ALLOC_IN_RC(eadx_reg));
4463 match(RegL);
4465 format %{ "EAX" %}
4466 interface(REG_INTER);
4467 %}
4469 // Flags register, used as output of compare instructions
4470 operand eFlagsReg() %{
4471 constraint(ALLOC_IN_RC(int_flags));
4472 match(RegFlags);
4474 format %{ "EFLAGS" %}
4475 interface(REG_INTER);
4476 %}
4478 // Flags register, used as output of FLOATING POINT compare instructions
4479 operand eFlagsRegU() %{
4480 constraint(ALLOC_IN_RC(int_flags));
4481 match(RegFlags);
4483 format %{ "EFLAGS_U" %}
4484 interface(REG_INTER);
4485 %}
4487 operand eFlagsRegUCF() %{
4488 constraint(ALLOC_IN_RC(int_flags));
4489 match(RegFlags);
4490 predicate(false);
4492 format %{ "EFLAGS_U_CF" %}
4493 interface(REG_INTER);
4494 %}
4496 // Condition Code Register used by long compare
4497 operand flagsReg_long_LTGE() %{
4498 constraint(ALLOC_IN_RC(int_flags));
4499 match(RegFlags);
4500 format %{ "FLAGS_LTGE" %}
4501 interface(REG_INTER);
4502 %}
4503 operand flagsReg_long_EQNE() %{
4504 constraint(ALLOC_IN_RC(int_flags));
4505 match(RegFlags);
4506 format %{ "FLAGS_EQNE" %}
4507 interface(REG_INTER);
4508 %}
4509 operand flagsReg_long_LEGT() %{
4510 constraint(ALLOC_IN_RC(int_flags));
4511 match(RegFlags);
4512 format %{ "FLAGS_LEGT" %}
4513 interface(REG_INTER);
4514 %}
4516 // Float register operands
4517 operand regDPR() %{
4518 predicate( UseSSE < 2 );
4519 constraint(ALLOC_IN_RC(dbl_reg));
4520 match(RegD);
4521 match(regDPR1);
4522 match(regDPR2);
4523 format %{ %}
4524 interface(REG_INTER);
4525 %}
4527 operand regDPR1(regDPR reg) %{
4528 predicate( UseSSE < 2 );
4529 constraint(ALLOC_IN_RC(dbl_reg0));
4530 match(reg);
4531 format %{ "FPR1" %}
4532 interface(REG_INTER);
4533 %}
4535 operand regDPR2(regDPR reg) %{
4536 predicate( UseSSE < 2 );
4537 constraint(ALLOC_IN_RC(dbl_reg1));
4538 match(reg);
4539 format %{ "FPR2" %}
4540 interface(REG_INTER);
4541 %}
4543 operand regnotDPR1(regDPR reg) %{
4544 predicate( UseSSE < 2 );
4545 constraint(ALLOC_IN_RC(dbl_notreg0));
4546 match(reg);
4547 format %{ %}
4548 interface(REG_INTER);
4549 %}
4551 // XMM Double register operands
4552 operand regD() %{
4553 predicate( UseSSE>=2 );
4554 constraint(ALLOC_IN_RC(xdb_reg));
4555 match(RegD);
4556 match(regD6);
4557 match(regD7);
4558 format %{ %}
4559 interface(REG_INTER);
4560 %}
4562 // XMM6 double register operands
4563 operand regD6(regD reg) %{
4564 predicate( UseSSE>=2 );
4565 constraint(ALLOC_IN_RC(xdb_reg6));
4566 match(reg);
4567 format %{ "XMM6" %}
4568 interface(REG_INTER);
4569 %}
4571 // XMM7 double register operands
4572 operand regD7(regD reg) %{
4573 predicate( UseSSE>=2 );
4574 constraint(ALLOC_IN_RC(xdb_reg7));
4575 match(reg);
4576 format %{ "XMM7" %}
4577 interface(REG_INTER);
4578 %}
4580 // Float register operands
4581 operand regFPR() %{
4582 predicate( UseSSE < 2 );
4583 constraint(ALLOC_IN_RC(flt_reg));
4584 match(RegF);
4585 match(regFPR1);
4586 format %{ %}
4587 interface(REG_INTER);
4588 %}
4590 // Float register operands
4591 operand regFPR1(regFPR reg) %{
4592 predicate( UseSSE < 2 );
4593 constraint(ALLOC_IN_RC(flt_reg0));
4594 match(reg);
4595 format %{ "FPR1" %}
4596 interface(REG_INTER);
4597 %}
4599 // XMM register operands
4600 operand regF() %{
4601 predicate( UseSSE>=1 );
4602 constraint(ALLOC_IN_RC(xmm_reg));
4603 match(RegF);
4604 format %{ %}
4605 interface(REG_INTER);
4606 %}
4609 //----------Memory Operands----------------------------------------------------
4610 // Direct Memory Operand
4611 operand direct(immP addr) %{
4612 match(addr);
4614 format %{ "[$addr]" %}
4615 interface(MEMORY_INTER) %{
4616 base(0xFFFFFFFF);
4617 index(0x4);
4618 scale(0x0);
4619 disp($addr);
4620 %}
4621 %}
4623 // Indirect Memory Operand
4624 operand indirect(eRegP reg) %{
4625 constraint(ALLOC_IN_RC(e_reg));
4626 match(reg);
4628 format %{ "[$reg]" %}
4629 interface(MEMORY_INTER) %{
4630 base($reg);
4631 index(0x4);
4632 scale(0x0);
4633 disp(0x0);
4634 %}
4635 %}
4637 // Indirect Memory Plus Short Offset Operand
4638 operand indOffset8(eRegP reg, immI8 off) %{
4639 match(AddP reg off);
4641 format %{ "[$reg + $off]" %}
4642 interface(MEMORY_INTER) %{
4643 base($reg);
4644 index(0x4);
4645 scale(0x0);
4646 disp($off);
4647 %}
4648 %}
4650 // Indirect Memory Plus Long Offset Operand
4651 operand indOffset32(eRegP reg, immI off) %{
4652 match(AddP reg off);
4654 format %{ "[$reg + $off]" %}
4655 interface(MEMORY_INTER) %{
4656 base($reg);
4657 index(0x4);
4658 scale(0x0);
4659 disp($off);
4660 %}
4661 %}
4663 // Indirect Memory Plus Long Offset Operand
4664 operand indOffset32X(eRegI reg, immP off) %{
4665 match(AddP off reg);
4667 format %{ "[$reg + $off]" %}
4668 interface(MEMORY_INTER) %{
4669 base($reg);
4670 index(0x4);
4671 scale(0x0);
4672 disp($off);
4673 %}
4674 %}
4676 // Indirect Memory Plus Index Register Plus Offset Operand
4677 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
4678 match(AddP (AddP reg ireg) off);
4680 op_cost(10);
4681 format %{"[$reg + $off + $ireg]" %}
4682 interface(MEMORY_INTER) %{
4683 base($reg);
4684 index($ireg);
4685 scale(0x0);
4686 disp($off);
4687 %}
4688 %}
4690 // Indirect Memory Plus Index Register Plus Offset Operand
4691 operand indIndex(eRegP reg, eRegI ireg) %{
4692 match(AddP reg ireg);
4694 op_cost(10);
4695 format %{"[$reg + $ireg]" %}
4696 interface(MEMORY_INTER) %{
4697 base($reg);
4698 index($ireg);
4699 scale(0x0);
4700 disp(0x0);
4701 %}
4702 %}
4704 // // -------------------------------------------------------------------------
4705 // // 486 architecture doesn't support "scale * index + offset" with out a base
4706 // // -------------------------------------------------------------------------
4707 // // Scaled Memory Operands
4708 // // Indirect Memory Times Scale Plus Offset Operand
4709 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
4710 // match(AddP off (LShiftI ireg scale));
4711 //
4712 // op_cost(10);
4713 // format %{"[$off + $ireg << $scale]" %}
4714 // interface(MEMORY_INTER) %{
4715 // base(0x4);
4716 // index($ireg);
4717 // scale($scale);
4718 // disp($off);
4719 // %}
4720 // %}
4722 // Indirect Memory Times Scale Plus Index Register
4723 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
4724 match(AddP reg (LShiftI ireg scale));
4726 op_cost(10);
4727 format %{"[$reg + $ireg << $scale]" %}
4728 interface(MEMORY_INTER) %{
4729 base($reg);
4730 index($ireg);
4731 scale($scale);
4732 disp(0x0);
4733 %}
4734 %}
4736 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4737 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
4738 match(AddP (AddP reg (LShiftI ireg scale)) off);
4740 op_cost(10);
4741 format %{"[$reg + $off + $ireg << $scale]" %}
4742 interface(MEMORY_INTER) %{
4743 base($reg);
4744 index($ireg);
4745 scale($scale);
4746 disp($off);
4747 %}
4748 %}
4750 //----------Load Long Memory Operands------------------------------------------
4751 // The load-long idiom will use it's address expression again after loading
4752 // the first word of the long. If the load-long destination overlaps with
4753 // registers used in the addressing expression, the 2nd half will be loaded
4754 // from a clobbered address. Fix this by requiring that load-long use
4755 // address registers that do not overlap with the load-long target.
4757 // load-long support
4758 operand load_long_RegP() %{
4759 constraint(ALLOC_IN_RC(esi_reg));
4760 match(RegP);
4761 match(eSIRegP);
4762 op_cost(100);
4763 format %{ %}
4764 interface(REG_INTER);
4765 %}
4767 // Indirect Memory Operand Long
4768 operand load_long_indirect(load_long_RegP reg) %{
4769 constraint(ALLOC_IN_RC(esi_reg));
4770 match(reg);
4772 format %{ "[$reg]" %}
4773 interface(MEMORY_INTER) %{
4774 base($reg);
4775 index(0x4);
4776 scale(0x0);
4777 disp(0x0);
4778 %}
4779 %}
4781 // Indirect Memory Plus Long Offset Operand
4782 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4783 match(AddP reg off);
4785 format %{ "[$reg + $off]" %}
4786 interface(MEMORY_INTER) %{
4787 base($reg);
4788 index(0x4);
4789 scale(0x0);
4790 disp($off);
4791 %}
4792 %}
4794 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4797 //----------Special Memory Operands--------------------------------------------
4798 // Stack Slot Operand - This operand is used for loading and storing temporary
4799 // values on the stack where a match requires a value to
4800 // flow through memory.
4801 operand stackSlotP(sRegP reg) %{
4802 constraint(ALLOC_IN_RC(stack_slots));
4803 // No match rule because this operand is only generated in matching
4804 format %{ "[$reg]" %}
4805 interface(MEMORY_INTER) %{
4806 base(0x4); // ESP
4807 index(0x4); // No Index
4808 scale(0x0); // No Scale
4809 disp($reg); // Stack Offset
4810 %}
4811 %}
4813 operand stackSlotI(sRegI reg) %{
4814 constraint(ALLOC_IN_RC(stack_slots));
4815 // No match rule because this operand is only generated in matching
4816 format %{ "[$reg]" %}
4817 interface(MEMORY_INTER) %{
4818 base(0x4); // ESP
4819 index(0x4); // No Index
4820 scale(0x0); // No Scale
4821 disp($reg); // Stack Offset
4822 %}
4823 %}
4825 operand stackSlotF(sRegF reg) %{
4826 constraint(ALLOC_IN_RC(stack_slots));
4827 // No match rule because this operand is only generated in matching
4828 format %{ "[$reg]" %}
4829 interface(MEMORY_INTER) %{
4830 base(0x4); // ESP
4831 index(0x4); // No Index
4832 scale(0x0); // No Scale
4833 disp($reg); // Stack Offset
4834 %}
4835 %}
4837 operand stackSlotD(sRegD reg) %{
4838 constraint(ALLOC_IN_RC(stack_slots));
4839 // No match rule because this operand is only generated in matching
4840 format %{ "[$reg]" %}
4841 interface(MEMORY_INTER) %{
4842 base(0x4); // ESP
4843 index(0x4); // No Index
4844 scale(0x0); // No Scale
4845 disp($reg); // Stack Offset
4846 %}
4847 %}
4849 operand stackSlotL(sRegL reg) %{
4850 constraint(ALLOC_IN_RC(stack_slots));
4851 // No match rule because this operand is only generated in matching
4852 format %{ "[$reg]" %}
4853 interface(MEMORY_INTER) %{
4854 base(0x4); // ESP
4855 index(0x4); // No Index
4856 scale(0x0); // No Scale
4857 disp($reg); // Stack Offset
4858 %}
4859 %}
4861 //----------Memory Operands - Win95 Implicit Null Variants----------------
4862 // Indirect Memory Operand
4863 operand indirect_win95_safe(eRegP_no_EBP reg)
4864 %{
4865 constraint(ALLOC_IN_RC(e_reg));
4866 match(reg);
4868 op_cost(100);
4869 format %{ "[$reg]" %}
4870 interface(MEMORY_INTER) %{
4871 base($reg);
4872 index(0x4);
4873 scale(0x0);
4874 disp(0x0);
4875 %}
4876 %}
4878 // Indirect Memory Plus Short Offset Operand
4879 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4880 %{
4881 match(AddP reg off);
4883 op_cost(100);
4884 format %{ "[$reg + $off]" %}
4885 interface(MEMORY_INTER) %{
4886 base($reg);
4887 index(0x4);
4888 scale(0x0);
4889 disp($off);
4890 %}
4891 %}
4893 // Indirect Memory Plus Long Offset Operand
4894 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4895 %{
4896 match(AddP reg off);
4898 op_cost(100);
4899 format %{ "[$reg + $off]" %}
4900 interface(MEMORY_INTER) %{
4901 base($reg);
4902 index(0x4);
4903 scale(0x0);
4904 disp($off);
4905 %}
4906 %}
4908 // Indirect Memory Plus Index Register Plus Offset Operand
4909 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
4910 %{
4911 match(AddP (AddP reg ireg) off);
4913 op_cost(100);
4914 format %{"[$reg + $off + $ireg]" %}
4915 interface(MEMORY_INTER) %{
4916 base($reg);
4917 index($ireg);
4918 scale(0x0);
4919 disp($off);
4920 %}
4921 %}
4923 // Indirect Memory Times Scale Plus Index Register
4924 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
4925 %{
4926 match(AddP reg (LShiftI ireg scale));
4928 op_cost(100);
4929 format %{"[$reg + $ireg << $scale]" %}
4930 interface(MEMORY_INTER) %{
4931 base($reg);
4932 index($ireg);
4933 scale($scale);
4934 disp(0x0);
4935 %}
4936 %}
4938 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4939 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
4940 %{
4941 match(AddP (AddP reg (LShiftI ireg scale)) off);
4943 op_cost(100);
4944 format %{"[$reg + $off + $ireg << $scale]" %}
4945 interface(MEMORY_INTER) %{
4946 base($reg);
4947 index($ireg);
4948 scale($scale);
4949 disp($off);
4950 %}
4951 %}
4953 //----------Conditional Branch Operands----------------------------------------
4954 // Comparison Op - This is the operation of the comparison, and is limited to
4955 // the following set of codes:
4956 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4957 //
4958 // Other attributes of the comparison, such as unsignedness, are specified
4959 // by the comparison instruction that sets a condition code flags register.
4960 // That result is represented by a flags operand whose subtype is appropriate
4961 // to the unsignedness (etc.) of the comparison.
4962 //
4963 // Later, the instruction which matches both the Comparison Op (a Bool) and
4964 // the flags (produced by the Cmp) specifies the coding of the comparison op
4965 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4967 // Comparision Code
4968 operand cmpOp() %{
4969 match(Bool);
4971 format %{ "" %}
4972 interface(COND_INTER) %{
4973 equal(0x4, "e");
4974 not_equal(0x5, "ne");
4975 less(0xC, "l");
4976 greater_equal(0xD, "ge");
4977 less_equal(0xE, "le");
4978 greater(0xF, "g");
4979 %}
4980 %}
4982 // Comparison Code, unsigned compare. Used by FP also, with
4983 // C2 (unordered) turned into GT or LT already. The other bits
4984 // C0 and C3 are turned into Carry & Zero flags.
4985 operand cmpOpU() %{
4986 match(Bool);
4988 format %{ "" %}
4989 interface(COND_INTER) %{
4990 equal(0x4, "e");
4991 not_equal(0x5, "ne");
4992 less(0x2, "b");
4993 greater_equal(0x3, "nb");
4994 less_equal(0x6, "be");
4995 greater(0x7, "nbe");
4996 %}
4997 %}
4999 // Floating comparisons that don't require any fixup for the unordered case
5000 operand cmpOpUCF() %{
5001 match(Bool);
5002 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5003 n->as_Bool()->_test._test == BoolTest::ge ||
5004 n->as_Bool()->_test._test == BoolTest::le ||
5005 n->as_Bool()->_test._test == BoolTest::gt);
5006 format %{ "" %}
5007 interface(COND_INTER) %{
5008 equal(0x4, "e");
5009 not_equal(0x5, "ne");
5010 less(0x2, "b");
5011 greater_equal(0x3, "nb");
5012 less_equal(0x6, "be");
5013 greater(0x7, "nbe");
5014 %}
5015 %}
5018 // Floating comparisons that can be fixed up with extra conditional jumps
5019 operand cmpOpUCF2() %{
5020 match(Bool);
5021 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5022 n->as_Bool()->_test._test == BoolTest::eq);
5023 format %{ "" %}
5024 interface(COND_INTER) %{
5025 equal(0x4, "e");
5026 not_equal(0x5, "ne");
5027 less(0x2, "b");
5028 greater_equal(0x3, "nb");
5029 less_equal(0x6, "be");
5030 greater(0x7, "nbe");
5031 %}
5032 %}
5034 // Comparison Code for FP conditional move
5035 operand cmpOp_fcmov() %{
5036 match(Bool);
5038 format %{ "" %}
5039 interface(COND_INTER) %{
5040 equal (0x0C8);
5041 not_equal (0x1C8);
5042 less (0x0C0);
5043 greater_equal(0x1C0);
5044 less_equal (0x0D0);
5045 greater (0x1D0);
5046 %}
5047 %}
5049 // Comparision Code used in long compares
5050 operand cmpOp_commute() %{
5051 match(Bool);
5053 format %{ "" %}
5054 interface(COND_INTER) %{
5055 equal(0x4, "e");
5056 not_equal(0x5, "ne");
5057 less(0xF, "g");
5058 greater_equal(0xE, "le");
5059 less_equal(0xD, "ge");
5060 greater(0xC, "l");
5061 %}
5062 %}
5064 //----------OPERAND CLASSES----------------------------------------------------
5065 // Operand Classes are groups of operands that are used as to simplify
5066 // instruction definitions by not requiring the AD writer to specify separate
5067 // instructions for every form of operand when the instruction accepts
5068 // multiple operand types with the same basic encoding and format. The classic
5069 // case of this is memory operands.
5071 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5072 indIndex, indIndexScale, indIndexScaleOffset);
5074 // Long memory operations are encoded in 2 instructions and a +4 offset.
5075 // This means some kind of offset is always required and you cannot use
5076 // an oop as the offset (done when working on static globals).
5077 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5078 indIndex, indIndexScale, indIndexScaleOffset);
5081 //----------PIPELINE-----------------------------------------------------------
5082 // Rules which define the behavior of the target architectures pipeline.
5083 pipeline %{
5085 //----------ATTRIBUTES---------------------------------------------------------
5086 attributes %{
5087 variable_size_instructions; // Fixed size instructions
5088 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5089 instruction_unit_size = 1; // An instruction is 1 bytes long
5090 instruction_fetch_unit_size = 16; // The processor fetches one line
5091 instruction_fetch_units = 1; // of 16 bytes
5093 // List of nop instructions
5094 nops( MachNop );
5095 %}
5097 //----------RESOURCES----------------------------------------------------------
5098 // Resources are the functional units available to the machine
5100 // Generic P2/P3 pipeline
5101 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5102 // 3 instructions decoded per cycle.
5103 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5104 // 2 ALU op, only ALU0 handles mul/div instructions.
5105 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5106 MS0, MS1, MEM = MS0 | MS1,
5107 BR, FPU,
5108 ALU0, ALU1, ALU = ALU0 | ALU1 );
5110 //----------PIPELINE DESCRIPTION-----------------------------------------------
5111 // Pipeline Description specifies the stages in the machine's pipeline
5113 // Generic P2/P3 pipeline
5114 pipe_desc(S0, S1, S2, S3, S4, S5);
5116 //----------PIPELINE CLASSES---------------------------------------------------
5117 // Pipeline Classes describe the stages in which input and output are
5118 // referenced by the hardware pipeline.
5120 // Naming convention: ialu or fpu
5121 // Then: _reg
5122 // Then: _reg if there is a 2nd register
5123 // Then: _long if it's a pair of instructions implementing a long
5124 // Then: _fat if it requires the big decoder
5125 // Or: _mem if it requires the big decoder and a memory unit.
5127 // Integer ALU reg operation
5128 pipe_class ialu_reg(eRegI dst) %{
5129 single_instruction;
5130 dst : S4(write);
5131 dst : S3(read);
5132 DECODE : S0; // any decoder
5133 ALU : S3; // any alu
5134 %}
5136 // Long ALU reg operation
5137 pipe_class ialu_reg_long(eRegL dst) %{
5138 instruction_count(2);
5139 dst : S4(write);
5140 dst : S3(read);
5141 DECODE : S0(2); // any 2 decoders
5142 ALU : S3(2); // both alus
5143 %}
5145 // Integer ALU reg operation using big decoder
5146 pipe_class ialu_reg_fat(eRegI dst) %{
5147 single_instruction;
5148 dst : S4(write);
5149 dst : S3(read);
5150 D0 : S0; // big decoder only
5151 ALU : S3; // any alu
5152 %}
5154 // Long ALU reg operation using big decoder
5155 pipe_class ialu_reg_long_fat(eRegL dst) %{
5156 instruction_count(2);
5157 dst : S4(write);
5158 dst : S3(read);
5159 D0 : S0(2); // big decoder only; twice
5160 ALU : S3(2); // any 2 alus
5161 %}
5163 // Integer ALU reg-reg operation
5164 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5165 single_instruction;
5166 dst : S4(write);
5167 src : S3(read);
5168 DECODE : S0; // any decoder
5169 ALU : S3; // any alu
5170 %}
5172 // Long ALU reg-reg operation
5173 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5174 instruction_count(2);
5175 dst : S4(write);
5176 src : S3(read);
5177 DECODE : S0(2); // any 2 decoders
5178 ALU : S3(2); // both alus
5179 %}
5181 // Integer ALU reg-reg operation
5182 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5183 single_instruction;
5184 dst : S4(write);
5185 src : S3(read);
5186 D0 : S0; // big decoder only
5187 ALU : S3; // any alu
5188 %}
5190 // Long ALU reg-reg operation
5191 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5192 instruction_count(2);
5193 dst : S4(write);
5194 src : S3(read);
5195 D0 : S0(2); // big decoder only; twice
5196 ALU : S3(2); // both alus
5197 %}
5199 // Integer ALU reg-mem operation
5200 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5201 single_instruction;
5202 dst : S5(write);
5203 mem : S3(read);
5204 D0 : S0; // big decoder only
5205 ALU : S4; // any alu
5206 MEM : S3; // any mem
5207 %}
5209 // Long ALU reg-mem operation
5210 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5211 instruction_count(2);
5212 dst : S5(write);
5213 mem : S3(read);
5214 D0 : S0(2); // big decoder only; twice
5215 ALU : S4(2); // any 2 alus
5216 MEM : S3(2); // both mems
5217 %}
5219 // Integer mem operation (prefetch)
5220 pipe_class ialu_mem(memory mem)
5221 %{
5222 single_instruction;
5223 mem : S3(read);
5224 D0 : S0; // big decoder only
5225 MEM : S3; // any mem
5226 %}
5228 // Integer Store to Memory
5229 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5230 single_instruction;
5231 mem : S3(read);
5232 src : S5(read);
5233 D0 : S0; // big decoder only
5234 ALU : S4; // any alu
5235 MEM : S3;
5236 %}
5238 // Long Store to Memory
5239 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5240 instruction_count(2);
5241 mem : S3(read);
5242 src : S5(read);
5243 D0 : S0(2); // big decoder only; twice
5244 ALU : S4(2); // any 2 alus
5245 MEM : S3(2); // Both mems
5246 %}
5248 // Integer Store to Memory
5249 pipe_class ialu_mem_imm(memory mem) %{
5250 single_instruction;
5251 mem : S3(read);
5252 D0 : S0; // big decoder only
5253 ALU : S4; // any alu
5254 MEM : S3;
5255 %}
5257 // Integer ALU0 reg-reg operation
5258 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5259 single_instruction;
5260 dst : S4(write);
5261 src : S3(read);
5262 D0 : S0; // Big decoder only
5263 ALU0 : S3; // only alu0
5264 %}
5266 // Integer ALU0 reg-mem operation
5267 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5268 single_instruction;
5269 dst : S5(write);
5270 mem : S3(read);
5271 D0 : S0; // big decoder only
5272 ALU0 : S4; // ALU0 only
5273 MEM : S3; // any mem
5274 %}
5276 // Integer ALU reg-reg operation
5277 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5278 single_instruction;
5279 cr : S4(write);
5280 src1 : S3(read);
5281 src2 : S3(read);
5282 DECODE : S0; // any decoder
5283 ALU : S3; // any alu
5284 %}
5286 // Integer ALU reg-imm operation
5287 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5288 single_instruction;
5289 cr : S4(write);
5290 src1 : S3(read);
5291 DECODE : S0; // any decoder
5292 ALU : S3; // any alu
5293 %}
5295 // Integer ALU reg-mem operation
5296 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5297 single_instruction;
5298 cr : S4(write);
5299 src1 : S3(read);
5300 src2 : S3(read);
5301 D0 : S0; // big decoder only
5302 ALU : S4; // any alu
5303 MEM : S3;
5304 %}
5306 // Conditional move reg-reg
5307 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5308 instruction_count(4);
5309 y : S4(read);
5310 q : S3(read);
5311 p : S3(read);
5312 DECODE : S0(4); // any decoder
5313 %}
5315 // Conditional move reg-reg
5316 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5317 single_instruction;
5318 dst : S4(write);
5319 src : S3(read);
5320 cr : S3(read);
5321 DECODE : S0; // any decoder
5322 %}
5324 // Conditional move reg-mem
5325 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5326 single_instruction;
5327 dst : S4(write);
5328 src : S3(read);
5329 cr : S3(read);
5330 DECODE : S0; // any decoder
5331 MEM : S3;
5332 %}
5334 // Conditional move reg-reg long
5335 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5336 single_instruction;
5337 dst : S4(write);
5338 src : S3(read);
5339 cr : S3(read);
5340 DECODE : S0(2); // any 2 decoders
5341 %}
5343 // Conditional move double reg-reg
5344 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5345 single_instruction;
5346 dst : S4(write);
5347 src : S3(read);
5348 cr : S3(read);
5349 DECODE : S0; // any decoder
5350 %}
5352 // Float reg-reg operation
5353 pipe_class fpu_reg(regDPR dst) %{
5354 instruction_count(2);
5355 dst : S3(read);
5356 DECODE : S0(2); // any 2 decoders
5357 FPU : S3;
5358 %}
5360 // Float reg-reg operation
5361 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5362 instruction_count(2);
5363 dst : S4(write);
5364 src : S3(read);
5365 DECODE : S0(2); // any 2 decoders
5366 FPU : S3;
5367 %}
5369 // Float reg-reg operation
5370 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5371 instruction_count(3);
5372 dst : S4(write);
5373 src1 : S3(read);
5374 src2 : S3(read);
5375 DECODE : S0(3); // any 3 decoders
5376 FPU : S3(2);
5377 %}
5379 // Float reg-reg operation
5380 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5381 instruction_count(4);
5382 dst : S4(write);
5383 src1 : S3(read);
5384 src2 : S3(read);
5385 src3 : S3(read);
5386 DECODE : S0(4); // any 3 decoders
5387 FPU : S3(2);
5388 %}
5390 // Float reg-reg operation
5391 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5392 instruction_count(4);
5393 dst : S4(write);
5394 src1 : S3(read);
5395 src2 : S3(read);
5396 src3 : S3(read);
5397 DECODE : S1(3); // any 3 decoders
5398 D0 : S0; // Big decoder only
5399 FPU : S3(2);
5400 MEM : S3;
5401 %}
5403 // Float reg-mem operation
5404 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5405 instruction_count(2);
5406 dst : S5(write);
5407 mem : S3(read);
5408 D0 : S0; // big decoder only
5409 DECODE : S1; // any decoder for FPU POP
5410 FPU : S4;
5411 MEM : S3; // any mem
5412 %}
5414 // Float reg-mem operation
5415 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5416 instruction_count(3);
5417 dst : S5(write);
5418 src1 : S3(read);
5419 mem : S3(read);
5420 D0 : S0; // big decoder only
5421 DECODE : S1(2); // any decoder for FPU POP
5422 FPU : S4;
5423 MEM : S3; // any mem
5424 %}
5426 // Float mem-reg operation
5427 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5428 instruction_count(2);
5429 src : S5(read);
5430 mem : S3(read);
5431 DECODE : S0; // any decoder for FPU PUSH
5432 D0 : S1; // big decoder only
5433 FPU : S4;
5434 MEM : S3; // any mem
5435 %}
5437 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5438 instruction_count(3);
5439 src1 : S3(read);
5440 src2 : S3(read);
5441 mem : S3(read);
5442 DECODE : S0(2); // any decoder for FPU PUSH
5443 D0 : S1; // big decoder only
5444 FPU : S4;
5445 MEM : S3; // any mem
5446 %}
5448 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5449 instruction_count(3);
5450 src1 : S3(read);
5451 src2 : S3(read);
5452 mem : S4(read);
5453 DECODE : S0; // any decoder for FPU PUSH
5454 D0 : S0(2); // big decoder only
5455 FPU : S4;
5456 MEM : S3(2); // any mem
5457 %}
5459 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5460 instruction_count(2);
5461 src1 : S3(read);
5462 dst : S4(read);
5463 D0 : S0(2); // big decoder only
5464 MEM : S3(2); // any mem
5465 %}
5467 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5468 instruction_count(3);
5469 src1 : S3(read);
5470 src2 : S3(read);
5471 dst : S4(read);
5472 D0 : S0(3); // big decoder only
5473 FPU : S4;
5474 MEM : S3(3); // any mem
5475 %}
5477 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5478 instruction_count(3);
5479 src1 : S4(read);
5480 mem : S4(read);
5481 DECODE : S0; // any decoder for FPU PUSH
5482 D0 : S0(2); // big decoder only
5483 FPU : S4;
5484 MEM : S3(2); // any mem
5485 %}
5487 // Float load constant
5488 pipe_class fpu_reg_con(regDPR dst) %{
5489 instruction_count(2);
5490 dst : S5(write);
5491 D0 : S0; // big decoder only for the load
5492 DECODE : S1; // any decoder for FPU POP
5493 FPU : S4;
5494 MEM : S3; // any mem
5495 %}
5497 // Float load constant
5498 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5499 instruction_count(3);
5500 dst : S5(write);
5501 src : S3(read);
5502 D0 : S0; // big decoder only for the load
5503 DECODE : S1(2); // any decoder for FPU POP
5504 FPU : S4;
5505 MEM : S3; // any mem
5506 %}
5508 // UnConditional branch
5509 pipe_class pipe_jmp( label labl ) %{
5510 single_instruction;
5511 BR : S3;
5512 %}
5514 // Conditional branch
5515 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5516 single_instruction;
5517 cr : S1(read);
5518 BR : S3;
5519 %}
5521 // Allocation idiom
5522 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5523 instruction_count(1); force_serialization;
5524 fixed_latency(6);
5525 heap_ptr : S3(read);
5526 DECODE : S0(3);
5527 D0 : S2;
5528 MEM : S3;
5529 ALU : S3(2);
5530 dst : S5(write);
5531 BR : S5;
5532 %}
5534 // Generic big/slow expanded idiom
5535 pipe_class pipe_slow( ) %{
5536 instruction_count(10); multiple_bundles; force_serialization;
5537 fixed_latency(100);
5538 D0 : S0(2);
5539 MEM : S3(2);
5540 %}
5542 // The real do-nothing guy
5543 pipe_class empty( ) %{
5544 instruction_count(0);
5545 %}
5547 // Define the class for the Nop node
5548 define %{
5549 MachNop = empty;
5550 %}
5552 %}
5554 //----------INSTRUCTIONS-------------------------------------------------------
5555 //
5556 // match -- States which machine-independent subtree may be replaced
5557 // by this instruction.
5558 // ins_cost -- The estimated cost of this instruction is used by instruction
5559 // selection to identify a minimum cost tree of machine
5560 // instructions that matches a tree of machine-independent
5561 // instructions.
5562 // format -- A string providing the disassembly for this instruction.
5563 // The value of an instruction's operand may be inserted
5564 // by referring to it with a '$' prefix.
5565 // opcode -- Three instruction opcodes may be provided. These are referred
5566 // to within an encode class as $primary, $secondary, and $tertiary
5567 // respectively. The primary opcode is commonly used to
5568 // indicate the type of machine instruction, while secondary
5569 // and tertiary are often used for prefix options or addressing
5570 // modes.
5571 // ins_encode -- A list of encode classes with parameters. The encode class
5572 // name must have been defined in an 'enc_class' specification
5573 // in the encode section of the architecture description.
5575 //----------BSWAP-Instruction--------------------------------------------------
5576 instruct bytes_reverse_int(eRegI dst) %{
5577 match(Set dst (ReverseBytesI dst));
5579 format %{ "BSWAP $dst" %}
5580 opcode(0x0F, 0xC8);
5581 ins_encode( OpcP, OpcSReg(dst) );
5582 ins_pipe( ialu_reg );
5583 %}
5585 instruct bytes_reverse_long(eRegL dst) %{
5586 match(Set dst (ReverseBytesL dst));
5588 format %{ "BSWAP $dst.lo\n\t"
5589 "BSWAP $dst.hi\n\t"
5590 "XCHG $dst.lo $dst.hi" %}
5592 ins_cost(125);
5593 ins_encode( bswap_long_bytes(dst) );
5594 ins_pipe( ialu_reg_reg);
5595 %}
5597 instruct bytes_reverse_unsigned_short(eRegI dst) %{
5598 match(Set dst (ReverseBytesUS dst));
5600 format %{ "BSWAP $dst\n\t"
5601 "SHR $dst,16\n\t" %}
5602 ins_encode %{
5603 __ bswapl($dst$$Register);
5604 __ shrl($dst$$Register, 16);
5605 %}
5606 ins_pipe( ialu_reg );
5607 %}
5609 instruct bytes_reverse_short(eRegI dst) %{
5610 match(Set dst (ReverseBytesS dst));
5612 format %{ "BSWAP $dst\n\t"
5613 "SAR $dst,16\n\t" %}
5614 ins_encode %{
5615 __ bswapl($dst$$Register);
5616 __ sarl($dst$$Register, 16);
5617 %}
5618 ins_pipe( ialu_reg );
5619 %}
5622 //---------- Zeros Count Instructions ------------------------------------------
5624 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5625 predicate(UseCountLeadingZerosInstruction);
5626 match(Set dst (CountLeadingZerosI src));
5627 effect(KILL cr);
5629 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5630 ins_encode %{
5631 __ lzcntl($dst$$Register, $src$$Register);
5632 %}
5633 ins_pipe(ialu_reg);
5634 %}
5636 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
5637 predicate(!UseCountLeadingZerosInstruction);
5638 match(Set dst (CountLeadingZerosI src));
5639 effect(KILL cr);
5641 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5642 "JNZ skip\n\t"
5643 "MOV $dst, -1\n"
5644 "skip:\n\t"
5645 "NEG $dst\n\t"
5646 "ADD $dst, 31" %}
5647 ins_encode %{
5648 Register Rdst = $dst$$Register;
5649 Register Rsrc = $src$$Register;
5650 Label skip;
5651 __ bsrl(Rdst, Rsrc);
5652 __ jccb(Assembler::notZero, skip);
5653 __ movl(Rdst, -1);
5654 __ bind(skip);
5655 __ negl(Rdst);
5656 __ addl(Rdst, BitsPerInt - 1);
5657 %}
5658 ins_pipe(ialu_reg);
5659 %}
5661 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5662 predicate(UseCountLeadingZerosInstruction);
5663 match(Set dst (CountLeadingZerosL src));
5664 effect(TEMP dst, KILL cr);
5666 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5667 "JNC done\n\t"
5668 "LZCNT $dst, $src.lo\n\t"
5669 "ADD $dst, 32\n"
5670 "done:" %}
5671 ins_encode %{
5672 Register Rdst = $dst$$Register;
5673 Register Rsrc = $src$$Register;
5674 Label done;
5675 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5676 __ jccb(Assembler::carryClear, done);
5677 __ lzcntl(Rdst, Rsrc);
5678 __ addl(Rdst, BitsPerInt);
5679 __ bind(done);
5680 %}
5681 ins_pipe(ialu_reg);
5682 %}
5684 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
5685 predicate(!UseCountLeadingZerosInstruction);
5686 match(Set dst (CountLeadingZerosL src));
5687 effect(TEMP dst, KILL cr);
5689 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5690 "JZ msw_is_zero\n\t"
5691 "ADD $dst, 32\n\t"
5692 "JMP not_zero\n"
5693 "msw_is_zero:\n\t"
5694 "BSR $dst, $src.lo\n\t"
5695 "JNZ not_zero\n\t"
5696 "MOV $dst, -1\n"
5697 "not_zero:\n\t"
5698 "NEG $dst\n\t"
5699 "ADD $dst, 63\n" %}
5700 ins_encode %{
5701 Register Rdst = $dst$$Register;
5702 Register Rsrc = $src$$Register;
5703 Label msw_is_zero;
5704 Label not_zero;
5705 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5706 __ jccb(Assembler::zero, msw_is_zero);
5707 __ addl(Rdst, BitsPerInt);
5708 __ jmpb(not_zero);
5709 __ bind(msw_is_zero);
5710 __ bsrl(Rdst, Rsrc);
5711 __ jccb(Assembler::notZero, not_zero);
5712 __ movl(Rdst, -1);
5713 __ bind(not_zero);
5714 __ negl(Rdst);
5715 __ addl(Rdst, BitsPerLong - 1);
5716 %}
5717 ins_pipe(ialu_reg);
5718 %}
5720 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5721 match(Set dst (CountTrailingZerosI src));
5722 effect(KILL cr);
5724 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5725 "JNZ done\n\t"
5726 "MOV $dst, 32\n"
5727 "done:" %}
5728 ins_encode %{
5729 Register Rdst = $dst$$Register;
5730 Label done;
5731 __ bsfl(Rdst, $src$$Register);
5732 __ jccb(Assembler::notZero, done);
5733 __ movl(Rdst, BitsPerInt);
5734 __ bind(done);
5735 %}
5736 ins_pipe(ialu_reg);
5737 %}
5739 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5740 match(Set dst (CountTrailingZerosL src));
5741 effect(TEMP dst, KILL cr);
5743 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5744 "JNZ done\n\t"
5745 "BSF $dst, $src.hi\n\t"
5746 "JNZ msw_not_zero\n\t"
5747 "MOV $dst, 32\n"
5748 "msw_not_zero:\n\t"
5749 "ADD $dst, 32\n"
5750 "done:" %}
5751 ins_encode %{
5752 Register Rdst = $dst$$Register;
5753 Register Rsrc = $src$$Register;
5754 Label msw_not_zero;
5755 Label done;
5756 __ bsfl(Rdst, Rsrc);
5757 __ jccb(Assembler::notZero, done);
5758 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5759 __ jccb(Assembler::notZero, msw_not_zero);
5760 __ movl(Rdst, BitsPerInt);
5761 __ bind(msw_not_zero);
5762 __ addl(Rdst, BitsPerInt);
5763 __ bind(done);
5764 %}
5765 ins_pipe(ialu_reg);
5766 %}
5769 //---------- Population Count Instructions -------------------------------------
5771 instruct popCountI(eRegI dst, eRegI src) %{
5772 predicate(UsePopCountInstruction);
5773 match(Set dst (PopCountI src));
5775 format %{ "POPCNT $dst, $src" %}
5776 ins_encode %{
5777 __ popcntl($dst$$Register, $src$$Register);
5778 %}
5779 ins_pipe(ialu_reg);
5780 %}
5782 instruct popCountI_mem(eRegI dst, memory mem) %{
5783 predicate(UsePopCountInstruction);
5784 match(Set dst (PopCountI (LoadI mem)));
5786 format %{ "POPCNT $dst, $mem" %}
5787 ins_encode %{
5788 __ popcntl($dst$$Register, $mem$$Address);
5789 %}
5790 ins_pipe(ialu_reg);
5791 %}
5793 // Note: Long.bitCount(long) returns an int.
5794 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
5795 predicate(UsePopCountInstruction);
5796 match(Set dst (PopCountL src));
5797 effect(KILL cr, TEMP tmp, TEMP dst);
5799 format %{ "POPCNT $dst, $src.lo\n\t"
5800 "POPCNT $tmp, $src.hi\n\t"
5801 "ADD $dst, $tmp" %}
5802 ins_encode %{
5803 __ popcntl($dst$$Register, $src$$Register);
5804 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5805 __ addl($dst$$Register, $tmp$$Register);
5806 %}
5807 ins_pipe(ialu_reg);
5808 %}
5810 // Note: Long.bitCount(long) returns an int.
5811 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
5812 predicate(UsePopCountInstruction);
5813 match(Set dst (PopCountL (LoadL mem)));
5814 effect(KILL cr, TEMP tmp, TEMP dst);
5816 format %{ "POPCNT $dst, $mem\n\t"
5817 "POPCNT $tmp, $mem+4\n\t"
5818 "ADD $dst, $tmp" %}
5819 ins_encode %{
5820 //__ popcntl($dst$$Register, $mem$$Address$$first);
5821 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5822 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5823 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5824 __ addl($dst$$Register, $tmp$$Register);
5825 %}
5826 ins_pipe(ialu_reg);
5827 %}
5830 //----------Load/Store/Move Instructions---------------------------------------
5831 //----------Load Instructions--------------------------------------------------
5832 // Load Byte (8bit signed)
5833 instruct loadB(xRegI dst, memory mem) %{
5834 match(Set dst (LoadB mem));
5836 ins_cost(125);
5837 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5839 ins_encode %{
5840 __ movsbl($dst$$Register, $mem$$Address);
5841 %}
5843 ins_pipe(ialu_reg_mem);
5844 %}
5846 // Load Byte (8bit signed) into Long Register
5847 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5848 match(Set dst (ConvI2L (LoadB mem)));
5849 effect(KILL cr);
5851 ins_cost(375);
5852 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5853 "MOV $dst.hi,$dst.lo\n\t"
5854 "SAR $dst.hi,7" %}
5856 ins_encode %{
5857 __ movsbl($dst$$Register, $mem$$Address);
5858 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5859 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5860 %}
5862 ins_pipe(ialu_reg_mem);
5863 %}
5865 // Load Unsigned Byte (8bit UNsigned)
5866 instruct loadUB(xRegI dst, memory mem) %{
5867 match(Set dst (LoadUB mem));
5869 ins_cost(125);
5870 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5872 ins_encode %{
5873 __ movzbl($dst$$Register, $mem$$Address);
5874 %}
5876 ins_pipe(ialu_reg_mem);
5877 %}
5879 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5880 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5881 match(Set dst (ConvI2L (LoadUB mem)));
5882 effect(KILL cr);
5884 ins_cost(250);
5885 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5886 "XOR $dst.hi,$dst.hi" %}
5888 ins_encode %{
5889 Register Rdst = $dst$$Register;
5890 __ movzbl(Rdst, $mem$$Address);
5891 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5892 %}
5894 ins_pipe(ialu_reg_mem);
5895 %}
5897 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5898 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5899 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5900 effect(KILL cr);
5902 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5903 "XOR $dst.hi,$dst.hi\n\t"
5904 "AND $dst.lo,$mask" %}
5905 ins_encode %{
5906 Register Rdst = $dst$$Register;
5907 __ movzbl(Rdst, $mem$$Address);
5908 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5909 __ andl(Rdst, $mask$$constant);
5910 %}
5911 ins_pipe(ialu_reg_mem);
5912 %}
5914 // Load Short (16bit signed)
5915 instruct loadS(eRegI dst, memory mem) %{
5916 match(Set dst (LoadS mem));
5918 ins_cost(125);
5919 format %{ "MOVSX $dst,$mem\t# short" %}
5921 ins_encode %{
5922 __ movswl($dst$$Register, $mem$$Address);
5923 %}
5925 ins_pipe(ialu_reg_mem);
5926 %}
5928 // Load Short (16 bit signed) to Byte (8 bit signed)
5929 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
5930 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5932 ins_cost(125);
5933 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5934 ins_encode %{
5935 __ movsbl($dst$$Register, $mem$$Address);
5936 %}
5937 ins_pipe(ialu_reg_mem);
5938 %}
5940 // Load Short (16bit signed) into Long Register
5941 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5942 match(Set dst (ConvI2L (LoadS mem)));
5943 effect(KILL cr);
5945 ins_cost(375);
5946 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5947 "MOV $dst.hi,$dst.lo\n\t"
5948 "SAR $dst.hi,15" %}
5950 ins_encode %{
5951 __ movswl($dst$$Register, $mem$$Address);
5952 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5953 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5954 %}
5956 ins_pipe(ialu_reg_mem);
5957 %}
5959 // Load Unsigned Short/Char (16bit unsigned)
5960 instruct loadUS(eRegI dst, memory mem) %{
5961 match(Set dst (LoadUS mem));
5963 ins_cost(125);
5964 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5966 ins_encode %{
5967 __ movzwl($dst$$Register, $mem$$Address);
5968 %}
5970 ins_pipe(ialu_reg_mem);
5971 %}
5973 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5974 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
5975 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5977 ins_cost(125);
5978 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5979 ins_encode %{
5980 __ movsbl($dst$$Register, $mem$$Address);
5981 %}
5982 ins_pipe(ialu_reg_mem);
5983 %}
5985 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5986 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5987 match(Set dst (ConvI2L (LoadUS mem)));
5988 effect(KILL cr);
5990 ins_cost(250);
5991 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5992 "XOR $dst.hi,$dst.hi" %}
5994 ins_encode %{
5995 __ movzwl($dst$$Register, $mem$$Address);
5996 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5997 %}
5999 ins_pipe(ialu_reg_mem);
6000 %}
6002 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6003 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6004 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6005 effect(KILL cr);
6007 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6008 "XOR $dst.hi,$dst.hi" %}
6009 ins_encode %{
6010 Register Rdst = $dst$$Register;
6011 __ movzbl(Rdst, $mem$$Address);
6012 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6013 %}
6014 ins_pipe(ialu_reg_mem);
6015 %}
6017 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6018 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6019 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6020 effect(KILL cr);
6022 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6023 "XOR $dst.hi,$dst.hi\n\t"
6024 "AND $dst.lo,$mask" %}
6025 ins_encode %{
6026 Register Rdst = $dst$$Register;
6027 __ movzwl(Rdst, $mem$$Address);
6028 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6029 __ andl(Rdst, $mask$$constant);
6030 %}
6031 ins_pipe(ialu_reg_mem);
6032 %}
6034 // Load Integer
6035 instruct loadI(eRegI dst, memory mem) %{
6036 match(Set dst (LoadI mem));
6038 ins_cost(125);
6039 format %{ "MOV $dst,$mem\t# int" %}
6041 ins_encode %{
6042 __ movl($dst$$Register, $mem$$Address);
6043 %}
6045 ins_pipe(ialu_reg_mem);
6046 %}
6048 // Load Integer (32 bit signed) to Byte (8 bit signed)
6049 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6050 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6052 ins_cost(125);
6053 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6054 ins_encode %{
6055 __ movsbl($dst$$Register, $mem$$Address);
6056 %}
6057 ins_pipe(ialu_reg_mem);
6058 %}
6060 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6061 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6062 match(Set dst (AndI (LoadI mem) mask));
6064 ins_cost(125);
6065 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6066 ins_encode %{
6067 __ movzbl($dst$$Register, $mem$$Address);
6068 %}
6069 ins_pipe(ialu_reg_mem);
6070 %}
6072 // Load Integer (32 bit signed) to Short (16 bit signed)
6073 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6074 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6076 ins_cost(125);
6077 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6078 ins_encode %{
6079 __ movswl($dst$$Register, $mem$$Address);
6080 %}
6081 ins_pipe(ialu_reg_mem);
6082 %}
6084 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6085 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6086 match(Set dst (AndI (LoadI mem) mask));
6088 ins_cost(125);
6089 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6090 ins_encode %{
6091 __ movzwl($dst$$Register, $mem$$Address);
6092 %}
6093 ins_pipe(ialu_reg_mem);
6094 %}
6096 // Load Integer into Long Register
6097 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6098 match(Set dst (ConvI2L (LoadI mem)));
6099 effect(KILL cr);
6101 ins_cost(375);
6102 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6103 "MOV $dst.hi,$dst.lo\n\t"
6104 "SAR $dst.hi,31" %}
6106 ins_encode %{
6107 __ movl($dst$$Register, $mem$$Address);
6108 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6109 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6110 %}
6112 ins_pipe(ialu_reg_mem);
6113 %}
6115 // Load Integer with mask 0xFF into Long Register
6116 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6117 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6118 effect(KILL cr);
6120 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6121 "XOR $dst.hi,$dst.hi" %}
6122 ins_encode %{
6123 Register Rdst = $dst$$Register;
6124 __ movzbl(Rdst, $mem$$Address);
6125 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6126 %}
6127 ins_pipe(ialu_reg_mem);
6128 %}
6130 // Load Integer with mask 0xFFFF into Long Register
6131 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6132 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6133 effect(KILL cr);
6135 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6136 "XOR $dst.hi,$dst.hi" %}
6137 ins_encode %{
6138 Register Rdst = $dst$$Register;
6139 __ movzwl(Rdst, $mem$$Address);
6140 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6141 %}
6142 ins_pipe(ialu_reg_mem);
6143 %}
6145 // Load Integer with 32-bit mask into Long Register
6146 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6147 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6148 effect(KILL cr);
6150 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6151 "XOR $dst.hi,$dst.hi\n\t"
6152 "AND $dst.lo,$mask" %}
6153 ins_encode %{
6154 Register Rdst = $dst$$Register;
6155 __ movl(Rdst, $mem$$Address);
6156 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6157 __ andl(Rdst, $mask$$constant);
6158 %}
6159 ins_pipe(ialu_reg_mem);
6160 %}
6162 // Load Unsigned Integer into Long Register
6163 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6164 match(Set dst (LoadUI2L mem));
6165 effect(KILL cr);
6167 ins_cost(250);
6168 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6169 "XOR $dst.hi,$dst.hi" %}
6171 ins_encode %{
6172 __ movl($dst$$Register, $mem$$Address);
6173 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6174 %}
6176 ins_pipe(ialu_reg_mem);
6177 %}
6179 // Load Long. Cannot clobber address while loading, so restrict address
6180 // register to ESI
6181 instruct loadL(eRegL dst, load_long_memory mem) %{
6182 predicate(!((LoadLNode*)n)->require_atomic_access());
6183 match(Set dst (LoadL mem));
6185 ins_cost(250);
6186 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6187 "MOV $dst.hi,$mem+4" %}
6189 ins_encode %{
6190 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6191 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6192 __ movl($dst$$Register, Amemlo);
6193 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6194 %}
6196 ins_pipe(ialu_reg_long_mem);
6197 %}
6199 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6200 // then store it down to the stack and reload on the int
6201 // side.
6202 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6203 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6204 match(Set dst (LoadL mem));
6206 ins_cost(200);
6207 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6208 "FISTp $dst" %}
6209 ins_encode(enc_loadL_volatile(mem,dst));
6210 ins_pipe( fpu_reg_mem );
6211 %}
6213 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6214 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6215 match(Set dst (LoadL mem));
6216 effect(TEMP tmp);
6217 ins_cost(180);
6218 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6219 "MOVSD $dst,$tmp" %}
6220 ins_encode %{
6221 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6222 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6223 %}
6224 ins_pipe( pipe_slow );
6225 %}
6227 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6228 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6229 match(Set dst (LoadL mem));
6230 effect(TEMP tmp);
6231 ins_cost(160);
6232 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6233 "MOVD $dst.lo,$tmp\n\t"
6234 "PSRLQ $tmp,32\n\t"
6235 "MOVD $dst.hi,$tmp" %}
6236 ins_encode %{
6237 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6238 __ movdl($dst$$Register, $tmp$$XMMRegister);
6239 __ psrlq($tmp$$XMMRegister, 32);
6240 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6241 %}
6242 ins_pipe( pipe_slow );
6243 %}
6245 // Load Range
6246 instruct loadRange(eRegI dst, memory mem) %{
6247 match(Set dst (LoadRange mem));
6249 ins_cost(125);
6250 format %{ "MOV $dst,$mem" %}
6251 opcode(0x8B);
6252 ins_encode( OpcP, RegMem(dst,mem));
6253 ins_pipe( ialu_reg_mem );
6254 %}
6257 // Load Pointer
6258 instruct loadP(eRegP dst, memory mem) %{
6259 match(Set dst (LoadP mem));
6261 ins_cost(125);
6262 format %{ "MOV $dst,$mem" %}
6263 opcode(0x8B);
6264 ins_encode( OpcP, RegMem(dst,mem));
6265 ins_pipe( ialu_reg_mem );
6266 %}
6268 // Load Klass Pointer
6269 instruct loadKlass(eRegP dst, memory mem) %{
6270 match(Set dst (LoadKlass mem));
6272 ins_cost(125);
6273 format %{ "MOV $dst,$mem" %}
6274 opcode(0x8B);
6275 ins_encode( OpcP, RegMem(dst,mem));
6276 ins_pipe( ialu_reg_mem );
6277 %}
6279 // Load Double
6280 instruct loadDPR(regDPR dst, memory mem) %{
6281 predicate(UseSSE<=1);
6282 match(Set dst (LoadD mem));
6284 ins_cost(150);
6285 format %{ "FLD_D ST,$mem\n\t"
6286 "FSTP $dst" %}
6287 opcode(0xDD); /* DD /0 */
6288 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6289 Pop_Reg_DPR(dst) );
6290 ins_pipe( fpu_reg_mem );
6291 %}
6293 // Load Double to XMM
6294 instruct loadD(regD dst, memory mem) %{
6295 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6296 match(Set dst (LoadD mem));
6297 ins_cost(145);
6298 format %{ "MOVSD $dst,$mem" %}
6299 ins_encode %{
6300 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6301 %}
6302 ins_pipe( pipe_slow );
6303 %}
6305 instruct loadD_partial(regD dst, memory mem) %{
6306 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6307 match(Set dst (LoadD mem));
6308 ins_cost(145);
6309 format %{ "MOVLPD $dst,$mem" %}
6310 ins_encode %{
6311 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6312 %}
6313 ins_pipe( pipe_slow );
6314 %}
6316 // Load to XMM register (single-precision floating point)
6317 // MOVSS instruction
6318 instruct loadF(regF dst, memory mem) %{
6319 predicate(UseSSE>=1);
6320 match(Set dst (LoadF mem));
6321 ins_cost(145);
6322 format %{ "MOVSS $dst,$mem" %}
6323 ins_encode %{
6324 __ movflt ($dst$$XMMRegister, $mem$$Address);
6325 %}
6326 ins_pipe( pipe_slow );
6327 %}
6329 // Load Float
6330 instruct loadFPR(regFPR dst, memory mem) %{
6331 predicate(UseSSE==0);
6332 match(Set dst (LoadF mem));
6334 ins_cost(150);
6335 format %{ "FLD_S ST,$mem\n\t"
6336 "FSTP $dst" %}
6337 opcode(0xD9); /* D9 /0 */
6338 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6339 Pop_Reg_FPR(dst) );
6340 ins_pipe( fpu_reg_mem );
6341 %}
6343 // Load Aligned Packed Byte to XMM register
6344 instruct loadA8B(regD dst, memory mem) %{
6345 predicate(UseSSE>=1);
6346 match(Set dst (Load8B mem));
6347 ins_cost(125);
6348 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6349 ins_encode %{
6350 __ movq($dst$$XMMRegister, $mem$$Address);
6351 %}
6352 ins_pipe( pipe_slow );
6353 %}
6355 // Load Aligned Packed Short to XMM register
6356 instruct loadA4S(regD dst, memory mem) %{
6357 predicate(UseSSE>=1);
6358 match(Set dst (Load4S mem));
6359 ins_cost(125);
6360 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6361 ins_encode %{
6362 __ movq($dst$$XMMRegister, $mem$$Address);
6363 %}
6364 ins_pipe( pipe_slow );
6365 %}
6367 // Load Aligned Packed Char to XMM register
6368 instruct loadA4C(regD dst, memory mem) %{
6369 predicate(UseSSE>=1);
6370 match(Set dst (Load4C mem));
6371 ins_cost(125);
6372 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6373 ins_encode %{
6374 __ movq($dst$$XMMRegister, $mem$$Address);
6375 %}
6376 ins_pipe( pipe_slow );
6377 %}
6379 // Load Aligned Packed Integer to XMM register
6380 instruct load2IU(regD dst, memory mem) %{
6381 predicate(UseSSE>=1);
6382 match(Set dst (Load2I mem));
6383 ins_cost(125);
6384 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6385 ins_encode %{
6386 __ movq($dst$$XMMRegister, $mem$$Address);
6387 %}
6388 ins_pipe( pipe_slow );
6389 %}
6391 // Load Aligned Packed Single to XMM
6392 instruct loadA2F(regD dst, memory mem) %{
6393 predicate(UseSSE>=1);
6394 match(Set dst (Load2F mem));
6395 ins_cost(145);
6396 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6397 ins_encode %{
6398 __ movq($dst$$XMMRegister, $mem$$Address);
6399 %}
6400 ins_pipe( pipe_slow );
6401 %}
6403 // Load Effective Address
6404 instruct leaP8(eRegP dst, indOffset8 mem) %{
6405 match(Set dst mem);
6407 ins_cost(110);
6408 format %{ "LEA $dst,$mem" %}
6409 opcode(0x8D);
6410 ins_encode( OpcP, RegMem(dst,mem));
6411 ins_pipe( ialu_reg_reg_fat );
6412 %}
6414 instruct leaP32(eRegP dst, indOffset32 mem) %{
6415 match(Set dst mem);
6417 ins_cost(110);
6418 format %{ "LEA $dst,$mem" %}
6419 opcode(0x8D);
6420 ins_encode( OpcP, RegMem(dst,mem));
6421 ins_pipe( ialu_reg_reg_fat );
6422 %}
6424 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6425 match(Set dst mem);
6427 ins_cost(110);
6428 format %{ "LEA $dst,$mem" %}
6429 opcode(0x8D);
6430 ins_encode( OpcP, RegMem(dst,mem));
6431 ins_pipe( ialu_reg_reg_fat );
6432 %}
6434 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6435 match(Set dst mem);
6437 ins_cost(110);
6438 format %{ "LEA $dst,$mem" %}
6439 opcode(0x8D);
6440 ins_encode( OpcP, RegMem(dst,mem));
6441 ins_pipe( ialu_reg_reg_fat );
6442 %}
6444 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6445 match(Set dst mem);
6447 ins_cost(110);
6448 format %{ "LEA $dst,$mem" %}
6449 opcode(0x8D);
6450 ins_encode( OpcP, RegMem(dst,mem));
6451 ins_pipe( ialu_reg_reg_fat );
6452 %}
6454 // Load Constant
6455 instruct loadConI(eRegI dst, immI src) %{
6456 match(Set dst src);
6458 format %{ "MOV $dst,$src" %}
6459 ins_encode( LdImmI(dst, src) );
6460 ins_pipe( ialu_reg_fat );
6461 %}
6463 // Load Constant zero
6464 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6465 match(Set dst src);
6466 effect(KILL cr);
6468 ins_cost(50);
6469 format %{ "XOR $dst,$dst" %}
6470 opcode(0x33); /* + rd */
6471 ins_encode( OpcP, RegReg( dst, dst ) );
6472 ins_pipe( ialu_reg );
6473 %}
6475 instruct loadConP(eRegP dst, immP src) %{
6476 match(Set dst src);
6478 format %{ "MOV $dst,$src" %}
6479 opcode(0xB8); /* + rd */
6480 ins_encode( LdImmP(dst, src) );
6481 ins_pipe( ialu_reg_fat );
6482 %}
6484 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6485 match(Set dst src);
6486 effect(KILL cr);
6487 ins_cost(200);
6488 format %{ "MOV $dst.lo,$src.lo\n\t"
6489 "MOV $dst.hi,$src.hi" %}
6490 opcode(0xB8);
6491 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6492 ins_pipe( ialu_reg_long_fat );
6493 %}
6495 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6496 match(Set dst src);
6497 effect(KILL cr);
6498 ins_cost(150);
6499 format %{ "XOR $dst.lo,$dst.lo\n\t"
6500 "XOR $dst.hi,$dst.hi" %}
6501 opcode(0x33,0x33);
6502 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6503 ins_pipe( ialu_reg_long );
6504 %}
6506 // The instruction usage is guarded by predicate in operand immFPR().
6507 instruct loadConFPR(regFPR dst, immFPR con) %{
6508 match(Set dst con);
6509 ins_cost(125);
6510 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6511 "FSTP $dst" %}
6512 ins_encode %{
6513 __ fld_s($constantaddress($con));
6514 __ fstp_d($dst$$reg);
6515 %}
6516 ins_pipe(fpu_reg_con);
6517 %}
6519 // The instruction usage is guarded by predicate in operand immFPR0().
6520 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6521 match(Set dst con);
6522 ins_cost(125);
6523 format %{ "FLDZ ST\n\t"
6524 "FSTP $dst" %}
6525 ins_encode %{
6526 __ fldz();
6527 __ fstp_d($dst$$reg);
6528 %}
6529 ins_pipe(fpu_reg_con);
6530 %}
6532 // The instruction usage is guarded by predicate in operand immFPR1().
6533 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6534 match(Set dst con);
6535 ins_cost(125);
6536 format %{ "FLD1 ST\n\t"
6537 "FSTP $dst" %}
6538 ins_encode %{
6539 __ fld1();
6540 __ fstp_d($dst$$reg);
6541 %}
6542 ins_pipe(fpu_reg_con);
6543 %}
6545 // The instruction usage is guarded by predicate in operand immF().
6546 instruct loadConF(regF dst, immF con) %{
6547 match(Set dst con);
6548 ins_cost(125);
6549 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6550 ins_encode %{
6551 __ movflt($dst$$XMMRegister, $constantaddress($con));
6552 %}
6553 ins_pipe(pipe_slow);
6554 %}
6556 // The instruction usage is guarded by predicate in operand immF0().
6557 instruct loadConF0(regF dst, immF0 src) %{
6558 match(Set dst src);
6559 ins_cost(100);
6560 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6561 ins_encode %{
6562 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6563 %}
6564 ins_pipe(pipe_slow);
6565 %}
6567 // The instruction usage is guarded by predicate in operand immDPR().
6568 instruct loadConDPR(regDPR dst, immDPR con) %{
6569 match(Set dst con);
6570 ins_cost(125);
6572 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6573 "FSTP $dst" %}
6574 ins_encode %{
6575 __ fld_d($constantaddress($con));
6576 __ fstp_d($dst$$reg);
6577 %}
6578 ins_pipe(fpu_reg_con);
6579 %}
6581 // The instruction usage is guarded by predicate in operand immDPR0().
6582 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6583 match(Set dst con);
6584 ins_cost(125);
6586 format %{ "FLDZ ST\n\t"
6587 "FSTP $dst" %}
6588 ins_encode %{
6589 __ fldz();
6590 __ fstp_d($dst$$reg);
6591 %}
6592 ins_pipe(fpu_reg_con);
6593 %}
6595 // The instruction usage is guarded by predicate in operand immDPR1().
6596 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6597 match(Set dst con);
6598 ins_cost(125);
6600 format %{ "FLD1 ST\n\t"
6601 "FSTP $dst" %}
6602 ins_encode %{
6603 __ fld1();
6604 __ fstp_d($dst$$reg);
6605 %}
6606 ins_pipe(fpu_reg_con);
6607 %}
6609 // The instruction usage is guarded by predicate in operand immD().
6610 instruct loadConD(regD dst, immD con) %{
6611 match(Set dst con);
6612 ins_cost(125);
6613 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6614 ins_encode %{
6615 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6616 %}
6617 ins_pipe(pipe_slow);
6618 %}
6620 // The instruction usage is guarded by predicate in operand immD0().
6621 instruct loadConD0(regD dst, immD0 src) %{
6622 match(Set dst src);
6623 ins_cost(100);
6624 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6625 ins_encode %{
6626 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6627 %}
6628 ins_pipe( pipe_slow );
6629 %}
6631 // Load Stack Slot
6632 instruct loadSSI(eRegI dst, stackSlotI src) %{
6633 match(Set dst src);
6634 ins_cost(125);
6636 format %{ "MOV $dst,$src" %}
6637 opcode(0x8B);
6638 ins_encode( OpcP, RegMem(dst,src));
6639 ins_pipe( ialu_reg_mem );
6640 %}
6642 instruct loadSSL(eRegL dst, stackSlotL src) %{
6643 match(Set dst src);
6645 ins_cost(200);
6646 format %{ "MOV $dst,$src.lo\n\t"
6647 "MOV $dst+4,$src.hi" %}
6648 opcode(0x8B, 0x8B);
6649 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6650 ins_pipe( ialu_mem_long_reg );
6651 %}
6653 // Load Stack Slot
6654 instruct loadSSP(eRegP dst, stackSlotP src) %{
6655 match(Set dst src);
6656 ins_cost(125);
6658 format %{ "MOV $dst,$src" %}
6659 opcode(0x8B);
6660 ins_encode( OpcP, RegMem(dst,src));
6661 ins_pipe( ialu_reg_mem );
6662 %}
6664 // Load Stack Slot
6665 instruct loadSSF(regFPR dst, stackSlotF src) %{
6666 match(Set dst src);
6667 ins_cost(125);
6669 format %{ "FLD_S $src\n\t"
6670 "FSTP $dst" %}
6671 opcode(0xD9); /* D9 /0, FLD m32real */
6672 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6673 Pop_Reg_FPR(dst) );
6674 ins_pipe( fpu_reg_mem );
6675 %}
6677 // Load Stack Slot
6678 instruct loadSSD(regDPR dst, stackSlotD src) %{
6679 match(Set dst src);
6680 ins_cost(125);
6682 format %{ "FLD_D $src\n\t"
6683 "FSTP $dst" %}
6684 opcode(0xDD); /* DD /0, FLD m64real */
6685 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6686 Pop_Reg_DPR(dst) );
6687 ins_pipe( fpu_reg_mem );
6688 %}
6690 // Prefetch instructions.
6691 // Must be safe to execute with invalid address (cannot fault).
6693 instruct prefetchr0( memory mem ) %{
6694 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6695 match(PrefetchRead mem);
6696 ins_cost(0);
6697 size(0);
6698 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6699 ins_encode();
6700 ins_pipe(empty);
6701 %}
6703 instruct prefetchr( memory mem ) %{
6704 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6705 match(PrefetchRead mem);
6706 ins_cost(100);
6708 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6709 ins_encode %{
6710 __ prefetchr($mem$$Address);
6711 %}
6712 ins_pipe(ialu_mem);
6713 %}
6715 instruct prefetchrNTA( memory mem ) %{
6716 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6717 match(PrefetchRead mem);
6718 ins_cost(100);
6720 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6721 ins_encode %{
6722 __ prefetchnta($mem$$Address);
6723 %}
6724 ins_pipe(ialu_mem);
6725 %}
6727 instruct prefetchrT0( memory mem ) %{
6728 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6729 match(PrefetchRead mem);
6730 ins_cost(100);
6732 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6733 ins_encode %{
6734 __ prefetcht0($mem$$Address);
6735 %}
6736 ins_pipe(ialu_mem);
6737 %}
6739 instruct prefetchrT2( memory mem ) %{
6740 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6741 match(PrefetchRead mem);
6742 ins_cost(100);
6744 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6745 ins_encode %{
6746 __ prefetcht2($mem$$Address);
6747 %}
6748 ins_pipe(ialu_mem);
6749 %}
6751 instruct prefetchw0( memory mem ) %{
6752 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6753 match(PrefetchWrite mem);
6754 ins_cost(0);
6755 size(0);
6756 format %{ "Prefetch (non-SSE is empty encoding)" %}
6757 ins_encode();
6758 ins_pipe(empty);
6759 %}
6761 instruct prefetchw( memory mem ) %{
6762 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6763 match( PrefetchWrite mem );
6764 ins_cost(100);
6766 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6767 ins_encode %{
6768 __ prefetchw($mem$$Address);
6769 %}
6770 ins_pipe(ialu_mem);
6771 %}
6773 instruct prefetchwNTA( memory mem ) %{
6774 predicate(UseSSE>=1);
6775 match(PrefetchWrite mem);
6776 ins_cost(100);
6778 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6779 ins_encode %{
6780 __ prefetchnta($mem$$Address);
6781 %}
6782 ins_pipe(ialu_mem);
6783 %}
6785 // Prefetch instructions for allocation.
6787 instruct prefetchAlloc0( memory mem ) %{
6788 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6789 match(PrefetchAllocation mem);
6790 ins_cost(0);
6791 size(0);
6792 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6793 ins_encode();
6794 ins_pipe(empty);
6795 %}
6797 instruct prefetchAlloc( memory mem ) %{
6798 predicate(AllocatePrefetchInstr==3);
6799 match( PrefetchAllocation mem );
6800 ins_cost(100);
6802 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6803 ins_encode %{
6804 __ prefetchw($mem$$Address);
6805 %}
6806 ins_pipe(ialu_mem);
6807 %}
6809 instruct prefetchAllocNTA( memory mem ) %{
6810 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6811 match(PrefetchAllocation mem);
6812 ins_cost(100);
6814 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6815 ins_encode %{
6816 __ prefetchnta($mem$$Address);
6817 %}
6818 ins_pipe(ialu_mem);
6819 %}
6821 instruct prefetchAllocT0( memory mem ) %{
6822 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6823 match(PrefetchAllocation mem);
6824 ins_cost(100);
6826 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6827 ins_encode %{
6828 __ prefetcht0($mem$$Address);
6829 %}
6830 ins_pipe(ialu_mem);
6831 %}
6833 instruct prefetchAllocT2( memory mem ) %{
6834 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6835 match(PrefetchAllocation mem);
6836 ins_cost(100);
6838 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6839 ins_encode %{
6840 __ prefetcht2($mem$$Address);
6841 %}
6842 ins_pipe(ialu_mem);
6843 %}
6845 //----------Store Instructions-------------------------------------------------
6847 // Store Byte
6848 instruct storeB(memory mem, xRegI src) %{
6849 match(Set mem (StoreB mem src));
6851 ins_cost(125);
6852 format %{ "MOV8 $mem,$src" %}
6853 opcode(0x88);
6854 ins_encode( OpcP, RegMem( src, mem ) );
6855 ins_pipe( ialu_mem_reg );
6856 %}
6858 // Store Char/Short
6859 instruct storeC(memory mem, eRegI src) %{
6860 match(Set mem (StoreC mem src));
6862 ins_cost(125);
6863 format %{ "MOV16 $mem,$src" %}
6864 opcode(0x89, 0x66);
6865 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6866 ins_pipe( ialu_mem_reg );
6867 %}
6869 // Store Integer
6870 instruct storeI(memory mem, eRegI src) %{
6871 match(Set mem (StoreI mem src));
6873 ins_cost(125);
6874 format %{ "MOV $mem,$src" %}
6875 opcode(0x89);
6876 ins_encode( OpcP, RegMem( src, mem ) );
6877 ins_pipe( ialu_mem_reg );
6878 %}
6880 // Store Long
6881 instruct storeL(long_memory mem, eRegL src) %{
6882 predicate(!((StoreLNode*)n)->require_atomic_access());
6883 match(Set mem (StoreL mem src));
6885 ins_cost(200);
6886 format %{ "MOV $mem,$src.lo\n\t"
6887 "MOV $mem+4,$src.hi" %}
6888 opcode(0x89, 0x89);
6889 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6890 ins_pipe( ialu_mem_long_reg );
6891 %}
6893 // Store Long to Integer
6894 instruct storeL2I(memory mem, eRegL src) %{
6895 match(Set mem (StoreI mem (ConvL2I src)));
6897 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6898 ins_encode %{
6899 __ movl($mem$$Address, $src$$Register);
6900 %}
6901 ins_pipe(ialu_mem_reg);
6902 %}
6904 // Volatile Store Long. Must be atomic, so move it into
6905 // the FP TOS and then do a 64-bit FIST. Has to probe the
6906 // target address before the store (for null-ptr checks)
6907 // so the memory operand is used twice in the encoding.
6908 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6909 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6910 match(Set mem (StoreL mem src));
6911 effect( KILL cr );
6912 ins_cost(400);
6913 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6914 "FILD $src\n\t"
6915 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6916 opcode(0x3B);
6917 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6918 ins_pipe( fpu_reg_mem );
6919 %}
6921 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6922 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6923 match(Set mem (StoreL mem src));
6924 effect( TEMP tmp, KILL cr );
6925 ins_cost(380);
6926 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6927 "MOVSD $tmp,$src\n\t"
6928 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6929 ins_encode %{
6930 __ cmpl(rax, $mem$$Address);
6931 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6932 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6933 %}
6934 ins_pipe( pipe_slow );
6935 %}
6937 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6938 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6939 match(Set mem (StoreL mem src));
6940 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6941 ins_cost(360);
6942 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6943 "MOVD $tmp,$src.lo\n\t"
6944 "MOVD $tmp2,$src.hi\n\t"
6945 "PUNPCKLDQ $tmp,$tmp2\n\t"
6946 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6947 ins_encode %{
6948 __ cmpl(rax, $mem$$Address);
6949 __ movdl($tmp$$XMMRegister, $src$$Register);
6950 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6951 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6952 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6953 %}
6954 ins_pipe( pipe_slow );
6955 %}
6957 // Store Pointer; for storing unknown oops and raw pointers
6958 instruct storeP(memory mem, anyRegP src) %{
6959 match(Set mem (StoreP mem src));
6961 ins_cost(125);
6962 format %{ "MOV $mem,$src" %}
6963 opcode(0x89);
6964 ins_encode( OpcP, RegMem( src, mem ) );
6965 ins_pipe( ialu_mem_reg );
6966 %}
6968 // Store Integer Immediate
6969 instruct storeImmI(memory mem, immI src) %{
6970 match(Set mem (StoreI mem src));
6972 ins_cost(150);
6973 format %{ "MOV $mem,$src" %}
6974 opcode(0xC7); /* C7 /0 */
6975 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6976 ins_pipe( ialu_mem_imm );
6977 %}
6979 // Store Short/Char Immediate
6980 instruct storeImmI16(memory mem, immI16 src) %{
6981 predicate(UseStoreImmI16);
6982 match(Set mem (StoreC mem src));
6984 ins_cost(150);
6985 format %{ "MOV16 $mem,$src" %}
6986 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6987 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6988 ins_pipe( ialu_mem_imm );
6989 %}
6991 // Store Pointer Immediate; null pointers or constant oops that do not
6992 // need card-mark barriers.
6993 instruct storeImmP(memory mem, immP src) %{
6994 match(Set mem (StoreP mem src));
6996 ins_cost(150);
6997 format %{ "MOV $mem,$src" %}
6998 opcode(0xC7); /* C7 /0 */
6999 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7000 ins_pipe( ialu_mem_imm );
7001 %}
7003 // Store Byte Immediate
7004 instruct storeImmB(memory mem, immI8 src) %{
7005 match(Set mem (StoreB mem src));
7007 ins_cost(150);
7008 format %{ "MOV8 $mem,$src" %}
7009 opcode(0xC6); /* C6 /0 */
7010 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7011 ins_pipe( ialu_mem_imm );
7012 %}
7014 // Store Aligned Packed Byte XMM register to memory
7015 instruct storeA8B(memory mem, regD src) %{
7016 predicate(UseSSE>=1);
7017 match(Set mem (Store8B mem src));
7018 ins_cost(145);
7019 format %{ "MOVQ $mem,$src\t! packed8B" %}
7020 ins_encode %{
7021 __ movq($mem$$Address, $src$$XMMRegister);
7022 %}
7023 ins_pipe( pipe_slow );
7024 %}
7026 // Store Aligned Packed Char/Short XMM register to memory
7027 instruct storeA4C(memory mem, regD src) %{
7028 predicate(UseSSE>=1);
7029 match(Set mem (Store4C mem src));
7030 ins_cost(145);
7031 format %{ "MOVQ $mem,$src\t! packed4C" %}
7032 ins_encode %{
7033 __ movq($mem$$Address, $src$$XMMRegister);
7034 %}
7035 ins_pipe( pipe_slow );
7036 %}
7038 // Store Aligned Packed Integer XMM register to memory
7039 instruct storeA2I(memory mem, regD src) %{
7040 predicate(UseSSE>=1);
7041 match(Set mem (Store2I mem src));
7042 ins_cost(145);
7043 format %{ "MOVQ $mem,$src\t! packed2I" %}
7044 ins_encode %{
7045 __ movq($mem$$Address, $src$$XMMRegister);
7046 %}
7047 ins_pipe( pipe_slow );
7048 %}
7050 // Store CMS card-mark Immediate
7051 instruct storeImmCM(memory mem, immI8 src) %{
7052 match(Set mem (StoreCM mem src));
7054 ins_cost(150);
7055 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7056 opcode(0xC6); /* C6 /0 */
7057 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7058 ins_pipe( ialu_mem_imm );
7059 %}
7061 // Store Double
7062 instruct storeDPR( memory mem, regDPR1 src) %{
7063 predicate(UseSSE<=1);
7064 match(Set mem (StoreD mem src));
7066 ins_cost(100);
7067 format %{ "FST_D $mem,$src" %}
7068 opcode(0xDD); /* DD /2 */
7069 ins_encode( enc_FPR_store(mem,src) );
7070 ins_pipe( fpu_mem_reg );
7071 %}
7073 // Store double does rounding on x86
7074 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
7075 predicate(UseSSE<=1);
7076 match(Set mem (StoreD mem (RoundDouble src)));
7078 ins_cost(100);
7079 format %{ "FST_D $mem,$src\t# round" %}
7080 opcode(0xDD); /* DD /2 */
7081 ins_encode( enc_FPR_store(mem,src) );
7082 ins_pipe( fpu_mem_reg );
7083 %}
7085 // Store XMM register to memory (double-precision floating points)
7086 // MOVSD instruction
7087 instruct storeD(memory mem, regD src) %{
7088 predicate(UseSSE>=2);
7089 match(Set mem (StoreD mem src));
7090 ins_cost(95);
7091 format %{ "MOVSD $mem,$src" %}
7092 ins_encode %{
7093 __ movdbl($mem$$Address, $src$$XMMRegister);
7094 %}
7095 ins_pipe( pipe_slow );
7096 %}
7098 // Store XMM register to memory (single-precision floating point)
7099 // MOVSS instruction
7100 instruct storeF(memory mem, regF src) %{
7101 predicate(UseSSE>=1);
7102 match(Set mem (StoreF mem src));
7103 ins_cost(95);
7104 format %{ "MOVSS $mem,$src" %}
7105 ins_encode %{
7106 __ movflt($mem$$Address, $src$$XMMRegister);
7107 %}
7108 ins_pipe( pipe_slow );
7109 %}
7111 // Store Aligned Packed Single Float XMM register to memory
7112 instruct storeA2F(memory mem, regD src) %{
7113 predicate(UseSSE>=1);
7114 match(Set mem (Store2F mem src));
7115 ins_cost(145);
7116 format %{ "MOVQ $mem,$src\t! packed2F" %}
7117 ins_encode %{
7118 __ movq($mem$$Address, $src$$XMMRegister);
7119 %}
7120 ins_pipe( pipe_slow );
7121 %}
7123 // Store Float
7124 instruct storeFPR( memory mem, regFPR1 src) %{
7125 predicate(UseSSE==0);
7126 match(Set mem (StoreF mem src));
7128 ins_cost(100);
7129 format %{ "FST_S $mem,$src" %}
7130 opcode(0xD9); /* D9 /2 */
7131 ins_encode( enc_FPR_store(mem,src) );
7132 ins_pipe( fpu_mem_reg );
7133 %}
7135 // Store Float does rounding on x86
7136 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7137 predicate(UseSSE==0);
7138 match(Set mem (StoreF mem (RoundFloat src)));
7140 ins_cost(100);
7141 format %{ "FST_S $mem,$src\t# round" %}
7142 opcode(0xD9); /* D9 /2 */
7143 ins_encode( enc_FPR_store(mem,src) );
7144 ins_pipe( fpu_mem_reg );
7145 %}
7147 // Store Float does rounding on x86
7148 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7149 predicate(UseSSE<=1);
7150 match(Set mem (StoreF mem (ConvD2F src)));
7152 ins_cost(100);
7153 format %{ "FST_S $mem,$src\t# D-round" %}
7154 opcode(0xD9); /* D9 /2 */
7155 ins_encode( enc_FPR_store(mem,src) );
7156 ins_pipe( fpu_mem_reg );
7157 %}
7159 // Store immediate Float value (it is faster than store from FPU register)
7160 // The instruction usage is guarded by predicate in operand immFPR().
7161 instruct storeFPR_imm( memory mem, immFPR src) %{
7162 match(Set mem (StoreF mem src));
7164 ins_cost(50);
7165 format %{ "MOV $mem,$src\t# store float" %}
7166 opcode(0xC7); /* C7 /0 */
7167 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7168 ins_pipe( ialu_mem_imm );
7169 %}
7171 // Store immediate Float value (it is faster than store from XMM register)
7172 // The instruction usage is guarded by predicate in operand immF().
7173 instruct storeF_imm( memory mem, immF src) %{
7174 match(Set mem (StoreF mem src));
7176 ins_cost(50);
7177 format %{ "MOV $mem,$src\t# store float" %}
7178 opcode(0xC7); /* C7 /0 */
7179 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7180 ins_pipe( ialu_mem_imm );
7181 %}
7183 // Store Integer to stack slot
7184 instruct storeSSI(stackSlotI dst, eRegI src) %{
7185 match(Set dst src);
7187 ins_cost(100);
7188 format %{ "MOV $dst,$src" %}
7189 opcode(0x89);
7190 ins_encode( OpcPRegSS( dst, src ) );
7191 ins_pipe( ialu_mem_reg );
7192 %}
7194 // Store Integer to stack slot
7195 instruct storeSSP(stackSlotP dst, eRegP src) %{
7196 match(Set dst src);
7198 ins_cost(100);
7199 format %{ "MOV $dst,$src" %}
7200 opcode(0x89);
7201 ins_encode( OpcPRegSS( dst, src ) );
7202 ins_pipe( ialu_mem_reg );
7203 %}
7205 // Store Long to stack slot
7206 instruct storeSSL(stackSlotL dst, eRegL src) %{
7207 match(Set dst src);
7209 ins_cost(200);
7210 format %{ "MOV $dst,$src.lo\n\t"
7211 "MOV $dst+4,$src.hi" %}
7212 opcode(0x89, 0x89);
7213 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7214 ins_pipe( ialu_mem_long_reg );
7215 %}
7217 //----------MemBar Instructions-----------------------------------------------
7218 // Memory barrier flavors
7220 instruct membar_acquire() %{
7221 match(MemBarAcquire);
7222 ins_cost(400);
7224 size(0);
7225 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7226 ins_encode();
7227 ins_pipe(empty);
7228 %}
7230 instruct membar_acquire_lock() %{
7231 match(MemBarAcquireLock);
7232 ins_cost(0);
7234 size(0);
7235 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7236 ins_encode( );
7237 ins_pipe(empty);
7238 %}
7240 instruct membar_release() %{
7241 match(MemBarRelease);
7242 ins_cost(400);
7244 size(0);
7245 format %{ "MEMBAR-release ! (empty encoding)" %}
7246 ins_encode( );
7247 ins_pipe(empty);
7248 %}
7250 instruct membar_release_lock() %{
7251 match(MemBarReleaseLock);
7252 ins_cost(0);
7254 size(0);
7255 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7256 ins_encode( );
7257 ins_pipe(empty);
7258 %}
7260 instruct membar_volatile(eFlagsReg cr) %{
7261 match(MemBarVolatile);
7262 effect(KILL cr);
7263 ins_cost(400);
7265 format %{
7266 $$template
7267 if (os::is_MP()) {
7268 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7269 } else {
7270 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7271 }
7272 %}
7273 ins_encode %{
7274 __ membar(Assembler::StoreLoad);
7275 %}
7276 ins_pipe(pipe_slow);
7277 %}
7279 instruct unnecessary_membar_volatile() %{
7280 match(MemBarVolatile);
7281 predicate(Matcher::post_store_load_barrier(n));
7282 ins_cost(0);
7284 size(0);
7285 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7286 ins_encode( );
7287 ins_pipe(empty);
7288 %}
7290 instruct membar_storestore() %{
7291 match(MemBarStoreStore);
7292 ins_cost(0);
7294 size(0);
7295 format %{ "MEMBAR-storestore (empty encoding)" %}
7296 ins_encode( );
7297 ins_pipe(empty);
7298 %}
7300 //----------Move Instructions--------------------------------------------------
7301 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7302 match(Set dst (CastX2P src));
7303 format %{ "# X2P $dst, $src" %}
7304 ins_encode( /*empty encoding*/ );
7305 ins_cost(0);
7306 ins_pipe(empty);
7307 %}
7309 instruct castP2X(eRegI dst, eRegP src ) %{
7310 match(Set dst (CastP2X src));
7311 ins_cost(50);
7312 format %{ "MOV $dst, $src\t# CastP2X" %}
7313 ins_encode( enc_Copy( dst, src) );
7314 ins_pipe( ialu_reg_reg );
7315 %}
7317 //----------Conditional Move---------------------------------------------------
7318 // Conditional move
7319 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
7320 predicate(!VM_Version::supports_cmov() );
7321 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7322 ins_cost(200);
7323 format %{ "J$cop,us skip\t# signed cmove\n\t"
7324 "MOV $dst,$src\n"
7325 "skip:" %}
7326 ins_encode %{
7327 Label Lskip;
7328 // Invert sense of branch from sense of CMOV
7329 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7330 __ movl($dst$$Register, $src$$Register);
7331 __ bind(Lskip);
7332 %}
7333 ins_pipe( pipe_cmov_reg );
7334 %}
7336 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
7337 predicate(!VM_Version::supports_cmov() );
7338 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7339 ins_cost(200);
7340 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7341 "MOV $dst,$src\n"
7342 "skip:" %}
7343 ins_encode %{
7344 Label Lskip;
7345 // Invert sense of branch from sense of CMOV
7346 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7347 __ movl($dst$$Register, $src$$Register);
7348 __ bind(Lskip);
7349 %}
7350 ins_pipe( pipe_cmov_reg );
7351 %}
7353 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7354 predicate(VM_Version::supports_cmov() );
7355 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7356 ins_cost(200);
7357 format %{ "CMOV$cop $dst,$src" %}
7358 opcode(0x0F,0x40);
7359 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7360 ins_pipe( pipe_cmov_reg );
7361 %}
7363 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7364 predicate(VM_Version::supports_cmov() );
7365 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7366 ins_cost(200);
7367 format %{ "CMOV$cop $dst,$src" %}
7368 opcode(0x0F,0x40);
7369 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7370 ins_pipe( pipe_cmov_reg );
7371 %}
7373 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7374 predicate(VM_Version::supports_cmov() );
7375 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7376 ins_cost(200);
7377 expand %{
7378 cmovI_regU(cop, cr, dst, src);
7379 %}
7380 %}
7382 // Conditional move
7383 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7384 predicate(VM_Version::supports_cmov() );
7385 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7386 ins_cost(250);
7387 format %{ "CMOV$cop $dst,$src" %}
7388 opcode(0x0F,0x40);
7389 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7390 ins_pipe( pipe_cmov_mem );
7391 %}
7393 // Conditional move
7394 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7395 predicate(VM_Version::supports_cmov() );
7396 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7397 ins_cost(250);
7398 format %{ "CMOV$cop $dst,$src" %}
7399 opcode(0x0F,0x40);
7400 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7401 ins_pipe( pipe_cmov_mem );
7402 %}
7404 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7405 predicate(VM_Version::supports_cmov() );
7406 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7407 ins_cost(250);
7408 expand %{
7409 cmovI_memU(cop, cr, dst, src);
7410 %}
7411 %}
7413 // Conditional move
7414 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7415 predicate(VM_Version::supports_cmov() );
7416 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7417 ins_cost(200);
7418 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7419 opcode(0x0F,0x40);
7420 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7421 ins_pipe( pipe_cmov_reg );
7422 %}
7424 // Conditional move (non-P6 version)
7425 // Note: a CMoveP is generated for stubs and native wrappers
7426 // regardless of whether we are on a P6, so we
7427 // emulate a cmov here
7428 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7429 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7430 ins_cost(300);
7431 format %{ "Jn$cop skip\n\t"
7432 "MOV $dst,$src\t# pointer\n"
7433 "skip:" %}
7434 opcode(0x8b);
7435 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7436 ins_pipe( pipe_cmov_reg );
7437 %}
7439 // Conditional move
7440 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7441 predicate(VM_Version::supports_cmov() );
7442 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7443 ins_cost(200);
7444 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7445 opcode(0x0F,0x40);
7446 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7447 ins_pipe( pipe_cmov_reg );
7448 %}
7450 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7451 predicate(VM_Version::supports_cmov() );
7452 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7453 ins_cost(200);
7454 expand %{
7455 cmovP_regU(cop, cr, dst, src);
7456 %}
7457 %}
7459 // DISABLED: Requires the ADLC to emit a bottom_type call that
7460 // correctly meets the two pointer arguments; one is an incoming
7461 // register but the other is a memory operand. ALSO appears to
7462 // be buggy with implicit null checks.
7463 //
7464 //// Conditional move
7465 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7466 // predicate(VM_Version::supports_cmov() );
7467 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7468 // ins_cost(250);
7469 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7470 // opcode(0x0F,0x40);
7471 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7472 // ins_pipe( pipe_cmov_mem );
7473 //%}
7474 //
7475 //// Conditional move
7476 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7477 // predicate(VM_Version::supports_cmov() );
7478 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7479 // ins_cost(250);
7480 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7481 // opcode(0x0F,0x40);
7482 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7483 // ins_pipe( pipe_cmov_mem );
7484 //%}
7486 // Conditional move
7487 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7488 predicate(UseSSE<=1);
7489 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7490 ins_cost(200);
7491 format %{ "FCMOV$cop $dst,$src\t# double" %}
7492 opcode(0xDA);
7493 ins_encode( enc_cmov_dpr(cop,src) );
7494 ins_pipe( pipe_cmovDPR_reg );
7495 %}
7497 // Conditional move
7498 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7499 predicate(UseSSE==0);
7500 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7501 ins_cost(200);
7502 format %{ "FCMOV$cop $dst,$src\t# float" %}
7503 opcode(0xDA);
7504 ins_encode( enc_cmov_dpr(cop,src) );
7505 ins_pipe( pipe_cmovDPR_reg );
7506 %}
7508 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7509 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7510 predicate(UseSSE<=1);
7511 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7512 ins_cost(200);
7513 format %{ "Jn$cop skip\n\t"
7514 "MOV $dst,$src\t# double\n"
7515 "skip:" %}
7516 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7517 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7518 ins_pipe( pipe_cmovDPR_reg );
7519 %}
7521 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7522 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7523 predicate(UseSSE==0);
7524 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7525 ins_cost(200);
7526 format %{ "Jn$cop skip\n\t"
7527 "MOV $dst,$src\t# float\n"
7528 "skip:" %}
7529 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7530 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7531 ins_pipe( pipe_cmovDPR_reg );
7532 %}
7534 // No CMOVE with SSE/SSE2
7535 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7536 predicate (UseSSE>=1);
7537 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7538 ins_cost(200);
7539 format %{ "Jn$cop skip\n\t"
7540 "MOVSS $dst,$src\t# float\n"
7541 "skip:" %}
7542 ins_encode %{
7543 Label skip;
7544 // Invert sense of branch from sense of CMOV
7545 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7546 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7547 __ bind(skip);
7548 %}
7549 ins_pipe( pipe_slow );
7550 %}
7552 // No CMOVE with SSE/SSE2
7553 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7554 predicate (UseSSE>=2);
7555 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7556 ins_cost(200);
7557 format %{ "Jn$cop skip\n\t"
7558 "MOVSD $dst,$src\t# float\n"
7559 "skip:" %}
7560 ins_encode %{
7561 Label skip;
7562 // Invert sense of branch from sense of CMOV
7563 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7564 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7565 __ bind(skip);
7566 %}
7567 ins_pipe( pipe_slow );
7568 %}
7570 // unsigned version
7571 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7572 predicate (UseSSE>=1);
7573 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7574 ins_cost(200);
7575 format %{ "Jn$cop skip\n\t"
7576 "MOVSS $dst,$src\t# float\n"
7577 "skip:" %}
7578 ins_encode %{
7579 Label skip;
7580 // Invert sense of branch from sense of CMOV
7581 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7582 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7583 __ bind(skip);
7584 %}
7585 ins_pipe( pipe_slow );
7586 %}
7588 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7589 predicate (UseSSE>=1);
7590 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7591 ins_cost(200);
7592 expand %{
7593 fcmovF_regU(cop, cr, dst, src);
7594 %}
7595 %}
7597 // unsigned version
7598 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7599 predicate (UseSSE>=2);
7600 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7601 ins_cost(200);
7602 format %{ "Jn$cop skip\n\t"
7603 "MOVSD $dst,$src\t# float\n"
7604 "skip:" %}
7605 ins_encode %{
7606 Label skip;
7607 // Invert sense of branch from sense of CMOV
7608 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7609 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7610 __ bind(skip);
7611 %}
7612 ins_pipe( pipe_slow );
7613 %}
7615 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7616 predicate (UseSSE>=2);
7617 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7618 ins_cost(200);
7619 expand %{
7620 fcmovD_regU(cop, cr, dst, src);
7621 %}
7622 %}
7624 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7625 predicate(VM_Version::supports_cmov() );
7626 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7627 ins_cost(200);
7628 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7629 "CMOV$cop $dst.hi,$src.hi" %}
7630 opcode(0x0F,0x40);
7631 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7632 ins_pipe( pipe_cmov_reg_long );
7633 %}
7635 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7636 predicate(VM_Version::supports_cmov() );
7637 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7638 ins_cost(200);
7639 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7640 "CMOV$cop $dst.hi,$src.hi" %}
7641 opcode(0x0F,0x40);
7642 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7643 ins_pipe( pipe_cmov_reg_long );
7644 %}
7646 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7647 predicate(VM_Version::supports_cmov() );
7648 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7649 ins_cost(200);
7650 expand %{
7651 cmovL_regU(cop, cr, dst, src);
7652 %}
7653 %}
7655 //----------Arithmetic Instructions--------------------------------------------
7656 //----------Addition Instructions----------------------------------------------
7657 // Integer Addition Instructions
7658 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7659 match(Set dst (AddI dst src));
7660 effect(KILL cr);
7662 size(2);
7663 format %{ "ADD $dst,$src" %}
7664 opcode(0x03);
7665 ins_encode( OpcP, RegReg( dst, src) );
7666 ins_pipe( ialu_reg_reg );
7667 %}
7669 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7670 match(Set dst (AddI dst src));
7671 effect(KILL cr);
7673 format %{ "ADD $dst,$src" %}
7674 opcode(0x81, 0x00); /* /0 id */
7675 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7676 ins_pipe( ialu_reg );
7677 %}
7679 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7680 predicate(UseIncDec);
7681 match(Set dst (AddI dst src));
7682 effect(KILL cr);
7684 size(1);
7685 format %{ "INC $dst" %}
7686 opcode(0x40); /* */
7687 ins_encode( Opc_plus( primary, dst ) );
7688 ins_pipe( ialu_reg );
7689 %}
7691 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7692 match(Set dst (AddI src0 src1));
7693 ins_cost(110);
7695 format %{ "LEA $dst,[$src0 + $src1]" %}
7696 opcode(0x8D); /* 0x8D /r */
7697 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7698 ins_pipe( ialu_reg_reg );
7699 %}
7701 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7702 match(Set dst (AddP src0 src1));
7703 ins_cost(110);
7705 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7706 opcode(0x8D); /* 0x8D /r */
7707 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7708 ins_pipe( ialu_reg_reg );
7709 %}
7711 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7712 predicate(UseIncDec);
7713 match(Set dst (AddI dst src));
7714 effect(KILL cr);
7716 size(1);
7717 format %{ "DEC $dst" %}
7718 opcode(0x48); /* */
7719 ins_encode( Opc_plus( primary, dst ) );
7720 ins_pipe( ialu_reg );
7721 %}
7723 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7724 match(Set dst (AddP dst src));
7725 effect(KILL cr);
7727 size(2);
7728 format %{ "ADD $dst,$src" %}
7729 opcode(0x03);
7730 ins_encode( OpcP, RegReg( dst, src) );
7731 ins_pipe( ialu_reg_reg );
7732 %}
7734 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7735 match(Set dst (AddP dst src));
7736 effect(KILL cr);
7738 format %{ "ADD $dst,$src" %}
7739 opcode(0x81,0x00); /* Opcode 81 /0 id */
7740 // ins_encode( RegImm( dst, src) );
7741 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7742 ins_pipe( ialu_reg );
7743 %}
7745 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7746 match(Set dst (AddI dst (LoadI src)));
7747 effect(KILL cr);
7749 ins_cost(125);
7750 format %{ "ADD $dst,$src" %}
7751 opcode(0x03);
7752 ins_encode( OpcP, RegMem( dst, src) );
7753 ins_pipe( ialu_reg_mem );
7754 %}
7756 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7757 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7758 effect(KILL cr);
7760 ins_cost(150);
7761 format %{ "ADD $dst,$src" %}
7762 opcode(0x01); /* Opcode 01 /r */
7763 ins_encode( OpcP, RegMem( src, dst ) );
7764 ins_pipe( ialu_mem_reg );
7765 %}
7767 // Add Memory with Immediate
7768 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7769 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7770 effect(KILL cr);
7772 ins_cost(125);
7773 format %{ "ADD $dst,$src" %}
7774 opcode(0x81); /* Opcode 81 /0 id */
7775 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7776 ins_pipe( ialu_mem_imm );
7777 %}
7779 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7780 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7781 effect(KILL cr);
7783 ins_cost(125);
7784 format %{ "INC $dst" %}
7785 opcode(0xFF); /* Opcode FF /0 */
7786 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7787 ins_pipe( ialu_mem_imm );
7788 %}
7790 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7791 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7792 effect(KILL cr);
7794 ins_cost(125);
7795 format %{ "DEC $dst" %}
7796 opcode(0xFF); /* Opcode FF /1 */
7797 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7798 ins_pipe( ialu_mem_imm );
7799 %}
7802 instruct checkCastPP( eRegP dst ) %{
7803 match(Set dst (CheckCastPP dst));
7805 size(0);
7806 format %{ "#checkcastPP of $dst" %}
7807 ins_encode( /*empty encoding*/ );
7808 ins_pipe( empty );
7809 %}
7811 instruct castPP( eRegP dst ) %{
7812 match(Set dst (CastPP dst));
7813 format %{ "#castPP of $dst" %}
7814 ins_encode( /*empty encoding*/ );
7815 ins_pipe( empty );
7816 %}
7818 instruct castII( eRegI dst ) %{
7819 match(Set dst (CastII dst));
7820 format %{ "#castII of $dst" %}
7821 ins_encode( /*empty encoding*/ );
7822 ins_cost(0);
7823 ins_pipe( empty );
7824 %}
7827 // Load-locked - same as a regular pointer load when used with compare-swap
7828 instruct loadPLocked(eRegP dst, memory mem) %{
7829 match(Set dst (LoadPLocked mem));
7831 ins_cost(125);
7832 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7833 opcode(0x8B);
7834 ins_encode( OpcP, RegMem(dst,mem));
7835 ins_pipe( ialu_reg_mem );
7836 %}
7838 // LoadLong-locked - same as a volatile long load when used with compare-swap
7839 instruct loadLLocked(stackSlotL dst, memory mem) %{
7840 predicate(UseSSE<=1);
7841 match(Set dst (LoadLLocked mem));
7843 ins_cost(200);
7844 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7845 "FISTp $dst" %}
7846 ins_encode(enc_loadL_volatile(mem,dst));
7847 ins_pipe( fpu_reg_mem );
7848 %}
7850 instruct loadLX_Locked(stackSlotL dst, memory mem, regD tmp) %{
7851 predicate(UseSSE>=2);
7852 match(Set dst (LoadLLocked mem));
7853 effect(TEMP tmp);
7854 ins_cost(180);
7855 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7856 "MOVSD $dst,$tmp" %}
7857 ins_encode %{
7858 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7859 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
7860 %}
7861 ins_pipe( pipe_slow );
7862 %}
7864 instruct loadLX_reg_Locked(eRegL dst, memory mem, regD tmp) %{
7865 predicate(UseSSE>=2);
7866 match(Set dst (LoadLLocked mem));
7867 effect(TEMP tmp);
7868 ins_cost(160);
7869 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7870 "MOVD $dst.lo,$tmp\n\t"
7871 "PSRLQ $tmp,32\n\t"
7872 "MOVD $dst.hi,$tmp" %}
7873 ins_encode %{
7874 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7875 __ movdl($dst$$Register, $tmp$$XMMRegister);
7876 __ psrlq($tmp$$XMMRegister, 32);
7877 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
7878 %}
7879 ins_pipe( pipe_slow );
7880 %}
7882 // Conditional-store of the updated heap-top.
7883 // Used during allocation of the shared heap.
7884 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7885 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7886 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7887 // EAX is killed if there is contention, but then it's also unused.
7888 // In the common case of no contention, EAX holds the new oop address.
7889 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7890 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7891 ins_pipe( pipe_cmpxchg );
7892 %}
7894 // Conditional-store of an int value.
7895 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7896 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
7897 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7898 effect(KILL oldval);
7899 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7900 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7901 ins_pipe( pipe_cmpxchg );
7902 %}
7904 // Conditional-store of a long value.
7905 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7906 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7907 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7908 effect(KILL oldval);
7909 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7910 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7911 "XCHG EBX,ECX"
7912 %}
7913 ins_encode %{
7914 // Note: we need to swap rbx, and rcx before and after the
7915 // cmpxchg8 instruction because the instruction uses
7916 // rcx as the high order word of the new value to store but
7917 // our register encoding uses rbx.
7918 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7919 if( os::is_MP() )
7920 __ lock();
7921 __ cmpxchg8($mem$$Address);
7922 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7923 %}
7924 ins_pipe( pipe_cmpxchg );
7925 %}
7927 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7929 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7930 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7931 effect(KILL cr, KILL oldval);
7932 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7933 "MOV $res,0\n\t"
7934 "JNE,s fail\n\t"
7935 "MOV $res,1\n"
7936 "fail:" %}
7937 ins_encode( enc_cmpxchg8(mem_ptr),
7938 enc_flags_ne_to_boolean(res) );
7939 ins_pipe( pipe_cmpxchg );
7940 %}
7942 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7943 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7944 effect(KILL cr, KILL oldval);
7945 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7946 "MOV $res,0\n\t"
7947 "JNE,s fail\n\t"
7948 "MOV $res,1\n"
7949 "fail:" %}
7950 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7951 ins_pipe( pipe_cmpxchg );
7952 %}
7954 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7955 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7956 effect(KILL cr, KILL oldval);
7957 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7958 "MOV $res,0\n\t"
7959 "JNE,s fail\n\t"
7960 "MOV $res,1\n"
7961 "fail:" %}
7962 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7963 ins_pipe( pipe_cmpxchg );
7964 %}
7966 //----------Subtraction Instructions-------------------------------------------
7967 // Integer Subtraction Instructions
7968 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7969 match(Set dst (SubI dst src));
7970 effect(KILL cr);
7972 size(2);
7973 format %{ "SUB $dst,$src" %}
7974 opcode(0x2B);
7975 ins_encode( OpcP, RegReg( dst, src) );
7976 ins_pipe( ialu_reg_reg );
7977 %}
7979 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7980 match(Set dst (SubI dst src));
7981 effect(KILL cr);
7983 format %{ "SUB $dst,$src" %}
7984 opcode(0x81,0x05); /* Opcode 81 /5 */
7985 // ins_encode( RegImm( dst, src) );
7986 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7987 ins_pipe( ialu_reg );
7988 %}
7990 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7991 match(Set dst (SubI dst (LoadI src)));
7992 effect(KILL cr);
7994 ins_cost(125);
7995 format %{ "SUB $dst,$src" %}
7996 opcode(0x2B);
7997 ins_encode( OpcP, RegMem( dst, src) );
7998 ins_pipe( ialu_reg_mem );
7999 %}
8001 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8002 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8003 effect(KILL cr);
8005 ins_cost(150);
8006 format %{ "SUB $dst,$src" %}
8007 opcode(0x29); /* Opcode 29 /r */
8008 ins_encode( OpcP, RegMem( src, dst ) );
8009 ins_pipe( ialu_mem_reg );
8010 %}
8012 // Subtract from a pointer
8013 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8014 match(Set dst (AddP dst (SubI zero src)));
8015 effect(KILL cr);
8017 size(2);
8018 format %{ "SUB $dst,$src" %}
8019 opcode(0x2B);
8020 ins_encode( OpcP, RegReg( dst, src) );
8021 ins_pipe( ialu_reg_reg );
8022 %}
8024 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8025 match(Set dst (SubI zero dst));
8026 effect(KILL cr);
8028 size(2);
8029 format %{ "NEG $dst" %}
8030 opcode(0xF7,0x03); // Opcode F7 /3
8031 ins_encode( OpcP, RegOpc( dst ) );
8032 ins_pipe( ialu_reg );
8033 %}
8036 //----------Multiplication/Division Instructions-------------------------------
8037 // Integer Multiplication Instructions
8038 // Multiply Register
8039 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8040 match(Set dst (MulI dst src));
8041 effect(KILL cr);
8043 size(3);
8044 ins_cost(300);
8045 format %{ "IMUL $dst,$src" %}
8046 opcode(0xAF, 0x0F);
8047 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8048 ins_pipe( ialu_reg_reg_alu0 );
8049 %}
8051 // Multiply 32-bit Immediate
8052 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8053 match(Set dst (MulI src imm));
8054 effect(KILL cr);
8056 ins_cost(300);
8057 format %{ "IMUL $dst,$src,$imm" %}
8058 opcode(0x69); /* 69 /r id */
8059 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8060 ins_pipe( ialu_reg_reg_alu0 );
8061 %}
8063 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8064 match(Set dst src);
8065 effect(KILL cr);
8067 // Note that this is artificially increased to make it more expensive than loadConL
8068 ins_cost(250);
8069 format %{ "MOV EAX,$src\t// low word only" %}
8070 opcode(0xB8);
8071 ins_encode( LdImmL_Lo(dst, src) );
8072 ins_pipe( ialu_reg_fat );
8073 %}
8075 // Multiply by 32-bit Immediate, taking the shifted high order results
8076 // (special case for shift by 32)
8077 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8078 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8079 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8080 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8081 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8082 effect(USE src1, KILL cr);
8084 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8085 ins_cost(0*100 + 1*400 - 150);
8086 format %{ "IMUL EDX:EAX,$src1" %}
8087 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8088 ins_pipe( pipe_slow );
8089 %}
8091 // Multiply by 32-bit Immediate, taking the shifted high order results
8092 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8093 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8094 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8095 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8096 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8097 effect(USE src1, KILL cr);
8099 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8100 ins_cost(1*100 + 1*400 - 150);
8101 format %{ "IMUL EDX:EAX,$src1\n\t"
8102 "SAR EDX,$cnt-32" %}
8103 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8104 ins_pipe( pipe_slow );
8105 %}
8107 // Multiply Memory 32-bit Immediate
8108 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8109 match(Set dst (MulI (LoadI src) imm));
8110 effect(KILL cr);
8112 ins_cost(300);
8113 format %{ "IMUL $dst,$src,$imm" %}
8114 opcode(0x69); /* 69 /r id */
8115 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8116 ins_pipe( ialu_reg_mem_alu0 );
8117 %}
8119 // Multiply Memory
8120 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8121 match(Set dst (MulI dst (LoadI src)));
8122 effect(KILL cr);
8124 ins_cost(350);
8125 format %{ "IMUL $dst,$src" %}
8126 opcode(0xAF, 0x0F);
8127 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8128 ins_pipe( ialu_reg_mem_alu0 );
8129 %}
8131 // Multiply Register Int to Long
8132 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8133 // Basic Idea: long = (long)int * (long)int
8134 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8135 effect(DEF dst, USE src, USE src1, KILL flags);
8137 ins_cost(300);
8138 format %{ "IMUL $dst,$src1" %}
8140 ins_encode( long_int_multiply( dst, src1 ) );
8141 ins_pipe( ialu_reg_reg_alu0 );
8142 %}
8144 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8145 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8146 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8147 effect(KILL flags);
8149 ins_cost(300);
8150 format %{ "MUL $dst,$src1" %}
8152 ins_encode( long_uint_multiply(dst, src1) );
8153 ins_pipe( ialu_reg_reg_alu0 );
8154 %}
8156 // Multiply Register Long
8157 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8158 match(Set dst (MulL dst src));
8159 effect(KILL cr, TEMP tmp);
8160 ins_cost(4*100+3*400);
8161 // Basic idea: lo(result) = lo(x_lo * y_lo)
8162 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8163 format %{ "MOV $tmp,$src.lo\n\t"
8164 "IMUL $tmp,EDX\n\t"
8165 "MOV EDX,$src.hi\n\t"
8166 "IMUL EDX,EAX\n\t"
8167 "ADD $tmp,EDX\n\t"
8168 "MUL EDX:EAX,$src.lo\n\t"
8169 "ADD EDX,$tmp" %}
8170 ins_encode( long_multiply( dst, src, tmp ) );
8171 ins_pipe( pipe_slow );
8172 %}
8174 // Multiply Register Long where the left operand's high 32 bits are zero
8175 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8176 predicate(is_operand_hi32_zero(n->in(1)));
8177 match(Set dst (MulL dst src));
8178 effect(KILL cr, TEMP tmp);
8179 ins_cost(2*100+2*400);
8180 // Basic idea: lo(result) = lo(x_lo * y_lo)
8181 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8182 format %{ "MOV $tmp,$src.hi\n\t"
8183 "IMUL $tmp,EAX\n\t"
8184 "MUL EDX:EAX,$src.lo\n\t"
8185 "ADD EDX,$tmp" %}
8186 ins_encode %{
8187 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8188 __ imull($tmp$$Register, rax);
8189 __ mull($src$$Register);
8190 __ addl(rdx, $tmp$$Register);
8191 %}
8192 ins_pipe( pipe_slow );
8193 %}
8195 // Multiply Register Long where the right operand's high 32 bits are zero
8196 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8197 predicate(is_operand_hi32_zero(n->in(2)));
8198 match(Set dst (MulL dst src));
8199 effect(KILL cr, TEMP tmp);
8200 ins_cost(2*100+2*400);
8201 // Basic idea: lo(result) = lo(x_lo * y_lo)
8202 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8203 format %{ "MOV $tmp,$src.lo\n\t"
8204 "IMUL $tmp,EDX\n\t"
8205 "MUL EDX:EAX,$src.lo\n\t"
8206 "ADD EDX,$tmp" %}
8207 ins_encode %{
8208 __ movl($tmp$$Register, $src$$Register);
8209 __ imull($tmp$$Register, rdx);
8210 __ mull($src$$Register);
8211 __ addl(rdx, $tmp$$Register);
8212 %}
8213 ins_pipe( pipe_slow );
8214 %}
8216 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8217 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8218 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8219 match(Set dst (MulL dst src));
8220 effect(KILL cr);
8221 ins_cost(1*400);
8222 // Basic idea: lo(result) = lo(x_lo * y_lo)
8223 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8224 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8225 ins_encode %{
8226 __ mull($src$$Register);
8227 %}
8228 ins_pipe( pipe_slow );
8229 %}
8231 // Multiply Register Long by small constant
8232 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8233 match(Set dst (MulL dst src));
8234 effect(KILL cr, TEMP tmp);
8235 ins_cost(2*100+2*400);
8236 size(12);
8237 // Basic idea: lo(result) = lo(src * EAX)
8238 // hi(result) = hi(src * EAX) + lo(src * EDX)
8239 format %{ "IMUL $tmp,EDX,$src\n\t"
8240 "MOV EDX,$src\n\t"
8241 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8242 "ADD EDX,$tmp" %}
8243 ins_encode( long_multiply_con( dst, src, tmp ) );
8244 ins_pipe( pipe_slow );
8245 %}
8247 // Integer DIV with Register
8248 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8249 match(Set rax (DivI rax div));
8250 effect(KILL rdx, KILL cr);
8251 size(26);
8252 ins_cost(30*100+10*100);
8253 format %{ "CMP EAX,0x80000000\n\t"
8254 "JNE,s normal\n\t"
8255 "XOR EDX,EDX\n\t"
8256 "CMP ECX,-1\n\t"
8257 "JE,s done\n"
8258 "normal: CDQ\n\t"
8259 "IDIV $div\n\t"
8260 "done:" %}
8261 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8262 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8263 ins_pipe( ialu_reg_reg_alu0 );
8264 %}
8266 // Divide Register Long
8267 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8268 match(Set dst (DivL src1 src2));
8269 effect( KILL cr, KILL cx, KILL bx );
8270 ins_cost(10000);
8271 format %{ "PUSH $src1.hi\n\t"
8272 "PUSH $src1.lo\n\t"
8273 "PUSH $src2.hi\n\t"
8274 "PUSH $src2.lo\n\t"
8275 "CALL SharedRuntime::ldiv\n\t"
8276 "ADD ESP,16" %}
8277 ins_encode( long_div(src1,src2) );
8278 ins_pipe( pipe_slow );
8279 %}
8281 // Integer DIVMOD with Register, both quotient and mod results
8282 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8283 match(DivModI rax div);
8284 effect(KILL cr);
8285 size(26);
8286 ins_cost(30*100+10*100);
8287 format %{ "CMP EAX,0x80000000\n\t"
8288 "JNE,s normal\n\t"
8289 "XOR EDX,EDX\n\t"
8290 "CMP ECX,-1\n\t"
8291 "JE,s done\n"
8292 "normal: CDQ\n\t"
8293 "IDIV $div\n\t"
8294 "done:" %}
8295 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8296 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8297 ins_pipe( pipe_slow );
8298 %}
8300 // Integer MOD with Register
8301 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8302 match(Set rdx (ModI rax div));
8303 effect(KILL rax, KILL cr);
8305 size(26);
8306 ins_cost(300);
8307 format %{ "CDQ\n\t"
8308 "IDIV $div" %}
8309 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8310 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8311 ins_pipe( ialu_reg_reg_alu0 );
8312 %}
8314 // Remainder Register Long
8315 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8316 match(Set dst (ModL src1 src2));
8317 effect( KILL cr, KILL cx, KILL bx );
8318 ins_cost(10000);
8319 format %{ "PUSH $src1.hi\n\t"
8320 "PUSH $src1.lo\n\t"
8321 "PUSH $src2.hi\n\t"
8322 "PUSH $src2.lo\n\t"
8323 "CALL SharedRuntime::lrem\n\t"
8324 "ADD ESP,16" %}
8325 ins_encode( long_mod(src1,src2) );
8326 ins_pipe( pipe_slow );
8327 %}
8329 // Divide Register Long (no special case since divisor != -1)
8330 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8331 match(Set dst (DivL dst imm));
8332 effect( TEMP tmp, TEMP tmp2, KILL cr );
8333 ins_cost(1000);
8334 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8335 "XOR $tmp2,$tmp2\n\t"
8336 "CMP $tmp,EDX\n\t"
8337 "JA,s fast\n\t"
8338 "MOV $tmp2,EAX\n\t"
8339 "MOV EAX,EDX\n\t"
8340 "MOV EDX,0\n\t"
8341 "JLE,s pos\n\t"
8342 "LNEG EAX : $tmp2\n\t"
8343 "DIV $tmp # unsigned division\n\t"
8344 "XCHG EAX,$tmp2\n\t"
8345 "DIV $tmp\n\t"
8346 "LNEG $tmp2 : EAX\n\t"
8347 "JMP,s done\n"
8348 "pos:\n\t"
8349 "DIV $tmp\n\t"
8350 "XCHG EAX,$tmp2\n"
8351 "fast:\n\t"
8352 "DIV $tmp\n"
8353 "done:\n\t"
8354 "MOV EDX,$tmp2\n\t"
8355 "NEG EDX:EAX # if $imm < 0" %}
8356 ins_encode %{
8357 int con = (int)$imm$$constant;
8358 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8359 int pcon = (con > 0) ? con : -con;
8360 Label Lfast, Lpos, Ldone;
8362 __ movl($tmp$$Register, pcon);
8363 __ xorl($tmp2$$Register,$tmp2$$Register);
8364 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8365 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8367 __ movl($tmp2$$Register, $dst$$Register); // save
8368 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8369 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8370 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8372 // Negative dividend.
8373 // convert value to positive to use unsigned division
8374 __ lneg($dst$$Register, $tmp2$$Register);
8375 __ divl($tmp$$Register);
8376 __ xchgl($dst$$Register, $tmp2$$Register);
8377 __ divl($tmp$$Register);
8378 // revert result back to negative
8379 __ lneg($tmp2$$Register, $dst$$Register);
8380 __ jmpb(Ldone);
8382 __ bind(Lpos);
8383 __ divl($tmp$$Register); // Use unsigned division
8384 __ xchgl($dst$$Register, $tmp2$$Register);
8385 // Fallthrow for final divide, tmp2 has 32 bit hi result
8387 __ bind(Lfast);
8388 // fast path: src is positive
8389 __ divl($tmp$$Register); // Use unsigned division
8391 __ bind(Ldone);
8392 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8393 if (con < 0) {
8394 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8395 }
8396 %}
8397 ins_pipe( pipe_slow );
8398 %}
8400 // Remainder Register Long (remainder fit into 32 bits)
8401 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8402 match(Set dst (ModL dst imm));
8403 effect( TEMP tmp, TEMP tmp2, KILL cr );
8404 ins_cost(1000);
8405 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8406 "CMP $tmp,EDX\n\t"
8407 "JA,s fast\n\t"
8408 "MOV $tmp2,EAX\n\t"
8409 "MOV EAX,EDX\n\t"
8410 "MOV EDX,0\n\t"
8411 "JLE,s pos\n\t"
8412 "LNEG EAX : $tmp2\n\t"
8413 "DIV $tmp # unsigned division\n\t"
8414 "MOV EAX,$tmp2\n\t"
8415 "DIV $tmp\n\t"
8416 "NEG EDX\n\t"
8417 "JMP,s done\n"
8418 "pos:\n\t"
8419 "DIV $tmp\n\t"
8420 "MOV EAX,$tmp2\n"
8421 "fast:\n\t"
8422 "DIV $tmp\n"
8423 "done:\n\t"
8424 "MOV EAX,EDX\n\t"
8425 "SAR EDX,31\n\t" %}
8426 ins_encode %{
8427 int con = (int)$imm$$constant;
8428 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8429 int pcon = (con > 0) ? con : -con;
8430 Label Lfast, Lpos, Ldone;
8432 __ movl($tmp$$Register, pcon);
8433 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8434 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8436 __ movl($tmp2$$Register, $dst$$Register); // save
8437 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8438 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8439 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8441 // Negative dividend.
8442 // convert value to positive to use unsigned division
8443 __ lneg($dst$$Register, $tmp2$$Register);
8444 __ divl($tmp$$Register);
8445 __ movl($dst$$Register, $tmp2$$Register);
8446 __ divl($tmp$$Register);
8447 // revert remainder back to negative
8448 __ negl(HIGH_FROM_LOW($dst$$Register));
8449 __ jmpb(Ldone);
8451 __ bind(Lpos);
8452 __ divl($tmp$$Register);
8453 __ movl($dst$$Register, $tmp2$$Register);
8455 __ bind(Lfast);
8456 // fast path: src is positive
8457 __ divl($tmp$$Register);
8459 __ bind(Ldone);
8460 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8461 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8463 %}
8464 ins_pipe( pipe_slow );
8465 %}
8467 // Integer Shift Instructions
8468 // Shift Left by one
8469 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8470 match(Set dst (LShiftI dst shift));
8471 effect(KILL cr);
8473 size(2);
8474 format %{ "SHL $dst,$shift" %}
8475 opcode(0xD1, 0x4); /* D1 /4 */
8476 ins_encode( OpcP, RegOpc( dst ) );
8477 ins_pipe( ialu_reg );
8478 %}
8480 // Shift Left by 8-bit immediate
8481 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8482 match(Set dst (LShiftI dst shift));
8483 effect(KILL cr);
8485 size(3);
8486 format %{ "SHL $dst,$shift" %}
8487 opcode(0xC1, 0x4); /* C1 /4 ib */
8488 ins_encode( RegOpcImm( dst, shift) );
8489 ins_pipe( ialu_reg );
8490 %}
8492 // Shift Left by variable
8493 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8494 match(Set dst (LShiftI dst shift));
8495 effect(KILL cr);
8497 size(2);
8498 format %{ "SHL $dst,$shift" %}
8499 opcode(0xD3, 0x4); /* D3 /4 */
8500 ins_encode( OpcP, RegOpc( dst ) );
8501 ins_pipe( ialu_reg_reg );
8502 %}
8504 // Arithmetic shift right by one
8505 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8506 match(Set dst (RShiftI dst shift));
8507 effect(KILL cr);
8509 size(2);
8510 format %{ "SAR $dst,$shift" %}
8511 opcode(0xD1, 0x7); /* D1 /7 */
8512 ins_encode( OpcP, RegOpc( dst ) );
8513 ins_pipe( ialu_reg );
8514 %}
8516 // Arithmetic shift right by one
8517 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8518 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8519 effect(KILL cr);
8520 format %{ "SAR $dst,$shift" %}
8521 opcode(0xD1, 0x7); /* D1 /7 */
8522 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8523 ins_pipe( ialu_mem_imm );
8524 %}
8526 // Arithmetic Shift Right by 8-bit immediate
8527 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8528 match(Set dst (RShiftI dst shift));
8529 effect(KILL cr);
8531 size(3);
8532 format %{ "SAR $dst,$shift" %}
8533 opcode(0xC1, 0x7); /* C1 /7 ib */
8534 ins_encode( RegOpcImm( dst, shift ) );
8535 ins_pipe( ialu_mem_imm );
8536 %}
8538 // Arithmetic Shift Right by 8-bit immediate
8539 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8540 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8541 effect(KILL cr);
8543 format %{ "SAR $dst,$shift" %}
8544 opcode(0xC1, 0x7); /* C1 /7 ib */
8545 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8546 ins_pipe( ialu_mem_imm );
8547 %}
8549 // Arithmetic Shift Right by variable
8550 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8551 match(Set dst (RShiftI dst shift));
8552 effect(KILL cr);
8554 size(2);
8555 format %{ "SAR $dst,$shift" %}
8556 opcode(0xD3, 0x7); /* D3 /7 */
8557 ins_encode( OpcP, RegOpc( dst ) );
8558 ins_pipe( ialu_reg_reg );
8559 %}
8561 // Logical shift right by one
8562 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8563 match(Set dst (URShiftI dst shift));
8564 effect(KILL cr);
8566 size(2);
8567 format %{ "SHR $dst,$shift" %}
8568 opcode(0xD1, 0x5); /* D1 /5 */
8569 ins_encode( OpcP, RegOpc( dst ) );
8570 ins_pipe( ialu_reg );
8571 %}
8573 // Logical Shift Right by 8-bit immediate
8574 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8575 match(Set dst (URShiftI dst shift));
8576 effect(KILL cr);
8578 size(3);
8579 format %{ "SHR $dst,$shift" %}
8580 opcode(0xC1, 0x5); /* C1 /5 ib */
8581 ins_encode( RegOpcImm( dst, shift) );
8582 ins_pipe( ialu_reg );
8583 %}
8586 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8587 // This idiom is used by the compiler for the i2b bytecode.
8588 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8589 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8591 size(3);
8592 format %{ "MOVSX $dst,$src :8" %}
8593 ins_encode %{
8594 __ movsbl($dst$$Register, $src$$Register);
8595 %}
8596 ins_pipe(ialu_reg_reg);
8597 %}
8599 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8600 // This idiom is used by the compiler the i2s bytecode.
8601 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8602 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8604 size(3);
8605 format %{ "MOVSX $dst,$src :16" %}
8606 ins_encode %{
8607 __ movswl($dst$$Register, $src$$Register);
8608 %}
8609 ins_pipe(ialu_reg_reg);
8610 %}
8613 // Logical Shift Right by variable
8614 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8615 match(Set dst (URShiftI dst shift));
8616 effect(KILL cr);
8618 size(2);
8619 format %{ "SHR $dst,$shift" %}
8620 opcode(0xD3, 0x5); /* D3 /5 */
8621 ins_encode( OpcP, RegOpc( dst ) );
8622 ins_pipe( ialu_reg_reg );
8623 %}
8626 //----------Logical Instructions-----------------------------------------------
8627 //----------Integer Logical Instructions---------------------------------------
8628 // And Instructions
8629 // And Register with Register
8630 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8631 match(Set dst (AndI dst src));
8632 effect(KILL cr);
8634 size(2);
8635 format %{ "AND $dst,$src" %}
8636 opcode(0x23);
8637 ins_encode( OpcP, RegReg( dst, src) );
8638 ins_pipe( ialu_reg_reg );
8639 %}
8641 // And Register with Immediate
8642 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8643 match(Set dst (AndI dst src));
8644 effect(KILL cr);
8646 format %{ "AND $dst,$src" %}
8647 opcode(0x81,0x04); /* Opcode 81 /4 */
8648 // ins_encode( RegImm( dst, src) );
8649 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8650 ins_pipe( ialu_reg );
8651 %}
8653 // And Register with Memory
8654 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8655 match(Set dst (AndI dst (LoadI src)));
8656 effect(KILL cr);
8658 ins_cost(125);
8659 format %{ "AND $dst,$src" %}
8660 opcode(0x23);
8661 ins_encode( OpcP, RegMem( dst, src) );
8662 ins_pipe( ialu_reg_mem );
8663 %}
8665 // And Memory with Register
8666 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8667 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8668 effect(KILL cr);
8670 ins_cost(150);
8671 format %{ "AND $dst,$src" %}
8672 opcode(0x21); /* Opcode 21 /r */
8673 ins_encode( OpcP, RegMem( src, dst ) );
8674 ins_pipe( ialu_mem_reg );
8675 %}
8677 // And Memory with Immediate
8678 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8679 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8680 effect(KILL cr);
8682 ins_cost(125);
8683 format %{ "AND $dst,$src" %}
8684 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8685 // ins_encode( MemImm( dst, src) );
8686 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8687 ins_pipe( ialu_mem_imm );
8688 %}
8690 // Or Instructions
8691 // Or Register with Register
8692 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8693 match(Set dst (OrI dst src));
8694 effect(KILL cr);
8696 size(2);
8697 format %{ "OR $dst,$src" %}
8698 opcode(0x0B);
8699 ins_encode( OpcP, RegReg( dst, src) );
8700 ins_pipe( ialu_reg_reg );
8701 %}
8703 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8704 match(Set dst (OrI dst (CastP2X src)));
8705 effect(KILL cr);
8707 size(2);
8708 format %{ "OR $dst,$src" %}
8709 opcode(0x0B);
8710 ins_encode( OpcP, RegReg( dst, src) );
8711 ins_pipe( ialu_reg_reg );
8712 %}
8715 // Or Register with Immediate
8716 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8717 match(Set dst (OrI dst src));
8718 effect(KILL cr);
8720 format %{ "OR $dst,$src" %}
8721 opcode(0x81,0x01); /* Opcode 81 /1 id */
8722 // ins_encode( RegImm( dst, src) );
8723 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8724 ins_pipe( ialu_reg );
8725 %}
8727 // Or Register with Memory
8728 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8729 match(Set dst (OrI dst (LoadI src)));
8730 effect(KILL cr);
8732 ins_cost(125);
8733 format %{ "OR $dst,$src" %}
8734 opcode(0x0B);
8735 ins_encode( OpcP, RegMem( dst, src) );
8736 ins_pipe( ialu_reg_mem );
8737 %}
8739 // Or Memory with Register
8740 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8741 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8742 effect(KILL cr);
8744 ins_cost(150);
8745 format %{ "OR $dst,$src" %}
8746 opcode(0x09); /* Opcode 09 /r */
8747 ins_encode( OpcP, RegMem( src, dst ) );
8748 ins_pipe( ialu_mem_reg );
8749 %}
8751 // Or Memory with Immediate
8752 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8753 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8754 effect(KILL cr);
8756 ins_cost(125);
8757 format %{ "OR $dst,$src" %}
8758 opcode(0x81,0x1); /* Opcode 81 /1 id */
8759 // ins_encode( MemImm( dst, src) );
8760 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8761 ins_pipe( ialu_mem_imm );
8762 %}
8764 // ROL/ROR
8765 // ROL expand
8766 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8767 effect(USE_DEF dst, USE shift, KILL cr);
8769 format %{ "ROL $dst, $shift" %}
8770 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8771 ins_encode( OpcP, RegOpc( dst ));
8772 ins_pipe( ialu_reg );
8773 %}
8775 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8776 effect(USE_DEF dst, USE shift, KILL cr);
8778 format %{ "ROL $dst, $shift" %}
8779 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8780 ins_encode( RegOpcImm(dst, shift) );
8781 ins_pipe(ialu_reg);
8782 %}
8784 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8785 effect(USE_DEF dst, USE shift, KILL cr);
8787 format %{ "ROL $dst, $shift" %}
8788 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8789 ins_encode(OpcP, RegOpc(dst));
8790 ins_pipe( ialu_reg_reg );
8791 %}
8792 // end of ROL expand
8794 // ROL 32bit by one once
8795 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8796 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8798 expand %{
8799 rolI_eReg_imm1(dst, lshift, cr);
8800 %}
8801 %}
8803 // ROL 32bit var by imm8 once
8804 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8805 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8806 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8808 expand %{
8809 rolI_eReg_imm8(dst, lshift, cr);
8810 %}
8811 %}
8813 // ROL 32bit var by var once
8814 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8815 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8817 expand %{
8818 rolI_eReg_CL(dst, shift, cr);
8819 %}
8820 %}
8822 // ROL 32bit var by var once
8823 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8824 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8826 expand %{
8827 rolI_eReg_CL(dst, shift, cr);
8828 %}
8829 %}
8831 // ROR expand
8832 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8833 effect(USE_DEF dst, USE shift, KILL cr);
8835 format %{ "ROR $dst, $shift" %}
8836 opcode(0xD1,0x1); /* Opcode D1 /1 */
8837 ins_encode( OpcP, RegOpc( dst ) );
8838 ins_pipe( ialu_reg );
8839 %}
8841 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8842 effect (USE_DEF dst, USE shift, KILL cr);
8844 format %{ "ROR $dst, $shift" %}
8845 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8846 ins_encode( RegOpcImm(dst, shift) );
8847 ins_pipe( ialu_reg );
8848 %}
8850 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8851 effect(USE_DEF dst, USE shift, KILL cr);
8853 format %{ "ROR $dst, $shift" %}
8854 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8855 ins_encode(OpcP, RegOpc(dst));
8856 ins_pipe( ialu_reg_reg );
8857 %}
8858 // end of ROR expand
8860 // ROR right once
8861 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8862 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8864 expand %{
8865 rorI_eReg_imm1(dst, rshift, cr);
8866 %}
8867 %}
8869 // ROR 32bit by immI8 once
8870 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8871 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8872 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8874 expand %{
8875 rorI_eReg_imm8(dst, rshift, cr);
8876 %}
8877 %}
8879 // ROR 32bit var by var once
8880 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8881 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8883 expand %{
8884 rorI_eReg_CL(dst, shift, cr);
8885 %}
8886 %}
8888 // ROR 32bit var by var once
8889 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8890 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8892 expand %{
8893 rorI_eReg_CL(dst, shift, cr);
8894 %}
8895 %}
8897 // Xor Instructions
8898 // Xor Register with Register
8899 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8900 match(Set dst (XorI dst src));
8901 effect(KILL cr);
8903 size(2);
8904 format %{ "XOR $dst,$src" %}
8905 opcode(0x33);
8906 ins_encode( OpcP, RegReg( dst, src) );
8907 ins_pipe( ialu_reg_reg );
8908 %}
8910 // Xor Register with Immediate -1
8911 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
8912 match(Set dst (XorI dst imm));
8914 size(2);
8915 format %{ "NOT $dst" %}
8916 ins_encode %{
8917 __ notl($dst$$Register);
8918 %}
8919 ins_pipe( ialu_reg );
8920 %}
8922 // Xor Register with Immediate
8923 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8924 match(Set dst (XorI dst src));
8925 effect(KILL cr);
8927 format %{ "XOR $dst,$src" %}
8928 opcode(0x81,0x06); /* Opcode 81 /6 id */
8929 // ins_encode( RegImm( dst, src) );
8930 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8931 ins_pipe( ialu_reg );
8932 %}
8934 // Xor Register with Memory
8935 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8936 match(Set dst (XorI dst (LoadI src)));
8937 effect(KILL cr);
8939 ins_cost(125);
8940 format %{ "XOR $dst,$src" %}
8941 opcode(0x33);
8942 ins_encode( OpcP, RegMem(dst, src) );
8943 ins_pipe( ialu_reg_mem );
8944 %}
8946 // Xor Memory with Register
8947 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8948 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8949 effect(KILL cr);
8951 ins_cost(150);
8952 format %{ "XOR $dst,$src" %}
8953 opcode(0x31); /* Opcode 31 /r */
8954 ins_encode( OpcP, RegMem( src, dst ) );
8955 ins_pipe( ialu_mem_reg );
8956 %}
8958 // Xor Memory with Immediate
8959 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8960 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8961 effect(KILL cr);
8963 ins_cost(125);
8964 format %{ "XOR $dst,$src" %}
8965 opcode(0x81,0x6); /* Opcode 81 /6 id */
8966 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8967 ins_pipe( ialu_mem_imm );
8968 %}
8970 //----------Convert Int to Boolean---------------------------------------------
8972 instruct movI_nocopy(eRegI dst, eRegI src) %{
8973 effect( DEF dst, USE src );
8974 format %{ "MOV $dst,$src" %}
8975 ins_encode( enc_Copy( dst, src) );
8976 ins_pipe( ialu_reg_reg );
8977 %}
8979 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
8980 effect( USE_DEF dst, USE src, KILL cr );
8982 size(4);
8983 format %{ "NEG $dst\n\t"
8984 "ADC $dst,$src" %}
8985 ins_encode( neg_reg(dst),
8986 OpcRegReg(0x13,dst,src) );
8987 ins_pipe( ialu_reg_reg_long );
8988 %}
8990 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
8991 match(Set dst (Conv2B src));
8993 expand %{
8994 movI_nocopy(dst,src);
8995 ci2b(dst,src,cr);
8996 %}
8997 %}
8999 instruct movP_nocopy(eRegI dst, eRegP src) %{
9000 effect( DEF dst, USE src );
9001 format %{ "MOV $dst,$src" %}
9002 ins_encode( enc_Copy( dst, src) );
9003 ins_pipe( ialu_reg_reg );
9004 %}
9006 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9007 effect( USE_DEF dst, USE src, KILL cr );
9008 format %{ "NEG $dst\n\t"
9009 "ADC $dst,$src" %}
9010 ins_encode( neg_reg(dst),
9011 OpcRegReg(0x13,dst,src) );
9012 ins_pipe( ialu_reg_reg_long );
9013 %}
9015 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9016 match(Set dst (Conv2B src));
9018 expand %{
9019 movP_nocopy(dst,src);
9020 cp2b(dst,src,cr);
9021 %}
9022 %}
9024 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9025 match(Set dst (CmpLTMask p q));
9026 effect( KILL cr );
9027 ins_cost(400);
9029 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9030 format %{ "XOR $dst,$dst\n\t"
9031 "CMP $p,$q\n\t"
9032 "SETlt $dst\n\t"
9033 "NEG $dst" %}
9034 ins_encode( OpcRegReg(0x33,dst,dst),
9035 OpcRegReg(0x3B,p,q),
9036 setLT_reg(dst), neg_reg(dst) );
9037 ins_pipe( pipe_slow );
9038 %}
9040 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9041 match(Set dst (CmpLTMask dst zero));
9042 effect( DEF dst, KILL cr );
9043 ins_cost(100);
9045 format %{ "SAR $dst,31" %}
9046 opcode(0xC1, 0x7); /* C1 /7 ib */
9047 ins_encode( RegOpcImm( dst, 0x1F ) );
9048 ins_pipe( ialu_reg );
9049 %}
9052 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9053 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9054 effect( KILL tmp, KILL cr );
9055 ins_cost(400);
9056 // annoyingly, $tmp has no edges so you cant ask for it in
9057 // any format or encoding
9058 format %{ "SUB $p,$q\n\t"
9059 "SBB ECX,ECX\n\t"
9060 "AND ECX,$y\n\t"
9061 "ADD $p,ECX" %}
9062 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9063 ins_pipe( pipe_cmplt );
9064 %}
9066 /* If I enable this, I encourage spilling in the inner loop of compress.
9067 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9068 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9069 effect( USE_KILL tmp, KILL cr );
9070 ins_cost(400);
9072 format %{ "SUB $p,$q\n\t"
9073 "SBB ECX,ECX\n\t"
9074 "AND ECX,$y\n\t"
9075 "ADD $p,ECX" %}
9076 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9077 %}
9078 */
9080 //----------Long Instructions------------------------------------------------
9081 // Add Long Register with Register
9082 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9083 match(Set dst (AddL dst src));
9084 effect(KILL cr);
9085 ins_cost(200);
9086 format %{ "ADD $dst.lo,$src.lo\n\t"
9087 "ADC $dst.hi,$src.hi" %}
9088 opcode(0x03, 0x13);
9089 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9090 ins_pipe( ialu_reg_reg_long );
9091 %}
9093 // Add Long Register with Immediate
9094 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9095 match(Set dst (AddL dst src));
9096 effect(KILL cr);
9097 format %{ "ADD $dst.lo,$src.lo\n\t"
9098 "ADC $dst.hi,$src.hi" %}
9099 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9100 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9101 ins_pipe( ialu_reg_long );
9102 %}
9104 // Add Long Register with Memory
9105 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9106 match(Set dst (AddL dst (LoadL mem)));
9107 effect(KILL cr);
9108 ins_cost(125);
9109 format %{ "ADD $dst.lo,$mem\n\t"
9110 "ADC $dst.hi,$mem+4" %}
9111 opcode(0x03, 0x13);
9112 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9113 ins_pipe( ialu_reg_long_mem );
9114 %}
9116 // Subtract Long Register with Register.
9117 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9118 match(Set dst (SubL dst src));
9119 effect(KILL cr);
9120 ins_cost(200);
9121 format %{ "SUB $dst.lo,$src.lo\n\t"
9122 "SBB $dst.hi,$src.hi" %}
9123 opcode(0x2B, 0x1B);
9124 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9125 ins_pipe( ialu_reg_reg_long );
9126 %}
9128 // Subtract Long Register with Immediate
9129 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9130 match(Set dst (SubL dst src));
9131 effect(KILL cr);
9132 format %{ "SUB $dst.lo,$src.lo\n\t"
9133 "SBB $dst.hi,$src.hi" %}
9134 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9135 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9136 ins_pipe( ialu_reg_long );
9137 %}
9139 // Subtract Long Register with Memory
9140 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9141 match(Set dst (SubL dst (LoadL mem)));
9142 effect(KILL cr);
9143 ins_cost(125);
9144 format %{ "SUB $dst.lo,$mem\n\t"
9145 "SBB $dst.hi,$mem+4" %}
9146 opcode(0x2B, 0x1B);
9147 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9148 ins_pipe( ialu_reg_long_mem );
9149 %}
9151 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9152 match(Set dst (SubL zero dst));
9153 effect(KILL cr);
9154 ins_cost(300);
9155 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9156 ins_encode( neg_long(dst) );
9157 ins_pipe( ialu_reg_reg_long );
9158 %}
9160 // And Long Register with Register
9161 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9162 match(Set dst (AndL dst src));
9163 effect(KILL cr);
9164 format %{ "AND $dst.lo,$src.lo\n\t"
9165 "AND $dst.hi,$src.hi" %}
9166 opcode(0x23,0x23);
9167 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9168 ins_pipe( ialu_reg_reg_long );
9169 %}
9171 // And Long Register with Immediate
9172 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9173 match(Set dst (AndL dst src));
9174 effect(KILL cr);
9175 format %{ "AND $dst.lo,$src.lo\n\t"
9176 "AND $dst.hi,$src.hi" %}
9177 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9178 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9179 ins_pipe( ialu_reg_long );
9180 %}
9182 // And Long Register with Memory
9183 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9184 match(Set dst (AndL dst (LoadL mem)));
9185 effect(KILL cr);
9186 ins_cost(125);
9187 format %{ "AND $dst.lo,$mem\n\t"
9188 "AND $dst.hi,$mem+4" %}
9189 opcode(0x23, 0x23);
9190 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9191 ins_pipe( ialu_reg_long_mem );
9192 %}
9194 // Or Long Register with Register
9195 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9196 match(Set dst (OrL dst src));
9197 effect(KILL cr);
9198 format %{ "OR $dst.lo,$src.lo\n\t"
9199 "OR $dst.hi,$src.hi" %}
9200 opcode(0x0B,0x0B);
9201 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9202 ins_pipe( ialu_reg_reg_long );
9203 %}
9205 // Or Long Register with Immediate
9206 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9207 match(Set dst (OrL dst src));
9208 effect(KILL cr);
9209 format %{ "OR $dst.lo,$src.lo\n\t"
9210 "OR $dst.hi,$src.hi" %}
9211 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9212 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9213 ins_pipe( ialu_reg_long );
9214 %}
9216 // Or Long Register with Memory
9217 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9218 match(Set dst (OrL dst (LoadL mem)));
9219 effect(KILL cr);
9220 ins_cost(125);
9221 format %{ "OR $dst.lo,$mem\n\t"
9222 "OR $dst.hi,$mem+4" %}
9223 opcode(0x0B,0x0B);
9224 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9225 ins_pipe( ialu_reg_long_mem );
9226 %}
9228 // Xor Long Register with Register
9229 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9230 match(Set dst (XorL dst src));
9231 effect(KILL cr);
9232 format %{ "XOR $dst.lo,$src.lo\n\t"
9233 "XOR $dst.hi,$src.hi" %}
9234 opcode(0x33,0x33);
9235 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9236 ins_pipe( ialu_reg_reg_long );
9237 %}
9239 // Xor Long Register with Immediate -1
9240 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9241 match(Set dst (XorL dst imm));
9242 format %{ "NOT $dst.lo\n\t"
9243 "NOT $dst.hi" %}
9244 ins_encode %{
9245 __ notl($dst$$Register);
9246 __ notl(HIGH_FROM_LOW($dst$$Register));
9247 %}
9248 ins_pipe( ialu_reg_long );
9249 %}
9251 // Xor Long Register with Immediate
9252 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9253 match(Set dst (XorL dst src));
9254 effect(KILL cr);
9255 format %{ "XOR $dst.lo,$src.lo\n\t"
9256 "XOR $dst.hi,$src.hi" %}
9257 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9258 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9259 ins_pipe( ialu_reg_long );
9260 %}
9262 // Xor Long Register with Memory
9263 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9264 match(Set dst (XorL dst (LoadL mem)));
9265 effect(KILL cr);
9266 ins_cost(125);
9267 format %{ "XOR $dst.lo,$mem\n\t"
9268 "XOR $dst.hi,$mem+4" %}
9269 opcode(0x33,0x33);
9270 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9271 ins_pipe( ialu_reg_long_mem );
9272 %}
9274 // Shift Left Long by 1
9275 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9276 predicate(UseNewLongLShift);
9277 match(Set dst (LShiftL dst cnt));
9278 effect(KILL cr);
9279 ins_cost(100);
9280 format %{ "ADD $dst.lo,$dst.lo\n\t"
9281 "ADC $dst.hi,$dst.hi" %}
9282 ins_encode %{
9283 __ addl($dst$$Register,$dst$$Register);
9284 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9285 %}
9286 ins_pipe( ialu_reg_long );
9287 %}
9289 // Shift Left Long by 2
9290 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9291 predicate(UseNewLongLShift);
9292 match(Set dst (LShiftL dst cnt));
9293 effect(KILL cr);
9294 ins_cost(100);
9295 format %{ "ADD $dst.lo,$dst.lo\n\t"
9296 "ADC $dst.hi,$dst.hi\n\t"
9297 "ADD $dst.lo,$dst.lo\n\t"
9298 "ADC $dst.hi,$dst.hi" %}
9299 ins_encode %{
9300 __ addl($dst$$Register,$dst$$Register);
9301 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9302 __ addl($dst$$Register,$dst$$Register);
9303 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9304 %}
9305 ins_pipe( ialu_reg_long );
9306 %}
9308 // Shift Left Long by 3
9309 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9310 predicate(UseNewLongLShift);
9311 match(Set dst (LShiftL dst cnt));
9312 effect(KILL cr);
9313 ins_cost(100);
9314 format %{ "ADD $dst.lo,$dst.lo\n\t"
9315 "ADC $dst.hi,$dst.hi\n\t"
9316 "ADD $dst.lo,$dst.lo\n\t"
9317 "ADC $dst.hi,$dst.hi\n\t"
9318 "ADD $dst.lo,$dst.lo\n\t"
9319 "ADC $dst.hi,$dst.hi" %}
9320 ins_encode %{
9321 __ addl($dst$$Register,$dst$$Register);
9322 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9323 __ addl($dst$$Register,$dst$$Register);
9324 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9325 __ addl($dst$$Register,$dst$$Register);
9326 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9327 %}
9328 ins_pipe( ialu_reg_long );
9329 %}
9331 // Shift Left Long by 1-31
9332 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9333 match(Set dst (LShiftL dst cnt));
9334 effect(KILL cr);
9335 ins_cost(200);
9336 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9337 "SHL $dst.lo,$cnt" %}
9338 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9339 ins_encode( move_long_small_shift(dst,cnt) );
9340 ins_pipe( ialu_reg_long );
9341 %}
9343 // Shift Left Long by 32-63
9344 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9345 match(Set dst (LShiftL dst cnt));
9346 effect(KILL cr);
9347 ins_cost(300);
9348 format %{ "MOV $dst.hi,$dst.lo\n"
9349 "\tSHL $dst.hi,$cnt-32\n"
9350 "\tXOR $dst.lo,$dst.lo" %}
9351 opcode(0xC1, 0x4); /* C1 /4 ib */
9352 ins_encode( move_long_big_shift_clr(dst,cnt) );
9353 ins_pipe( ialu_reg_long );
9354 %}
9356 // Shift Left Long by variable
9357 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9358 match(Set dst (LShiftL dst shift));
9359 effect(KILL cr);
9360 ins_cost(500+200);
9361 size(17);
9362 format %{ "TEST $shift,32\n\t"
9363 "JEQ,s small\n\t"
9364 "MOV $dst.hi,$dst.lo\n\t"
9365 "XOR $dst.lo,$dst.lo\n"
9366 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9367 "SHL $dst.lo,$shift" %}
9368 ins_encode( shift_left_long( dst, shift ) );
9369 ins_pipe( pipe_slow );
9370 %}
9372 // Shift Right Long by 1-31
9373 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9374 match(Set dst (URShiftL dst cnt));
9375 effect(KILL cr);
9376 ins_cost(200);
9377 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9378 "SHR $dst.hi,$cnt" %}
9379 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9380 ins_encode( move_long_small_shift(dst,cnt) );
9381 ins_pipe( ialu_reg_long );
9382 %}
9384 // Shift Right Long by 32-63
9385 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9386 match(Set dst (URShiftL dst cnt));
9387 effect(KILL cr);
9388 ins_cost(300);
9389 format %{ "MOV $dst.lo,$dst.hi\n"
9390 "\tSHR $dst.lo,$cnt-32\n"
9391 "\tXOR $dst.hi,$dst.hi" %}
9392 opcode(0xC1, 0x5); /* C1 /5 ib */
9393 ins_encode( move_long_big_shift_clr(dst,cnt) );
9394 ins_pipe( ialu_reg_long );
9395 %}
9397 // Shift Right Long by variable
9398 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9399 match(Set dst (URShiftL dst shift));
9400 effect(KILL cr);
9401 ins_cost(600);
9402 size(17);
9403 format %{ "TEST $shift,32\n\t"
9404 "JEQ,s small\n\t"
9405 "MOV $dst.lo,$dst.hi\n\t"
9406 "XOR $dst.hi,$dst.hi\n"
9407 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9408 "SHR $dst.hi,$shift" %}
9409 ins_encode( shift_right_long( dst, shift ) );
9410 ins_pipe( pipe_slow );
9411 %}
9413 // Shift Right Long by 1-31
9414 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9415 match(Set dst (RShiftL dst cnt));
9416 effect(KILL cr);
9417 ins_cost(200);
9418 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9419 "SAR $dst.hi,$cnt" %}
9420 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9421 ins_encode( move_long_small_shift(dst,cnt) );
9422 ins_pipe( ialu_reg_long );
9423 %}
9425 // Shift Right Long by 32-63
9426 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9427 match(Set dst (RShiftL dst cnt));
9428 effect(KILL cr);
9429 ins_cost(300);
9430 format %{ "MOV $dst.lo,$dst.hi\n"
9431 "\tSAR $dst.lo,$cnt-32\n"
9432 "\tSAR $dst.hi,31" %}
9433 opcode(0xC1, 0x7); /* C1 /7 ib */
9434 ins_encode( move_long_big_shift_sign(dst,cnt) );
9435 ins_pipe( ialu_reg_long );
9436 %}
9438 // Shift Right arithmetic Long by variable
9439 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9440 match(Set dst (RShiftL dst shift));
9441 effect(KILL cr);
9442 ins_cost(600);
9443 size(18);
9444 format %{ "TEST $shift,32\n\t"
9445 "JEQ,s small\n\t"
9446 "MOV $dst.lo,$dst.hi\n\t"
9447 "SAR $dst.hi,31\n"
9448 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9449 "SAR $dst.hi,$shift" %}
9450 ins_encode( shift_right_arith_long( dst, shift ) );
9451 ins_pipe( pipe_slow );
9452 %}
9455 //----------Double Instructions------------------------------------------------
9456 // Double Math
9458 // Compare & branch
9460 // P6 version of float compare, sets condition codes in EFLAGS
9461 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9462 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9463 match(Set cr (CmpD src1 src2));
9464 effect(KILL rax);
9465 ins_cost(150);
9466 format %{ "FLD $src1\n\t"
9467 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9468 "JNP exit\n\t"
9469 "MOV ah,1 // saw a NaN, set CF\n\t"
9470 "SAHF\n"
9471 "exit:\tNOP // avoid branch to branch" %}
9472 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9473 ins_encode( Push_Reg_DPR(src1),
9474 OpcP, RegOpc(src2),
9475 cmpF_P6_fixup );
9476 ins_pipe( pipe_slow );
9477 %}
9479 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9480 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9481 match(Set cr (CmpD src1 src2));
9482 ins_cost(150);
9483 format %{ "FLD $src1\n\t"
9484 "FUCOMIP ST,$src2 // P6 instruction" %}
9485 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9486 ins_encode( Push_Reg_DPR(src1),
9487 OpcP, RegOpc(src2));
9488 ins_pipe( pipe_slow );
9489 %}
9491 // Compare & branch
9492 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9493 predicate(UseSSE<=1);
9494 match(Set cr (CmpD src1 src2));
9495 effect(KILL rax);
9496 ins_cost(200);
9497 format %{ "FLD $src1\n\t"
9498 "FCOMp $src2\n\t"
9499 "FNSTSW AX\n\t"
9500 "TEST AX,0x400\n\t"
9501 "JZ,s flags\n\t"
9502 "MOV AH,1\t# unordered treat as LT\n"
9503 "flags:\tSAHF" %}
9504 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9505 ins_encode( Push_Reg_DPR(src1),
9506 OpcP, RegOpc(src2),
9507 fpu_flags);
9508 ins_pipe( pipe_slow );
9509 %}
9511 // Compare vs zero into -1,0,1
9512 instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9513 predicate(UseSSE<=1);
9514 match(Set dst (CmpD3 src1 zero));
9515 effect(KILL cr, KILL rax);
9516 ins_cost(280);
9517 format %{ "FTSTD $dst,$src1" %}
9518 opcode(0xE4, 0xD9);
9519 ins_encode( Push_Reg_DPR(src1),
9520 OpcS, OpcP, PopFPU,
9521 CmpF_Result(dst));
9522 ins_pipe( pipe_slow );
9523 %}
9525 // Compare into -1,0,1
9526 instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9527 predicate(UseSSE<=1);
9528 match(Set dst (CmpD3 src1 src2));
9529 effect(KILL cr, KILL rax);
9530 ins_cost(300);
9531 format %{ "FCMPD $dst,$src1,$src2" %}
9532 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9533 ins_encode( Push_Reg_DPR(src1),
9534 OpcP, RegOpc(src2),
9535 CmpF_Result(dst));
9536 ins_pipe( pipe_slow );
9537 %}
9539 // float compare and set condition codes in EFLAGS by XMM regs
9540 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9541 predicate(UseSSE>=2);
9542 match(Set cr (CmpD src1 src2));
9543 ins_cost(145);
9544 format %{ "UCOMISD $src1,$src2\n\t"
9545 "JNP,s exit\n\t"
9546 "PUSHF\t# saw NaN, set CF\n\t"
9547 "AND [rsp], #0xffffff2b\n\t"
9548 "POPF\n"
9549 "exit:" %}
9550 ins_encode %{
9551 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9552 emit_cmpfp_fixup(_masm);
9553 %}
9554 ins_pipe( pipe_slow );
9555 %}
9557 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9558 predicate(UseSSE>=2);
9559 match(Set cr (CmpD src1 src2));
9560 ins_cost(100);
9561 format %{ "UCOMISD $src1,$src2" %}
9562 ins_encode %{
9563 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9564 %}
9565 ins_pipe( pipe_slow );
9566 %}
9568 // float compare and set condition codes in EFLAGS by XMM regs
9569 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9570 predicate(UseSSE>=2);
9571 match(Set cr (CmpD src1 (LoadD src2)));
9572 ins_cost(145);
9573 format %{ "UCOMISD $src1,$src2\n\t"
9574 "JNP,s exit\n\t"
9575 "PUSHF\t# saw NaN, set CF\n\t"
9576 "AND [rsp], #0xffffff2b\n\t"
9577 "POPF\n"
9578 "exit:" %}
9579 ins_encode %{
9580 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9581 emit_cmpfp_fixup(_masm);
9582 %}
9583 ins_pipe( pipe_slow );
9584 %}
9586 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9587 predicate(UseSSE>=2);
9588 match(Set cr (CmpD src1 (LoadD src2)));
9589 ins_cost(100);
9590 format %{ "UCOMISD $src1,$src2" %}
9591 ins_encode %{
9592 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9593 %}
9594 ins_pipe( pipe_slow );
9595 %}
9597 // Compare into -1,0,1 in XMM
9598 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9599 predicate(UseSSE>=2);
9600 match(Set dst (CmpD3 src1 src2));
9601 effect(KILL cr);
9602 ins_cost(255);
9603 format %{ "UCOMISD $src1, $src2\n\t"
9604 "MOV $dst, #-1\n\t"
9605 "JP,s done\n\t"
9606 "JB,s done\n\t"
9607 "SETNE $dst\n\t"
9608 "MOVZB $dst, $dst\n"
9609 "done:" %}
9610 ins_encode %{
9611 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9612 emit_cmpfp3(_masm, $dst$$Register);
9613 %}
9614 ins_pipe( pipe_slow );
9615 %}
9617 // Compare into -1,0,1 in XMM and memory
9618 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9619 predicate(UseSSE>=2);
9620 match(Set dst (CmpD3 src1 (LoadD src2)));
9621 effect(KILL cr);
9622 ins_cost(275);
9623 format %{ "UCOMISD $src1, $src2\n\t"
9624 "MOV $dst, #-1\n\t"
9625 "JP,s done\n\t"
9626 "JB,s done\n\t"
9627 "SETNE $dst\n\t"
9628 "MOVZB $dst, $dst\n"
9629 "done:" %}
9630 ins_encode %{
9631 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9632 emit_cmpfp3(_masm, $dst$$Register);
9633 %}
9634 ins_pipe( pipe_slow );
9635 %}
9638 instruct subDPR_reg(regDPR dst, regDPR src) %{
9639 predicate (UseSSE <=1);
9640 match(Set dst (SubD dst src));
9642 format %{ "FLD $src\n\t"
9643 "DSUBp $dst,ST" %}
9644 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9645 ins_cost(150);
9646 ins_encode( Push_Reg_DPR(src),
9647 OpcP, RegOpc(dst) );
9648 ins_pipe( fpu_reg_reg );
9649 %}
9651 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9652 predicate (UseSSE <=1);
9653 match(Set dst (RoundDouble (SubD src1 src2)));
9654 ins_cost(250);
9656 format %{ "FLD $src2\n\t"
9657 "DSUB ST,$src1\n\t"
9658 "FSTP_D $dst\t# D-round" %}
9659 opcode(0xD8, 0x5);
9660 ins_encode( Push_Reg_DPR(src2),
9661 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9662 ins_pipe( fpu_mem_reg_reg );
9663 %}
9666 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9667 predicate (UseSSE <=1);
9668 match(Set dst (SubD dst (LoadD src)));
9669 ins_cost(150);
9671 format %{ "FLD $src\n\t"
9672 "DSUBp $dst,ST" %}
9673 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9674 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9675 OpcP, RegOpc(dst) );
9676 ins_pipe( fpu_reg_mem );
9677 %}
9679 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9680 predicate (UseSSE<=1);
9681 match(Set dst (AbsD src));
9682 ins_cost(100);
9683 format %{ "FABS" %}
9684 opcode(0xE1, 0xD9);
9685 ins_encode( OpcS, OpcP );
9686 ins_pipe( fpu_reg_reg );
9687 %}
9689 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9690 predicate(UseSSE<=1);
9691 match(Set dst (NegD src));
9692 ins_cost(100);
9693 format %{ "FCHS" %}
9694 opcode(0xE0, 0xD9);
9695 ins_encode( OpcS, OpcP );
9696 ins_pipe( fpu_reg_reg );
9697 %}
9699 instruct addDPR_reg(regDPR dst, regDPR src) %{
9700 predicate(UseSSE<=1);
9701 match(Set dst (AddD dst src));
9702 format %{ "FLD $src\n\t"
9703 "DADD $dst,ST" %}
9704 size(4);
9705 ins_cost(150);
9706 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9707 ins_encode( Push_Reg_DPR(src),
9708 OpcP, RegOpc(dst) );
9709 ins_pipe( fpu_reg_reg );
9710 %}
9713 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9714 predicate(UseSSE<=1);
9715 match(Set dst (RoundDouble (AddD src1 src2)));
9716 ins_cost(250);
9718 format %{ "FLD $src2\n\t"
9719 "DADD ST,$src1\n\t"
9720 "FSTP_D $dst\t# D-round" %}
9721 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9722 ins_encode( Push_Reg_DPR(src2),
9723 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9724 ins_pipe( fpu_mem_reg_reg );
9725 %}
9728 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9729 predicate(UseSSE<=1);
9730 match(Set dst (AddD dst (LoadD src)));
9731 ins_cost(150);
9733 format %{ "FLD $src\n\t"
9734 "DADDp $dst,ST" %}
9735 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9736 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9737 OpcP, RegOpc(dst) );
9738 ins_pipe( fpu_reg_mem );
9739 %}
9741 // add-to-memory
9742 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9743 predicate(UseSSE<=1);
9744 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9745 ins_cost(150);
9747 format %{ "FLD_D $dst\n\t"
9748 "DADD ST,$src\n\t"
9749 "FST_D $dst" %}
9750 opcode(0xDD, 0x0);
9751 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9752 Opcode(0xD8), RegOpc(src),
9753 set_instruction_start,
9754 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9755 ins_pipe( fpu_reg_mem );
9756 %}
9758 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9759 predicate(UseSSE<=1);
9760 match(Set dst (AddD dst con));
9761 ins_cost(125);
9762 format %{ "FLD1\n\t"
9763 "DADDp $dst,ST" %}
9764 ins_encode %{
9765 __ fld1();
9766 __ faddp($dst$$reg);
9767 %}
9768 ins_pipe(fpu_reg);
9769 %}
9771 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9772 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9773 match(Set dst (AddD dst con));
9774 ins_cost(200);
9775 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9776 "DADDp $dst,ST" %}
9777 ins_encode %{
9778 __ fld_d($constantaddress($con));
9779 __ faddp($dst$$reg);
9780 %}
9781 ins_pipe(fpu_reg_mem);
9782 %}
9784 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9785 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9786 match(Set dst (RoundDouble (AddD src con)));
9787 ins_cost(200);
9788 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9789 "DADD ST,$src\n\t"
9790 "FSTP_D $dst\t# D-round" %}
9791 ins_encode %{
9792 __ fld_d($constantaddress($con));
9793 __ fadd($src$$reg);
9794 __ fstp_d(Address(rsp, $dst$$disp));
9795 %}
9796 ins_pipe(fpu_mem_reg_con);
9797 %}
9799 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9800 predicate(UseSSE<=1);
9801 match(Set dst (MulD dst src));
9802 format %{ "FLD $src\n\t"
9803 "DMULp $dst,ST" %}
9804 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9805 ins_cost(150);
9806 ins_encode( Push_Reg_DPR(src),
9807 OpcP, RegOpc(dst) );
9808 ins_pipe( fpu_reg_reg );
9809 %}
9811 // Strict FP instruction biases argument before multiply then
9812 // biases result to avoid double rounding of subnormals.
9813 //
9814 // scale arg1 by multiplying arg1 by 2^(-15360)
9815 // load arg2
9816 // multiply scaled arg1 by arg2
9817 // rescale product by 2^(15360)
9818 //
9819 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9820 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9821 match(Set dst (MulD dst src));
9822 ins_cost(1); // Select this instruction for all strict FP double multiplies
9824 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9825 "DMULp $dst,ST\n\t"
9826 "FLD $src\n\t"
9827 "DMULp $dst,ST\n\t"
9828 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9829 "DMULp $dst,ST\n\t" %}
9830 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9831 ins_encode( strictfp_bias1(dst),
9832 Push_Reg_DPR(src),
9833 OpcP, RegOpc(dst),
9834 strictfp_bias2(dst) );
9835 ins_pipe( fpu_reg_reg );
9836 %}
9838 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9839 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9840 match(Set dst (MulD dst con));
9841 ins_cost(200);
9842 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9843 "DMULp $dst,ST" %}
9844 ins_encode %{
9845 __ fld_d($constantaddress($con));
9846 __ fmulp($dst$$reg);
9847 %}
9848 ins_pipe(fpu_reg_mem);
9849 %}
9852 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9853 predicate( UseSSE<=1 );
9854 match(Set dst (MulD dst (LoadD src)));
9855 ins_cost(200);
9856 format %{ "FLD_D $src\n\t"
9857 "DMULp $dst,ST" %}
9858 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9859 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9860 OpcP, RegOpc(dst) );
9861 ins_pipe( fpu_reg_mem );
9862 %}
9864 //
9865 // Cisc-alternate to reg-reg multiply
9866 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9867 predicate( UseSSE<=1 );
9868 match(Set dst (MulD src (LoadD mem)));
9869 ins_cost(250);
9870 format %{ "FLD_D $mem\n\t"
9871 "DMUL ST,$src\n\t"
9872 "FSTP_D $dst" %}
9873 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9874 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9875 OpcReg_FPR(src),
9876 Pop_Reg_DPR(dst) );
9877 ins_pipe( fpu_reg_reg_mem );
9878 %}
9881 // MACRO3 -- addDPR a mulDPR
9882 // This instruction is a '2-address' instruction in that the result goes
9883 // back to src2. This eliminates a move from the macro; possibly the
9884 // register allocator will have to add it back (and maybe not).
9885 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9886 predicate( UseSSE<=1 );
9887 match(Set src2 (AddD (MulD src0 src1) src2));
9888 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9889 "DMUL ST,$src1\n\t"
9890 "DADDp $src2,ST" %}
9891 ins_cost(250);
9892 opcode(0xDD); /* LoadD DD /0 */
9893 ins_encode( Push_Reg_FPR(src0),
9894 FMul_ST_reg(src1),
9895 FAddP_reg_ST(src2) );
9896 ins_pipe( fpu_reg_reg_reg );
9897 %}
9900 // MACRO3 -- subDPR a mulDPR
9901 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9902 predicate( UseSSE<=1 );
9903 match(Set src2 (SubD (MulD src0 src1) src2));
9904 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9905 "DMUL ST,$src1\n\t"
9906 "DSUBRp $src2,ST" %}
9907 ins_cost(250);
9908 ins_encode( Push_Reg_FPR(src0),
9909 FMul_ST_reg(src1),
9910 Opcode(0xDE), Opc_plus(0xE0,src2));
9911 ins_pipe( fpu_reg_reg_reg );
9912 %}
9915 instruct divDPR_reg(regDPR dst, regDPR src) %{
9916 predicate( UseSSE<=1 );
9917 match(Set dst (DivD dst src));
9919 format %{ "FLD $src\n\t"
9920 "FDIVp $dst,ST" %}
9921 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9922 ins_cost(150);
9923 ins_encode( Push_Reg_DPR(src),
9924 OpcP, RegOpc(dst) );
9925 ins_pipe( fpu_reg_reg );
9926 %}
9928 // Strict FP instruction biases argument before division then
9929 // biases result, to avoid double rounding of subnormals.
9930 //
9931 // scale dividend by multiplying dividend by 2^(-15360)
9932 // load divisor
9933 // divide scaled dividend by divisor
9934 // rescale quotient by 2^(15360)
9935 //
9936 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9937 predicate (UseSSE<=1);
9938 match(Set dst (DivD dst src));
9939 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9940 ins_cost(01);
9942 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9943 "DMULp $dst,ST\n\t"
9944 "FLD $src\n\t"
9945 "FDIVp $dst,ST\n\t"
9946 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9947 "DMULp $dst,ST\n\t" %}
9948 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9949 ins_encode( strictfp_bias1(dst),
9950 Push_Reg_DPR(src),
9951 OpcP, RegOpc(dst),
9952 strictfp_bias2(dst) );
9953 ins_pipe( fpu_reg_reg );
9954 %}
9956 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9957 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9958 match(Set dst (RoundDouble (DivD src1 src2)));
9960 format %{ "FLD $src1\n\t"
9961 "FDIV ST,$src2\n\t"
9962 "FSTP_D $dst\t# D-round" %}
9963 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9964 ins_encode( Push_Reg_DPR(src1),
9965 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9966 ins_pipe( fpu_mem_reg_reg );
9967 %}
9970 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9971 predicate(UseSSE<=1);
9972 match(Set dst (ModD dst src));
9973 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9975 format %{ "DMOD $dst,$src" %}
9976 ins_cost(250);
9977 ins_encode(Push_Reg_Mod_DPR(dst, src),
9978 emitModDPR(),
9979 Push_Result_Mod_DPR(src),
9980 Pop_Reg_DPR(dst));
9981 ins_pipe( pipe_slow );
9982 %}
9984 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9985 predicate(UseSSE>=2);
9986 match(Set dst (ModD src0 src1));
9987 effect(KILL rax, KILL cr);
9989 format %{ "SUB ESP,8\t # DMOD\n"
9990 "\tMOVSD [ESP+0],$src1\n"
9991 "\tFLD_D [ESP+0]\n"
9992 "\tMOVSD [ESP+0],$src0\n"
9993 "\tFLD_D [ESP+0]\n"
9994 "loop:\tFPREM\n"
9995 "\tFWAIT\n"
9996 "\tFNSTSW AX\n"
9997 "\tSAHF\n"
9998 "\tJP loop\n"
9999 "\tFSTP_D [ESP+0]\n"
10000 "\tMOVSD $dst,[ESP+0]\n"
10001 "\tADD ESP,8\n"
10002 "\tFSTP ST0\t # Restore FPU Stack"
10003 %}
10004 ins_cost(250);
10005 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10006 ins_pipe( pipe_slow );
10007 %}
10009 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10010 predicate (UseSSE<=1);
10011 match(Set dst (SinD src));
10012 ins_cost(1800);
10013 format %{ "DSIN $dst" %}
10014 opcode(0xD9, 0xFE);
10015 ins_encode( OpcP, OpcS );
10016 ins_pipe( pipe_slow );
10017 %}
10019 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10020 predicate (UseSSE>=2);
10021 match(Set dst (SinD dst));
10022 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10023 ins_cost(1800);
10024 format %{ "DSIN $dst" %}
10025 opcode(0xD9, 0xFE);
10026 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10027 ins_pipe( pipe_slow );
10028 %}
10030 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10031 predicate (UseSSE<=1);
10032 match(Set dst (CosD src));
10033 ins_cost(1800);
10034 format %{ "DCOS $dst" %}
10035 opcode(0xD9, 0xFF);
10036 ins_encode( OpcP, OpcS );
10037 ins_pipe( pipe_slow );
10038 %}
10040 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10041 predicate (UseSSE>=2);
10042 match(Set dst (CosD dst));
10043 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10044 ins_cost(1800);
10045 format %{ "DCOS $dst" %}
10046 opcode(0xD9, 0xFF);
10047 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10048 ins_pipe( pipe_slow );
10049 %}
10051 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10052 predicate (UseSSE<=1);
10053 match(Set dst(TanD src));
10054 format %{ "DTAN $dst" %}
10055 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10056 Opcode(0xDD), Opcode(0xD8)); // fstp st
10057 ins_pipe( pipe_slow );
10058 %}
10060 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10061 predicate (UseSSE>=2);
10062 match(Set dst(TanD dst));
10063 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10064 format %{ "DTAN $dst" %}
10065 ins_encode( Push_SrcD(dst),
10066 Opcode(0xD9), Opcode(0xF2), // fptan
10067 Opcode(0xDD), Opcode(0xD8), // fstp st
10068 Push_ResultD(dst) );
10069 ins_pipe( pipe_slow );
10070 %}
10072 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10073 predicate (UseSSE<=1);
10074 match(Set dst(AtanD dst src));
10075 format %{ "DATA $dst,$src" %}
10076 opcode(0xD9, 0xF3);
10077 ins_encode( Push_Reg_DPR(src),
10078 OpcP, OpcS, RegOpc(dst) );
10079 ins_pipe( pipe_slow );
10080 %}
10082 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10083 predicate (UseSSE>=2);
10084 match(Set dst(AtanD dst src));
10085 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10086 format %{ "DATA $dst,$src" %}
10087 opcode(0xD9, 0xF3);
10088 ins_encode( Push_SrcD(src),
10089 OpcP, OpcS, Push_ResultD(dst) );
10090 ins_pipe( pipe_slow );
10091 %}
10093 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10094 predicate (UseSSE<=1);
10095 match(Set dst (SqrtD src));
10096 format %{ "DSQRT $dst,$src" %}
10097 opcode(0xFA, 0xD9);
10098 ins_encode( Push_Reg_DPR(src),
10099 OpcS, OpcP, Pop_Reg_DPR(dst) );
10100 ins_pipe( pipe_slow );
10101 %}
10103 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10104 predicate (UseSSE<=1);
10105 match(Set Y (PowD X Y)); // Raise X to the Yth power
10106 effect(KILL rax, KILL rbx, KILL rcx);
10107 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10108 "FLD_D $X\n\t"
10109 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10111 "FDUP \t\t\t# Q Q\n\t"
10112 "FRNDINT\t\t\t# int(Q) Q\n\t"
10113 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10114 "FISTP dword [ESP]\n\t"
10115 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10116 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10117 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10118 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10119 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10120 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10121 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10122 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10123 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10124 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10125 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10126 "MOV [ESP+0],0\n\t"
10127 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10129 "ADD ESP,8"
10130 %}
10131 ins_encode( push_stack_temp_qword,
10132 Push_Reg_DPR(X),
10133 Opcode(0xD9), Opcode(0xF1), // fyl2x
10134 pow_exp_core_encoding,
10135 pop_stack_temp_qword);
10136 ins_pipe( pipe_slow );
10137 %}
10139 instruct powD_reg(regD dst, regD src0, regD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10140 predicate (UseSSE>=2);
10141 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10142 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10143 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10144 "MOVSD [ESP],$src1\n\t"
10145 "FLD FPR1,$src1\n\t"
10146 "MOVSD [ESP],$src0\n\t"
10147 "FLD FPR1,$src0\n\t"
10148 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10150 "FDUP \t\t\t# Q Q\n\t"
10151 "FRNDINT\t\t\t# int(Q) Q\n\t"
10152 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10153 "FISTP dword [ESP]\n\t"
10154 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10155 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10156 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10157 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10158 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10159 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10160 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10161 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10162 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10163 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10164 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10165 "MOV [ESP+0],0\n\t"
10166 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10168 "FST_D [ESP]\n\t"
10169 "MOVSD $dst,[ESP]\n\t"
10170 "ADD ESP,8"
10171 %}
10172 ins_encode( push_stack_temp_qword,
10173 push_xmm_to_fpr1(src1),
10174 push_xmm_to_fpr1(src0),
10175 Opcode(0xD9), Opcode(0xF1), // fyl2x
10176 pow_exp_core_encoding,
10177 Push_ResultD(dst) );
10178 ins_pipe( pipe_slow );
10179 %}
10182 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10183 predicate (UseSSE<=1);
10184 match(Set dpr1 (ExpD dpr1));
10185 effect(KILL rax, KILL rbx, KILL rcx);
10186 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10187 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10188 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10190 "FDUP \t\t\t# Q Q\n\t"
10191 "FRNDINT\t\t\t# int(Q) Q\n\t"
10192 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10193 "FISTP dword [ESP]\n\t"
10194 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10195 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10196 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10197 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10198 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10199 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10200 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10201 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10202 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10203 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10204 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10205 "MOV [ESP+0],0\n\t"
10206 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10208 "ADD ESP,8"
10209 %}
10210 ins_encode( push_stack_temp_qword,
10211 Opcode(0xD9), Opcode(0xEA), // fldl2e
10212 Opcode(0xDE), Opcode(0xC9), // fmulp
10213 pow_exp_core_encoding,
10214 pop_stack_temp_qword);
10215 ins_pipe( pipe_slow );
10216 %}
10218 instruct expD_reg(regD dst, regD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10219 predicate (UseSSE>=2);
10220 match(Set dst (ExpD src));
10221 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10222 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10223 "MOVSD [ESP],$src\n\t"
10224 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10225 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10227 "FDUP \t\t\t# Q Q\n\t"
10228 "FRNDINT\t\t\t# int(Q) Q\n\t"
10229 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10230 "FISTP dword [ESP]\n\t"
10231 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10232 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10233 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10234 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10235 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10236 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10237 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10238 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10239 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10240 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10241 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10242 "MOV [ESP+0],0\n\t"
10243 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10245 "FST_D [ESP]\n\t"
10246 "MOVSD $dst,[ESP]\n\t"
10247 "ADD ESP,8"
10248 %}
10249 ins_encode( Push_SrcD(src),
10250 Opcode(0xD9), Opcode(0xEA), // fldl2e
10251 Opcode(0xDE), Opcode(0xC9), // fmulp
10252 pow_exp_core_encoding,
10253 Push_ResultD(dst) );
10254 ins_pipe( pipe_slow );
10255 %}
10259 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10260 predicate (UseSSE<=1);
10261 // The source Double operand on FPU stack
10262 match(Set dst (Log10D src));
10263 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10264 // fxch ; swap ST(0) with ST(1)
10265 // fyl2x ; compute log_10(2) * log_2(x)
10266 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10267 "FXCH \n\t"
10268 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10269 %}
10270 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10271 Opcode(0xD9), Opcode(0xC9), // fxch
10272 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10274 ins_pipe( pipe_slow );
10275 %}
10277 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10278 predicate (UseSSE>=2);
10279 effect(KILL cr);
10280 match(Set dst (Log10D src));
10281 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10282 // fyl2x ; compute log_10(2) * log_2(x)
10283 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10284 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10285 %}
10286 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10287 Push_SrcD(src),
10288 Opcode(0xD9), Opcode(0xF1), // fyl2x
10289 Push_ResultD(dst));
10291 ins_pipe( pipe_slow );
10292 %}
10294 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10295 predicate (UseSSE<=1);
10296 // The source Double operand on FPU stack
10297 match(Set dst (LogD src));
10298 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10299 // fxch ; swap ST(0) with ST(1)
10300 // fyl2x ; compute log_e(2) * log_2(x)
10301 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10302 "FXCH \n\t"
10303 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10304 %}
10305 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10306 Opcode(0xD9), Opcode(0xC9), // fxch
10307 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10309 ins_pipe( pipe_slow );
10310 %}
10312 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10313 predicate (UseSSE>=2);
10314 effect(KILL cr);
10315 // The source and result Double operands in XMM registers
10316 match(Set dst (LogD src));
10317 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10318 // fyl2x ; compute log_e(2) * log_2(x)
10319 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10320 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10321 %}
10322 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10323 Push_SrcD(src),
10324 Opcode(0xD9), Opcode(0xF1), // fyl2x
10325 Push_ResultD(dst));
10326 ins_pipe( pipe_slow );
10327 %}
10329 //-------------Float Instructions-------------------------------
10330 // Float Math
10332 // Code for float compare:
10333 // fcompp();
10334 // fwait(); fnstsw_ax();
10335 // sahf();
10336 // movl(dst, unordered_result);
10337 // jcc(Assembler::parity, exit);
10338 // movl(dst, less_result);
10339 // jcc(Assembler::below, exit);
10340 // movl(dst, equal_result);
10341 // jcc(Assembler::equal, exit);
10342 // movl(dst, greater_result);
10343 // exit:
10345 // P6 version of float compare, sets condition codes in EFLAGS
10346 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10347 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10348 match(Set cr (CmpF src1 src2));
10349 effect(KILL rax);
10350 ins_cost(150);
10351 format %{ "FLD $src1\n\t"
10352 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10353 "JNP exit\n\t"
10354 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10355 "SAHF\n"
10356 "exit:\tNOP // avoid branch to branch" %}
10357 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10358 ins_encode( Push_Reg_DPR(src1),
10359 OpcP, RegOpc(src2),
10360 cmpF_P6_fixup );
10361 ins_pipe( pipe_slow );
10362 %}
10364 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10365 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10366 match(Set cr (CmpF src1 src2));
10367 ins_cost(100);
10368 format %{ "FLD $src1\n\t"
10369 "FUCOMIP ST,$src2 // P6 instruction" %}
10370 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10371 ins_encode( Push_Reg_DPR(src1),
10372 OpcP, RegOpc(src2));
10373 ins_pipe( pipe_slow );
10374 %}
10377 // Compare & branch
10378 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10379 predicate(UseSSE == 0);
10380 match(Set cr (CmpF src1 src2));
10381 effect(KILL rax);
10382 ins_cost(200);
10383 format %{ "FLD $src1\n\t"
10384 "FCOMp $src2\n\t"
10385 "FNSTSW AX\n\t"
10386 "TEST AX,0x400\n\t"
10387 "JZ,s flags\n\t"
10388 "MOV AH,1\t# unordered treat as LT\n"
10389 "flags:\tSAHF" %}
10390 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10391 ins_encode( Push_Reg_DPR(src1),
10392 OpcP, RegOpc(src2),
10393 fpu_flags);
10394 ins_pipe( pipe_slow );
10395 %}
10397 // Compare vs zero into -1,0,1
10398 instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10399 predicate(UseSSE == 0);
10400 match(Set dst (CmpF3 src1 zero));
10401 effect(KILL cr, KILL rax);
10402 ins_cost(280);
10403 format %{ "FTSTF $dst,$src1" %}
10404 opcode(0xE4, 0xD9);
10405 ins_encode( Push_Reg_DPR(src1),
10406 OpcS, OpcP, PopFPU,
10407 CmpF_Result(dst));
10408 ins_pipe( pipe_slow );
10409 %}
10411 // Compare into -1,0,1
10412 instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10413 predicate(UseSSE == 0);
10414 match(Set dst (CmpF3 src1 src2));
10415 effect(KILL cr, KILL rax);
10416 ins_cost(300);
10417 format %{ "FCMPF $dst,$src1,$src2" %}
10418 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10419 ins_encode( Push_Reg_DPR(src1),
10420 OpcP, RegOpc(src2),
10421 CmpF_Result(dst));
10422 ins_pipe( pipe_slow );
10423 %}
10425 // float compare and set condition codes in EFLAGS by XMM regs
10426 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10427 predicate(UseSSE>=1);
10428 match(Set cr (CmpF src1 src2));
10429 ins_cost(145);
10430 format %{ "UCOMISS $src1,$src2\n\t"
10431 "JNP,s exit\n\t"
10432 "PUSHF\t# saw NaN, set CF\n\t"
10433 "AND [rsp], #0xffffff2b\n\t"
10434 "POPF\n"
10435 "exit:" %}
10436 ins_encode %{
10437 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10438 emit_cmpfp_fixup(_masm);
10439 %}
10440 ins_pipe( pipe_slow );
10441 %}
10443 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10444 predicate(UseSSE>=1);
10445 match(Set cr (CmpF src1 src2));
10446 ins_cost(100);
10447 format %{ "UCOMISS $src1,$src2" %}
10448 ins_encode %{
10449 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10450 %}
10451 ins_pipe( pipe_slow );
10452 %}
10454 // float compare and set condition codes in EFLAGS by XMM regs
10455 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10456 predicate(UseSSE>=1);
10457 match(Set cr (CmpF src1 (LoadF src2)));
10458 ins_cost(165);
10459 format %{ "UCOMISS $src1,$src2\n\t"
10460 "JNP,s exit\n\t"
10461 "PUSHF\t# saw NaN, set CF\n\t"
10462 "AND [rsp], #0xffffff2b\n\t"
10463 "POPF\n"
10464 "exit:" %}
10465 ins_encode %{
10466 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10467 emit_cmpfp_fixup(_masm);
10468 %}
10469 ins_pipe( pipe_slow );
10470 %}
10472 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10473 predicate(UseSSE>=1);
10474 match(Set cr (CmpF src1 (LoadF src2)));
10475 ins_cost(100);
10476 format %{ "UCOMISS $src1,$src2" %}
10477 ins_encode %{
10478 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10479 %}
10480 ins_pipe( pipe_slow );
10481 %}
10483 // Compare into -1,0,1 in XMM
10484 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10485 predicate(UseSSE>=1);
10486 match(Set dst (CmpF3 src1 src2));
10487 effect(KILL cr);
10488 ins_cost(255);
10489 format %{ "UCOMISS $src1, $src2\n\t"
10490 "MOV $dst, #-1\n\t"
10491 "JP,s done\n\t"
10492 "JB,s done\n\t"
10493 "SETNE $dst\n\t"
10494 "MOVZB $dst, $dst\n"
10495 "done:" %}
10496 ins_encode %{
10497 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10498 emit_cmpfp3(_masm, $dst$$Register);
10499 %}
10500 ins_pipe( pipe_slow );
10501 %}
10503 // Compare into -1,0,1 in XMM and memory
10504 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10505 predicate(UseSSE>=1);
10506 match(Set dst (CmpF3 src1 (LoadF src2)));
10507 effect(KILL cr);
10508 ins_cost(275);
10509 format %{ "UCOMISS $src1, $src2\n\t"
10510 "MOV $dst, #-1\n\t"
10511 "JP,s done\n\t"
10512 "JB,s done\n\t"
10513 "SETNE $dst\n\t"
10514 "MOVZB $dst, $dst\n"
10515 "done:" %}
10516 ins_encode %{
10517 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10518 emit_cmpfp3(_masm, $dst$$Register);
10519 %}
10520 ins_pipe( pipe_slow );
10521 %}
10523 // Spill to obtain 24-bit precision
10524 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10525 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10526 match(Set dst (SubF src1 src2));
10528 format %{ "FSUB $dst,$src1 - $src2" %}
10529 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10530 ins_encode( Push_Reg_FPR(src1),
10531 OpcReg_FPR(src2),
10532 Pop_Mem_FPR(dst) );
10533 ins_pipe( fpu_mem_reg_reg );
10534 %}
10535 //
10536 // This instruction does not round to 24-bits
10537 instruct subFPR_reg(regFPR dst, regFPR src) %{
10538 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10539 match(Set dst (SubF dst src));
10541 format %{ "FSUB $dst,$src" %}
10542 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10543 ins_encode( Push_Reg_FPR(src),
10544 OpcP, RegOpc(dst) );
10545 ins_pipe( fpu_reg_reg );
10546 %}
10548 // Spill to obtain 24-bit precision
10549 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10550 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10551 match(Set dst (AddF src1 src2));
10553 format %{ "FADD $dst,$src1,$src2" %}
10554 opcode(0xD8, 0x0); /* D8 C0+i */
10555 ins_encode( Push_Reg_FPR(src2),
10556 OpcReg_FPR(src1),
10557 Pop_Mem_FPR(dst) );
10558 ins_pipe( fpu_mem_reg_reg );
10559 %}
10560 //
10561 // This instruction does not round to 24-bits
10562 instruct addFPR_reg(regFPR dst, regFPR src) %{
10563 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10564 match(Set dst (AddF dst src));
10566 format %{ "FLD $src\n\t"
10567 "FADDp $dst,ST" %}
10568 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10569 ins_encode( Push_Reg_FPR(src),
10570 OpcP, RegOpc(dst) );
10571 ins_pipe( fpu_reg_reg );
10572 %}
10574 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10575 predicate(UseSSE==0);
10576 match(Set dst (AbsF src));
10577 ins_cost(100);
10578 format %{ "FABS" %}
10579 opcode(0xE1, 0xD9);
10580 ins_encode( OpcS, OpcP );
10581 ins_pipe( fpu_reg_reg );
10582 %}
10584 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10585 predicate(UseSSE==0);
10586 match(Set dst (NegF src));
10587 ins_cost(100);
10588 format %{ "FCHS" %}
10589 opcode(0xE0, 0xD9);
10590 ins_encode( OpcS, OpcP );
10591 ins_pipe( fpu_reg_reg );
10592 %}
10594 // Cisc-alternate to addFPR_reg
10595 // Spill to obtain 24-bit precision
10596 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10597 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10598 match(Set dst (AddF src1 (LoadF src2)));
10600 format %{ "FLD $src2\n\t"
10601 "FADD ST,$src1\n\t"
10602 "FSTP_S $dst" %}
10603 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10604 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10605 OpcReg_FPR(src1),
10606 Pop_Mem_FPR(dst) );
10607 ins_pipe( fpu_mem_reg_mem );
10608 %}
10609 //
10610 // Cisc-alternate to addFPR_reg
10611 // This instruction does not round to 24-bits
10612 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10613 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10614 match(Set dst (AddF dst (LoadF src)));
10616 format %{ "FADD $dst,$src" %}
10617 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10618 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10619 OpcP, RegOpc(dst) );
10620 ins_pipe( fpu_reg_mem );
10621 %}
10623 // // Following two instructions for _222_mpegaudio
10624 // Spill to obtain 24-bit precision
10625 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10626 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10627 match(Set dst (AddF src1 src2));
10629 format %{ "FADD $dst,$src1,$src2" %}
10630 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10631 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10632 OpcReg_FPR(src2),
10633 Pop_Mem_FPR(dst) );
10634 ins_pipe( fpu_mem_reg_mem );
10635 %}
10637 // Cisc-spill variant
10638 // Spill to obtain 24-bit precision
10639 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10640 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10641 match(Set dst (AddF src1 (LoadF src2)));
10643 format %{ "FADD $dst,$src1,$src2 cisc" %}
10644 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10645 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10646 set_instruction_start,
10647 OpcP, RMopc_Mem(secondary,src1),
10648 Pop_Mem_FPR(dst) );
10649 ins_pipe( fpu_mem_mem_mem );
10650 %}
10652 // Spill to obtain 24-bit precision
10653 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10654 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10655 match(Set dst (AddF src1 src2));
10657 format %{ "FADD $dst,$src1,$src2" %}
10658 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10659 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10660 set_instruction_start,
10661 OpcP, RMopc_Mem(secondary,src1),
10662 Pop_Mem_FPR(dst) );
10663 ins_pipe( fpu_mem_mem_mem );
10664 %}
10667 // Spill to obtain 24-bit precision
10668 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10669 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10670 match(Set dst (AddF src con));
10671 format %{ "FLD $src\n\t"
10672 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10673 "FSTP_S $dst" %}
10674 ins_encode %{
10675 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10676 __ fadd_s($constantaddress($con));
10677 __ fstp_s(Address(rsp, $dst$$disp));
10678 %}
10679 ins_pipe(fpu_mem_reg_con);
10680 %}
10681 //
10682 // This instruction does not round to 24-bits
10683 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10684 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10685 match(Set dst (AddF src con));
10686 format %{ "FLD $src\n\t"
10687 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10688 "FSTP $dst" %}
10689 ins_encode %{
10690 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10691 __ fadd_s($constantaddress($con));
10692 __ fstp_d($dst$$reg);
10693 %}
10694 ins_pipe(fpu_reg_reg_con);
10695 %}
10697 // Spill to obtain 24-bit precision
10698 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10699 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10700 match(Set dst (MulF src1 src2));
10702 format %{ "FLD $src1\n\t"
10703 "FMUL $src2\n\t"
10704 "FSTP_S $dst" %}
10705 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10706 ins_encode( Push_Reg_FPR(src1),
10707 OpcReg_FPR(src2),
10708 Pop_Mem_FPR(dst) );
10709 ins_pipe( fpu_mem_reg_reg );
10710 %}
10711 //
10712 // This instruction does not round to 24-bits
10713 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10714 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10715 match(Set dst (MulF src1 src2));
10717 format %{ "FLD $src1\n\t"
10718 "FMUL $src2\n\t"
10719 "FSTP_S $dst" %}
10720 opcode(0xD8, 0x1); /* D8 C8+i */
10721 ins_encode( Push_Reg_FPR(src2),
10722 OpcReg_FPR(src1),
10723 Pop_Reg_FPR(dst) );
10724 ins_pipe( fpu_reg_reg_reg );
10725 %}
10728 // Spill to obtain 24-bit precision
10729 // Cisc-alternate to reg-reg multiply
10730 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10731 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10732 match(Set dst (MulF src1 (LoadF src2)));
10734 format %{ "FLD_S $src2\n\t"
10735 "FMUL $src1\n\t"
10736 "FSTP_S $dst" %}
10737 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10738 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10739 OpcReg_FPR(src1),
10740 Pop_Mem_FPR(dst) );
10741 ins_pipe( fpu_mem_reg_mem );
10742 %}
10743 //
10744 // This instruction does not round to 24-bits
10745 // Cisc-alternate to reg-reg multiply
10746 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10747 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10748 match(Set dst (MulF src1 (LoadF src2)));
10750 format %{ "FMUL $dst,$src1,$src2" %}
10751 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10752 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10753 OpcReg_FPR(src1),
10754 Pop_Reg_FPR(dst) );
10755 ins_pipe( fpu_reg_reg_mem );
10756 %}
10758 // Spill to obtain 24-bit precision
10759 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10760 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10761 match(Set dst (MulF src1 src2));
10763 format %{ "FMUL $dst,$src1,$src2" %}
10764 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10765 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10766 set_instruction_start,
10767 OpcP, RMopc_Mem(secondary,src1),
10768 Pop_Mem_FPR(dst) );
10769 ins_pipe( fpu_mem_mem_mem );
10770 %}
10772 // Spill to obtain 24-bit precision
10773 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10774 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10775 match(Set dst (MulF src con));
10777 format %{ "FLD $src\n\t"
10778 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10779 "FSTP_S $dst" %}
10780 ins_encode %{
10781 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10782 __ fmul_s($constantaddress($con));
10783 __ fstp_s(Address(rsp, $dst$$disp));
10784 %}
10785 ins_pipe(fpu_mem_reg_con);
10786 %}
10787 //
10788 // This instruction does not round to 24-bits
10789 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10790 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10791 match(Set dst (MulF src con));
10793 format %{ "FLD $src\n\t"
10794 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10795 "FSTP $dst" %}
10796 ins_encode %{
10797 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10798 __ fmul_s($constantaddress($con));
10799 __ fstp_d($dst$$reg);
10800 %}
10801 ins_pipe(fpu_reg_reg_con);
10802 %}
10805 //
10806 // MACRO1 -- subsume unshared load into mulFPR
10807 // This instruction does not round to 24-bits
10808 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10809 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10810 match(Set dst (MulF (LoadF mem1) src));
10812 format %{ "FLD $mem1 ===MACRO1===\n\t"
10813 "FMUL ST,$src\n\t"
10814 "FSTP $dst" %}
10815 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10816 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10817 OpcReg_FPR(src),
10818 Pop_Reg_FPR(dst) );
10819 ins_pipe( fpu_reg_reg_mem );
10820 %}
10821 //
10822 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10823 // This instruction does not round to 24-bits
10824 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10825 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10826 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10827 ins_cost(95);
10829 format %{ "FLD $mem1 ===MACRO2===\n\t"
10830 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10831 "FADD ST,$src2\n\t"
10832 "FSTP $dst" %}
10833 opcode(0xD9); /* LoadF D9 /0 */
10834 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10835 FMul_ST_reg(src1),
10836 FAdd_ST_reg(src2),
10837 Pop_Reg_FPR(dst) );
10838 ins_pipe( fpu_reg_mem_reg_reg );
10839 %}
10841 // MACRO3 -- addFPR a mulFPR
10842 // This instruction does not round to 24-bits. It is a '2-address'
10843 // instruction in that the result goes back to src2. This eliminates
10844 // a move from the macro; possibly the register allocator will have
10845 // to add it back (and maybe not).
10846 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10847 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10848 match(Set src2 (AddF (MulF src0 src1) src2));
10850 format %{ "FLD $src0 ===MACRO3===\n\t"
10851 "FMUL ST,$src1\n\t"
10852 "FADDP $src2,ST" %}
10853 opcode(0xD9); /* LoadF D9 /0 */
10854 ins_encode( Push_Reg_FPR(src0),
10855 FMul_ST_reg(src1),
10856 FAddP_reg_ST(src2) );
10857 ins_pipe( fpu_reg_reg_reg );
10858 %}
10860 // MACRO4 -- divFPR subFPR
10861 // This instruction does not round to 24-bits
10862 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10863 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10864 match(Set dst (DivF (SubF src2 src1) src3));
10866 format %{ "FLD $src2 ===MACRO4===\n\t"
10867 "FSUB ST,$src1\n\t"
10868 "FDIV ST,$src3\n\t"
10869 "FSTP $dst" %}
10870 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10871 ins_encode( Push_Reg_FPR(src2),
10872 subFPR_divFPR_encode(src1,src3),
10873 Pop_Reg_FPR(dst) );
10874 ins_pipe( fpu_reg_reg_reg_reg );
10875 %}
10877 // Spill to obtain 24-bit precision
10878 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10879 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10880 match(Set dst (DivF src1 src2));
10882 format %{ "FDIV $dst,$src1,$src2" %}
10883 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10884 ins_encode( Push_Reg_FPR(src1),
10885 OpcReg_FPR(src2),
10886 Pop_Mem_FPR(dst) );
10887 ins_pipe( fpu_mem_reg_reg );
10888 %}
10889 //
10890 // This instruction does not round to 24-bits
10891 instruct divFPR_reg(regFPR dst, regFPR src) %{
10892 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10893 match(Set dst (DivF dst src));
10895 format %{ "FDIV $dst,$src" %}
10896 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10897 ins_encode( Push_Reg_FPR(src),
10898 OpcP, RegOpc(dst) );
10899 ins_pipe( fpu_reg_reg );
10900 %}
10903 // Spill to obtain 24-bit precision
10904 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10905 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10906 match(Set dst (ModF src1 src2));
10907 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10909 format %{ "FMOD $dst,$src1,$src2" %}
10910 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10911 emitModDPR(),
10912 Push_Result_Mod_DPR(src2),
10913 Pop_Mem_FPR(dst));
10914 ins_pipe( pipe_slow );
10915 %}
10916 //
10917 // This instruction does not round to 24-bits
10918 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10919 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10920 match(Set dst (ModF dst src));
10921 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10923 format %{ "FMOD $dst,$src" %}
10924 ins_encode(Push_Reg_Mod_DPR(dst, src),
10925 emitModDPR(),
10926 Push_Result_Mod_DPR(src),
10927 Pop_Reg_FPR(dst));
10928 ins_pipe( pipe_slow );
10929 %}
10931 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10932 predicate(UseSSE>=1);
10933 match(Set dst (ModF src0 src1));
10934 effect(KILL rax, KILL cr);
10935 format %{ "SUB ESP,4\t # FMOD\n"
10936 "\tMOVSS [ESP+0],$src1\n"
10937 "\tFLD_S [ESP+0]\n"
10938 "\tMOVSS [ESP+0],$src0\n"
10939 "\tFLD_S [ESP+0]\n"
10940 "loop:\tFPREM\n"
10941 "\tFWAIT\n"
10942 "\tFNSTSW AX\n"
10943 "\tSAHF\n"
10944 "\tJP loop\n"
10945 "\tFSTP_S [ESP+0]\n"
10946 "\tMOVSS $dst,[ESP+0]\n"
10947 "\tADD ESP,4\n"
10948 "\tFSTP ST0\t # Restore FPU Stack"
10949 %}
10950 ins_cost(250);
10951 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10952 ins_pipe( pipe_slow );
10953 %}
10956 //----------Arithmetic Conversion Instructions---------------------------------
10957 // The conversions operations are all Alpha sorted. Please keep it that way!
10959 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10960 predicate(UseSSE==0);
10961 match(Set dst (RoundFloat src));
10962 ins_cost(125);
10963 format %{ "FST_S $dst,$src\t# F-round" %}
10964 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10965 ins_pipe( fpu_mem_reg );
10966 %}
10968 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10969 predicate(UseSSE<=1);
10970 match(Set dst (RoundDouble src));
10971 ins_cost(125);
10972 format %{ "FST_D $dst,$src\t# D-round" %}
10973 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10974 ins_pipe( fpu_mem_reg );
10975 %}
10977 // Force rounding to 24-bit precision and 6-bit exponent
10978 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10979 predicate(UseSSE==0);
10980 match(Set dst (ConvD2F src));
10981 format %{ "FST_S $dst,$src\t# F-round" %}
10982 expand %{
10983 roundFloat_mem_reg(dst,src);
10984 %}
10985 %}
10987 // Force rounding to 24-bit precision and 6-bit exponent
10988 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10989 predicate(UseSSE==1);
10990 match(Set dst (ConvD2F src));
10991 effect( KILL cr );
10992 format %{ "SUB ESP,4\n\t"
10993 "FST_S [ESP],$src\t# F-round\n\t"
10994 "MOVSS $dst,[ESP]\n\t"
10995 "ADD ESP,4" %}
10996 ins_encode %{
10997 __ subptr(rsp, 4);
10998 if ($src$$reg != FPR1L_enc) {
10999 __ fld_s($src$$reg-1);
11000 __ fstp_s(Address(rsp, 0));
11001 } else {
11002 __ fst_s(Address(rsp, 0));
11003 }
11004 __ movflt($dst$$XMMRegister, Address(rsp, 0));
11005 __ addptr(rsp, 4);
11006 %}
11007 ins_pipe( pipe_slow );
11008 %}
11010 // Force rounding double precision to single precision
11011 instruct convD2F_reg(regF dst, regD src) %{
11012 predicate(UseSSE>=2);
11013 match(Set dst (ConvD2F src));
11014 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11015 ins_encode %{
11016 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11017 %}
11018 ins_pipe( pipe_slow );
11019 %}
11021 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
11022 predicate(UseSSE==0);
11023 match(Set dst (ConvF2D src));
11024 format %{ "FST_S $dst,$src\t# D-round" %}
11025 ins_encode( Pop_Reg_Reg_DPR(dst, src));
11026 ins_pipe( fpu_reg_reg );
11027 %}
11029 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
11030 predicate(UseSSE==1);
11031 match(Set dst (ConvF2D src));
11032 format %{ "FST_D $dst,$src\t# D-round" %}
11033 expand %{
11034 roundDouble_mem_reg(dst,src);
11035 %}
11036 %}
11038 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
11039 predicate(UseSSE==1);
11040 match(Set dst (ConvF2D src));
11041 effect( KILL cr );
11042 format %{ "SUB ESP,4\n\t"
11043 "MOVSS [ESP] $src\n\t"
11044 "FLD_S [ESP]\n\t"
11045 "ADD ESP,4\n\t"
11046 "FSTP $dst\t# D-round" %}
11047 ins_encode %{
11048 __ subptr(rsp, 4);
11049 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11050 __ fld_s(Address(rsp, 0));
11051 __ addptr(rsp, 4);
11052 __ fstp_d($dst$$reg);
11053 %}
11054 ins_pipe( pipe_slow );
11055 %}
11057 instruct convF2D_reg(regD dst, regF src) %{
11058 predicate(UseSSE>=2);
11059 match(Set dst (ConvF2D src));
11060 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11061 ins_encode %{
11062 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11063 %}
11064 ins_pipe( pipe_slow );
11065 %}
11067 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11068 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
11069 predicate(UseSSE<=1);
11070 match(Set dst (ConvD2I src));
11071 effect( KILL tmp, KILL cr );
11072 format %{ "FLD $src\t# Convert double to int \n\t"
11073 "FLDCW trunc mode\n\t"
11074 "SUB ESP,4\n\t"
11075 "FISTp [ESP + #0]\n\t"
11076 "FLDCW std/24-bit mode\n\t"
11077 "POP EAX\n\t"
11078 "CMP EAX,0x80000000\n\t"
11079 "JNE,s fast\n\t"
11080 "FLD_D $src\n\t"
11081 "CALL d2i_wrapper\n"
11082 "fast:" %}
11083 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
11084 ins_pipe( pipe_slow );
11085 %}
11087 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11088 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11089 predicate(UseSSE>=2);
11090 match(Set dst (ConvD2I src));
11091 effect( KILL tmp, KILL cr );
11092 format %{ "CVTTSD2SI $dst, $src\n\t"
11093 "CMP $dst,0x80000000\n\t"
11094 "JNE,s fast\n\t"
11095 "SUB ESP, 8\n\t"
11096 "MOVSD [ESP], $src\n\t"
11097 "FLD_D [ESP]\n\t"
11098 "ADD ESP, 8\n\t"
11099 "CALL d2i_wrapper\n"
11100 "fast:" %}
11101 ins_encode %{
11102 Label fast;
11103 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11104 __ cmpl($dst$$Register, 0x80000000);
11105 __ jccb(Assembler::notEqual, fast);
11106 __ subptr(rsp, 8);
11107 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11108 __ fld_d(Address(rsp, 0));
11109 __ addptr(rsp, 8);
11110 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11111 __ bind(fast);
11112 %}
11113 ins_pipe( pipe_slow );
11114 %}
11116 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11117 predicate(UseSSE<=1);
11118 match(Set dst (ConvD2L src));
11119 effect( KILL cr );
11120 format %{ "FLD $src\t# Convert double to long\n\t"
11121 "FLDCW trunc mode\n\t"
11122 "SUB ESP,8\n\t"
11123 "FISTp [ESP + #0]\n\t"
11124 "FLDCW std/24-bit mode\n\t"
11125 "POP EAX\n\t"
11126 "POP EDX\n\t"
11127 "CMP EDX,0x80000000\n\t"
11128 "JNE,s fast\n\t"
11129 "TEST EAX,EAX\n\t"
11130 "JNE,s fast\n\t"
11131 "FLD $src\n\t"
11132 "CALL d2l_wrapper\n"
11133 "fast:" %}
11134 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11135 ins_pipe( pipe_slow );
11136 %}
11138 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11139 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11140 predicate (UseSSE>=2);
11141 match(Set dst (ConvD2L src));
11142 effect( KILL cr );
11143 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11144 "MOVSD [ESP],$src\n\t"
11145 "FLD_D [ESP]\n\t"
11146 "FLDCW trunc mode\n\t"
11147 "FISTp [ESP + #0]\n\t"
11148 "FLDCW std/24-bit mode\n\t"
11149 "POP EAX\n\t"
11150 "POP EDX\n\t"
11151 "CMP EDX,0x80000000\n\t"
11152 "JNE,s fast\n\t"
11153 "TEST EAX,EAX\n\t"
11154 "JNE,s fast\n\t"
11155 "SUB ESP,8\n\t"
11156 "MOVSD [ESP],$src\n\t"
11157 "FLD_D [ESP]\n\t"
11158 "ADD ESP,8\n\t"
11159 "CALL d2l_wrapper\n"
11160 "fast:" %}
11161 ins_encode %{
11162 Label fast;
11163 __ subptr(rsp, 8);
11164 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11165 __ fld_d(Address(rsp, 0));
11166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11167 __ fistp_d(Address(rsp, 0));
11168 // Restore the rounding mode, mask the exception
11169 if (Compile::current()->in_24_bit_fp_mode()) {
11170 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11171 } else {
11172 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11173 }
11174 // Load the converted long, adjust CPU stack
11175 __ pop(rax);
11176 __ pop(rdx);
11177 __ cmpl(rdx, 0x80000000);
11178 __ jccb(Assembler::notEqual, fast);
11179 __ testl(rax, rax);
11180 __ jccb(Assembler::notEqual, fast);
11181 __ subptr(rsp, 8);
11182 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11183 __ fld_d(Address(rsp, 0));
11184 __ addptr(rsp, 8);
11185 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11186 __ bind(fast);
11187 %}
11188 ins_pipe( pipe_slow );
11189 %}
11191 // Convert a double to an int. Java semantics require we do complex
11192 // manglations in the corner cases. So we set the rounding mode to
11193 // 'zero', store the darned double down as an int, and reset the
11194 // rounding mode to 'nearest'. The hardware stores a flag value down
11195 // if we would overflow or converted a NAN; we check for this and
11196 // and go the slow path if needed.
11197 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11198 predicate(UseSSE==0);
11199 match(Set dst (ConvF2I src));
11200 effect( KILL tmp, KILL cr );
11201 format %{ "FLD $src\t# Convert float to int \n\t"
11202 "FLDCW trunc mode\n\t"
11203 "SUB ESP,4\n\t"
11204 "FISTp [ESP + #0]\n\t"
11205 "FLDCW std/24-bit mode\n\t"
11206 "POP EAX\n\t"
11207 "CMP EAX,0x80000000\n\t"
11208 "JNE,s fast\n\t"
11209 "FLD $src\n\t"
11210 "CALL d2i_wrapper\n"
11211 "fast:" %}
11212 // DPR2I_encoding works for FPR2I
11213 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11214 ins_pipe( pipe_slow );
11215 %}
11217 // Convert a float in xmm to an int reg.
11218 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11219 predicate(UseSSE>=1);
11220 match(Set dst (ConvF2I src));
11221 effect( KILL tmp, KILL cr );
11222 format %{ "CVTTSS2SI $dst, $src\n\t"
11223 "CMP $dst,0x80000000\n\t"
11224 "JNE,s fast\n\t"
11225 "SUB ESP, 4\n\t"
11226 "MOVSS [ESP], $src\n\t"
11227 "FLD [ESP]\n\t"
11228 "ADD ESP, 4\n\t"
11229 "CALL d2i_wrapper\n"
11230 "fast:" %}
11231 ins_encode %{
11232 Label fast;
11233 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11234 __ cmpl($dst$$Register, 0x80000000);
11235 __ jccb(Assembler::notEqual, fast);
11236 __ subptr(rsp, 4);
11237 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11238 __ fld_s(Address(rsp, 0));
11239 __ addptr(rsp, 4);
11240 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11241 __ bind(fast);
11242 %}
11243 ins_pipe( pipe_slow );
11244 %}
11246 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11247 predicate(UseSSE==0);
11248 match(Set dst (ConvF2L src));
11249 effect( KILL cr );
11250 format %{ "FLD $src\t# Convert float to long\n\t"
11251 "FLDCW trunc mode\n\t"
11252 "SUB ESP,8\n\t"
11253 "FISTp [ESP + #0]\n\t"
11254 "FLDCW std/24-bit mode\n\t"
11255 "POP EAX\n\t"
11256 "POP EDX\n\t"
11257 "CMP EDX,0x80000000\n\t"
11258 "JNE,s fast\n\t"
11259 "TEST EAX,EAX\n\t"
11260 "JNE,s fast\n\t"
11261 "FLD $src\n\t"
11262 "CALL d2l_wrapper\n"
11263 "fast:" %}
11264 // DPR2L_encoding works for FPR2L
11265 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11266 ins_pipe( pipe_slow );
11267 %}
11269 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11270 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11271 predicate (UseSSE>=1);
11272 match(Set dst (ConvF2L src));
11273 effect( KILL cr );
11274 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11275 "MOVSS [ESP],$src\n\t"
11276 "FLD_S [ESP]\n\t"
11277 "FLDCW trunc mode\n\t"
11278 "FISTp [ESP + #0]\n\t"
11279 "FLDCW std/24-bit mode\n\t"
11280 "POP EAX\n\t"
11281 "POP EDX\n\t"
11282 "CMP EDX,0x80000000\n\t"
11283 "JNE,s fast\n\t"
11284 "TEST EAX,EAX\n\t"
11285 "JNE,s fast\n\t"
11286 "SUB ESP,4\t# Convert float to long\n\t"
11287 "MOVSS [ESP],$src\n\t"
11288 "FLD_S [ESP]\n\t"
11289 "ADD ESP,4\n\t"
11290 "CALL d2l_wrapper\n"
11291 "fast:" %}
11292 ins_encode %{
11293 Label fast;
11294 __ subptr(rsp, 8);
11295 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11296 __ fld_s(Address(rsp, 0));
11297 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11298 __ fistp_d(Address(rsp, 0));
11299 // Restore the rounding mode, mask the exception
11300 if (Compile::current()->in_24_bit_fp_mode()) {
11301 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11302 } else {
11303 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11304 }
11305 // Load the converted long, adjust CPU stack
11306 __ pop(rax);
11307 __ pop(rdx);
11308 __ cmpl(rdx, 0x80000000);
11309 __ jccb(Assembler::notEqual, fast);
11310 __ testl(rax, rax);
11311 __ jccb(Assembler::notEqual, fast);
11312 __ subptr(rsp, 4);
11313 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11314 __ fld_s(Address(rsp, 0));
11315 __ addptr(rsp, 4);
11316 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11317 __ bind(fast);
11318 %}
11319 ins_pipe( pipe_slow );
11320 %}
11322 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11323 predicate( UseSSE<=1 );
11324 match(Set dst (ConvI2D src));
11325 format %{ "FILD $src\n\t"
11326 "FSTP $dst" %}
11327 opcode(0xDB, 0x0); /* DB /0 */
11328 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11329 ins_pipe( fpu_reg_mem );
11330 %}
11332 instruct convI2D_reg(regD dst, eRegI src) %{
11333 predicate( UseSSE>=2 && !UseXmmI2D );
11334 match(Set dst (ConvI2D src));
11335 format %{ "CVTSI2SD $dst,$src" %}
11336 ins_encode %{
11337 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11338 %}
11339 ins_pipe( pipe_slow );
11340 %}
11342 instruct convI2D_mem(regD dst, memory mem) %{
11343 predicate( UseSSE>=2 );
11344 match(Set dst (ConvI2D (LoadI mem)));
11345 format %{ "CVTSI2SD $dst,$mem" %}
11346 ins_encode %{
11347 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11348 %}
11349 ins_pipe( pipe_slow );
11350 %}
11352 instruct convXI2D_reg(regD dst, eRegI src)
11353 %{
11354 predicate( UseSSE>=2 && UseXmmI2D );
11355 match(Set dst (ConvI2D src));
11357 format %{ "MOVD $dst,$src\n\t"
11358 "CVTDQ2PD $dst,$dst\t# i2d" %}
11359 ins_encode %{
11360 __ movdl($dst$$XMMRegister, $src$$Register);
11361 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11362 %}
11363 ins_pipe(pipe_slow); // XXX
11364 %}
11366 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11367 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11368 match(Set dst (ConvI2D (LoadI mem)));
11369 format %{ "FILD $mem\n\t"
11370 "FSTP $dst" %}
11371 opcode(0xDB); /* DB /0 */
11372 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11373 Pop_Reg_DPR(dst));
11374 ins_pipe( fpu_reg_mem );
11375 %}
11377 // Convert a byte to a float; no rounding step needed.
11378 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11379 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11380 match(Set dst (ConvI2F src));
11381 format %{ "FILD $src\n\t"
11382 "FSTP $dst" %}
11384 opcode(0xDB, 0x0); /* DB /0 */
11385 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11386 ins_pipe( fpu_reg_mem );
11387 %}
11389 // In 24-bit mode, force exponent rounding by storing back out
11390 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11391 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11392 match(Set dst (ConvI2F src));
11393 ins_cost(200);
11394 format %{ "FILD $src\n\t"
11395 "FSTP_S $dst" %}
11396 opcode(0xDB, 0x0); /* DB /0 */
11397 ins_encode( Push_Mem_I(src),
11398 Pop_Mem_FPR(dst));
11399 ins_pipe( fpu_mem_mem );
11400 %}
11402 // In 24-bit mode, force exponent rounding by storing back out
11403 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11404 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11405 match(Set dst (ConvI2F (LoadI mem)));
11406 ins_cost(200);
11407 format %{ "FILD $mem\n\t"
11408 "FSTP_S $dst" %}
11409 opcode(0xDB); /* DB /0 */
11410 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11411 Pop_Mem_FPR(dst));
11412 ins_pipe( fpu_mem_mem );
11413 %}
11415 // This instruction does not round to 24-bits
11416 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11417 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11418 match(Set dst (ConvI2F src));
11419 format %{ "FILD $src\n\t"
11420 "FSTP $dst" %}
11421 opcode(0xDB, 0x0); /* DB /0 */
11422 ins_encode( Push_Mem_I(src),
11423 Pop_Reg_FPR(dst));
11424 ins_pipe( fpu_reg_mem );
11425 %}
11427 // This instruction does not round to 24-bits
11428 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11429 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11430 match(Set dst (ConvI2F (LoadI mem)));
11431 format %{ "FILD $mem\n\t"
11432 "FSTP $dst" %}
11433 opcode(0xDB); /* DB /0 */
11434 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11435 Pop_Reg_FPR(dst));
11436 ins_pipe( fpu_reg_mem );
11437 %}
11439 // Convert an int to a float in xmm; no rounding step needed.
11440 instruct convI2F_reg(regF dst, eRegI src) %{
11441 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11442 match(Set dst (ConvI2F src));
11443 format %{ "CVTSI2SS $dst, $src" %}
11444 ins_encode %{
11445 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11446 %}
11447 ins_pipe( pipe_slow );
11448 %}
11450 instruct convXI2F_reg(regF dst, eRegI src)
11451 %{
11452 predicate( UseSSE>=2 && UseXmmI2F );
11453 match(Set dst (ConvI2F src));
11455 format %{ "MOVD $dst,$src\n\t"
11456 "CVTDQ2PS $dst,$dst\t# i2f" %}
11457 ins_encode %{
11458 __ movdl($dst$$XMMRegister, $src$$Register);
11459 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11460 %}
11461 ins_pipe(pipe_slow); // XXX
11462 %}
11464 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11465 match(Set dst (ConvI2L src));
11466 effect(KILL cr);
11467 ins_cost(375);
11468 format %{ "MOV $dst.lo,$src\n\t"
11469 "MOV $dst.hi,$src\n\t"
11470 "SAR $dst.hi,31" %}
11471 ins_encode(convert_int_long(dst,src));
11472 ins_pipe( ialu_reg_reg_long );
11473 %}
11475 // Zero-extend convert int to long
11476 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11477 match(Set dst (AndL (ConvI2L src) mask) );
11478 effect( KILL flags );
11479 ins_cost(250);
11480 format %{ "MOV $dst.lo,$src\n\t"
11481 "XOR $dst.hi,$dst.hi" %}
11482 opcode(0x33); // XOR
11483 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11484 ins_pipe( ialu_reg_reg_long );
11485 %}
11487 // Zero-extend long
11488 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11489 match(Set dst (AndL src mask) );
11490 effect( KILL flags );
11491 ins_cost(250);
11492 format %{ "MOV $dst.lo,$src.lo\n\t"
11493 "XOR $dst.hi,$dst.hi\n\t" %}
11494 opcode(0x33); // XOR
11495 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11496 ins_pipe( ialu_reg_reg_long );
11497 %}
11499 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11500 predicate (UseSSE<=1);
11501 match(Set dst (ConvL2D src));
11502 effect( KILL cr );
11503 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11504 "PUSH $src.lo\n\t"
11505 "FILD ST,[ESP + #0]\n\t"
11506 "ADD ESP,8\n\t"
11507 "FSTP_D $dst\t# D-round" %}
11508 opcode(0xDF, 0x5); /* DF /5 */
11509 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11510 ins_pipe( pipe_slow );
11511 %}
11513 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11514 predicate (UseSSE>=2);
11515 match(Set dst (ConvL2D src));
11516 effect( KILL cr );
11517 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11518 "PUSH $src.lo\n\t"
11519 "FILD_D [ESP]\n\t"
11520 "FSTP_D [ESP]\n\t"
11521 "MOVSD $dst,[ESP]\n\t"
11522 "ADD ESP,8" %}
11523 opcode(0xDF, 0x5); /* DF /5 */
11524 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11525 ins_pipe( pipe_slow );
11526 %}
11528 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11529 predicate (UseSSE>=1);
11530 match(Set dst (ConvL2F src));
11531 effect( KILL cr );
11532 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11533 "PUSH $src.lo\n\t"
11534 "FILD_D [ESP]\n\t"
11535 "FSTP_S [ESP]\n\t"
11536 "MOVSS $dst,[ESP]\n\t"
11537 "ADD ESP,8" %}
11538 opcode(0xDF, 0x5); /* DF /5 */
11539 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11540 ins_pipe( pipe_slow );
11541 %}
11543 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11544 match(Set dst (ConvL2F src));
11545 effect( KILL cr );
11546 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11547 "PUSH $src.lo\n\t"
11548 "FILD ST,[ESP + #0]\n\t"
11549 "ADD ESP,8\n\t"
11550 "FSTP_S $dst\t# F-round" %}
11551 opcode(0xDF, 0x5); /* DF /5 */
11552 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11553 ins_pipe( pipe_slow );
11554 %}
11556 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11557 match(Set dst (ConvL2I src));
11558 effect( DEF dst, USE src );
11559 format %{ "MOV $dst,$src.lo" %}
11560 ins_encode(enc_CopyL_Lo(dst,src));
11561 ins_pipe( ialu_reg_reg );
11562 %}
11565 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11566 match(Set dst (MoveF2I src));
11567 effect( DEF dst, USE src );
11568 ins_cost(100);
11569 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11570 ins_encode %{
11571 __ movl($dst$$Register, Address(rsp, $src$$disp));
11572 %}
11573 ins_pipe( ialu_reg_mem );
11574 %}
11576 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11577 predicate(UseSSE==0);
11578 match(Set dst (MoveF2I src));
11579 effect( DEF dst, USE src );
11581 ins_cost(125);
11582 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11583 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11584 ins_pipe( fpu_mem_reg );
11585 %}
11587 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11588 predicate(UseSSE>=1);
11589 match(Set dst (MoveF2I src));
11590 effect( DEF dst, USE src );
11592 ins_cost(95);
11593 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11594 ins_encode %{
11595 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11596 %}
11597 ins_pipe( pipe_slow );
11598 %}
11600 instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{
11601 predicate(UseSSE>=2);
11602 match(Set dst (MoveF2I src));
11603 effect( DEF dst, USE src );
11604 ins_cost(85);
11605 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11606 ins_encode %{
11607 __ movdl($dst$$Register, $src$$XMMRegister);
11608 %}
11609 ins_pipe( pipe_slow );
11610 %}
11612 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11613 match(Set dst (MoveI2F src));
11614 effect( DEF dst, USE src );
11616 ins_cost(100);
11617 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11618 ins_encode %{
11619 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11620 %}
11621 ins_pipe( ialu_mem_reg );
11622 %}
11625 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11626 predicate(UseSSE==0);
11627 match(Set dst (MoveI2F src));
11628 effect(DEF dst, USE src);
11630 ins_cost(125);
11631 format %{ "FLD_S $src\n\t"
11632 "FSTP $dst\t# MoveI2F_stack_reg" %}
11633 opcode(0xD9); /* D9 /0, FLD m32real */
11634 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11635 Pop_Reg_FPR(dst) );
11636 ins_pipe( fpu_reg_mem );
11637 %}
11639 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11640 predicate(UseSSE>=1);
11641 match(Set dst (MoveI2F src));
11642 effect( DEF dst, USE src );
11644 ins_cost(95);
11645 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11646 ins_encode %{
11647 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11648 %}
11649 ins_pipe( pipe_slow );
11650 %}
11652 instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{
11653 predicate(UseSSE>=2);
11654 match(Set dst (MoveI2F src));
11655 effect( DEF dst, USE src );
11657 ins_cost(85);
11658 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11659 ins_encode %{
11660 __ movdl($dst$$XMMRegister, $src$$Register);
11661 %}
11662 ins_pipe( pipe_slow );
11663 %}
11665 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11666 match(Set dst (MoveD2L src));
11667 effect(DEF dst, USE src);
11669 ins_cost(250);
11670 format %{ "MOV $dst.lo,$src\n\t"
11671 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11672 opcode(0x8B, 0x8B);
11673 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11674 ins_pipe( ialu_mem_long_reg );
11675 %}
11677 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11678 predicate(UseSSE<=1);
11679 match(Set dst (MoveD2L src));
11680 effect(DEF dst, USE src);
11682 ins_cost(125);
11683 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11684 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11685 ins_pipe( fpu_mem_reg );
11686 %}
11688 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11689 predicate(UseSSE>=2);
11690 match(Set dst (MoveD2L src));
11691 effect(DEF dst, USE src);
11692 ins_cost(95);
11693 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11694 ins_encode %{
11695 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11696 %}
11697 ins_pipe( pipe_slow );
11698 %}
11700 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11701 predicate(UseSSE>=2);
11702 match(Set dst (MoveD2L src));
11703 effect(DEF dst, USE src, TEMP tmp);
11704 ins_cost(85);
11705 format %{ "MOVD $dst.lo,$src\n\t"
11706 "PSHUFLW $tmp,$src,0x4E\n\t"
11707 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11708 ins_encode %{
11709 __ movdl($dst$$Register, $src$$XMMRegister);
11710 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11711 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11712 %}
11713 ins_pipe( pipe_slow );
11714 %}
11716 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11717 match(Set dst (MoveL2D src));
11718 effect(DEF dst, USE src);
11720 ins_cost(200);
11721 format %{ "MOV $dst,$src.lo\n\t"
11722 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11723 opcode(0x89, 0x89);
11724 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11725 ins_pipe( ialu_mem_long_reg );
11726 %}
11729 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11730 predicate(UseSSE<=1);
11731 match(Set dst (MoveL2D src));
11732 effect(DEF dst, USE src);
11733 ins_cost(125);
11735 format %{ "FLD_D $src\n\t"
11736 "FSTP $dst\t# MoveL2D_stack_reg" %}
11737 opcode(0xDD); /* DD /0, FLD m64real */
11738 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11739 Pop_Reg_DPR(dst) );
11740 ins_pipe( fpu_reg_mem );
11741 %}
11744 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11745 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11746 match(Set dst (MoveL2D src));
11747 effect(DEF dst, USE src);
11749 ins_cost(95);
11750 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11751 ins_encode %{
11752 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11753 %}
11754 ins_pipe( pipe_slow );
11755 %}
11757 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11758 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11759 match(Set dst (MoveL2D src));
11760 effect(DEF dst, USE src);
11762 ins_cost(95);
11763 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11764 ins_encode %{
11765 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11766 %}
11767 ins_pipe( pipe_slow );
11768 %}
11770 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11771 predicate(UseSSE>=2);
11772 match(Set dst (MoveL2D src));
11773 effect(TEMP dst, USE src, TEMP tmp);
11774 ins_cost(85);
11775 format %{ "MOVD $dst,$src.lo\n\t"
11776 "MOVD $tmp,$src.hi\n\t"
11777 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11778 ins_encode %{
11779 __ movdl($dst$$XMMRegister, $src$$Register);
11780 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11781 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11782 %}
11783 ins_pipe( pipe_slow );
11784 %}
11786 // Replicate scalar to packed byte (1 byte) values in xmm
11787 instruct Repl8B_reg(regD dst, regD src) %{
11788 predicate(UseSSE>=2);
11789 match(Set dst (Replicate8B src));
11790 format %{ "MOVDQA $dst,$src\n\t"
11791 "PUNPCKLBW $dst,$dst\n\t"
11792 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11793 ins_encode %{
11794 if ($dst$$reg != $src$$reg) {
11795 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
11796 }
11797 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11798 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11799 %}
11800 ins_pipe( pipe_slow );
11801 %}
11803 // Replicate scalar to packed byte (1 byte) values in xmm
11804 instruct Repl8B_eRegI(regD dst, eRegI src) %{
11805 predicate(UseSSE>=2);
11806 match(Set dst (Replicate8B src));
11807 format %{ "MOVD $dst,$src\n\t"
11808 "PUNPCKLBW $dst,$dst\n\t"
11809 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11810 ins_encode %{
11811 __ movdl($dst$$XMMRegister, $src$$Register);
11812 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
11813 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11814 %}
11815 ins_pipe( pipe_slow );
11816 %}
11818 // Replicate scalar zero to packed byte (1 byte) values in xmm
11819 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11820 predicate(UseSSE>=2);
11821 match(Set dst (Replicate8B zero));
11822 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11823 ins_encode %{
11824 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11825 %}
11826 ins_pipe( fpu_reg_reg );
11827 %}
11829 // Replicate scalar to packed shore (2 byte) values in xmm
11830 instruct Repl4S_reg(regD dst, regD src) %{
11831 predicate(UseSSE>=2);
11832 match(Set dst (Replicate4S src));
11833 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11834 ins_encode %{
11835 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11836 %}
11837 ins_pipe( fpu_reg_reg );
11838 %}
11840 // Replicate scalar to packed shore (2 byte) values in xmm
11841 instruct Repl4S_eRegI(regD dst, eRegI src) %{
11842 predicate(UseSSE>=2);
11843 match(Set dst (Replicate4S src));
11844 format %{ "MOVD $dst,$src\n\t"
11845 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11846 ins_encode %{
11847 __ movdl($dst$$XMMRegister, $src$$Register);
11848 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11849 %}
11850 ins_pipe( fpu_reg_reg );
11851 %}
11853 // Replicate scalar zero to packed short (2 byte) values in xmm
11854 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11855 predicate(UseSSE>=2);
11856 match(Set dst (Replicate4S zero));
11857 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11858 ins_encode %{
11859 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11860 %}
11861 ins_pipe( fpu_reg_reg );
11862 %}
11864 // Replicate scalar to packed char (2 byte) values in xmm
11865 instruct Repl4C_reg(regD dst, regD src) %{
11866 predicate(UseSSE>=2);
11867 match(Set dst (Replicate4C src));
11868 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11869 ins_encode %{
11870 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11871 %}
11872 ins_pipe( fpu_reg_reg );
11873 %}
11875 // Replicate scalar to packed char (2 byte) values in xmm
11876 instruct Repl4C_eRegI(regD dst, eRegI src) %{
11877 predicate(UseSSE>=2);
11878 match(Set dst (Replicate4C src));
11879 format %{ "MOVD $dst,$src\n\t"
11880 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11881 ins_encode %{
11882 __ movdl($dst$$XMMRegister, $src$$Register);
11883 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11884 %}
11885 ins_pipe( fpu_reg_reg );
11886 %}
11888 // Replicate scalar zero to packed char (2 byte) values in xmm
11889 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11890 predicate(UseSSE>=2);
11891 match(Set dst (Replicate4C zero));
11892 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11893 ins_encode %{
11894 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11895 %}
11896 ins_pipe( fpu_reg_reg );
11897 %}
11899 // Replicate scalar to packed integer (4 byte) values in xmm
11900 instruct Repl2I_reg(regD dst, regD src) %{
11901 predicate(UseSSE>=2);
11902 match(Set dst (Replicate2I src));
11903 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11904 ins_encode %{
11905 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
11906 %}
11907 ins_pipe( fpu_reg_reg );
11908 %}
11910 // Replicate scalar to packed integer (4 byte) values in xmm
11911 instruct Repl2I_eRegI(regD dst, eRegI src) %{
11912 predicate(UseSSE>=2);
11913 match(Set dst (Replicate2I src));
11914 format %{ "MOVD $dst,$src\n\t"
11915 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11916 ins_encode %{
11917 __ movdl($dst$$XMMRegister, $src$$Register);
11918 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
11919 %}
11920 ins_pipe( fpu_reg_reg );
11921 %}
11923 // Replicate scalar zero to packed integer (2 byte) values in xmm
11924 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11925 predicate(UseSSE>=2);
11926 match(Set dst (Replicate2I zero));
11927 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11928 ins_encode %{
11929 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11930 %}
11931 ins_pipe( fpu_reg_reg );
11932 %}
11934 // Replicate scalar to packed single precision floating point values in xmm
11935 instruct Repl2F_reg(regD dst, regD src) %{
11936 predicate(UseSSE>=2);
11937 match(Set dst (Replicate2F src));
11938 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11939 ins_encode %{
11940 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11941 %}
11942 ins_pipe( fpu_reg_reg );
11943 %}
11945 // Replicate scalar to packed single precision floating point values in xmm
11946 instruct Repl2F_regF(regD dst, regF src) %{
11947 predicate(UseSSE>=2);
11948 match(Set dst (Replicate2F src));
11949 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11950 ins_encode %{
11951 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
11952 %}
11953 ins_pipe( fpu_reg_reg );
11954 %}
11956 // Replicate scalar to packed single precision floating point values in xmm
11957 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11958 predicate(UseSSE>=2);
11959 match(Set dst (Replicate2F zero));
11960 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11961 ins_encode %{
11962 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11963 %}
11964 ins_pipe( fpu_reg_reg );
11965 %}
11967 // =======================================================================
11968 // fast clearing of an array
11969 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11970 match(Set dummy (ClearArray cnt base));
11971 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11972 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11973 "XOR EAX,EAX\n\t"
11974 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11975 opcode(0,0x4);
11976 ins_encode( Opcode(0xD1), RegOpc(ECX),
11977 OpcRegReg(0x33,EAX,EAX),
11978 Opcode(0xF3), Opcode(0xAB) );
11979 ins_pipe( pipe_slow );
11980 %}
11982 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11983 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11984 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11985 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11987 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11988 ins_encode %{
11989 __ string_compare($str1$$Register, $str2$$Register,
11990 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11991 $tmp1$$XMMRegister);
11992 %}
11993 ins_pipe( pipe_slow );
11994 %}
11996 // fast string equals
11997 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11998 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11999 match(Set result (StrEquals (Binary str1 str2) cnt));
12000 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12002 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12003 ins_encode %{
12004 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12005 $cnt$$Register, $result$$Register, $tmp3$$Register,
12006 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12007 %}
12008 ins_pipe( pipe_slow );
12009 %}
12011 // fast search of substring with known size.
12012 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
12013 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
12014 predicate(UseSSE42Intrinsics);
12015 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12016 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12018 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
12019 ins_encode %{
12020 int icnt2 = (int)$int_cnt2$$constant;
12021 if (icnt2 >= 8) {
12022 // IndexOf for constant substrings with size >= 8 elements
12023 // which don't need to be loaded through stack.
12024 __ string_indexofC8($str1$$Register, $str2$$Register,
12025 $cnt1$$Register, $cnt2$$Register,
12026 icnt2, $result$$Register,
12027 $vec$$XMMRegister, $tmp$$Register);
12028 } else {
12029 // Small strings are loaded through stack if they cross page boundary.
12030 __ string_indexof($str1$$Register, $str2$$Register,
12031 $cnt1$$Register, $cnt2$$Register,
12032 icnt2, $result$$Register,
12033 $vec$$XMMRegister, $tmp$$Register);
12034 }
12035 %}
12036 ins_pipe( pipe_slow );
12037 %}
12039 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12040 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
12041 predicate(UseSSE42Intrinsics);
12042 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12043 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12045 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12046 ins_encode %{
12047 __ string_indexof($str1$$Register, $str2$$Register,
12048 $cnt1$$Register, $cnt2$$Register,
12049 (-1), $result$$Register,
12050 $vec$$XMMRegister, $tmp$$Register);
12051 %}
12052 ins_pipe( pipe_slow );
12053 %}
12055 // fast array equals
12056 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12057 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12058 %{
12059 match(Set result (AryEq ary1 ary2));
12060 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12061 //ins_cost(300);
12063 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12064 ins_encode %{
12065 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12066 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12067 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12068 %}
12069 ins_pipe( pipe_slow );
12070 %}
12072 //----------Control Flow Instructions------------------------------------------
12073 // Signed compare Instructions
12074 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12075 match(Set cr (CmpI op1 op2));
12076 effect( DEF cr, USE op1, USE op2 );
12077 format %{ "CMP $op1,$op2" %}
12078 opcode(0x3B); /* Opcode 3B /r */
12079 ins_encode( OpcP, RegReg( op1, op2) );
12080 ins_pipe( ialu_cr_reg_reg );
12081 %}
12083 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12084 match(Set cr (CmpI op1 op2));
12085 effect( DEF cr, USE op1 );
12086 format %{ "CMP $op1,$op2" %}
12087 opcode(0x81,0x07); /* Opcode 81 /7 */
12088 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12089 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12090 ins_pipe( ialu_cr_reg_imm );
12091 %}
12093 // Cisc-spilled version of cmpI_eReg
12094 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12095 match(Set cr (CmpI op1 (LoadI op2)));
12097 format %{ "CMP $op1,$op2" %}
12098 ins_cost(500);
12099 opcode(0x3B); /* Opcode 3B /r */
12100 ins_encode( OpcP, RegMem( op1, op2) );
12101 ins_pipe( ialu_cr_reg_mem );
12102 %}
12104 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12105 match(Set cr (CmpI src zero));
12106 effect( DEF cr, USE src );
12108 format %{ "TEST $src,$src" %}
12109 opcode(0x85);
12110 ins_encode( OpcP, RegReg( src, src ) );
12111 ins_pipe( ialu_cr_reg_imm );
12112 %}
12114 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12115 match(Set cr (CmpI (AndI src con) zero));
12117 format %{ "TEST $src,$con" %}
12118 opcode(0xF7,0x00);
12119 ins_encode( OpcP, RegOpc(src), Con32(con) );
12120 ins_pipe( ialu_cr_reg_imm );
12121 %}
12123 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12124 match(Set cr (CmpI (AndI src mem) zero));
12126 format %{ "TEST $src,$mem" %}
12127 opcode(0x85);
12128 ins_encode( OpcP, RegMem( src, mem ) );
12129 ins_pipe( ialu_cr_reg_mem );
12130 %}
12132 // Unsigned compare Instructions; really, same as signed except they
12133 // produce an eFlagsRegU instead of eFlagsReg.
12134 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12135 match(Set cr (CmpU op1 op2));
12137 format %{ "CMPu $op1,$op2" %}
12138 opcode(0x3B); /* Opcode 3B /r */
12139 ins_encode( OpcP, RegReg( op1, op2) );
12140 ins_pipe( ialu_cr_reg_reg );
12141 %}
12143 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12144 match(Set cr (CmpU op1 op2));
12146 format %{ "CMPu $op1,$op2" %}
12147 opcode(0x81,0x07); /* Opcode 81 /7 */
12148 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12149 ins_pipe( ialu_cr_reg_imm );
12150 %}
12152 // // Cisc-spilled version of cmpU_eReg
12153 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12154 match(Set cr (CmpU op1 (LoadI op2)));
12156 format %{ "CMPu $op1,$op2" %}
12157 ins_cost(500);
12158 opcode(0x3B); /* Opcode 3B /r */
12159 ins_encode( OpcP, RegMem( op1, op2) );
12160 ins_pipe( ialu_cr_reg_mem );
12161 %}
12163 // // Cisc-spilled version of cmpU_eReg
12164 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12165 // match(Set cr (CmpU (LoadI op1) op2));
12166 //
12167 // format %{ "CMPu $op1,$op2" %}
12168 // ins_cost(500);
12169 // opcode(0x39); /* Opcode 39 /r */
12170 // ins_encode( OpcP, RegMem( op1, op2) );
12171 //%}
12173 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12174 match(Set cr (CmpU src zero));
12176 format %{ "TESTu $src,$src" %}
12177 opcode(0x85);
12178 ins_encode( OpcP, RegReg( src, src ) );
12179 ins_pipe( ialu_cr_reg_imm );
12180 %}
12182 // Unsigned pointer compare Instructions
12183 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12184 match(Set cr (CmpP op1 op2));
12186 format %{ "CMPu $op1,$op2" %}
12187 opcode(0x3B); /* Opcode 3B /r */
12188 ins_encode( OpcP, RegReg( op1, op2) );
12189 ins_pipe( ialu_cr_reg_reg );
12190 %}
12192 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12193 match(Set cr (CmpP op1 op2));
12195 format %{ "CMPu $op1,$op2" %}
12196 opcode(0x81,0x07); /* Opcode 81 /7 */
12197 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12198 ins_pipe( ialu_cr_reg_imm );
12199 %}
12201 // // Cisc-spilled version of cmpP_eReg
12202 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12203 match(Set cr (CmpP op1 (LoadP op2)));
12205 format %{ "CMPu $op1,$op2" %}
12206 ins_cost(500);
12207 opcode(0x3B); /* Opcode 3B /r */
12208 ins_encode( OpcP, RegMem( op1, op2) );
12209 ins_pipe( ialu_cr_reg_mem );
12210 %}
12212 // // Cisc-spilled version of cmpP_eReg
12213 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12214 // match(Set cr (CmpP (LoadP op1) op2));
12215 //
12216 // format %{ "CMPu $op1,$op2" %}
12217 // ins_cost(500);
12218 // opcode(0x39); /* Opcode 39 /r */
12219 // ins_encode( OpcP, RegMem( op1, op2) );
12220 //%}
12222 // Compare raw pointer (used in out-of-heap check).
12223 // Only works because non-oop pointers must be raw pointers
12224 // and raw pointers have no anti-dependencies.
12225 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12226 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12227 match(Set cr (CmpP op1 (LoadP op2)));
12229 format %{ "CMPu $op1,$op2" %}
12230 opcode(0x3B); /* Opcode 3B /r */
12231 ins_encode( OpcP, RegMem( op1, op2) );
12232 ins_pipe( ialu_cr_reg_mem );
12233 %}
12235 //
12236 // This will generate a signed flags result. This should be ok
12237 // since any compare to a zero should be eq/neq.
12238 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12239 match(Set cr (CmpP src zero));
12241 format %{ "TEST $src,$src" %}
12242 opcode(0x85);
12243 ins_encode( OpcP, RegReg( src, src ) );
12244 ins_pipe( ialu_cr_reg_imm );
12245 %}
12247 // Cisc-spilled version of testP_reg
12248 // This will generate a signed flags result. This should be ok
12249 // since any compare to a zero should be eq/neq.
12250 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12251 match(Set cr (CmpP (LoadP op) zero));
12253 format %{ "TEST $op,0xFFFFFFFF" %}
12254 ins_cost(500);
12255 opcode(0xF7); /* Opcode F7 /0 */
12256 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12257 ins_pipe( ialu_cr_reg_imm );
12258 %}
12260 // Yanked all unsigned pointer compare operations.
12261 // Pointer compares are done with CmpP which is already unsigned.
12263 //----------Max and Min--------------------------------------------------------
12264 // Min Instructions
12265 ////
12266 // *** Min and Max using the conditional move are slower than the
12267 // *** branch version on a Pentium III.
12268 // // Conditional move for min
12269 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12270 // effect( USE_DEF op2, USE op1, USE cr );
12271 // format %{ "CMOVlt $op2,$op1\t! min" %}
12272 // opcode(0x4C,0x0F);
12273 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12274 // ins_pipe( pipe_cmov_reg );
12275 //%}
12276 //
12277 //// Min Register with Register (P6 version)
12278 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12279 // predicate(VM_Version::supports_cmov() );
12280 // match(Set op2 (MinI op1 op2));
12281 // ins_cost(200);
12282 // expand %{
12283 // eFlagsReg cr;
12284 // compI_eReg(cr,op1,op2);
12285 // cmovI_reg_lt(op2,op1,cr);
12286 // %}
12287 //%}
12289 // Min Register with Register (generic version)
12290 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12291 match(Set dst (MinI dst src));
12292 effect(KILL flags);
12293 ins_cost(300);
12295 format %{ "MIN $dst,$src" %}
12296 opcode(0xCC);
12297 ins_encode( min_enc(dst,src) );
12298 ins_pipe( pipe_slow );
12299 %}
12301 // Max Register with Register
12302 // *** Min and Max using the conditional move are slower than the
12303 // *** branch version on a Pentium III.
12304 // // Conditional move for max
12305 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12306 // effect( USE_DEF op2, USE op1, USE cr );
12307 // format %{ "CMOVgt $op2,$op1\t! max" %}
12308 // opcode(0x4F,0x0F);
12309 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12310 // ins_pipe( pipe_cmov_reg );
12311 //%}
12312 //
12313 // // Max Register with Register (P6 version)
12314 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12315 // predicate(VM_Version::supports_cmov() );
12316 // match(Set op2 (MaxI op1 op2));
12317 // ins_cost(200);
12318 // expand %{
12319 // eFlagsReg cr;
12320 // compI_eReg(cr,op1,op2);
12321 // cmovI_reg_gt(op2,op1,cr);
12322 // %}
12323 //%}
12325 // Max Register with Register (generic version)
12326 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12327 match(Set dst (MaxI dst src));
12328 effect(KILL flags);
12329 ins_cost(300);
12331 format %{ "MAX $dst,$src" %}
12332 opcode(0xCC);
12333 ins_encode( max_enc(dst,src) );
12334 ins_pipe( pipe_slow );
12335 %}
12337 // ============================================================================
12338 // Counted Loop limit node which represents exact final iterator value.
12339 // Note: the resulting value should fit into integer range since
12340 // counted loops have limit check on overflow.
12341 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12342 match(Set limit (LoopLimit (Binary init limit) stride));
12343 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12344 ins_cost(300);
12346 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12347 ins_encode %{
12348 int strd = (int)$stride$$constant;
12349 assert(strd != 1 && strd != -1, "sanity");
12350 int m1 = (strd > 0) ? 1 : -1;
12351 // Convert limit to long (EAX:EDX)
12352 __ cdql();
12353 // Convert init to long (init:tmp)
12354 __ movl($tmp$$Register, $init$$Register);
12355 __ sarl($tmp$$Register, 31);
12356 // $limit - $init
12357 __ subl($limit$$Register, $init$$Register);
12358 __ sbbl($limit_hi$$Register, $tmp$$Register);
12359 // + ($stride - 1)
12360 if (strd > 0) {
12361 __ addl($limit$$Register, (strd - 1));
12362 __ adcl($limit_hi$$Register, 0);
12363 __ movl($tmp$$Register, strd);
12364 } else {
12365 __ addl($limit$$Register, (strd + 1));
12366 __ adcl($limit_hi$$Register, -1);
12367 __ lneg($limit_hi$$Register, $limit$$Register);
12368 __ movl($tmp$$Register, -strd);
12369 }
12370 // signed devision: (EAX:EDX) / pos_stride
12371 __ idivl($tmp$$Register);
12372 if (strd < 0) {
12373 // restore sign
12374 __ negl($tmp$$Register);
12375 }
12376 // (EAX) * stride
12377 __ mull($tmp$$Register);
12378 // + init (ignore upper bits)
12379 __ addl($limit$$Register, $init$$Register);
12380 %}
12381 ins_pipe( pipe_slow );
12382 %}
12384 // ============================================================================
12385 // Branch Instructions
12386 // Jump Table
12387 instruct jumpXtnd(eRegI switch_val) %{
12388 match(Jump switch_val);
12389 ins_cost(350);
12390 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12391 ins_encode %{
12392 // Jump to Address(table_base + switch_reg)
12393 Address index(noreg, $switch_val$$Register, Address::times_1);
12394 __ jump(ArrayAddress($constantaddress, index));
12395 %}
12396 ins_pipe(pipe_jmp);
12397 %}
12399 // Jump Direct - Label defines a relative address from JMP+1
12400 instruct jmpDir(label labl) %{
12401 match(Goto);
12402 effect(USE labl);
12404 ins_cost(300);
12405 format %{ "JMP $labl" %}
12406 size(5);
12407 ins_encode %{
12408 Label* L = $labl$$label;
12409 __ jmp(*L, false); // Always long jump
12410 %}
12411 ins_pipe( pipe_jmp );
12412 %}
12414 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12415 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12416 match(If cop cr);
12417 effect(USE labl);
12419 ins_cost(300);
12420 format %{ "J$cop $labl" %}
12421 size(6);
12422 ins_encode %{
12423 Label* L = $labl$$label;
12424 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12425 %}
12426 ins_pipe( pipe_jcc );
12427 %}
12429 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12430 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12431 match(CountedLoopEnd cop cr);
12432 effect(USE labl);
12434 ins_cost(300);
12435 format %{ "J$cop $labl\t# Loop end" %}
12436 size(6);
12437 ins_encode %{
12438 Label* L = $labl$$label;
12439 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12440 %}
12441 ins_pipe( pipe_jcc );
12442 %}
12444 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12445 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12446 match(CountedLoopEnd cop cmp);
12447 effect(USE labl);
12449 ins_cost(300);
12450 format %{ "J$cop,u $labl\t# Loop end" %}
12451 size(6);
12452 ins_encode %{
12453 Label* L = $labl$$label;
12454 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12455 %}
12456 ins_pipe( pipe_jcc );
12457 %}
12459 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12460 match(CountedLoopEnd cop cmp);
12461 effect(USE labl);
12463 ins_cost(200);
12464 format %{ "J$cop,u $labl\t# Loop end" %}
12465 size(6);
12466 ins_encode %{
12467 Label* L = $labl$$label;
12468 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12469 %}
12470 ins_pipe( pipe_jcc );
12471 %}
12473 // Jump Direct Conditional - using unsigned comparison
12474 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12475 match(If cop cmp);
12476 effect(USE labl);
12478 ins_cost(300);
12479 format %{ "J$cop,u $labl" %}
12480 size(6);
12481 ins_encode %{
12482 Label* L = $labl$$label;
12483 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12484 %}
12485 ins_pipe(pipe_jcc);
12486 %}
12488 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12489 match(If cop cmp);
12490 effect(USE labl);
12492 ins_cost(200);
12493 format %{ "J$cop,u $labl" %}
12494 size(6);
12495 ins_encode %{
12496 Label* L = $labl$$label;
12497 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12498 %}
12499 ins_pipe(pipe_jcc);
12500 %}
12502 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12503 match(If cop cmp);
12504 effect(USE labl);
12506 ins_cost(200);
12507 format %{ $$template
12508 if ($cop$$cmpcode == Assembler::notEqual) {
12509 $$emit$$"JP,u $labl\n\t"
12510 $$emit$$"J$cop,u $labl"
12511 } else {
12512 $$emit$$"JP,u done\n\t"
12513 $$emit$$"J$cop,u $labl\n\t"
12514 $$emit$$"done:"
12515 }
12516 %}
12517 ins_encode %{
12518 Label* l = $labl$$label;
12519 if ($cop$$cmpcode == Assembler::notEqual) {
12520 __ jcc(Assembler::parity, *l, false);
12521 __ jcc(Assembler::notEqual, *l, false);
12522 } else if ($cop$$cmpcode == Assembler::equal) {
12523 Label done;
12524 __ jccb(Assembler::parity, done);
12525 __ jcc(Assembler::equal, *l, false);
12526 __ bind(done);
12527 } else {
12528 ShouldNotReachHere();
12529 }
12530 %}
12531 ins_pipe(pipe_jcc);
12532 %}
12534 // ============================================================================
12535 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12536 // array for an instance of the superklass. Set a hidden internal cache on a
12537 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12538 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12539 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12540 match(Set result (PartialSubtypeCheck sub super));
12541 effect( KILL rcx, KILL cr );
12543 ins_cost(1100); // slightly larger than the next version
12544 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12545 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12546 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12547 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12548 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12549 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12550 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12551 "miss:\t" %}
12553 opcode(0x1); // Force a XOR of EDI
12554 ins_encode( enc_PartialSubtypeCheck() );
12555 ins_pipe( pipe_slow );
12556 %}
12558 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12559 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12560 effect( KILL rcx, KILL result );
12562 ins_cost(1000);
12563 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12564 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12565 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12566 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12567 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12568 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12569 "miss:\t" %}
12571 opcode(0x0); // No need to XOR EDI
12572 ins_encode( enc_PartialSubtypeCheck() );
12573 ins_pipe( pipe_slow );
12574 %}
12576 // ============================================================================
12577 // Branch Instructions -- short offset versions
12578 //
12579 // These instructions are used to replace jumps of a long offset (the default
12580 // match) with jumps of a shorter offset. These instructions are all tagged
12581 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12582 // match rules in general matching. Instead, the ADLC generates a conversion
12583 // method in the MachNode which can be used to do in-place replacement of the
12584 // long variant with the shorter variant. The compiler will determine if a
12585 // branch can be taken by the is_short_branch_offset() predicate in the machine
12586 // specific code section of the file.
12588 // Jump Direct - Label defines a relative address from JMP+1
12589 instruct jmpDir_short(label labl) %{
12590 match(Goto);
12591 effect(USE labl);
12593 ins_cost(300);
12594 format %{ "JMP,s $labl" %}
12595 size(2);
12596 ins_encode %{
12597 Label* L = $labl$$label;
12598 __ jmpb(*L);
12599 %}
12600 ins_pipe( pipe_jmp );
12601 ins_short_branch(1);
12602 %}
12604 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12605 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12606 match(If cop cr);
12607 effect(USE labl);
12609 ins_cost(300);
12610 format %{ "J$cop,s $labl" %}
12611 size(2);
12612 ins_encode %{
12613 Label* L = $labl$$label;
12614 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12615 %}
12616 ins_pipe( pipe_jcc );
12617 ins_short_branch(1);
12618 %}
12620 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12621 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12622 match(CountedLoopEnd cop cr);
12623 effect(USE labl);
12625 ins_cost(300);
12626 format %{ "J$cop,s $labl\t# Loop end" %}
12627 size(2);
12628 ins_encode %{
12629 Label* L = $labl$$label;
12630 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12631 %}
12632 ins_pipe( pipe_jcc );
12633 ins_short_branch(1);
12634 %}
12636 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12637 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12638 match(CountedLoopEnd cop cmp);
12639 effect(USE labl);
12641 ins_cost(300);
12642 format %{ "J$cop,us $labl\t# Loop end" %}
12643 size(2);
12644 ins_encode %{
12645 Label* L = $labl$$label;
12646 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12647 %}
12648 ins_pipe( pipe_jcc );
12649 ins_short_branch(1);
12650 %}
12652 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12653 match(CountedLoopEnd cop cmp);
12654 effect(USE labl);
12656 ins_cost(300);
12657 format %{ "J$cop,us $labl\t# Loop end" %}
12658 size(2);
12659 ins_encode %{
12660 Label* L = $labl$$label;
12661 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12662 %}
12663 ins_pipe( pipe_jcc );
12664 ins_short_branch(1);
12665 %}
12667 // Jump Direct Conditional - using unsigned comparison
12668 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12669 match(If cop cmp);
12670 effect(USE labl);
12672 ins_cost(300);
12673 format %{ "J$cop,us $labl" %}
12674 size(2);
12675 ins_encode %{
12676 Label* L = $labl$$label;
12677 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12678 %}
12679 ins_pipe( pipe_jcc );
12680 ins_short_branch(1);
12681 %}
12683 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12684 match(If cop cmp);
12685 effect(USE labl);
12687 ins_cost(300);
12688 format %{ "J$cop,us $labl" %}
12689 size(2);
12690 ins_encode %{
12691 Label* L = $labl$$label;
12692 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12693 %}
12694 ins_pipe( pipe_jcc );
12695 ins_short_branch(1);
12696 %}
12698 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12699 match(If cop cmp);
12700 effect(USE labl);
12702 ins_cost(300);
12703 format %{ $$template
12704 if ($cop$$cmpcode == Assembler::notEqual) {
12705 $$emit$$"JP,u,s $labl\n\t"
12706 $$emit$$"J$cop,u,s $labl"
12707 } else {
12708 $$emit$$"JP,u,s done\n\t"
12709 $$emit$$"J$cop,u,s $labl\n\t"
12710 $$emit$$"done:"
12711 }
12712 %}
12713 size(4);
12714 ins_encode %{
12715 Label* l = $labl$$label;
12716 if ($cop$$cmpcode == Assembler::notEqual) {
12717 __ jccb(Assembler::parity, *l);
12718 __ jccb(Assembler::notEqual, *l);
12719 } else if ($cop$$cmpcode == Assembler::equal) {
12720 Label done;
12721 __ jccb(Assembler::parity, done);
12722 __ jccb(Assembler::equal, *l);
12723 __ bind(done);
12724 } else {
12725 ShouldNotReachHere();
12726 }
12727 %}
12728 ins_pipe(pipe_jcc);
12729 ins_short_branch(1);
12730 %}
12732 // ============================================================================
12733 // Long Compare
12734 //
12735 // Currently we hold longs in 2 registers. Comparing such values efficiently
12736 // is tricky. The flavor of compare used depends on whether we are testing
12737 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12738 // The GE test is the negated LT test. The LE test can be had by commuting
12739 // the operands (yielding a GE test) and then negating; negate again for the
12740 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12741 // NE test is negated from that.
12743 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12744 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12745 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12746 // are collapsed internally in the ADLC's dfa-gen code. The match for
12747 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12748 // foo match ends up with the wrong leaf. One fix is to not match both
12749 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12750 // both forms beat the trinary form of long-compare and both are very useful
12751 // on Intel which has so few registers.
12753 // Manifest a CmpL result in an integer register. Very painful.
12754 // This is the test to avoid.
12755 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12756 match(Set dst (CmpL3 src1 src2));
12757 effect( KILL flags );
12758 ins_cost(1000);
12759 format %{ "XOR $dst,$dst\n\t"
12760 "CMP $src1.hi,$src2.hi\n\t"
12761 "JLT,s m_one\n\t"
12762 "JGT,s p_one\n\t"
12763 "CMP $src1.lo,$src2.lo\n\t"
12764 "JB,s m_one\n\t"
12765 "JEQ,s done\n"
12766 "p_one:\tINC $dst\n\t"
12767 "JMP,s done\n"
12768 "m_one:\tDEC $dst\n"
12769 "done:" %}
12770 ins_encode %{
12771 Label p_one, m_one, done;
12772 __ xorptr($dst$$Register, $dst$$Register);
12773 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12774 __ jccb(Assembler::less, m_one);
12775 __ jccb(Assembler::greater, p_one);
12776 __ cmpl($src1$$Register, $src2$$Register);
12777 __ jccb(Assembler::below, m_one);
12778 __ jccb(Assembler::equal, done);
12779 __ bind(p_one);
12780 __ incrementl($dst$$Register);
12781 __ jmpb(done);
12782 __ bind(m_one);
12783 __ decrementl($dst$$Register);
12784 __ bind(done);
12785 %}
12786 ins_pipe( pipe_slow );
12787 %}
12789 //======
12790 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12791 // compares. Can be used for LE or GT compares by reversing arguments.
12792 // NOT GOOD FOR EQ/NE tests.
12793 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12794 match( Set flags (CmpL src zero ));
12795 ins_cost(100);
12796 format %{ "TEST $src.hi,$src.hi" %}
12797 opcode(0x85);
12798 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12799 ins_pipe( ialu_cr_reg_reg );
12800 %}
12802 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12803 // compares. Can be used for LE or GT compares by reversing arguments.
12804 // NOT GOOD FOR EQ/NE tests.
12805 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12806 match( Set flags (CmpL src1 src2 ));
12807 effect( TEMP tmp );
12808 ins_cost(300);
12809 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12810 "MOV $tmp,$src1.hi\n\t"
12811 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12812 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12813 ins_pipe( ialu_cr_reg_reg );
12814 %}
12816 // Long compares reg < zero/req OR reg >= zero/req.
12817 // Just a wrapper for a normal branch, plus the predicate test.
12818 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12819 match(If cmp flags);
12820 effect(USE labl);
12821 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12822 expand %{
12823 jmpCon(cmp,flags,labl); // JLT or JGE...
12824 %}
12825 %}
12827 // Compare 2 longs and CMOVE longs.
12828 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12829 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12830 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12831 ins_cost(400);
12832 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12833 "CMOV$cmp $dst.hi,$src.hi" %}
12834 opcode(0x0F,0x40);
12835 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12836 ins_pipe( pipe_cmov_reg_long );
12837 %}
12839 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12840 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12841 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12842 ins_cost(500);
12843 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12844 "CMOV$cmp $dst.hi,$src.hi" %}
12845 opcode(0x0F,0x40);
12846 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12847 ins_pipe( pipe_cmov_reg_long );
12848 %}
12850 // Compare 2 longs and CMOVE ints.
12851 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12852 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12853 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12854 ins_cost(200);
12855 format %{ "CMOV$cmp $dst,$src" %}
12856 opcode(0x0F,0x40);
12857 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12858 ins_pipe( pipe_cmov_reg );
12859 %}
12861 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12862 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12863 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12864 ins_cost(250);
12865 format %{ "CMOV$cmp $dst,$src" %}
12866 opcode(0x0F,0x40);
12867 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12868 ins_pipe( pipe_cmov_mem );
12869 %}
12871 // Compare 2 longs and CMOVE ints.
12872 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12873 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12874 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12875 ins_cost(200);
12876 format %{ "CMOV$cmp $dst,$src" %}
12877 opcode(0x0F,0x40);
12878 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12879 ins_pipe( pipe_cmov_reg );
12880 %}
12882 // Compare 2 longs and CMOVE doubles
12883 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12884 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12885 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12886 ins_cost(200);
12887 expand %{
12888 fcmovDPR_regS(cmp,flags,dst,src);
12889 %}
12890 %}
12892 // Compare 2 longs and CMOVE doubles
12893 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12894 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12895 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12896 ins_cost(200);
12897 expand %{
12898 fcmovD_regS(cmp,flags,dst,src);
12899 %}
12900 %}
12902 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12903 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12904 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12905 ins_cost(200);
12906 expand %{
12907 fcmovFPR_regS(cmp,flags,dst,src);
12908 %}
12909 %}
12911 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12912 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12913 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12914 ins_cost(200);
12915 expand %{
12916 fcmovF_regS(cmp,flags,dst,src);
12917 %}
12918 %}
12920 //======
12921 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12922 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12923 match( Set flags (CmpL src zero ));
12924 effect(TEMP tmp);
12925 ins_cost(200);
12926 format %{ "MOV $tmp,$src.lo\n\t"
12927 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12928 ins_encode( long_cmp_flags0( src, tmp ) );
12929 ins_pipe( ialu_reg_reg_long );
12930 %}
12932 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12933 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12934 match( Set flags (CmpL src1 src2 ));
12935 ins_cost(200+300);
12936 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12937 "JNE,s skip\n\t"
12938 "CMP $src1.hi,$src2.hi\n\t"
12939 "skip:\t" %}
12940 ins_encode( long_cmp_flags1( src1, src2 ) );
12941 ins_pipe( ialu_cr_reg_reg );
12942 %}
12944 // Long compare reg == zero/reg OR reg != zero/reg
12945 // Just a wrapper for a normal branch, plus the predicate test.
12946 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12947 match(If cmp flags);
12948 effect(USE labl);
12949 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12950 expand %{
12951 jmpCon(cmp,flags,labl); // JEQ or JNE...
12952 %}
12953 %}
12955 // Compare 2 longs and CMOVE longs.
12956 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12957 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12958 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12959 ins_cost(400);
12960 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12961 "CMOV$cmp $dst.hi,$src.hi" %}
12962 opcode(0x0F,0x40);
12963 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12964 ins_pipe( pipe_cmov_reg_long );
12965 %}
12967 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12968 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12969 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12970 ins_cost(500);
12971 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12972 "CMOV$cmp $dst.hi,$src.hi" %}
12973 opcode(0x0F,0x40);
12974 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12975 ins_pipe( pipe_cmov_reg_long );
12976 %}
12978 // Compare 2 longs and CMOVE ints.
12979 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12980 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12981 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12982 ins_cost(200);
12983 format %{ "CMOV$cmp $dst,$src" %}
12984 opcode(0x0F,0x40);
12985 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12986 ins_pipe( pipe_cmov_reg );
12987 %}
12989 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
12990 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12991 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12992 ins_cost(250);
12993 format %{ "CMOV$cmp $dst,$src" %}
12994 opcode(0x0F,0x40);
12995 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12996 ins_pipe( pipe_cmov_mem );
12997 %}
12999 // Compare 2 longs and CMOVE ints.
13000 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13001 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13002 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13003 ins_cost(200);
13004 format %{ "CMOV$cmp $dst,$src" %}
13005 opcode(0x0F,0x40);
13006 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13007 ins_pipe( pipe_cmov_reg );
13008 %}
13010 // Compare 2 longs and CMOVE doubles
13011 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
13012 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13013 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13014 ins_cost(200);
13015 expand %{
13016 fcmovDPR_regS(cmp,flags,dst,src);
13017 %}
13018 %}
13020 // Compare 2 longs and CMOVE doubles
13021 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13022 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13023 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13024 ins_cost(200);
13025 expand %{
13026 fcmovD_regS(cmp,flags,dst,src);
13027 %}
13028 %}
13030 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
13031 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13032 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13033 ins_cost(200);
13034 expand %{
13035 fcmovFPR_regS(cmp,flags,dst,src);
13036 %}
13037 %}
13039 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13040 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13041 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13042 ins_cost(200);
13043 expand %{
13044 fcmovF_regS(cmp,flags,dst,src);
13045 %}
13046 %}
13048 //======
13049 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13050 // Same as cmpL_reg_flags_LEGT except must negate src
13051 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13052 match( Set flags (CmpL src zero ));
13053 effect( TEMP tmp );
13054 ins_cost(300);
13055 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13056 "CMP $tmp,$src.lo\n\t"
13057 "SBB $tmp,$src.hi\n\t" %}
13058 ins_encode( long_cmp_flags3(src, tmp) );
13059 ins_pipe( ialu_reg_reg_long );
13060 %}
13062 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13063 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13064 // requires a commuted test to get the same result.
13065 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13066 match( Set flags (CmpL src1 src2 ));
13067 effect( TEMP tmp );
13068 ins_cost(300);
13069 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13070 "MOV $tmp,$src2.hi\n\t"
13071 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13072 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13073 ins_pipe( ialu_cr_reg_reg );
13074 %}
13076 // Long compares reg < zero/req OR reg >= zero/req.
13077 // Just a wrapper for a normal branch, plus the predicate test
13078 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13079 match(If cmp flags);
13080 effect(USE labl);
13081 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13082 ins_cost(300);
13083 expand %{
13084 jmpCon(cmp,flags,labl); // JGT or JLE...
13085 %}
13086 %}
13088 // Compare 2 longs and CMOVE longs.
13089 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13090 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13091 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13092 ins_cost(400);
13093 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13094 "CMOV$cmp $dst.hi,$src.hi" %}
13095 opcode(0x0F,0x40);
13096 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13097 ins_pipe( pipe_cmov_reg_long );
13098 %}
13100 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13101 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13102 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13103 ins_cost(500);
13104 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13105 "CMOV$cmp $dst.hi,$src.hi+4" %}
13106 opcode(0x0F,0x40);
13107 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13108 ins_pipe( pipe_cmov_reg_long );
13109 %}
13111 // Compare 2 longs and CMOVE ints.
13112 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13113 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13114 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13115 ins_cost(200);
13116 format %{ "CMOV$cmp $dst,$src" %}
13117 opcode(0x0F,0x40);
13118 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13119 ins_pipe( pipe_cmov_reg );
13120 %}
13122 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13123 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13124 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13125 ins_cost(250);
13126 format %{ "CMOV$cmp $dst,$src" %}
13127 opcode(0x0F,0x40);
13128 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13129 ins_pipe( pipe_cmov_mem );
13130 %}
13132 // Compare 2 longs and CMOVE ptrs.
13133 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13134 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13135 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13136 ins_cost(200);
13137 format %{ "CMOV$cmp $dst,$src" %}
13138 opcode(0x0F,0x40);
13139 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13140 ins_pipe( pipe_cmov_reg );
13141 %}
13143 // Compare 2 longs and CMOVE doubles
13144 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
13145 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13146 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13147 ins_cost(200);
13148 expand %{
13149 fcmovDPR_regS(cmp,flags,dst,src);
13150 %}
13151 %}
13153 // Compare 2 longs and CMOVE doubles
13154 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13155 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13156 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13157 ins_cost(200);
13158 expand %{
13159 fcmovD_regS(cmp,flags,dst,src);
13160 %}
13161 %}
13163 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
13164 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13165 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13166 ins_cost(200);
13167 expand %{
13168 fcmovFPR_regS(cmp,flags,dst,src);
13169 %}
13170 %}
13173 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13174 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13175 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13176 ins_cost(200);
13177 expand %{
13178 fcmovF_regS(cmp,flags,dst,src);
13179 %}
13180 %}
13183 // ============================================================================
13184 // Procedure Call/Return Instructions
13185 // Call Java Static Instruction
13186 // Note: If this code changes, the corresponding ret_addr_offset() and
13187 // compute_padding() functions will have to be adjusted.
13188 instruct CallStaticJavaDirect(method meth) %{
13189 match(CallStaticJava);
13190 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13191 effect(USE meth);
13193 ins_cost(300);
13194 format %{ "CALL,static " %}
13195 opcode(0xE8); /* E8 cd */
13196 ins_encode( pre_call_FPU,
13197 Java_Static_Call( meth ),
13198 call_epilog,
13199 post_call_FPU );
13200 ins_pipe( pipe_slow );
13201 ins_alignment(4);
13202 %}
13204 // Call Java Static Instruction (method handle version)
13205 // Note: If this code changes, the corresponding ret_addr_offset() and
13206 // compute_padding() functions will have to be adjusted.
13207 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13208 match(CallStaticJava);
13209 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13210 effect(USE meth);
13211 // EBP is saved by all callees (for interpreter stack correction).
13212 // We use it here for a similar purpose, in {preserve,restore}_SP.
13214 ins_cost(300);
13215 format %{ "CALL,static/MethodHandle " %}
13216 opcode(0xE8); /* E8 cd */
13217 ins_encode( pre_call_FPU,
13218 preserve_SP,
13219 Java_Static_Call( meth ),
13220 restore_SP,
13221 call_epilog,
13222 post_call_FPU );
13223 ins_pipe( pipe_slow );
13224 ins_alignment(4);
13225 %}
13227 // Call Java Dynamic Instruction
13228 // Note: If this code changes, the corresponding ret_addr_offset() and
13229 // compute_padding() functions will have to be adjusted.
13230 instruct CallDynamicJavaDirect(method meth) %{
13231 match(CallDynamicJava);
13232 effect(USE meth);
13234 ins_cost(300);
13235 format %{ "MOV EAX,(oop)-1\n\t"
13236 "CALL,dynamic" %}
13237 opcode(0xE8); /* E8 cd */
13238 ins_encode( pre_call_FPU,
13239 Java_Dynamic_Call( meth ),
13240 call_epilog,
13241 post_call_FPU );
13242 ins_pipe( pipe_slow );
13243 ins_alignment(4);
13244 %}
13246 // Call Runtime Instruction
13247 instruct CallRuntimeDirect(method meth) %{
13248 match(CallRuntime );
13249 effect(USE meth);
13251 ins_cost(300);
13252 format %{ "CALL,runtime " %}
13253 opcode(0xE8); /* E8 cd */
13254 // Use FFREEs to clear entries in float stack
13255 ins_encode( pre_call_FPU,
13256 FFree_Float_Stack_All,
13257 Java_To_Runtime( meth ),
13258 post_call_FPU );
13259 ins_pipe( pipe_slow );
13260 %}
13262 // Call runtime without safepoint
13263 instruct CallLeafDirect(method meth) %{
13264 match(CallLeaf);
13265 effect(USE meth);
13267 ins_cost(300);
13268 format %{ "CALL_LEAF,runtime " %}
13269 opcode(0xE8); /* E8 cd */
13270 ins_encode( pre_call_FPU,
13271 FFree_Float_Stack_All,
13272 Java_To_Runtime( meth ),
13273 Verify_FPU_For_Leaf, post_call_FPU );
13274 ins_pipe( pipe_slow );
13275 %}
13277 instruct CallLeafNoFPDirect(method meth) %{
13278 match(CallLeafNoFP);
13279 effect(USE meth);
13281 ins_cost(300);
13282 format %{ "CALL_LEAF_NOFP,runtime " %}
13283 opcode(0xE8); /* E8 cd */
13284 ins_encode(Java_To_Runtime(meth));
13285 ins_pipe( pipe_slow );
13286 %}
13289 // Return Instruction
13290 // Remove the return address & jump to it.
13291 instruct Ret() %{
13292 match(Return);
13293 format %{ "RET" %}
13294 opcode(0xC3);
13295 ins_encode(OpcP);
13296 ins_pipe( pipe_jmp );
13297 %}
13299 // Tail Call; Jump from runtime stub to Java code.
13300 // Also known as an 'interprocedural jump'.
13301 // Target of jump will eventually return to caller.
13302 // TailJump below removes the return address.
13303 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13304 match(TailCall jump_target method_oop );
13305 ins_cost(300);
13306 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13307 opcode(0xFF, 0x4); /* Opcode FF /4 */
13308 ins_encode( OpcP, RegOpc(jump_target) );
13309 ins_pipe( pipe_jmp );
13310 %}
13313 // Tail Jump; remove the return address; jump to target.
13314 // TailCall above leaves the return address around.
13315 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13316 match( TailJump jump_target ex_oop );
13317 ins_cost(300);
13318 format %{ "POP EDX\t# pop return address into dummy\n\t"
13319 "JMP $jump_target " %}
13320 opcode(0xFF, 0x4); /* Opcode FF /4 */
13321 ins_encode( enc_pop_rdx,
13322 OpcP, RegOpc(jump_target) );
13323 ins_pipe( pipe_jmp );
13324 %}
13326 // Create exception oop: created by stack-crawling runtime code.
13327 // Created exception is now available to this handler, and is setup
13328 // just prior to jumping to this handler. No code emitted.
13329 instruct CreateException( eAXRegP ex_oop )
13330 %{
13331 match(Set ex_oop (CreateEx));
13333 size(0);
13334 // use the following format syntax
13335 format %{ "# exception oop is in EAX; no code emitted" %}
13336 ins_encode();
13337 ins_pipe( empty );
13338 %}
13341 // Rethrow exception:
13342 // The exception oop will come in the first argument position.
13343 // Then JUMP (not call) to the rethrow stub code.
13344 instruct RethrowException()
13345 %{
13346 match(Rethrow);
13348 // use the following format syntax
13349 format %{ "JMP rethrow_stub" %}
13350 ins_encode(enc_rethrow);
13351 ins_pipe( pipe_jmp );
13352 %}
13354 // inlined locking and unlocking
13357 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13358 match( Set cr (FastLock object box) );
13359 effect( TEMP tmp, TEMP scr, USE_KILL box );
13360 ins_cost(300);
13361 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13362 ins_encode( Fast_Lock(object,box,tmp,scr) );
13363 ins_pipe( pipe_slow );
13364 %}
13366 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13367 match( Set cr (FastUnlock object box) );
13368 effect( TEMP tmp, USE_KILL box );
13369 ins_cost(300);
13370 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13371 ins_encode( Fast_Unlock(object,box,tmp) );
13372 ins_pipe( pipe_slow );
13373 %}
13377 // ============================================================================
13378 // Safepoint Instruction
13379 instruct safePoint_poll(eFlagsReg cr) %{
13380 match(SafePoint);
13381 effect(KILL cr);
13383 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13384 // On SPARC that might be acceptable as we can generate the address with
13385 // just a sethi, saving an or. By polling at offset 0 we can end up
13386 // putting additional pressure on the index-0 in the D$. Because of
13387 // alignment (just like the situation at hand) the lower indices tend
13388 // to see more traffic. It'd be better to change the polling address
13389 // to offset 0 of the last $line in the polling page.
13391 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13392 ins_cost(125);
13393 size(6) ;
13394 ins_encode( Safepoint_Poll() );
13395 ins_pipe( ialu_reg_mem );
13396 %}
13399 // ============================================================================
13400 // This name is KNOWN by the ADLC and cannot be changed.
13401 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13402 // for this guy.
13403 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13404 match(Set dst (ThreadLocal));
13405 effect(DEF dst, KILL cr);
13407 format %{ "MOV $dst, Thread::current()" %}
13408 ins_encode %{
13409 Register dstReg = as_Register($dst$$reg);
13410 __ get_thread(dstReg);
13411 %}
13412 ins_pipe( ialu_reg_fat );
13413 %}
13417 //----------PEEPHOLE RULES-----------------------------------------------------
13418 // These must follow all instruction definitions as they use the names
13419 // defined in the instructions definitions.
13420 //
13421 // peepmatch ( root_instr_name [preceding_instruction]* );
13422 //
13423 // peepconstraint %{
13424 // (instruction_number.operand_name relational_op instruction_number.operand_name
13425 // [, ...] );
13426 // // instruction numbers are zero-based using left to right order in peepmatch
13427 //
13428 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13429 // // provide an instruction_number.operand_name for each operand that appears
13430 // // in the replacement instruction's match rule
13431 //
13432 // ---------VM FLAGS---------------------------------------------------------
13433 //
13434 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13435 //
13436 // Each peephole rule is given an identifying number starting with zero and
13437 // increasing by one in the order seen by the parser. An individual peephole
13438 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13439 // on the command-line.
13440 //
13441 // ---------CURRENT LIMITATIONS----------------------------------------------
13442 //
13443 // Only match adjacent instructions in same basic block
13444 // Only equality constraints
13445 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13446 // Only one replacement instruction
13447 //
13448 // ---------EXAMPLE----------------------------------------------------------
13449 //
13450 // // pertinent parts of existing instructions in architecture description
13451 // instruct movI(eRegI dst, eRegI src) %{
13452 // match(Set dst (CopyI src));
13453 // %}
13454 //
13455 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13456 // match(Set dst (AddI dst src));
13457 // effect(KILL cr);
13458 // %}
13459 //
13460 // // Change (inc mov) to lea
13461 // peephole %{
13462 // // increment preceeded by register-register move
13463 // peepmatch ( incI_eReg movI );
13464 // // require that the destination register of the increment
13465 // // match the destination register of the move
13466 // peepconstraint ( 0.dst == 1.dst );
13467 // // construct a replacement instruction that sets
13468 // // the destination to ( move's source register + one )
13469 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13470 // %}
13471 //
13472 // Implementation no longer uses movX instructions since
13473 // machine-independent system no longer uses CopyX nodes.
13474 //
13475 // peephole %{
13476 // peepmatch ( incI_eReg movI );
13477 // peepconstraint ( 0.dst == 1.dst );
13478 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13479 // %}
13480 //
13481 // peephole %{
13482 // peepmatch ( decI_eReg movI );
13483 // peepconstraint ( 0.dst == 1.dst );
13484 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13485 // %}
13486 //
13487 // peephole %{
13488 // peepmatch ( addI_eReg_imm movI );
13489 // peepconstraint ( 0.dst == 1.dst );
13490 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13491 // %}
13492 //
13493 // peephole %{
13494 // peepmatch ( addP_eReg_imm movP );
13495 // peepconstraint ( 0.dst == 1.dst );
13496 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13497 // %}
13499 // // Change load of spilled value to only a spill
13500 // instruct storeI(memory mem, eRegI src) %{
13501 // match(Set mem (StoreI mem src));
13502 // %}
13503 //
13504 // instruct loadI(eRegI dst, memory mem) %{
13505 // match(Set dst (LoadI mem));
13506 // %}
13507 //
13508 peephole %{
13509 peepmatch ( loadI storeI );
13510 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13511 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13512 %}
13514 //----------SMARTSPILL RULES---------------------------------------------------
13515 // These must follow all instruction definitions as they use the names
13516 // defined in the instructions definitions.