Tue, 24 Dec 2013 11:48:39 -0800
8029233: Update copyright year to match last edit in jdk8 hotspot repository for 2013
Summary: Copyright year updated for files modified during 2013
Reviewed-by: twisti, iveresov
1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 extern bool use_block_zeroing(Node* count);
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
471 %}
473 source %{
474 #define __ _masm.
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
532 // ****************************************************************************
534 // REQUIRED FUNCTIONALITY
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedClassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
563 } else {
564 klass_load_size = 1*BytesPerInstWord;
565 }
566 if (Assembler::is_simm13(v_off)) {
567 return klass_load_size +
568 (2*BytesPerInstWord + // ld_ptr, ld_ptr
569 NativeCall::instruction_size); // call; delay slot
570 } else {
571 return klass_load_size +
572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
573 NativeCall::instruction_size); // call; delay slot
574 }
575 }
576 }
578 int MachCallRuntimeNode::ret_addr_offset() {
579 #ifdef _LP64
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 #else
586 return NativeCall::instruction_size; // call; delay slot
587 #endif
588 }
590 // Indicate if the safepoint node needs the polling page as an input.
591 // Since Sparc does not have absolute addressing, it does.
592 bool SafePointNode::needs_polling_address_input() {
593 return true;
594 }
596 // emit an interrupt that is caught by the debugger (for debugging compiler)
597 void emit_break(CodeBuffer &cbuf) {
598 MacroAssembler _masm(&cbuf);
599 __ breakpoint_trap();
600 }
602 #ifndef PRODUCT
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
604 st->print("TA");
605 }
606 #endif
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
609 emit_break(cbuf);
610 }
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
613 return MachNode::size(ra_);
614 }
616 // Traceable jump
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
618 MacroAssembler _masm(&cbuf);
619 Register rdest = reg_to_register_object(jump_target);
620 __ JMP(rdest, 0);
621 __ delayed()->nop();
622 }
624 // Traceable jump and set exception pc
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
626 MacroAssembler _masm(&cbuf);
627 Register rdest = reg_to_register_object(jump_target);
628 __ JMP(rdest, 0);
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
630 }
632 void emit_nop(CodeBuffer &cbuf) {
633 MacroAssembler _masm(&cbuf);
634 __ nop();
635 }
637 void emit_illtrap(CodeBuffer &cbuf) {
638 MacroAssembler _masm(&cbuf);
639 __ illtrap(0);
640 }
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
644 assert(n->rule() != loadUB_rule, "");
646 intptr_t offset = 0;
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
648 const Node* addr = n->get_base_and_disp(offset, adr_type);
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 atype = atype->add_offset(offset);
653 assert(disp32 == offset, "wrong disp32");
654 return atype->_offset;
655 }
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
659 assert(n->rule() != loadUB_rule, "");
661 intptr_t offset = 0;
662 Node* addr = n->in(2);
663 assert(addr->bottom_type()->isa_oopptr() == atype, "");
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
665 Node* a = addr->in(2/*AddPNode::Address*/);
666 Node* o = addr->in(3/*AddPNode::Offset*/);
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
668 atype = a->bottom_type()->is_ptr()->add_offset(offset);
669 assert(atype->isa_oop_ptr(), "still an oop");
670 }
671 offset = atype->is_ptr()->_offset;
672 if (offset != Type::OffsetBot) offset += disp32;
673 return offset;
674 }
676 static inline jdouble replicate_immI(int con, int count, int width) {
677 // Load a constant replicated "count" times with width "width"
678 assert(count*width == 8 && width <= 4, "sanity");
679 int bit_width = width * 8;
680 jlong val = con;
681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
682 for (int i = 0; i < count - 1; i++) {
683 val |= (val << bit_width);
684 }
685 jdouble dval = *((jdouble*) &val); // coerce to double type
686 return dval;
687 }
689 static inline jdouble replicate_immF(float con) {
690 // Replicate float con 2 times and pack into vector.
691 int val = *((int*)&con);
692 jlong lval = val;
693 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
694 jdouble dval = *((jdouble*) &lval); // coerce to double type
695 return dval;
696 }
698 // Standard Sparc opcode form2 field breakdown
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits
701 int op = (f30 << 30) |
702 (f29 << 29) |
703 (f25 << 25) |
704 (f22 << 22) |
705 (f20 << 20) |
706 (f19 << 19) |
707 (f0 << 0);
708 cbuf.insts()->emit_int32(op);
709 }
711 // Standard Sparc opcode form2 field breakdown
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
713 f0 >>= 10; // Drop 10 bits
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits
715 int op = (f30 << 30) |
716 (f25 << 25) |
717 (f22 << 22) |
718 (f0 << 0);
719 cbuf.insts()->emit_int32(op);
720 }
722 // Standard Sparc opcode form3 field breakdown
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
724 int op = (f30 << 30) |
725 (f25 << 25) |
726 (f19 << 19) |
727 (f14 << 14) |
728 (f5 << 5) |
729 (f0 << 0);
730 cbuf.insts()->emit_int32(op);
731 }
733 // Standard Sparc opcode form3 field breakdown
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
735 simm13 &= (1<<13)-1; // Mask to 13 bits
736 int op = (f30 << 30) |
737 (f25 << 25) |
738 (f19 << 19) |
739 (f14 << 14) |
740 (1 << 13) | // bit to indicate immediate-mode
741 (simm13<<0);
742 cbuf.insts()->emit_int32(op);
743 }
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
746 simm10 &= (1<<10)-1; // Mask to 10 bits
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
748 }
750 #ifdef ASSERT
751 // Helper function for VerifyOops in emit_form3_mem_reg
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
753 warning("VerifyOops encountered unexpected instruction:");
754 n->dump(2);
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 }
757 #endif
760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of
766 // the current method activation. +VerifyOops complements techniques
767 // like ScavengeALot, because it eagerly inspects oops in transit,
768 // as they enter or leave the stack, as opposed to ScavengeALot,
769 // which inspects oops "at rest", in the stack or heap, at safepoints.
770 // For this reason, +VerifyOops can sometimes detect bugs very close
771 // to their point of creation. It can also serve as a cross-check
772 // on the validity of oop maps, when used toegether with ScavengeALot.
774 // It would be good to verify oops at other points, especially
775 // when an oop is used as a base pointer for a load or store.
776 // This is presently difficult, because it is hard to know when
777 // a base address is biased or not. (If we had such information,
778 // it would be easy and useful to make a two-argument version of
779 // verify_oop which unbiases the base, and performs verification.)
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
782 bool is_verified_oop_base = false;
783 bool is_verified_oop_load = false;
784 bool is_verified_oop_store = false;
785 int tmp_enc = -1;
786 if (VerifyOops && src1_enc != R_SP_enc) {
787 // classify the op, mainly for an assert check
788 int st_op = 0, ld_op = 0;
789 switch (primary) {
790 case Assembler::stb_op3: st_op = Op_StoreB; break;
791 case Assembler::sth_op3: st_op = Op_StoreC; break;
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
793 case Assembler::stw_op3: st_op = Op_StoreI; break;
794 case Assembler::std_op3: st_op = Op_StoreL; break;
795 case Assembler::stf_op3: st_op = Op_StoreF; break;
796 case Assembler::stdf_op3: st_op = Op_StoreD; break;
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
810 default: ShouldNotReachHere();
811 }
812 if (tertiary == REGP_OP) {
813 if (st_op == Op_StoreI) st_op = Op_StoreP;
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
815 else ShouldNotReachHere();
816 if (st_op) {
817 // a store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 Node* n2 = n->in(3);
820 if (n2 != NULL) {
821 const Type* t = n2->bottom_type();
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 } else {
825 // a load
826 const Type* t = n->bottom_type();
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
828 }
829 }
831 if (ld_op) {
832 // a Load
833 // inputs are (0:control, 1:memory, 2:address)
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
849 !(n->rule() == loadUB_rule)) {
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
851 }
852 } else if (st_op) {
853 // a Store
854 // inputs are (0:control, 1:memory, 2:address, 3:value)
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
912 uint index = src2_enc;
913 int disp = disp32;
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
916 disp += STACK_BIAS;
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
918 if (!Assembler::is_simm13(disp)) {
919 ra->C->record_method_not_compilable("unable to handle large constant offsets");
920 return;
921 }
922 }
924 // We should have a compiler bailout here rather than a guarantee.
925 // Better yet would be some mechanism to handle variable-size matches correctly.
926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
928 if( disp == 0 ) {
929 // use reg-reg form
930 // bit 13 is already zero
931 instr |= index;
932 } else {
933 // use reg-imm form
934 instr |= 0x00002000; // set bit 13 to one
935 instr |= disp & 0x1FFF;
936 }
938 cbuf.insts()->emit_int32(instr);
940 #ifdef ASSERT
941 {
942 MacroAssembler _masm(&cbuf);
943 if (is_verified_oop_base) {
944 __ verify_oop(reg_to_register_object(src1_enc));
945 }
946 if (is_verified_oop_store) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 if (tmp_enc != -1) {
950 __ mov(O7, reg_to_register_object(tmp_enc));
951 }
952 if (is_verified_oop_load) {
953 __ verify_oop(reg_to_register_object(dst_enc));
954 }
955 }
956 #endif
957 }
959 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
960 // The method which records debug information at every safepoint
961 // expects the call to be the first instruction in the snippet as
962 // it creates a PcDesc structure which tracks the offset of a call
963 // from the start of the codeBlob. This offset is computed as
964 // code_end() - code_begin() of the code which has been emitted
965 // so far.
966 // In this particular case we have skirted around the problem by
967 // putting the "mov" instruction in the delay slot but the problem
968 // may bite us again at some other point and a cleaner/generic
969 // solution using relocations would be needed.
970 MacroAssembler _masm(&cbuf);
971 __ set_inst_mark();
973 // We flush the current window just so that there is a valid stack copy
974 // the fact that the current window becomes active again instantly is
975 // not a problem there is nothing live in it.
977 #ifdef ASSERT
978 int startpos = __ offset();
979 #endif /* ASSERT */
981 __ call((address)entry_point, rtype);
983 if (preserve_g2) __ delayed()->mov(G2, L7);
984 else __ delayed()->nop();
986 if (preserve_g2) __ mov(L7, G2);
988 #ifdef ASSERT
989 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
990 #ifdef _LP64
991 // Trash argument dump slots.
992 __ set(0xb0b8ac0db0b8ac0d, G1);
993 __ mov(G1, G5);
994 __ stx(G1, SP, STACK_BIAS + 0x80);
995 __ stx(G1, SP, STACK_BIAS + 0x88);
996 __ stx(G1, SP, STACK_BIAS + 0x90);
997 __ stx(G1, SP, STACK_BIAS + 0x98);
998 __ stx(G1, SP, STACK_BIAS + 0xA0);
999 __ stx(G1, SP, STACK_BIAS + 0xA8);
1000 #else // _LP64
1001 // this is also a native call, so smash the first 7 stack locations,
1002 // and the various registers
1004 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1005 // while [SP+0x44..0x58] are the argument dump slots.
1006 __ set((intptr_t)0xbaadf00d, G1);
1007 __ mov(G1, G5);
1008 __ sllx(G1, 32, G1);
1009 __ or3(G1, G5, G1);
1010 __ mov(G1, G5);
1011 __ stx(G1, SP, 0x40);
1012 __ stx(G1, SP, 0x48);
1013 __ stx(G1, SP, 0x50);
1014 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1015 #endif // _LP64
1016 }
1017 #endif /*ASSERT*/
1018 }
1020 //=============================================================================
1021 // REQUIRED FUNCTIONALITY for encoding
1022 void emit_lo(CodeBuffer &cbuf, int val) { }
1023 void emit_hi(CodeBuffer &cbuf, int val) { }
1026 //=============================================================================
1027 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1029 int Compile::ConstantTable::calculate_table_base_offset() const {
1030 if (UseRDPCForConstantTableBase) {
1031 // The table base offset might be less but then it fits into
1032 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1033 return Assembler::min_simm13();
1034 } else {
1035 int offset = -(size() / 2);
1036 if (!Assembler::is_simm13(offset)) {
1037 offset = Assembler::min_simm13();
1038 }
1039 return offset;
1040 }
1041 }
1043 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1044 Compile* C = ra_->C;
1045 Compile::ConstantTable& constant_table = C->constant_table();
1046 MacroAssembler _masm(&cbuf);
1048 Register r = as_Register(ra_->get_encode(this));
1049 CodeSection* consts_section = __ code()->consts();
1050 int consts_size = consts_section->align_at_start(consts_section->size());
1051 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1053 if (UseRDPCForConstantTableBase) {
1054 // For the following RDPC logic to work correctly the consts
1055 // section must be allocated right before the insts section. This
1056 // assert checks for that. The layout and the SECT_* constants
1057 // are defined in src/share/vm/asm/codeBuffer.hpp.
1058 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1059 int insts_offset = __ offset();
1061 // Layout:
1062 //
1063 // |----------- consts section ------------|----------- insts section -----------...
1064 // |------ constant table -----|- padding -|------------------x----
1065 // \ current PC (RDPC instruction)
1066 // |<------------- consts_size ----------->|<- insts_offset ->|
1067 // \ table base
1068 // The table base offset is later added to the load displacement
1069 // so it has to be negative.
1070 int table_base_offset = -(consts_size + insts_offset);
1071 int disp;
1073 // If the displacement from the current PC to the constant table
1074 // base fits into simm13 we set the constant table base to the
1075 // current PC.
1076 if (Assembler::is_simm13(table_base_offset)) {
1077 constant_table.set_table_base_offset(table_base_offset);
1078 disp = 0;
1079 } else {
1080 // Otherwise we set the constant table base offset to the
1081 // maximum negative displacement of load instructions to keep
1082 // the disp as small as possible:
1083 //
1084 // |<------------- consts_size ----------->|<- insts_offset ->|
1085 // |<--------- min_simm13 --------->|<-------- disp --------->|
1086 // \ table base
1087 table_base_offset = Assembler::min_simm13();
1088 constant_table.set_table_base_offset(table_base_offset);
1089 disp = (consts_size + insts_offset) + table_base_offset;
1090 }
1092 __ rdpc(r);
1094 if (disp != 0) {
1095 assert(r != O7, "need temporary");
1096 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1097 }
1098 }
1099 else {
1100 // Materialize the constant table base.
1101 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1102 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1103 AddressLiteral base(baseaddr, rspec);
1104 __ set(base, r);
1105 }
1106 }
1108 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1109 if (UseRDPCForConstantTableBase) {
1110 // This is really the worst case but generally it's only 1 instruction.
1111 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1112 } else {
1113 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1114 }
1115 }
1117 #ifndef PRODUCT
1118 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1119 char reg[128];
1120 ra_->dump_register(this, reg);
1121 if (UseRDPCForConstantTableBase) {
1122 st->print("RDPC %s\t! constant table base", reg);
1123 } else {
1124 st->print("SET &constanttable,%s\t! constant table base", reg);
1125 }
1126 }
1127 #endif
1130 //=============================================================================
1132 #ifndef PRODUCT
1133 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1134 Compile* C = ra_->C;
1136 for (int i = 0; i < OptoPrologueNops; i++) {
1137 st->print_cr("NOP"); st->print("\t");
1138 }
1140 if( VerifyThread ) {
1141 st->print_cr("Verify_Thread"); st->print("\t");
1142 }
1144 size_t framesize = C->frame_slots() << LogBytesPerInt;
1146 // Calls to C2R adapters often do not accept exceptional returns.
1147 // We require that their callers must bang for them. But be careful, because
1148 // some VM calls (such as call site linkage) can use several kilobytes of
1149 // stack. But the stack safety zone should account for that.
1150 // See bugs 4446381, 4468289, 4497237.
1151 if (C->need_stack_bang(framesize)) {
1152 st->print_cr("! stack bang"); st->print("\t");
1153 }
1155 if (Assembler::is_simm13(-framesize)) {
1156 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1157 } else {
1158 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1159 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1160 st->print ("SAVE R_SP,R_G3,R_SP");
1161 }
1163 }
1164 #endif
1166 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1167 Compile* C = ra_->C;
1168 MacroAssembler _masm(&cbuf);
1170 for (int i = 0; i < OptoPrologueNops; i++) {
1171 __ nop();
1172 }
1174 __ verify_thread();
1176 size_t framesize = C->frame_slots() << LogBytesPerInt;
1177 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1178 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1180 // Calls to C2R adapters often do not accept exceptional returns.
1181 // We require that their callers must bang for them. But be careful, because
1182 // some VM calls (such as call site linkage) can use several kilobytes of
1183 // stack. But the stack safety zone should account for that.
1184 // See bugs 4446381, 4468289, 4497237.
1185 if (C->need_stack_bang(framesize)) {
1186 __ generate_stack_overflow_check(framesize);
1187 }
1189 if (Assembler::is_simm13(-framesize)) {
1190 __ save(SP, -framesize, SP);
1191 } else {
1192 __ sethi(-framesize & ~0x3ff, G3);
1193 __ add(G3, -framesize & 0x3ff, G3);
1194 __ save(SP, G3, SP);
1195 }
1196 C->set_frame_complete( __ offset() );
1198 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1199 // NOTE: We set the table base offset here because users might be
1200 // emitted before MachConstantBaseNode.
1201 Compile::ConstantTable& constant_table = C->constant_table();
1202 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1203 }
1204 }
1206 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1207 return MachNode::size(ra_);
1208 }
1210 int MachPrologNode::reloc() const {
1211 return 10; // a large enough number
1212 }
1214 //=============================================================================
1215 #ifndef PRODUCT
1216 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1217 Compile* C = ra_->C;
1219 if( do_polling() && ra_->C->is_method_compilation() ) {
1220 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1221 #ifdef _LP64
1222 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1223 #else
1224 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1225 #endif
1226 }
1228 if( do_polling() )
1229 st->print("RET\n\t");
1231 st->print("RESTORE");
1232 }
1233 #endif
1235 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1236 MacroAssembler _masm(&cbuf);
1237 Compile* C = ra_->C;
1239 __ verify_thread();
1241 // If this does safepoint polling, then do it here
1242 if( do_polling() && ra_->C->is_method_compilation() ) {
1243 AddressLiteral polling_page(os::get_polling_page());
1244 __ sethi(polling_page, L0);
1245 __ relocate(relocInfo::poll_return_type);
1246 __ ld_ptr( L0, 0, G0 );
1247 }
1249 // If this is a return, then stuff the restore in the delay slot
1250 if( do_polling() ) {
1251 __ ret();
1252 __ delayed()->restore();
1253 } else {
1254 __ restore();
1255 }
1256 }
1258 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1262 int MachEpilogNode::reloc() const {
1263 return 16; // a large enough number
1264 }
1266 const Pipeline * MachEpilogNode::pipeline() const {
1267 return MachNode::pipeline_class();
1268 }
1270 int MachEpilogNode::safepoint_offset() const {
1271 assert( do_polling(), "no return for this epilog node");
1272 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1273 }
1275 //=============================================================================
1277 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1278 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1279 static enum RC rc_class( OptoReg::Name reg ) {
1280 if( !OptoReg::is_valid(reg) ) return rc_bad;
1281 if (OptoReg::is_stack(reg)) return rc_stack;
1282 VMReg r = OptoReg::as_VMReg(reg);
1283 if (r->is_Register()) return rc_int;
1284 assert(r->is_FloatRegister(), "must be");
1285 return rc_float;
1286 }
1288 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1289 if (cbuf) {
1290 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1291 }
1292 #ifndef PRODUCT
1293 else if (!do_size) {
1294 if (size != 0) st->print("\n\t");
1295 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1296 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1297 }
1298 #endif
1299 return size+4;
1300 }
1302 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1303 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1304 #ifndef PRODUCT
1305 else if( !do_size ) {
1306 if( size != 0 ) st->print("\n\t");
1307 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1308 }
1309 #endif
1310 return size+4;
1311 }
1313 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1314 PhaseRegAlloc *ra_,
1315 bool do_size,
1316 outputStream* st ) const {
1317 // Get registers to move
1318 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1319 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1320 OptoReg::Name dst_second = ra_->get_reg_second(this );
1321 OptoReg::Name dst_first = ra_->get_reg_first(this );
1323 enum RC src_second_rc = rc_class(src_second);
1324 enum RC src_first_rc = rc_class(src_first);
1325 enum RC dst_second_rc = rc_class(dst_second);
1326 enum RC dst_first_rc = rc_class(dst_first);
1328 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1330 // Generate spill code!
1331 int size = 0;
1333 if( src_first == dst_first && src_second == dst_second )
1334 return size; // Self copy, no move
1336 // --------------------------------------
1337 // Check for mem-mem move. Load into unused float registers and fall into
1338 // the float-store case.
1339 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1340 int offset = ra_->reg2offset(src_first);
1341 // Further check for aligned-adjacent pair, so we can use a double load
1342 if( (src_first&1)==0 && src_first+1 == src_second ) {
1343 src_second = OptoReg::Name(R_F31_num);
1344 src_second_rc = rc_float;
1345 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1346 } else {
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1348 }
1349 src_first = OptoReg::Name(R_F30_num);
1350 src_first_rc = rc_float;
1351 }
1353 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1354 int offset = ra_->reg2offset(src_second);
1355 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1356 src_second = OptoReg::Name(R_F31_num);
1357 src_second_rc = rc_float;
1358 }
1360 // --------------------------------------
1361 // Check for float->int copy; requires a trip through memory
1362 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1363 int offset = frame::register_save_words*wordSize;
1364 if (cbuf) {
1365 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1366 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1367 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1368 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1369 }
1370 #ifndef PRODUCT
1371 else if (!do_size) {
1372 if (size != 0) st->print("\n\t");
1373 st->print( "SUB R_SP,16,R_SP\n");
1374 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1375 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1376 st->print("\tADD R_SP,16,R_SP\n");
1377 }
1378 #endif
1379 size += 16;
1380 }
1382 // Check for float->int copy on T4
1383 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1384 // Further check for aligned-adjacent pair, so we can use a double move
1385 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1386 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1387 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1388 }
1389 // Check for int->float copy on T4
1390 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1391 // Further check for aligned-adjacent pair, so we can use a double move
1392 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1393 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1394 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1395 }
1397 // --------------------------------------
1398 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1399 // In such cases, I have to do the big-endian swap. For aligned targets, the
1400 // hardware does the flop for me. Doubles are always aligned, so no problem
1401 // there. Misaligned sources only come from native-long-returns (handled
1402 // special below).
1403 #ifndef _LP64
1404 if( src_first_rc == rc_int && // source is already big-endian
1405 src_second_rc != rc_bad && // 64-bit move
1406 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1407 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1408 // Do the big-endian flop.
1409 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1410 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1411 }
1412 #endif
1414 // --------------------------------------
1415 // Check for integer reg-reg copy
1416 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1417 #ifndef _LP64
1418 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1419 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1420 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1421 // operand contains the least significant word of the 64-bit value and vice versa.
1422 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1423 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1424 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1425 if( cbuf ) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1427 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1428 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1429 #ifndef PRODUCT
1430 } else if( !do_size ) {
1431 if( size != 0 ) st->print("\n\t");
1432 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1433 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1434 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1435 #endif
1436 }
1437 return size+12;
1438 }
1439 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1440 // returning a long value in I0/I1
1441 // a SpillCopy must be able to target a return instruction's reg_class
1442 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1443 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1444 // operand contains the least significant word of the 64-bit value and vice versa.
1445 OptoReg::Name tdest = dst_first;
1447 if (src_first == dst_first) {
1448 tdest = OptoReg::Name(R_O7_num);
1449 size += 4;
1450 }
1452 if( cbuf ) {
1453 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1454 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1455 // ShrL_reg_imm6
1456 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1457 // ShrR_reg_imm6 src, 0, dst
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1459 if (tdest != dst_first) {
1460 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1461 }
1462 }
1463 #ifndef PRODUCT
1464 else if( !do_size ) {
1465 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1466 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1467 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1468 if (tdest != dst_first) {
1469 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1470 }
1471 }
1472 #endif // PRODUCT
1473 return size+8;
1474 }
1475 #endif // !_LP64
1476 // Else normal reg-reg copy
1477 assert( src_second != dst_first, "smashed second before evacuating it" );
1478 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1479 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1480 // This moves an aligned adjacent pair.
1481 // See if we are done.
1482 if( src_first+1 == src_second && dst_first+1 == dst_second )
1483 return size;
1484 }
1486 // Check for integer store
1487 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1488 int offset = ra_->reg2offset(dst_first);
1489 // Further check for aligned-adjacent pair, so we can use a double store
1490 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1491 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1492 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1493 }
1495 // Check for integer load
1496 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1497 int offset = ra_->reg2offset(src_first);
1498 // Further check for aligned-adjacent pair, so we can use a double load
1499 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1500 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1501 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1502 }
1504 // Check for float reg-reg copy
1505 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1506 // Further check for aligned-adjacent pair, so we can use a double move
1507 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1508 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1509 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1510 }
1512 // Check for float store
1513 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1514 int offset = ra_->reg2offset(dst_first);
1515 // Further check for aligned-adjacent pair, so we can use a double store
1516 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1517 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1518 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1519 }
1521 // Check for float load
1522 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1523 int offset = ra_->reg2offset(src_first);
1524 // Further check for aligned-adjacent pair, so we can use a double load
1525 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1526 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1527 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1528 }
1530 // --------------------------------------------------------------------
1531 // Check for hi bits still needing moving. Only happens for misaligned
1532 // arguments to native calls.
1533 if( src_second == dst_second )
1534 return size; // Self copy; no move
1535 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1537 #ifndef _LP64
1538 // In the LP64 build, all registers can be moved as aligned/adjacent
1539 // pairs, so there's never any need to move the high bits separately.
1540 // The 32-bit builds have to deal with the 32-bit ABI which can force
1541 // all sorts of silly alignment problems.
1543 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1544 // 32-bits of a 64-bit register, but are needed in low bits of another
1545 // register (else it's a hi-bits-to-hi-bits copy which should have
1546 // happened already as part of a 64-bit move)
1547 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1548 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1549 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1550 // Shift src_second down to dst_second's low bits.
1551 if( cbuf ) {
1552 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1553 #ifndef PRODUCT
1554 } else if( !do_size ) {
1555 if( size != 0 ) st->print("\n\t");
1556 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1557 #endif
1558 }
1559 return size+4;
1560 }
1562 // Check for high word integer store. Must down-shift the hi bits
1563 // into a temp register, then fall into the case of storing int bits.
1564 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1565 // Shift src_second down to dst_second's low bits.
1566 if( cbuf ) {
1567 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1568 #ifndef PRODUCT
1569 } else if( !do_size ) {
1570 if( size != 0 ) st->print("\n\t");
1571 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1572 #endif
1573 }
1574 size+=4;
1575 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1576 }
1578 // Check for high word integer load
1579 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1580 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1582 // Check for high word integer store
1583 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1584 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1586 // Check for high word float store
1587 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1588 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1590 #endif // !_LP64
1592 Unimplemented();
1593 }
1595 #ifndef PRODUCT
1596 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1597 implementation( NULL, ra_, false, st );
1598 }
1599 #endif
1601 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1602 implementation( &cbuf, ra_, false, NULL );
1603 }
1605 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1606 return implementation( NULL, ra_, true, NULL );
1607 }
1609 //=============================================================================
1610 #ifndef PRODUCT
1611 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1612 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1613 }
1614 #endif
1616 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1617 MacroAssembler _masm(&cbuf);
1618 for(int i = 0; i < _count; i += 1) {
1619 __ nop();
1620 }
1621 }
1623 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1624 return 4 * _count;
1625 }
1628 //=============================================================================
1629 #ifndef PRODUCT
1630 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1631 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1632 int reg = ra_->get_reg_first(this);
1633 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1634 }
1635 #endif
1637 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1638 MacroAssembler _masm(&cbuf);
1639 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1640 int reg = ra_->get_encode(this);
1642 if (Assembler::is_simm13(offset)) {
1643 __ add(SP, offset, reg_to_register_object(reg));
1644 } else {
1645 __ set(offset, O7);
1646 __ add(SP, O7, reg_to_register_object(reg));
1647 }
1648 }
1650 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1651 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1652 assert(ra_ == ra_->C->regalloc(), "sanity");
1653 return ra_->C->scratch_emit_size(this);
1654 }
1656 //=============================================================================
1657 #ifndef PRODUCT
1658 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1659 st->print_cr("\nUEP:");
1660 #ifdef _LP64
1661 if (UseCompressedClassPointers) {
1662 assert(Universe::heap() != NULL, "java heap should be initialized");
1663 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1664 if (Universe::narrow_klass_base() != 0) {
1665 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1666 if (Universe::narrow_klass_shift() != 0) {
1667 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1668 }
1669 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1670 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1671 } else {
1672 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1673 }
1674 } else {
1675 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1676 }
1677 st->print_cr("\tCMP R_G5,R_G3" );
1678 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1679 #else // _LP64
1680 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1681 st->print_cr("\tCMP R_G5,R_G3" );
1682 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1683 #endif // _LP64
1684 }
1685 #endif
1687 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1688 MacroAssembler _masm(&cbuf);
1689 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1690 Register temp_reg = G3;
1691 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1693 // Load klass from receiver
1694 __ load_klass(O0, temp_reg);
1695 // Compare against expected klass
1696 __ cmp(temp_reg, G5_ic_reg);
1697 // Branch to miss code, checks xcc or icc depending
1698 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1699 }
1701 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1702 return MachNode::size(ra_);
1703 }
1706 //=============================================================================
1708 uint size_exception_handler() {
1709 if (TraceJumps) {
1710 return (400); // just a guess
1711 }
1712 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1713 }
1715 uint size_deopt_handler() {
1716 if (TraceJumps) {
1717 return (400); // just a guess
1718 }
1719 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1720 }
1722 // Emit exception handler code.
1723 int emit_exception_handler(CodeBuffer& cbuf) {
1724 Register temp_reg = G3;
1725 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1726 MacroAssembler _masm(&cbuf);
1728 address base =
1729 __ start_a_stub(size_exception_handler());
1730 if (base == NULL) return 0; // CodeBuffer::expand failed
1732 int offset = __ offset();
1734 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1735 __ delayed()->nop();
1737 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1739 __ end_a_stub();
1741 return offset;
1742 }
1744 int emit_deopt_handler(CodeBuffer& cbuf) {
1745 // Can't use any of the current frame's registers as we may have deopted
1746 // at a poll and everything (including G3) can be live.
1747 Register temp_reg = L0;
1748 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1749 MacroAssembler _masm(&cbuf);
1751 address base =
1752 __ start_a_stub(size_deopt_handler());
1753 if (base == NULL) return 0; // CodeBuffer::expand failed
1755 int offset = __ offset();
1756 __ save_frame(0);
1757 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1758 __ delayed()->restore();
1760 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1762 __ end_a_stub();
1763 return offset;
1765 }
1767 // Given a register encoding, produce a Integer Register object
1768 static Register reg_to_register_object(int register_encoding) {
1769 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1770 return as_Register(register_encoding);
1771 }
1773 // Given a register encoding, produce a single-precision Float Register object
1774 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1775 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1776 return as_SingleFloatRegister(register_encoding);
1777 }
1779 // Given a register encoding, produce a double-precision Float Register object
1780 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1781 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1782 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1783 return as_DoubleFloatRegister(register_encoding);
1784 }
1786 const bool Matcher::match_rule_supported(int opcode) {
1787 if (!has_match_rule(opcode))
1788 return false;
1790 switch (opcode) {
1791 case Op_CountLeadingZerosI:
1792 case Op_CountLeadingZerosL:
1793 case Op_CountTrailingZerosI:
1794 case Op_CountTrailingZerosL:
1795 case Op_PopCountI:
1796 case Op_PopCountL:
1797 if (!UsePopCountInstruction)
1798 return false;
1799 case Op_CompareAndSwapL:
1800 #ifdef _LP64
1801 case Op_CompareAndSwapP:
1802 #endif
1803 if (!VM_Version::supports_cx8())
1804 return false;
1805 break;
1806 }
1808 return true; // Per default match rules are supported.
1809 }
1811 int Matcher::regnum_to_fpu_offset(int regnum) {
1812 return regnum - 32; // The FP registers are in the second chunk
1813 }
1815 #ifdef ASSERT
1816 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1817 #endif
1819 // Vector width in bytes
1820 const int Matcher::vector_width_in_bytes(BasicType bt) {
1821 assert(MaxVectorSize == 8, "");
1822 return 8;
1823 }
1825 // Vector ideal reg
1826 const int Matcher::vector_ideal_reg(int size) {
1827 assert(MaxVectorSize == 8, "");
1828 return Op_RegD;
1829 }
1831 const int Matcher::vector_shift_count_ideal_reg(int size) {
1832 fatal("vector shift is not supported");
1833 return Node::NotAMachineReg;
1834 }
1836 // Limits on vector size (number of elements) loaded into vector.
1837 const int Matcher::max_vector_size(const BasicType bt) {
1838 assert(is_java_primitive(bt), "only primitive type vectors");
1839 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1840 }
1842 const int Matcher::min_vector_size(const BasicType bt) {
1843 return max_vector_size(bt); // Same as max.
1844 }
1846 // SPARC doesn't support misaligned vectors store/load.
1847 const bool Matcher::misaligned_vectors_ok() {
1848 return false;
1849 }
1851 // USII supports fxtof through the whole range of number, USIII doesn't
1852 const bool Matcher::convL2FSupported(void) {
1853 return VM_Version::has_fast_fxtof();
1854 }
1856 // Is this branch offset short enough that a short branch can be used?
1857 //
1858 // NOTE: If the platform does not provide any short branch variants, then
1859 // this method should return false for offset 0.
1860 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1861 // The passed offset is relative to address of the branch.
1862 // Don't need to adjust the offset.
1863 return UseCBCond && Assembler::is_simm12(offset);
1864 }
1866 const bool Matcher::isSimpleConstant64(jlong value) {
1867 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1868 // Depends on optimizations in MacroAssembler::setx.
1869 int hi = (int)(value >> 32);
1870 int lo = (int)(value & ~0);
1871 return (hi == 0) || (hi == -1) || (lo == 0);
1872 }
1874 // No scaling for the parameter the ClearArray node.
1875 const bool Matcher::init_array_count_is_in_bytes = true;
1877 // Threshold size for cleararray.
1878 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1880 // No additional cost for CMOVL.
1881 const int Matcher::long_cmove_cost() { return 0; }
1883 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1884 const int Matcher::float_cmove_cost() {
1885 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1886 }
1888 // Should the Matcher clone shifts on addressing modes, expecting them to
1889 // be subsumed into complex addressing expressions or compute them into
1890 // registers? True for Intel but false for most RISCs
1891 const bool Matcher::clone_shift_expressions = false;
1893 // Do we need to mask the count passed to shift instructions or does
1894 // the cpu only look at the lower 5/6 bits anyway?
1895 const bool Matcher::need_masked_shift_count = false;
1897 bool Matcher::narrow_oop_use_complex_address() {
1898 NOT_LP64(ShouldNotCallThis());
1899 assert(UseCompressedOops, "only for compressed oops code");
1900 return false;
1901 }
1903 bool Matcher::narrow_klass_use_complex_address() {
1904 NOT_LP64(ShouldNotCallThis());
1905 assert(UseCompressedClassPointers, "only for compressed klass code");
1906 return false;
1907 }
1909 // Is it better to copy float constants, or load them directly from memory?
1910 // Intel can load a float constant from a direct address, requiring no
1911 // extra registers. Most RISCs will have to materialize an address into a
1912 // register first, so they would do better to copy the constant from stack.
1913 const bool Matcher::rematerialize_float_constants = false;
1915 // If CPU can load and store mis-aligned doubles directly then no fixup is
1916 // needed. Else we split the double into 2 integer pieces and move it
1917 // piece-by-piece. Only happens when passing doubles into C code as the
1918 // Java calling convention forces doubles to be aligned.
1919 #ifdef _LP64
1920 const bool Matcher::misaligned_doubles_ok = true;
1921 #else
1922 const bool Matcher::misaligned_doubles_ok = false;
1923 #endif
1925 // No-op on SPARC.
1926 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1927 }
1929 // Advertise here if the CPU requires explicit rounding operations
1930 // to implement the UseStrictFP mode.
1931 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1933 // Are floats conerted to double when stored to stack during deoptimization?
1934 // Sparc does not handle callee-save floats.
1935 bool Matcher::float_in_double() { return false; }
1937 // Do ints take an entire long register or just half?
1938 // Note that we if-def off of _LP64.
1939 // The relevant question is how the int is callee-saved. In _LP64
1940 // the whole long is written but de-opt'ing will have to extract
1941 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1942 #ifdef _LP64
1943 const bool Matcher::int_in_long = true;
1944 #else
1945 const bool Matcher::int_in_long = false;
1946 #endif
1948 // Return whether or not this register is ever used as an argument. This
1949 // function is used on startup to build the trampoline stubs in generateOptoStub.
1950 // Registers not mentioned will be killed by the VM call in the trampoline, and
1951 // arguments in those registers not be available to the callee.
1952 bool Matcher::can_be_java_arg( int reg ) {
1953 // Standard sparc 6 args in registers
1954 if( reg == R_I0_num ||
1955 reg == R_I1_num ||
1956 reg == R_I2_num ||
1957 reg == R_I3_num ||
1958 reg == R_I4_num ||
1959 reg == R_I5_num ) return true;
1960 #ifdef _LP64
1961 // 64-bit builds can pass 64-bit pointers and longs in
1962 // the high I registers
1963 if( reg == R_I0H_num ||
1964 reg == R_I1H_num ||
1965 reg == R_I2H_num ||
1966 reg == R_I3H_num ||
1967 reg == R_I4H_num ||
1968 reg == R_I5H_num ) return true;
1970 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1971 return true;
1972 }
1974 #else
1975 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1976 // Longs cannot be passed in O regs, because O regs become I regs
1977 // after a 'save' and I regs get their high bits chopped off on
1978 // interrupt.
1979 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1980 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1981 #endif
1982 // A few float args in registers
1983 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1985 return false;
1986 }
1988 bool Matcher::is_spillable_arg( int reg ) {
1989 return can_be_java_arg(reg);
1990 }
1992 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1993 // Use hardware SDIVX instruction when it is
1994 // faster than a code which use multiply.
1995 return VM_Version::has_fast_idiv();
1996 }
1998 // Register for DIVI projection of divmodI
1999 RegMask Matcher::divI_proj_mask() {
2000 ShouldNotReachHere();
2001 return RegMask();
2002 }
2004 // Register for MODI projection of divmodI
2005 RegMask Matcher::modI_proj_mask() {
2006 ShouldNotReachHere();
2007 return RegMask();
2008 }
2010 // Register for DIVL projection of divmodL
2011 RegMask Matcher::divL_proj_mask() {
2012 ShouldNotReachHere();
2013 return RegMask();
2014 }
2016 // Register for MODL projection of divmodL
2017 RegMask Matcher::modL_proj_mask() {
2018 ShouldNotReachHere();
2019 return RegMask();
2020 }
2022 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2023 return L7_REGP_mask();
2024 }
2026 const RegMask Matcher::mathExactI_result_proj_mask() {
2027 return G1_REGI_mask();
2028 }
2030 const RegMask Matcher::mathExactL_result_proj_mask() {
2031 return G1_REGL_mask();
2032 }
2034 const RegMask Matcher::mathExactI_flags_proj_mask() {
2035 return INT_FLAGS_mask();
2036 }
2039 %}
2042 // The intptr_t operand types, defined by textual substitution.
2043 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2044 #ifdef _LP64
2045 #define immX immL
2046 #define immX13 immL13
2047 #define immX13m7 immL13m7
2048 #define iRegX iRegL
2049 #define g1RegX g1RegL
2050 #else
2051 #define immX immI
2052 #define immX13 immI13
2053 #define immX13m7 immI13m7
2054 #define iRegX iRegI
2055 #define g1RegX g1RegI
2056 #endif
2058 //----------ENCODING BLOCK-----------------------------------------------------
2059 // This block specifies the encoding classes used by the compiler to output
2060 // byte streams. Encoding classes are parameterized macros used by
2061 // Machine Instruction Nodes in order to generate the bit encoding of the
2062 // instruction. Operands specify their base encoding interface with the
2063 // interface keyword. There are currently supported four interfaces,
2064 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2065 // operand to generate a function which returns its register number when
2066 // queried. CONST_INTER causes an operand to generate a function which
2067 // returns the value of the constant when queried. MEMORY_INTER causes an
2068 // operand to generate four functions which return the Base Register, the
2069 // Index Register, the Scale Value, and the Offset Value of the operand when
2070 // queried. COND_INTER causes an operand to generate six functions which
2071 // return the encoding code (ie - encoding bits for the instruction)
2072 // associated with each basic boolean condition for a conditional instruction.
2073 //
2074 // Instructions specify two basic values for encoding. Again, a function
2075 // is available to check if the constant displacement is an oop. They use the
2076 // ins_encode keyword to specify their encoding classes (which must be
2077 // a sequence of enc_class names, and their parameters, specified in
2078 // the encoding block), and they use the
2079 // opcode keyword to specify, in order, their primary, secondary, and
2080 // tertiary opcode. Only the opcode sections which a particular instruction
2081 // needs for encoding need to be specified.
2082 encode %{
2083 enc_class enc_untested %{
2084 #ifdef ASSERT
2085 MacroAssembler _masm(&cbuf);
2086 __ untested("encoding");
2087 #endif
2088 %}
2090 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2091 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2092 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2093 %}
2095 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2096 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2097 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2098 %}
2100 enc_class form3_mem_prefetch_read( memory mem ) %{
2101 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2102 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2103 %}
2105 enc_class form3_mem_prefetch_write( memory mem ) %{
2106 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2107 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2108 %}
2110 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2111 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2112 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2113 guarantee($mem$$index == R_G0_enc, "double index?");
2114 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2115 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2116 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2117 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2118 %}
2120 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2121 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2122 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2123 guarantee($mem$$index == R_G0_enc, "double index?");
2124 // Load long with 2 instructions
2125 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2126 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2127 %}
2129 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2130 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2131 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2132 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2133 %}
2135 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2136 // Encode a reg-reg copy. If it is useless, then empty encoding.
2137 if( $rs2$$reg != $rd$$reg )
2138 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2139 %}
2141 // Target lo half of long
2142 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2143 // Encode a reg-reg copy. If it is useless, then empty encoding.
2144 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2145 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2146 %}
2148 // Source lo half of long
2149 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2150 // Encode a reg-reg copy. If it is useless, then empty encoding.
2151 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2152 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2153 %}
2155 // Target hi half of long
2156 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2157 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2158 %}
2160 // Source lo half of long, and leave it sign extended.
2161 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2162 // Sign extend low half
2163 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2164 %}
2166 // Source hi half of long, and leave it sign extended.
2167 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2168 // Shift high half to low half
2169 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2170 %}
2172 // Source hi half of long
2173 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2174 // Encode a reg-reg copy. If it is useless, then empty encoding.
2175 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2176 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2177 %}
2179 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2180 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2181 %}
2183 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2184 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2185 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2186 %}
2188 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2189 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2190 // clear if nothing else is happening
2191 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2192 // blt,a,pn done
2193 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2194 // mov dst,-1 in delay slot
2195 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2196 %}
2198 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2199 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2200 %}
2202 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2203 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2204 %}
2206 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2207 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2208 %}
2210 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2211 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2212 %}
2214 enc_class move_return_pc_to_o1() %{
2215 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2216 %}
2218 #ifdef _LP64
2219 /* %%% merge with enc_to_bool */
2220 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2221 MacroAssembler _masm(&cbuf);
2223 Register src_reg = reg_to_register_object($src$$reg);
2224 Register dst_reg = reg_to_register_object($dst$$reg);
2225 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2226 %}
2227 #endif
2229 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2230 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2231 MacroAssembler _masm(&cbuf);
2233 Register p_reg = reg_to_register_object($p$$reg);
2234 Register q_reg = reg_to_register_object($q$$reg);
2235 Register y_reg = reg_to_register_object($y$$reg);
2236 Register tmp_reg = reg_to_register_object($tmp$$reg);
2238 __ subcc( p_reg, q_reg, p_reg );
2239 __ add ( p_reg, y_reg, tmp_reg );
2240 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2241 %}
2243 enc_class form_d2i_helper(regD src, regF dst) %{
2244 // fcmp %fcc0,$src,$src
2245 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2246 // branch %fcc0 not-nan, predict taken
2247 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2248 // fdtoi $src,$dst
2249 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2250 // fitos $dst,$dst (if nan)
2251 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2252 // clear $dst (if nan)
2253 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2254 // carry on here...
2255 %}
2257 enc_class form_d2l_helper(regD src, regD dst) %{
2258 // fcmp %fcc0,$src,$src check for NAN
2259 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2260 // branch %fcc0 not-nan, predict taken
2261 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2262 // fdtox $src,$dst convert in delay slot
2263 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2264 // fxtod $dst,$dst (if nan)
2265 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2266 // clear $dst (if nan)
2267 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2268 // carry on here...
2269 %}
2271 enc_class form_f2i_helper(regF src, regF dst) %{
2272 // fcmps %fcc0,$src,$src
2273 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2274 // branch %fcc0 not-nan, predict taken
2275 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2276 // fstoi $src,$dst
2277 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2278 // fitos $dst,$dst (if nan)
2279 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2280 // clear $dst (if nan)
2281 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2282 // carry on here...
2283 %}
2285 enc_class form_f2l_helper(regF src, regD dst) %{
2286 // fcmps %fcc0,$src,$src
2287 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2288 // branch %fcc0 not-nan, predict taken
2289 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2290 // fstox $src,$dst
2291 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2292 // fxtod $dst,$dst (if nan)
2293 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2294 // clear $dst (if nan)
2295 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2296 // carry on here...
2297 %}
2299 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2300 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2301 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2302 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2304 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2306 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2307 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2309 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2310 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2311 %}
2313 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2314 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2315 %}
2317 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2318 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2319 %}
2321 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2322 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2323 %}
2325 enc_class form3_convI2F(regF rs2, regF rd) %{
2326 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2327 %}
2329 // Encloding class for traceable jumps
2330 enc_class form_jmpl(g3RegP dest) %{
2331 emit_jmpl(cbuf, $dest$$reg);
2332 %}
2334 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2335 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2336 %}
2338 enc_class form2_nop() %{
2339 emit_nop(cbuf);
2340 %}
2342 enc_class form2_illtrap() %{
2343 emit_illtrap(cbuf);
2344 %}
2347 // Compare longs and convert into -1, 0, 1.
2348 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2349 // CMP $src1,$src2
2350 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2351 // blt,a,pn done
2352 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2353 // mov dst,-1 in delay slot
2354 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2355 // bgt,a,pn done
2356 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2357 // mov dst,1 in delay slot
2358 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2359 // CLR $dst
2360 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2361 %}
2363 enc_class enc_PartialSubtypeCheck() %{
2364 MacroAssembler _masm(&cbuf);
2365 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2366 __ delayed()->nop();
2367 %}
2369 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2370 MacroAssembler _masm(&cbuf);
2371 Label* L = $labl$$label;
2372 Assembler::Predict predict_taken =
2373 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2375 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2376 __ delayed()->nop();
2377 %}
2379 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2380 MacroAssembler _masm(&cbuf);
2381 Label* L = $labl$$label;
2382 Assembler::Predict predict_taken =
2383 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2385 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2386 __ delayed()->nop();
2387 %}
2389 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2390 int op = (Assembler::arith_op << 30) |
2391 ($dst$$reg << 25) |
2392 (Assembler::movcc_op3 << 19) |
2393 (1 << 18) | // cc2 bit for 'icc'
2394 ($cmp$$cmpcode << 14) |
2395 (0 << 13) | // select register move
2396 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2397 ($src$$reg << 0);
2398 cbuf.insts()->emit_int32(op);
2399 %}
2401 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2402 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2403 int op = (Assembler::arith_op << 30) |
2404 ($dst$$reg << 25) |
2405 (Assembler::movcc_op3 << 19) |
2406 (1 << 18) | // cc2 bit for 'icc'
2407 ($cmp$$cmpcode << 14) |
2408 (1 << 13) | // select immediate move
2409 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2410 (simm11 << 0);
2411 cbuf.insts()->emit_int32(op);
2412 %}
2414 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2415 int op = (Assembler::arith_op << 30) |
2416 ($dst$$reg << 25) |
2417 (Assembler::movcc_op3 << 19) |
2418 (0 << 18) | // cc2 bit for 'fccX'
2419 ($cmp$$cmpcode << 14) |
2420 (0 << 13) | // select register move
2421 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2422 ($src$$reg << 0);
2423 cbuf.insts()->emit_int32(op);
2424 %}
2426 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2427 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2428 int op = (Assembler::arith_op << 30) |
2429 ($dst$$reg << 25) |
2430 (Assembler::movcc_op3 << 19) |
2431 (0 << 18) | // cc2 bit for 'fccX'
2432 ($cmp$$cmpcode << 14) |
2433 (1 << 13) | // select immediate move
2434 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2435 (simm11 << 0);
2436 cbuf.insts()->emit_int32(op);
2437 %}
2439 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2440 int op = (Assembler::arith_op << 30) |
2441 ($dst$$reg << 25) |
2442 (Assembler::fpop2_op3 << 19) |
2443 (0 << 18) |
2444 ($cmp$$cmpcode << 14) |
2445 (1 << 13) | // select register move
2446 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2447 ($primary << 5) | // select single, double or quad
2448 ($src$$reg << 0);
2449 cbuf.insts()->emit_int32(op);
2450 %}
2452 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2453 int op = (Assembler::arith_op << 30) |
2454 ($dst$$reg << 25) |
2455 (Assembler::fpop2_op3 << 19) |
2456 (0 << 18) |
2457 ($cmp$$cmpcode << 14) |
2458 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2459 ($primary << 5) | // select single, double or quad
2460 ($src$$reg << 0);
2461 cbuf.insts()->emit_int32(op);
2462 %}
2464 // Used by the MIN/MAX encodings. Same as a CMOV, but
2465 // the condition comes from opcode-field instead of an argument.
2466 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2467 int op = (Assembler::arith_op << 30) |
2468 ($dst$$reg << 25) |
2469 (Assembler::movcc_op3 << 19) |
2470 (1 << 18) | // cc2 bit for 'icc'
2471 ($primary << 14) |
2472 (0 << 13) | // select register move
2473 (0 << 11) | // cc1, cc0 bits for 'icc'
2474 ($src$$reg << 0);
2475 cbuf.insts()->emit_int32(op);
2476 %}
2478 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2479 int op = (Assembler::arith_op << 30) |
2480 ($dst$$reg << 25) |
2481 (Assembler::movcc_op3 << 19) |
2482 (6 << 16) | // cc2 bit for 'xcc'
2483 ($primary << 14) |
2484 (0 << 13) | // select register move
2485 (0 << 11) | // cc1, cc0 bits for 'icc'
2486 ($src$$reg << 0);
2487 cbuf.insts()->emit_int32(op);
2488 %}
2490 enc_class Set13( immI13 src, iRegI rd ) %{
2491 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2492 %}
2494 enc_class SetHi22( immI src, iRegI rd ) %{
2495 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2496 %}
2498 enc_class Set32( immI src, iRegI rd ) %{
2499 MacroAssembler _masm(&cbuf);
2500 __ set($src$$constant, reg_to_register_object($rd$$reg));
2501 %}
2503 enc_class call_epilog %{
2504 if( VerifyStackAtCalls ) {
2505 MacroAssembler _masm(&cbuf);
2506 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2507 Register temp_reg = G3;
2508 __ add(SP, framesize, temp_reg);
2509 __ cmp(temp_reg, FP);
2510 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2511 }
2512 %}
2514 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2515 // to G1 so the register allocator will not have to deal with the misaligned register
2516 // pair.
2517 enc_class adjust_long_from_native_call %{
2518 #ifndef _LP64
2519 if (returns_long()) {
2520 // sllx O0,32,O0
2521 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2522 // srl O1,0,O1
2523 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2524 // or O0,O1,G1
2525 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2526 }
2527 #endif
2528 %}
2530 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2531 // CALL directly to the runtime
2532 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2533 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2534 /*preserve_g2=*/true);
2535 %}
2537 enc_class preserve_SP %{
2538 MacroAssembler _masm(&cbuf);
2539 __ mov(SP, L7_mh_SP_save);
2540 %}
2542 enc_class restore_SP %{
2543 MacroAssembler _masm(&cbuf);
2544 __ mov(L7_mh_SP_save, SP);
2545 %}
2547 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2548 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2549 // who we intended to call.
2550 if (!_method) {
2551 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2552 } else if (_optimized_virtual) {
2553 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2554 } else {
2555 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2556 }
2557 if (_method) { // Emit stub for static call.
2558 CompiledStaticCall::emit_to_interp_stub(cbuf);
2559 }
2560 %}
2562 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2563 MacroAssembler _masm(&cbuf);
2564 __ set_inst_mark();
2565 int vtable_index = this->_vtable_index;
2566 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2567 if (vtable_index < 0) {
2568 // must be invalid_vtable_index, not nonvirtual_vtable_index
2569 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2570 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2571 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2572 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2573 __ ic_call((address)$meth$$method);
2574 } else {
2575 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2576 // Just go thru the vtable
2577 // get receiver klass (receiver already checked for non-null)
2578 // If we end up going thru a c2i adapter interpreter expects method in G5
2579 int off = __ offset();
2580 __ load_klass(O0, G3_scratch);
2581 int klass_load_size;
2582 if (UseCompressedClassPointers) {
2583 assert(Universe::heap() != NULL, "java heap should be initialized");
2584 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2585 } else {
2586 klass_load_size = 1*BytesPerInstWord;
2587 }
2588 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2589 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2590 if (Assembler::is_simm13(v_off)) {
2591 __ ld_ptr(G3, v_off, G5_method);
2592 } else {
2593 // Generate 2 instructions
2594 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2595 __ or3(G5_method, v_off & 0x3ff, G5_method);
2596 // ld_ptr, set_hi, set
2597 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2598 "Unexpected instruction size(s)");
2599 __ ld_ptr(G3, G5_method, G5_method);
2600 }
2601 // NOTE: for vtable dispatches, the vtable entry will never be null.
2602 // However it may very well end up in handle_wrong_method if the
2603 // method is abstract for the particular class.
2604 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2605 // jump to target (either compiled code or c2iadapter)
2606 __ jmpl(G3_scratch, G0, O7);
2607 __ delayed()->nop();
2608 }
2609 %}
2611 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2612 MacroAssembler _masm(&cbuf);
2614 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2615 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2616 // we might be calling a C2I adapter which needs it.
2618 assert(temp_reg != G5_ic_reg, "conflicting registers");
2619 // Load nmethod
2620 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2622 // CALL to compiled java, indirect the contents of G3
2623 __ set_inst_mark();
2624 __ callr(temp_reg, G0);
2625 __ delayed()->nop();
2626 %}
2628 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2629 MacroAssembler _masm(&cbuf);
2630 Register Rdividend = reg_to_register_object($src1$$reg);
2631 Register Rdivisor = reg_to_register_object($src2$$reg);
2632 Register Rresult = reg_to_register_object($dst$$reg);
2634 __ sra(Rdivisor, 0, Rdivisor);
2635 __ sra(Rdividend, 0, Rdividend);
2636 __ sdivx(Rdividend, Rdivisor, Rresult);
2637 %}
2639 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2640 MacroAssembler _masm(&cbuf);
2642 Register Rdividend = reg_to_register_object($src1$$reg);
2643 int divisor = $imm$$constant;
2644 Register Rresult = reg_to_register_object($dst$$reg);
2646 __ sra(Rdividend, 0, Rdividend);
2647 __ sdivx(Rdividend, divisor, Rresult);
2648 %}
2650 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2651 MacroAssembler _masm(&cbuf);
2652 Register Rsrc1 = reg_to_register_object($src1$$reg);
2653 Register Rsrc2 = reg_to_register_object($src2$$reg);
2654 Register Rdst = reg_to_register_object($dst$$reg);
2656 __ sra( Rsrc1, 0, Rsrc1 );
2657 __ sra( Rsrc2, 0, Rsrc2 );
2658 __ mulx( Rsrc1, Rsrc2, Rdst );
2659 __ srlx( Rdst, 32, Rdst );
2660 %}
2662 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2663 MacroAssembler _masm(&cbuf);
2664 Register Rdividend = reg_to_register_object($src1$$reg);
2665 Register Rdivisor = reg_to_register_object($src2$$reg);
2666 Register Rresult = reg_to_register_object($dst$$reg);
2667 Register Rscratch = reg_to_register_object($scratch$$reg);
2669 assert(Rdividend != Rscratch, "");
2670 assert(Rdivisor != Rscratch, "");
2672 __ sra(Rdividend, 0, Rdividend);
2673 __ sra(Rdivisor, 0, Rdivisor);
2674 __ sdivx(Rdividend, Rdivisor, Rscratch);
2675 __ mulx(Rscratch, Rdivisor, Rscratch);
2676 __ sub(Rdividend, Rscratch, Rresult);
2677 %}
2679 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2680 MacroAssembler _masm(&cbuf);
2682 Register Rdividend = reg_to_register_object($src1$$reg);
2683 int divisor = $imm$$constant;
2684 Register Rresult = reg_to_register_object($dst$$reg);
2685 Register Rscratch = reg_to_register_object($scratch$$reg);
2687 assert(Rdividend != Rscratch, "");
2689 __ sra(Rdividend, 0, Rdividend);
2690 __ sdivx(Rdividend, divisor, Rscratch);
2691 __ mulx(Rscratch, divisor, Rscratch);
2692 __ sub(Rdividend, Rscratch, Rresult);
2693 %}
2695 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2696 MacroAssembler _masm(&cbuf);
2698 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2699 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2701 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2702 %}
2704 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2705 MacroAssembler _masm(&cbuf);
2707 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2708 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2710 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2711 %}
2713 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2714 MacroAssembler _masm(&cbuf);
2716 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2717 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2719 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2720 %}
2722 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2723 MacroAssembler _masm(&cbuf);
2725 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2726 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2728 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2729 %}
2731 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2732 MacroAssembler _masm(&cbuf);
2734 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2735 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2737 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2738 %}
2740 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2741 MacroAssembler _masm(&cbuf);
2743 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2744 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2746 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2747 %}
2749 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2750 MacroAssembler _masm(&cbuf);
2752 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2753 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2755 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2756 %}
2758 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2759 MacroAssembler _masm(&cbuf);
2761 Register Roop = reg_to_register_object($oop$$reg);
2762 Register Rbox = reg_to_register_object($box$$reg);
2763 Register Rscratch = reg_to_register_object($scratch$$reg);
2764 Register Rmark = reg_to_register_object($scratch2$$reg);
2766 assert(Roop != Rscratch, "");
2767 assert(Roop != Rmark, "");
2768 assert(Rbox != Rscratch, "");
2769 assert(Rbox != Rmark, "");
2771 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2772 %}
2774 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2775 MacroAssembler _masm(&cbuf);
2777 Register Roop = reg_to_register_object($oop$$reg);
2778 Register Rbox = reg_to_register_object($box$$reg);
2779 Register Rscratch = reg_to_register_object($scratch$$reg);
2780 Register Rmark = reg_to_register_object($scratch2$$reg);
2782 assert(Roop != Rscratch, "");
2783 assert(Roop != Rmark, "");
2784 assert(Rbox != Rscratch, "");
2785 assert(Rbox != Rmark, "");
2787 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2788 %}
2790 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2791 MacroAssembler _masm(&cbuf);
2792 Register Rmem = reg_to_register_object($mem$$reg);
2793 Register Rold = reg_to_register_object($old$$reg);
2794 Register Rnew = reg_to_register_object($new$$reg);
2796 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2797 __ cmp( Rold, Rnew );
2798 %}
2800 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2801 Register Rmem = reg_to_register_object($mem$$reg);
2802 Register Rold = reg_to_register_object($old$$reg);
2803 Register Rnew = reg_to_register_object($new$$reg);
2805 MacroAssembler _masm(&cbuf);
2806 __ mov(Rnew, O7);
2807 __ casx(Rmem, Rold, O7);
2808 __ cmp( Rold, O7 );
2809 %}
2811 // raw int cas, used for compareAndSwap
2812 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2813 Register Rmem = reg_to_register_object($mem$$reg);
2814 Register Rold = reg_to_register_object($old$$reg);
2815 Register Rnew = reg_to_register_object($new$$reg);
2817 MacroAssembler _masm(&cbuf);
2818 __ mov(Rnew, O7);
2819 __ cas(Rmem, Rold, O7);
2820 __ cmp( Rold, O7 );
2821 %}
2823 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2824 Register Rres = reg_to_register_object($res$$reg);
2826 MacroAssembler _masm(&cbuf);
2827 __ mov(1, Rres);
2828 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2829 %}
2831 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2832 Register Rres = reg_to_register_object($res$$reg);
2834 MacroAssembler _masm(&cbuf);
2835 __ mov(1, Rres);
2836 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2837 %}
2839 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2840 MacroAssembler _masm(&cbuf);
2841 Register Rdst = reg_to_register_object($dst$$reg);
2842 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2843 : reg_to_DoubleFloatRegister_object($src1$$reg);
2844 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2845 : reg_to_DoubleFloatRegister_object($src2$$reg);
2847 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2848 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2849 %}
2852 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2853 Label Ldone, Lloop;
2854 MacroAssembler _masm(&cbuf);
2856 Register str1_reg = reg_to_register_object($str1$$reg);
2857 Register str2_reg = reg_to_register_object($str2$$reg);
2858 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2859 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2860 Register result_reg = reg_to_register_object($result$$reg);
2862 assert(result_reg != str1_reg &&
2863 result_reg != str2_reg &&
2864 result_reg != cnt1_reg &&
2865 result_reg != cnt2_reg ,
2866 "need different registers");
2868 // Compute the minimum of the string lengths(str1_reg) and the
2869 // difference of the string lengths (stack)
2871 // See if the lengths are different, and calculate min in str1_reg.
2872 // Stash diff in O7 in case we need it for a tie-breaker.
2873 Label Lskip;
2874 __ subcc(cnt1_reg, cnt2_reg, O7);
2875 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2876 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2877 // cnt2 is shorter, so use its count:
2878 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2879 __ bind(Lskip);
2881 // reallocate cnt1_reg, cnt2_reg, result_reg
2882 // Note: limit_reg holds the string length pre-scaled by 2
2883 Register limit_reg = cnt1_reg;
2884 Register chr2_reg = cnt2_reg;
2885 Register chr1_reg = result_reg;
2886 // str{12} are the base pointers
2888 // Is the minimum length zero?
2889 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2890 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2891 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2893 // Load first characters
2894 __ lduh(str1_reg, 0, chr1_reg);
2895 __ lduh(str2_reg, 0, chr2_reg);
2897 // Compare first characters
2898 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2899 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2900 assert(chr1_reg == result_reg, "result must be pre-placed");
2901 __ delayed()->nop();
2903 {
2904 // Check after comparing first character to see if strings are equivalent
2905 Label LSkip2;
2906 // Check if the strings start at same location
2907 __ cmp(str1_reg, str2_reg);
2908 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2909 __ delayed()->nop();
2911 // Check if the length difference is zero (in O7)
2912 __ cmp(G0, O7);
2913 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2914 __ delayed()->mov(G0, result_reg); // result is zero
2916 // Strings might not be equal
2917 __ bind(LSkip2);
2918 }
2920 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2921 __ signx(limit_reg);
2923 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2924 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2925 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2927 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2928 __ add(str1_reg, limit_reg, str1_reg);
2929 __ add(str2_reg, limit_reg, str2_reg);
2930 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2932 // Compare the rest of the characters
2933 __ lduh(str1_reg, limit_reg, chr1_reg);
2934 __ bind(Lloop);
2935 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2936 __ lduh(str2_reg, limit_reg, chr2_reg);
2937 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2938 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2939 assert(chr1_reg == result_reg, "result must be pre-placed");
2940 __ delayed()->inccc(limit_reg, sizeof(jchar));
2941 // annul LDUH if branch is not taken to prevent access past end of string
2942 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2943 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2945 // If strings are equal up to min length, return the length difference.
2946 __ mov(O7, result_reg);
2948 // Otherwise, return the difference between the first mismatched chars.
2949 __ bind(Ldone);
2950 %}
2952 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2953 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2954 MacroAssembler _masm(&cbuf);
2956 Register str1_reg = reg_to_register_object($str1$$reg);
2957 Register str2_reg = reg_to_register_object($str2$$reg);
2958 Register cnt_reg = reg_to_register_object($cnt$$reg);
2959 Register tmp1_reg = O7;
2960 Register result_reg = reg_to_register_object($result$$reg);
2962 assert(result_reg != str1_reg &&
2963 result_reg != str2_reg &&
2964 result_reg != cnt_reg &&
2965 result_reg != tmp1_reg ,
2966 "need different registers");
2968 __ cmp(str1_reg, str2_reg); //same char[] ?
2969 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2970 __ delayed()->add(G0, 1, result_reg);
2972 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2973 __ delayed()->add(G0, 1, result_reg); // count == 0
2975 //rename registers
2976 Register limit_reg = cnt_reg;
2977 Register chr1_reg = result_reg;
2978 Register chr2_reg = tmp1_reg;
2980 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2981 __ signx(limit_reg);
2983 //check for alignment and position the pointers to the ends
2984 __ or3(str1_reg, str2_reg, chr1_reg);
2985 __ andcc(chr1_reg, 0x3, chr1_reg);
2986 // notZero means at least one not 4-byte aligned.
2987 // We could optimize the case when both arrays are not aligned
2988 // but it is not frequent case and it requires additional checks.
2989 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2990 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2992 // Compare char[] arrays aligned to 4 bytes.
2993 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2994 chr1_reg, chr2_reg, Ldone);
2995 __ ba(Ldone);
2996 __ delayed()->add(G0, 1, result_reg);
2998 // char by char compare
2999 __ bind(Lchar);
3000 __ add(str1_reg, limit_reg, str1_reg);
3001 __ add(str2_reg, limit_reg, str2_reg);
3002 __ neg(limit_reg); //negate count
3004 __ lduh(str1_reg, limit_reg, chr1_reg);
3005 // Lchar_loop
3006 __ bind(Lchar_loop);
3007 __ lduh(str2_reg, limit_reg, chr2_reg);
3008 __ cmp(chr1_reg, chr2_reg);
3009 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3010 __ delayed()->mov(G0, result_reg); //not equal
3011 __ inccc(limit_reg, sizeof(jchar));
3012 // annul LDUH if branch is not taken to prevent access past end of string
3013 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3014 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3016 __ add(G0, 1, result_reg); //equal
3018 __ bind(Ldone);
3019 %}
3021 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3022 Label Lvector, Ldone, Lloop;
3023 MacroAssembler _masm(&cbuf);
3025 Register ary1_reg = reg_to_register_object($ary1$$reg);
3026 Register ary2_reg = reg_to_register_object($ary2$$reg);
3027 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3028 Register tmp2_reg = O7;
3029 Register result_reg = reg_to_register_object($result$$reg);
3031 int length_offset = arrayOopDesc::length_offset_in_bytes();
3032 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3034 // return true if the same array
3035 __ cmp(ary1_reg, ary2_reg);
3036 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3037 __ delayed()->add(G0, 1, result_reg); // equal
3039 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3040 __ delayed()->mov(G0, result_reg); // not equal
3042 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3043 __ delayed()->mov(G0, result_reg); // not equal
3045 //load the lengths of arrays
3046 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3047 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3049 // return false if the two arrays are not equal length
3050 __ cmp(tmp1_reg, tmp2_reg);
3051 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3052 __ delayed()->mov(G0, result_reg); // not equal
3054 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3055 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3057 // load array addresses
3058 __ add(ary1_reg, base_offset, ary1_reg);
3059 __ add(ary2_reg, base_offset, ary2_reg);
3061 // renaming registers
3062 Register chr1_reg = result_reg; // for characters in ary1
3063 Register chr2_reg = tmp2_reg; // for characters in ary2
3064 Register limit_reg = tmp1_reg; // length
3066 // set byte count
3067 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3069 // Compare char[] arrays aligned to 4 bytes.
3070 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3071 chr1_reg, chr2_reg, Ldone);
3072 __ add(G0, 1, result_reg); // equals
3074 __ bind(Ldone);
3075 %}
3077 enc_class enc_rethrow() %{
3078 cbuf.set_insts_mark();
3079 Register temp_reg = G3;
3080 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3081 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3082 MacroAssembler _masm(&cbuf);
3083 #ifdef ASSERT
3084 __ save_frame(0);
3085 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3086 __ sethi(last_rethrow_addrlit, L1);
3087 Address addr(L1, last_rethrow_addrlit.low10());
3088 __ rdpc(L2);
3089 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3090 __ st_ptr(L2, addr);
3091 __ restore();
3092 #endif
3093 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3094 __ delayed()->nop();
3095 %}
3097 enc_class emit_mem_nop() %{
3098 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3099 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3100 %}
3102 enc_class emit_fadd_nop() %{
3103 // Generates the instruction FMOVS f31,f31
3104 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3105 %}
3107 enc_class emit_br_nop() %{
3108 // Generates the instruction BPN,PN .
3109 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3110 %}
3112 enc_class enc_membar_acquire %{
3113 MacroAssembler _masm(&cbuf);
3114 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3115 %}
3117 enc_class enc_membar_release %{
3118 MacroAssembler _masm(&cbuf);
3119 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3120 %}
3122 enc_class enc_membar_volatile %{
3123 MacroAssembler _masm(&cbuf);
3124 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3125 %}
3127 %}
3129 //----------FRAME--------------------------------------------------------------
3130 // Definition of frame structure and management information.
3131 //
3132 // S T A C K L A Y O U T Allocators stack-slot number
3133 // | (to get allocators register number
3134 // G Owned by | | v add VMRegImpl::stack0)
3135 // r CALLER | |
3136 // o | +--------+ pad to even-align allocators stack-slot
3137 // w V | pad0 | numbers; owned by CALLER
3138 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3139 // h ^ | in | 5
3140 // | | args | 4 Holes in incoming args owned by SELF
3141 // | | | | 3
3142 // | | +--------+
3143 // V | | old out| Empty on Intel, window on Sparc
3144 // | old |preserve| Must be even aligned.
3145 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3146 // | | in | 3 area for Intel ret address
3147 // Owned by |preserve| Empty on Sparc.
3148 // SELF +--------+
3149 // | | pad2 | 2 pad to align old SP
3150 // | +--------+ 1
3151 // | | locks | 0
3152 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3153 // | | pad1 | 11 pad to align new SP
3154 // | +--------+
3155 // | | | 10
3156 // | | spills | 9 spills
3157 // V | | 8 (pad0 slot for callee)
3158 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3159 // ^ | out | 7
3160 // | | args | 6 Holes in outgoing args owned by CALLEE
3161 // Owned by +--------+
3162 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3163 // | new |preserve| Must be even-aligned.
3164 // | SP-+--------+----> Matcher::_new_SP, even aligned
3165 // | | |
3166 //
3167 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3168 // known from SELF's arguments and the Java calling convention.
3169 // Region 6-7 is determined per call site.
3170 // Note 2: If the calling convention leaves holes in the incoming argument
3171 // area, those holes are owned by SELF. Holes in the outgoing area
3172 // are owned by the CALLEE. Holes should not be nessecary in the
3173 // incoming area, as the Java calling convention is completely under
3174 // the control of the AD file. Doubles can be sorted and packed to
3175 // avoid holes. Holes in the outgoing arguments may be nessecary for
3176 // varargs C calling conventions.
3177 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3178 // even aligned with pad0 as needed.
3179 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3180 // region 6-11 is even aligned; it may be padded out more so that
3181 // the region from SP to FP meets the minimum stack alignment.
3183 frame %{
3184 // What direction does stack grow in (assumed to be same for native & Java)
3185 stack_direction(TOWARDS_LOW);
3187 // These two registers define part of the calling convention
3188 // between compiled code and the interpreter.
3189 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3190 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3192 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3193 cisc_spilling_operand_name(indOffset);
3195 // Number of stack slots consumed by a Monitor enter
3196 #ifdef _LP64
3197 sync_stack_slots(2);
3198 #else
3199 sync_stack_slots(1);
3200 #endif
3202 // Compiled code's Frame Pointer
3203 frame_pointer(R_SP);
3205 // Stack alignment requirement
3206 stack_alignment(StackAlignmentInBytes);
3207 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3208 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3210 // Number of stack slots between incoming argument block and the start of
3211 // a new frame. The PROLOG must add this many slots to the stack. The
3212 // EPILOG must remove this many slots.
3213 in_preserve_stack_slots(0);
3215 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3216 // for calls to C. Supports the var-args backing area for register parms.
3217 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3218 #ifdef _LP64
3219 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3220 varargs_C_out_slots_killed(12);
3221 #else
3222 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3223 varargs_C_out_slots_killed( 7);
3224 #endif
3226 // The after-PROLOG location of the return address. Location of
3227 // return address specifies a type (REG or STACK) and a number
3228 // representing the register number (i.e. - use a register name) or
3229 // stack slot.
3230 return_addr(REG R_I7); // Ret Addr is in register I7
3232 // Body of function which returns an OptoRegs array locating
3233 // arguments either in registers or in stack slots for calling
3234 // java
3235 calling_convention %{
3236 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3238 %}
3240 // Body of function which returns an OptoRegs array locating
3241 // arguments either in registers or in stack slots for callin
3242 // C.
3243 c_calling_convention %{
3244 // This is obviously always outgoing
3245 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3246 %}
3248 // Location of native (C/C++) and interpreter return values. This is specified to
3249 // be the same as Java. In the 32-bit VM, long values are actually returned from
3250 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3251 // to and from the register pairs is done by the appropriate call and epilog
3252 // opcodes. This simplifies the register allocator.
3253 c_return_value %{
3254 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3255 #ifdef _LP64
3256 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3257 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3258 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3259 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3260 #else // !_LP64
3261 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3262 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3263 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3264 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3265 #endif
3266 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3267 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3268 %}
3270 // Location of compiled Java return values. Same as C
3271 return_value %{
3272 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3273 #ifdef _LP64
3274 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3275 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3276 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3277 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3278 #else // !_LP64
3279 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3280 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3281 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3282 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3283 #endif
3284 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3285 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3286 %}
3288 %}
3291 //----------ATTRIBUTES---------------------------------------------------------
3292 //----------Operand Attributes-------------------------------------------------
3293 op_attrib op_cost(1); // Required cost attribute
3295 //----------Instruction Attributes---------------------------------------------
3296 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3297 ins_attrib ins_size(32); // Required size attribute (in bits)
3298 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3299 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3300 // non-matching short branch variant of some
3301 // long branch?
3303 //----------OPERANDS-----------------------------------------------------------
3304 // Operand definitions must precede instruction definitions for correct parsing
3305 // in the ADLC because operands constitute user defined types which are used in
3306 // instruction definitions.
3308 //----------Simple Operands----------------------------------------------------
3309 // Immediate Operands
3310 // Integer Immediate: 32-bit
3311 operand immI() %{
3312 match(ConI);
3314 op_cost(0);
3315 // formats are generated automatically for constants and base registers
3316 format %{ %}
3317 interface(CONST_INTER);
3318 %}
3320 // Integer Immediate: 8-bit
3321 operand immI8() %{
3322 predicate(Assembler::is_simm8(n->get_int()));
3323 match(ConI);
3324 op_cost(0);
3325 format %{ %}
3326 interface(CONST_INTER);
3327 %}
3329 // Integer Immediate: 13-bit
3330 operand immI13() %{
3331 predicate(Assembler::is_simm13(n->get_int()));
3332 match(ConI);
3333 op_cost(0);
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
3339 // Integer Immediate: 13-bit minus 7
3340 operand immI13m7() %{
3341 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3342 match(ConI);
3343 op_cost(0);
3345 format %{ %}
3346 interface(CONST_INTER);
3347 %}
3349 // Integer Immediate: 16-bit
3350 operand immI16() %{
3351 predicate(Assembler::is_simm16(n->get_int()));
3352 match(ConI);
3353 op_cost(0);
3354 format %{ %}
3355 interface(CONST_INTER);
3356 %}
3358 // Unsigned (positive) Integer Immediate: 13-bit
3359 operand immU13() %{
3360 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3361 match(ConI);
3362 op_cost(0);
3364 format %{ %}
3365 interface(CONST_INTER);
3366 %}
3368 // Integer Immediate: 6-bit
3369 operand immU6() %{
3370 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3371 match(ConI);
3372 op_cost(0);
3373 format %{ %}
3374 interface(CONST_INTER);
3375 %}
3377 // Integer Immediate: 11-bit
3378 operand immI11() %{
3379 predicate(Assembler::is_simm11(n->get_int()));
3380 match(ConI);
3381 op_cost(0);
3382 format %{ %}
3383 interface(CONST_INTER);
3384 %}
3386 // Integer Immediate: 5-bit
3387 operand immI5() %{
3388 predicate(Assembler::is_simm5(n->get_int()));
3389 match(ConI);
3390 op_cost(0);
3391 format %{ %}
3392 interface(CONST_INTER);
3393 %}
3395 // Integer Immediate: 0-bit
3396 operand immI0() %{
3397 predicate(n->get_int() == 0);
3398 match(ConI);
3399 op_cost(0);
3401 format %{ %}
3402 interface(CONST_INTER);
3403 %}
3405 // Integer Immediate: the value 10
3406 operand immI10() %{
3407 predicate(n->get_int() == 10);
3408 match(ConI);
3409 op_cost(0);
3411 format %{ %}
3412 interface(CONST_INTER);
3413 %}
3415 // Integer Immediate: the values 0-31
3416 operand immU5() %{
3417 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3418 match(ConI);
3419 op_cost(0);
3421 format %{ %}
3422 interface(CONST_INTER);
3423 %}
3425 // Integer Immediate: the values 1-31
3426 operand immI_1_31() %{
3427 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3428 match(ConI);
3429 op_cost(0);
3431 format %{ %}
3432 interface(CONST_INTER);
3433 %}
3435 // Integer Immediate: the values 32-63
3436 operand immI_32_63() %{
3437 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3438 match(ConI);
3439 op_cost(0);
3441 format %{ %}
3442 interface(CONST_INTER);
3443 %}
3445 // Immediates for special shifts (sign extend)
3447 // Integer Immediate: the value 16
3448 operand immI_16() %{
3449 predicate(n->get_int() == 16);
3450 match(ConI);
3451 op_cost(0);
3453 format %{ %}
3454 interface(CONST_INTER);
3455 %}
3457 // Integer Immediate: the value 24
3458 operand immI_24() %{
3459 predicate(n->get_int() == 24);
3460 match(ConI);
3461 op_cost(0);
3463 format %{ %}
3464 interface(CONST_INTER);
3465 %}
3467 // Integer Immediate: the value 255
3468 operand immI_255() %{
3469 predicate( n->get_int() == 255 );
3470 match(ConI);
3471 op_cost(0);
3473 format %{ %}
3474 interface(CONST_INTER);
3475 %}
3477 // Integer Immediate: the value 65535
3478 operand immI_65535() %{
3479 predicate(n->get_int() == 65535);
3480 match(ConI);
3481 op_cost(0);
3483 format %{ %}
3484 interface(CONST_INTER);
3485 %}
3487 // Long Immediate: the value FF
3488 operand immL_FF() %{
3489 predicate( n->get_long() == 0xFFL );
3490 match(ConL);
3491 op_cost(0);
3493 format %{ %}
3494 interface(CONST_INTER);
3495 %}
3497 // Long Immediate: the value FFFF
3498 operand immL_FFFF() %{
3499 predicate( n->get_long() == 0xFFFFL );
3500 match(ConL);
3501 op_cost(0);
3503 format %{ %}
3504 interface(CONST_INTER);
3505 %}
3507 // Pointer Immediate: 32 or 64-bit
3508 operand immP() %{
3509 match(ConP);
3511 op_cost(5);
3512 // formats are generated automatically for constants and base registers
3513 format %{ %}
3514 interface(CONST_INTER);
3515 %}
3517 #ifdef _LP64
3518 // Pointer Immediate: 64-bit
3519 operand immP_set() %{
3520 predicate(!VM_Version::is_niagara_plus());
3521 match(ConP);
3523 op_cost(5);
3524 // formats are generated automatically for constants and base registers
3525 format %{ %}
3526 interface(CONST_INTER);
3527 %}
3529 // Pointer Immediate: 64-bit
3530 // From Niagara2 processors on a load should be better than materializing.
3531 operand immP_load() %{
3532 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3533 match(ConP);
3535 op_cost(5);
3536 // formats are generated automatically for constants and base registers
3537 format %{ %}
3538 interface(CONST_INTER);
3539 %}
3541 // Pointer Immediate: 64-bit
3542 operand immP_no_oop_cheap() %{
3543 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3544 match(ConP);
3546 op_cost(5);
3547 // formats are generated automatically for constants and base registers
3548 format %{ %}
3549 interface(CONST_INTER);
3550 %}
3551 #endif
3553 operand immP13() %{
3554 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3555 match(ConP);
3556 op_cost(0);
3558 format %{ %}
3559 interface(CONST_INTER);
3560 %}
3562 operand immP0() %{
3563 predicate(n->get_ptr() == 0);
3564 match(ConP);
3565 op_cost(0);
3567 format %{ %}
3568 interface(CONST_INTER);
3569 %}
3571 operand immP_poll() %{
3572 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3573 match(ConP);
3575 // formats are generated automatically for constants and base registers
3576 format %{ %}
3577 interface(CONST_INTER);
3578 %}
3580 // Pointer Immediate
3581 operand immN()
3582 %{
3583 match(ConN);
3585 op_cost(10);
3586 format %{ %}
3587 interface(CONST_INTER);
3588 %}
3590 operand immNKlass()
3591 %{
3592 match(ConNKlass);
3594 op_cost(10);
3595 format %{ %}
3596 interface(CONST_INTER);
3597 %}
3599 // NULL Pointer Immediate
3600 operand immN0()
3601 %{
3602 predicate(n->get_narrowcon() == 0);
3603 match(ConN);
3605 op_cost(0);
3606 format %{ %}
3607 interface(CONST_INTER);
3608 %}
3610 operand immL() %{
3611 match(ConL);
3612 op_cost(40);
3613 // formats are generated automatically for constants and base registers
3614 format %{ %}
3615 interface(CONST_INTER);
3616 %}
3618 operand immL0() %{
3619 predicate(n->get_long() == 0L);
3620 match(ConL);
3621 op_cost(0);
3622 // formats are generated automatically for constants and base registers
3623 format %{ %}
3624 interface(CONST_INTER);
3625 %}
3627 // Integer Immediate: 5-bit
3628 operand immL5() %{
3629 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3630 match(ConL);
3631 op_cost(0);
3632 format %{ %}
3633 interface(CONST_INTER);
3634 %}
3636 // Long Immediate: 13-bit
3637 operand immL13() %{
3638 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3639 match(ConL);
3640 op_cost(0);
3642 format %{ %}
3643 interface(CONST_INTER);
3644 %}
3646 // Long Immediate: 13-bit minus 7
3647 operand immL13m7() %{
3648 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3649 match(ConL);
3650 op_cost(0);
3652 format %{ %}
3653 interface(CONST_INTER);
3654 %}
3656 // Long Immediate: low 32-bit mask
3657 operand immL_32bits() %{
3658 predicate(n->get_long() == 0xFFFFFFFFL);
3659 match(ConL);
3660 op_cost(0);
3662 format %{ %}
3663 interface(CONST_INTER);
3664 %}
3666 // Long Immediate: cheap (materialize in <= 3 instructions)
3667 operand immL_cheap() %{
3668 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3669 match(ConL);
3670 op_cost(0);
3672 format %{ %}
3673 interface(CONST_INTER);
3674 %}
3676 // Long Immediate: expensive (materialize in > 3 instructions)
3677 operand immL_expensive() %{
3678 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3679 match(ConL);
3680 op_cost(0);
3682 format %{ %}
3683 interface(CONST_INTER);
3684 %}
3686 // Double Immediate
3687 operand immD() %{
3688 match(ConD);
3690 op_cost(40);
3691 format %{ %}
3692 interface(CONST_INTER);
3693 %}
3695 operand immD0() %{
3696 #ifdef _LP64
3697 // on 64-bit architectures this comparision is faster
3698 predicate(jlong_cast(n->getd()) == 0);
3699 #else
3700 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3701 #endif
3702 match(ConD);
3704 op_cost(0);
3705 format %{ %}
3706 interface(CONST_INTER);
3707 %}
3709 // Float Immediate
3710 operand immF() %{
3711 match(ConF);
3713 op_cost(20);
3714 format %{ %}
3715 interface(CONST_INTER);
3716 %}
3718 // Float Immediate: 0
3719 operand immF0() %{
3720 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3721 match(ConF);
3723 op_cost(0);
3724 format %{ %}
3725 interface(CONST_INTER);
3726 %}
3728 // Integer Register Operands
3729 // Integer Register
3730 operand iRegI() %{
3731 constraint(ALLOC_IN_RC(int_reg));
3732 match(RegI);
3734 match(notemp_iRegI);
3735 match(g1RegI);
3736 match(o0RegI);
3737 match(iRegIsafe);
3739 format %{ %}
3740 interface(REG_INTER);
3741 %}
3743 operand notemp_iRegI() %{
3744 constraint(ALLOC_IN_RC(notemp_int_reg));
3745 match(RegI);
3747 match(o0RegI);
3749 format %{ %}
3750 interface(REG_INTER);
3751 %}
3753 operand o0RegI() %{
3754 constraint(ALLOC_IN_RC(o0_regI));
3755 match(iRegI);
3757 format %{ %}
3758 interface(REG_INTER);
3759 %}
3761 // Pointer Register
3762 operand iRegP() %{
3763 constraint(ALLOC_IN_RC(ptr_reg));
3764 match(RegP);
3766 match(lock_ptr_RegP);
3767 match(g1RegP);
3768 match(g2RegP);
3769 match(g3RegP);
3770 match(g4RegP);
3771 match(i0RegP);
3772 match(o0RegP);
3773 match(o1RegP);
3774 match(l7RegP);
3776 format %{ %}
3777 interface(REG_INTER);
3778 %}
3780 operand sp_ptr_RegP() %{
3781 constraint(ALLOC_IN_RC(sp_ptr_reg));
3782 match(RegP);
3783 match(iRegP);
3785 format %{ %}
3786 interface(REG_INTER);
3787 %}
3789 operand lock_ptr_RegP() %{
3790 constraint(ALLOC_IN_RC(lock_ptr_reg));
3791 match(RegP);
3792 match(i0RegP);
3793 match(o0RegP);
3794 match(o1RegP);
3795 match(l7RegP);
3797 format %{ %}
3798 interface(REG_INTER);
3799 %}
3801 operand g1RegP() %{
3802 constraint(ALLOC_IN_RC(g1_regP));
3803 match(iRegP);
3805 format %{ %}
3806 interface(REG_INTER);
3807 %}
3809 operand g2RegP() %{
3810 constraint(ALLOC_IN_RC(g2_regP));
3811 match(iRegP);
3813 format %{ %}
3814 interface(REG_INTER);
3815 %}
3817 operand g3RegP() %{
3818 constraint(ALLOC_IN_RC(g3_regP));
3819 match(iRegP);
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3825 operand g1RegI() %{
3826 constraint(ALLOC_IN_RC(g1_regI));
3827 match(iRegI);
3829 format %{ %}
3830 interface(REG_INTER);
3831 %}
3833 operand g3RegI() %{
3834 constraint(ALLOC_IN_RC(g3_regI));
3835 match(iRegI);
3837 format %{ %}
3838 interface(REG_INTER);
3839 %}
3841 operand g4RegI() %{
3842 constraint(ALLOC_IN_RC(g4_regI));
3843 match(iRegI);
3845 format %{ %}
3846 interface(REG_INTER);
3847 %}
3849 operand g4RegP() %{
3850 constraint(ALLOC_IN_RC(g4_regP));
3851 match(iRegP);
3853 format %{ %}
3854 interface(REG_INTER);
3855 %}
3857 operand i0RegP() %{
3858 constraint(ALLOC_IN_RC(i0_regP));
3859 match(iRegP);
3861 format %{ %}
3862 interface(REG_INTER);
3863 %}
3865 operand o0RegP() %{
3866 constraint(ALLOC_IN_RC(o0_regP));
3867 match(iRegP);
3869 format %{ %}
3870 interface(REG_INTER);
3871 %}
3873 operand o1RegP() %{
3874 constraint(ALLOC_IN_RC(o1_regP));
3875 match(iRegP);
3877 format %{ %}
3878 interface(REG_INTER);
3879 %}
3881 operand o2RegP() %{
3882 constraint(ALLOC_IN_RC(o2_regP));
3883 match(iRegP);
3885 format %{ %}
3886 interface(REG_INTER);
3887 %}
3889 operand o7RegP() %{
3890 constraint(ALLOC_IN_RC(o7_regP));
3891 match(iRegP);
3893 format %{ %}
3894 interface(REG_INTER);
3895 %}
3897 operand l7RegP() %{
3898 constraint(ALLOC_IN_RC(l7_regP));
3899 match(iRegP);
3901 format %{ %}
3902 interface(REG_INTER);
3903 %}
3905 operand o7RegI() %{
3906 constraint(ALLOC_IN_RC(o7_regI));
3907 match(iRegI);
3909 format %{ %}
3910 interface(REG_INTER);
3911 %}
3913 operand iRegN() %{
3914 constraint(ALLOC_IN_RC(int_reg));
3915 match(RegN);
3917 format %{ %}
3918 interface(REG_INTER);
3919 %}
3921 // Long Register
3922 operand iRegL() %{
3923 constraint(ALLOC_IN_RC(long_reg));
3924 match(RegL);
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3930 operand o2RegL() %{
3931 constraint(ALLOC_IN_RC(o2_regL));
3932 match(iRegL);
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3938 operand o7RegL() %{
3939 constraint(ALLOC_IN_RC(o7_regL));
3940 match(iRegL);
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3946 operand g1RegL() %{
3947 constraint(ALLOC_IN_RC(g1_regL));
3948 match(iRegL);
3950 format %{ %}
3951 interface(REG_INTER);
3952 %}
3954 operand g3RegL() %{
3955 constraint(ALLOC_IN_RC(g3_regL));
3956 match(iRegL);
3958 format %{ %}
3959 interface(REG_INTER);
3960 %}
3962 // Int Register safe
3963 // This is 64bit safe
3964 operand iRegIsafe() %{
3965 constraint(ALLOC_IN_RC(long_reg));
3967 match(iRegI);
3969 format %{ %}
3970 interface(REG_INTER);
3971 %}
3973 // Condition Code Flag Register
3974 operand flagsReg() %{
3975 constraint(ALLOC_IN_RC(int_flags));
3976 match(RegFlags);
3978 format %{ "ccr" %} // both ICC and XCC
3979 interface(REG_INTER);
3980 %}
3982 // Condition Code Register, unsigned comparisons.
3983 operand flagsRegU() %{
3984 constraint(ALLOC_IN_RC(int_flags));
3985 match(RegFlags);
3987 format %{ "icc_U" %}
3988 interface(REG_INTER);
3989 %}
3991 // Condition Code Register, pointer comparisons.
3992 operand flagsRegP() %{
3993 constraint(ALLOC_IN_RC(int_flags));
3994 match(RegFlags);
3996 #ifdef _LP64
3997 format %{ "xcc_P" %}
3998 #else
3999 format %{ "icc_P" %}
4000 #endif
4001 interface(REG_INTER);
4002 %}
4004 // Condition Code Register, long comparisons.
4005 operand flagsRegL() %{
4006 constraint(ALLOC_IN_RC(int_flags));
4007 match(RegFlags);
4009 format %{ "xcc_L" %}
4010 interface(REG_INTER);
4011 %}
4013 // Condition Code Register, floating comparisons, unordered same as "less".
4014 operand flagsRegF() %{
4015 constraint(ALLOC_IN_RC(float_flags));
4016 match(RegFlags);
4017 match(flagsRegF0);
4019 format %{ %}
4020 interface(REG_INTER);
4021 %}
4023 operand flagsRegF0() %{
4024 constraint(ALLOC_IN_RC(float_flag0));
4025 match(RegFlags);
4027 format %{ %}
4028 interface(REG_INTER);
4029 %}
4032 // Condition Code Flag Register used by long compare
4033 operand flagsReg_long_LTGE() %{
4034 constraint(ALLOC_IN_RC(int_flags));
4035 match(RegFlags);
4036 format %{ "icc_LTGE" %}
4037 interface(REG_INTER);
4038 %}
4039 operand flagsReg_long_EQNE() %{
4040 constraint(ALLOC_IN_RC(int_flags));
4041 match(RegFlags);
4042 format %{ "icc_EQNE" %}
4043 interface(REG_INTER);
4044 %}
4045 operand flagsReg_long_LEGT() %{
4046 constraint(ALLOC_IN_RC(int_flags));
4047 match(RegFlags);
4048 format %{ "icc_LEGT" %}
4049 interface(REG_INTER);
4050 %}
4053 operand regD() %{
4054 constraint(ALLOC_IN_RC(dflt_reg));
4055 match(RegD);
4057 match(regD_low);
4059 format %{ %}
4060 interface(REG_INTER);
4061 %}
4063 operand regF() %{
4064 constraint(ALLOC_IN_RC(sflt_reg));
4065 match(RegF);
4067 format %{ %}
4068 interface(REG_INTER);
4069 %}
4071 operand regD_low() %{
4072 constraint(ALLOC_IN_RC(dflt_low_reg));
4073 match(regD);
4075 format %{ %}
4076 interface(REG_INTER);
4077 %}
4079 // Special Registers
4081 // Method Register
4082 operand inline_cache_regP(iRegP reg) %{
4083 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4084 match(reg);
4085 format %{ %}
4086 interface(REG_INTER);
4087 %}
4089 operand interpreter_method_oop_regP(iRegP reg) %{
4090 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4091 match(reg);
4092 format %{ %}
4093 interface(REG_INTER);
4094 %}
4097 //----------Complex Operands---------------------------------------------------
4098 // Indirect Memory Reference
4099 operand indirect(sp_ptr_RegP reg) %{
4100 constraint(ALLOC_IN_RC(sp_ptr_reg));
4101 match(reg);
4103 op_cost(100);
4104 format %{ "[$reg]" %}
4105 interface(MEMORY_INTER) %{
4106 base($reg);
4107 index(0x0);
4108 scale(0x0);
4109 disp(0x0);
4110 %}
4111 %}
4113 // Indirect with simm13 Offset
4114 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4115 constraint(ALLOC_IN_RC(sp_ptr_reg));
4116 match(AddP reg offset);
4118 op_cost(100);
4119 format %{ "[$reg + $offset]" %}
4120 interface(MEMORY_INTER) %{
4121 base($reg);
4122 index(0x0);
4123 scale(0x0);
4124 disp($offset);
4125 %}
4126 %}
4128 // Indirect with simm13 Offset minus 7
4129 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4130 constraint(ALLOC_IN_RC(sp_ptr_reg));
4131 match(AddP reg offset);
4133 op_cost(100);
4134 format %{ "[$reg + $offset]" %}
4135 interface(MEMORY_INTER) %{
4136 base($reg);
4137 index(0x0);
4138 scale(0x0);
4139 disp($offset);
4140 %}
4141 %}
4143 // Note: Intel has a swapped version also, like this:
4144 //operand indOffsetX(iRegI reg, immP offset) %{
4145 // constraint(ALLOC_IN_RC(int_reg));
4146 // match(AddP offset reg);
4147 //
4148 // op_cost(100);
4149 // format %{ "[$reg + $offset]" %}
4150 // interface(MEMORY_INTER) %{
4151 // base($reg);
4152 // index(0x0);
4153 // scale(0x0);
4154 // disp($offset);
4155 // %}
4156 //%}
4157 //// However, it doesn't make sense for SPARC, since
4158 // we have no particularly good way to embed oops in
4159 // single instructions.
4161 // Indirect with Register Index
4162 operand indIndex(iRegP addr, iRegX index) %{
4163 constraint(ALLOC_IN_RC(ptr_reg));
4164 match(AddP addr index);
4166 op_cost(100);
4167 format %{ "[$addr + $index]" %}
4168 interface(MEMORY_INTER) %{
4169 base($addr);
4170 index($index);
4171 scale(0x0);
4172 disp(0x0);
4173 %}
4174 %}
4176 //----------Special Memory Operands--------------------------------------------
4177 // Stack Slot Operand - This operand is used for loading and storing temporary
4178 // values on the stack where a match requires a value to
4179 // flow through memory.
4180 operand stackSlotI(sRegI reg) %{
4181 constraint(ALLOC_IN_RC(stack_slots));
4182 op_cost(100);
4183 //match(RegI);
4184 format %{ "[$reg]" %}
4185 interface(MEMORY_INTER) %{
4186 base(0xE); // R_SP
4187 index(0x0);
4188 scale(0x0);
4189 disp($reg); // Stack Offset
4190 %}
4191 %}
4193 operand stackSlotP(sRegP reg) %{
4194 constraint(ALLOC_IN_RC(stack_slots));
4195 op_cost(100);
4196 //match(RegP);
4197 format %{ "[$reg]" %}
4198 interface(MEMORY_INTER) %{
4199 base(0xE); // R_SP
4200 index(0x0);
4201 scale(0x0);
4202 disp($reg); // Stack Offset
4203 %}
4204 %}
4206 operand stackSlotF(sRegF reg) %{
4207 constraint(ALLOC_IN_RC(stack_slots));
4208 op_cost(100);
4209 //match(RegF);
4210 format %{ "[$reg]" %}
4211 interface(MEMORY_INTER) %{
4212 base(0xE); // R_SP
4213 index(0x0);
4214 scale(0x0);
4215 disp($reg); // Stack Offset
4216 %}
4217 %}
4218 operand stackSlotD(sRegD reg) %{
4219 constraint(ALLOC_IN_RC(stack_slots));
4220 op_cost(100);
4221 //match(RegD);
4222 format %{ "[$reg]" %}
4223 interface(MEMORY_INTER) %{
4224 base(0xE); // R_SP
4225 index(0x0);
4226 scale(0x0);
4227 disp($reg); // Stack Offset
4228 %}
4229 %}
4230 operand stackSlotL(sRegL reg) %{
4231 constraint(ALLOC_IN_RC(stack_slots));
4232 op_cost(100);
4233 //match(RegL);
4234 format %{ "[$reg]" %}
4235 interface(MEMORY_INTER) %{
4236 base(0xE); // R_SP
4237 index(0x0);
4238 scale(0x0);
4239 disp($reg); // Stack Offset
4240 %}
4241 %}
4243 // Operands for expressing Control Flow
4244 // NOTE: Label is a predefined operand which should not be redefined in
4245 // the AD file. It is generically handled within the ADLC.
4247 //----------Conditional Branch Operands----------------------------------------
4248 // Comparison Op - This is the operation of the comparison, and is limited to
4249 // the following set of codes:
4250 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4251 //
4252 // Other attributes of the comparison, such as unsignedness, are specified
4253 // by the comparison instruction that sets a condition code flags register.
4254 // That result is represented by a flags operand whose subtype is appropriate
4255 // to the unsignedness (etc.) of the comparison.
4256 //
4257 // Later, the instruction which matches both the Comparison Op (a Bool) and
4258 // the flags (produced by the Cmp) specifies the coding of the comparison op
4259 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4261 operand cmpOp() %{
4262 match(Bool);
4264 format %{ "" %}
4265 interface(COND_INTER) %{
4266 equal(0x1);
4267 not_equal(0x9);
4268 less(0x3);
4269 greater_equal(0xB);
4270 less_equal(0x2);
4271 greater(0xA);
4272 overflow(0x7);
4273 no_overflow(0xF);
4274 %}
4275 %}
4277 // Comparison Op, unsigned
4278 operand cmpOpU() %{
4279 match(Bool);
4280 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4281 n->as_Bool()->_test._test != BoolTest::no_overflow);
4283 format %{ "u" %}
4284 interface(COND_INTER) %{
4285 equal(0x1);
4286 not_equal(0x9);
4287 less(0x5);
4288 greater_equal(0xD);
4289 less_equal(0x4);
4290 greater(0xC);
4291 overflow(0x7);
4292 no_overflow(0xF);
4293 %}
4294 %}
4296 // Comparison Op, pointer (same as unsigned)
4297 operand cmpOpP() %{
4298 match(Bool);
4299 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4300 n->as_Bool()->_test._test != BoolTest::no_overflow);
4302 format %{ "p" %}
4303 interface(COND_INTER) %{
4304 equal(0x1);
4305 not_equal(0x9);
4306 less(0x5);
4307 greater_equal(0xD);
4308 less_equal(0x4);
4309 greater(0xC);
4310 overflow(0x7);
4311 no_overflow(0xF);
4312 %}
4313 %}
4315 // Comparison Op, branch-register encoding
4316 operand cmpOp_reg() %{
4317 match(Bool);
4318 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4319 n->as_Bool()->_test._test != BoolTest::no_overflow);
4321 format %{ "" %}
4322 interface(COND_INTER) %{
4323 equal (0x1);
4324 not_equal (0x5);
4325 less (0x3);
4326 greater_equal(0x7);
4327 less_equal (0x2);
4328 greater (0x6);
4329 overflow(0x7); // not supported
4330 no_overflow(0xF); // not supported
4331 %}
4332 %}
4334 // Comparison Code, floating, unordered same as less
4335 operand cmpOpF() %{
4336 match(Bool);
4337 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4338 n->as_Bool()->_test._test != BoolTest::no_overflow);
4340 format %{ "fl" %}
4341 interface(COND_INTER) %{
4342 equal(0x9);
4343 not_equal(0x1);
4344 less(0x3);
4345 greater_equal(0xB);
4346 less_equal(0xE);
4347 greater(0x6);
4349 overflow(0x7); // not supported
4350 no_overflow(0xF); // not supported
4351 %}
4352 %}
4354 // Used by long compare
4355 operand cmpOp_commute() %{
4356 match(Bool);
4357 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4358 n->as_Bool()->_test._test != BoolTest::no_overflow);
4360 format %{ "" %}
4361 interface(COND_INTER) %{
4362 equal(0x1);
4363 not_equal(0x9);
4364 less(0xA);
4365 greater_equal(0x2);
4366 less_equal(0xB);
4367 greater(0x3);
4368 overflow(0x7);
4369 no_overflow(0xF);
4370 %}
4371 %}
4373 //----------OPERAND CLASSES----------------------------------------------------
4374 // Operand Classes are groups of operands that are used to simplify
4375 // instruction definitions by not requiring the AD writer to specify separate
4376 // instructions for every form of operand when the instruction accepts
4377 // multiple operand types with the same basic encoding and format. The classic
4378 // case of this is memory operands.
4379 opclass memory( indirect, indOffset13, indIndex );
4380 opclass indIndexMemory( indIndex );
4382 //----------PIPELINE-----------------------------------------------------------
4383 pipeline %{
4385 //----------ATTRIBUTES---------------------------------------------------------
4386 attributes %{
4387 fixed_size_instructions; // Fixed size instructions
4388 branch_has_delay_slot; // Branch has delay slot following
4389 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4390 instruction_unit_size = 4; // An instruction is 4 bytes long
4391 instruction_fetch_unit_size = 16; // The processor fetches one line
4392 instruction_fetch_units = 1; // of 16 bytes
4394 // List of nop instructions
4395 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4396 %}
4398 //----------RESOURCES----------------------------------------------------------
4399 // Resources are the functional units available to the machine
4400 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4402 //----------PIPELINE DESCRIPTION-----------------------------------------------
4403 // Pipeline Description specifies the stages in the machine's pipeline
4405 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4407 //----------PIPELINE CLASSES---------------------------------------------------
4408 // Pipeline Classes describe the stages in which input and output are
4409 // referenced by the hardware pipeline.
4411 // Integer ALU reg-reg operation
4412 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4413 single_instruction;
4414 dst : E(write);
4415 src1 : R(read);
4416 src2 : R(read);
4417 IALU : R;
4418 %}
4420 // Integer ALU reg-reg long operation
4421 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4422 instruction_count(2);
4423 dst : E(write);
4424 src1 : R(read);
4425 src2 : R(read);
4426 IALU : R;
4427 IALU : R;
4428 %}
4430 // Integer ALU reg-reg long dependent operation
4431 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4432 instruction_count(1); multiple_bundles;
4433 dst : E(write);
4434 src1 : R(read);
4435 src2 : R(read);
4436 cr : E(write);
4437 IALU : R(2);
4438 %}
4440 // Integer ALU reg-imm operaion
4441 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4442 single_instruction;
4443 dst : E(write);
4444 src1 : R(read);
4445 IALU : R;
4446 %}
4448 // Integer ALU reg-reg operation with condition code
4449 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4450 single_instruction;
4451 dst : E(write);
4452 cr : E(write);
4453 src1 : R(read);
4454 src2 : R(read);
4455 IALU : R;
4456 %}
4458 // Integer ALU reg-imm operation with condition code
4459 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4460 single_instruction;
4461 dst : E(write);
4462 cr : E(write);
4463 src1 : R(read);
4464 IALU : R;
4465 %}
4467 // Integer ALU zero-reg operation
4468 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4469 single_instruction;
4470 dst : E(write);
4471 src2 : R(read);
4472 IALU : R;
4473 %}
4475 // Integer ALU zero-reg operation with condition code only
4476 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4477 single_instruction;
4478 cr : E(write);
4479 src : R(read);
4480 IALU : R;
4481 %}
4483 // Integer ALU reg-reg operation with condition code only
4484 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4485 single_instruction;
4486 cr : E(write);
4487 src1 : R(read);
4488 src2 : R(read);
4489 IALU : R;
4490 %}
4492 // Integer ALU reg-imm operation with condition code only
4493 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4494 single_instruction;
4495 cr : E(write);
4496 src1 : R(read);
4497 IALU : R;
4498 %}
4500 // Integer ALU reg-reg-zero operation with condition code only
4501 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4502 single_instruction;
4503 cr : E(write);
4504 src1 : R(read);
4505 src2 : R(read);
4506 IALU : R;
4507 %}
4509 // Integer ALU reg-imm-zero operation with condition code only
4510 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4511 single_instruction;
4512 cr : E(write);
4513 src1 : R(read);
4514 IALU : R;
4515 %}
4517 // Integer ALU reg-reg operation with condition code, src1 modified
4518 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4519 single_instruction;
4520 cr : E(write);
4521 src1 : E(write);
4522 src1 : R(read);
4523 src2 : R(read);
4524 IALU : R;
4525 %}
4527 // Integer ALU reg-imm operation with condition code, src1 modified
4528 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4529 single_instruction;
4530 cr : E(write);
4531 src1 : E(write);
4532 src1 : R(read);
4533 IALU : R;
4534 %}
4536 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4537 multiple_bundles;
4538 dst : E(write)+4;
4539 cr : E(write);
4540 src1 : R(read);
4541 src2 : R(read);
4542 IALU : R(3);
4543 BR : R(2);
4544 %}
4546 // Integer ALU operation
4547 pipe_class ialu_none(iRegI dst) %{
4548 single_instruction;
4549 dst : E(write);
4550 IALU : R;
4551 %}
4553 // Integer ALU reg operation
4554 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4555 single_instruction; may_have_no_code;
4556 dst : E(write);
4557 src : R(read);
4558 IALU : R;
4559 %}
4561 // Integer ALU reg conditional operation
4562 // This instruction has a 1 cycle stall, and cannot execute
4563 // in the same cycle as the instruction setting the condition
4564 // code. We kludge this by pretending to read the condition code
4565 // 1 cycle earlier, and by marking the functional units as busy
4566 // for 2 cycles with the result available 1 cycle later than
4567 // is really the case.
4568 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4569 single_instruction;
4570 op2_out : C(write);
4571 op1 : R(read);
4572 cr : R(read); // This is really E, with a 1 cycle stall
4573 BR : R(2);
4574 MS : R(2);
4575 %}
4577 #ifdef _LP64
4578 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4579 instruction_count(1); multiple_bundles;
4580 dst : C(write)+1;
4581 src : R(read)+1;
4582 IALU : R(1);
4583 BR : E(2);
4584 MS : E(2);
4585 %}
4586 #endif
4588 // Integer ALU reg operation
4589 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4590 single_instruction; may_have_no_code;
4591 dst : E(write);
4592 src : R(read);
4593 IALU : R;
4594 %}
4595 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4596 single_instruction; may_have_no_code;
4597 dst : E(write);
4598 src : R(read);
4599 IALU : R;
4600 %}
4602 // Two integer ALU reg operations
4603 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4604 instruction_count(2);
4605 dst : E(write);
4606 src : R(read);
4607 A0 : R;
4608 A1 : R;
4609 %}
4611 // Two integer ALU reg operations
4612 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4613 instruction_count(2); may_have_no_code;
4614 dst : E(write);
4615 src : R(read);
4616 A0 : R;
4617 A1 : R;
4618 %}
4620 // Integer ALU imm operation
4621 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4622 single_instruction;
4623 dst : E(write);
4624 IALU : R;
4625 %}
4627 // Integer ALU reg-reg with carry operation
4628 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4629 single_instruction;
4630 dst : E(write);
4631 src1 : R(read);
4632 src2 : R(read);
4633 IALU : R;
4634 %}
4636 // Integer ALU cc operation
4637 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4638 single_instruction;
4639 dst : E(write);
4640 cc : R(read);
4641 IALU : R;
4642 %}
4644 // Integer ALU cc / second IALU operation
4645 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4646 instruction_count(1); multiple_bundles;
4647 dst : E(write)+1;
4648 src : R(read);
4649 IALU : R;
4650 %}
4652 // Integer ALU cc / second IALU operation
4653 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4654 instruction_count(1); multiple_bundles;
4655 dst : E(write)+1;
4656 p : R(read);
4657 q : R(read);
4658 IALU : R;
4659 %}
4661 // Integer ALU hi-lo-reg operation
4662 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4663 instruction_count(1); multiple_bundles;
4664 dst : E(write)+1;
4665 IALU : R(2);
4666 %}
4668 // Float ALU hi-lo-reg operation (with temp)
4669 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4670 instruction_count(1); multiple_bundles;
4671 dst : E(write)+1;
4672 IALU : R(2);
4673 %}
4675 // Long Constant
4676 pipe_class loadConL( iRegL dst, immL src ) %{
4677 instruction_count(2); multiple_bundles;
4678 dst : E(write)+1;
4679 IALU : R(2);
4680 IALU : R(2);
4681 %}
4683 // Pointer Constant
4684 pipe_class loadConP( iRegP dst, immP src ) %{
4685 instruction_count(0); multiple_bundles;
4686 fixed_latency(6);
4687 %}
4689 // Polling Address
4690 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4691 #ifdef _LP64
4692 instruction_count(0); multiple_bundles;
4693 fixed_latency(6);
4694 #else
4695 dst : E(write);
4696 IALU : R;
4697 #endif
4698 %}
4700 // Long Constant small
4701 pipe_class loadConLlo( iRegL dst, immL src ) %{
4702 instruction_count(2);
4703 dst : E(write);
4704 IALU : R;
4705 IALU : R;
4706 %}
4708 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4709 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4710 instruction_count(1); multiple_bundles;
4711 src : R(read);
4712 dst : M(write)+1;
4713 IALU : R;
4714 MS : E;
4715 %}
4717 // Integer ALU nop operation
4718 pipe_class ialu_nop() %{
4719 single_instruction;
4720 IALU : R;
4721 %}
4723 // Integer ALU nop operation
4724 pipe_class ialu_nop_A0() %{
4725 single_instruction;
4726 A0 : R;
4727 %}
4729 // Integer ALU nop operation
4730 pipe_class ialu_nop_A1() %{
4731 single_instruction;
4732 A1 : R;
4733 %}
4735 // Integer Multiply reg-reg operation
4736 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4737 single_instruction;
4738 dst : E(write);
4739 src1 : R(read);
4740 src2 : R(read);
4741 MS : R(5);
4742 %}
4744 // Integer Multiply reg-imm operation
4745 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4746 single_instruction;
4747 dst : E(write);
4748 src1 : R(read);
4749 MS : R(5);
4750 %}
4752 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4753 single_instruction;
4754 dst : E(write)+4;
4755 src1 : R(read);
4756 src2 : R(read);
4757 MS : R(6);
4758 %}
4760 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4761 single_instruction;
4762 dst : E(write)+4;
4763 src1 : R(read);
4764 MS : R(6);
4765 %}
4767 // Integer Divide reg-reg
4768 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4769 instruction_count(1); multiple_bundles;
4770 dst : E(write);
4771 temp : E(write);
4772 src1 : R(read);
4773 src2 : R(read);
4774 temp : R(read);
4775 MS : R(38);
4776 %}
4778 // Integer Divide reg-imm
4779 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4780 instruction_count(1); multiple_bundles;
4781 dst : E(write);
4782 temp : E(write);
4783 src1 : R(read);
4784 temp : R(read);
4785 MS : R(38);
4786 %}
4788 // Long Divide
4789 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4790 dst : E(write)+71;
4791 src1 : R(read);
4792 src2 : R(read)+1;
4793 MS : R(70);
4794 %}
4796 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4797 dst : E(write)+71;
4798 src1 : R(read);
4799 MS : R(70);
4800 %}
4802 // Floating Point Add Float
4803 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4804 single_instruction;
4805 dst : X(write);
4806 src1 : E(read);
4807 src2 : E(read);
4808 FA : R;
4809 %}
4811 // Floating Point Add Double
4812 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4813 single_instruction;
4814 dst : X(write);
4815 src1 : E(read);
4816 src2 : E(read);
4817 FA : R;
4818 %}
4820 // Floating Point Conditional Move based on integer flags
4821 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4822 single_instruction;
4823 dst : X(write);
4824 src : E(read);
4825 cr : R(read);
4826 FA : R(2);
4827 BR : R(2);
4828 %}
4830 // Floating Point Conditional Move based on integer flags
4831 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4832 single_instruction;
4833 dst : X(write);
4834 src : E(read);
4835 cr : R(read);
4836 FA : R(2);
4837 BR : R(2);
4838 %}
4840 // Floating Point Multiply Float
4841 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4842 single_instruction;
4843 dst : X(write);
4844 src1 : E(read);
4845 src2 : E(read);
4846 FM : R;
4847 %}
4849 // Floating Point Multiply Double
4850 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4851 single_instruction;
4852 dst : X(write);
4853 src1 : E(read);
4854 src2 : E(read);
4855 FM : R;
4856 %}
4858 // Floating Point Divide Float
4859 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4860 single_instruction;
4861 dst : X(write);
4862 src1 : E(read);
4863 src2 : E(read);
4864 FM : R;
4865 FDIV : C(14);
4866 %}
4868 // Floating Point Divide Double
4869 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4870 single_instruction;
4871 dst : X(write);
4872 src1 : E(read);
4873 src2 : E(read);
4874 FM : R;
4875 FDIV : C(17);
4876 %}
4878 // Floating Point Move/Negate/Abs Float
4879 pipe_class faddF_reg(regF dst, regF src) %{
4880 single_instruction;
4881 dst : W(write);
4882 src : E(read);
4883 FA : R(1);
4884 %}
4886 // Floating Point Move/Negate/Abs Double
4887 pipe_class faddD_reg(regD dst, regD src) %{
4888 single_instruction;
4889 dst : W(write);
4890 src : E(read);
4891 FA : R;
4892 %}
4894 // Floating Point Convert F->D
4895 pipe_class fcvtF2D(regD dst, regF src) %{
4896 single_instruction;
4897 dst : X(write);
4898 src : E(read);
4899 FA : R;
4900 %}
4902 // Floating Point Convert I->D
4903 pipe_class fcvtI2D(regD dst, regF src) %{
4904 single_instruction;
4905 dst : X(write);
4906 src : E(read);
4907 FA : R;
4908 %}
4910 // Floating Point Convert LHi->D
4911 pipe_class fcvtLHi2D(regD dst, regD src) %{
4912 single_instruction;
4913 dst : X(write);
4914 src : E(read);
4915 FA : R;
4916 %}
4918 // Floating Point Convert L->D
4919 pipe_class fcvtL2D(regD dst, regF src) %{
4920 single_instruction;
4921 dst : X(write);
4922 src : E(read);
4923 FA : R;
4924 %}
4926 // Floating Point Convert L->F
4927 pipe_class fcvtL2F(regD dst, regF src) %{
4928 single_instruction;
4929 dst : X(write);
4930 src : E(read);
4931 FA : R;
4932 %}
4934 // Floating Point Convert D->F
4935 pipe_class fcvtD2F(regD dst, regF src) %{
4936 single_instruction;
4937 dst : X(write);
4938 src : E(read);
4939 FA : R;
4940 %}
4942 // Floating Point Convert I->L
4943 pipe_class fcvtI2L(regD dst, regF src) %{
4944 single_instruction;
4945 dst : X(write);
4946 src : E(read);
4947 FA : R;
4948 %}
4950 // Floating Point Convert D->F
4951 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4952 instruction_count(1); multiple_bundles;
4953 dst : X(write)+6;
4954 src : E(read);
4955 FA : R;
4956 %}
4958 // Floating Point Convert D->L
4959 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4960 instruction_count(1); multiple_bundles;
4961 dst : X(write)+6;
4962 src : E(read);
4963 FA : R;
4964 %}
4966 // Floating Point Convert F->I
4967 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4968 instruction_count(1); multiple_bundles;
4969 dst : X(write)+6;
4970 src : E(read);
4971 FA : R;
4972 %}
4974 // Floating Point Convert F->L
4975 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4976 instruction_count(1); multiple_bundles;
4977 dst : X(write)+6;
4978 src : E(read);
4979 FA : R;
4980 %}
4982 // Floating Point Convert I->F
4983 pipe_class fcvtI2F(regF dst, regF src) %{
4984 single_instruction;
4985 dst : X(write);
4986 src : E(read);
4987 FA : R;
4988 %}
4990 // Floating Point Compare
4991 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4992 single_instruction;
4993 cr : X(write);
4994 src1 : E(read);
4995 src2 : E(read);
4996 FA : R;
4997 %}
4999 // Floating Point Compare
5000 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5001 single_instruction;
5002 cr : X(write);
5003 src1 : E(read);
5004 src2 : E(read);
5005 FA : R;
5006 %}
5008 // Floating Add Nop
5009 pipe_class fadd_nop() %{
5010 single_instruction;
5011 FA : R;
5012 %}
5014 // Integer Store to Memory
5015 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5016 single_instruction;
5017 mem : R(read);
5018 src : C(read);
5019 MS : R;
5020 %}
5022 // Integer Store to Memory
5023 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5024 single_instruction;
5025 mem : R(read);
5026 src : C(read);
5027 MS : R;
5028 %}
5030 // Integer Store Zero to Memory
5031 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5032 single_instruction;
5033 mem : R(read);
5034 MS : R;
5035 %}
5037 // Special Stack Slot Store
5038 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5039 single_instruction;
5040 stkSlot : R(read);
5041 src : C(read);
5042 MS : R;
5043 %}
5045 // Special Stack Slot Store
5046 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5047 instruction_count(2); multiple_bundles;
5048 stkSlot : R(read);
5049 src : C(read);
5050 MS : R(2);
5051 %}
5053 // Float Store
5054 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5055 single_instruction;
5056 mem : R(read);
5057 src : C(read);
5058 MS : R;
5059 %}
5061 // Float Store
5062 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5063 single_instruction;
5064 mem : R(read);
5065 MS : R;
5066 %}
5068 // Double Store
5069 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5070 instruction_count(1);
5071 mem : R(read);
5072 src : C(read);
5073 MS : R;
5074 %}
5076 // Double Store
5077 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5078 single_instruction;
5079 mem : R(read);
5080 MS : R;
5081 %}
5083 // Special Stack Slot Float Store
5084 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5085 single_instruction;
5086 stkSlot : R(read);
5087 src : C(read);
5088 MS : R;
5089 %}
5091 // Special Stack Slot Double Store
5092 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5093 single_instruction;
5094 stkSlot : R(read);
5095 src : C(read);
5096 MS : R;
5097 %}
5099 // Integer Load (when sign bit propagation not needed)
5100 pipe_class iload_mem(iRegI dst, memory mem) %{
5101 single_instruction;
5102 mem : R(read);
5103 dst : C(write);
5104 MS : R;
5105 %}
5107 // Integer Load from stack operand
5108 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5109 single_instruction;
5110 mem : R(read);
5111 dst : C(write);
5112 MS : R;
5113 %}
5115 // Integer Load (when sign bit propagation or masking is needed)
5116 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5117 single_instruction;
5118 mem : R(read);
5119 dst : M(write);
5120 MS : R;
5121 %}
5123 // Float Load
5124 pipe_class floadF_mem(regF dst, memory mem) %{
5125 single_instruction;
5126 mem : R(read);
5127 dst : M(write);
5128 MS : R;
5129 %}
5131 // Float Load
5132 pipe_class floadD_mem(regD dst, memory mem) %{
5133 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5134 mem : R(read);
5135 dst : M(write);
5136 MS : R;
5137 %}
5139 // Float Load
5140 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5141 single_instruction;
5142 stkSlot : R(read);
5143 dst : M(write);
5144 MS : R;
5145 %}
5147 // Float Load
5148 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5149 single_instruction;
5150 stkSlot : R(read);
5151 dst : M(write);
5152 MS : R;
5153 %}
5155 // Memory Nop
5156 pipe_class mem_nop() %{
5157 single_instruction;
5158 MS : R;
5159 %}
5161 pipe_class sethi(iRegP dst, immI src) %{
5162 single_instruction;
5163 dst : E(write);
5164 IALU : R;
5165 %}
5167 pipe_class loadPollP(iRegP poll) %{
5168 single_instruction;
5169 poll : R(read);
5170 MS : R;
5171 %}
5173 pipe_class br(Universe br, label labl) %{
5174 single_instruction_with_delay_slot;
5175 BR : R;
5176 %}
5178 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5179 single_instruction_with_delay_slot;
5180 cr : E(read);
5181 BR : R;
5182 %}
5184 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5185 single_instruction_with_delay_slot;
5186 op1 : E(read);
5187 BR : R;
5188 MS : R;
5189 %}
5191 // Compare and branch
5192 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5193 instruction_count(2); has_delay_slot;
5194 cr : E(write);
5195 src1 : R(read);
5196 src2 : R(read);
5197 IALU : R;
5198 BR : R;
5199 %}
5201 // Compare and branch
5202 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5203 instruction_count(2); has_delay_slot;
5204 cr : E(write);
5205 src1 : R(read);
5206 IALU : R;
5207 BR : R;
5208 %}
5210 // Compare and branch using cbcond
5211 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5212 single_instruction;
5213 src1 : E(read);
5214 src2 : E(read);
5215 IALU : R;
5216 BR : R;
5217 %}
5219 // Compare and branch using cbcond
5220 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5221 single_instruction;
5222 src1 : E(read);
5223 IALU : R;
5224 BR : R;
5225 %}
5227 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5228 single_instruction_with_delay_slot;
5229 cr : E(read);
5230 BR : R;
5231 %}
5233 pipe_class br_nop() %{
5234 single_instruction;
5235 BR : R;
5236 %}
5238 pipe_class simple_call(method meth) %{
5239 instruction_count(2); multiple_bundles; force_serialization;
5240 fixed_latency(100);
5241 BR : R(1);
5242 MS : R(1);
5243 A0 : R(1);
5244 %}
5246 pipe_class compiled_call(method meth) %{
5247 instruction_count(1); multiple_bundles; force_serialization;
5248 fixed_latency(100);
5249 MS : R(1);
5250 %}
5252 pipe_class call(method meth) %{
5253 instruction_count(0); multiple_bundles; force_serialization;
5254 fixed_latency(100);
5255 %}
5257 pipe_class tail_call(Universe ignore, label labl) %{
5258 single_instruction; has_delay_slot;
5259 fixed_latency(100);
5260 BR : R(1);
5261 MS : R(1);
5262 %}
5264 pipe_class ret(Universe ignore) %{
5265 single_instruction; has_delay_slot;
5266 BR : R(1);
5267 MS : R(1);
5268 %}
5270 pipe_class ret_poll(g3RegP poll) %{
5271 instruction_count(3); has_delay_slot;
5272 poll : E(read);
5273 MS : R;
5274 %}
5276 // The real do-nothing guy
5277 pipe_class empty( ) %{
5278 instruction_count(0);
5279 %}
5281 pipe_class long_memory_op() %{
5282 instruction_count(0); multiple_bundles; force_serialization;
5283 fixed_latency(25);
5284 MS : R(1);
5285 %}
5287 // Check-cast
5288 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5289 array : R(read);
5290 match : R(read);
5291 IALU : R(2);
5292 BR : R(2);
5293 MS : R;
5294 %}
5296 // Convert FPU flags into +1,0,-1
5297 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5298 src1 : E(read);
5299 src2 : E(read);
5300 dst : E(write);
5301 FA : R;
5302 MS : R(2);
5303 BR : R(2);
5304 %}
5306 // Compare for p < q, and conditionally add y
5307 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5308 p : E(read);
5309 q : E(read);
5310 y : E(read);
5311 IALU : R(3)
5312 %}
5314 // Perform a compare, then move conditionally in a branch delay slot.
5315 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5316 src2 : E(read);
5317 srcdst : E(read);
5318 IALU : R;
5319 BR : R;
5320 %}
5322 // Define the class for the Nop node
5323 define %{
5324 MachNop = ialu_nop;
5325 %}
5327 %}
5329 //----------INSTRUCTIONS-------------------------------------------------------
5331 //------------Special Stack Slot instructions - no match rules-----------------
5332 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5333 // No match rule to avoid chain rule match.
5334 effect(DEF dst, USE src);
5335 ins_cost(MEMORY_REF_COST);
5336 size(4);
5337 format %{ "LDF $src,$dst\t! stkI to regF" %}
5338 opcode(Assembler::ldf_op3);
5339 ins_encode(simple_form3_mem_reg(src, dst));
5340 ins_pipe(floadF_stk);
5341 %}
5343 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5344 // No match rule to avoid chain rule match.
5345 effect(DEF dst, USE src);
5346 ins_cost(MEMORY_REF_COST);
5347 size(4);
5348 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5349 opcode(Assembler::lddf_op3);
5350 ins_encode(simple_form3_mem_reg(src, dst));
5351 ins_pipe(floadD_stk);
5352 %}
5354 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5355 // No match rule to avoid chain rule match.
5356 effect(DEF dst, USE src);
5357 ins_cost(MEMORY_REF_COST);
5358 size(4);
5359 format %{ "STF $src,$dst\t! regF to stkI" %}
5360 opcode(Assembler::stf_op3);
5361 ins_encode(simple_form3_mem_reg(dst, src));
5362 ins_pipe(fstoreF_stk_reg);
5363 %}
5365 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5366 // No match rule to avoid chain rule match.
5367 effect(DEF dst, USE src);
5368 ins_cost(MEMORY_REF_COST);
5369 size(4);
5370 format %{ "STDF $src,$dst\t! regD to stkL" %}
5371 opcode(Assembler::stdf_op3);
5372 ins_encode(simple_form3_mem_reg(dst, src));
5373 ins_pipe(fstoreD_stk_reg);
5374 %}
5376 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5377 effect(DEF dst, USE src);
5378 ins_cost(MEMORY_REF_COST*2);
5379 size(8);
5380 format %{ "STW $src,$dst.hi\t! long\n\t"
5381 "STW R_G0,$dst.lo" %}
5382 opcode(Assembler::stw_op3);
5383 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5384 ins_pipe(lstoreI_stk_reg);
5385 %}
5387 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5388 // No match rule to avoid chain rule match.
5389 effect(DEF dst, USE src);
5390 ins_cost(MEMORY_REF_COST);
5391 size(4);
5392 format %{ "STX $src,$dst\t! regL to stkD" %}
5393 opcode(Assembler::stx_op3);
5394 ins_encode(simple_form3_mem_reg( dst, src ) );
5395 ins_pipe(istore_stk_reg);
5396 %}
5398 //---------- Chain stack slots between similar types --------
5400 // Load integer from stack slot
5401 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5402 match(Set dst src);
5403 ins_cost(MEMORY_REF_COST);
5405 size(4);
5406 format %{ "LDUW $src,$dst\t!stk" %}
5407 opcode(Assembler::lduw_op3);
5408 ins_encode(simple_form3_mem_reg( src, dst ) );
5409 ins_pipe(iload_mem);
5410 %}
5412 // Store integer to stack slot
5413 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5414 match(Set dst src);
5415 ins_cost(MEMORY_REF_COST);
5417 size(4);
5418 format %{ "STW $src,$dst\t!stk" %}
5419 opcode(Assembler::stw_op3);
5420 ins_encode(simple_form3_mem_reg( dst, src ) );
5421 ins_pipe(istore_mem_reg);
5422 %}
5424 // Load long from stack slot
5425 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5426 match(Set dst src);
5428 ins_cost(MEMORY_REF_COST);
5429 size(4);
5430 format %{ "LDX $src,$dst\t! long" %}
5431 opcode(Assembler::ldx_op3);
5432 ins_encode(simple_form3_mem_reg( src, dst ) );
5433 ins_pipe(iload_mem);
5434 %}
5436 // Store long to stack slot
5437 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5438 match(Set dst src);
5440 ins_cost(MEMORY_REF_COST);
5441 size(4);
5442 format %{ "STX $src,$dst\t! long" %}
5443 opcode(Assembler::stx_op3);
5444 ins_encode(simple_form3_mem_reg( dst, src ) );
5445 ins_pipe(istore_mem_reg);
5446 %}
5448 #ifdef _LP64
5449 // Load pointer from stack slot, 64-bit encoding
5450 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5451 match(Set dst src);
5452 ins_cost(MEMORY_REF_COST);
5453 size(4);
5454 format %{ "LDX $src,$dst\t!ptr" %}
5455 opcode(Assembler::ldx_op3);
5456 ins_encode(simple_form3_mem_reg( src, dst ) );
5457 ins_pipe(iload_mem);
5458 %}
5460 // Store pointer to stack slot
5461 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5462 match(Set dst src);
5463 ins_cost(MEMORY_REF_COST);
5464 size(4);
5465 format %{ "STX $src,$dst\t!ptr" %}
5466 opcode(Assembler::stx_op3);
5467 ins_encode(simple_form3_mem_reg( dst, src ) );
5468 ins_pipe(istore_mem_reg);
5469 %}
5470 #else // _LP64
5471 // Load pointer from stack slot, 32-bit encoding
5472 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5473 match(Set dst src);
5474 ins_cost(MEMORY_REF_COST);
5475 format %{ "LDUW $src,$dst\t!ptr" %}
5476 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5477 ins_encode(simple_form3_mem_reg( src, dst ) );
5478 ins_pipe(iload_mem);
5479 %}
5481 // Store pointer to stack slot
5482 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5483 match(Set dst src);
5484 ins_cost(MEMORY_REF_COST);
5485 format %{ "STW $src,$dst\t!ptr" %}
5486 opcode(Assembler::stw_op3, Assembler::ldst_op);
5487 ins_encode(simple_form3_mem_reg( dst, src ) );
5488 ins_pipe(istore_mem_reg);
5489 %}
5490 #endif // _LP64
5492 //------------Special Nop instructions for bundling - no match rules-----------
5493 // Nop using the A0 functional unit
5494 instruct Nop_A0() %{
5495 ins_cost(0);
5497 format %{ "NOP ! Alu Pipeline" %}
5498 opcode(Assembler::or_op3, Assembler::arith_op);
5499 ins_encode( form2_nop() );
5500 ins_pipe(ialu_nop_A0);
5501 %}
5503 // Nop using the A1 functional unit
5504 instruct Nop_A1( ) %{
5505 ins_cost(0);
5507 format %{ "NOP ! Alu Pipeline" %}
5508 opcode(Assembler::or_op3, Assembler::arith_op);
5509 ins_encode( form2_nop() );
5510 ins_pipe(ialu_nop_A1);
5511 %}
5513 // Nop using the memory functional unit
5514 instruct Nop_MS( ) %{
5515 ins_cost(0);
5517 format %{ "NOP ! Memory Pipeline" %}
5518 ins_encode( emit_mem_nop );
5519 ins_pipe(mem_nop);
5520 %}
5522 // Nop using the floating add functional unit
5523 instruct Nop_FA( ) %{
5524 ins_cost(0);
5526 format %{ "NOP ! Floating Add Pipeline" %}
5527 ins_encode( emit_fadd_nop );
5528 ins_pipe(fadd_nop);
5529 %}
5531 // Nop using the branch functional unit
5532 instruct Nop_BR( ) %{
5533 ins_cost(0);
5535 format %{ "NOP ! Branch Pipeline" %}
5536 ins_encode( emit_br_nop );
5537 ins_pipe(br_nop);
5538 %}
5540 //----------Load/Store/Move Instructions---------------------------------------
5541 //----------Load Instructions--------------------------------------------------
5542 // Load Byte (8bit signed)
5543 instruct loadB(iRegI dst, memory mem) %{
5544 match(Set dst (LoadB mem));
5545 ins_cost(MEMORY_REF_COST);
5547 size(4);
5548 format %{ "LDSB $mem,$dst\t! byte" %}
5549 ins_encode %{
5550 __ ldsb($mem$$Address, $dst$$Register);
5551 %}
5552 ins_pipe(iload_mask_mem);
5553 %}
5555 // Load Byte (8bit signed) into a Long Register
5556 instruct loadB2L(iRegL dst, memory mem) %{
5557 match(Set dst (ConvI2L (LoadB mem)));
5558 ins_cost(MEMORY_REF_COST);
5560 size(4);
5561 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5562 ins_encode %{
5563 __ ldsb($mem$$Address, $dst$$Register);
5564 %}
5565 ins_pipe(iload_mask_mem);
5566 %}
5568 // Load Unsigned Byte (8bit UNsigned) into an int reg
5569 instruct loadUB(iRegI dst, memory mem) %{
5570 match(Set dst (LoadUB mem));
5571 ins_cost(MEMORY_REF_COST);
5573 size(4);
5574 format %{ "LDUB $mem,$dst\t! ubyte" %}
5575 ins_encode %{
5576 __ ldub($mem$$Address, $dst$$Register);
5577 %}
5578 ins_pipe(iload_mem);
5579 %}
5581 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5582 instruct loadUB2L(iRegL dst, memory mem) %{
5583 match(Set dst (ConvI2L (LoadUB mem)));
5584 ins_cost(MEMORY_REF_COST);
5586 size(4);
5587 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5588 ins_encode %{
5589 __ ldub($mem$$Address, $dst$$Register);
5590 %}
5591 ins_pipe(iload_mem);
5592 %}
5594 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5595 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5596 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5597 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5599 size(2*4);
5600 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5601 "AND $dst,$mask,$dst" %}
5602 ins_encode %{
5603 __ ldub($mem$$Address, $dst$$Register);
5604 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5605 %}
5606 ins_pipe(iload_mem);
5607 %}
5609 // Load Short (16bit signed)
5610 instruct loadS(iRegI dst, memory mem) %{
5611 match(Set dst (LoadS mem));
5612 ins_cost(MEMORY_REF_COST);
5614 size(4);
5615 format %{ "LDSH $mem,$dst\t! short" %}
5616 ins_encode %{
5617 __ ldsh($mem$$Address, $dst$$Register);
5618 %}
5619 ins_pipe(iload_mask_mem);
5620 %}
5622 // Load Short (16 bit signed) to Byte (8 bit signed)
5623 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5624 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5625 ins_cost(MEMORY_REF_COST);
5627 size(4);
5629 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5630 ins_encode %{
5631 __ ldsb($mem$$Address, $dst$$Register, 1);
5632 %}
5633 ins_pipe(iload_mask_mem);
5634 %}
5636 // Load Short (16bit signed) into a Long Register
5637 instruct loadS2L(iRegL dst, memory mem) %{
5638 match(Set dst (ConvI2L (LoadS mem)));
5639 ins_cost(MEMORY_REF_COST);
5641 size(4);
5642 format %{ "LDSH $mem,$dst\t! short -> long" %}
5643 ins_encode %{
5644 __ ldsh($mem$$Address, $dst$$Register);
5645 %}
5646 ins_pipe(iload_mask_mem);
5647 %}
5649 // Load Unsigned Short/Char (16bit UNsigned)
5650 instruct loadUS(iRegI dst, memory mem) %{
5651 match(Set dst (LoadUS mem));
5652 ins_cost(MEMORY_REF_COST);
5654 size(4);
5655 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5656 ins_encode %{
5657 __ lduh($mem$$Address, $dst$$Register);
5658 %}
5659 ins_pipe(iload_mem);
5660 %}
5662 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5663 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5664 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5665 ins_cost(MEMORY_REF_COST);
5667 size(4);
5668 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5669 ins_encode %{
5670 __ ldsb($mem$$Address, $dst$$Register, 1);
5671 %}
5672 ins_pipe(iload_mask_mem);
5673 %}
5675 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5676 instruct loadUS2L(iRegL dst, memory mem) %{
5677 match(Set dst (ConvI2L (LoadUS mem)));
5678 ins_cost(MEMORY_REF_COST);
5680 size(4);
5681 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5682 ins_encode %{
5683 __ lduh($mem$$Address, $dst$$Register);
5684 %}
5685 ins_pipe(iload_mem);
5686 %}
5688 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5689 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5690 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5691 ins_cost(MEMORY_REF_COST);
5693 size(4);
5694 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5695 ins_encode %{
5696 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5697 %}
5698 ins_pipe(iload_mem);
5699 %}
5701 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5702 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5703 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5704 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5706 size(2*4);
5707 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5708 "AND $dst,$mask,$dst" %}
5709 ins_encode %{
5710 Register Rdst = $dst$$Register;
5711 __ lduh($mem$$Address, Rdst);
5712 __ and3(Rdst, $mask$$constant, Rdst);
5713 %}
5714 ins_pipe(iload_mem);
5715 %}
5717 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5718 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5719 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5720 effect(TEMP dst, TEMP tmp);
5721 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5723 size((3+1)*4); // set may use two instructions.
5724 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5725 "SET $mask,$tmp\n\t"
5726 "AND $dst,$tmp,$dst" %}
5727 ins_encode %{
5728 Register Rdst = $dst$$Register;
5729 Register Rtmp = $tmp$$Register;
5730 __ lduh($mem$$Address, Rdst);
5731 __ set($mask$$constant, Rtmp);
5732 __ and3(Rdst, Rtmp, Rdst);
5733 %}
5734 ins_pipe(iload_mem);
5735 %}
5737 // Load Integer
5738 instruct loadI(iRegI dst, memory mem) %{
5739 match(Set dst (LoadI mem));
5740 ins_cost(MEMORY_REF_COST);
5742 size(4);
5743 format %{ "LDUW $mem,$dst\t! int" %}
5744 ins_encode %{
5745 __ lduw($mem$$Address, $dst$$Register);
5746 %}
5747 ins_pipe(iload_mem);
5748 %}
5750 // Load Integer to Byte (8 bit signed)
5751 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5752 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5753 ins_cost(MEMORY_REF_COST);
5755 size(4);
5757 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5758 ins_encode %{
5759 __ ldsb($mem$$Address, $dst$$Register, 3);
5760 %}
5761 ins_pipe(iload_mask_mem);
5762 %}
5764 // Load Integer to Unsigned Byte (8 bit UNsigned)
5765 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5766 match(Set dst (AndI (LoadI mem) mask));
5767 ins_cost(MEMORY_REF_COST);
5769 size(4);
5771 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5772 ins_encode %{
5773 __ ldub($mem$$Address, $dst$$Register, 3);
5774 %}
5775 ins_pipe(iload_mask_mem);
5776 %}
5778 // Load Integer to Short (16 bit signed)
5779 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5780 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5781 ins_cost(MEMORY_REF_COST);
5783 size(4);
5785 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5786 ins_encode %{
5787 __ ldsh($mem$$Address, $dst$$Register, 2);
5788 %}
5789 ins_pipe(iload_mask_mem);
5790 %}
5792 // Load Integer to Unsigned Short (16 bit UNsigned)
5793 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5794 match(Set dst (AndI (LoadI mem) mask));
5795 ins_cost(MEMORY_REF_COST);
5797 size(4);
5799 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5800 ins_encode %{
5801 __ lduh($mem$$Address, $dst$$Register, 2);
5802 %}
5803 ins_pipe(iload_mask_mem);
5804 %}
5806 // Load Integer into a Long Register
5807 instruct loadI2L(iRegL dst, memory mem) %{
5808 match(Set dst (ConvI2L (LoadI mem)));
5809 ins_cost(MEMORY_REF_COST);
5811 size(4);
5812 format %{ "LDSW $mem,$dst\t! int -> long" %}
5813 ins_encode %{
5814 __ ldsw($mem$$Address, $dst$$Register);
5815 %}
5816 ins_pipe(iload_mask_mem);
5817 %}
5819 // Load Integer with mask 0xFF into a Long Register
5820 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5821 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5822 ins_cost(MEMORY_REF_COST);
5824 size(4);
5825 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5826 ins_encode %{
5827 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5828 %}
5829 ins_pipe(iload_mem);
5830 %}
5832 // Load Integer with mask 0xFFFF into a Long Register
5833 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5834 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5835 ins_cost(MEMORY_REF_COST);
5837 size(4);
5838 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5839 ins_encode %{
5840 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5841 %}
5842 ins_pipe(iload_mem);
5843 %}
5845 // Load Integer with a 13-bit mask into a Long Register
5846 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5847 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5848 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5850 size(2*4);
5851 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5852 "AND $dst,$mask,$dst" %}
5853 ins_encode %{
5854 Register Rdst = $dst$$Register;
5855 __ lduw($mem$$Address, Rdst);
5856 __ and3(Rdst, $mask$$constant, Rdst);
5857 %}
5858 ins_pipe(iload_mem);
5859 %}
5861 // Load Integer with a 32-bit mask into a Long Register
5862 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5863 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5864 effect(TEMP dst, TEMP tmp);
5865 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5867 size((3+1)*4); // set may use two instructions.
5868 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5869 "SET $mask,$tmp\n\t"
5870 "AND $dst,$tmp,$dst" %}
5871 ins_encode %{
5872 Register Rdst = $dst$$Register;
5873 Register Rtmp = $tmp$$Register;
5874 __ lduw($mem$$Address, Rdst);
5875 __ set($mask$$constant, Rtmp);
5876 __ and3(Rdst, Rtmp, Rdst);
5877 %}
5878 ins_pipe(iload_mem);
5879 %}
5881 // Load Unsigned Integer into a Long Register
5882 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5883 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5884 ins_cost(MEMORY_REF_COST);
5886 size(4);
5887 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5888 ins_encode %{
5889 __ lduw($mem$$Address, $dst$$Register);
5890 %}
5891 ins_pipe(iload_mem);
5892 %}
5894 // Load Long - aligned
5895 instruct loadL(iRegL dst, memory mem ) %{
5896 match(Set dst (LoadL mem));
5897 ins_cost(MEMORY_REF_COST);
5899 size(4);
5900 format %{ "LDX $mem,$dst\t! long" %}
5901 ins_encode %{
5902 __ ldx($mem$$Address, $dst$$Register);
5903 %}
5904 ins_pipe(iload_mem);
5905 %}
5907 // Load Long - UNaligned
5908 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5909 match(Set dst (LoadL_unaligned mem));
5910 effect(KILL tmp);
5911 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5912 size(16);
5913 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5914 "\tLDUW $mem ,$dst\n"
5915 "\tSLLX #32, $dst, $dst\n"
5916 "\tOR $dst, R_O7, $dst" %}
5917 opcode(Assembler::lduw_op3);
5918 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5919 ins_pipe(iload_mem);
5920 %}
5922 // Load Range
5923 instruct loadRange(iRegI dst, memory mem) %{
5924 match(Set dst (LoadRange mem));
5925 ins_cost(MEMORY_REF_COST);
5927 size(4);
5928 format %{ "LDUW $mem,$dst\t! range" %}
5929 opcode(Assembler::lduw_op3);
5930 ins_encode(simple_form3_mem_reg( mem, dst ) );
5931 ins_pipe(iload_mem);
5932 %}
5934 // Load Integer into %f register (for fitos/fitod)
5935 instruct loadI_freg(regF dst, memory mem) %{
5936 match(Set dst (LoadI mem));
5937 ins_cost(MEMORY_REF_COST);
5938 size(4);
5940 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5941 opcode(Assembler::ldf_op3);
5942 ins_encode(simple_form3_mem_reg( mem, dst ) );
5943 ins_pipe(floadF_mem);
5944 %}
5946 // Load Pointer
5947 instruct loadP(iRegP dst, memory mem) %{
5948 match(Set dst (LoadP mem));
5949 ins_cost(MEMORY_REF_COST);
5950 size(4);
5952 #ifndef _LP64
5953 format %{ "LDUW $mem,$dst\t! ptr" %}
5954 ins_encode %{
5955 __ lduw($mem$$Address, $dst$$Register);
5956 %}
5957 #else
5958 format %{ "LDX $mem,$dst\t! ptr" %}
5959 ins_encode %{
5960 __ ldx($mem$$Address, $dst$$Register);
5961 %}
5962 #endif
5963 ins_pipe(iload_mem);
5964 %}
5966 // Load Compressed Pointer
5967 instruct loadN(iRegN dst, memory mem) %{
5968 match(Set dst (LoadN mem));
5969 ins_cost(MEMORY_REF_COST);
5970 size(4);
5972 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5973 ins_encode %{
5974 __ lduw($mem$$Address, $dst$$Register);
5975 %}
5976 ins_pipe(iload_mem);
5977 %}
5979 // Load Klass Pointer
5980 instruct loadKlass(iRegP dst, memory mem) %{
5981 match(Set dst (LoadKlass mem));
5982 ins_cost(MEMORY_REF_COST);
5983 size(4);
5985 #ifndef _LP64
5986 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5987 ins_encode %{
5988 __ lduw($mem$$Address, $dst$$Register);
5989 %}
5990 #else
5991 format %{ "LDX $mem,$dst\t! klass ptr" %}
5992 ins_encode %{
5993 __ ldx($mem$$Address, $dst$$Register);
5994 %}
5995 #endif
5996 ins_pipe(iload_mem);
5997 %}
5999 // Load narrow Klass Pointer
6000 instruct loadNKlass(iRegN dst, memory mem) %{
6001 match(Set dst (LoadNKlass mem));
6002 ins_cost(MEMORY_REF_COST);
6003 size(4);
6005 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6006 ins_encode %{
6007 __ lduw($mem$$Address, $dst$$Register);
6008 %}
6009 ins_pipe(iload_mem);
6010 %}
6012 // Load Double
6013 instruct loadD(regD dst, memory mem) %{
6014 match(Set dst (LoadD mem));
6015 ins_cost(MEMORY_REF_COST);
6017 size(4);
6018 format %{ "LDDF $mem,$dst" %}
6019 opcode(Assembler::lddf_op3);
6020 ins_encode(simple_form3_mem_reg( mem, dst ) );
6021 ins_pipe(floadD_mem);
6022 %}
6024 // Load Double - UNaligned
6025 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6026 match(Set dst (LoadD_unaligned mem));
6027 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6028 size(8);
6029 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6030 "\tLDF $mem+4,$dst.lo\t!" %}
6031 opcode(Assembler::ldf_op3);
6032 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6033 ins_pipe(iload_mem);
6034 %}
6036 // Load Float
6037 instruct loadF(regF dst, memory mem) %{
6038 match(Set dst (LoadF mem));
6039 ins_cost(MEMORY_REF_COST);
6041 size(4);
6042 format %{ "LDF $mem,$dst" %}
6043 opcode(Assembler::ldf_op3);
6044 ins_encode(simple_form3_mem_reg( mem, dst ) );
6045 ins_pipe(floadF_mem);
6046 %}
6048 // Load Constant
6049 instruct loadConI( iRegI dst, immI src ) %{
6050 match(Set dst src);
6051 ins_cost(DEFAULT_COST * 3/2);
6052 format %{ "SET $src,$dst" %}
6053 ins_encode( Set32(src, dst) );
6054 ins_pipe(ialu_hi_lo_reg);
6055 %}
6057 instruct loadConI13( iRegI dst, immI13 src ) %{
6058 match(Set dst src);
6060 size(4);
6061 format %{ "MOV $src,$dst" %}
6062 ins_encode( Set13( src, dst ) );
6063 ins_pipe(ialu_imm);
6064 %}
6066 #ifndef _LP64
6067 instruct loadConP(iRegP dst, immP con) %{
6068 match(Set dst con);
6069 ins_cost(DEFAULT_COST * 3/2);
6070 format %{ "SET $con,$dst\t!ptr" %}
6071 ins_encode %{
6072 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6073 intptr_t val = $con$$constant;
6074 if (constant_reloc == relocInfo::oop_type) {
6075 __ set_oop_constant((jobject) val, $dst$$Register);
6076 } else if (constant_reloc == relocInfo::metadata_type) {
6077 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6078 } else { // non-oop pointers, e.g. card mark base, heap top
6079 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6080 __ set(val, $dst$$Register);
6081 }
6082 %}
6083 ins_pipe(loadConP);
6084 %}
6085 #else
6086 instruct loadConP_set(iRegP dst, immP_set con) %{
6087 match(Set dst con);
6088 ins_cost(DEFAULT_COST * 3/2);
6089 format %{ "SET $con,$dst\t! ptr" %}
6090 ins_encode %{
6091 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6092 intptr_t val = $con$$constant;
6093 if (constant_reloc == relocInfo::oop_type) {
6094 __ set_oop_constant((jobject) val, $dst$$Register);
6095 } else if (constant_reloc == relocInfo::metadata_type) {
6096 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6097 } else { // non-oop pointers, e.g. card mark base, heap top
6098 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6099 __ set(val, $dst$$Register);
6100 }
6101 %}
6102 ins_pipe(loadConP);
6103 %}
6105 instruct loadConP_load(iRegP dst, immP_load con) %{
6106 match(Set dst con);
6107 ins_cost(MEMORY_REF_COST);
6108 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6109 ins_encode %{
6110 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6111 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6112 %}
6113 ins_pipe(loadConP);
6114 %}
6116 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6117 match(Set dst con);
6118 ins_cost(DEFAULT_COST * 3/2);
6119 format %{ "SET $con,$dst\t! non-oop ptr" %}
6120 ins_encode %{
6121 __ set($con$$constant, $dst$$Register);
6122 %}
6123 ins_pipe(loadConP);
6124 %}
6125 #endif // _LP64
6127 instruct loadConP0(iRegP dst, immP0 src) %{
6128 match(Set dst src);
6130 size(4);
6131 format %{ "CLR $dst\t!ptr" %}
6132 ins_encode %{
6133 __ clr($dst$$Register);
6134 %}
6135 ins_pipe(ialu_imm);
6136 %}
6138 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6139 match(Set dst src);
6140 ins_cost(DEFAULT_COST);
6141 format %{ "SET $src,$dst\t!ptr" %}
6142 ins_encode %{
6143 AddressLiteral polling_page(os::get_polling_page());
6144 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6145 %}
6146 ins_pipe(loadConP_poll);
6147 %}
6149 instruct loadConN0(iRegN dst, immN0 src) %{
6150 match(Set dst src);
6152 size(4);
6153 format %{ "CLR $dst\t! compressed NULL ptr" %}
6154 ins_encode %{
6155 __ clr($dst$$Register);
6156 %}
6157 ins_pipe(ialu_imm);
6158 %}
6160 instruct loadConN(iRegN dst, immN src) %{
6161 match(Set dst src);
6162 ins_cost(DEFAULT_COST * 3/2);
6163 format %{ "SET $src,$dst\t! compressed ptr" %}
6164 ins_encode %{
6165 Register dst = $dst$$Register;
6166 __ set_narrow_oop((jobject)$src$$constant, dst);
6167 %}
6168 ins_pipe(ialu_hi_lo_reg);
6169 %}
6171 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6172 match(Set dst src);
6173 ins_cost(DEFAULT_COST * 3/2);
6174 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6175 ins_encode %{
6176 Register dst = $dst$$Register;
6177 __ set_narrow_klass((Klass*)$src$$constant, dst);
6178 %}
6179 ins_pipe(ialu_hi_lo_reg);
6180 %}
6182 // Materialize long value (predicated by immL_cheap).
6183 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6184 match(Set dst con);
6185 effect(KILL tmp);
6186 ins_cost(DEFAULT_COST * 3);
6187 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6188 ins_encode %{
6189 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6190 %}
6191 ins_pipe(loadConL);
6192 %}
6194 // Load long value from constant table (predicated by immL_expensive).
6195 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6196 match(Set dst con);
6197 ins_cost(MEMORY_REF_COST);
6198 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6199 ins_encode %{
6200 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6201 __ ldx($constanttablebase, con_offset, $dst$$Register);
6202 %}
6203 ins_pipe(loadConL);
6204 %}
6206 instruct loadConL0( iRegL dst, immL0 src ) %{
6207 match(Set dst src);
6208 ins_cost(DEFAULT_COST);
6209 size(4);
6210 format %{ "CLR $dst\t! long" %}
6211 ins_encode( Set13( src, dst ) );
6212 ins_pipe(ialu_imm);
6213 %}
6215 instruct loadConL13( iRegL dst, immL13 src ) %{
6216 match(Set dst src);
6217 ins_cost(DEFAULT_COST * 2);
6219 size(4);
6220 format %{ "MOV $src,$dst\t! long" %}
6221 ins_encode( Set13( src, dst ) );
6222 ins_pipe(ialu_imm);
6223 %}
6225 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6226 match(Set dst con);
6227 effect(KILL tmp);
6228 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6229 ins_encode %{
6230 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6231 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6232 %}
6233 ins_pipe(loadConFD);
6234 %}
6236 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6237 match(Set dst con);
6238 effect(KILL tmp);
6239 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6240 ins_encode %{
6241 // XXX This is a quick fix for 6833573.
6242 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6243 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6244 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6245 %}
6246 ins_pipe(loadConFD);
6247 %}
6249 // Prefetch instructions.
6250 // Must be safe to execute with invalid address (cannot fault).
6252 instruct prefetchr( memory mem ) %{
6253 match( PrefetchRead mem );
6254 ins_cost(MEMORY_REF_COST);
6255 size(4);
6257 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6258 opcode(Assembler::prefetch_op3);
6259 ins_encode( form3_mem_prefetch_read( mem ) );
6260 ins_pipe(iload_mem);
6261 %}
6263 instruct prefetchw( memory mem ) %{
6264 match( PrefetchWrite mem );
6265 ins_cost(MEMORY_REF_COST);
6266 size(4);
6268 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6269 opcode(Assembler::prefetch_op3);
6270 ins_encode( form3_mem_prefetch_write( mem ) );
6271 ins_pipe(iload_mem);
6272 %}
6274 // Prefetch instructions for allocation.
6276 instruct prefetchAlloc( memory mem ) %{
6277 predicate(AllocatePrefetchInstr == 0);
6278 match( PrefetchAllocation mem );
6279 ins_cost(MEMORY_REF_COST);
6280 size(4);
6282 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6283 opcode(Assembler::prefetch_op3);
6284 ins_encode( form3_mem_prefetch_write( mem ) );
6285 ins_pipe(iload_mem);
6286 %}
6288 // Use BIS instruction to prefetch for allocation.
6289 // Could fault, need space at the end of TLAB.
6290 instruct prefetchAlloc_bis( iRegP dst ) %{
6291 predicate(AllocatePrefetchInstr == 1);
6292 match( PrefetchAllocation dst );
6293 ins_cost(MEMORY_REF_COST);
6294 size(4);
6296 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6297 ins_encode %{
6298 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6299 %}
6300 ins_pipe(istore_mem_reg);
6301 %}
6303 // Next code is used for finding next cache line address to prefetch.
6304 #ifndef _LP64
6305 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6306 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6307 ins_cost(DEFAULT_COST);
6308 size(4);
6310 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6311 ins_encode %{
6312 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6313 %}
6314 ins_pipe(ialu_reg_imm);
6315 %}
6316 #else
6317 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6318 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6319 ins_cost(DEFAULT_COST);
6320 size(4);
6322 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6323 ins_encode %{
6324 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6325 %}
6326 ins_pipe(ialu_reg_imm);
6327 %}
6328 #endif
6330 //----------Store Instructions-------------------------------------------------
6331 // Store Byte
6332 instruct storeB(memory mem, iRegI src) %{
6333 match(Set mem (StoreB mem src));
6334 ins_cost(MEMORY_REF_COST);
6336 size(4);
6337 format %{ "STB $src,$mem\t! byte" %}
6338 opcode(Assembler::stb_op3);
6339 ins_encode(simple_form3_mem_reg( mem, src ) );
6340 ins_pipe(istore_mem_reg);
6341 %}
6343 instruct storeB0(memory mem, immI0 src) %{
6344 match(Set mem (StoreB mem src));
6345 ins_cost(MEMORY_REF_COST);
6347 size(4);
6348 format %{ "STB $src,$mem\t! byte" %}
6349 opcode(Assembler::stb_op3);
6350 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6351 ins_pipe(istore_mem_zero);
6352 %}
6354 instruct storeCM0(memory mem, immI0 src) %{
6355 match(Set mem (StoreCM mem src));
6356 ins_cost(MEMORY_REF_COST);
6358 size(4);
6359 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6360 opcode(Assembler::stb_op3);
6361 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6362 ins_pipe(istore_mem_zero);
6363 %}
6365 // Store Char/Short
6366 instruct storeC(memory mem, iRegI src) %{
6367 match(Set mem (StoreC mem src));
6368 ins_cost(MEMORY_REF_COST);
6370 size(4);
6371 format %{ "STH $src,$mem\t! short" %}
6372 opcode(Assembler::sth_op3);
6373 ins_encode(simple_form3_mem_reg( mem, src ) );
6374 ins_pipe(istore_mem_reg);
6375 %}
6377 instruct storeC0(memory mem, immI0 src) %{
6378 match(Set mem (StoreC mem src));
6379 ins_cost(MEMORY_REF_COST);
6381 size(4);
6382 format %{ "STH $src,$mem\t! short" %}
6383 opcode(Assembler::sth_op3);
6384 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6385 ins_pipe(istore_mem_zero);
6386 %}
6388 // Store Integer
6389 instruct storeI(memory mem, iRegI src) %{
6390 match(Set mem (StoreI mem src));
6391 ins_cost(MEMORY_REF_COST);
6393 size(4);
6394 format %{ "STW $src,$mem" %}
6395 opcode(Assembler::stw_op3);
6396 ins_encode(simple_form3_mem_reg( mem, src ) );
6397 ins_pipe(istore_mem_reg);
6398 %}
6400 // Store Long
6401 instruct storeL(memory mem, iRegL src) %{
6402 match(Set mem (StoreL mem src));
6403 ins_cost(MEMORY_REF_COST);
6404 size(4);
6405 format %{ "STX $src,$mem\t! long" %}
6406 opcode(Assembler::stx_op3);
6407 ins_encode(simple_form3_mem_reg( mem, src ) );
6408 ins_pipe(istore_mem_reg);
6409 %}
6411 instruct storeI0(memory mem, immI0 src) %{
6412 match(Set mem (StoreI mem src));
6413 ins_cost(MEMORY_REF_COST);
6415 size(4);
6416 format %{ "STW $src,$mem" %}
6417 opcode(Assembler::stw_op3);
6418 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6419 ins_pipe(istore_mem_zero);
6420 %}
6422 instruct storeL0(memory mem, immL0 src) %{
6423 match(Set mem (StoreL mem src));
6424 ins_cost(MEMORY_REF_COST);
6426 size(4);
6427 format %{ "STX $src,$mem" %}
6428 opcode(Assembler::stx_op3);
6429 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6430 ins_pipe(istore_mem_zero);
6431 %}
6433 // Store Integer from float register (used after fstoi)
6434 instruct storeI_Freg(memory mem, regF src) %{
6435 match(Set mem (StoreI mem src));
6436 ins_cost(MEMORY_REF_COST);
6438 size(4);
6439 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6440 opcode(Assembler::stf_op3);
6441 ins_encode(simple_form3_mem_reg( mem, src ) );
6442 ins_pipe(fstoreF_mem_reg);
6443 %}
6445 // Store Pointer
6446 instruct storeP(memory dst, sp_ptr_RegP src) %{
6447 match(Set dst (StoreP dst src));
6448 ins_cost(MEMORY_REF_COST);
6449 size(4);
6451 #ifndef _LP64
6452 format %{ "STW $src,$dst\t! ptr" %}
6453 opcode(Assembler::stw_op3, 0, REGP_OP);
6454 #else
6455 format %{ "STX $src,$dst\t! ptr" %}
6456 opcode(Assembler::stx_op3, 0, REGP_OP);
6457 #endif
6458 ins_encode( form3_mem_reg( dst, src ) );
6459 ins_pipe(istore_mem_spORreg);
6460 %}
6462 instruct storeP0(memory dst, immP0 src) %{
6463 match(Set dst (StoreP dst src));
6464 ins_cost(MEMORY_REF_COST);
6465 size(4);
6467 #ifndef _LP64
6468 format %{ "STW $src,$dst\t! ptr" %}
6469 opcode(Assembler::stw_op3, 0, REGP_OP);
6470 #else
6471 format %{ "STX $src,$dst\t! ptr" %}
6472 opcode(Assembler::stx_op3, 0, REGP_OP);
6473 #endif
6474 ins_encode( form3_mem_reg( dst, R_G0 ) );
6475 ins_pipe(istore_mem_zero);
6476 %}
6478 // Store Compressed Pointer
6479 instruct storeN(memory dst, iRegN src) %{
6480 match(Set dst (StoreN dst src));
6481 ins_cost(MEMORY_REF_COST);
6482 size(4);
6484 format %{ "STW $src,$dst\t! compressed ptr" %}
6485 ins_encode %{
6486 Register base = as_Register($dst$$base);
6487 Register index = as_Register($dst$$index);
6488 Register src = $src$$Register;
6489 if (index != G0) {
6490 __ stw(src, base, index);
6491 } else {
6492 __ stw(src, base, $dst$$disp);
6493 }
6494 %}
6495 ins_pipe(istore_mem_spORreg);
6496 %}
6498 instruct storeNKlass(memory dst, iRegN src) %{
6499 match(Set dst (StoreNKlass dst src));
6500 ins_cost(MEMORY_REF_COST);
6501 size(4);
6503 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6504 ins_encode %{
6505 Register base = as_Register($dst$$base);
6506 Register index = as_Register($dst$$index);
6507 Register src = $src$$Register;
6508 if (index != G0) {
6509 __ stw(src, base, index);
6510 } else {
6511 __ stw(src, base, $dst$$disp);
6512 }
6513 %}
6514 ins_pipe(istore_mem_spORreg);
6515 %}
6517 instruct storeN0(memory dst, immN0 src) %{
6518 match(Set dst (StoreN dst src));
6519 ins_cost(MEMORY_REF_COST);
6520 size(4);
6522 format %{ "STW $src,$dst\t! compressed ptr" %}
6523 ins_encode %{
6524 Register base = as_Register($dst$$base);
6525 Register index = as_Register($dst$$index);
6526 if (index != G0) {
6527 __ stw(0, base, index);
6528 } else {
6529 __ stw(0, base, $dst$$disp);
6530 }
6531 %}
6532 ins_pipe(istore_mem_zero);
6533 %}
6535 // Store Double
6536 instruct storeD( memory mem, regD src) %{
6537 match(Set mem (StoreD mem src));
6538 ins_cost(MEMORY_REF_COST);
6540 size(4);
6541 format %{ "STDF $src,$mem" %}
6542 opcode(Assembler::stdf_op3);
6543 ins_encode(simple_form3_mem_reg( mem, src ) );
6544 ins_pipe(fstoreD_mem_reg);
6545 %}
6547 instruct storeD0( memory mem, immD0 src) %{
6548 match(Set mem (StoreD mem src));
6549 ins_cost(MEMORY_REF_COST);
6551 size(4);
6552 format %{ "STX $src,$mem" %}
6553 opcode(Assembler::stx_op3);
6554 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6555 ins_pipe(fstoreD_mem_zero);
6556 %}
6558 // Store Float
6559 instruct storeF( memory mem, regF src) %{
6560 match(Set mem (StoreF mem src));
6561 ins_cost(MEMORY_REF_COST);
6563 size(4);
6564 format %{ "STF $src,$mem" %}
6565 opcode(Assembler::stf_op3);
6566 ins_encode(simple_form3_mem_reg( mem, src ) );
6567 ins_pipe(fstoreF_mem_reg);
6568 %}
6570 instruct storeF0( memory mem, immF0 src) %{
6571 match(Set mem (StoreF mem src));
6572 ins_cost(MEMORY_REF_COST);
6574 size(4);
6575 format %{ "STW $src,$mem\t! storeF0" %}
6576 opcode(Assembler::stw_op3);
6577 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6578 ins_pipe(fstoreF_mem_zero);
6579 %}
6581 // Convert oop pointer into compressed form
6582 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6583 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6584 match(Set dst (EncodeP src));
6585 format %{ "encode_heap_oop $src, $dst" %}
6586 ins_encode %{
6587 __ encode_heap_oop($src$$Register, $dst$$Register);
6588 %}
6589 ins_pipe(ialu_reg);
6590 %}
6592 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6593 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6594 match(Set dst (EncodeP src));
6595 format %{ "encode_heap_oop_not_null $src, $dst" %}
6596 ins_encode %{
6597 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6598 %}
6599 ins_pipe(ialu_reg);
6600 %}
6602 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6603 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6604 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6605 match(Set dst (DecodeN src));
6606 format %{ "decode_heap_oop $src, $dst" %}
6607 ins_encode %{
6608 __ decode_heap_oop($src$$Register, $dst$$Register);
6609 %}
6610 ins_pipe(ialu_reg);
6611 %}
6613 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6614 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6615 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6616 match(Set dst (DecodeN src));
6617 format %{ "decode_heap_oop_not_null $src, $dst" %}
6618 ins_encode %{
6619 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6620 %}
6621 ins_pipe(ialu_reg);
6622 %}
6624 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6625 match(Set dst (EncodePKlass src));
6626 format %{ "encode_klass_not_null $src, $dst" %}
6627 ins_encode %{
6628 __ encode_klass_not_null($src$$Register, $dst$$Register);
6629 %}
6630 ins_pipe(ialu_reg);
6631 %}
6633 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6634 match(Set dst (DecodeNKlass src));
6635 format %{ "decode_klass_not_null $src, $dst" %}
6636 ins_encode %{
6637 __ decode_klass_not_null($src$$Register, $dst$$Register);
6638 %}
6639 ins_pipe(ialu_reg);
6640 %}
6642 //----------MemBar Instructions-----------------------------------------------
6643 // Memory barrier flavors
6645 instruct membar_acquire() %{
6646 match(MemBarAcquire);
6647 ins_cost(4*MEMORY_REF_COST);
6649 size(0);
6650 format %{ "MEMBAR-acquire" %}
6651 ins_encode( enc_membar_acquire );
6652 ins_pipe(long_memory_op);
6653 %}
6655 instruct membar_acquire_lock() %{
6656 match(MemBarAcquireLock);
6657 ins_cost(0);
6659 size(0);
6660 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6661 ins_encode( );
6662 ins_pipe(empty);
6663 %}
6665 instruct membar_release() %{
6666 match(MemBarRelease);
6667 ins_cost(4*MEMORY_REF_COST);
6669 size(0);
6670 format %{ "MEMBAR-release" %}
6671 ins_encode( enc_membar_release );
6672 ins_pipe(long_memory_op);
6673 %}
6675 instruct membar_release_lock() %{
6676 match(MemBarReleaseLock);
6677 ins_cost(0);
6679 size(0);
6680 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6681 ins_encode( );
6682 ins_pipe(empty);
6683 %}
6685 instruct membar_volatile() %{
6686 match(MemBarVolatile);
6687 ins_cost(4*MEMORY_REF_COST);
6689 size(4);
6690 format %{ "MEMBAR-volatile" %}
6691 ins_encode( enc_membar_volatile );
6692 ins_pipe(long_memory_op);
6693 %}
6695 instruct unnecessary_membar_volatile() %{
6696 match(MemBarVolatile);
6697 predicate(Matcher::post_store_load_barrier(n));
6698 ins_cost(0);
6700 size(0);
6701 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6702 ins_encode( );
6703 ins_pipe(empty);
6704 %}
6706 instruct membar_storestore() %{
6707 match(MemBarStoreStore);
6708 ins_cost(0);
6710 size(0);
6711 format %{ "!MEMBAR-storestore (empty encoding)" %}
6712 ins_encode( );
6713 ins_pipe(empty);
6714 %}
6716 //----------Register Move Instructions-----------------------------------------
6717 instruct roundDouble_nop(regD dst) %{
6718 match(Set dst (RoundDouble dst));
6719 ins_cost(0);
6720 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6721 ins_encode( );
6722 ins_pipe(empty);
6723 %}
6726 instruct roundFloat_nop(regF dst) %{
6727 match(Set dst (RoundFloat dst));
6728 ins_cost(0);
6729 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6730 ins_encode( );
6731 ins_pipe(empty);
6732 %}
6735 // Cast Index to Pointer for unsafe natives
6736 instruct castX2P(iRegX src, iRegP dst) %{
6737 match(Set dst (CastX2P src));
6739 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6740 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6741 ins_pipe(ialu_reg);
6742 %}
6744 // Cast Pointer to Index for unsafe natives
6745 instruct castP2X(iRegP src, iRegX dst) %{
6746 match(Set dst (CastP2X src));
6748 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6749 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6750 ins_pipe(ialu_reg);
6751 %}
6753 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6754 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6755 match(Set stkSlot src); // chain rule
6756 ins_cost(MEMORY_REF_COST);
6757 format %{ "STDF $src,$stkSlot\t!stk" %}
6758 opcode(Assembler::stdf_op3);
6759 ins_encode(simple_form3_mem_reg(stkSlot, src));
6760 ins_pipe(fstoreD_stk_reg);
6761 %}
6763 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6764 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6765 match(Set dst stkSlot); // chain rule
6766 ins_cost(MEMORY_REF_COST);
6767 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6768 opcode(Assembler::lddf_op3);
6769 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6770 ins_pipe(floadD_stk);
6771 %}
6773 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6774 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6775 match(Set stkSlot src); // chain rule
6776 ins_cost(MEMORY_REF_COST);
6777 format %{ "STF $src,$stkSlot\t!stk" %}
6778 opcode(Assembler::stf_op3);
6779 ins_encode(simple_form3_mem_reg(stkSlot, src));
6780 ins_pipe(fstoreF_stk_reg);
6781 %}
6783 //----------Conditional Move---------------------------------------------------
6784 // Conditional move
6785 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6786 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6787 ins_cost(150);
6788 format %{ "MOV$cmp $pcc,$src,$dst" %}
6789 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6790 ins_pipe(ialu_reg);
6791 %}
6793 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6794 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6795 ins_cost(140);
6796 format %{ "MOV$cmp $pcc,$src,$dst" %}
6797 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6798 ins_pipe(ialu_imm);
6799 %}
6801 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6802 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6803 ins_cost(150);
6804 size(4);
6805 format %{ "MOV$cmp $icc,$src,$dst" %}
6806 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6807 ins_pipe(ialu_reg);
6808 %}
6810 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6811 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6812 ins_cost(140);
6813 size(4);
6814 format %{ "MOV$cmp $icc,$src,$dst" %}
6815 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6816 ins_pipe(ialu_imm);
6817 %}
6819 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6820 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6821 ins_cost(150);
6822 size(4);
6823 format %{ "MOV$cmp $icc,$src,$dst" %}
6824 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6825 ins_pipe(ialu_reg);
6826 %}
6828 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6829 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6830 ins_cost(140);
6831 size(4);
6832 format %{ "MOV$cmp $icc,$src,$dst" %}
6833 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6834 ins_pipe(ialu_imm);
6835 %}
6837 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6838 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6839 ins_cost(150);
6840 size(4);
6841 format %{ "MOV$cmp $fcc,$src,$dst" %}
6842 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6843 ins_pipe(ialu_reg);
6844 %}
6846 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6847 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6848 ins_cost(140);
6849 size(4);
6850 format %{ "MOV$cmp $fcc,$src,$dst" %}
6851 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6852 ins_pipe(ialu_imm);
6853 %}
6855 // Conditional move for RegN. Only cmov(reg,reg).
6856 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6857 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6858 ins_cost(150);
6859 format %{ "MOV$cmp $pcc,$src,$dst" %}
6860 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6861 ins_pipe(ialu_reg);
6862 %}
6864 // This instruction also works with CmpN so we don't need cmovNN_reg.
6865 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6866 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6867 ins_cost(150);
6868 size(4);
6869 format %{ "MOV$cmp $icc,$src,$dst" %}
6870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6871 ins_pipe(ialu_reg);
6872 %}
6874 // This instruction also works with CmpN so we don't need cmovNN_reg.
6875 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6876 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6877 ins_cost(150);
6878 size(4);
6879 format %{ "MOV$cmp $icc,$src,$dst" %}
6880 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6881 ins_pipe(ialu_reg);
6882 %}
6884 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6885 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6886 ins_cost(150);
6887 size(4);
6888 format %{ "MOV$cmp $fcc,$src,$dst" %}
6889 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6890 ins_pipe(ialu_reg);
6891 %}
6893 // Conditional move
6894 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6895 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6896 ins_cost(150);
6897 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6898 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6899 ins_pipe(ialu_reg);
6900 %}
6902 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6903 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6904 ins_cost(140);
6905 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6906 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6907 ins_pipe(ialu_imm);
6908 %}
6910 // This instruction also works with CmpN so we don't need cmovPN_reg.
6911 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6912 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6913 ins_cost(150);
6915 size(4);
6916 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6917 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6918 ins_pipe(ialu_reg);
6919 %}
6921 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6922 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6923 ins_cost(150);
6925 size(4);
6926 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6927 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6928 ins_pipe(ialu_reg);
6929 %}
6931 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6932 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6933 ins_cost(140);
6935 size(4);
6936 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6937 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6938 ins_pipe(ialu_imm);
6939 %}
6941 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6942 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6943 ins_cost(140);
6945 size(4);
6946 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6947 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6948 ins_pipe(ialu_imm);
6949 %}
6951 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6952 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6953 ins_cost(150);
6954 size(4);
6955 format %{ "MOV$cmp $fcc,$src,$dst" %}
6956 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6957 ins_pipe(ialu_imm);
6958 %}
6960 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6961 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6962 ins_cost(140);
6963 size(4);
6964 format %{ "MOV$cmp $fcc,$src,$dst" %}
6965 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6966 ins_pipe(ialu_imm);
6967 %}
6969 // Conditional move
6970 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6971 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6972 ins_cost(150);
6973 opcode(0x101);
6974 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6975 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6976 ins_pipe(int_conditional_float_move);
6977 %}
6979 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6980 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6981 ins_cost(150);
6983 size(4);
6984 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6985 opcode(0x101);
6986 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6987 ins_pipe(int_conditional_float_move);
6988 %}
6990 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6991 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6992 ins_cost(150);
6994 size(4);
6995 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6996 opcode(0x101);
6997 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6998 ins_pipe(int_conditional_float_move);
6999 %}
7001 // Conditional move,
7002 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7003 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7004 ins_cost(150);
7005 size(4);
7006 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7007 opcode(0x1);
7008 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7009 ins_pipe(int_conditional_double_move);
7010 %}
7012 // Conditional move
7013 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7014 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7015 ins_cost(150);
7016 size(4);
7017 opcode(0x102);
7018 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7019 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7020 ins_pipe(int_conditional_double_move);
7021 %}
7023 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7024 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7025 ins_cost(150);
7027 size(4);
7028 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7029 opcode(0x102);
7030 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7031 ins_pipe(int_conditional_double_move);
7032 %}
7034 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7035 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7036 ins_cost(150);
7038 size(4);
7039 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7040 opcode(0x102);
7041 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7042 ins_pipe(int_conditional_double_move);
7043 %}
7045 // Conditional move,
7046 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7047 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7048 ins_cost(150);
7049 size(4);
7050 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7051 opcode(0x2);
7052 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7053 ins_pipe(int_conditional_double_move);
7054 %}
7056 // Conditional move
7057 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7058 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7059 ins_cost(150);
7060 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7061 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7062 ins_pipe(ialu_reg);
7063 %}
7065 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7066 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7067 ins_cost(140);
7068 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7069 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7070 ins_pipe(ialu_imm);
7071 %}
7073 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7074 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7075 ins_cost(150);
7077 size(4);
7078 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7079 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7080 ins_pipe(ialu_reg);
7081 %}
7084 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7085 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7086 ins_cost(150);
7088 size(4);
7089 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7090 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7091 ins_pipe(ialu_reg);
7092 %}
7095 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7096 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7097 ins_cost(150);
7099 size(4);
7100 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7101 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7102 ins_pipe(ialu_reg);
7103 %}
7107 //----------OS and Locking Instructions----------------------------------------
7109 // This name is KNOWN by the ADLC and cannot be changed.
7110 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7111 // for this guy.
7112 instruct tlsLoadP(g2RegP dst) %{
7113 match(Set dst (ThreadLocal));
7115 size(0);
7116 ins_cost(0);
7117 format %{ "# TLS is in G2" %}
7118 ins_encode( /*empty encoding*/ );
7119 ins_pipe(ialu_none);
7120 %}
7122 instruct checkCastPP( iRegP dst ) %{
7123 match(Set dst (CheckCastPP dst));
7125 size(0);
7126 format %{ "# checkcastPP of $dst" %}
7127 ins_encode( /*empty encoding*/ );
7128 ins_pipe(empty);
7129 %}
7132 instruct castPP( iRegP dst ) %{
7133 match(Set dst (CastPP dst));
7134 format %{ "# castPP of $dst" %}
7135 ins_encode( /*empty encoding*/ );
7136 ins_pipe(empty);
7137 %}
7139 instruct castII( iRegI dst ) %{
7140 match(Set dst (CastII dst));
7141 format %{ "# castII of $dst" %}
7142 ins_encode( /*empty encoding*/ );
7143 ins_cost(0);
7144 ins_pipe(empty);
7145 %}
7147 //----------Arithmetic Instructions--------------------------------------------
7148 // Addition Instructions
7149 // Register Addition
7150 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7151 match(Set dst (AddI src1 src2));
7153 size(4);
7154 format %{ "ADD $src1,$src2,$dst" %}
7155 ins_encode %{
7156 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7157 %}
7158 ins_pipe(ialu_reg_reg);
7159 %}
7161 // Immediate Addition
7162 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7163 match(Set dst (AddI src1 src2));
7165 size(4);
7166 format %{ "ADD $src1,$src2,$dst" %}
7167 opcode(Assembler::add_op3, Assembler::arith_op);
7168 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7169 ins_pipe(ialu_reg_imm);
7170 %}
7172 // Pointer Register Addition
7173 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7174 match(Set dst (AddP src1 src2));
7176 size(4);
7177 format %{ "ADD $src1,$src2,$dst" %}
7178 opcode(Assembler::add_op3, Assembler::arith_op);
7179 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7180 ins_pipe(ialu_reg_reg);
7181 %}
7183 // Pointer Immediate Addition
7184 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7185 match(Set dst (AddP src1 src2));
7187 size(4);
7188 format %{ "ADD $src1,$src2,$dst" %}
7189 opcode(Assembler::add_op3, Assembler::arith_op);
7190 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7191 ins_pipe(ialu_reg_imm);
7192 %}
7194 // Long Addition
7195 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7196 match(Set dst (AddL src1 src2));
7198 size(4);
7199 format %{ "ADD $src1,$src2,$dst\t! long" %}
7200 opcode(Assembler::add_op3, Assembler::arith_op);
7201 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7202 ins_pipe(ialu_reg_reg);
7203 %}
7205 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7206 match(Set dst (AddL src1 con));
7208 size(4);
7209 format %{ "ADD $src1,$con,$dst" %}
7210 opcode(Assembler::add_op3, Assembler::arith_op);
7211 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7212 ins_pipe(ialu_reg_imm);
7213 %}
7215 //----------Conditional_store--------------------------------------------------
7216 // Conditional-store of the updated heap-top.
7217 // Used during allocation of the shared heap.
7218 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7220 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7221 instruct loadPLocked(iRegP dst, memory mem) %{
7222 match(Set dst (LoadPLocked mem));
7223 ins_cost(MEMORY_REF_COST);
7225 #ifndef _LP64
7226 size(4);
7227 format %{ "LDUW $mem,$dst\t! ptr" %}
7228 opcode(Assembler::lduw_op3, 0, REGP_OP);
7229 #else
7230 format %{ "LDX $mem,$dst\t! ptr" %}
7231 opcode(Assembler::ldx_op3, 0, REGP_OP);
7232 #endif
7233 ins_encode( form3_mem_reg( mem, dst ) );
7234 ins_pipe(iload_mem);
7235 %}
7237 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7238 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7239 effect( KILL newval );
7240 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7241 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7242 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7243 ins_pipe( long_memory_op );
7244 %}
7246 // Conditional-store of an int value.
7247 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7248 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7249 effect( KILL newval );
7250 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7251 "CMP $oldval,$newval\t\t! See if we made progress" %}
7252 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7253 ins_pipe( long_memory_op );
7254 %}
7256 // Conditional-store of a long value.
7257 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7258 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7259 effect( KILL newval );
7260 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7261 "CMP $oldval,$newval\t\t! See if we made progress" %}
7262 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7263 ins_pipe( long_memory_op );
7264 %}
7266 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7268 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7269 predicate(VM_Version::supports_cx8());
7270 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7271 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7272 format %{
7273 "MOV $newval,O7\n\t"
7274 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7275 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7276 "MOV 1,$res\n\t"
7277 "MOVne xcc,R_G0,$res"
7278 %}
7279 ins_encode( enc_casx(mem_ptr, oldval, newval),
7280 enc_lflags_ne_to_boolean(res) );
7281 ins_pipe( long_memory_op );
7282 %}
7285 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7286 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7287 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7288 format %{
7289 "MOV $newval,O7\n\t"
7290 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7291 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7292 "MOV 1,$res\n\t"
7293 "MOVne icc,R_G0,$res"
7294 %}
7295 ins_encode( enc_casi(mem_ptr, oldval, newval),
7296 enc_iflags_ne_to_boolean(res) );
7297 ins_pipe( long_memory_op );
7298 %}
7300 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7301 #ifdef _LP64
7302 predicate(VM_Version::supports_cx8());
7303 #endif
7304 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7305 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7306 format %{
7307 "MOV $newval,O7\n\t"
7308 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7309 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7310 "MOV 1,$res\n\t"
7311 "MOVne xcc,R_G0,$res"
7312 %}
7313 #ifdef _LP64
7314 ins_encode( enc_casx(mem_ptr, oldval, newval),
7315 enc_lflags_ne_to_boolean(res) );
7316 #else
7317 ins_encode( enc_casi(mem_ptr, oldval, newval),
7318 enc_iflags_ne_to_boolean(res) );
7319 #endif
7320 ins_pipe( long_memory_op );
7321 %}
7323 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7324 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7325 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7326 format %{
7327 "MOV $newval,O7\n\t"
7328 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7329 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7330 "MOV 1,$res\n\t"
7331 "MOVne icc,R_G0,$res"
7332 %}
7333 ins_encode( enc_casi(mem_ptr, oldval, newval),
7334 enc_iflags_ne_to_boolean(res) );
7335 ins_pipe( long_memory_op );
7336 %}
7338 instruct xchgI( memory mem, iRegI newval) %{
7339 match(Set newval (GetAndSetI mem newval));
7340 format %{ "SWAP [$mem],$newval" %}
7341 size(4);
7342 ins_encode %{
7343 __ swap($mem$$Address, $newval$$Register);
7344 %}
7345 ins_pipe( long_memory_op );
7346 %}
7348 #ifndef _LP64
7349 instruct xchgP( memory mem, iRegP newval) %{
7350 match(Set newval (GetAndSetP mem newval));
7351 format %{ "SWAP [$mem],$newval" %}
7352 size(4);
7353 ins_encode %{
7354 __ swap($mem$$Address, $newval$$Register);
7355 %}
7356 ins_pipe( long_memory_op );
7357 %}
7358 #endif
7360 instruct xchgN( memory mem, iRegN newval) %{
7361 match(Set newval (GetAndSetN mem newval));
7362 format %{ "SWAP [$mem],$newval" %}
7363 size(4);
7364 ins_encode %{
7365 __ swap($mem$$Address, $newval$$Register);
7366 %}
7367 ins_pipe( long_memory_op );
7368 %}
7370 //---------------------
7371 // Subtraction Instructions
7372 // Register Subtraction
7373 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7374 match(Set dst (SubI src1 src2));
7376 size(4);
7377 format %{ "SUB $src1,$src2,$dst" %}
7378 opcode(Assembler::sub_op3, Assembler::arith_op);
7379 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7380 ins_pipe(ialu_reg_reg);
7381 %}
7383 // Immediate Subtraction
7384 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7385 match(Set dst (SubI src1 src2));
7387 size(4);
7388 format %{ "SUB $src1,$src2,$dst" %}
7389 opcode(Assembler::sub_op3, Assembler::arith_op);
7390 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7391 ins_pipe(ialu_reg_imm);
7392 %}
7394 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7395 match(Set dst (SubI zero src2));
7397 size(4);
7398 format %{ "NEG $src2,$dst" %}
7399 opcode(Assembler::sub_op3, Assembler::arith_op);
7400 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7401 ins_pipe(ialu_zero_reg);
7402 %}
7404 // Long subtraction
7405 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7406 match(Set dst (SubL src1 src2));
7408 size(4);
7409 format %{ "SUB $src1,$src2,$dst\t! long" %}
7410 opcode(Assembler::sub_op3, Assembler::arith_op);
7411 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7412 ins_pipe(ialu_reg_reg);
7413 %}
7415 // Immediate Subtraction
7416 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7417 match(Set dst (SubL src1 con));
7419 size(4);
7420 format %{ "SUB $src1,$con,$dst\t! long" %}
7421 opcode(Assembler::sub_op3, Assembler::arith_op);
7422 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7423 ins_pipe(ialu_reg_imm);
7424 %}
7426 // Long negation
7427 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7428 match(Set dst (SubL zero src2));
7430 size(4);
7431 format %{ "NEG $src2,$dst\t! long" %}
7432 opcode(Assembler::sub_op3, Assembler::arith_op);
7433 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7434 ins_pipe(ialu_zero_reg);
7435 %}
7437 // Multiplication Instructions
7438 // Integer Multiplication
7439 // Register Multiplication
7440 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7441 match(Set dst (MulI src1 src2));
7443 size(4);
7444 format %{ "MULX $src1,$src2,$dst" %}
7445 opcode(Assembler::mulx_op3, Assembler::arith_op);
7446 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7447 ins_pipe(imul_reg_reg);
7448 %}
7450 // Immediate Multiplication
7451 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7452 match(Set dst (MulI src1 src2));
7454 size(4);
7455 format %{ "MULX $src1,$src2,$dst" %}
7456 opcode(Assembler::mulx_op3, Assembler::arith_op);
7457 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7458 ins_pipe(imul_reg_imm);
7459 %}
7461 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7462 match(Set dst (MulL src1 src2));
7463 ins_cost(DEFAULT_COST * 5);
7464 size(4);
7465 format %{ "MULX $src1,$src2,$dst\t! long" %}
7466 opcode(Assembler::mulx_op3, Assembler::arith_op);
7467 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7468 ins_pipe(mulL_reg_reg);
7469 %}
7471 // Immediate Multiplication
7472 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7473 match(Set dst (MulL src1 src2));
7474 ins_cost(DEFAULT_COST * 5);
7475 size(4);
7476 format %{ "MULX $src1,$src2,$dst" %}
7477 opcode(Assembler::mulx_op3, Assembler::arith_op);
7478 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7479 ins_pipe(mulL_reg_imm);
7480 %}
7482 // Integer Division
7483 // Register Division
7484 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7485 match(Set dst (DivI src1 src2));
7486 ins_cost((2+71)*DEFAULT_COST);
7488 format %{ "SRA $src2,0,$src2\n\t"
7489 "SRA $src1,0,$src1\n\t"
7490 "SDIVX $src1,$src2,$dst" %}
7491 ins_encode( idiv_reg( src1, src2, dst ) );
7492 ins_pipe(sdiv_reg_reg);
7493 %}
7495 // Immediate Division
7496 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7497 match(Set dst (DivI src1 src2));
7498 ins_cost((2+71)*DEFAULT_COST);
7500 format %{ "SRA $src1,0,$src1\n\t"
7501 "SDIVX $src1,$src2,$dst" %}
7502 ins_encode( idiv_imm( src1, src2, dst ) );
7503 ins_pipe(sdiv_reg_imm);
7504 %}
7506 //----------Div-By-10-Expansion------------------------------------------------
7507 // Extract hi bits of a 32x32->64 bit multiply.
7508 // Expand rule only, not matched
7509 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7510 effect( DEF dst, USE src1, USE src2 );
7511 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7512 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7513 ins_encode( enc_mul_hi(dst,src1,src2));
7514 ins_pipe(sdiv_reg_reg);
7515 %}
7517 // Magic constant, reciprocal of 10
7518 instruct loadConI_x66666667(iRegIsafe dst) %{
7519 effect( DEF dst );
7521 size(8);
7522 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7523 ins_encode( Set32(0x66666667, dst) );
7524 ins_pipe(ialu_hi_lo_reg);
7525 %}
7527 // Register Shift Right Arithmetic Long by 32-63
7528 instruct sra_31( iRegI dst, iRegI src ) %{
7529 effect( DEF dst, USE src );
7530 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7531 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7532 ins_pipe(ialu_reg_reg);
7533 %}
7535 // Arithmetic Shift Right by 8-bit immediate
7536 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7537 effect( DEF dst, USE src );
7538 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7539 opcode(Assembler::sra_op3, Assembler::arith_op);
7540 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7541 ins_pipe(ialu_reg_imm);
7542 %}
7544 // Integer DIV with 10
7545 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7546 match(Set dst (DivI src div));
7547 ins_cost((6+6)*DEFAULT_COST);
7548 expand %{
7549 iRegIsafe tmp1; // Killed temps;
7550 iRegIsafe tmp2; // Killed temps;
7551 iRegI tmp3; // Killed temps;
7552 iRegI tmp4; // Killed temps;
7553 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7554 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7555 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7556 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7557 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7558 %}
7559 %}
7561 // Register Long Division
7562 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7563 match(Set dst (DivL src1 src2));
7564 ins_cost(DEFAULT_COST*71);
7565 size(4);
7566 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7567 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7568 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7569 ins_pipe(divL_reg_reg);
7570 %}
7572 // Register Long Division
7573 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7574 match(Set dst (DivL src1 src2));
7575 ins_cost(DEFAULT_COST*71);
7576 size(4);
7577 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7578 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7579 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7580 ins_pipe(divL_reg_imm);
7581 %}
7583 // Integer Remainder
7584 // Register Remainder
7585 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7586 match(Set dst (ModI src1 src2));
7587 effect( KILL ccr, KILL temp);
7589 format %{ "SREM $src1,$src2,$dst" %}
7590 ins_encode( irem_reg(src1, src2, dst, temp) );
7591 ins_pipe(sdiv_reg_reg);
7592 %}
7594 // Immediate Remainder
7595 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7596 match(Set dst (ModI src1 src2));
7597 effect( KILL ccr, KILL temp);
7599 format %{ "SREM $src1,$src2,$dst" %}
7600 ins_encode( irem_imm(src1, src2, dst, temp) );
7601 ins_pipe(sdiv_reg_imm);
7602 %}
7604 // Register Long Remainder
7605 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7606 effect(DEF dst, USE src1, USE src2);
7607 size(4);
7608 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7609 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7610 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7611 ins_pipe(divL_reg_reg);
7612 %}
7614 // Register Long Division
7615 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7616 effect(DEF dst, USE src1, USE src2);
7617 size(4);
7618 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7619 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7620 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7621 ins_pipe(divL_reg_imm);
7622 %}
7624 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7625 effect(DEF dst, USE src1, USE src2);
7626 size(4);
7627 format %{ "MULX $src1,$src2,$dst\t! long" %}
7628 opcode(Assembler::mulx_op3, Assembler::arith_op);
7629 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7630 ins_pipe(mulL_reg_reg);
7631 %}
7633 // Immediate Multiplication
7634 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7635 effect(DEF dst, USE src1, USE src2);
7636 size(4);
7637 format %{ "MULX $src1,$src2,$dst" %}
7638 opcode(Assembler::mulx_op3, Assembler::arith_op);
7639 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7640 ins_pipe(mulL_reg_imm);
7641 %}
7643 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7644 effect(DEF dst, USE src1, USE src2);
7645 size(4);
7646 format %{ "SUB $src1,$src2,$dst\t! long" %}
7647 opcode(Assembler::sub_op3, Assembler::arith_op);
7648 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7649 ins_pipe(ialu_reg_reg);
7650 %}
7652 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7653 effect(DEF dst, USE src1, USE src2);
7654 size(4);
7655 format %{ "SUB $src1,$src2,$dst\t! long" %}
7656 opcode(Assembler::sub_op3, Assembler::arith_op);
7657 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7658 ins_pipe(ialu_reg_reg);
7659 %}
7661 // Register Long Remainder
7662 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7663 match(Set dst (ModL src1 src2));
7664 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7665 expand %{
7666 iRegL tmp1;
7667 iRegL tmp2;
7668 divL_reg_reg_1(tmp1, src1, src2);
7669 mulL_reg_reg_1(tmp2, tmp1, src2);
7670 subL_reg_reg_1(dst, src1, tmp2);
7671 %}
7672 %}
7674 // Register Long Remainder
7675 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7676 match(Set dst (ModL src1 src2));
7677 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7678 expand %{
7679 iRegL tmp1;
7680 iRegL tmp2;
7681 divL_reg_imm13_1(tmp1, src1, src2);
7682 mulL_reg_imm13_1(tmp2, tmp1, src2);
7683 subL_reg_reg_2 (dst, src1, tmp2);
7684 %}
7685 %}
7687 // Integer Shift Instructions
7688 // Register Shift Left
7689 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7690 match(Set dst (LShiftI src1 src2));
7692 size(4);
7693 format %{ "SLL $src1,$src2,$dst" %}
7694 opcode(Assembler::sll_op3, Assembler::arith_op);
7695 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7696 ins_pipe(ialu_reg_reg);
7697 %}
7699 // Register Shift Left Immediate
7700 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7701 match(Set dst (LShiftI src1 src2));
7703 size(4);
7704 format %{ "SLL $src1,$src2,$dst" %}
7705 opcode(Assembler::sll_op3, Assembler::arith_op);
7706 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7707 ins_pipe(ialu_reg_imm);
7708 %}
7710 // Register Shift Left
7711 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7712 match(Set dst (LShiftL src1 src2));
7714 size(4);
7715 format %{ "SLLX $src1,$src2,$dst" %}
7716 opcode(Assembler::sllx_op3, Assembler::arith_op);
7717 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7718 ins_pipe(ialu_reg_reg);
7719 %}
7721 // Register Shift Left Immediate
7722 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7723 match(Set dst (LShiftL src1 src2));
7725 size(4);
7726 format %{ "SLLX $src1,$src2,$dst" %}
7727 opcode(Assembler::sllx_op3, Assembler::arith_op);
7728 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7729 ins_pipe(ialu_reg_imm);
7730 %}
7732 // Register Arithmetic Shift Right
7733 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7734 match(Set dst (RShiftI src1 src2));
7735 size(4);
7736 format %{ "SRA $src1,$src2,$dst" %}
7737 opcode(Assembler::sra_op3, Assembler::arith_op);
7738 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7739 ins_pipe(ialu_reg_reg);
7740 %}
7742 // Register Arithmetic Shift Right Immediate
7743 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7744 match(Set dst (RShiftI src1 src2));
7746 size(4);
7747 format %{ "SRA $src1,$src2,$dst" %}
7748 opcode(Assembler::sra_op3, Assembler::arith_op);
7749 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7750 ins_pipe(ialu_reg_imm);
7751 %}
7753 // Register Shift Right Arithmatic Long
7754 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7755 match(Set dst (RShiftL src1 src2));
7757 size(4);
7758 format %{ "SRAX $src1,$src2,$dst" %}
7759 opcode(Assembler::srax_op3, Assembler::arith_op);
7760 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7761 ins_pipe(ialu_reg_reg);
7762 %}
7764 // Register Shift Left Immediate
7765 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7766 match(Set dst (RShiftL src1 src2));
7768 size(4);
7769 format %{ "SRAX $src1,$src2,$dst" %}
7770 opcode(Assembler::srax_op3, Assembler::arith_op);
7771 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7772 ins_pipe(ialu_reg_imm);
7773 %}
7775 // Register Shift Right
7776 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7777 match(Set dst (URShiftI src1 src2));
7779 size(4);
7780 format %{ "SRL $src1,$src2,$dst" %}
7781 opcode(Assembler::srl_op3, Assembler::arith_op);
7782 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7783 ins_pipe(ialu_reg_reg);
7784 %}
7786 // Register Shift Right Immediate
7787 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7788 match(Set dst (URShiftI src1 src2));
7790 size(4);
7791 format %{ "SRL $src1,$src2,$dst" %}
7792 opcode(Assembler::srl_op3, Assembler::arith_op);
7793 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7794 ins_pipe(ialu_reg_imm);
7795 %}
7797 // Register Shift Right
7798 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7799 match(Set dst (URShiftL src1 src2));
7801 size(4);
7802 format %{ "SRLX $src1,$src2,$dst" %}
7803 opcode(Assembler::srlx_op3, Assembler::arith_op);
7804 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7805 ins_pipe(ialu_reg_reg);
7806 %}
7808 // Register Shift Right Immediate
7809 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7810 match(Set dst (URShiftL src1 src2));
7812 size(4);
7813 format %{ "SRLX $src1,$src2,$dst" %}
7814 opcode(Assembler::srlx_op3, Assembler::arith_op);
7815 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7816 ins_pipe(ialu_reg_imm);
7817 %}
7819 // Register Shift Right Immediate with a CastP2X
7820 #ifdef _LP64
7821 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7822 match(Set dst (URShiftL (CastP2X src1) src2));
7823 size(4);
7824 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7825 opcode(Assembler::srlx_op3, Assembler::arith_op);
7826 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7827 ins_pipe(ialu_reg_imm);
7828 %}
7829 #else
7830 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7831 match(Set dst (URShiftI (CastP2X src1) src2));
7832 size(4);
7833 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7834 opcode(Assembler::srl_op3, Assembler::arith_op);
7835 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7836 ins_pipe(ialu_reg_imm);
7837 %}
7838 #endif
7841 //----------Floating Point Arithmetic Instructions-----------------------------
7843 // Add float single precision
7844 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7845 match(Set dst (AddF src1 src2));
7847 size(4);
7848 format %{ "FADDS $src1,$src2,$dst" %}
7849 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7850 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7851 ins_pipe(faddF_reg_reg);
7852 %}
7854 // Add float double precision
7855 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7856 match(Set dst (AddD src1 src2));
7858 size(4);
7859 format %{ "FADDD $src1,$src2,$dst" %}
7860 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7861 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7862 ins_pipe(faddD_reg_reg);
7863 %}
7865 // Sub float single precision
7866 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7867 match(Set dst (SubF src1 src2));
7869 size(4);
7870 format %{ "FSUBS $src1,$src2,$dst" %}
7871 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7872 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7873 ins_pipe(faddF_reg_reg);
7874 %}
7876 // Sub float double precision
7877 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7878 match(Set dst (SubD src1 src2));
7880 size(4);
7881 format %{ "FSUBD $src1,$src2,$dst" %}
7882 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7883 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7884 ins_pipe(faddD_reg_reg);
7885 %}
7887 // Mul float single precision
7888 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7889 match(Set dst (MulF src1 src2));
7891 size(4);
7892 format %{ "FMULS $src1,$src2,$dst" %}
7893 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7894 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7895 ins_pipe(fmulF_reg_reg);
7896 %}
7898 // Mul float double precision
7899 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7900 match(Set dst (MulD src1 src2));
7902 size(4);
7903 format %{ "FMULD $src1,$src2,$dst" %}
7904 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7905 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7906 ins_pipe(fmulD_reg_reg);
7907 %}
7909 // Div float single precision
7910 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7911 match(Set dst (DivF src1 src2));
7913 size(4);
7914 format %{ "FDIVS $src1,$src2,$dst" %}
7915 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7916 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7917 ins_pipe(fdivF_reg_reg);
7918 %}
7920 // Div float double precision
7921 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7922 match(Set dst (DivD src1 src2));
7924 size(4);
7925 format %{ "FDIVD $src1,$src2,$dst" %}
7926 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7927 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7928 ins_pipe(fdivD_reg_reg);
7929 %}
7931 // Absolute float double precision
7932 instruct absD_reg(regD dst, regD src) %{
7933 match(Set dst (AbsD src));
7935 format %{ "FABSd $src,$dst" %}
7936 ins_encode(fabsd(dst, src));
7937 ins_pipe(faddD_reg);
7938 %}
7940 // Absolute float single precision
7941 instruct absF_reg(regF dst, regF src) %{
7942 match(Set dst (AbsF src));
7944 format %{ "FABSs $src,$dst" %}
7945 ins_encode(fabss(dst, src));
7946 ins_pipe(faddF_reg);
7947 %}
7949 instruct negF_reg(regF dst, regF src) %{
7950 match(Set dst (NegF src));
7952 size(4);
7953 format %{ "FNEGs $src,$dst" %}
7954 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7955 ins_encode(form3_opf_rs2F_rdF(src, dst));
7956 ins_pipe(faddF_reg);
7957 %}
7959 instruct negD_reg(regD dst, regD src) %{
7960 match(Set dst (NegD src));
7962 format %{ "FNEGd $src,$dst" %}
7963 ins_encode(fnegd(dst, src));
7964 ins_pipe(faddD_reg);
7965 %}
7967 // Sqrt float double precision
7968 instruct sqrtF_reg_reg(regF dst, regF src) %{
7969 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7971 size(4);
7972 format %{ "FSQRTS $src,$dst" %}
7973 ins_encode(fsqrts(dst, src));
7974 ins_pipe(fdivF_reg_reg);
7975 %}
7977 // Sqrt float double precision
7978 instruct sqrtD_reg_reg(regD dst, regD src) %{
7979 match(Set dst (SqrtD src));
7981 size(4);
7982 format %{ "FSQRTD $src,$dst" %}
7983 ins_encode(fsqrtd(dst, src));
7984 ins_pipe(fdivD_reg_reg);
7985 %}
7987 //----------Logical Instructions-----------------------------------------------
7988 // And Instructions
7989 // Register And
7990 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7991 match(Set dst (AndI src1 src2));
7993 size(4);
7994 format %{ "AND $src1,$src2,$dst" %}
7995 opcode(Assembler::and_op3, Assembler::arith_op);
7996 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7997 ins_pipe(ialu_reg_reg);
7998 %}
8000 // Immediate And
8001 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8002 match(Set dst (AndI src1 src2));
8004 size(4);
8005 format %{ "AND $src1,$src2,$dst" %}
8006 opcode(Assembler::and_op3, Assembler::arith_op);
8007 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8008 ins_pipe(ialu_reg_imm);
8009 %}
8011 // Register And Long
8012 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8013 match(Set dst (AndL src1 src2));
8015 ins_cost(DEFAULT_COST);
8016 size(4);
8017 format %{ "AND $src1,$src2,$dst\t! long" %}
8018 opcode(Assembler::and_op3, Assembler::arith_op);
8019 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8020 ins_pipe(ialu_reg_reg);
8021 %}
8023 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8024 match(Set dst (AndL src1 con));
8026 ins_cost(DEFAULT_COST);
8027 size(4);
8028 format %{ "AND $src1,$con,$dst\t! long" %}
8029 opcode(Assembler::and_op3, Assembler::arith_op);
8030 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8031 ins_pipe(ialu_reg_imm);
8032 %}
8034 // Or Instructions
8035 // Register Or
8036 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8037 match(Set dst (OrI src1 src2));
8039 size(4);
8040 format %{ "OR $src1,$src2,$dst" %}
8041 opcode(Assembler::or_op3, Assembler::arith_op);
8042 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8043 ins_pipe(ialu_reg_reg);
8044 %}
8046 // Immediate Or
8047 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8048 match(Set dst (OrI src1 src2));
8050 size(4);
8051 format %{ "OR $src1,$src2,$dst" %}
8052 opcode(Assembler::or_op3, Assembler::arith_op);
8053 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8054 ins_pipe(ialu_reg_imm);
8055 %}
8057 // Register Or Long
8058 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8059 match(Set dst (OrL src1 src2));
8061 ins_cost(DEFAULT_COST);
8062 size(4);
8063 format %{ "OR $src1,$src2,$dst\t! long" %}
8064 opcode(Assembler::or_op3, Assembler::arith_op);
8065 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8066 ins_pipe(ialu_reg_reg);
8067 %}
8069 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8070 match(Set dst (OrL src1 con));
8071 ins_cost(DEFAULT_COST*2);
8073 ins_cost(DEFAULT_COST);
8074 size(4);
8075 format %{ "OR $src1,$con,$dst\t! long" %}
8076 opcode(Assembler::or_op3, Assembler::arith_op);
8077 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8078 ins_pipe(ialu_reg_imm);
8079 %}
8081 #ifndef _LP64
8083 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8084 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8085 match(Set dst (OrI src1 (CastP2X src2)));
8087 size(4);
8088 format %{ "OR $src1,$src2,$dst" %}
8089 opcode(Assembler::or_op3, Assembler::arith_op);
8090 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8091 ins_pipe(ialu_reg_reg);
8092 %}
8094 #else
8096 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8097 match(Set dst (OrL src1 (CastP2X src2)));
8099 ins_cost(DEFAULT_COST);
8100 size(4);
8101 format %{ "OR $src1,$src2,$dst\t! long" %}
8102 opcode(Assembler::or_op3, Assembler::arith_op);
8103 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8104 ins_pipe(ialu_reg_reg);
8105 %}
8107 #endif
8109 // Xor Instructions
8110 // Register Xor
8111 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8112 match(Set dst (XorI src1 src2));
8114 size(4);
8115 format %{ "XOR $src1,$src2,$dst" %}
8116 opcode(Assembler::xor_op3, Assembler::arith_op);
8117 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8118 ins_pipe(ialu_reg_reg);
8119 %}
8121 // Immediate Xor
8122 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8123 match(Set dst (XorI src1 src2));
8125 size(4);
8126 format %{ "XOR $src1,$src2,$dst" %}
8127 opcode(Assembler::xor_op3, Assembler::arith_op);
8128 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8129 ins_pipe(ialu_reg_imm);
8130 %}
8132 // Register Xor Long
8133 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8134 match(Set dst (XorL src1 src2));
8136 ins_cost(DEFAULT_COST);
8137 size(4);
8138 format %{ "XOR $src1,$src2,$dst\t! long" %}
8139 opcode(Assembler::xor_op3, Assembler::arith_op);
8140 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8141 ins_pipe(ialu_reg_reg);
8142 %}
8144 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8145 match(Set dst (XorL src1 con));
8147 ins_cost(DEFAULT_COST);
8148 size(4);
8149 format %{ "XOR $src1,$con,$dst\t! long" %}
8150 opcode(Assembler::xor_op3, Assembler::arith_op);
8151 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8152 ins_pipe(ialu_reg_imm);
8153 %}
8155 //----------Convert to Boolean-------------------------------------------------
8156 // Nice hack for 32-bit tests but doesn't work for
8157 // 64-bit pointers.
8158 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8159 match(Set dst (Conv2B src));
8160 effect( KILL ccr );
8161 ins_cost(DEFAULT_COST*2);
8162 format %{ "CMP R_G0,$src\n\t"
8163 "ADDX R_G0,0,$dst" %}
8164 ins_encode( enc_to_bool( src, dst ) );
8165 ins_pipe(ialu_reg_ialu);
8166 %}
8168 #ifndef _LP64
8169 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8170 match(Set dst (Conv2B src));
8171 effect( KILL ccr );
8172 ins_cost(DEFAULT_COST*2);
8173 format %{ "CMP R_G0,$src\n\t"
8174 "ADDX R_G0,0,$dst" %}
8175 ins_encode( enc_to_bool( src, dst ) );
8176 ins_pipe(ialu_reg_ialu);
8177 %}
8178 #else
8179 instruct convP2B( iRegI dst, iRegP src ) %{
8180 match(Set dst (Conv2B src));
8181 ins_cost(DEFAULT_COST*2);
8182 format %{ "MOV $src,$dst\n\t"
8183 "MOVRNZ $src,1,$dst" %}
8184 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8185 ins_pipe(ialu_clr_and_mover);
8186 %}
8187 #endif
8189 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8190 match(Set dst (CmpLTMask src zero));
8191 effect(KILL ccr);
8192 size(4);
8193 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8194 ins_encode %{
8195 __ sra($src$$Register, 31, $dst$$Register);
8196 %}
8197 ins_pipe(ialu_reg_imm);
8198 %}
8200 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8201 match(Set dst (CmpLTMask p q));
8202 effect( KILL ccr );
8203 ins_cost(DEFAULT_COST*4);
8204 format %{ "CMP $p,$q\n\t"
8205 "MOV #0,$dst\n\t"
8206 "BLT,a .+8\n\t"
8207 "MOV #-1,$dst" %}
8208 ins_encode( enc_ltmask(p,q,dst) );
8209 ins_pipe(ialu_reg_reg_ialu);
8210 %}
8212 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8213 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8214 effect(KILL ccr, TEMP tmp);
8215 ins_cost(DEFAULT_COST*3);
8217 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8218 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8219 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8220 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8221 ins_pipe(cadd_cmpltmask);
8222 %}
8224 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8225 match(Set p (AndI (CmpLTMask p q) y));
8226 effect(KILL ccr);
8227 ins_cost(DEFAULT_COST*3);
8229 format %{ "CMP $p,$q\n\t"
8230 "MOV $y,$p\n\t"
8231 "MOVge G0,$p" %}
8232 ins_encode %{
8233 __ cmp($p$$Register, $q$$Register);
8234 __ mov($y$$Register, $p$$Register);
8235 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8236 %}
8237 ins_pipe(ialu_reg_reg_ialu);
8238 %}
8240 //-----------------------------------------------------------------
8241 // Direct raw moves between float and general registers using VIS3.
8243 // ins_pipe(faddF_reg);
8244 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8245 predicate(UseVIS >= 3);
8246 match(Set dst (MoveF2I src));
8248 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8249 ins_encode %{
8250 __ movstouw($src$$FloatRegister, $dst$$Register);
8251 %}
8252 ins_pipe(ialu_reg_reg);
8253 %}
8255 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8256 predicate(UseVIS >= 3);
8257 match(Set dst (MoveI2F src));
8259 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8260 ins_encode %{
8261 __ movwtos($src$$Register, $dst$$FloatRegister);
8262 %}
8263 ins_pipe(ialu_reg_reg);
8264 %}
8266 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8267 predicate(UseVIS >= 3);
8268 match(Set dst (MoveD2L src));
8270 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8271 ins_encode %{
8272 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8273 %}
8274 ins_pipe(ialu_reg_reg);
8275 %}
8277 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8278 predicate(UseVIS >= 3);
8279 match(Set dst (MoveL2D src));
8281 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8282 ins_encode %{
8283 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8284 %}
8285 ins_pipe(ialu_reg_reg);
8286 %}
8289 // Raw moves between float and general registers using stack.
8291 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8292 match(Set dst (MoveF2I src));
8293 effect(DEF dst, USE src);
8294 ins_cost(MEMORY_REF_COST);
8296 size(4);
8297 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8298 opcode(Assembler::lduw_op3);
8299 ins_encode(simple_form3_mem_reg( src, dst ) );
8300 ins_pipe(iload_mem);
8301 %}
8303 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8304 match(Set dst (MoveI2F src));
8305 effect(DEF dst, USE src);
8306 ins_cost(MEMORY_REF_COST);
8308 size(4);
8309 format %{ "LDF $src,$dst\t! MoveI2F" %}
8310 opcode(Assembler::ldf_op3);
8311 ins_encode(simple_form3_mem_reg(src, dst));
8312 ins_pipe(floadF_stk);
8313 %}
8315 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8316 match(Set dst (MoveD2L src));
8317 effect(DEF dst, USE src);
8318 ins_cost(MEMORY_REF_COST);
8320 size(4);
8321 format %{ "LDX $src,$dst\t! MoveD2L" %}
8322 opcode(Assembler::ldx_op3);
8323 ins_encode(simple_form3_mem_reg( src, dst ) );
8324 ins_pipe(iload_mem);
8325 %}
8327 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8328 match(Set dst (MoveL2D src));
8329 effect(DEF dst, USE src);
8330 ins_cost(MEMORY_REF_COST);
8332 size(4);
8333 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8334 opcode(Assembler::lddf_op3);
8335 ins_encode(simple_form3_mem_reg(src, dst));
8336 ins_pipe(floadD_stk);
8337 %}
8339 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8340 match(Set dst (MoveF2I src));
8341 effect(DEF dst, USE src);
8342 ins_cost(MEMORY_REF_COST);
8344 size(4);
8345 format %{ "STF $src,$dst\t! MoveF2I" %}
8346 opcode(Assembler::stf_op3);
8347 ins_encode(simple_form3_mem_reg(dst, src));
8348 ins_pipe(fstoreF_stk_reg);
8349 %}
8351 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8352 match(Set dst (MoveI2F src));
8353 effect(DEF dst, USE src);
8354 ins_cost(MEMORY_REF_COST);
8356 size(4);
8357 format %{ "STW $src,$dst\t! MoveI2F" %}
8358 opcode(Assembler::stw_op3);
8359 ins_encode(simple_form3_mem_reg( dst, src ) );
8360 ins_pipe(istore_mem_reg);
8361 %}
8363 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8364 match(Set dst (MoveD2L src));
8365 effect(DEF dst, USE src);
8366 ins_cost(MEMORY_REF_COST);
8368 size(4);
8369 format %{ "STDF $src,$dst\t! MoveD2L" %}
8370 opcode(Assembler::stdf_op3);
8371 ins_encode(simple_form3_mem_reg(dst, src));
8372 ins_pipe(fstoreD_stk_reg);
8373 %}
8375 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8376 match(Set dst (MoveL2D src));
8377 effect(DEF dst, USE src);
8378 ins_cost(MEMORY_REF_COST);
8380 size(4);
8381 format %{ "STX $src,$dst\t! MoveL2D" %}
8382 opcode(Assembler::stx_op3);
8383 ins_encode(simple_form3_mem_reg( dst, src ) );
8384 ins_pipe(istore_mem_reg);
8385 %}
8388 //----------Arithmetic Conversion Instructions---------------------------------
8389 // The conversions operations are all Alpha sorted. Please keep it that way!
8391 instruct convD2F_reg(regF dst, regD src) %{
8392 match(Set dst (ConvD2F src));
8393 size(4);
8394 format %{ "FDTOS $src,$dst" %}
8395 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8396 ins_encode(form3_opf_rs2D_rdF(src, dst));
8397 ins_pipe(fcvtD2F);
8398 %}
8401 // Convert a double to an int in a float register.
8402 // If the double is a NAN, stuff a zero in instead.
8403 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8404 effect(DEF dst, USE src, KILL fcc0);
8405 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8406 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8407 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8408 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8409 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8410 "skip:" %}
8411 ins_encode(form_d2i_helper(src,dst));
8412 ins_pipe(fcvtD2I);
8413 %}
8415 instruct convD2I_stk(stackSlotI dst, regD src) %{
8416 match(Set dst (ConvD2I src));
8417 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8418 expand %{
8419 regF tmp;
8420 convD2I_helper(tmp, src);
8421 regF_to_stkI(dst, tmp);
8422 %}
8423 %}
8425 instruct convD2I_reg(iRegI dst, regD src) %{
8426 predicate(UseVIS >= 3);
8427 match(Set dst (ConvD2I src));
8428 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8429 expand %{
8430 regF tmp;
8431 convD2I_helper(tmp, src);
8432 MoveF2I_reg_reg(dst, tmp);
8433 %}
8434 %}
8437 // Convert a double to a long in a double register.
8438 // If the double is a NAN, stuff a zero in instead.
8439 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8440 effect(DEF dst, USE src, KILL fcc0);
8441 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8442 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8443 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8444 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8445 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8446 "skip:" %}
8447 ins_encode(form_d2l_helper(src,dst));
8448 ins_pipe(fcvtD2L);
8449 %}
8451 instruct convD2L_stk(stackSlotL dst, regD src) %{
8452 match(Set dst (ConvD2L src));
8453 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8454 expand %{
8455 regD tmp;
8456 convD2L_helper(tmp, src);
8457 regD_to_stkL(dst, tmp);
8458 %}
8459 %}
8461 instruct convD2L_reg(iRegL dst, regD src) %{
8462 predicate(UseVIS >= 3);
8463 match(Set dst (ConvD2L src));
8464 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8465 expand %{
8466 regD tmp;
8467 convD2L_helper(tmp, src);
8468 MoveD2L_reg_reg(dst, tmp);
8469 %}
8470 %}
8473 instruct convF2D_reg(regD dst, regF src) %{
8474 match(Set dst (ConvF2D src));
8475 format %{ "FSTOD $src,$dst" %}
8476 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8477 ins_encode(form3_opf_rs2F_rdD(src, dst));
8478 ins_pipe(fcvtF2D);
8479 %}
8482 // Convert a float to an int in a float register.
8483 // If the float is a NAN, stuff a zero in instead.
8484 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8485 effect(DEF dst, USE src, KILL fcc0);
8486 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8487 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8488 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8489 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8490 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8491 "skip:" %}
8492 ins_encode(form_f2i_helper(src,dst));
8493 ins_pipe(fcvtF2I);
8494 %}
8496 instruct convF2I_stk(stackSlotI dst, regF src) %{
8497 match(Set dst (ConvF2I src));
8498 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8499 expand %{
8500 regF tmp;
8501 convF2I_helper(tmp, src);
8502 regF_to_stkI(dst, tmp);
8503 %}
8504 %}
8506 instruct convF2I_reg(iRegI dst, regF src) %{
8507 predicate(UseVIS >= 3);
8508 match(Set dst (ConvF2I src));
8509 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8510 expand %{
8511 regF tmp;
8512 convF2I_helper(tmp, src);
8513 MoveF2I_reg_reg(dst, tmp);
8514 %}
8515 %}
8518 // Convert a float to a long in a float register.
8519 // If the float is a NAN, stuff a zero in instead.
8520 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8521 effect(DEF dst, USE src, KILL fcc0);
8522 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8523 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8524 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8525 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8526 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8527 "skip:" %}
8528 ins_encode(form_f2l_helper(src,dst));
8529 ins_pipe(fcvtF2L);
8530 %}
8532 instruct convF2L_stk(stackSlotL dst, regF src) %{
8533 match(Set dst (ConvF2L src));
8534 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8535 expand %{
8536 regD tmp;
8537 convF2L_helper(tmp, src);
8538 regD_to_stkL(dst, tmp);
8539 %}
8540 %}
8542 instruct convF2L_reg(iRegL dst, regF src) %{
8543 predicate(UseVIS >= 3);
8544 match(Set dst (ConvF2L src));
8545 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8546 expand %{
8547 regD tmp;
8548 convF2L_helper(tmp, src);
8549 MoveD2L_reg_reg(dst, tmp);
8550 %}
8551 %}
8554 instruct convI2D_helper(regD dst, regF tmp) %{
8555 effect(USE tmp, DEF dst);
8556 format %{ "FITOD $tmp,$dst" %}
8557 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8558 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8559 ins_pipe(fcvtI2D);
8560 %}
8562 instruct convI2D_stk(stackSlotI src, regD dst) %{
8563 match(Set dst (ConvI2D src));
8564 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8565 expand %{
8566 regF tmp;
8567 stkI_to_regF(tmp, src);
8568 convI2D_helper(dst, tmp);
8569 %}
8570 %}
8572 instruct convI2D_reg(regD_low dst, iRegI src) %{
8573 predicate(UseVIS >= 3);
8574 match(Set dst (ConvI2D src));
8575 expand %{
8576 regF tmp;
8577 MoveI2F_reg_reg(tmp, src);
8578 convI2D_helper(dst, tmp);
8579 %}
8580 %}
8582 instruct convI2D_mem(regD_low dst, memory mem) %{
8583 match(Set dst (ConvI2D (LoadI mem)));
8584 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8585 size(8);
8586 format %{ "LDF $mem,$dst\n\t"
8587 "FITOD $dst,$dst" %}
8588 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8589 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8590 ins_pipe(floadF_mem);
8591 %}
8594 instruct convI2F_helper(regF dst, regF tmp) %{
8595 effect(DEF dst, USE tmp);
8596 format %{ "FITOS $tmp,$dst" %}
8597 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8598 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8599 ins_pipe(fcvtI2F);
8600 %}
8602 instruct convI2F_stk(regF dst, stackSlotI src) %{
8603 match(Set dst (ConvI2F src));
8604 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8605 expand %{
8606 regF tmp;
8607 stkI_to_regF(tmp,src);
8608 convI2F_helper(dst, tmp);
8609 %}
8610 %}
8612 instruct convI2F_reg(regF dst, iRegI src) %{
8613 predicate(UseVIS >= 3);
8614 match(Set dst (ConvI2F src));
8615 ins_cost(DEFAULT_COST);
8616 expand %{
8617 regF tmp;
8618 MoveI2F_reg_reg(tmp, src);
8619 convI2F_helper(dst, tmp);
8620 %}
8621 %}
8623 instruct convI2F_mem( regF dst, memory mem ) %{
8624 match(Set dst (ConvI2F (LoadI mem)));
8625 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8626 size(8);
8627 format %{ "LDF $mem,$dst\n\t"
8628 "FITOS $dst,$dst" %}
8629 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8630 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8631 ins_pipe(floadF_mem);
8632 %}
8635 instruct convI2L_reg(iRegL dst, iRegI src) %{
8636 match(Set dst (ConvI2L src));
8637 size(4);
8638 format %{ "SRA $src,0,$dst\t! int->long" %}
8639 opcode(Assembler::sra_op3, Assembler::arith_op);
8640 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8641 ins_pipe(ialu_reg_reg);
8642 %}
8644 // Zero-extend convert int to long
8645 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8646 match(Set dst (AndL (ConvI2L src) mask) );
8647 size(4);
8648 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8649 opcode(Assembler::srl_op3, Assembler::arith_op);
8650 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8651 ins_pipe(ialu_reg_reg);
8652 %}
8654 // Zero-extend long
8655 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8656 match(Set dst (AndL src mask) );
8657 size(4);
8658 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8659 opcode(Assembler::srl_op3, Assembler::arith_op);
8660 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8661 ins_pipe(ialu_reg_reg);
8662 %}
8665 //-----------
8666 // Long to Double conversion using V8 opcodes.
8667 // Still useful because cheetah traps and becomes
8668 // amazingly slow for some common numbers.
8670 // Magic constant, 0x43300000
8671 instruct loadConI_x43300000(iRegI dst) %{
8672 effect(DEF dst);
8673 size(4);
8674 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8675 ins_encode(SetHi22(0x43300000, dst));
8676 ins_pipe(ialu_none);
8677 %}
8679 // Magic constant, 0x41f00000
8680 instruct loadConI_x41f00000(iRegI dst) %{
8681 effect(DEF dst);
8682 size(4);
8683 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8684 ins_encode(SetHi22(0x41f00000, dst));
8685 ins_pipe(ialu_none);
8686 %}
8688 // Construct a double from two float halves
8689 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8690 effect(DEF dst, USE src1, USE src2);
8691 size(8);
8692 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8693 "FMOVS $src2.lo,$dst.lo" %}
8694 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8695 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8696 ins_pipe(faddD_reg_reg);
8697 %}
8699 // Convert integer in high half of a double register (in the lower half of
8700 // the double register file) to double
8701 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8702 effect(DEF dst, USE src);
8703 size(4);
8704 format %{ "FITOD $src,$dst" %}
8705 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8706 ins_encode(form3_opf_rs2D_rdD(src, dst));
8707 ins_pipe(fcvtLHi2D);
8708 %}
8710 // Add float double precision
8711 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8712 effect(DEF dst, USE src1, USE src2);
8713 size(4);
8714 format %{ "FADDD $src1,$src2,$dst" %}
8715 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8716 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8717 ins_pipe(faddD_reg_reg);
8718 %}
8720 // Sub float double precision
8721 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8722 effect(DEF dst, USE src1, USE src2);
8723 size(4);
8724 format %{ "FSUBD $src1,$src2,$dst" %}
8725 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8726 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8727 ins_pipe(faddD_reg_reg);
8728 %}
8730 // Mul float double precision
8731 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8732 effect(DEF dst, USE src1, USE src2);
8733 size(4);
8734 format %{ "FMULD $src1,$src2,$dst" %}
8735 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8736 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8737 ins_pipe(fmulD_reg_reg);
8738 %}
8740 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8741 match(Set dst (ConvL2D src));
8742 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8744 expand %{
8745 regD_low tmpsrc;
8746 iRegI ix43300000;
8747 iRegI ix41f00000;
8748 stackSlotL lx43300000;
8749 stackSlotL lx41f00000;
8750 regD_low dx43300000;
8751 regD dx41f00000;
8752 regD tmp1;
8753 regD_low tmp2;
8754 regD tmp3;
8755 regD tmp4;
8757 stkL_to_regD(tmpsrc, src);
8759 loadConI_x43300000(ix43300000);
8760 loadConI_x41f00000(ix41f00000);
8761 regI_to_stkLHi(lx43300000, ix43300000);
8762 regI_to_stkLHi(lx41f00000, ix41f00000);
8763 stkL_to_regD(dx43300000, lx43300000);
8764 stkL_to_regD(dx41f00000, lx41f00000);
8766 convI2D_regDHi_regD(tmp1, tmpsrc);
8767 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8768 subD_regD_regD(tmp3, tmp2, dx43300000);
8769 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8770 addD_regD_regD(dst, tmp3, tmp4);
8771 %}
8772 %}
8774 // Long to Double conversion using fast fxtof
8775 instruct convL2D_helper(regD dst, regD tmp) %{
8776 effect(DEF dst, USE tmp);
8777 size(4);
8778 format %{ "FXTOD $tmp,$dst" %}
8779 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8780 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8781 ins_pipe(fcvtL2D);
8782 %}
8784 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8785 predicate(VM_Version::has_fast_fxtof());
8786 match(Set dst (ConvL2D src));
8787 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8788 expand %{
8789 regD tmp;
8790 stkL_to_regD(tmp, src);
8791 convL2D_helper(dst, tmp);
8792 %}
8793 %}
8795 instruct convL2D_reg(regD dst, iRegL src) %{
8796 predicate(UseVIS >= 3);
8797 match(Set dst (ConvL2D src));
8798 expand %{
8799 regD tmp;
8800 MoveL2D_reg_reg(tmp, src);
8801 convL2D_helper(dst, tmp);
8802 %}
8803 %}
8805 // Long to Float conversion using fast fxtof
8806 instruct convL2F_helper(regF dst, regD tmp) %{
8807 effect(DEF dst, USE tmp);
8808 size(4);
8809 format %{ "FXTOS $tmp,$dst" %}
8810 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8811 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8812 ins_pipe(fcvtL2F);
8813 %}
8815 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8816 match(Set dst (ConvL2F src));
8817 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8818 expand %{
8819 regD tmp;
8820 stkL_to_regD(tmp, src);
8821 convL2F_helper(dst, tmp);
8822 %}
8823 %}
8825 instruct convL2F_reg(regF dst, iRegL src) %{
8826 predicate(UseVIS >= 3);
8827 match(Set dst (ConvL2F src));
8828 ins_cost(DEFAULT_COST);
8829 expand %{
8830 regD tmp;
8831 MoveL2D_reg_reg(tmp, src);
8832 convL2F_helper(dst, tmp);
8833 %}
8834 %}
8836 //-----------
8838 instruct convL2I_reg(iRegI dst, iRegL src) %{
8839 match(Set dst (ConvL2I src));
8840 #ifndef _LP64
8841 format %{ "MOV $src.lo,$dst\t! long->int" %}
8842 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8843 ins_pipe(ialu_move_reg_I_to_L);
8844 #else
8845 size(4);
8846 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8847 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8848 ins_pipe(ialu_reg);
8849 #endif
8850 %}
8852 // Register Shift Right Immediate
8853 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8854 match(Set dst (ConvL2I (RShiftL src cnt)));
8856 size(4);
8857 format %{ "SRAX $src,$cnt,$dst" %}
8858 opcode(Assembler::srax_op3, Assembler::arith_op);
8859 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8860 ins_pipe(ialu_reg_imm);
8861 %}
8863 //----------Control Flow Instructions------------------------------------------
8864 // Compare Instructions
8865 // Compare Integers
8866 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8867 match(Set icc (CmpI op1 op2));
8868 effect( DEF icc, USE op1, USE op2 );
8870 size(4);
8871 format %{ "CMP $op1,$op2" %}
8872 opcode(Assembler::subcc_op3, Assembler::arith_op);
8873 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8874 ins_pipe(ialu_cconly_reg_reg);
8875 %}
8877 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8878 match(Set icc (CmpU op1 op2));
8880 size(4);
8881 format %{ "CMP $op1,$op2\t! unsigned" %}
8882 opcode(Assembler::subcc_op3, Assembler::arith_op);
8883 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8884 ins_pipe(ialu_cconly_reg_reg);
8885 %}
8887 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8888 match(Set icc (CmpI op1 op2));
8889 effect( DEF icc, USE op1 );
8891 size(4);
8892 format %{ "CMP $op1,$op2" %}
8893 opcode(Assembler::subcc_op3, Assembler::arith_op);
8894 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8895 ins_pipe(ialu_cconly_reg_imm);
8896 %}
8898 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8899 match(Set icc (CmpI (AndI op1 op2) zero));
8901 size(4);
8902 format %{ "BTST $op2,$op1" %}
8903 opcode(Assembler::andcc_op3, Assembler::arith_op);
8904 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8905 ins_pipe(ialu_cconly_reg_reg_zero);
8906 %}
8908 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8909 match(Set icc (CmpI (AndI op1 op2) zero));
8911 size(4);
8912 format %{ "BTST $op2,$op1" %}
8913 opcode(Assembler::andcc_op3, Assembler::arith_op);
8914 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8915 ins_pipe(ialu_cconly_reg_imm_zero);
8916 %}
8918 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8919 match(Set xcc (CmpL op1 op2));
8920 effect( DEF xcc, USE op1, USE op2 );
8922 size(4);
8923 format %{ "CMP $op1,$op2\t\t! long" %}
8924 opcode(Assembler::subcc_op3, Assembler::arith_op);
8925 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8926 ins_pipe(ialu_cconly_reg_reg);
8927 %}
8929 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8930 match(Set xcc (CmpL op1 con));
8931 effect( DEF xcc, USE op1, USE con );
8933 size(4);
8934 format %{ "CMP $op1,$con\t\t! long" %}
8935 opcode(Assembler::subcc_op3, Assembler::arith_op);
8936 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8937 ins_pipe(ialu_cconly_reg_reg);
8938 %}
8940 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8941 match(Set xcc (CmpL (AndL op1 op2) zero));
8942 effect( DEF xcc, USE op1, USE op2 );
8944 size(4);
8945 format %{ "BTST $op1,$op2\t\t! long" %}
8946 opcode(Assembler::andcc_op3, Assembler::arith_op);
8947 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8948 ins_pipe(ialu_cconly_reg_reg);
8949 %}
8951 // useful for checking the alignment of a pointer:
8952 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8953 match(Set xcc (CmpL (AndL op1 con) zero));
8954 effect( DEF xcc, USE op1, USE con );
8956 size(4);
8957 format %{ "BTST $op1,$con\t\t! long" %}
8958 opcode(Assembler::andcc_op3, Assembler::arith_op);
8959 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8960 ins_pipe(ialu_cconly_reg_reg);
8961 %}
8963 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8964 match(Set icc (CmpU op1 op2));
8966 size(4);
8967 format %{ "CMP $op1,$op2\t! unsigned" %}
8968 opcode(Assembler::subcc_op3, Assembler::arith_op);
8969 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8970 ins_pipe(ialu_cconly_reg_imm);
8971 %}
8973 // Compare Pointers
8974 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8975 match(Set pcc (CmpP op1 op2));
8977 size(4);
8978 format %{ "CMP $op1,$op2\t! ptr" %}
8979 opcode(Assembler::subcc_op3, Assembler::arith_op);
8980 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8981 ins_pipe(ialu_cconly_reg_reg);
8982 %}
8984 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8985 match(Set pcc (CmpP op1 op2));
8987 size(4);
8988 format %{ "CMP $op1,$op2\t! ptr" %}
8989 opcode(Assembler::subcc_op3, Assembler::arith_op);
8990 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8991 ins_pipe(ialu_cconly_reg_imm);
8992 %}
8994 // Compare Narrow oops
8995 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8996 match(Set icc (CmpN op1 op2));
8998 size(4);
8999 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9000 opcode(Assembler::subcc_op3, Assembler::arith_op);
9001 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9002 ins_pipe(ialu_cconly_reg_reg);
9003 %}
9005 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9006 match(Set icc (CmpN op1 op2));
9008 size(4);
9009 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9010 opcode(Assembler::subcc_op3, Assembler::arith_op);
9011 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9012 ins_pipe(ialu_cconly_reg_imm);
9013 %}
9015 //----------Max and Min--------------------------------------------------------
9016 // Min Instructions
9017 // Conditional move for min
9018 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9019 effect( USE_DEF op2, USE op1, USE icc );
9021 size(4);
9022 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9023 opcode(Assembler::less);
9024 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9025 ins_pipe(ialu_reg_flags);
9026 %}
9028 // Min Register with Register.
9029 instruct minI_eReg(iRegI op1, iRegI op2) %{
9030 match(Set op2 (MinI op1 op2));
9031 ins_cost(DEFAULT_COST*2);
9032 expand %{
9033 flagsReg icc;
9034 compI_iReg(icc,op1,op2);
9035 cmovI_reg_lt(op2,op1,icc);
9036 %}
9037 %}
9039 // Max Instructions
9040 // Conditional move for max
9041 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9042 effect( USE_DEF op2, USE op1, USE icc );
9043 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9044 opcode(Assembler::greater);
9045 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9046 ins_pipe(ialu_reg_flags);
9047 %}
9049 // Max Register with Register
9050 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9051 match(Set op2 (MaxI op1 op2));
9052 ins_cost(DEFAULT_COST*2);
9053 expand %{
9054 flagsReg icc;
9055 compI_iReg(icc,op1,op2);
9056 cmovI_reg_gt(op2,op1,icc);
9057 %}
9058 %}
9061 //----------Float Compares----------------------------------------------------
9062 // Compare floating, generate condition code
9063 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9064 match(Set fcc (CmpF src1 src2));
9066 size(4);
9067 format %{ "FCMPs $fcc,$src1,$src2" %}
9068 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9069 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9070 ins_pipe(faddF_fcc_reg_reg_zero);
9071 %}
9073 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9074 match(Set fcc (CmpD src1 src2));
9076 size(4);
9077 format %{ "FCMPd $fcc,$src1,$src2" %}
9078 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9079 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9080 ins_pipe(faddD_fcc_reg_reg_zero);
9081 %}
9084 // Compare floating, generate -1,0,1
9085 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9086 match(Set dst (CmpF3 src1 src2));
9087 effect(KILL fcc0);
9088 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9089 format %{ "fcmpl $dst,$src1,$src2" %}
9090 // Primary = float
9091 opcode( true );
9092 ins_encode( floating_cmp( dst, src1, src2 ) );
9093 ins_pipe( floating_cmp );
9094 %}
9096 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9097 match(Set dst (CmpD3 src1 src2));
9098 effect(KILL fcc0);
9099 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9100 format %{ "dcmpl $dst,$src1,$src2" %}
9101 // Primary = double (not float)
9102 opcode( false );
9103 ins_encode( floating_cmp( dst, src1, src2 ) );
9104 ins_pipe( floating_cmp );
9105 %}
9107 //----------Branches---------------------------------------------------------
9108 // Jump
9109 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9110 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9111 match(Jump switch_val);
9112 effect(TEMP table);
9114 ins_cost(350);
9116 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9117 "LD [O7 + $switch_val], O7\n\t"
9118 "JUMP O7" %}
9119 ins_encode %{
9120 // Calculate table address into a register.
9121 Register table_reg;
9122 Register label_reg = O7;
9123 // If we are calculating the size of this instruction don't trust
9124 // zero offsets because they might change when
9125 // MachConstantBaseNode decides to optimize the constant table
9126 // base.
9127 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9128 table_reg = $constanttablebase;
9129 } else {
9130 table_reg = O7;
9131 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9132 __ add($constanttablebase, con_offset, table_reg);
9133 }
9135 // Jump to base address + switch value
9136 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9137 __ jmp(label_reg, G0);
9138 __ delayed()->nop();
9139 %}
9140 ins_pipe(ialu_reg_reg);
9141 %}
9143 // Direct Branch. Use V8 version with longer range.
9144 instruct branch(label labl) %{
9145 match(Goto);
9146 effect(USE labl);
9148 size(8);
9149 ins_cost(BRANCH_COST);
9150 format %{ "BA $labl" %}
9151 ins_encode %{
9152 Label* L = $labl$$label;
9153 __ ba(*L);
9154 __ delayed()->nop();
9155 %}
9156 ins_pipe(br);
9157 %}
9159 // Direct Branch, short with no delay slot
9160 instruct branch_short(label labl) %{
9161 match(Goto);
9162 predicate(UseCBCond);
9163 effect(USE labl);
9165 size(4);
9166 ins_cost(BRANCH_COST);
9167 format %{ "BA $labl\t! short branch" %}
9168 ins_encode %{
9169 Label* L = $labl$$label;
9170 assert(__ use_cbcond(*L), "back to back cbcond");
9171 __ ba_short(*L);
9172 %}
9173 ins_short_branch(1);
9174 ins_avoid_back_to_back(1);
9175 ins_pipe(cbcond_reg_imm);
9176 %}
9178 // Conditional Direct Branch
9179 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9180 match(If cmp icc);
9181 effect(USE labl);
9183 size(8);
9184 ins_cost(BRANCH_COST);
9185 format %{ "BP$cmp $icc,$labl" %}
9186 // Prim = bits 24-22, Secnd = bits 31-30
9187 ins_encode( enc_bp( labl, cmp, icc ) );
9188 ins_pipe(br_cc);
9189 %}
9191 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9192 match(If cmp icc);
9193 effect(USE labl);
9195 ins_cost(BRANCH_COST);
9196 format %{ "BP$cmp $icc,$labl" %}
9197 // Prim = bits 24-22, Secnd = bits 31-30
9198 ins_encode( enc_bp( labl, cmp, icc ) );
9199 ins_pipe(br_cc);
9200 %}
9202 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9203 match(If cmp pcc);
9204 effect(USE labl);
9206 size(8);
9207 ins_cost(BRANCH_COST);
9208 format %{ "BP$cmp $pcc,$labl" %}
9209 ins_encode %{
9210 Label* L = $labl$$label;
9211 Assembler::Predict predict_taken =
9212 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9214 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9215 __ delayed()->nop();
9216 %}
9217 ins_pipe(br_cc);
9218 %}
9220 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9221 match(If cmp fcc);
9222 effect(USE labl);
9224 size(8);
9225 ins_cost(BRANCH_COST);
9226 format %{ "FBP$cmp $fcc,$labl" %}
9227 ins_encode %{
9228 Label* L = $labl$$label;
9229 Assembler::Predict predict_taken =
9230 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9232 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9233 __ delayed()->nop();
9234 %}
9235 ins_pipe(br_fcc);
9236 %}
9238 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9239 match(CountedLoopEnd cmp icc);
9240 effect(USE labl);
9242 size(8);
9243 ins_cost(BRANCH_COST);
9244 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9245 // Prim = bits 24-22, Secnd = bits 31-30
9246 ins_encode( enc_bp( labl, cmp, icc ) );
9247 ins_pipe(br_cc);
9248 %}
9250 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9251 match(CountedLoopEnd cmp icc);
9252 effect(USE labl);
9254 size(8);
9255 ins_cost(BRANCH_COST);
9256 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9257 // Prim = bits 24-22, Secnd = bits 31-30
9258 ins_encode( enc_bp( labl, cmp, icc ) );
9259 ins_pipe(br_cc);
9260 %}
9262 // Compare and branch instructions
9263 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9264 match(If cmp (CmpI op1 op2));
9265 effect(USE labl, KILL icc);
9267 size(12);
9268 ins_cost(BRANCH_COST);
9269 format %{ "CMP $op1,$op2\t! int\n\t"
9270 "BP$cmp $labl" %}
9271 ins_encode %{
9272 Label* L = $labl$$label;
9273 Assembler::Predict predict_taken =
9274 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9275 __ cmp($op1$$Register, $op2$$Register);
9276 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9277 __ delayed()->nop();
9278 %}
9279 ins_pipe(cmp_br_reg_reg);
9280 %}
9282 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9283 match(If cmp (CmpI op1 op2));
9284 effect(USE labl, KILL icc);
9286 size(12);
9287 ins_cost(BRANCH_COST);
9288 format %{ "CMP $op1,$op2\t! int\n\t"
9289 "BP$cmp $labl" %}
9290 ins_encode %{
9291 Label* L = $labl$$label;
9292 Assembler::Predict predict_taken =
9293 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9294 __ cmp($op1$$Register, $op2$$constant);
9295 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9296 __ delayed()->nop();
9297 %}
9298 ins_pipe(cmp_br_reg_imm);
9299 %}
9301 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9302 match(If cmp (CmpU op1 op2));
9303 effect(USE labl, KILL icc);
9305 size(12);
9306 ins_cost(BRANCH_COST);
9307 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9308 "BP$cmp $labl" %}
9309 ins_encode %{
9310 Label* L = $labl$$label;
9311 Assembler::Predict predict_taken =
9312 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9313 __ cmp($op1$$Register, $op2$$Register);
9314 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9315 __ delayed()->nop();
9316 %}
9317 ins_pipe(cmp_br_reg_reg);
9318 %}
9320 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9321 match(If cmp (CmpU op1 op2));
9322 effect(USE labl, KILL icc);
9324 size(12);
9325 ins_cost(BRANCH_COST);
9326 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9327 "BP$cmp $labl" %}
9328 ins_encode %{
9329 Label* L = $labl$$label;
9330 Assembler::Predict predict_taken =
9331 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9332 __ cmp($op1$$Register, $op2$$constant);
9333 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9334 __ delayed()->nop();
9335 %}
9336 ins_pipe(cmp_br_reg_imm);
9337 %}
9339 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9340 match(If cmp (CmpL op1 op2));
9341 effect(USE labl, KILL xcc);
9343 size(12);
9344 ins_cost(BRANCH_COST);
9345 format %{ "CMP $op1,$op2\t! long\n\t"
9346 "BP$cmp $labl" %}
9347 ins_encode %{
9348 Label* L = $labl$$label;
9349 Assembler::Predict predict_taken =
9350 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9351 __ cmp($op1$$Register, $op2$$Register);
9352 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9353 __ delayed()->nop();
9354 %}
9355 ins_pipe(cmp_br_reg_reg);
9356 %}
9358 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9359 match(If cmp (CmpL op1 op2));
9360 effect(USE labl, KILL xcc);
9362 size(12);
9363 ins_cost(BRANCH_COST);
9364 format %{ "CMP $op1,$op2\t! long\n\t"
9365 "BP$cmp $labl" %}
9366 ins_encode %{
9367 Label* L = $labl$$label;
9368 Assembler::Predict predict_taken =
9369 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9370 __ cmp($op1$$Register, $op2$$constant);
9371 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9372 __ delayed()->nop();
9373 %}
9374 ins_pipe(cmp_br_reg_imm);
9375 %}
9377 // Compare Pointers and branch
9378 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9379 match(If cmp (CmpP op1 op2));
9380 effect(USE labl, KILL pcc);
9382 size(12);
9383 ins_cost(BRANCH_COST);
9384 format %{ "CMP $op1,$op2\t! ptr\n\t"
9385 "B$cmp $labl" %}
9386 ins_encode %{
9387 Label* L = $labl$$label;
9388 Assembler::Predict predict_taken =
9389 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9390 __ cmp($op1$$Register, $op2$$Register);
9391 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9392 __ delayed()->nop();
9393 %}
9394 ins_pipe(cmp_br_reg_reg);
9395 %}
9397 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9398 match(If cmp (CmpP op1 null));
9399 effect(USE labl, KILL pcc);
9401 size(12);
9402 ins_cost(BRANCH_COST);
9403 format %{ "CMP $op1,0\t! ptr\n\t"
9404 "B$cmp $labl" %}
9405 ins_encode %{
9406 Label* L = $labl$$label;
9407 Assembler::Predict predict_taken =
9408 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9409 __ cmp($op1$$Register, G0);
9410 // bpr() is not used here since it has shorter distance.
9411 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9412 __ delayed()->nop();
9413 %}
9414 ins_pipe(cmp_br_reg_reg);
9415 %}
9417 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9418 match(If cmp (CmpN op1 op2));
9419 effect(USE labl, KILL icc);
9421 size(12);
9422 ins_cost(BRANCH_COST);
9423 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9424 "BP$cmp $labl" %}
9425 ins_encode %{
9426 Label* L = $labl$$label;
9427 Assembler::Predict predict_taken =
9428 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9429 __ cmp($op1$$Register, $op2$$Register);
9430 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9431 __ delayed()->nop();
9432 %}
9433 ins_pipe(cmp_br_reg_reg);
9434 %}
9436 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9437 match(If cmp (CmpN op1 null));
9438 effect(USE labl, KILL icc);
9440 size(12);
9441 ins_cost(BRANCH_COST);
9442 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9443 "BP$cmp $labl" %}
9444 ins_encode %{
9445 Label* L = $labl$$label;
9446 Assembler::Predict predict_taken =
9447 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9448 __ cmp($op1$$Register, G0);
9449 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9450 __ delayed()->nop();
9451 %}
9452 ins_pipe(cmp_br_reg_reg);
9453 %}
9455 // Loop back branch
9456 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9457 match(CountedLoopEnd cmp (CmpI op1 op2));
9458 effect(USE labl, KILL icc);
9460 size(12);
9461 ins_cost(BRANCH_COST);
9462 format %{ "CMP $op1,$op2\t! int\n\t"
9463 "BP$cmp $labl\t! Loop end" %}
9464 ins_encode %{
9465 Label* L = $labl$$label;
9466 Assembler::Predict predict_taken =
9467 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9468 __ cmp($op1$$Register, $op2$$Register);
9469 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9470 __ delayed()->nop();
9471 %}
9472 ins_pipe(cmp_br_reg_reg);
9473 %}
9475 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9476 match(CountedLoopEnd cmp (CmpI op1 op2));
9477 effect(USE labl, KILL icc);
9479 size(12);
9480 ins_cost(BRANCH_COST);
9481 format %{ "CMP $op1,$op2\t! int\n\t"
9482 "BP$cmp $labl\t! Loop end" %}
9483 ins_encode %{
9484 Label* L = $labl$$label;
9485 Assembler::Predict predict_taken =
9486 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9487 __ cmp($op1$$Register, $op2$$constant);
9488 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9489 __ delayed()->nop();
9490 %}
9491 ins_pipe(cmp_br_reg_imm);
9492 %}
9494 // Short compare and branch instructions
9495 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9496 match(If cmp (CmpI op1 op2));
9497 predicate(UseCBCond);
9498 effect(USE labl, KILL icc);
9500 size(4);
9501 ins_cost(BRANCH_COST);
9502 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9503 ins_encode %{
9504 Label* L = $labl$$label;
9505 assert(__ use_cbcond(*L), "back to back cbcond");
9506 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9507 %}
9508 ins_short_branch(1);
9509 ins_avoid_back_to_back(1);
9510 ins_pipe(cbcond_reg_reg);
9511 %}
9513 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9514 match(If cmp (CmpI op1 op2));
9515 predicate(UseCBCond);
9516 effect(USE labl, KILL icc);
9518 size(4);
9519 ins_cost(BRANCH_COST);
9520 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9521 ins_encode %{
9522 Label* L = $labl$$label;
9523 assert(__ use_cbcond(*L), "back to back cbcond");
9524 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9525 %}
9526 ins_short_branch(1);
9527 ins_avoid_back_to_back(1);
9528 ins_pipe(cbcond_reg_imm);
9529 %}
9531 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9532 match(If cmp (CmpU op1 op2));
9533 predicate(UseCBCond);
9534 effect(USE labl, KILL icc);
9536 size(4);
9537 ins_cost(BRANCH_COST);
9538 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9539 ins_encode %{
9540 Label* L = $labl$$label;
9541 assert(__ use_cbcond(*L), "back to back cbcond");
9542 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9543 %}
9544 ins_short_branch(1);
9545 ins_avoid_back_to_back(1);
9546 ins_pipe(cbcond_reg_reg);
9547 %}
9549 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9550 match(If cmp (CmpU op1 op2));
9551 predicate(UseCBCond);
9552 effect(USE labl, KILL icc);
9554 size(4);
9555 ins_cost(BRANCH_COST);
9556 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9557 ins_encode %{
9558 Label* L = $labl$$label;
9559 assert(__ use_cbcond(*L), "back to back cbcond");
9560 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9561 %}
9562 ins_short_branch(1);
9563 ins_avoid_back_to_back(1);
9564 ins_pipe(cbcond_reg_imm);
9565 %}
9567 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9568 match(If cmp (CmpL op1 op2));
9569 predicate(UseCBCond);
9570 effect(USE labl, KILL xcc);
9572 size(4);
9573 ins_cost(BRANCH_COST);
9574 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9575 ins_encode %{
9576 Label* L = $labl$$label;
9577 assert(__ use_cbcond(*L), "back to back cbcond");
9578 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9579 %}
9580 ins_short_branch(1);
9581 ins_avoid_back_to_back(1);
9582 ins_pipe(cbcond_reg_reg);
9583 %}
9585 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9586 match(If cmp (CmpL op1 op2));
9587 predicate(UseCBCond);
9588 effect(USE labl, KILL xcc);
9590 size(4);
9591 ins_cost(BRANCH_COST);
9592 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9593 ins_encode %{
9594 Label* L = $labl$$label;
9595 assert(__ use_cbcond(*L), "back to back cbcond");
9596 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9597 %}
9598 ins_short_branch(1);
9599 ins_avoid_back_to_back(1);
9600 ins_pipe(cbcond_reg_imm);
9601 %}
9603 // Compare Pointers and branch
9604 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9605 match(If cmp (CmpP op1 op2));
9606 predicate(UseCBCond);
9607 effect(USE labl, KILL pcc);
9609 size(4);
9610 ins_cost(BRANCH_COST);
9611 #ifdef _LP64
9612 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9613 #else
9614 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9615 #endif
9616 ins_encode %{
9617 Label* L = $labl$$label;
9618 assert(__ use_cbcond(*L), "back to back cbcond");
9619 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9620 %}
9621 ins_short_branch(1);
9622 ins_avoid_back_to_back(1);
9623 ins_pipe(cbcond_reg_reg);
9624 %}
9626 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9627 match(If cmp (CmpP op1 null));
9628 predicate(UseCBCond);
9629 effect(USE labl, KILL pcc);
9631 size(4);
9632 ins_cost(BRANCH_COST);
9633 #ifdef _LP64
9634 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9635 #else
9636 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9637 #endif
9638 ins_encode %{
9639 Label* L = $labl$$label;
9640 assert(__ use_cbcond(*L), "back to back cbcond");
9641 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9642 %}
9643 ins_short_branch(1);
9644 ins_avoid_back_to_back(1);
9645 ins_pipe(cbcond_reg_reg);
9646 %}
9648 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9649 match(If cmp (CmpN op1 op2));
9650 predicate(UseCBCond);
9651 effect(USE labl, KILL icc);
9653 size(4);
9654 ins_cost(BRANCH_COST);
9655 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9656 ins_encode %{
9657 Label* L = $labl$$label;
9658 assert(__ use_cbcond(*L), "back to back cbcond");
9659 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9660 %}
9661 ins_short_branch(1);
9662 ins_avoid_back_to_back(1);
9663 ins_pipe(cbcond_reg_reg);
9664 %}
9666 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9667 match(If cmp (CmpN op1 null));
9668 predicate(UseCBCond);
9669 effect(USE labl, KILL icc);
9671 size(4);
9672 ins_cost(BRANCH_COST);
9673 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9674 ins_encode %{
9675 Label* L = $labl$$label;
9676 assert(__ use_cbcond(*L), "back to back cbcond");
9677 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9678 %}
9679 ins_short_branch(1);
9680 ins_avoid_back_to_back(1);
9681 ins_pipe(cbcond_reg_reg);
9682 %}
9684 // Loop back branch
9685 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9686 match(CountedLoopEnd cmp (CmpI op1 op2));
9687 predicate(UseCBCond);
9688 effect(USE labl, KILL icc);
9690 size(4);
9691 ins_cost(BRANCH_COST);
9692 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9693 ins_encode %{
9694 Label* L = $labl$$label;
9695 assert(__ use_cbcond(*L), "back to back cbcond");
9696 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9697 %}
9698 ins_short_branch(1);
9699 ins_avoid_back_to_back(1);
9700 ins_pipe(cbcond_reg_reg);
9701 %}
9703 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9704 match(CountedLoopEnd cmp (CmpI op1 op2));
9705 predicate(UseCBCond);
9706 effect(USE labl, KILL icc);
9708 size(4);
9709 ins_cost(BRANCH_COST);
9710 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9711 ins_encode %{
9712 Label* L = $labl$$label;
9713 assert(__ use_cbcond(*L), "back to back cbcond");
9714 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9715 %}
9716 ins_short_branch(1);
9717 ins_avoid_back_to_back(1);
9718 ins_pipe(cbcond_reg_imm);
9719 %}
9721 // Branch-on-register tests all 64 bits. We assume that values
9722 // in 64-bit registers always remains zero or sign extended
9723 // unless our code munges the high bits. Interrupts can chop
9724 // the high order bits to zero or sign at any time.
9725 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9726 match(If cmp (CmpI op1 zero));
9727 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9728 effect(USE labl);
9730 size(8);
9731 ins_cost(BRANCH_COST);
9732 format %{ "BR$cmp $op1,$labl" %}
9733 ins_encode( enc_bpr( labl, cmp, op1 ) );
9734 ins_pipe(br_reg);
9735 %}
9737 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9738 match(If cmp (CmpP op1 null));
9739 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9740 effect(USE labl);
9742 size(8);
9743 ins_cost(BRANCH_COST);
9744 format %{ "BR$cmp $op1,$labl" %}
9745 ins_encode( enc_bpr( labl, cmp, op1 ) );
9746 ins_pipe(br_reg);
9747 %}
9749 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9750 match(If cmp (CmpL op1 zero));
9751 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9752 effect(USE labl);
9754 size(8);
9755 ins_cost(BRANCH_COST);
9756 format %{ "BR$cmp $op1,$labl" %}
9757 ins_encode( enc_bpr( labl, cmp, op1 ) );
9758 ins_pipe(br_reg);
9759 %}
9762 // ============================================================================
9763 // Long Compare
9764 //
9765 // Currently we hold longs in 2 registers. Comparing such values efficiently
9766 // is tricky. The flavor of compare used depends on whether we are testing
9767 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9768 // The GE test is the negated LT test. The LE test can be had by commuting
9769 // the operands (yielding a GE test) and then negating; negate again for the
9770 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9771 // NE test is negated from that.
9773 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9774 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9775 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9776 // are collapsed internally in the ADLC's dfa-gen code. The match for
9777 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9778 // foo match ends up with the wrong leaf. One fix is to not match both
9779 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9780 // both forms beat the trinary form of long-compare and both are very useful
9781 // on Intel which has so few registers.
9783 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9784 match(If cmp xcc);
9785 effect(USE labl);
9787 size(8);
9788 ins_cost(BRANCH_COST);
9789 format %{ "BP$cmp $xcc,$labl" %}
9790 ins_encode %{
9791 Label* L = $labl$$label;
9792 Assembler::Predict predict_taken =
9793 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9795 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9796 __ delayed()->nop();
9797 %}
9798 ins_pipe(br_cc);
9799 %}
9801 // Manifest a CmpL3 result in an integer register. Very painful.
9802 // This is the test to avoid.
9803 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9804 match(Set dst (CmpL3 src1 src2) );
9805 effect( KILL ccr );
9806 ins_cost(6*DEFAULT_COST);
9807 size(24);
9808 format %{ "CMP $src1,$src2\t\t! long\n"
9809 "\tBLT,a,pn done\n"
9810 "\tMOV -1,$dst\t! delay slot\n"
9811 "\tBGT,a,pn done\n"
9812 "\tMOV 1,$dst\t! delay slot\n"
9813 "\tCLR $dst\n"
9814 "done:" %}
9815 ins_encode( cmpl_flag(src1,src2,dst) );
9816 ins_pipe(cmpL_reg);
9817 %}
9819 // Conditional move
9820 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9821 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9822 ins_cost(150);
9823 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9824 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9825 ins_pipe(ialu_reg);
9826 %}
9828 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9829 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9830 ins_cost(140);
9831 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9832 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9833 ins_pipe(ialu_imm);
9834 %}
9836 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9837 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9838 ins_cost(150);
9839 format %{ "MOV$cmp $xcc,$src,$dst" %}
9840 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9841 ins_pipe(ialu_reg);
9842 %}
9844 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9845 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9846 ins_cost(140);
9847 format %{ "MOV$cmp $xcc,$src,$dst" %}
9848 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9849 ins_pipe(ialu_imm);
9850 %}
9852 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9853 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9854 ins_cost(150);
9855 format %{ "MOV$cmp $xcc,$src,$dst" %}
9856 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9857 ins_pipe(ialu_reg);
9858 %}
9860 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9861 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9862 ins_cost(150);
9863 format %{ "MOV$cmp $xcc,$src,$dst" %}
9864 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9865 ins_pipe(ialu_reg);
9866 %}
9868 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9869 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9870 ins_cost(140);
9871 format %{ "MOV$cmp $xcc,$src,$dst" %}
9872 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9873 ins_pipe(ialu_imm);
9874 %}
9876 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9877 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9878 ins_cost(150);
9879 opcode(0x101);
9880 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9881 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9882 ins_pipe(int_conditional_float_move);
9883 %}
9885 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9886 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9887 ins_cost(150);
9888 opcode(0x102);
9889 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9890 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9891 ins_pipe(int_conditional_float_move);
9892 %}
9894 // ============================================================================
9895 // Safepoint Instruction
9896 instruct safePoint_poll(iRegP poll) %{
9897 match(SafePoint poll);
9898 effect(USE poll);
9900 size(4);
9901 #ifdef _LP64
9902 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9903 #else
9904 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9905 #endif
9906 ins_encode %{
9907 __ relocate(relocInfo::poll_type);
9908 __ ld_ptr($poll$$Register, 0, G0);
9909 %}
9910 ins_pipe(loadPollP);
9911 %}
9913 // ============================================================================
9914 // Call Instructions
9915 // Call Java Static Instruction
9916 instruct CallStaticJavaDirect( method meth ) %{
9917 match(CallStaticJava);
9918 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9919 effect(USE meth);
9921 size(8);
9922 ins_cost(CALL_COST);
9923 format %{ "CALL,static ; NOP ==> " %}
9924 ins_encode( Java_Static_Call( meth ), call_epilog );
9925 ins_pipe(simple_call);
9926 %}
9928 // Call Java Static Instruction (method handle version)
9929 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9930 match(CallStaticJava);
9931 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9932 effect(USE meth, KILL l7_mh_SP_save);
9934 size(16);
9935 ins_cost(CALL_COST);
9936 format %{ "CALL,static/MethodHandle" %}
9937 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9938 ins_pipe(simple_call);
9939 %}
9941 // Call Java Dynamic Instruction
9942 instruct CallDynamicJavaDirect( method meth ) %{
9943 match(CallDynamicJava);
9944 effect(USE meth);
9946 ins_cost(CALL_COST);
9947 format %{ "SET (empty),R_G5\n\t"
9948 "CALL,dynamic ; NOP ==> " %}
9949 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9950 ins_pipe(call);
9951 %}
9953 // Call Runtime Instruction
9954 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9955 match(CallRuntime);
9956 effect(USE meth, KILL l7);
9957 ins_cost(CALL_COST);
9958 format %{ "CALL,runtime" %}
9959 ins_encode( Java_To_Runtime( meth ),
9960 call_epilog, adjust_long_from_native_call );
9961 ins_pipe(simple_call);
9962 %}
9964 // Call runtime without safepoint - same as CallRuntime
9965 instruct CallLeafDirect(method meth, l7RegP l7) %{
9966 match(CallLeaf);
9967 effect(USE meth, KILL l7);
9968 ins_cost(CALL_COST);
9969 format %{ "CALL,runtime leaf" %}
9970 ins_encode( Java_To_Runtime( meth ),
9971 call_epilog,
9972 adjust_long_from_native_call );
9973 ins_pipe(simple_call);
9974 %}
9976 // Call runtime without safepoint - same as CallLeaf
9977 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9978 match(CallLeafNoFP);
9979 effect(USE meth, KILL l7);
9980 ins_cost(CALL_COST);
9981 format %{ "CALL,runtime leaf nofp" %}
9982 ins_encode( Java_To_Runtime( meth ),
9983 call_epilog,
9984 adjust_long_from_native_call );
9985 ins_pipe(simple_call);
9986 %}
9988 // Tail Call; Jump from runtime stub to Java code.
9989 // Also known as an 'interprocedural jump'.
9990 // Target of jump will eventually return to caller.
9991 // TailJump below removes the return address.
9992 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9993 match(TailCall jump_target method_oop );
9995 ins_cost(CALL_COST);
9996 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9997 ins_encode(form_jmpl(jump_target));
9998 ins_pipe(tail_call);
9999 %}
10002 // Return Instruction
10003 instruct Ret() %{
10004 match(Return);
10006 // The epilogue node did the ret already.
10007 size(0);
10008 format %{ "! return" %}
10009 ins_encode();
10010 ins_pipe(empty);
10011 %}
10014 // Tail Jump; remove the return address; jump to target.
10015 // TailCall above leaves the return address around.
10016 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10017 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10018 // "restore" before this instruction (in Epilogue), we need to materialize it
10019 // in %i0.
10020 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10021 match( TailJump jump_target ex_oop );
10022 ins_cost(CALL_COST);
10023 format %{ "! discard R_O7\n\t"
10024 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10025 ins_encode(form_jmpl_set_exception_pc(jump_target));
10026 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10027 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10028 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10029 ins_pipe(tail_call);
10030 %}
10032 // Create exception oop: created by stack-crawling runtime code.
10033 // Created exception is now available to this handler, and is setup
10034 // just prior to jumping to this handler. No code emitted.
10035 instruct CreateException( o0RegP ex_oop )
10036 %{
10037 match(Set ex_oop (CreateEx));
10038 ins_cost(0);
10040 size(0);
10041 // use the following format syntax
10042 format %{ "! exception oop is in R_O0; no code emitted" %}
10043 ins_encode();
10044 ins_pipe(empty);
10045 %}
10048 // Rethrow exception:
10049 // The exception oop will come in the first argument position.
10050 // Then JUMP (not call) to the rethrow stub code.
10051 instruct RethrowException()
10052 %{
10053 match(Rethrow);
10054 ins_cost(CALL_COST);
10056 // use the following format syntax
10057 format %{ "Jmp rethrow_stub" %}
10058 ins_encode(enc_rethrow);
10059 ins_pipe(tail_call);
10060 %}
10063 // Die now
10064 instruct ShouldNotReachHere( )
10065 %{
10066 match(Halt);
10067 ins_cost(CALL_COST);
10069 size(4);
10070 // Use the following format syntax
10071 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10072 ins_encode( form2_illtrap() );
10073 ins_pipe(tail_call);
10074 %}
10076 // ============================================================================
10077 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10078 // array for an instance of the superklass. Set a hidden internal cache on a
10079 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10080 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10081 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10082 match(Set index (PartialSubtypeCheck sub super));
10083 effect( KILL pcc, KILL o7 );
10084 ins_cost(DEFAULT_COST*10);
10085 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10086 ins_encode( enc_PartialSubtypeCheck() );
10087 ins_pipe(partial_subtype_check_pipe);
10088 %}
10090 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10091 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10092 effect( KILL idx, KILL o7 );
10093 ins_cost(DEFAULT_COST*10);
10094 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10095 ins_encode( enc_PartialSubtypeCheck() );
10096 ins_pipe(partial_subtype_check_pipe);
10097 %}
10100 // ============================================================================
10101 // inlined locking and unlocking
10103 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10104 match(Set pcc (FastLock object box));
10106 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10107 ins_cost(100);
10109 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10110 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10111 ins_pipe(long_memory_op);
10112 %}
10115 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10116 match(Set pcc (FastUnlock object box));
10117 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10118 ins_cost(100);
10120 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10121 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10122 ins_pipe(long_memory_op);
10123 %}
10125 // The encodings are generic.
10126 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10127 predicate(!use_block_zeroing(n->in(2)) );
10128 match(Set dummy (ClearArray cnt base));
10129 effect(TEMP temp, KILL ccr);
10130 ins_cost(300);
10131 format %{ "MOV $cnt,$temp\n"
10132 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10133 " BRge loop\t\t! Clearing loop\n"
10134 " STX G0,[$base+$temp]\t! delay slot" %}
10136 ins_encode %{
10137 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10138 Register nof_bytes_arg = $cnt$$Register;
10139 Register nof_bytes_tmp = $temp$$Register;
10140 Register base_pointer_arg = $base$$Register;
10142 Label loop;
10143 __ mov(nof_bytes_arg, nof_bytes_tmp);
10145 // Loop and clear, walking backwards through the array.
10146 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10147 __ bind(loop);
10148 __ deccc(nof_bytes_tmp, 8);
10149 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10150 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10151 // %%%% this mini-loop must not cross a cache boundary!
10152 %}
10153 ins_pipe(long_memory_op);
10154 %}
10156 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10157 predicate(use_block_zeroing(n->in(2)));
10158 match(Set dummy (ClearArray cnt base));
10159 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10160 ins_cost(300);
10161 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10163 ins_encode %{
10165 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10166 Register to = $base$$Register;
10167 Register count = $cnt$$Register;
10169 Label Ldone;
10170 __ nop(); // Separate short branches
10171 // Use BIS for zeroing (temp is not used).
10172 __ bis_zeroing(to, count, G0, Ldone);
10173 __ bind(Ldone);
10175 %}
10176 ins_pipe(long_memory_op);
10177 %}
10179 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10180 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10181 match(Set dummy (ClearArray cnt base));
10182 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10183 ins_cost(300);
10184 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10186 ins_encode %{
10188 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10189 Register to = $base$$Register;
10190 Register count = $cnt$$Register;
10191 Register temp = $tmp$$Register;
10193 Label Ldone;
10194 __ nop(); // Separate short branches
10195 // Use BIS for zeroing
10196 __ bis_zeroing(to, count, temp, Ldone);
10197 __ bind(Ldone);
10199 %}
10200 ins_pipe(long_memory_op);
10201 %}
10203 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10204 o7RegI tmp, flagsReg ccr) %{
10205 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10206 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10207 ins_cost(300);
10208 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10209 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10210 ins_pipe(long_memory_op);
10211 %}
10213 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10214 o7RegI tmp, flagsReg ccr) %{
10215 match(Set result (StrEquals (Binary str1 str2) cnt));
10216 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10217 ins_cost(300);
10218 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10219 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10220 ins_pipe(long_memory_op);
10221 %}
10223 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10224 o7RegI tmp2, flagsReg ccr) %{
10225 match(Set result (AryEq ary1 ary2));
10226 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10227 ins_cost(300);
10228 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10229 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10230 ins_pipe(long_memory_op);
10231 %}
10234 //---------- Zeros Count Instructions ------------------------------------------
10236 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10237 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10238 match(Set dst (CountLeadingZerosI src));
10239 effect(TEMP dst, TEMP tmp, KILL cr);
10241 // x |= (x >> 1);
10242 // x |= (x >> 2);
10243 // x |= (x >> 4);
10244 // x |= (x >> 8);
10245 // x |= (x >> 16);
10246 // return (WORDBITS - popc(x));
10247 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10248 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10249 "OR $dst,$tmp,$dst\n\t"
10250 "SRL $dst,2,$tmp\n\t"
10251 "OR $dst,$tmp,$dst\n\t"
10252 "SRL $dst,4,$tmp\n\t"
10253 "OR $dst,$tmp,$dst\n\t"
10254 "SRL $dst,8,$tmp\n\t"
10255 "OR $dst,$tmp,$dst\n\t"
10256 "SRL $dst,16,$tmp\n\t"
10257 "OR $dst,$tmp,$dst\n\t"
10258 "POPC $dst,$dst\n\t"
10259 "MOV 32,$tmp\n\t"
10260 "SUB $tmp,$dst,$dst" %}
10261 ins_encode %{
10262 Register Rdst = $dst$$Register;
10263 Register Rsrc = $src$$Register;
10264 Register Rtmp = $tmp$$Register;
10265 __ srl(Rsrc, 1, Rtmp);
10266 __ srl(Rsrc, 0, Rdst);
10267 __ or3(Rdst, Rtmp, Rdst);
10268 __ srl(Rdst, 2, Rtmp);
10269 __ or3(Rdst, Rtmp, Rdst);
10270 __ srl(Rdst, 4, Rtmp);
10271 __ or3(Rdst, Rtmp, Rdst);
10272 __ srl(Rdst, 8, Rtmp);
10273 __ or3(Rdst, Rtmp, Rdst);
10274 __ srl(Rdst, 16, Rtmp);
10275 __ or3(Rdst, Rtmp, Rdst);
10276 __ popc(Rdst, Rdst);
10277 __ mov(BitsPerInt, Rtmp);
10278 __ sub(Rtmp, Rdst, Rdst);
10279 %}
10280 ins_pipe(ialu_reg);
10281 %}
10283 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10284 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10285 match(Set dst (CountLeadingZerosL src));
10286 effect(TEMP dst, TEMP tmp, KILL cr);
10288 // x |= (x >> 1);
10289 // x |= (x >> 2);
10290 // x |= (x >> 4);
10291 // x |= (x >> 8);
10292 // x |= (x >> 16);
10293 // x |= (x >> 32);
10294 // return (WORDBITS - popc(x));
10295 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10296 "OR $src,$tmp,$dst\n\t"
10297 "SRLX $dst,2,$tmp\n\t"
10298 "OR $dst,$tmp,$dst\n\t"
10299 "SRLX $dst,4,$tmp\n\t"
10300 "OR $dst,$tmp,$dst\n\t"
10301 "SRLX $dst,8,$tmp\n\t"
10302 "OR $dst,$tmp,$dst\n\t"
10303 "SRLX $dst,16,$tmp\n\t"
10304 "OR $dst,$tmp,$dst\n\t"
10305 "SRLX $dst,32,$tmp\n\t"
10306 "OR $dst,$tmp,$dst\n\t"
10307 "POPC $dst,$dst\n\t"
10308 "MOV 64,$tmp\n\t"
10309 "SUB $tmp,$dst,$dst" %}
10310 ins_encode %{
10311 Register Rdst = $dst$$Register;
10312 Register Rsrc = $src$$Register;
10313 Register Rtmp = $tmp$$Register;
10314 __ srlx(Rsrc, 1, Rtmp);
10315 __ or3( Rsrc, Rtmp, Rdst);
10316 __ srlx(Rdst, 2, Rtmp);
10317 __ or3( Rdst, Rtmp, Rdst);
10318 __ srlx(Rdst, 4, Rtmp);
10319 __ or3( Rdst, Rtmp, Rdst);
10320 __ srlx(Rdst, 8, Rtmp);
10321 __ or3( Rdst, Rtmp, Rdst);
10322 __ srlx(Rdst, 16, Rtmp);
10323 __ or3( Rdst, Rtmp, Rdst);
10324 __ srlx(Rdst, 32, Rtmp);
10325 __ or3( Rdst, Rtmp, Rdst);
10326 __ popc(Rdst, Rdst);
10327 __ mov(BitsPerLong, Rtmp);
10328 __ sub(Rtmp, Rdst, Rdst);
10329 %}
10330 ins_pipe(ialu_reg);
10331 %}
10333 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10334 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10335 match(Set dst (CountTrailingZerosI src));
10336 effect(TEMP dst, KILL cr);
10338 // return popc(~x & (x - 1));
10339 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10340 "ANDN $dst,$src,$dst\n\t"
10341 "SRL $dst,R_G0,$dst\n\t"
10342 "POPC $dst,$dst" %}
10343 ins_encode %{
10344 Register Rdst = $dst$$Register;
10345 Register Rsrc = $src$$Register;
10346 __ sub(Rsrc, 1, Rdst);
10347 __ andn(Rdst, Rsrc, Rdst);
10348 __ srl(Rdst, G0, Rdst);
10349 __ popc(Rdst, Rdst);
10350 %}
10351 ins_pipe(ialu_reg);
10352 %}
10354 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10355 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10356 match(Set dst (CountTrailingZerosL src));
10357 effect(TEMP dst, KILL cr);
10359 // return popc(~x & (x - 1));
10360 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10361 "ANDN $dst,$src,$dst\n\t"
10362 "POPC $dst,$dst" %}
10363 ins_encode %{
10364 Register Rdst = $dst$$Register;
10365 Register Rsrc = $src$$Register;
10366 __ sub(Rsrc, 1, Rdst);
10367 __ andn(Rdst, Rsrc, Rdst);
10368 __ popc(Rdst, Rdst);
10369 %}
10370 ins_pipe(ialu_reg);
10371 %}
10374 //---------- Population Count Instructions -------------------------------------
10376 instruct popCountI(iRegIsafe dst, iRegI src) %{
10377 predicate(UsePopCountInstruction);
10378 match(Set dst (PopCountI src));
10380 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10381 "POPC $dst, $dst" %}
10382 ins_encode %{
10383 __ srl($src$$Register, G0, $dst$$Register);
10384 __ popc($dst$$Register, $dst$$Register);
10385 %}
10386 ins_pipe(ialu_reg);
10387 %}
10389 // Note: Long.bitCount(long) returns an int.
10390 instruct popCountL(iRegIsafe dst, iRegL src) %{
10391 predicate(UsePopCountInstruction);
10392 match(Set dst (PopCountL src));
10394 format %{ "POPC $src, $dst" %}
10395 ins_encode %{
10396 __ popc($src$$Register, $dst$$Register);
10397 %}
10398 ins_pipe(ialu_reg);
10399 %}
10402 // ============================================================================
10403 //------------Bytes reverse--------------------------------------------------
10405 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10406 match(Set dst (ReverseBytesI src));
10408 // Op cost is artificially doubled to make sure that load or store
10409 // instructions are preferred over this one which requires a spill
10410 // onto a stack slot.
10411 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10412 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10414 ins_encode %{
10415 __ set($src$$disp + STACK_BIAS, O7);
10416 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10417 %}
10418 ins_pipe( iload_mem );
10419 %}
10421 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10422 match(Set dst (ReverseBytesL src));
10424 // Op cost is artificially doubled to make sure that load or store
10425 // instructions are preferred over this one which requires a spill
10426 // onto a stack slot.
10427 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10428 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10430 ins_encode %{
10431 __ set($src$$disp + STACK_BIAS, O7);
10432 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10433 %}
10434 ins_pipe( iload_mem );
10435 %}
10437 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10438 match(Set dst (ReverseBytesUS src));
10440 // Op cost is artificially doubled to make sure that load or store
10441 // instructions are preferred over this one which requires a spill
10442 // onto a stack slot.
10443 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10444 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10446 ins_encode %{
10447 // the value was spilled as an int so bias the load
10448 __ set($src$$disp + STACK_BIAS + 2, O7);
10449 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10450 %}
10451 ins_pipe( iload_mem );
10452 %}
10454 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10455 match(Set dst (ReverseBytesS src));
10457 // Op cost is artificially doubled to make sure that load or store
10458 // instructions are preferred over this one which requires a spill
10459 // onto a stack slot.
10460 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10461 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10463 ins_encode %{
10464 // the value was spilled as an int so bias the load
10465 __ set($src$$disp + STACK_BIAS + 2, O7);
10466 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10467 %}
10468 ins_pipe( iload_mem );
10469 %}
10471 // Load Integer reversed byte order
10472 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10473 match(Set dst (ReverseBytesI (LoadI src)));
10475 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10476 size(4);
10477 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10479 ins_encode %{
10480 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10481 %}
10482 ins_pipe(iload_mem);
10483 %}
10485 // Load Long - aligned and reversed
10486 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10487 match(Set dst (ReverseBytesL (LoadL src)));
10489 ins_cost(MEMORY_REF_COST);
10490 size(4);
10491 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10493 ins_encode %{
10494 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10495 %}
10496 ins_pipe(iload_mem);
10497 %}
10499 // Load unsigned short / char reversed byte order
10500 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10501 match(Set dst (ReverseBytesUS (LoadUS src)));
10503 ins_cost(MEMORY_REF_COST);
10504 size(4);
10505 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10507 ins_encode %{
10508 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10509 %}
10510 ins_pipe(iload_mem);
10511 %}
10513 // Load short reversed byte order
10514 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10515 match(Set dst (ReverseBytesS (LoadS src)));
10517 ins_cost(MEMORY_REF_COST);
10518 size(4);
10519 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10521 ins_encode %{
10522 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10523 %}
10524 ins_pipe(iload_mem);
10525 %}
10527 // Store Integer reversed byte order
10528 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10529 match(Set dst (StoreI dst (ReverseBytesI src)));
10531 ins_cost(MEMORY_REF_COST);
10532 size(4);
10533 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10535 ins_encode %{
10536 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10537 %}
10538 ins_pipe(istore_mem_reg);
10539 %}
10541 // Store Long reversed byte order
10542 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10543 match(Set dst (StoreL dst (ReverseBytesL src)));
10545 ins_cost(MEMORY_REF_COST);
10546 size(4);
10547 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10549 ins_encode %{
10550 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10551 %}
10552 ins_pipe(istore_mem_reg);
10553 %}
10555 // Store unsighed short/char reversed byte order
10556 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10557 match(Set dst (StoreC dst (ReverseBytesUS src)));
10559 ins_cost(MEMORY_REF_COST);
10560 size(4);
10561 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10563 ins_encode %{
10564 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10565 %}
10566 ins_pipe(istore_mem_reg);
10567 %}
10569 // Store short reversed byte order
10570 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10571 match(Set dst (StoreC dst (ReverseBytesS src)));
10573 ins_cost(MEMORY_REF_COST);
10574 size(4);
10575 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10577 ins_encode %{
10578 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10579 %}
10580 ins_pipe(istore_mem_reg);
10581 %}
10583 // ====================VECTOR INSTRUCTIONS=====================================
10585 // Load Aligned Packed values into a Double Register
10586 instruct loadV8(regD dst, memory mem) %{
10587 predicate(n->as_LoadVector()->memory_size() == 8);
10588 match(Set dst (LoadVector mem));
10589 ins_cost(MEMORY_REF_COST);
10590 size(4);
10591 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10592 ins_encode %{
10593 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10594 %}
10595 ins_pipe(floadD_mem);
10596 %}
10598 // Store Vector in Double register to memory
10599 instruct storeV8(memory mem, regD src) %{
10600 predicate(n->as_StoreVector()->memory_size() == 8);
10601 match(Set mem (StoreVector mem src));
10602 ins_cost(MEMORY_REF_COST);
10603 size(4);
10604 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10605 ins_encode %{
10606 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10607 %}
10608 ins_pipe(fstoreD_mem_reg);
10609 %}
10611 // Store Zero into vector in memory
10612 instruct storeV8B_zero(memory mem, immI0 zero) %{
10613 predicate(n->as_StoreVector()->memory_size() == 8);
10614 match(Set mem (StoreVector mem (ReplicateB zero)));
10615 ins_cost(MEMORY_REF_COST);
10616 size(4);
10617 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10618 ins_encode %{
10619 __ stx(G0, $mem$$Address);
10620 %}
10621 ins_pipe(fstoreD_mem_zero);
10622 %}
10624 instruct storeV4S_zero(memory mem, immI0 zero) %{
10625 predicate(n->as_StoreVector()->memory_size() == 8);
10626 match(Set mem (StoreVector mem (ReplicateS zero)));
10627 ins_cost(MEMORY_REF_COST);
10628 size(4);
10629 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10630 ins_encode %{
10631 __ stx(G0, $mem$$Address);
10632 %}
10633 ins_pipe(fstoreD_mem_zero);
10634 %}
10636 instruct storeV2I_zero(memory mem, immI0 zero) %{
10637 predicate(n->as_StoreVector()->memory_size() == 8);
10638 match(Set mem (StoreVector mem (ReplicateI zero)));
10639 ins_cost(MEMORY_REF_COST);
10640 size(4);
10641 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10642 ins_encode %{
10643 __ stx(G0, $mem$$Address);
10644 %}
10645 ins_pipe(fstoreD_mem_zero);
10646 %}
10648 instruct storeV2F_zero(memory mem, immF0 zero) %{
10649 predicate(n->as_StoreVector()->memory_size() == 8);
10650 match(Set mem (StoreVector mem (ReplicateF zero)));
10651 ins_cost(MEMORY_REF_COST);
10652 size(4);
10653 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10654 ins_encode %{
10655 __ stx(G0, $mem$$Address);
10656 %}
10657 ins_pipe(fstoreD_mem_zero);
10658 %}
10660 // Replicate scalar to packed byte values into Double register
10661 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10662 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10663 match(Set dst (ReplicateB src));
10664 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10665 format %{ "SLLX $src,56,$tmp\n\t"
10666 "SRLX $tmp, 8,$tmp2\n\t"
10667 "OR $tmp,$tmp2,$tmp\n\t"
10668 "SRLX $tmp,16,$tmp2\n\t"
10669 "OR $tmp,$tmp2,$tmp\n\t"
10670 "SRLX $tmp,32,$tmp2\n\t"
10671 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10672 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10673 ins_encode %{
10674 Register Rsrc = $src$$Register;
10675 Register Rtmp = $tmp$$Register;
10676 Register Rtmp2 = $tmp2$$Register;
10677 __ sllx(Rsrc, 56, Rtmp);
10678 __ srlx(Rtmp, 8, Rtmp2);
10679 __ or3 (Rtmp, Rtmp2, Rtmp);
10680 __ srlx(Rtmp, 16, Rtmp2);
10681 __ or3 (Rtmp, Rtmp2, Rtmp);
10682 __ srlx(Rtmp, 32, Rtmp2);
10683 __ or3 (Rtmp, Rtmp2, Rtmp);
10684 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10685 %}
10686 ins_pipe(ialu_reg);
10687 %}
10689 // Replicate scalar to packed byte values into Double stack
10690 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10691 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10692 match(Set dst (ReplicateB src));
10693 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10694 format %{ "SLLX $src,56,$tmp\n\t"
10695 "SRLX $tmp, 8,$tmp2\n\t"
10696 "OR $tmp,$tmp2,$tmp\n\t"
10697 "SRLX $tmp,16,$tmp2\n\t"
10698 "OR $tmp,$tmp2,$tmp\n\t"
10699 "SRLX $tmp,32,$tmp2\n\t"
10700 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10701 "STX $tmp,$dst\t! regL to stkD" %}
10702 ins_encode %{
10703 Register Rsrc = $src$$Register;
10704 Register Rtmp = $tmp$$Register;
10705 Register Rtmp2 = $tmp2$$Register;
10706 __ sllx(Rsrc, 56, Rtmp);
10707 __ srlx(Rtmp, 8, Rtmp2);
10708 __ or3 (Rtmp, Rtmp2, Rtmp);
10709 __ srlx(Rtmp, 16, Rtmp2);
10710 __ or3 (Rtmp, Rtmp2, Rtmp);
10711 __ srlx(Rtmp, 32, Rtmp2);
10712 __ or3 (Rtmp, Rtmp2, Rtmp);
10713 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10714 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10715 %}
10716 ins_pipe(ialu_reg);
10717 %}
10719 // Replicate scalar constant to packed byte values in Double register
10720 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10721 predicate(n->as_Vector()->length() == 8);
10722 match(Set dst (ReplicateB con));
10723 effect(KILL tmp);
10724 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10725 ins_encode %{
10726 // XXX This is a quick fix for 6833573.
10727 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10728 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10729 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10730 %}
10731 ins_pipe(loadConFD);
10732 %}
10734 // Replicate scalar to packed char/short values into Double register
10735 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10736 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10737 match(Set dst (ReplicateS src));
10738 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10739 format %{ "SLLX $src,48,$tmp\n\t"
10740 "SRLX $tmp,16,$tmp2\n\t"
10741 "OR $tmp,$tmp2,$tmp\n\t"
10742 "SRLX $tmp,32,$tmp2\n\t"
10743 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10744 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10745 ins_encode %{
10746 Register Rsrc = $src$$Register;
10747 Register Rtmp = $tmp$$Register;
10748 Register Rtmp2 = $tmp2$$Register;
10749 __ sllx(Rsrc, 48, Rtmp);
10750 __ srlx(Rtmp, 16, Rtmp2);
10751 __ or3 (Rtmp, Rtmp2, Rtmp);
10752 __ srlx(Rtmp, 32, Rtmp2);
10753 __ or3 (Rtmp, Rtmp2, Rtmp);
10754 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10755 %}
10756 ins_pipe(ialu_reg);
10757 %}
10759 // Replicate scalar to packed char/short values into Double stack
10760 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10761 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10762 match(Set dst (ReplicateS src));
10763 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10764 format %{ "SLLX $src,48,$tmp\n\t"
10765 "SRLX $tmp,16,$tmp2\n\t"
10766 "OR $tmp,$tmp2,$tmp\n\t"
10767 "SRLX $tmp,32,$tmp2\n\t"
10768 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10769 "STX $tmp,$dst\t! regL to stkD" %}
10770 ins_encode %{
10771 Register Rsrc = $src$$Register;
10772 Register Rtmp = $tmp$$Register;
10773 Register Rtmp2 = $tmp2$$Register;
10774 __ sllx(Rsrc, 48, Rtmp);
10775 __ srlx(Rtmp, 16, Rtmp2);
10776 __ or3 (Rtmp, Rtmp2, Rtmp);
10777 __ srlx(Rtmp, 32, Rtmp2);
10778 __ or3 (Rtmp, Rtmp2, Rtmp);
10779 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10780 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10781 %}
10782 ins_pipe(ialu_reg);
10783 %}
10785 // Replicate scalar constant to packed char/short values in Double register
10786 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10787 predicate(n->as_Vector()->length() == 4);
10788 match(Set dst (ReplicateS con));
10789 effect(KILL tmp);
10790 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10791 ins_encode %{
10792 // XXX This is a quick fix for 6833573.
10793 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10794 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10795 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10796 %}
10797 ins_pipe(loadConFD);
10798 %}
10800 // Replicate scalar to packed int values into Double register
10801 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10802 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10803 match(Set dst (ReplicateI src));
10804 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10805 format %{ "SLLX $src,32,$tmp\n\t"
10806 "SRLX $tmp,32,$tmp2\n\t"
10807 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10808 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10809 ins_encode %{
10810 Register Rsrc = $src$$Register;
10811 Register Rtmp = $tmp$$Register;
10812 Register Rtmp2 = $tmp2$$Register;
10813 __ sllx(Rsrc, 32, Rtmp);
10814 __ srlx(Rtmp, 32, Rtmp2);
10815 __ or3 (Rtmp, Rtmp2, Rtmp);
10816 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10817 %}
10818 ins_pipe(ialu_reg);
10819 %}
10821 // Replicate scalar to packed int values into Double stack
10822 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10823 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10824 match(Set dst (ReplicateI src));
10825 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10826 format %{ "SLLX $src,32,$tmp\n\t"
10827 "SRLX $tmp,32,$tmp2\n\t"
10828 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10829 "STX $tmp,$dst\t! regL to stkD" %}
10830 ins_encode %{
10831 Register Rsrc = $src$$Register;
10832 Register Rtmp = $tmp$$Register;
10833 Register Rtmp2 = $tmp2$$Register;
10834 __ sllx(Rsrc, 32, Rtmp);
10835 __ srlx(Rtmp, 32, Rtmp2);
10836 __ or3 (Rtmp, Rtmp2, Rtmp);
10837 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10838 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10839 %}
10840 ins_pipe(ialu_reg);
10841 %}
10843 // Replicate scalar zero constant to packed int values in Double register
10844 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10845 predicate(n->as_Vector()->length() == 2);
10846 match(Set dst (ReplicateI con));
10847 effect(KILL tmp);
10848 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10849 ins_encode %{
10850 // XXX This is a quick fix for 6833573.
10851 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10852 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10853 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10854 %}
10855 ins_pipe(loadConFD);
10856 %}
10858 // Replicate scalar to packed float values into Double stack
10859 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10860 predicate(n->as_Vector()->length() == 2);
10861 match(Set dst (ReplicateF src));
10862 ins_cost(MEMORY_REF_COST*2);
10863 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10864 "STF $src,$dst.lo" %}
10865 opcode(Assembler::stf_op3);
10866 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10867 ins_pipe(fstoreF_stk_reg);
10868 %}
10870 // Replicate scalar zero constant to packed float values in Double register
10871 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10872 predicate(n->as_Vector()->length() == 2);
10873 match(Set dst (ReplicateF con));
10874 effect(KILL tmp);
10875 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10876 ins_encode %{
10877 // XXX This is a quick fix for 6833573.
10878 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10879 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10880 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10881 %}
10882 ins_pipe(loadConFD);
10883 %}
10885 //----------PEEPHOLE RULES-----------------------------------------------------
10886 // These must follow all instruction definitions as they use the names
10887 // defined in the instructions definitions.
10888 //
10889 // peepmatch ( root_instr_name [preceding_instruction]* );
10890 //
10891 // peepconstraint %{
10892 // (instruction_number.operand_name relational_op instruction_number.operand_name
10893 // [, ...] );
10894 // // instruction numbers are zero-based using left to right order in peepmatch
10895 //
10896 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10897 // // provide an instruction_number.operand_name for each operand that appears
10898 // // in the replacement instruction's match rule
10899 //
10900 // ---------VM FLAGS---------------------------------------------------------
10901 //
10902 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10903 //
10904 // Each peephole rule is given an identifying number starting with zero and
10905 // increasing by one in the order seen by the parser. An individual peephole
10906 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10907 // on the command-line.
10908 //
10909 // ---------CURRENT LIMITATIONS----------------------------------------------
10910 //
10911 // Only match adjacent instructions in same basic block
10912 // Only equality constraints
10913 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10914 // Only one replacement instruction
10915 //
10916 // ---------EXAMPLE----------------------------------------------------------
10917 //
10918 // // pertinent parts of existing instructions in architecture description
10919 // instruct movI(eRegI dst, eRegI src) %{
10920 // match(Set dst (CopyI src));
10921 // %}
10922 //
10923 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10924 // match(Set dst (AddI dst src));
10925 // effect(KILL cr);
10926 // %}
10927 //
10928 // // Change (inc mov) to lea
10929 // peephole %{
10930 // // increment preceeded by register-register move
10931 // peepmatch ( incI_eReg movI );
10932 // // require that the destination register of the increment
10933 // // match the destination register of the move
10934 // peepconstraint ( 0.dst == 1.dst );
10935 // // construct a replacement instruction that sets
10936 // // the destination to ( move's source register + one )
10937 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10938 // %}
10939 //
10941 // // Change load of spilled value to only a spill
10942 // instruct storeI(memory mem, eRegI src) %{
10943 // match(Set mem (StoreI mem src));
10944 // %}
10945 //
10946 // instruct loadI(eRegI dst, memory mem) %{
10947 // match(Set dst (LoadI mem));
10948 // %}
10949 //
10950 // peephole %{
10951 // peepmatch ( loadI storeI );
10952 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10953 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10954 // %}
10956 //----------SMARTSPILL RULES---------------------------------------------------
10957 // These must follow all instruction definitions as they use the names
10958 // defined in the instructions definitions.
10959 //
10960 // SPARC will probably not have any of these rules due to RISC instruction set.
10962 //----------PIPELINE-----------------------------------------------------------
10963 // Rules which define the behavior of the target architectures pipeline.