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 /*

  * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.

  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

  *

  * This code is free software; you can redistribute it and/or modify it

  * under the terms of the GNU General Public License version 2 only, as

  * published by the Free Software Foundation.

  *

  * This code is distributed in the hope that it will be useful, but WITHOUT

  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

  * version 2 for more details (a copy is included in the LICENSE file that

  * accompanied this code).

  *

  * You should have received a copy of the GNU General Public License version

  * 2 along with this work; if not, write to the Free Software Foundation,

  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

  *

  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

  * or visit www.oracle.com if you need additional information or have any

  * questions.

  *

  */

 #include "precompiled.hpp"

 #include "asm/assembler.hpp"

 #include "assembler_sparc.inline.hpp"

 #include "gc_interface/collectedHeap.inline.hpp"

 #include "interpreter/interpreter.hpp"

 #include "memory/cardTableModRefBS.hpp"

 #include "memory/resourceArea.hpp"

 #include "prims/methodHandles.hpp"

 #include "runtime/biasedLocking.hpp"

 #include "runtime/interfaceSupport.hpp"

 #include "runtime/objectMonitor.hpp"

 #include "runtime/os.hpp"

 #include "runtime/sharedRuntime.hpp"

 #include "runtime/stubRoutines.hpp"

 #ifndef SERIALGC

 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"

 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"

 #include "gc_implementation/g1/heapRegion.hpp"

 #endif

 // Convert the raw encoding form into the form expected by the

 // constructor for Address.

 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {

   assert(scale == 0, "not supported");

   RelocationHolder rspec;

   if (disp_is_oop) {

     rspec = Relocation::spec_simple(relocInfo::oop_type);

   }

   Register rindex = as_Register(index);

   if (rindex != G0) {

     Address madr(as_Register(base), rindex);

     madr._rspec = rspec;

     return madr;

   } else {

     Address madr(as_Register(base), disp);

     madr._rspec = rspec;

     return madr;

   }

 }

 Address Argument::address_in_frame() const {

   // Warning: In LP64 mode disp will occupy more than 10 bits, but

   //          op codes such as ld or ldx, only access disp() to get

   //          their simm13 argument.

   int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;

   if (is_in())

     return Address(FP, disp); // In argument.

   else

     return Address(SP, disp); // Out argument.

 }

 static const char* argumentNames[][2] = {

   {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},

   {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},

   {"A(n>9)","P(n>9)"}

 };

 const char* Argument::name() const {

   int nofArgs = sizeof argumentNames / sizeof argumentNames[0];

   int num = number();

   if (num >= nofArgs)  num = nofArgs - 1;

   return argumentNames[num][is_in() ? 1 : 0];

 }

 void Assembler::print_instruction(int inst) {

   const char* s;

   switch (inv_op(inst)) {

   default:         s = "????"; break;

   case call_op:    s = "call"; break;

   case branch_op:

     switch (inv_op2(inst)) {

       case bpr_op2:    s = "bpr";  break;

       case fb_op2:     s = "fb";   break;

       case fbp_op2:    s = "fbp";  break;

       case br_op2:     s = "br";   break;

       case bp_op2:     s = "bp";   break;

       case cb_op2:     s = "cb";   break;

       default:         s = "????"; break;

     }

   }

   ::tty->print("%s", s);

 }

 // Patch instruction inst at offset inst_pos to refer to dest_pos

 // and return the resulting instruction.

 // We should have pcs, not offsets, but since all is relative, it will work out

 // OK.

 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {

   int m; // mask for displacement field

   int v; // new value for displacement field

   const int word_aligned_ones = -4;

   switch (inv_op(inst)) {

   default: ShouldNotReachHere();

   case call_op:    m = wdisp(word_aligned_ones, 0, 30);  v = wdisp(dest_pos, inst_pos, 30); break;

   case branch_op:

     switch (inv_op2(inst)) {

       case bpr_op2:    m = wdisp16(word_aligned_ones, 0);      v = wdisp16(dest_pos, inst_pos);     break;

       case fbp_op2:    m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;

       case bp_op2:     m = wdisp(  word_aligned_ones, 0, 19);  v = wdisp(  dest_pos, inst_pos, 19); break;

       case fb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

       case br_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

       case cb_op2:     m = wdisp(  word_aligned_ones, 0, 22);  v = wdisp(  dest_pos, inst_pos, 22); break;

       default: ShouldNotReachHere();

     }

   }

   return  inst & ~m  |  v;

 }

 // Return the offset of the branch destionation of instruction inst

 // at offset pos.

 // Should have pcs, but since all is relative, it works out.

 int Assembler::branch_destination(int inst, int pos) {

   int r;

   switch (inv_op(inst)) {

   default: ShouldNotReachHere();

   case call_op:        r = inv_wdisp(inst, pos, 30);  break;

   case branch_op:

     switch (inv_op2(inst)) {

       case bpr_op2:    r = inv_wdisp16(inst, pos);    break;

       case fbp_op2:    r = inv_wdisp(  inst, pos, 19);  break;

       case bp_op2:     r = inv_wdisp(  inst, pos, 19);  break;

       case fb_op2:     r = inv_wdisp(  inst, pos, 22);  break;

       case br_op2:     r = inv_wdisp(  inst, pos, 22);  break;

       case cb_op2:     r = inv_wdisp(  inst, pos, 22);  break;

       default: ShouldNotReachHere();

     }

   }

   return r;

 }

 int AbstractAssembler::code_fill_byte() {

   return 0x00;                  // illegal instruction 0x00000000

 }

 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) {

   switch (in) {

   case rc_z:   return equal;

   case rc_lez: return lessEqual;

   case rc_lz:  return less;

   case rc_nz:  return notEqual;

   case rc_gz:  return greater;

   case rc_gez: return greaterEqual;

   default:

     ShouldNotReachHere();

   }

   return equal;

 }

 // Generate a bunch 'o stuff (including v9's

 #ifndef PRODUCT

 void Assembler::test_v9() {

   add(    G0, G1, G2 );

   add(    G3,  0, G4 );

   addcc(  G5, G6, G7 );

   addcc(  I0,  1, I1 );

   addc(   I2, I3, I4 );

   addc(   I5, -1, I6 );

   addccc( I7, L0, L1 );

   addccc( L2, (1 << 12) - 2, L3 );

   Label lbl1, lbl2, lbl3;

   bind(lbl1);

   bpr( rc_z,    true, pn, L4, pc(),  relocInfo::oop_type );

   delayed()->nop();

   bpr( rc_lez, false, pt, L5, lbl1);

   delayed()->nop();

   fb( f_never,     true, pc() + 4,  relocInfo::none);

   delayed()->nop();

   fb( f_notEqual, false, lbl2 );

   delayed()->nop();

   fbp( f_notZero,        true, fcc0, pn, pc() - 4,  relocInfo::none);

   delayed()->nop();

   fbp( f_lessOrGreater, false, fcc1, pt, lbl3 );

   delayed()->nop();

   br( equal,  true, pc() + 1024, relocInfo::none);

   delayed()->nop();

   br( lessEqual, false, lbl1 );

   delayed()->nop();

   br( never, false, lbl1 );

   delayed()->nop();

   bp( less,               true, icc, pn, pc(), relocInfo::none);

   delayed()->nop();

   bp( lessEqualUnsigned, false, xcc, pt, lbl2 );

   delayed()->nop();

   call( pc(), relocInfo::none);

   delayed()->nop();

   call( lbl3 );

   delayed()->nop();

   casa(  L6, L7, O0 );

   casxa( O1, O2, O3, 0 );

   udiv(   O4, O5, O7 );

   udiv(   G0, (1 << 12) - 1, G1 );

   sdiv(   G1, G2, G3 );

   sdiv(   G4, -((1 << 12) - 1), G5 );

   udivcc( G6, G7, I0 );

   udivcc( I1, -((1 << 12) - 2), I2 );

   sdivcc( I3, I4, I5 );

   sdivcc( I6, -((1 << 12) - 0), I7 );

   done();

   retry();

   fadd( FloatRegisterImpl::S, F0,  F1, F2 );

   fsub( FloatRegisterImpl::D, F34, F0, F62 );

   fcmp(  FloatRegisterImpl::Q, fcc0, F0, F60);

   fcmpe( FloatRegisterImpl::S, fcc1, F31, F30);

   ftox( FloatRegisterImpl::D, F2, F4 );

   ftoi( FloatRegisterImpl::Q, F4, F8 );

   ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 );

   fxtof( FloatRegisterImpl::S, F4, F5 );

   fitof( FloatRegisterImpl::D, F6, F8 );

   fmov( FloatRegisterImpl::Q, F16, F20 );

   fneg( FloatRegisterImpl::S, F6, F7 );

   fabs( FloatRegisterImpl::D, F10, F12 );

   fmul( FloatRegisterImpl::Q,  F24, F28, F32 );

   fmul( FloatRegisterImpl::S,  FloatRegisterImpl::D,  F8, F9, F14 );

   fdiv( FloatRegisterImpl::S,  F10, F11, F12 );

   fsqrt( FloatRegisterImpl::S, F13, F14 );

   flush( L0, L1 );

   flush( L2, -1 );

   flushw();

   illtrap( (1 << 22) - 2);

   impdep1( 17, (1 << 19) - 1 );

   impdep2( 3,  0 );

   jmpl( L3, L4, L5 );

   delayed()->nop();

   jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none));

   delayed()->nop();

   ldf(    FloatRegisterImpl::S, O0, O1, F15 );

   ldf(    FloatRegisterImpl::D, O2, -1, F14 );

   ldfsr(  O3, O4 );

   ldfsr(  O5, -1 );

   ldxfsr( O6, O7 );

   ldxfsr( I0, -1 );

   ldfa(  FloatRegisterImpl::D, I1, I2, 1, F16 );

   ldfa(  FloatRegisterImpl::Q, I3, -1,    F36 );

   ldsb(  I4, I5, I6 );

   ldsb(  I7, -1, G0 );

   ldsh(  G1, G3, G4 );

   ldsh(  G5, -1, G6 );

   ldsw(  G7, L0, L1 );

   ldsw(  L2, -1, L3 );

   ldub(  L4, L5, L6 );

   ldub(  L7, -1, O0 );

   lduh(  O1, O2, O3 );

   lduh(  O4, -1, O5 );

   lduw(  O6, O7, G0 );

   lduw(  G1, -1, G2 );

   ldx(   G3, G4, G5 );

   ldx(   G6, -1, G7 );

   ldd(   I0, I1, I2 );

   ldd(   I3, -1, I4 );

   ldsba(  I5, I6, 2, I7 );

   ldsba(  L0, -1, L1 );

   ldsha(  L2, L3, 3, L4 );

   ldsha(  L5, -1, L6 );

   ldswa(  L7, O0, (1 << 8) - 1, O1 );

   ldswa(  O2, -1, O3 );

   lduba(  O4, O5, 0, O6 );

   lduba(  O7, -1, I0 );

   lduha(  I1, I2, 1, I3 );

   lduha(  I4, -1, I5 );

   lduwa(  I6, I7, 2, L0 );

   lduwa(  L1, -1, L2 );

   ldxa(   L3, L4, 3, L5 );

   ldxa(   L6, -1, L7 );

   ldda(   G0, G1, 4, G2 );

   ldda(   G3, -1, G4 );

   ldstub(  G5, G6, G7 );

   ldstub(  O0, -1, O1 );

   ldstuba( O2, O3, 5, O4 );

   ldstuba( O5, -1, O6 );

   and3(    I0, L0, O0 );

   and3(    G7, -1, O7 );

   andcc(   L2, I2, G2 );

   andcc(   L4, -1, G4 );

   andn(    I5, I6, I7 );

   andn(    I6, -1, I7 );

   andncc(  I5, I6, I7 );

   andncc(  I7, -1, I6 );

   or3(     I5, I6, I7 );

   or3(     I7, -1, I6 );

   orcc(    I5, I6, I7 );

   orcc(    I7, -1, I6 );

   orn(     I5, I6, I7 );

   orn(     I7, -1, I6 );

   orncc(   I5, I6, I7 );

   orncc(   I7, -1, I6 );

   xor3(    I5, I6, I7 );

   xor3(    I7, -1, I6 );

   xorcc(   I5, I6, I7 );

   xorcc(   I7, -1, I6 );

   xnor(    I5, I6, I7 );

   xnor(    I7, -1, I6 );

   xnorcc(  I5, I6, I7 );

   xnorcc(  I7, -1, I6 );

   membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) );

   membar( StoreStore );

   membar( LoadStore );

   membar( StoreLoad );

   membar( LoadLoad );

   membar( Sync );

   membar( MemIssue );

   membar( Lookaside );

   fmov( FloatRegisterImpl::S, f_ordered,  true, fcc2, F16, F17 );

   fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 );

   movcc( overflowClear,  false, icc, I6, L4 );

   movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 );

   movr( rc_nz, I5, I6, I7 );

   movr( rc_gz, L1, -1,  L2 );

   mulx(  I5, I6, I7 );

   mulx(  I7, -1, I6 );

   sdivx( I5, I6, I7 );

   sdivx( I7, -1, I6 );

   udivx( I5, I6, I7 );

   udivx( I7, -1, I6 );

   umul(   I5, I6, I7 );

   umul(   I7, -1, I6 );

   smul(   I5, I6, I7 );

   smul(   I7, -1, I6 );

   umulcc( I5, I6, I7 );

   umulcc( I7, -1, I6 );

   smulcc( I5, I6, I7 );

   smulcc( I7, -1, I6 );

   mulscc(   I5, I6, I7 );

   mulscc(   I7, -1, I6 );

   nop();

   popc( G0,  G1);

   popc( -1, G2);

   prefetch(   L1, L2,    severalReads );

   prefetch(   L3, -1,    oneRead );

   prefetcha(  O3, O2, 6, severalWritesAndPossiblyReads );

   prefetcha(  G2, -1,    oneWrite );

   rett( I7, I7);

   delayed()->nop();

   rett( G0, -1, relocInfo::none);

   delayed()->nop();

   save(    I5, I6, I7 );

   save(    I7, -1, I6 );

   restore( I5, I6, I7 );

   restore( I7, -1, I6 );

   saved();

   restored();

   sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none));

   sll(  I5, I6, I7 );

   sll(  I7, 31, I6 );

   srl(  I5, I6, I7 );

   srl(  I7,  0, I6 );

   sra(  I5, I6, I7 );

   sra(  I7, 30, I6 );

   sllx( I5, I6, I7 );

   sllx( I7, 63, I6 );

   srlx( I5, I6, I7 );

   srlx( I7,  0, I6 );

   srax( I5, I6, I7 );

   srax( I7, 62, I6 );

   sir( -1 );

   stbar();

   stf(    FloatRegisterImpl::Q, F40, G0, I7 );

   stf(    FloatRegisterImpl::S, F18, I3, -1 );

   stfsr(  L1, L2 );

   stfsr(  I7, -1 );

   stxfsr( I6, I5 );

   stxfsr( L4, -1 );

   stfa(  FloatRegisterImpl::D, F22, I6, I7, 7 );

   stfa(  FloatRegisterImpl::Q, F44, G0, -1 );

   stb(  L5, O2, I7 );

   stb(  I7, I6, -1 );

   sth(  L5, O2, I7 );

   sth(  I7, I6, -1 );

   stw(  L5, O2, I7 );

   stw(  I7, I6, -1 );

   stx(  L5, O2, I7 );

   stx(  I7, I6, -1 );

   std(  L5, O2, I7 );

   std(  I7, I6, -1 );

   stba(  L5, O2, I7, 8 );

   stba(  I7, I6, -1    );

   stha(  L5, O2, I7, 9 );

   stha(  I7, I6, -1    );

   stwa(  L5, O2, I7, 0 );

   stwa(  I7, I6, -1    );

   stxa(  L5, O2, I7, 11 );

   stxa(  I7, I6, -1     );

   stda(  L5, O2, I7, 12 );

   stda(  I7, I6, -1     );

   sub(    I5, I6, I7 );

   sub(    I7, -1, I6 );

   subcc(  I5, I6, I7 );

   subcc(  I7, -1, I6 );

   subc(   I5, I6, I7 );

   subc(   I7, -1, I6 );

   subccc( I5, I6, I7 );

   subccc( I7, -1, I6 );

   swap( I5, I6, I7 );

   swap( I7, -1, I6 );

   swapa(   G0, G1, 13, G2 );

   swapa(   I7, -1,     I6 );

   taddcc(    I5, I6, I7 );

   taddcc(    I7, -1, I6 );

   taddcctv(  I5, I6, I7 );

   taddcctv(  I7, -1, I6 );

   tsubcc(    I5, I6, I7 );

   tsubcc(    I7, -1, I6 );

   tsubcctv(  I5, I6, I7 );

   tsubcctv(  I7, -1, I6 );

   trap( overflowClear, xcc, G0, G1 );

   trap( lessEqual,     icc, I7, 17 );

   bind(lbl2);

   bind(lbl3);

   code()->decode();

 }

 // Generate a bunch 'o stuff unique to V8

 void Assembler::test_v8_onlys() {

   Label lbl1;

   cb( cp_0or1or2, false, pc() - 4, relocInfo::none);

   delayed()->nop();

   cb( cp_never,    true, lbl1);

   delayed()->nop();

   cpop1(1, 2, 3, 4);

   cpop2(5, 6, 7, 8);

   ldc( I0, I1, 31);

   ldc( I2, -1,  0);

   lddc( I4, I4, 30);

   lddc( I6,  0, 1 );

   ldcsr( L0, L1, 0);

   ldcsr( L1, (1 << 12) - 1, 17 );

   stc( 31, L4, L5);

   stc( 30, L6, -(1 << 12) );

   stdc( 0, L7, G0);

   stdc( 1, G1, 0 );

   stcsr( 16, G2, G3);

   stcsr( 17, G4, 1 );

   stdcq( 4, G5, G6);

   stdcq( 5, G7, -1 );

   bind(lbl1);

   code()->decode();

 }

 #endif

 // Implementation of MacroAssembler

 void MacroAssembler::null_check(Register reg, int offset) {

   if (needs_explicit_null_check((intptr_t)offset)) {

     // provoke OS NULL exception if reg = NULL by

     // accessing M[reg] w/o changing any registers

     ld_ptr(reg, 0, G0);

   }

   else {

     // nothing to do, (later) access of M[reg + offset]

     // will provoke OS NULL exception if reg = NULL

   }

 }

 // Ring buffer jumps

 #ifndef PRODUCT

 void MacroAssembler::ret(  bool trace )   { if (trace) {

                                                     mov(I7, O7); // traceable register

                                                     JMP(O7, 2 * BytesPerInstWord);

                                                   } else {

                                                     jmpl( I7, 2 * BytesPerInstWord, G0 );

                                                   }

                                                 }

 void MacroAssembler::retl( bool trace )  { if (trace) JMP(O7, 2 * BytesPerInstWord);

                                                  else jmpl( O7, 2 * BytesPerInstWord, G0 ); }

 #endif /* PRODUCT */

 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {

   assert_not_delayed();

   // This can only be traceable if r1 & r2 are visible after a window save

   if (TraceJumps) {

 #ifndef PRODUCT

     save_frame(0);

     verify_thread();

     ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);

     add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);

     sll(O0, exact_log2(4*sizeof(intptr_t)), O2);

     add(O2, O1, O1);

     add(r1->after_save(), r2->after_save(), O2);

     set((intptr_t)file, O3);

     set(line, O4);

     Label L;

     // get nearby pc, store jmp target

     call(L, relocInfo::none);  // No relocation for call to pc+0x8

     delayed()->st(O2, O1, 0);

     bind(L);

     // store nearby pc

     st(O7, O1, sizeof(intptr_t));

     // store file

     st(O3, O1, 2*sizeof(intptr_t));

     // store line

     st(O4, O1, 3*sizeof(intptr_t));

     add(O0, 1, O0);

     and3(O0, JavaThread::jump_ring_buffer_size  - 1, O0);

     st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));

     restore();

 #endif /* PRODUCT */

   }

   jmpl(r1, r2, G0);

 }

 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {

   assert_not_delayed();

   // This can only be traceable if r1 is visible after a window save

   if (TraceJumps) {

 #ifndef PRODUCT

     save_frame(0);

     verify_thread();

     ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);

     add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);

     sll(O0, exact_log2(4*sizeof(intptr_t)), O2);

     add(O2, O1, O1);

     add(r1->after_save(), offset, O2);

     set((intptr_t)file, O3);

     set(line, O4);

     Label L;

     // get nearby pc, store jmp target

     call(L, relocInfo::none);  // No relocation for call to pc+0x8

     delayed()->st(O2, O1, 0);

     bind(L);

     // store nearby pc

     st(O7, O1, sizeof(intptr_t));

     // store file

     st(O3, O1, 2*sizeof(intptr_t));

     // store line

     st(O4, O1, 3*sizeof(intptr_t));

     add(O0, 1, O0);

     and3(O0, JavaThread::jump_ring_buffer_size  - 1, O0);

     st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));

     restore();

 #endif /* PRODUCT */

   }

   jmp(r1, offset);

 }

 // This code sequence is relocatable to any address, even on LP64.

 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {

   assert_not_delayed();

   // Force fixed length sethi because NativeJump and NativeFarCall don't handle

   // variable length instruction streams.

   patchable_sethi(addrlit, temp);

   Address a(temp, addrlit.low10() + offset);  // Add the offset to the displacement.

   if (TraceJumps) {

 #ifndef PRODUCT

     // Must do the add here so relocation can find the remainder of the

     // value to be relocated.

     add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));

     save_frame(0);

     verify_thread();

     ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);

     add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);

     sll(O0, exact_log2(4*sizeof(intptr_t)), O2);

     add(O2, O1, O1);

     set((intptr_t)file, O3);

     set(line, O4);

     Label L;

     // get nearby pc, store jmp target

     call(L, relocInfo::none);  // No relocation for call to pc+0x8

     delayed()->st(a.base()->after_save(), O1, 0);

     bind(L);

     // store nearby pc

     st(O7, O1, sizeof(intptr_t));

     // store file

     st(O3, O1, 2*sizeof(intptr_t));

     // store line

     st(O4, O1, 3*sizeof(intptr_t));

     add(O0, 1, O0);

     and3(O0, JavaThread::jump_ring_buffer_size  - 1, O0);

     st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));

     restore();

     jmpl(a.base(), G0, d);

 #else

     jmpl(a.base(), a.disp(), d);

 #endif /* PRODUCT */

   } else {

     jmpl(a.base(), a.disp(), d);

   }

 }

 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {

   jumpl(addrlit, temp, G0, offset, file, line);

 }

 // Convert to C varargs format

 void MacroAssembler::set_varargs( Argument inArg, Register d ) {

   // spill register-resident args to their memory slots

   // (SPARC calling convention requires callers to have already preallocated these)

   // Note that the inArg might in fact be an outgoing argument,

   // if a leaf routine or stub does some tricky argument shuffling.

   // This routine must work even though one of the saved arguments

   // is in the d register (e.g., set_varargs(Argument(0, false), O0)).

   for (Argument savePtr = inArg;

        savePtr.is_register();

        savePtr = savePtr.successor()) {

     st_ptr(savePtr.as_register(), savePtr.address_in_frame());

   }

   // return the address of the first memory slot

   Address a = inArg.address_in_frame();

   add(a.base(), a.disp(), d);

 }

 // Conditional breakpoint (for assertion checks in assembly code)

 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {

   trap(c, cc, G0, ST_RESERVED_FOR_USER_0);

 }

 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.

 void MacroAssembler::breakpoint_trap() {

   trap(ST_RESERVED_FOR_USER_0);

 }

 // flush windows (except current) using flushw instruction if avail.

 void MacroAssembler::flush_windows() {

   if (VM_Version::v9_instructions_work())  flushw();

   else                                     flush_windows_trap();

 }

 // Write serialization page so VM thread can do a pseudo remote membar

 // We use the current thread pointer to calculate a thread specific

 // offset to write to within the page. This minimizes bus traffic

 // due to cache line collision.

 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {

   srl(thread, os::get_serialize_page_shift_count(), tmp2);

   if (Assembler::is_simm13(os::vm_page_size())) {

     and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);

   }

   else {

     set((os::vm_page_size() - sizeof(int)), tmp1);

     and3(tmp2, tmp1, tmp2);

   }

   set(os::get_memory_serialize_page(), tmp1);

   st(G0, tmp1, tmp2);

 }

 void MacroAssembler::enter() {

   Unimplemented();

 }

 void MacroAssembler::leave() {

   Unimplemented();

 }

 void MacroAssembler::mult(Register s1, Register s2, Register d) {

   if(VM_Version::v9_instructions_work()) {

     mulx (s1, s2, d);

   } else {

     smul (s1, s2, d);

   }

 }

 void MacroAssembler::mult(Register s1, int simm13a, Register d) {

   if(VM_Version::v9_instructions_work()) {

     mulx (s1, simm13a, d);

   } else {

     smul (s1, simm13a, d);

   }

 }

 #ifdef ASSERT

 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {

   const Register s1 = G3_scratch;

   const Register s2 = G4_scratch;

   Label get_psr_test;

   // Get the condition codes the V8 way.

   read_ccr_trap(s1);

   mov(ccr_save, s2);

   // This is a test of V8 which has icc but not xcc

   // so mask off the xcc bits

   and3(s2, 0xf, s2);

   // Compare condition codes from the V8 and V9 ways.

   subcc(s2, s1, G0);

   br(Assembler::notEqual, true, Assembler::pt, get_psr_test);

   delayed()->breakpoint_trap();

   bind(get_psr_test);

 }

 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {

   const Register s1 = G3_scratch;

   const Register s2 = G4_scratch;

   Label set_psr_test;

   // Write out the saved condition codes the V8 way

   write_ccr_trap(ccr_save, s1, s2);

   // Read back the condition codes using the V9 instruction

   rdccr(s1);

   mov(ccr_save, s2);

   // This is a test of V8 which has icc but not xcc

   // so mask off the xcc bits

   and3(s2, 0xf, s2);

   and3(s1, 0xf, s1);

   // Compare the V8 way with the V9 way.

   subcc(s2, s1, G0);

   br(Assembler::notEqual, true, Assembler::pt, set_psr_test);

   delayed()->breakpoint_trap();

   bind(set_psr_test);

 }

 #else

 #define read_ccr_v8_assert(x)

 #define write_ccr_v8_assert(x)

 #endif // ASSERT

 void MacroAssembler::read_ccr(Register ccr_save) {

   if (VM_Version::v9_instructions_work()) {

     rdccr(ccr_save);

     // Test code sequence used on V8.  Do not move above rdccr.

     read_ccr_v8_assert(ccr_save);

   } else {

     read_ccr_trap(ccr_save);

   }

 }

 void MacroAssembler::write_ccr(Register ccr_save) {

   if (VM_Version::v9_instructions_work()) {

     // Test code sequence used on V8.  Do not move below wrccr.

     write_ccr_v8_assert(ccr_save);

     wrccr(ccr_save);

   } else {

     const Register temp_reg1 = G3_scratch;

     const Register temp_reg2 = G4_scratch;

     write_ccr_trap(ccr_save, temp_reg1, temp_reg2);

   }

 }

 // Calls to C land

 #ifdef ASSERT

 // a hook for debugging

 static Thread* reinitialize_thread() {

   return ThreadLocalStorage::thread();

 }

 #else

 #define reinitialize_thread ThreadLocalStorage::thread

 #endif

 #ifdef ASSERT

 address last_get_thread = NULL;

 #endif

 // call this when G2_thread is not known to be valid

 void MacroAssembler::get_thread() {

   save_frame(0);                // to avoid clobbering O0

   mov(G1, L0);                  // avoid clobbering G1

   mov(G5_method, L1);           // avoid clobbering G5

   mov(G3, L2);                  // avoid clobbering G3 also

   mov(G4, L5);                  // avoid clobbering G4

 #ifdef ASSERT

   AddressLiteral last_get_thread_addrlit(&last_get_thread);

   set(last_get_thread_addrlit, L3);

   inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call

   st_ptr(L4, L3, 0);

 #endif

   call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);

   delayed()->nop();

   mov(L0, G1);

   mov(L1, G5_method);

   mov(L2, G3);

   mov(L5, G4);

   restore(O0, 0, G2_thread);

 }

 static Thread* verify_thread_subroutine(Thread* gthread_value) {

   Thread* correct_value = ThreadLocalStorage::thread();

   guarantee(gthread_value == correct_value, "G2_thread value must be the thread");

   return correct_value;

 }

 void MacroAssembler::verify_thread() {

   if (VerifyThread) {

     // NOTE: this chops off the heads of the 64-bit O registers.

 #ifdef CC_INTERP

     save_frame(0);

 #else

     // make sure G2_thread contains the right value

     save_frame_and_mov(0, Lmethod, Lmethod);   // to avoid clobbering O0 (and propagate Lmethod for -Xprof)

     mov(G1, L1);                // avoid clobbering G1

     // G2 saved below

     mov(G3, L3);                // avoid clobbering G3

     mov(G4, L4);                // avoid clobbering G4

     mov(G5_method, L5);         // avoid clobbering G5_method

 #endif /* CC_INTERP */

 #if defined(COMPILER2) && !defined(_LP64)

     // Save & restore possible 64-bit Long arguments in G-regs

     srlx(G1,32,L0);

     srlx(G4,32,L6);

 #endif

     call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);

     delayed()->mov(G2_thread, O0);

     mov(L1, G1);                // Restore G1

     // G2 restored below

     mov(L3, G3);                // restore G3

     mov(L4, G4);                // restore G4

     mov(L5, G5_method);         // restore G5_method

 #if defined(COMPILER2) && !defined(_LP64)

     // Save & restore possible 64-bit Long arguments in G-regs

     sllx(L0,32,G2);             // Move old high G1 bits high in G2

     srl(G1, 0,G1);              // Clear current high G1 bits

     or3 (G1,G2,G1);             // Recover 64-bit G1

     sllx(L6,32,G2);             // Move old high G4 bits high in G2

     srl(G4, 0,G4);              // Clear current high G4 bits

     or3 (G4,G2,G4);             // Recover 64-bit G4

 #endif

     restore(O0, 0, G2_thread);

   }

 }

 void MacroAssembler::save_thread(const Register thread_cache) {

   verify_thread();

   if (thread_cache->is_valid()) {

     assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");

     mov(G2_thread, thread_cache);

   }

   if (VerifyThread) {

     // smash G2_thread, as if the VM were about to anyway

     set(0x67676767, G2_thread);

   }

 }

 void MacroAssembler::restore_thread(const Register thread_cache) {

   if (thread_cache->is_valid()) {

     assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");

     mov(thread_cache, G2_thread);

     verify_thread();

   } else {

     // do it the slow way

     get_thread();

   }

 }

 // %%% maybe get rid of [re]set_last_Java_frame

 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {

   assert_not_delayed();

   Address flags(G2_thread, JavaThread::frame_anchor_offset() +

                            JavaFrameAnchor::flags_offset());

   Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());

   // Always set last_Java_pc and flags first because once last_Java_sp is visible

   // has_last_Java_frame is true and users will look at the rest of the fields.

   // (Note: flags should always be zero before we get here so doesn't need to be set.)

 #ifdef ASSERT

   // Verify that flags was zeroed on return to Java

   Label PcOk;

   save_frame(0);                // to avoid clobbering O0

   ld_ptr(pc_addr, L0);

   tst(L0);

 #ifdef _LP64

   brx(Assembler::zero, false, Assembler::pt, PcOk);

 #else

   br(Assembler::zero, false, Assembler::pt, PcOk);

 #endif // _LP64

   delayed() -> nop();

   stop("last_Java_pc not zeroed before leaving Java");

   bind(PcOk);

   // Verify that flags was zeroed on return to Java

   Label FlagsOk;

   ld(flags, L0);

   tst(L0);

   br(Assembler::zero, false, Assembler::pt, FlagsOk);

   delayed() -> restore();

   stop("flags not zeroed before leaving Java");

   bind(FlagsOk);

 #endif /* ASSERT */

   //

   // When returning from calling out from Java mode the frame anchor's last_Java_pc

   // will always be set to NULL. It is set here so that if we are doing a call to

   // native (not VM) that we capture the known pc and don't have to rely on the

   // native call having a standard frame linkage where we can find the pc.

   if (last_Java_pc->is_valid()) {

     st_ptr(last_Java_pc, pc_addr);

   }

 #ifdef _LP64

 #ifdef ASSERT

   // Make sure that we have an odd stack

   Label StackOk;

   andcc(last_java_sp, 0x01, G0);

   br(Assembler::notZero, false, Assembler::pt, StackOk);

   delayed() -> nop();

   stop("Stack Not Biased in set_last_Java_frame");

   bind(StackOk);

 #endif // ASSERT

   assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");

   add( last_java_sp, STACK_BIAS, G4_scratch );

   st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());

 #else

   st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());

 #endif // _LP64

 }

 void MacroAssembler::reset_last_Java_frame(void) {

   assert_not_delayed();

   Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());

   Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());

   Address flags  (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());

 #ifdef ASSERT

   // check that it WAS previously set

 #ifdef CC_INTERP

     save_frame(0);

 #else

     save_frame_and_mov(0, Lmethod, Lmethod);     // Propagate Lmethod to helper frame for -Xprof

 #endif /* CC_INTERP */

     ld_ptr(sp_addr, L0);

     tst(L0);

     breakpoint_trap(Assembler::zero, Assembler::ptr_cc);

     restore();

 #endif // ASSERT

   st_ptr(G0, sp_addr);

   // Always return last_Java_pc to zero

   st_ptr(G0, pc_addr);

   // Always null flags after return to Java

   st(G0, flags);

 }

 void MacroAssembler::call_VM_base(

   Register        oop_result,

   Register        thread_cache,

   Register        last_java_sp,

   address         entry_point,

   int             number_of_arguments,

   bool            check_exceptions)

 {

   assert_not_delayed();

   // determine last_java_sp register

   if (!last_java_sp->is_valid()) {

     last_java_sp = SP;

   }

   // debugging support

   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");

   // 64-bit last_java_sp is biased!

   set_last_Java_frame(last_java_sp, noreg);

   if (VerifyThread)  mov(G2_thread, O0); // about to be smashed; pass early

   save_thread(thread_cache);

   // do the call

   call(entry_point, relocInfo::runtime_call_type);

   if (!VerifyThread)

     delayed()->mov(G2_thread, O0);  // pass thread as first argument

   else

     delayed()->nop();             // (thread already passed)

   restore_thread(thread_cache);

   reset_last_Java_frame();

   // check for pending exceptions. use Gtemp as scratch register.

   if (check_exceptions) {

     check_and_forward_exception(Gtemp);

   }

   // get oop result if there is one and reset the value in the thread

   if (oop_result->is_valid()) {

     get_vm_result(oop_result);

   }

 }

 void MacroAssembler::check_and_forward_exception(Register scratch_reg)

 {

   Label L;

   check_and_handle_popframe(scratch_reg);

   check_and_handle_earlyret(scratch_reg);

   Address exception_addr(G2_thread, Thread::pending_exception_offset());

   ld_ptr(exception_addr, scratch_reg);

   br_null(scratch_reg,false,pt,L);

   delayed()->nop();

   // we use O7 linkage so that forward_exception_entry has the issuing PC

   call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);

   delayed()->nop();

   bind(L);

 }

 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {

 }

 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {

 }

 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {

   call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);

 }

 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {

   // O0 is reserved for the thread

   mov(arg_1, O1);

   call_VM(oop_result, entry_point, 1, check_exceptions);

 }

 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {

   // O0 is reserved for the thread

   mov(arg_1, O1);

   mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");

   call_VM(oop_result, entry_point, 2, check_exceptions);

 }

 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {

   // O0 is reserved for the thread

   mov(arg_1, O1);

   mov(arg_2, O2); assert(arg_2 != O1,                "smashed argument");

   mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");

   call_VM(oop_result, entry_point, 3, check_exceptions);

 }

 // Note: The following call_VM overloadings are useful when a "save"

 // has already been performed by a stub, and the last Java frame is

 // the previous one.  In that case, last_java_sp must be passed as FP

 // instead of SP.

 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {

   call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);

 }

 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {

   // O0 is reserved for the thread

   mov(arg_1, O1);

   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);

 }

 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {

   // O0 is reserved for the thread

   mov(arg_1, O1);

   mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");

   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);

 }

 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {

   // O0 is reserved for the thread

   mov(arg_1, O1);

   mov(arg_2, O2); assert(arg_2 != O1,                "smashed argument");

   mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");

   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);

 }

 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {

   assert_not_delayed();

   save_thread(thread_cache);

   // do the call

   call(entry_point, relocInfo::runtime_call_type);

   delayed()->nop();

   restore_thread(thread_cache);

 }

 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {

   call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);

 }

 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {

   mov(arg_1, O0);

   call_VM_leaf(thread_cache, entry_point, 1);

 }

 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {

   mov(arg_1, O0);

   mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");

   call_VM_leaf(thread_cache, entry_point, 2);

 }

 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {

   mov(arg_1, O0);

   mov(arg_2, O1); assert(arg_2 != O0,                "smashed argument");

   mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");

   call_VM_leaf(thread_cache, entry_point, 3);

 }

 void MacroAssembler::get_vm_result(Register oop_result) {

   verify_thread();

   Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());

   ld_ptr(    vm_result_addr, oop_result);

   st_ptr(G0, vm_result_addr);

   verify_oop(oop_result);

 }

 void MacroAssembler::get_vm_result_2(Register oop_result) {

   verify_thread();

   Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());

   ld_ptr(vm_result_addr_2, oop_result);

   st_ptr(G0, vm_result_addr_2);

   verify_oop(oop_result);

 }

 // We require that C code which does not return a value in vm_result will

 // leave it undisturbed.

 void MacroAssembler::set_vm_result(Register oop_result) {

   verify_thread();

   Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());

   verify_oop(oop_result);

 # ifdef ASSERT

     // Check that we are not overwriting any other oop.

 #ifdef CC_INTERP

     save_frame(0);

 #else

     save_frame_and_mov(0, Lmethod, Lmethod);     // Propagate Lmethod for -Xprof

 #endif /* CC_INTERP */

     ld_ptr(vm_result_addr, L0);

     tst(L0);

     restore();

     breakpoint_trap(notZero, Assembler::ptr_cc);

     // }

 # endif

   st_ptr(oop_result, vm_result_addr);

 }

 void MacroAssembler::card_table_write(jbyte* byte_map_base,

                                       Register tmp, Register obj) {

 #ifdef _LP64

   srlx(obj, CardTableModRefBS::card_shift, obj);

 #else

   srl(obj, CardTableModRefBS::card_shift, obj);

 #endif

   assert(tmp != obj, "need separate temp reg");

   set((address) byte_map_base, tmp);

   stb(G0, tmp, obj);

 }

 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {

   address save_pc;

   int shiftcnt;

 #ifdef _LP64

 # ifdef CHECK_DELAY

   assert_not_delayed((char*) "cannot put two instructions in delay slot");

 # endif

   v9_dep();

   save_pc = pc();

   int msb32 = (int) (addrlit.value() >> 32);

   int lsb32 = (int) (addrlit.value());

   if (msb32 == 0 && lsb32 >= 0) {

     Assembler::sethi(lsb32, d, addrlit.rspec());

   }

   else if (msb32 == -1) {

     Assembler::sethi(~lsb32, d, addrlit.rspec());

     xor3(d, ~low10(~0), d);

   }

   else {

     Assembler::sethi(msb32, d, addrlit.rspec());  // msb 22-bits

     if (msb32 & 0x3ff)                            // Any bits?

       or3(d, msb32 & 0x3ff, d);                   // msb 32-bits are now in lsb 32

     if (lsb32 & 0xFFFFFC00) {                     // done?

       if ((lsb32 >> 20) & 0xfff) {                // Any bits set?

         sllx(d, 12, d);                           // Make room for next 12 bits

         or3(d, (lsb32 >> 20) & 0xfff, d);         // Or in next 12

         shiftcnt = 0;                             // We already shifted

       }

       else

         shiftcnt = 12;

       if ((lsb32 >> 10) & 0x3ff) {

         sllx(d, shiftcnt + 10, d);                // Make room for last 10 bits

         or3(d, (lsb32 >> 10) & 0x3ff, d);         // Or in next 10

         shiftcnt = 0;

       }

       else

         shiftcnt = 10;

       sllx(d, shiftcnt + 10, d);                  // Shift leaving disp field 0'd

     }

     else

       sllx(d, 32, d);

   }

   // Pad out the instruction sequence so it can be patched later.

   if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&

                            addrlit.rtype() != relocInfo::runtime_call_type)) {

     while (pc() < (save_pc + (7 * BytesPerInstWord)))

       nop();

   }

 #else

   Assembler::sethi(addrlit.value(), d, addrlit.rspec());

 #endif

 }

 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {

   internal_sethi(addrlit, d, false);

 }

 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {

   internal_sethi(addrlit, d, true);

 }

 int MacroAssembler::insts_for_sethi(address a, bool worst_case) {

 #ifdef _LP64

   if (worst_case)  return 7;

   intptr_t iaddr = (intptr_t) a;

   int msb32 = (int) (iaddr >> 32);

   int lsb32 = (int) (iaddr);

   int count;

   if (msb32 == 0 && lsb32 >= 0)

     count = 1;

   else if (msb32 == -1)

     count = 2;

   else {

     count = 2;

     if (msb32 & 0x3ff)

       count++;

     if (lsb32 & 0xFFFFFC00 ) {

       if ((lsb32 >> 20) & 0xfff)  count += 2;

       if ((lsb32 >> 10) & 0x3ff)  count += 2;

     }

   }

   return count;

 #else

   return 1;

 #endif

 }

 int MacroAssembler::worst_case_insts_for_set() {

   return insts_for_sethi(NULL, true) + 1;

 }

 // Keep in sync with MacroAssembler::insts_for_internal_set

 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {

   intptr_t value = addrlit.value();

   if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {

     // can optimize

     if (-4096 <= value && value <= 4095) {

       or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)

       return;

     }

     if (inv_hi22(hi22(value)) == value) {

       sethi(addrlit, d);

       return;

     }

   }

   assert_not_delayed((char*) "cannot put two instructions in delay slot");

   internal_sethi(addrlit, d, ForceRelocatable);

   if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {

     add(d, addrlit.low10(), d, addrlit.rspec());

   }

 }

 // Keep in sync with MacroAssembler::internal_set

 int MacroAssembler::insts_for_internal_set(intptr_t value) {

   // can optimize

   if (-4096 <= value && value <= 4095) {

     return 1;

   }

   if (inv_hi22(hi22(value)) == value) {

     return insts_for_sethi((address) value);

   }

   int count = insts_for_sethi((address) value);

   AddressLiteral al(value);

   if (al.low10() != 0) {

     count++;

   }

   return count;

 }

 void MacroAssembler::set(const AddressLiteral& al, Register d) {

   internal_set(al, d, false);

 }

 void MacroAssembler::set(intptr_t value, Register d) {

   AddressLiteral al(value);

   internal_set(al, d, false);

 }

 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {

   AddressLiteral al(addr, rspec);

   internal_set(al, d, false);

 }

 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {

   internal_set(al, d, true);

 }

 void MacroAssembler::patchable_set(intptr_t value, Register d) {

   AddressLiteral al(value);

   internal_set(al, d, true);

 }

 void MacroAssembler::set64(jlong value, Register d, Register tmp) {

   assert_not_delayed();

   v9_dep();

   int hi = (int)(value >> 32);

   int lo = (int)(value & ~0);

   // (Matcher::isSimpleConstant64 knows about the following optimizations.)

   if (Assembler::is_simm13(lo) && value == lo) {

     or3(G0, lo, d);

   } else if (hi == 0) {

     Assembler::sethi(lo, d);   // hardware version zero-extends to upper 32

     if (low10(lo) != 0)

       or3(d, low10(lo), d);

   }

   else if (hi == -1) {

     Assembler::sethi(~lo, d);  // hardware version zero-extends to upper 32

     xor3(d, low10(lo) ^ ~low10(~0), d);

   }

   else if (lo == 0) {

     if (Assembler::is_simm13(hi)) {

       or3(G0, hi, d);

     } else {

       Assembler::sethi(hi, d);   // hardware version zero-extends to upper 32

       if (low10(hi) != 0)

         or3(d, low10(hi), d);

     }

     sllx(d, 32, d);

   }

   else {

     Assembler::sethi(hi, tmp);

     Assembler::sethi(lo,   d); // macro assembler version sign-extends

     if (low10(hi) != 0)

       or3 (tmp, low10(hi), tmp);

     if (low10(lo) != 0)

       or3 (  d, low10(lo),   d);

     sllx(tmp, 32, tmp);

     or3 (d, tmp, d);

   }

 }

 int MacroAssembler::insts_for_set64(jlong value) {

   v9_dep();

   int hi = (int) (value >> 32);

   int lo = (int) (value & ~0);

   int count = 0;

   // (Matcher::isSimpleConstant64 knows about the following optimizations.)

   if (Assembler::is_simm13(lo) && value == lo) {

     count++;

   } else if (hi == 0) {

     count++;

     if (low10(lo) != 0)

       count++;

   }

   else if (hi == -1) {

     count += 2;

   }

   else if (lo == 0) {

     if (Assembler::is_simm13(hi)) {

       count++;

     } else {

       count++;

       if (low10(hi) != 0)

         count++;

     }

     count++;

   }

   else {

     count += 2;

     if (low10(hi) != 0)

       count++;

     if (low10(lo) != 0)

       count++;

     count += 2;

   }

   return count;

 }

 // compute size in bytes of sparc frame, given

 // number of extraWords

 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {

   int nWords = frame::memory_parameter_word_sp_offset;

   nWords += extraWords;

   if (nWords & 1) ++nWords; // round up to double-word

   return nWords * BytesPerWord;

 }

 // save_frame: given number of "extra" words in frame,

 // issue approp. save instruction (p 200, v8 manual)

 void MacroAssembler::save_frame(int extraWords = 0) {

   int delta = -total_frame_size_in_bytes(extraWords);

   if (is_simm13(delta)) {

     save(SP, delta, SP);

   } else {

     set(delta, G3_scratch);

     save(SP, G3_scratch, SP);

   }

 }

 void MacroAssembler::save_frame_c1(int size_in_bytes) {

   if (is_simm13(-size_in_bytes)) {

     save(SP, -size_in_bytes, SP);

   } else {

     set(-size_in_bytes, G3_scratch);

     save(SP, G3_scratch, SP);

   }

 }

 void MacroAssembler::save_frame_and_mov(int extraWords,

                                         Register s1, Register d1,

                                         Register s2, Register d2) {

   assert_not_delayed();

   // The trick here is to use precisely the same memory word

   // that trap handlers also use to save the register.

   // This word cannot be used for any other purpose, but

   // it works fine to save the register's value, whether or not

   // an interrupt flushes register windows at any given moment!

   Address s1_addr;

   if (s1->is_valid() && (s1->is_in() || s1->is_local())) {

     s1_addr = s1->address_in_saved_window();

     st_ptr(s1, s1_addr);

   }

   Address s2_addr;

   if (s2->is_valid() && (s2->is_in() || s2->is_local())) {

     s2_addr = s2->address_in_saved_window();

     st_ptr(s2, s2_addr);

   }

   save_frame(extraWords);

   if (s1_addr.base() == SP) {

     ld_ptr(s1_addr.after_save(), d1);

   } else if (s1->is_valid()) {

     mov(s1->after_save(), d1);

   }

   if (s2_addr.base() == SP) {

     ld_ptr(s2_addr.after_save(), d2);

   } else if (s2->is_valid()) {

     mov(s2->after_save(), d2);

   }

 }

 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {

   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");

   int oop_index = oop_recorder()->allocate_index(obj);

   return AddressLiteral(obj, oop_Relocation::spec(oop_index));

 }

 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {

   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");

   int oop_index = oop_recorder()->find_index(obj);

   return AddressLiteral(obj, oop_Relocation::spec(oop_index));

 }

 void  MacroAssembler::set_narrow_oop(jobject obj, Register d) {

   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");

   int oop_index = oop_recorder()->find_index(obj);

   RelocationHolder rspec = oop_Relocation::spec(oop_index);

   assert_not_delayed();

   // Relocation with special format (see relocInfo_sparc.hpp).

   relocate(rspec, 1);

   // Assembler::sethi(0x3fffff, d);

   emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );

   // Don't add relocation for 'add'. Do patching during 'sethi' processing.

   add(d, 0x3ff, d);

 }

 void MacroAssembler::align(int modulus) {

   while (offset() % modulus != 0) nop();

 }

 void MacroAssembler::safepoint() {

   relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint));

 }

 void RegistersForDebugging::print(outputStream* s) {

   int j;

   for ( j = 0;  j < 8;  ++j )

     if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]);

     else          s->print_cr( "fp = 0x%.16lx",    i[j]);

   s->cr();

   for ( j = 0;  j < 8;  ++j )

     s->print_cr("l%d = 0x%.16lx", j, l[j]);

   s->cr();

   for ( j = 0;  j < 8;  ++j )

     if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]);

     else          s->print_cr( "sp = 0x%.16lx",    o[j]);

   s->cr();

   for ( j = 0;  j < 8;  ++j )

     s->print_cr("g%d = 0x%.16lx", j, g[j]);

   s->cr();

   // print out floats with compression

   for (j = 0; j < 32; ) {

     jfloat val = f[j];

     int last = j;

     for ( ;  last+1 < 32;  ++last ) {

       char b1[1024], b2[1024];

       sprintf(b1, "%f", val);

       sprintf(b2, "%f", f[last+1]);

       if (strcmp(b1, b2))

         break;

     }

     s->print("f%d", j);

     if ( j != last )  s->print(" - f%d", last);

     s->print(" = %f", val);

     s->fill_to(25);

     s->print_cr(" (0x%x)", val);

     j = last + 1;

   }

   s->cr();

   // and doubles (evens only)

   for (j = 0; j < 32; ) {

     jdouble val = d[j];

     int last = j;

     for ( ;  last+1 < 32;  ++last ) {

       char b1[1024], b2[1024];

       sprintf(b1, "%f", val);

       sprintf(b2, "%f", d[last+1]);

       if (strcmp(b1, b2))

         break;

     }

     s->print("d%d", 2 * j);

     if ( j != last )  s->print(" - d%d", last);

     s->print(" = %f", val);

     s->fill_to(30);

     s->print("(0x%x)", *(int*)&val);

     s->fill_to(42);

     s->print_cr("(0x%x)", *(1 + (int*)&val));

     j = last + 1;

   }

   s->cr();

 }

 void RegistersForDebugging::save_registers(MacroAssembler* a) {

   a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);

   a->flush_windows();

   int i;

   for (i = 0; i < 8; ++i) {

     a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1);  a->st_ptr( L1, O0, i_offset(i));

     a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1);  a->st_ptr( L1, O0, l_offset(i));

     a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));

     a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));

   }

   for (i = 0;  i < 32; ++i) {

     a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));

   }

   for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) {

     a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));

   }

 }

 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {

   for (int i = 1; i < 8;  ++i) {

     a->ld_ptr(r, g_offset(i), as_gRegister(i));

   }

   for (int j = 0; j < 32; ++j) {

     a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));

   }

   for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) {

     a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));

   }

 }

 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack

 void MacroAssembler::push_fTOS() {

   // %%%%%% need to implement this

 }

 // pops double TOS element from CPU stack and pushes on FPU stack

 void MacroAssembler::pop_fTOS() {

   // %%%%%% need to implement this

 }

 void MacroAssembler::empty_FPU_stack() {

   // %%%%%% need to implement this

 }

 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {

   // plausibility check for oops

   if (!VerifyOops) return;

   if (reg == G0)  return;       // always NULL, which is always an oop

   char buffer[64];

 #ifdef COMPILER1

   if (CommentedAssembly) {

     snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());

     block_comment(buffer);

   }

 #endif

   int len = strlen(file) + strlen(msg) + 1 + 4;

   sprintf(buffer, "%d", line);

   len += strlen(buffer);

   sprintf(buffer, " at offset %d ", offset());

   len += strlen(buffer);

   char * real_msg = new char[len];

   sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line);

   // Call indirectly to solve generation ordering problem

   AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());

   // Make some space on stack above the current register window.

   // Enough to hold 8 64-bit registers.

   add(SP,-8*8,SP);

   // Save some 64-bit registers; a normal 'save' chops the heads off

   // of 64-bit longs in the 32-bit build.

   stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);

   stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);

   mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed

   stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);

   set((intptr_t)real_msg, O1);

   // Load address to call to into O7

   load_ptr_contents(a, O7);

   // Register call to verify_oop_subroutine

   callr(O7, G0);

   delayed()->nop();

   // recover frame size

   add(SP, 8*8,SP);

 }

 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {

   // plausibility check for oops

   if (!VerifyOops) return;

   char buffer[64];

   sprintf(buffer, "%d", line);

   int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer);

   sprintf(buffer, " at SP+%d ", addr.disp());

   len += strlen(buffer);

   char * real_msg = new char[len];

   sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);

   // Call indirectly to solve generation ordering problem

   AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());

   // Make some space on stack above the current register window.

   // Enough to hold 8 64-bit registers.

   add(SP,-8*8,SP);

   // Save some 64-bit registers; a normal 'save' chops the heads off

   // of 64-bit longs in the 32-bit build.

   stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);

   stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);

   ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed

   stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);

   set((intptr_t)real_msg, O1);

   // Load address to call to into O7

   load_ptr_contents(a, O7);

   // Register call to verify_oop_subroutine

   callr(O7, G0);

   delayed()->nop();

   // recover frame size

   add(SP, 8*8,SP);

 }

 // side-door communication with signalHandler in os_solaris.cpp

 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };

 // This macro is expanded just once; it creates shared code.  Contract:

 // receives an oop in O0.  Must restore O0 & O7 from TLS.  Must not smash ANY

 // registers, including flags.  May not use a register 'save', as this blows

 // the high bits of the O-regs if they contain Long values.  Acts as a 'leaf'

 // call.

 void MacroAssembler::verify_oop_subroutine() {

   assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" );

   // Leaf call; no frame.

   Label succeed, fail, null_or_fail;

   // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).

   // O0 is now the oop to be checked.  O7 is the return address.

   Register O0_obj = O0;

   // Save some more registers for temps.

   stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);

   stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);

   stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);

   stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);

   // Save flags

   Register O5_save_flags = O5;

   rdccr( O5_save_flags );

   { // count number of verifies

     Register O2_adr   = O2;

     Register O3_accum = O3;

     inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);

   }

   Register O2_mask = O2;

   Register O3_bits = O3;

   Register O4_temp = O4;

   // mark lower end of faulting range

   assert(_verify_oop_implicit_branch[0] == NULL, "set once");

   _verify_oop_implicit_branch[0] = pc();

   // We can't check the mark oop because it could be in the process of

   // locking or unlocking while this is running.

   set(Universe::verify_oop_mask (), O2_mask);

   set(Universe::verify_oop_bits (), O3_bits);

   // assert((obj & oop_mask) == oop_bits);

   and3(O0_obj, O2_mask, O4_temp);

   cmp(O4_temp, O3_bits);

   brx(notEqual, false, pn, null_or_fail);

   delayed()->nop();

   if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {

     // the null_or_fail case is useless; must test for null separately

     br_null(O0_obj, false, pn, succeed);

     delayed()->nop();

   }

   // Check the klassOop of this object for being in the right area of memory.

   // Cannot do the load in the delay above slot in case O0 is null

   load_klass(O0_obj, O0_obj);

   // assert((klass & klass_mask) == klass_bits);

   if( Universe::verify_klass_mask() != Universe::verify_oop_mask() )

     set(Universe::verify_klass_mask(), O2_mask);

   if( Universe::verify_klass_bits() != Universe::verify_oop_bits() )

     set(Universe::verify_klass_bits(), O3_bits);

   and3(O0_obj, O2_mask, O4_temp);

   cmp(O4_temp, O3_bits);

   brx(notEqual, false, pn, fail);

   delayed()->nop();

   // Check the klass's klass

   load_klass(O0_obj, O0_obj);

   and3(O0_obj, O2_mask, O4_temp);

   cmp(O4_temp, O3_bits);

   brx(notEqual, false, pn, fail);

   delayed()->wrccr( O5_save_flags ); // Restore CCR's

   // mark upper end of faulting range

   _verify_oop_implicit_branch[1] = pc();

   //-----------------------

   // all tests pass

   bind(succeed);

   // Restore prior 64-bit registers

   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);

   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);

   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);

   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);

   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);

   ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);

   retl();                       // Leaf return; restore prior O7 in delay slot

   delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);

   //-----------------------

   bind(null_or_fail);           // nulls are less common but OK

   br_null(O0_obj, false, pt, succeed);

   delayed()->wrccr( O5_save_flags ); // Restore CCR's

   //-----------------------

   // report failure:

   bind(fail);

   _verify_oop_implicit_branch[2] = pc();

   wrccr( O5_save_flags ); // Restore CCR's

   save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));

   // stop_subroutine expects message pointer in I1.

   mov(I1, O1);

   // Restore prior 64-bit registers

   ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);

   ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);

   ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);

   ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);

   ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);

   ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);

   // factor long stop-sequence into subroutine to save space

   assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");

   // call indirectly to solve generation ordering problem

   AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());

   load_ptr_contents(al, O5);

   jmpl(O5, 0, O7);

   delayed()->nop();

 }

 void MacroAssembler::stop(const char* msg) {

   // save frame first to get O7 for return address

   // add one word to size in case struct is odd number of words long

   // It must be doubleword-aligned for storing doubles into it.

     save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));

     // stop_subroutine expects message pointer in I1.

     set((intptr_t)msg, O1);

     // factor long stop-sequence into subroutine to save space

     assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");

     // call indirectly to solve generation ordering problem

     AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());

     load_ptr_contents(a, O5);

     jmpl(O5, 0, O7);

     delayed()->nop();

     breakpoint_trap();   // make stop actually stop rather than writing

                          // unnoticeable results in the output files.

     // restore(); done in callee to save space!

 }

 void MacroAssembler::warn(const char* msg) {

   save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));

   RegistersForDebugging::save_registers(this);

   mov(O0, L0);

   set((intptr_t)msg, O0);

   call( CAST_FROM_FN_PTR(address, warning) );

   delayed()->nop();

 //  ret();

 //  delayed()->restore();

   RegistersForDebugging::restore_registers(this, L0);

   restore();

 }

 void MacroAssembler::untested(const char* what) {

   // We must be able to turn interactive prompting off

   // in order to run automated test scripts on the VM

   // Use the flag ShowMessageBoxOnError

   char* b = new char[1024];

   sprintf(b, "untested: %s", what);

   if ( ShowMessageBoxOnError )   stop(b);

   else                           warn(b);

 }

 void MacroAssembler::stop_subroutine() {

   RegistersForDebugging::save_registers(this);

   // for the sake of the debugger, stick a PC on the current frame

   // (this assumes that the caller has performed an extra "save")

   mov(I7, L7);

   add(O7, -7 * BytesPerInt, I7);

   save_frame(); // one more save to free up another O7 register

   mov(I0, O1); // addr of reg save area

   // We expect pointer to message in I1. Caller must set it up in O1

   mov(I1, O0); // get msg

   call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);

   delayed()->nop();

   restore();

   RegistersForDebugging::restore_registers(this, O0);

   save_frame(0);

   call(CAST_FROM_FN_PTR(address,breakpoint));

   delayed()->nop();

   restore();

   mov(L7, I7);

   retl();

   delayed()->restore(); // see stop above

 }

 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {

   if ( ShowMessageBoxOnError ) {

       JavaThreadState saved_state = JavaThread::current()->thread_state();

       JavaThread::current()->set_thread_state(_thread_in_vm);

       {

         // In order to get locks work, we need to fake a in_VM state

         ttyLocker ttyl;

         ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);

         if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {

           ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value());

         }

         if (os::message_box(msg, "Execution stopped, print registers?"))

           regs->print(::tty);

       }

       ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);

   }

   else

      ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);

   assert(false, "error");

 }

 #ifndef PRODUCT

 void MacroAssembler::test() {

   ResourceMark rm;

   CodeBuffer cb("test", 10000, 10000);

   MacroAssembler* a = new MacroAssembler(&cb);

   VM_Version::allow_all();

   a->test_v9();

   a->test_v8_onlys();

   VM_Version::revert();

   StubRoutines::Sparc::test_stop_entry()();

 }

 #endif

 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {

   subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?

   Label no_extras;

   br( negative, true, pt, no_extras ); // if neg, clear reg

   delayed()->set(0, Rresult);          // annuled, so only if taken

   bind( no_extras );

 }

 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {

 #ifdef _LP64

   add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);

 #else

   add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);

 #endif

   bclr(1, Rresult);

   sll(Rresult, LogBytesPerWord, Rresult);  // Rresult has total frame bytes

 }

 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {

   calc_frame_size(Rextra_words, Rresult);

   neg(Rresult);

   save(SP, Rresult, SP);

 }

 // ---------------------------------------------------------

 Assembler::RCondition cond2rcond(Assembler::Condition c) {

   switch (c) {

     /*case zero: */

     case Assembler::equal:        return Assembler::rc_z;

     case Assembler::lessEqual:    return Assembler::rc_lez;

     case Assembler::less:         return Assembler::rc_lz;

     /*case notZero:*/

     case Assembler::notEqual:     return Assembler::rc_nz;

     case Assembler::greater:      return Assembler::rc_gz;

     case Assembler::greaterEqual: return Assembler::rc_gez;

   }

   ShouldNotReachHere();

   return Assembler::rc_z;

 }

 // compares register with zero and branches.  NOT FOR USE WITH 64-bit POINTERS

 void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) {

   tst(s1);

   br (c, a, p, L);

 }

 // Compares a pointer register with zero and branches on null.

 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.

 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {

   assert_not_delayed();

 #ifdef _LP64

   bpr( rc_z, a, p, s1, L );

 #else

   tst(s1);

   br ( zero, a, p, L );

 #endif

 }

 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {

   assert_not_delayed();

 #ifdef _LP64

   bpr( rc_nz, a, p, s1, L );

 #else

   tst(s1);

   br ( notZero, a, p, L );

 #endif

 }

 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,

                                      Register s1, address d,

                                      relocInfo::relocType rt ) {

   if (VM_Version::v9_instructions_work()) {

     bpr(rc, a, p, s1, d, rt);

   } else {

     tst(s1);

     br(reg_cond_to_cc_cond(rc), a, p, d, rt);

   }

 }

 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,

                                      Register s1, Label& L ) {

   if (VM_Version::v9_instructions_work()) {

     bpr(rc, a, p, s1, L);

   } else {

     tst(s1);

     br(reg_cond_to_cc_cond(rc), a, p, L);

   }

 }

 // instruction sequences factored across compiler & interpreter

 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,

                            Register Rb_hi, Register Rb_low,

                            Register Rresult) {

   Label check_low_parts, done;

   cmp(Ra_hi, Rb_hi );  // compare hi parts

   br(equal, true, pt, check_low_parts);

   delayed()->cmp(Ra_low, Rb_low); // test low parts

   // And, with an unsigned comparison, it does not matter if the numbers

   // are negative or not.

   // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.

   // The second one is bigger (unsignedly).

   // Other notes:  The first move in each triplet can be unconditional

   // (and therefore probably prefetchable).

   // And the equals case for the high part does not need testing,

   // since that triplet is reached only after finding the high halves differ.

   if (VM_Version::v9_instructions_work()) {

                                     mov  (                     -1, Rresult);

     ba( false, done );  delayed()-> movcc(greater, false, icc,  1, Rresult);

   }

   else {

     br(less,    true, pt, done); delayed()-> set(-1, Rresult);

     br(greater, true, pt, done); delayed()-> set( 1, Rresult);

   }

   bind( check_low_parts );

   if (VM_Version::v9_instructions_work()) {

     mov(                               -1, Rresult);

     movcc(equal,           false, icc,  0, Rresult);

     movcc(greaterUnsigned, false, icc,  1, Rresult);

   }

   else {

                                                     set(-1, Rresult);

     br(equal,           true, pt, done); delayed()->set( 0, Rresult);

     br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);

   }

   bind( done );

 }

 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {

   subcc(  G0, Rlow, Rlow );

   subc(   G0, Rhi,  Rhi  );

 }

 void MacroAssembler::lshl( Register Rin_high,  Register Rin_low,

                            Register Rcount,

                            Register Rout_high, Register Rout_low,

                            Register Rtemp ) {

   Register Ralt_count = Rtemp;

   Register Rxfer_bits = Rtemp;

   assert( Ralt_count != Rin_high

       &&  Ralt_count != Rin_low

       &&  Ralt_count != Rcount

       &&  Rxfer_bits != Rin_low

       &&  Rxfer_bits != Rin_high

       &&  Rxfer_bits != Rcount

       &&  Rxfer_bits != Rout_low

       &&  Rout_low   != Rin_high,

         "register alias checks");

   Label big_shift, done;

   // This code can be optimized to use the 64 bit shifts in V9.

   // Here we use the 32 bit shifts.

   and3( Rcount,         0x3f,           Rcount);     // take least significant 6 bits

   subcc(Rcount,         31,             Ralt_count);

   br(greater, true, pn, big_shift);

   delayed()->

   dec(Ralt_count);

   // shift < 32 bits, Ralt_count = Rcount-31

   // We get the transfer bits by shifting right by 32-count the low

   // register. This is done by shifting right by 31-count and then by one

   // more to take care of the special (rare) case where count is zero

   // (shifting by 32 would not work).

   neg(  Ralt_count                                 );

   // The order of the next two instructions is critical in the case where

   // Rin and Rout are the same and should not be reversed.

   srl(  Rin_low,        Ralt_count,     Rxfer_bits ); // shift right by 31-count

   if (Rcount != Rout_low) {

     sll(        Rin_low,        Rcount,         Rout_low   ); // low half

   }

   sll(  Rin_high,       Rcount,         Rout_high  );

   if (Rcount == Rout_low) {

     sll(        Rin_low,        Rcount,         Rout_low   ); // low half

   }

   srl(  Rxfer_bits,     1,              Rxfer_bits ); // shift right by one more

   ba (false, done);

   delayed()->

   or3(  Rout_high,      Rxfer_bits,     Rout_high);   // new hi value: or in shifted old hi part and xfer from low

   // shift >= 32 bits, Ralt_count = Rcount-32

   bind(big_shift);

   sll(  Rin_low,        Ralt_count,     Rout_high  );

   clr(  Rout_low                                   );

   bind(done);

 }

 void MacroAssembler::lshr( Register Rin_high,  Register Rin_low,

                            Register Rcount,

                            Register Rout_high, Register Rout_low,

                            Register Rtemp ) {

   Register Ralt_count = Rtemp;

   Register Rxfer_bits = Rtemp;

   assert( Ralt_count != Rin_high

       &&  Ralt_count != Rin_low

       &&  Ralt_count != Rcount

       &&  Rxfer_bits != Rin_low

       &&  Rxfer_bits != Rin_high

       &&  Rxfer_bits != Rcount

       &&  Rxfer_bits != Rout_high

       &&  Rout_high  != Rin_low,

         "register alias checks");

   Label big_shift, done;

   // This code can be optimized to use the 64 bit shifts in V9.

   // Here we use the 32 bit shifts.

   and3( Rcount,         0x3f,           Rcount);     // take least significant 6 bits

   subcc(Rcount,         31,             Ralt_count);

   br(greater, true, pn, big_shift);

   delayed()->dec(Ralt_count);

   // shift < 32 bits, Ralt_count = Rcount-31

   // We get the transfer bits by shifting left by 32-count the high

   // register. This is done by shifting left by 31-count and then by one

   // more to take care of the special (rare) case where count is zero

   // (shifting by 32 would not work).

   neg(  Ralt_count                                  );

   if (Rcount != Rout_low) {

     srl(        Rin_low,        Rcount,         Rout_low    );

   }

   // The order of the next two instructions is critical in the case where

   // Rin and Rout are the same and should not be reversed.

   sll(  Rin_high,       Ralt_count,     Rxfer_bits  ); // shift left by 31-count

   sra(  Rin_high,       Rcount,         Rout_high   ); // high half

   sll(  Rxfer_bits,     1,              Rxfer_bits  ); // shift left by one more

   if (Rcount == Rout_low) {

     srl(        Rin_low,        Rcount,         Rout_low    );

   }

   ba (false, done);

   delayed()->

   or3(  Rout_low,       Rxfer_bits,     Rout_low    ); // new low value: or shifted old low part and xfer from high

   // shift >= 32 bits, Ralt_count = Rcount-32

   bind(big_shift);

   sra(  Rin_high,       Ralt_count,     Rout_low    );

   sra(  Rin_high,       31,             Rout_high   ); // sign into hi

   bind( done );

 }

 void MacroAssembler::lushr( Register Rin_high,  Register Rin_low,

                             Register Rcount,

                             Register Rout_high, Register Rout_low,

                             Register Rtemp ) {

   Register Ralt_count = Rtemp;

   Register Rxfer_bits = Rtemp;

   assert( Ralt_count != Rin_high

       &&  Ralt_count != Rin_low

       &&  Ralt_count != Rcount

       &&  Rxfer_bits != Rin_low

       &&  Rxfer_bits != Rin_high

       &&  Rxfer_bits != Rcount

       &&  Rxfer_bits != Rout_high

       &&  Rout_high  != Rin_low,

         "register alias checks");

   Label big_shift, done;

   // This code can be optimized to use the 64 bit shifts in V9.

   // Here we use the 32 bit shifts.

   and3( Rcount,         0x3f,           Rcount);     // take least significant 6 bits

   subcc(Rcount,         31,             Ralt_count);

   br(greater, true, pn, big_shift);

   delayed()->dec(Ralt_count);

   // shift < 32 bits, Ralt_count = Rcount-31

   // We get the transfer bits by shifting left by 32-count the high

   // register. This is done by shifting left by 31-count and then by one

   // more to take care of the special (rare) case where count is zero

   // (shifting by 32 would not work).

   neg(  Ralt_count                                  );

   if (Rcount != Rout_low) {

     srl(        Rin_low,        Rcount,         Rout_low    );

   }

   // The order of the next two instructions is critical in the case where

   // Rin and Rout are the same and should not be reversed.

   sll(  Rin_high,       Ralt_count,     Rxfer_bits  ); // shift left by 31-count

   srl(  Rin_high,       Rcount,         Rout_high   ); // high half

   sll(  Rxfer_bits,     1,              Rxfer_bits  ); // shift left by one more

   if (Rcount == Rout_low) {

     srl(        Rin_low,        Rcount,         Rout_low    );

   }

   ba (false, done);

   delayed()->

   or3(  Rout_low,       Rxfer_bits,     Rout_low    ); // new low value: or shifted old low part and xfer from high

   // shift >= 32 bits, Ralt_count = Rcount-32

   bind(big_shift);

   srl(  Rin_high,       Ralt_count,     Rout_low    );

   clr(  Rout_high                                   );

   bind( done );

 }

 #ifdef _LP64

 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {

   cmp(Ra, Rb);

   mov(                       -1, Rresult);

   movcc(equal,   false, xcc,  0, Rresult);

   movcc(greater, false, xcc,  1, Rresult);

 }

 #endif

 void MacroAssembler::load_sized_value(Address src, Register dst,

                                       size_t size_in_bytes, bool is_signed) {

   switch (size_in_bytes) {

   case  8: ldx(src, dst); break;

   case  4: ld( src, dst); break;

   case  2: is_signed ? ldsh(src, dst) : lduh(src, dst); break;

   case  1: is_signed ? ldsb(src, dst) : ldub(src, dst); break;

   default: ShouldNotReachHere();

   }

 }

 void MacroAssembler::float_cmp( bool is_float, int unordered_result,

                                 FloatRegister Fa, FloatRegister Fb,

                                 Register Rresult) {

   fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);

   Condition lt = unordered_result == -1 ? f_unorderedOrLess    : f_less;

   Condition eq =                          f_equal;

   Condition gt = unordered_result ==  1 ? f_unorderedOrGreater : f_greater;

   if (VM_Version::v9_instructions_work()) {

     mov(                   -1, Rresult );

     movcc( eq, true, fcc0,  0, Rresult );

     movcc( gt, true, fcc0,  1, Rresult );

   } else {

     Label done;

                                          set( -1, Rresult );

     //fb(lt, true, pn, done); delayed()->set( -1, Rresult );

     fb( eq, true, pn, done);  delayed()->set(  0, Rresult );

     fb( gt, true, pn, done);  delayed()->set(  1, Rresult );

     bind (done);

   }

 }

 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)

 {

   if (VM_Version::v9_instructions_work()) {

     Assembler::fneg(w, s, d);

   } else {

     if (w == FloatRegisterImpl::S) {

       Assembler::fneg(w, s, d);

     } else if (w == FloatRegisterImpl::D) {

       // number() does a sanity check on the alignment.

       assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&

         ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");

       Assembler::fneg(FloatRegisterImpl::S, s, d);

       Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());

     } else {

       assert(w == FloatRegisterImpl::Q, "Invalid float register width");

       // number() does a sanity check on the alignment.

       assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&

         ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");

       Assembler::fneg(FloatRegisterImpl::S, s, d);

       Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());

       Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());

       Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());

     }

   }

 }

 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)

 {

   if (VM_Version::v9_instructions_work()) {

     Assembler::fmov(w, s, d);

   } else {

     if (w == FloatRegisterImpl::S) {

       Assembler::fmov(w, s, d);

     } else if (w == FloatRegisterImpl::D) {

       // number() does a sanity check on the alignment.

       assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&

         ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");

       Assembler::fmov(FloatRegisterImpl::S, s, d);

       Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());

     } else {

       assert(w == FloatRegisterImpl::Q, "Invalid float register width");

       // number() does a sanity check on the alignment.

       assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&

         ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");

       Assembler::fmov(FloatRegisterImpl::S, s, d);

       Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());

       Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());

       Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());

     }

   }

 }

 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)

 {

   if (VM_Version::v9_instructions_work()) {

     Assembler::fabs(w, s, d);

   } else {

     if (w == FloatRegisterImpl::S) {

       Assembler::fabs(w, s, d);

     } else if (w == FloatRegisterImpl::D) {

       // number() does a sanity check on the alignment.

       assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&

         ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");

       Assembler::fabs(FloatRegisterImpl::S, s, d);

       Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());

     } else {

       assert(w == FloatRegisterImpl::Q, "Invalid float register width");

       // number() does a sanity check on the alignment.

       assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&

        ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");

       Assembler::fabs(FloatRegisterImpl::S, s, d);

       Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());

       Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());

       Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());

     }

   }

 }

 void MacroAssembler::save_all_globals_into_locals() {

   mov(G1,L1);

   mov(G2,L2);

   mov(G3,L3);

   mov(G4,L4);

   mov(G5,L5);

   mov(G6,L6);

   mov(G7,L7);

 }

 void MacroAssembler::restore_globals_from_locals() {

   mov(L1,G1);

   mov(L2,G2);

   mov(L3,G3);

   mov(L4,G4);

   mov(L5,G5);

   mov(L6,G6);

   mov(L7,G7);

 }

 // Use for 64 bit operation.

 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)

 {

   // store ptr_reg as the new top value

 #ifdef _LP64

   casx(top_ptr_reg, top_reg, ptr_reg);

 #else

   cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm);

 #endif // _LP64

 }

 // [RGV] This routine does not handle 64 bit operations.

 //       use casx_under_lock() or casx directly!!!

 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)

 {

   // store ptr_reg as the new top value

   if (VM_Version::v9_instructions_work()) {

     cas(top_ptr_reg, top_reg, ptr_reg);

   } else {

     // If the register is not an out nor global, it is not visible

     // after the save.  Allocate a register for it, save its

     // value in the register save area (the save may not flush

     // registers to the save area).

     Register top_ptr_reg_after_save;

     Register top_reg_after_save;

     Register ptr_reg_after_save;

     if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) {

       top_ptr_reg_after_save = top_ptr_reg->after_save();

     } else {

       Address reg_save_addr = top_ptr_reg->address_in_saved_window();

       top_ptr_reg_after_save = L0;

       st(top_ptr_reg, reg_save_addr);

     }

     if (top_reg->is_out() || top_reg->is_global()) {

       top_reg_after_save = top_reg->after_save();

     } else {

       Address reg_save_addr = top_reg->address_in_saved_window();

       top_reg_after_save = L1;

       st(top_reg, reg_save_addr);

     }

     if (ptr_reg->is_out() || ptr_reg->is_global()) {

       ptr_reg_after_save = ptr_reg->after_save();

     } else {

       Address reg_save_addr = ptr_reg->address_in_saved_window();

       ptr_reg_after_save = L2;

       st(ptr_reg, reg_save_addr);

     }

     const Register& lock_reg = L3;

     const Register& lock_ptr_reg = L4;

     const Register& value_reg = L5;

     const Register& yield_reg = L6;

     const Register& yieldall_reg = L7;

     save_frame();

     if (top_ptr_reg_after_save == L0) {

       ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save);

     }

     if (top_reg_after_save == L1) {

       ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);

     }

     if (ptr_reg_after_save == L2) {

       ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);

     }

     Label(retry_get_lock);

     Label(not_same);

     Label(dont_yield);

     assert(lock_addr, "lock_address should be non null for v8");

     set((intptr_t)lock_addr, lock_ptr_reg);

     // Initialize yield counter

     mov(G0,yield_reg);

     mov(G0, yieldall_reg);

     set(StubRoutines::Sparc::locked, lock_reg);

     bind(retry_get_lock);

     cmp(yield_reg, V8AtomicOperationUnderLockSpinCount);

     br(Assembler::less, false, Assembler::pt, dont_yield);