Tue, 06 Dec 2011 18:28:51 -0500
7117052: instanceKlass::_init_state can be u1 type
Summary: Change instanceKlass::_init_state field to u1 type.
Reviewed-by: bdelsart, coleenp, dholmes, phh, never
Contributed-by: Jiangli Zhou <jiangli.zhou@oracle.com>
1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 extern bool use_block_zeroing(Node* count);
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
471 %}
473 source %{
474 #define __ _masm.
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
532 // ****************************************************************************
534 // REQUIRED FUNCTIONALITY
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedOops) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_oop_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if( Assembler::is_simm13(v_off) ) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 int bit_width = width * 8;
682 jlong elt_val = con;
683 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
684 jlong val = elt_val;
685 for (int i = 0; i < count - 1; i++) {
686 val <<= bit_width;
687 val |= elt_val;
688 }
689 jdouble dval = *((jdouble*) &val); // coerce to double type
690 return dval;
691 }
693 // Standard Sparc opcode form2 field breakdown
694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
695 f0 &= (1<<19)-1; // Mask displacement to 19 bits
696 int op = (f30 << 30) |
697 (f29 << 29) |
698 (f25 << 25) |
699 (f22 << 22) |
700 (f20 << 20) |
701 (f19 << 19) |
702 (f0 << 0);
703 cbuf.insts()->emit_int32(op);
704 }
706 // Standard Sparc opcode form2 field breakdown
707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
708 f0 >>= 10; // Drop 10 bits
709 f0 &= (1<<22)-1; // Mask displacement to 22 bits
710 int op = (f30 << 30) |
711 (f25 << 25) |
712 (f22 << 22) |
713 (f0 << 0);
714 cbuf.insts()->emit_int32(op);
715 }
717 // Standard Sparc opcode form3 field breakdown
718 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
719 int op = (f30 << 30) |
720 (f25 << 25) |
721 (f19 << 19) |
722 (f14 << 14) |
723 (f5 << 5) |
724 (f0 << 0);
725 cbuf.insts()->emit_int32(op);
726 }
728 // Standard Sparc opcode form3 field breakdown
729 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
730 simm13 &= (1<<13)-1; // Mask to 13 bits
731 int op = (f30 << 30) |
732 (f25 << 25) |
733 (f19 << 19) |
734 (f14 << 14) |
735 (1 << 13) | // bit to indicate immediate-mode
736 (simm13<<0);
737 cbuf.insts()->emit_int32(op);
738 }
740 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
741 simm10 &= (1<<10)-1; // Mask to 10 bits
742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
743 }
745 #ifdef ASSERT
746 // Helper function for VerifyOops in emit_form3_mem_reg
747 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
748 warning("VerifyOops encountered unexpected instruction:");
749 n->dump(2);
750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
751 }
752 #endif
755 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
756 int src1_enc, int disp32, int src2_enc, int dst_enc) {
758 #ifdef ASSERT
759 // The following code implements the +VerifyOops feature.
760 // It verifies oop values which are loaded into or stored out of
761 // the current method activation. +VerifyOops complements techniques
762 // like ScavengeALot, because it eagerly inspects oops in transit,
763 // as they enter or leave the stack, as opposed to ScavengeALot,
764 // which inspects oops "at rest", in the stack or heap, at safepoints.
765 // For this reason, +VerifyOops can sometimes detect bugs very close
766 // to their point of creation. It can also serve as a cross-check
767 // on the validity of oop maps, when used toegether with ScavengeALot.
769 // It would be good to verify oops at other points, especially
770 // when an oop is used as a base pointer for a load or store.
771 // This is presently difficult, because it is hard to know when
772 // a base address is biased or not. (If we had such information,
773 // it would be easy and useful to make a two-argument version of
774 // verify_oop which unbiases the base, and performs verification.)
776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
777 bool is_verified_oop_base = false;
778 bool is_verified_oop_load = false;
779 bool is_verified_oop_store = false;
780 int tmp_enc = -1;
781 if (VerifyOops && src1_enc != R_SP_enc) {
782 // classify the op, mainly for an assert check
783 int st_op = 0, ld_op = 0;
784 switch (primary) {
785 case Assembler::stb_op3: st_op = Op_StoreB; break;
786 case Assembler::sth_op3: st_op = Op_StoreC; break;
787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
788 case Assembler::stw_op3: st_op = Op_StoreI; break;
789 case Assembler::std_op3: st_op = Op_StoreL; break;
790 case Assembler::stf_op3: st_op = Op_StoreF; break;
791 case Assembler::stdf_op3: st_op = Op_StoreD; break;
793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
794 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
795 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
796 case Assembler::ldx_op3: // may become LoadP or stay LoadI
797 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
798 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
799 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
800 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
801 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
805 default: ShouldNotReachHere();
806 }
807 if (tertiary == REGP_OP) {
808 if (st_op == Op_StoreI) st_op = Op_StoreP;
809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
810 else ShouldNotReachHere();
811 if (st_op) {
812 // a store
813 // inputs are (0:control, 1:memory, 2:address, 3:value)
814 Node* n2 = n->in(3);
815 if (n2 != NULL) {
816 const Type* t = n2->bottom_type();
817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 } else {
820 // a load
821 const Type* t = n->bottom_type();
822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 }
826 if (ld_op) {
827 // a Load
828 // inputs are (0:control, 1:memory, 2:address)
829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
830 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
831 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
832 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
833 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
834 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
835 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
839 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
841 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
843 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
845 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
846 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
847 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
848 !(n->rule() == loadUB_rule)) {
849 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
850 }
851 } else if (st_op) {
852 // a Store
853 // inputs are (0:control, 1:memory, 2:address, 3:value)
854 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
855 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
856 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
857 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
858 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
860 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
862 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
863 verify_oops_warning(n, n->ideal_Opcode(), st_op);
864 }
865 }
867 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
868 Node* addr = n->in(2);
869 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
870 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
871 if (atype != NULL) {
872 intptr_t offset = get_offset_from_base(n, atype, disp32);
873 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
874 if (offset != offset_2) {
875 get_offset_from_base(n, atype, disp32);
876 get_offset_from_base_2(n, atype, disp32);
877 }
878 assert(offset == offset_2, "different offsets");
879 if (offset == disp32) {
880 // we now know that src1 is a true oop pointer
881 is_verified_oop_base = true;
882 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
883 if( primary == Assembler::ldd_op3 ) {
884 is_verified_oop_base = false; // Cannot 'ldd' into O7
885 } else {
886 tmp_enc = dst_enc;
887 dst_enc = R_O7_enc; // Load into O7; preserve source oop
888 assert(src1_enc != dst_enc, "");
889 }
890 }
891 }
892 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
893 || offset == oopDesc::mark_offset_in_bytes())) {
894 // loading the mark should not be allowed either, but
895 // we don't check this since it conflicts with InlineObjectHash
896 // usage of LoadINode to get the mark. We could keep the
897 // check if we create a new LoadMarkNode
898 // but do not verify the object before its header is initialized
899 ShouldNotReachHere();
900 }
901 }
902 }
903 }
904 }
905 #endif
907 uint instr;
908 instr = (Assembler::ldst_op << 30)
909 | (dst_enc << 25)
910 | (primary << 19)
911 | (src1_enc << 14);
913 uint index = src2_enc;
914 int disp = disp32;
916 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
917 disp += STACK_BIAS;
919 // We should have a compiler bailout here rather than a guarantee.
920 // Better yet would be some mechanism to handle variable-size matches correctly.
921 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
923 if( disp == 0 ) {
924 // use reg-reg form
925 // bit 13 is already zero
926 instr |= index;
927 } else {
928 // use reg-imm form
929 instr |= 0x00002000; // set bit 13 to one
930 instr |= disp & 0x1FFF;
931 }
933 cbuf.insts()->emit_int32(instr);
935 #ifdef ASSERT
936 {
937 MacroAssembler _masm(&cbuf);
938 if (is_verified_oop_base) {
939 __ verify_oop(reg_to_register_object(src1_enc));
940 }
941 if (is_verified_oop_store) {
942 __ verify_oop(reg_to_register_object(dst_enc));
943 }
944 if (tmp_enc != -1) {
945 __ mov(O7, reg_to_register_object(tmp_enc));
946 }
947 if (is_verified_oop_load) {
948 __ verify_oop(reg_to_register_object(dst_enc));
949 }
950 }
951 #endif
952 }
954 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
955 // The method which records debug information at every safepoint
956 // expects the call to be the first instruction in the snippet as
957 // it creates a PcDesc structure which tracks the offset of a call
958 // from the start of the codeBlob. This offset is computed as
959 // code_end() - code_begin() of the code which has been emitted
960 // so far.
961 // In this particular case we have skirted around the problem by
962 // putting the "mov" instruction in the delay slot but the problem
963 // may bite us again at some other point and a cleaner/generic
964 // solution using relocations would be needed.
965 MacroAssembler _masm(&cbuf);
966 __ set_inst_mark();
968 // We flush the current window just so that there is a valid stack copy
969 // the fact that the current window becomes active again instantly is
970 // not a problem there is nothing live in it.
972 #ifdef ASSERT
973 int startpos = __ offset();
974 #endif /* ASSERT */
976 __ call((address)entry_point, rtype);
978 if (preserve_g2) __ delayed()->mov(G2, L7);
979 else __ delayed()->nop();
981 if (preserve_g2) __ mov(L7, G2);
983 #ifdef ASSERT
984 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
985 #ifdef _LP64
986 // Trash argument dump slots.
987 __ set(0xb0b8ac0db0b8ac0d, G1);
988 __ mov(G1, G5);
989 __ stx(G1, SP, STACK_BIAS + 0x80);
990 __ stx(G1, SP, STACK_BIAS + 0x88);
991 __ stx(G1, SP, STACK_BIAS + 0x90);
992 __ stx(G1, SP, STACK_BIAS + 0x98);
993 __ stx(G1, SP, STACK_BIAS + 0xA0);
994 __ stx(G1, SP, STACK_BIAS + 0xA8);
995 #else // _LP64
996 // this is also a native call, so smash the first 7 stack locations,
997 // and the various registers
999 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1000 // while [SP+0x44..0x58] are the argument dump slots.
1001 __ set((intptr_t)0xbaadf00d, G1);
1002 __ mov(G1, G5);
1003 __ sllx(G1, 32, G1);
1004 __ or3(G1, G5, G1);
1005 __ mov(G1, G5);
1006 __ stx(G1, SP, 0x40);
1007 __ stx(G1, SP, 0x48);
1008 __ stx(G1, SP, 0x50);
1009 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1010 #endif // _LP64
1011 }
1012 #endif /*ASSERT*/
1013 }
1015 //=============================================================================
1016 // REQUIRED FUNCTIONALITY for encoding
1017 void emit_lo(CodeBuffer &cbuf, int val) { }
1018 void emit_hi(CodeBuffer &cbuf, int val) { }
1021 //=============================================================================
1022 const bool Matcher::constant_table_absolute_addressing = false;
1023 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1025 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1026 Compile* C = ra_->C;
1027 Compile::ConstantTable& constant_table = C->constant_table();
1028 MacroAssembler _masm(&cbuf);
1030 Register r = as_Register(ra_->get_encode(this));
1031 CodeSection* cs = __ code()->consts();
1032 int consts_size = cs->align_at_start(cs->size());
1034 if (UseRDPCForConstantTableBase) {
1035 // For the following RDPC logic to work correctly the consts
1036 // section must be allocated right before the insts section. This
1037 // assert checks for that. The layout and the SECT_* constants
1038 // are defined in src/share/vm/asm/codeBuffer.hpp.
1039 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1040 int offset = __ offset();
1041 int disp;
1043 // If the displacement from the current PC to the constant table
1044 // base fits into simm13 we set the constant table base to the
1045 // current PC.
1046 if (__ is_simm13(-(consts_size + offset))) {
1047 constant_table.set_table_base_offset(-(consts_size + offset));
1048 disp = 0;
1049 } else {
1050 // If the offset of the top constant (last entry in the table)
1051 // fits into simm13 we set the constant table base to the actual
1052 // table base.
1053 if (__ is_simm13(constant_table.top_offset())) {
1054 constant_table.set_table_base_offset(0);
1055 disp = consts_size + offset;
1056 } else {
1057 // Otherwise we set the constant table base in the middle of the
1058 // constant table.
1059 int half_consts_size = consts_size / 2;
1060 assert(half_consts_size * 2 == consts_size, "sanity");
1061 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1062 disp = half_consts_size + offset;
1063 }
1064 }
1066 __ rdpc(r);
1068 if (disp != 0) {
1069 assert(r != O7, "need temporary");
1070 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1071 }
1072 }
1073 else {
1074 // Materialize the constant table base.
1075 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1076 address baseaddr = cs->start() + -(constant_table.table_base_offset());
1077 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1078 AddressLiteral base(baseaddr, rspec);
1079 __ set(base, r);
1080 }
1081 }
1083 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1084 if (UseRDPCForConstantTableBase) {
1085 // This is really the worst case but generally it's only 1 instruction.
1086 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1087 } else {
1088 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1089 }
1090 }
1092 #ifndef PRODUCT
1093 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1094 char reg[128];
1095 ra_->dump_register(this, reg);
1096 if (UseRDPCForConstantTableBase) {
1097 st->print("RDPC %s\t! constant table base", reg);
1098 } else {
1099 st->print("SET &constanttable,%s\t! constant table base", reg);
1100 }
1101 }
1102 #endif
1105 //=============================================================================
1107 #ifndef PRODUCT
1108 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1109 Compile* C = ra_->C;
1111 for (int i = 0; i < OptoPrologueNops; i++) {
1112 st->print_cr("NOP"); st->print("\t");
1113 }
1115 if( VerifyThread ) {
1116 st->print_cr("Verify_Thread"); st->print("\t");
1117 }
1119 size_t framesize = C->frame_slots() << LogBytesPerInt;
1121 // Calls to C2R adapters often do not accept exceptional returns.
1122 // We require that their callers must bang for them. But be careful, because
1123 // some VM calls (such as call site linkage) can use several kilobytes of
1124 // stack. But the stack safety zone should account for that.
1125 // See bugs 4446381, 4468289, 4497237.
1126 if (C->need_stack_bang(framesize)) {
1127 st->print_cr("! stack bang"); st->print("\t");
1128 }
1130 if (Assembler::is_simm13(-framesize)) {
1131 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1132 } else {
1133 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1134 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1135 st->print ("SAVE R_SP,R_G3,R_SP");
1136 }
1138 }
1139 #endif
1141 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1142 Compile* C = ra_->C;
1143 MacroAssembler _masm(&cbuf);
1145 for (int i = 0; i < OptoPrologueNops; i++) {
1146 __ nop();
1147 }
1149 __ verify_thread();
1151 size_t framesize = C->frame_slots() << LogBytesPerInt;
1152 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1153 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1155 // Calls to C2R adapters often do not accept exceptional returns.
1156 // We require that their callers must bang for them. But be careful, because
1157 // some VM calls (such as call site linkage) can use several kilobytes of
1158 // stack. But the stack safety zone should account for that.
1159 // See bugs 4446381, 4468289, 4497237.
1160 if (C->need_stack_bang(framesize)) {
1161 __ generate_stack_overflow_check(framesize);
1162 }
1164 if (Assembler::is_simm13(-framesize)) {
1165 __ save(SP, -framesize, SP);
1166 } else {
1167 __ sethi(-framesize & ~0x3ff, G3);
1168 __ add(G3, -framesize & 0x3ff, G3);
1169 __ save(SP, G3, SP);
1170 }
1171 C->set_frame_complete( __ offset() );
1172 }
1174 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1175 return MachNode::size(ra_);
1176 }
1178 int MachPrologNode::reloc() const {
1179 return 10; // a large enough number
1180 }
1182 //=============================================================================
1183 #ifndef PRODUCT
1184 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1185 Compile* C = ra_->C;
1187 if( do_polling() && ra_->C->is_method_compilation() ) {
1188 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1189 #ifdef _LP64
1190 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1191 #else
1192 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1193 #endif
1194 }
1196 if( do_polling() )
1197 st->print("RET\n\t");
1199 st->print("RESTORE");
1200 }
1201 #endif
1203 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1204 MacroAssembler _masm(&cbuf);
1205 Compile* C = ra_->C;
1207 __ verify_thread();
1209 // If this does safepoint polling, then do it here
1210 if( do_polling() && ra_->C->is_method_compilation() ) {
1211 AddressLiteral polling_page(os::get_polling_page());
1212 __ sethi(polling_page, L0);
1213 __ relocate(relocInfo::poll_return_type);
1214 __ ld_ptr( L0, 0, G0 );
1215 }
1217 // If this is a return, then stuff the restore in the delay slot
1218 if( do_polling() ) {
1219 __ ret();
1220 __ delayed()->restore();
1221 } else {
1222 __ restore();
1223 }
1224 }
1226 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1227 return MachNode::size(ra_);
1228 }
1230 int MachEpilogNode::reloc() const {
1231 return 16; // a large enough number
1232 }
1234 const Pipeline * MachEpilogNode::pipeline() const {
1235 return MachNode::pipeline_class();
1236 }
1238 int MachEpilogNode::safepoint_offset() const {
1239 assert( do_polling(), "no return for this epilog node");
1240 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1241 }
1243 //=============================================================================
1245 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1246 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1247 static enum RC rc_class( OptoReg::Name reg ) {
1248 if( !OptoReg::is_valid(reg) ) return rc_bad;
1249 if (OptoReg::is_stack(reg)) return rc_stack;
1250 VMReg r = OptoReg::as_VMReg(reg);
1251 if (r->is_Register()) return rc_int;
1252 assert(r->is_FloatRegister(), "must be");
1253 return rc_float;
1254 }
1256 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1257 if( cbuf ) {
1258 // Better yet would be some mechanism to handle variable-size matches correctly
1259 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1260 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1261 } else {
1262 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1263 }
1264 }
1265 #ifndef PRODUCT
1266 else if( !do_size ) {
1267 if( size != 0 ) st->print("\n\t");
1268 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1269 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1270 }
1271 #endif
1272 return size+4;
1273 }
1275 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1276 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1277 #ifndef PRODUCT
1278 else if( !do_size ) {
1279 if( size != 0 ) st->print("\n\t");
1280 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1281 }
1282 #endif
1283 return size+4;
1284 }
1286 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1287 PhaseRegAlloc *ra_,
1288 bool do_size,
1289 outputStream* st ) const {
1290 // Get registers to move
1291 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1292 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1293 OptoReg::Name dst_second = ra_->get_reg_second(this );
1294 OptoReg::Name dst_first = ra_->get_reg_first(this );
1296 enum RC src_second_rc = rc_class(src_second);
1297 enum RC src_first_rc = rc_class(src_first);
1298 enum RC dst_second_rc = rc_class(dst_second);
1299 enum RC dst_first_rc = rc_class(dst_first);
1301 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1303 // Generate spill code!
1304 int size = 0;
1306 if( src_first == dst_first && src_second == dst_second )
1307 return size; // Self copy, no move
1309 // --------------------------------------
1310 // Check for mem-mem move. Load into unused float registers and fall into
1311 // the float-store case.
1312 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1313 int offset = ra_->reg2offset(src_first);
1314 // Further check for aligned-adjacent pair, so we can use a double load
1315 if( (src_first&1)==0 && src_first+1 == src_second ) {
1316 src_second = OptoReg::Name(R_F31_num);
1317 src_second_rc = rc_float;
1318 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1319 } else {
1320 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1321 }
1322 src_first = OptoReg::Name(R_F30_num);
1323 src_first_rc = rc_float;
1324 }
1326 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1327 int offset = ra_->reg2offset(src_second);
1328 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1329 src_second = OptoReg::Name(R_F31_num);
1330 src_second_rc = rc_float;
1331 }
1333 // --------------------------------------
1334 // Check for float->int copy; requires a trip through memory
1335 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1336 int offset = frame::register_save_words*wordSize;
1337 if (cbuf) {
1338 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1339 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1340 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1341 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1342 }
1343 #ifndef PRODUCT
1344 else if (!do_size) {
1345 if (size != 0) st->print("\n\t");
1346 st->print( "SUB R_SP,16,R_SP\n");
1347 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1348 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1349 st->print("\tADD R_SP,16,R_SP\n");
1350 }
1351 #endif
1352 size += 16;
1353 }
1355 // Check for float->int copy on T4
1356 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1357 // Further check for aligned-adjacent pair, so we can use a double move
1358 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1359 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1360 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1361 }
1362 // Check for int->float copy on T4
1363 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1364 // Further check for aligned-adjacent pair, so we can use a double move
1365 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1366 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1367 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1368 }
1370 // --------------------------------------
1371 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1372 // In such cases, I have to do the big-endian swap. For aligned targets, the
1373 // hardware does the flop for me. Doubles are always aligned, so no problem
1374 // there. Misaligned sources only come from native-long-returns (handled
1375 // special below).
1376 #ifndef _LP64
1377 if( src_first_rc == rc_int && // source is already big-endian
1378 src_second_rc != rc_bad && // 64-bit move
1379 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1380 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1381 // Do the big-endian flop.
1382 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1383 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1384 }
1385 #endif
1387 // --------------------------------------
1388 // Check for integer reg-reg copy
1389 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1390 #ifndef _LP64
1391 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1392 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1393 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1394 // operand contains the least significant word of the 64-bit value and vice versa.
1395 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1396 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1397 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1398 if( cbuf ) {
1399 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1400 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1401 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1402 #ifndef PRODUCT
1403 } else if( !do_size ) {
1404 if( size != 0 ) st->print("\n\t");
1405 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1406 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1407 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1408 #endif
1409 }
1410 return size+12;
1411 }
1412 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1413 // returning a long value in I0/I1
1414 // a SpillCopy must be able to target a return instruction's reg_class
1415 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1416 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1417 // operand contains the least significant word of the 64-bit value and vice versa.
1418 OptoReg::Name tdest = dst_first;
1420 if (src_first == dst_first) {
1421 tdest = OptoReg::Name(R_O7_num);
1422 size += 4;
1423 }
1425 if( cbuf ) {
1426 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1427 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1428 // ShrL_reg_imm6
1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1430 // ShrR_reg_imm6 src, 0, dst
1431 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1432 if (tdest != dst_first) {
1433 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1434 }
1435 }
1436 #ifndef PRODUCT
1437 else if( !do_size ) {
1438 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1439 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1440 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1441 if (tdest != dst_first) {
1442 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1443 }
1444 }
1445 #endif // PRODUCT
1446 return size+8;
1447 }
1448 #endif // !_LP64
1449 // Else normal reg-reg copy
1450 assert( src_second != dst_first, "smashed second before evacuating it" );
1451 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1452 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1453 // This moves an aligned adjacent pair.
1454 // See if we are done.
1455 if( src_first+1 == src_second && dst_first+1 == dst_second )
1456 return size;
1457 }
1459 // Check for integer store
1460 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1461 int offset = ra_->reg2offset(dst_first);
1462 // Further check for aligned-adjacent pair, so we can use a double store
1463 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1464 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1465 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1466 }
1468 // Check for integer load
1469 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1470 int offset = ra_->reg2offset(src_first);
1471 // Further check for aligned-adjacent pair, so we can use a double load
1472 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1473 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1474 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1475 }
1477 // Check for float reg-reg copy
1478 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1479 // Further check for aligned-adjacent pair, so we can use a double move
1480 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1481 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1482 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1483 }
1485 // Check for float store
1486 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1487 int offset = ra_->reg2offset(dst_first);
1488 // Further check for aligned-adjacent pair, so we can use a double store
1489 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1490 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1491 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1492 }
1494 // Check for float load
1495 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1496 int offset = ra_->reg2offset(src_first);
1497 // Further check for aligned-adjacent pair, so we can use a double load
1498 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1499 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1500 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1501 }
1503 // --------------------------------------------------------------------
1504 // Check for hi bits still needing moving. Only happens for misaligned
1505 // arguments to native calls.
1506 if( src_second == dst_second )
1507 return size; // Self copy; no move
1508 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1510 #ifndef _LP64
1511 // In the LP64 build, all registers can be moved as aligned/adjacent
1512 // pairs, so there's never any need to move the high bits separately.
1513 // The 32-bit builds have to deal with the 32-bit ABI which can force
1514 // all sorts of silly alignment problems.
1516 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1517 // 32-bits of a 64-bit register, but are needed in low bits of another
1518 // register (else it's a hi-bits-to-hi-bits copy which should have
1519 // happened already as part of a 64-bit move)
1520 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1521 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1522 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1523 // Shift src_second down to dst_second's low bits.
1524 if( cbuf ) {
1525 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1526 #ifndef PRODUCT
1527 } else if( !do_size ) {
1528 if( size != 0 ) st->print("\n\t");
1529 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1530 #endif
1531 }
1532 return size+4;
1533 }
1535 // Check for high word integer store. Must down-shift the hi bits
1536 // into a temp register, then fall into the case of storing int bits.
1537 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1538 // Shift src_second down to dst_second's low bits.
1539 if( cbuf ) {
1540 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1541 #ifndef PRODUCT
1542 } else if( !do_size ) {
1543 if( size != 0 ) st->print("\n\t");
1544 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1545 #endif
1546 }
1547 size+=4;
1548 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1549 }
1551 // Check for high word integer load
1552 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1553 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1555 // Check for high word integer store
1556 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1557 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1559 // Check for high word float store
1560 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1561 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1563 #endif // !_LP64
1565 Unimplemented();
1566 }
1568 #ifndef PRODUCT
1569 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1570 implementation( NULL, ra_, false, st );
1571 }
1572 #endif
1574 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1575 implementation( &cbuf, ra_, false, NULL );
1576 }
1578 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1579 return implementation( NULL, ra_, true, NULL );
1580 }
1582 //=============================================================================
1583 #ifndef PRODUCT
1584 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1585 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1586 }
1587 #endif
1589 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1590 MacroAssembler _masm(&cbuf);
1591 for(int i = 0; i < _count; i += 1) {
1592 __ nop();
1593 }
1594 }
1596 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1597 return 4 * _count;
1598 }
1601 //=============================================================================
1602 #ifndef PRODUCT
1603 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1604 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1605 int reg = ra_->get_reg_first(this);
1606 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1607 }
1608 #endif
1610 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1611 MacroAssembler _masm(&cbuf);
1612 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1613 int reg = ra_->get_encode(this);
1615 if (Assembler::is_simm13(offset)) {
1616 __ add(SP, offset, reg_to_register_object(reg));
1617 } else {
1618 __ set(offset, O7);
1619 __ add(SP, O7, reg_to_register_object(reg));
1620 }
1621 }
1623 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1624 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1625 assert(ra_ == ra_->C->regalloc(), "sanity");
1626 return ra_->C->scratch_emit_size(this);
1627 }
1629 //=============================================================================
1631 // emit call stub, compiled java to interpretor
1632 void emit_java_to_interp(CodeBuffer &cbuf ) {
1634 // Stub is fixed up when the corresponding call is converted from calling
1635 // compiled code to calling interpreted code.
1636 // set (empty), G5
1637 // jmp -1
1639 address mark = cbuf.insts_mark(); // get mark within main instrs section
1641 MacroAssembler _masm(&cbuf);
1643 address base =
1644 __ start_a_stub(Compile::MAX_stubs_size);
1645 if (base == NULL) return; // CodeBuffer::expand failed
1647 // static stub relocation stores the instruction address of the call
1648 __ relocate(static_stub_Relocation::spec(mark));
1650 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1652 __ set_inst_mark();
1653 AddressLiteral addrlit(-1);
1654 __ JUMP(addrlit, G3, 0);
1656 __ delayed()->nop();
1658 // Update current stubs pointer and restore code_end.
1659 __ end_a_stub();
1660 }
1662 // size of call stub, compiled java to interpretor
1663 uint size_java_to_interp() {
1664 // This doesn't need to be accurate but it must be larger or equal to
1665 // the real size of the stub.
1666 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1667 NativeJump::instruction_size + // sethi; jmp; nop
1668 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1669 }
1670 // relocation entries for call stub, compiled java to interpretor
1671 uint reloc_java_to_interp() {
1672 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1673 }
1676 //=============================================================================
1677 #ifndef PRODUCT
1678 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1679 st->print_cr("\nUEP:");
1680 #ifdef _LP64
1681 if (UseCompressedOops) {
1682 assert(Universe::heap() != NULL, "java heap should be initialized");
1683 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1684 st->print_cr("\tSLL R_G5,3,R_G5");
1685 if (Universe::narrow_oop_base() != NULL)
1686 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1687 } else {
1688 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1689 }
1690 st->print_cr("\tCMP R_G5,R_G3" );
1691 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1692 #else // _LP64
1693 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1694 st->print_cr("\tCMP R_G5,R_G3" );
1695 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1696 #endif // _LP64
1697 }
1698 #endif
1700 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1701 MacroAssembler _masm(&cbuf);
1702 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1703 Register temp_reg = G3;
1704 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1706 // Load klass from receiver
1707 __ load_klass(O0, temp_reg);
1708 // Compare against expected klass
1709 __ cmp(temp_reg, G5_ic_reg);
1710 // Branch to miss code, checks xcc or icc depending
1711 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1712 }
1714 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1715 return MachNode::size(ra_);
1716 }
1719 //=============================================================================
1721 uint size_exception_handler() {
1722 if (TraceJumps) {
1723 return (400); // just a guess
1724 }
1725 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1726 }
1728 uint size_deopt_handler() {
1729 if (TraceJumps) {
1730 return (400); // just a guess
1731 }
1732 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1733 }
1735 // Emit exception handler code.
1736 int emit_exception_handler(CodeBuffer& cbuf) {
1737 Register temp_reg = G3;
1738 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1739 MacroAssembler _masm(&cbuf);
1741 address base =
1742 __ start_a_stub(size_exception_handler());
1743 if (base == NULL) return 0; // CodeBuffer::expand failed
1745 int offset = __ offset();
1747 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1748 __ delayed()->nop();
1750 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1752 __ end_a_stub();
1754 return offset;
1755 }
1757 int emit_deopt_handler(CodeBuffer& cbuf) {
1758 // Can't use any of the current frame's registers as we may have deopted
1759 // at a poll and everything (including G3) can be live.
1760 Register temp_reg = L0;
1761 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1762 MacroAssembler _masm(&cbuf);
1764 address base =
1765 __ start_a_stub(size_deopt_handler());
1766 if (base == NULL) return 0; // CodeBuffer::expand failed
1768 int offset = __ offset();
1769 __ save_frame(0);
1770 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1771 __ delayed()->restore();
1773 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1775 __ end_a_stub();
1776 return offset;
1778 }
1780 // Given a register encoding, produce a Integer Register object
1781 static Register reg_to_register_object(int register_encoding) {
1782 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1783 return as_Register(register_encoding);
1784 }
1786 // Given a register encoding, produce a single-precision Float Register object
1787 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1788 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1789 return as_SingleFloatRegister(register_encoding);
1790 }
1792 // Given a register encoding, produce a double-precision Float Register object
1793 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1794 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1795 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1796 return as_DoubleFloatRegister(register_encoding);
1797 }
1799 const bool Matcher::match_rule_supported(int opcode) {
1800 if (!has_match_rule(opcode))
1801 return false;
1803 switch (opcode) {
1804 case Op_CountLeadingZerosI:
1805 case Op_CountLeadingZerosL:
1806 case Op_CountTrailingZerosI:
1807 case Op_CountTrailingZerosL:
1808 if (!UsePopCountInstruction)
1809 return false;
1810 break;
1811 }
1813 return true; // Per default match rules are supported.
1814 }
1816 int Matcher::regnum_to_fpu_offset(int regnum) {
1817 return regnum - 32; // The FP registers are in the second chunk
1818 }
1820 #ifdef ASSERT
1821 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1822 #endif
1824 // Vector width in bytes
1825 const uint Matcher::vector_width_in_bytes(void) {
1826 return 8;
1827 }
1829 // Vector ideal reg
1830 const uint Matcher::vector_ideal_reg(void) {
1831 return Op_RegD;
1832 }
1834 // USII supports fxtof through the whole range of number, USIII doesn't
1835 const bool Matcher::convL2FSupported(void) {
1836 return VM_Version::has_fast_fxtof();
1837 }
1839 // Is this branch offset short enough that a short branch can be used?
1840 //
1841 // NOTE: If the platform does not provide any short branch variants, then
1842 // this method should return false for offset 0.
1843 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1844 // The passed offset is relative to address of the branch.
1845 // Don't need to adjust the offset.
1846 return UseCBCond && Assembler::is_simm(offset, 12);
1847 }
1849 const bool Matcher::isSimpleConstant64(jlong value) {
1850 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1851 // Depends on optimizations in MacroAssembler::setx.
1852 int hi = (int)(value >> 32);
1853 int lo = (int)(value & ~0);
1854 return (hi == 0) || (hi == -1) || (lo == 0);
1855 }
1857 // No scaling for the parameter the ClearArray node.
1858 const bool Matcher::init_array_count_is_in_bytes = true;
1860 // Threshold size for cleararray.
1861 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1863 // No additional cost for CMOVL.
1864 const int Matcher::long_cmove_cost() { return 0; }
1866 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1867 const int Matcher::float_cmove_cost() {
1868 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1869 }
1871 // Should the Matcher clone shifts on addressing modes, expecting them to
1872 // be subsumed into complex addressing expressions or compute them into
1873 // registers? True for Intel but false for most RISCs
1874 const bool Matcher::clone_shift_expressions = false;
1876 // Do we need to mask the count passed to shift instructions or does
1877 // the cpu only look at the lower 5/6 bits anyway?
1878 const bool Matcher::need_masked_shift_count = false;
1880 bool Matcher::narrow_oop_use_complex_address() {
1881 NOT_LP64(ShouldNotCallThis());
1882 assert(UseCompressedOops, "only for compressed oops code");
1883 return false;
1884 }
1886 // Is it better to copy float constants, or load them directly from memory?
1887 // Intel can load a float constant from a direct address, requiring no
1888 // extra registers. Most RISCs will have to materialize an address into a
1889 // register first, so they would do better to copy the constant from stack.
1890 const bool Matcher::rematerialize_float_constants = false;
1892 // If CPU can load and store mis-aligned doubles directly then no fixup is
1893 // needed. Else we split the double into 2 integer pieces and move it
1894 // piece-by-piece. Only happens when passing doubles into C code as the
1895 // Java calling convention forces doubles to be aligned.
1896 #ifdef _LP64
1897 const bool Matcher::misaligned_doubles_ok = true;
1898 #else
1899 const bool Matcher::misaligned_doubles_ok = false;
1900 #endif
1902 // No-op on SPARC.
1903 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1904 }
1906 // Advertise here if the CPU requires explicit rounding operations
1907 // to implement the UseStrictFP mode.
1908 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1910 // Are floats conerted to double when stored to stack during deoptimization?
1911 // Sparc does not handle callee-save floats.
1912 bool Matcher::float_in_double() { return false; }
1914 // Do ints take an entire long register or just half?
1915 // Note that we if-def off of _LP64.
1916 // The relevant question is how the int is callee-saved. In _LP64
1917 // the whole long is written but de-opt'ing will have to extract
1918 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1919 #ifdef _LP64
1920 const bool Matcher::int_in_long = true;
1921 #else
1922 const bool Matcher::int_in_long = false;
1923 #endif
1925 // Return whether or not this register is ever used as an argument. This
1926 // function is used on startup to build the trampoline stubs in generateOptoStub.
1927 // Registers not mentioned will be killed by the VM call in the trampoline, and
1928 // arguments in those registers not be available to the callee.
1929 bool Matcher::can_be_java_arg( int reg ) {
1930 // Standard sparc 6 args in registers
1931 if( reg == R_I0_num ||
1932 reg == R_I1_num ||
1933 reg == R_I2_num ||
1934 reg == R_I3_num ||
1935 reg == R_I4_num ||
1936 reg == R_I5_num ) return true;
1937 #ifdef _LP64
1938 // 64-bit builds can pass 64-bit pointers and longs in
1939 // the high I registers
1940 if( reg == R_I0H_num ||
1941 reg == R_I1H_num ||
1942 reg == R_I2H_num ||
1943 reg == R_I3H_num ||
1944 reg == R_I4H_num ||
1945 reg == R_I5H_num ) return true;
1947 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1948 return true;
1949 }
1951 #else
1952 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1953 // Longs cannot be passed in O regs, because O regs become I regs
1954 // after a 'save' and I regs get their high bits chopped off on
1955 // interrupt.
1956 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1957 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1958 #endif
1959 // A few float args in registers
1960 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1962 return false;
1963 }
1965 bool Matcher::is_spillable_arg( int reg ) {
1966 return can_be_java_arg(reg);
1967 }
1969 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1970 // Use hardware SDIVX instruction when it is
1971 // faster than a code which use multiply.
1972 return VM_Version::has_fast_idiv();
1973 }
1975 // Register for DIVI projection of divmodI
1976 RegMask Matcher::divI_proj_mask() {
1977 ShouldNotReachHere();
1978 return RegMask();
1979 }
1981 // Register for MODI projection of divmodI
1982 RegMask Matcher::modI_proj_mask() {
1983 ShouldNotReachHere();
1984 return RegMask();
1985 }
1987 // Register for DIVL projection of divmodL
1988 RegMask Matcher::divL_proj_mask() {
1989 ShouldNotReachHere();
1990 return RegMask();
1991 }
1993 // Register for MODL projection of divmodL
1994 RegMask Matcher::modL_proj_mask() {
1995 ShouldNotReachHere();
1996 return RegMask();
1997 }
1999 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2000 return L7_REGP_mask;
2001 }
2003 %}
2006 // The intptr_t operand types, defined by textual substitution.
2007 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2008 #ifdef _LP64
2009 #define immX immL
2010 #define immX13 immL13
2011 #define immX13m7 immL13m7
2012 #define iRegX iRegL
2013 #define g1RegX g1RegL
2014 #else
2015 #define immX immI
2016 #define immX13 immI13
2017 #define immX13m7 immI13m7
2018 #define iRegX iRegI
2019 #define g1RegX g1RegI
2020 #endif
2022 //----------ENCODING BLOCK-----------------------------------------------------
2023 // This block specifies the encoding classes used by the compiler to output
2024 // byte streams. Encoding classes are parameterized macros used by
2025 // Machine Instruction Nodes in order to generate the bit encoding of the
2026 // instruction. Operands specify their base encoding interface with the
2027 // interface keyword. There are currently supported four interfaces,
2028 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2029 // operand to generate a function which returns its register number when
2030 // queried. CONST_INTER causes an operand to generate a function which
2031 // returns the value of the constant when queried. MEMORY_INTER causes an
2032 // operand to generate four functions which return the Base Register, the
2033 // Index Register, the Scale Value, and the Offset Value of the operand when
2034 // queried. COND_INTER causes an operand to generate six functions which
2035 // return the encoding code (ie - encoding bits for the instruction)
2036 // associated with each basic boolean condition for a conditional instruction.
2037 //
2038 // Instructions specify two basic values for encoding. Again, a function
2039 // is available to check if the constant displacement is an oop. They use the
2040 // ins_encode keyword to specify their encoding classes (which must be
2041 // a sequence of enc_class names, and their parameters, specified in
2042 // the encoding block), and they use the
2043 // opcode keyword to specify, in order, their primary, secondary, and
2044 // tertiary opcode. Only the opcode sections which a particular instruction
2045 // needs for encoding need to be specified.
2046 encode %{
2047 enc_class enc_untested %{
2048 #ifdef ASSERT
2049 MacroAssembler _masm(&cbuf);
2050 __ untested("encoding");
2051 #endif
2052 %}
2054 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2055 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2056 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2057 %}
2059 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2060 emit_form3_mem_reg(cbuf, this, $primary, -1,
2061 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2062 %}
2064 enc_class form3_mem_prefetch_read( memory mem ) %{
2065 emit_form3_mem_reg(cbuf, this, $primary, -1,
2066 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2067 %}
2069 enc_class form3_mem_prefetch_write( memory mem ) %{
2070 emit_form3_mem_reg(cbuf, this, $primary, -1,
2071 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2072 %}
2074 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2075 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2076 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2077 guarantee($mem$$index == R_G0_enc, "double index?");
2078 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2079 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2080 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2081 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2082 %}
2084 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2085 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2086 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2087 guarantee($mem$$index == R_G0_enc, "double index?");
2088 // Load long with 2 instructions
2089 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2090 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2091 %}
2093 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2094 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2095 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2096 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2097 %}
2099 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2100 // Encode a reg-reg copy. If it is useless, then empty encoding.
2101 if( $rs2$$reg != $rd$$reg )
2102 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2103 %}
2105 // Target lo half of long
2106 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2107 // Encode a reg-reg copy. If it is useless, then empty encoding.
2108 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2109 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2110 %}
2112 // Source lo half of long
2113 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2114 // Encode a reg-reg copy. If it is useless, then empty encoding.
2115 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2116 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2117 %}
2119 // Target hi half of long
2120 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2121 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2122 %}
2124 // Source lo half of long, and leave it sign extended.
2125 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2126 // Sign extend low half
2127 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2128 %}
2130 // Source hi half of long, and leave it sign extended.
2131 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2132 // Shift high half to low half
2133 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2134 %}
2136 // Source hi half of long
2137 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2138 // Encode a reg-reg copy. If it is useless, then empty encoding.
2139 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2140 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2141 %}
2143 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2144 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2145 %}
2147 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2148 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2149 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2150 %}
2152 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2153 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2154 // clear if nothing else is happening
2155 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2156 // blt,a,pn done
2157 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2158 // mov dst,-1 in delay slot
2159 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2160 %}
2162 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2163 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2164 %}
2166 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2167 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2168 %}
2170 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2171 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2172 %}
2174 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2175 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2176 %}
2178 enc_class move_return_pc_to_o1() %{
2179 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2180 %}
2182 #ifdef _LP64
2183 /* %%% merge with enc_to_bool */
2184 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2185 MacroAssembler _masm(&cbuf);
2187 Register src_reg = reg_to_register_object($src$$reg);
2188 Register dst_reg = reg_to_register_object($dst$$reg);
2189 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2190 %}
2191 #endif
2193 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2194 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2195 MacroAssembler _masm(&cbuf);
2197 Register p_reg = reg_to_register_object($p$$reg);
2198 Register q_reg = reg_to_register_object($q$$reg);
2199 Register y_reg = reg_to_register_object($y$$reg);
2200 Register tmp_reg = reg_to_register_object($tmp$$reg);
2202 __ subcc( p_reg, q_reg, p_reg );
2203 __ add ( p_reg, y_reg, tmp_reg );
2204 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2205 %}
2207 enc_class form_d2i_helper(regD src, regF dst) %{
2208 // fcmp %fcc0,$src,$src
2209 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2210 // branch %fcc0 not-nan, predict taken
2211 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2212 // fdtoi $src,$dst
2213 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2214 // fitos $dst,$dst (if nan)
2215 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2216 // clear $dst (if nan)
2217 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2218 // carry on here...
2219 %}
2221 enc_class form_d2l_helper(regD src, regD dst) %{
2222 // fcmp %fcc0,$src,$src check for NAN
2223 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2224 // branch %fcc0 not-nan, predict taken
2225 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2226 // fdtox $src,$dst convert in delay slot
2227 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2228 // fxtod $dst,$dst (if nan)
2229 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2230 // clear $dst (if nan)
2231 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2232 // carry on here...
2233 %}
2235 enc_class form_f2i_helper(regF src, regF dst) %{
2236 // fcmps %fcc0,$src,$src
2237 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2238 // branch %fcc0 not-nan, predict taken
2239 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2240 // fstoi $src,$dst
2241 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2242 // fitos $dst,$dst (if nan)
2243 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2244 // clear $dst (if nan)
2245 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2246 // carry on here...
2247 %}
2249 enc_class form_f2l_helper(regF src, regD dst) %{
2250 // fcmps %fcc0,$src,$src
2251 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2252 // branch %fcc0 not-nan, predict taken
2253 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2254 // fstox $src,$dst
2255 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2256 // fxtod $dst,$dst (if nan)
2257 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2258 // clear $dst (if nan)
2259 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2260 // carry on here...
2261 %}
2263 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2264 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2265 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2266 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2268 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2270 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2271 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2273 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2274 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2275 %}
2277 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2278 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2279 %}
2281 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2282 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2283 %}
2285 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2286 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2287 %}
2289 enc_class form3_convI2F(regF rs2, regF rd) %{
2290 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2291 %}
2293 // Encloding class for traceable jumps
2294 enc_class form_jmpl(g3RegP dest) %{
2295 emit_jmpl(cbuf, $dest$$reg);
2296 %}
2298 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2299 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2300 %}
2302 enc_class form2_nop() %{
2303 emit_nop(cbuf);
2304 %}
2306 enc_class form2_illtrap() %{
2307 emit_illtrap(cbuf);
2308 %}
2311 // Compare longs and convert into -1, 0, 1.
2312 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2313 // CMP $src1,$src2
2314 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2315 // blt,a,pn done
2316 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2317 // mov dst,-1 in delay slot
2318 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2319 // bgt,a,pn done
2320 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2321 // mov dst,1 in delay slot
2322 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2323 // CLR $dst
2324 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2325 %}
2327 enc_class enc_PartialSubtypeCheck() %{
2328 MacroAssembler _masm(&cbuf);
2329 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2330 __ delayed()->nop();
2331 %}
2333 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2334 MacroAssembler _masm(&cbuf);
2335 Label* L = $labl$$label;
2336 Assembler::Predict predict_taken =
2337 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2339 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2340 __ delayed()->nop();
2341 %}
2343 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2344 MacroAssembler _masm(&cbuf);
2345 Label* L = $labl$$label;
2346 Assembler::Predict predict_taken =
2347 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2349 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2350 __ delayed()->nop();
2351 %}
2353 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2354 int op = (Assembler::arith_op << 30) |
2355 ($dst$$reg << 25) |
2356 (Assembler::movcc_op3 << 19) |
2357 (1 << 18) | // cc2 bit for 'icc'
2358 ($cmp$$cmpcode << 14) |
2359 (0 << 13) | // select register move
2360 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2361 ($src$$reg << 0);
2362 cbuf.insts()->emit_int32(op);
2363 %}
2365 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2366 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2367 int op = (Assembler::arith_op << 30) |
2368 ($dst$$reg << 25) |
2369 (Assembler::movcc_op3 << 19) |
2370 (1 << 18) | // cc2 bit for 'icc'
2371 ($cmp$$cmpcode << 14) |
2372 (1 << 13) | // select immediate move
2373 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2374 (simm11 << 0);
2375 cbuf.insts()->emit_int32(op);
2376 %}
2378 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2379 int op = (Assembler::arith_op << 30) |
2380 ($dst$$reg << 25) |
2381 (Assembler::movcc_op3 << 19) |
2382 (0 << 18) | // cc2 bit for 'fccX'
2383 ($cmp$$cmpcode << 14) |
2384 (0 << 13) | // select register move
2385 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2386 ($src$$reg << 0);
2387 cbuf.insts()->emit_int32(op);
2388 %}
2390 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2391 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2392 int op = (Assembler::arith_op << 30) |
2393 ($dst$$reg << 25) |
2394 (Assembler::movcc_op3 << 19) |
2395 (0 << 18) | // cc2 bit for 'fccX'
2396 ($cmp$$cmpcode << 14) |
2397 (1 << 13) | // select immediate move
2398 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2399 (simm11 << 0);
2400 cbuf.insts()->emit_int32(op);
2401 %}
2403 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2404 int op = (Assembler::arith_op << 30) |
2405 ($dst$$reg << 25) |
2406 (Assembler::fpop2_op3 << 19) |
2407 (0 << 18) |
2408 ($cmp$$cmpcode << 14) |
2409 (1 << 13) | // select register move
2410 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2411 ($primary << 5) | // select single, double or quad
2412 ($src$$reg << 0);
2413 cbuf.insts()->emit_int32(op);
2414 %}
2416 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2417 int op = (Assembler::arith_op << 30) |
2418 ($dst$$reg << 25) |
2419 (Assembler::fpop2_op3 << 19) |
2420 (0 << 18) |
2421 ($cmp$$cmpcode << 14) |
2422 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2423 ($primary << 5) | // select single, double or quad
2424 ($src$$reg << 0);
2425 cbuf.insts()->emit_int32(op);
2426 %}
2428 // Used by the MIN/MAX encodings. Same as a CMOV, but
2429 // the condition comes from opcode-field instead of an argument.
2430 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2431 int op = (Assembler::arith_op << 30) |
2432 ($dst$$reg << 25) |
2433 (Assembler::movcc_op3 << 19) |
2434 (1 << 18) | // cc2 bit for 'icc'
2435 ($primary << 14) |
2436 (0 << 13) | // select register move
2437 (0 << 11) | // cc1, cc0 bits for 'icc'
2438 ($src$$reg << 0);
2439 cbuf.insts()->emit_int32(op);
2440 %}
2442 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2443 int op = (Assembler::arith_op << 30) |
2444 ($dst$$reg << 25) |
2445 (Assembler::movcc_op3 << 19) |
2446 (6 << 16) | // cc2 bit for 'xcc'
2447 ($primary << 14) |
2448 (0 << 13) | // select register move
2449 (0 << 11) | // cc1, cc0 bits for 'icc'
2450 ($src$$reg << 0);
2451 cbuf.insts()->emit_int32(op);
2452 %}
2454 enc_class Set13( immI13 src, iRegI rd ) %{
2455 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2456 %}
2458 enc_class SetHi22( immI src, iRegI rd ) %{
2459 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2460 %}
2462 enc_class Set32( immI src, iRegI rd ) %{
2463 MacroAssembler _masm(&cbuf);
2464 __ set($src$$constant, reg_to_register_object($rd$$reg));
2465 %}
2467 enc_class call_epilog %{
2468 if( VerifyStackAtCalls ) {
2469 MacroAssembler _masm(&cbuf);
2470 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2471 Register temp_reg = G3;
2472 __ add(SP, framesize, temp_reg);
2473 __ cmp(temp_reg, FP);
2474 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2475 }
2476 %}
2478 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2479 // to G1 so the register allocator will not have to deal with the misaligned register
2480 // pair.
2481 enc_class adjust_long_from_native_call %{
2482 #ifndef _LP64
2483 if (returns_long()) {
2484 // sllx O0,32,O0
2485 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2486 // srl O1,0,O1
2487 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2488 // or O0,O1,G1
2489 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2490 }
2491 #endif
2492 %}
2494 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2495 // CALL directly to the runtime
2496 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2497 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2498 /*preserve_g2=*/true);
2499 %}
2501 enc_class preserve_SP %{
2502 MacroAssembler _masm(&cbuf);
2503 __ mov(SP, L7_mh_SP_save);
2504 %}
2506 enc_class restore_SP %{
2507 MacroAssembler _masm(&cbuf);
2508 __ mov(L7_mh_SP_save, SP);
2509 %}
2511 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2512 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2513 // who we intended to call.
2514 if ( !_method ) {
2515 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2516 } else if (_optimized_virtual) {
2517 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2518 } else {
2519 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2520 }
2521 if( _method ) { // Emit stub for static call
2522 emit_java_to_interp(cbuf);
2523 }
2524 %}
2526 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2527 MacroAssembler _masm(&cbuf);
2528 __ set_inst_mark();
2529 int vtable_index = this->_vtable_index;
2530 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2531 if (vtable_index < 0) {
2532 // must be invalid_vtable_index, not nonvirtual_vtable_index
2533 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2534 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2535 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2536 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2537 // !!!!!
2538 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2539 // emit_call_dynamic_prologue( cbuf );
2540 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2542 address virtual_call_oop_addr = __ inst_mark();
2543 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2544 // who we intended to call.
2545 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2546 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2547 } else {
2548 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2549 // Just go thru the vtable
2550 // get receiver klass (receiver already checked for non-null)
2551 // If we end up going thru a c2i adapter interpreter expects method in G5
2552 int off = __ offset();
2553 __ load_klass(O0, G3_scratch);
2554 int klass_load_size;
2555 if (UseCompressedOops) {
2556 assert(Universe::heap() != NULL, "java heap should be initialized");
2557 if (Universe::narrow_oop_base() == NULL)
2558 klass_load_size = 2*BytesPerInstWord;
2559 else
2560 klass_load_size = 3*BytesPerInstWord;
2561 } else {
2562 klass_load_size = 1*BytesPerInstWord;
2563 }
2564 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2565 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2566 if( __ is_simm13(v_off) ) {
2567 __ ld_ptr(G3, v_off, G5_method);
2568 } else {
2569 // Generate 2 instructions
2570 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2571 __ or3(G5_method, v_off & 0x3ff, G5_method);
2572 // ld_ptr, set_hi, set
2573 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2574 "Unexpected instruction size(s)");
2575 __ ld_ptr(G3, G5_method, G5_method);
2576 }
2577 // NOTE: for vtable dispatches, the vtable entry will never be null.
2578 // However it may very well end up in handle_wrong_method if the
2579 // method is abstract for the particular class.
2580 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2581 // jump to target (either compiled code or c2iadapter)
2582 __ jmpl(G3_scratch, G0, O7);
2583 __ delayed()->nop();
2584 }
2585 %}
2587 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2588 MacroAssembler _masm(&cbuf);
2590 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2591 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2592 // we might be calling a C2I adapter which needs it.
2594 assert(temp_reg != G5_ic_reg, "conflicting registers");
2595 // Load nmethod
2596 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2598 // CALL to compiled java, indirect the contents of G3
2599 __ set_inst_mark();
2600 __ callr(temp_reg, G0);
2601 __ delayed()->nop();
2602 %}
2604 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2605 MacroAssembler _masm(&cbuf);
2606 Register Rdividend = reg_to_register_object($src1$$reg);
2607 Register Rdivisor = reg_to_register_object($src2$$reg);
2608 Register Rresult = reg_to_register_object($dst$$reg);
2610 __ sra(Rdivisor, 0, Rdivisor);
2611 __ sra(Rdividend, 0, Rdividend);
2612 __ sdivx(Rdividend, Rdivisor, Rresult);
2613 %}
2615 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2616 MacroAssembler _masm(&cbuf);
2618 Register Rdividend = reg_to_register_object($src1$$reg);
2619 int divisor = $imm$$constant;
2620 Register Rresult = reg_to_register_object($dst$$reg);
2622 __ sra(Rdividend, 0, Rdividend);
2623 __ sdivx(Rdividend, divisor, Rresult);
2624 %}
2626 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2627 MacroAssembler _masm(&cbuf);
2628 Register Rsrc1 = reg_to_register_object($src1$$reg);
2629 Register Rsrc2 = reg_to_register_object($src2$$reg);
2630 Register Rdst = reg_to_register_object($dst$$reg);
2632 __ sra( Rsrc1, 0, Rsrc1 );
2633 __ sra( Rsrc2, 0, Rsrc2 );
2634 __ mulx( Rsrc1, Rsrc2, Rdst );
2635 __ srlx( Rdst, 32, Rdst );
2636 %}
2638 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2639 MacroAssembler _masm(&cbuf);
2640 Register Rdividend = reg_to_register_object($src1$$reg);
2641 Register Rdivisor = reg_to_register_object($src2$$reg);
2642 Register Rresult = reg_to_register_object($dst$$reg);
2643 Register Rscratch = reg_to_register_object($scratch$$reg);
2645 assert(Rdividend != Rscratch, "");
2646 assert(Rdivisor != Rscratch, "");
2648 __ sra(Rdividend, 0, Rdividend);
2649 __ sra(Rdivisor, 0, Rdivisor);
2650 __ sdivx(Rdividend, Rdivisor, Rscratch);
2651 __ mulx(Rscratch, Rdivisor, Rscratch);
2652 __ sub(Rdividend, Rscratch, Rresult);
2653 %}
2655 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2656 MacroAssembler _masm(&cbuf);
2658 Register Rdividend = reg_to_register_object($src1$$reg);
2659 int divisor = $imm$$constant;
2660 Register Rresult = reg_to_register_object($dst$$reg);
2661 Register Rscratch = reg_to_register_object($scratch$$reg);
2663 assert(Rdividend != Rscratch, "");
2665 __ sra(Rdividend, 0, Rdividend);
2666 __ sdivx(Rdividend, divisor, Rscratch);
2667 __ mulx(Rscratch, divisor, Rscratch);
2668 __ sub(Rdividend, Rscratch, Rresult);
2669 %}
2671 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2672 MacroAssembler _masm(&cbuf);
2674 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2675 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2677 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2678 %}
2680 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2681 MacroAssembler _masm(&cbuf);
2683 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2684 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2686 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2687 %}
2689 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2690 MacroAssembler _masm(&cbuf);
2692 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2693 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2695 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2696 %}
2698 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2699 MacroAssembler _masm(&cbuf);
2701 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2702 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2704 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2705 %}
2707 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2708 MacroAssembler _masm(&cbuf);
2710 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2711 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2713 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2714 %}
2716 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2717 MacroAssembler _masm(&cbuf);
2719 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2720 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2722 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2723 %}
2725 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2726 MacroAssembler _masm(&cbuf);
2728 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2729 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2731 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2732 %}
2734 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2735 MacroAssembler _masm(&cbuf);
2737 Register Roop = reg_to_register_object($oop$$reg);
2738 Register Rbox = reg_to_register_object($box$$reg);
2739 Register Rscratch = reg_to_register_object($scratch$$reg);
2740 Register Rmark = reg_to_register_object($scratch2$$reg);
2742 assert(Roop != Rscratch, "");
2743 assert(Roop != Rmark, "");
2744 assert(Rbox != Rscratch, "");
2745 assert(Rbox != Rmark, "");
2747 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2748 %}
2750 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2751 MacroAssembler _masm(&cbuf);
2753 Register Roop = reg_to_register_object($oop$$reg);
2754 Register Rbox = reg_to_register_object($box$$reg);
2755 Register Rscratch = reg_to_register_object($scratch$$reg);
2756 Register Rmark = reg_to_register_object($scratch2$$reg);
2758 assert(Roop != Rscratch, "");
2759 assert(Roop != Rmark, "");
2760 assert(Rbox != Rscratch, "");
2761 assert(Rbox != Rmark, "");
2763 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2764 %}
2766 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2767 MacroAssembler _masm(&cbuf);
2768 Register Rmem = reg_to_register_object($mem$$reg);
2769 Register Rold = reg_to_register_object($old$$reg);
2770 Register Rnew = reg_to_register_object($new$$reg);
2772 // casx_under_lock picks 1 of 3 encodings:
2773 // For 32-bit pointers you get a 32-bit CAS
2774 // For 64-bit pointers you get a 64-bit CASX
2775 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2776 __ cmp( Rold, Rnew );
2777 %}
2779 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2780 Register Rmem = reg_to_register_object($mem$$reg);
2781 Register Rold = reg_to_register_object($old$$reg);
2782 Register Rnew = reg_to_register_object($new$$reg);
2784 MacroAssembler _masm(&cbuf);
2785 __ mov(Rnew, O7);
2786 __ casx(Rmem, Rold, O7);
2787 __ cmp( Rold, O7 );
2788 %}
2790 // raw int cas, used for compareAndSwap
2791 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2792 Register Rmem = reg_to_register_object($mem$$reg);
2793 Register Rold = reg_to_register_object($old$$reg);
2794 Register Rnew = reg_to_register_object($new$$reg);
2796 MacroAssembler _masm(&cbuf);
2797 __ mov(Rnew, O7);
2798 __ cas(Rmem, Rold, O7);
2799 __ cmp( Rold, O7 );
2800 %}
2802 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2803 Register Rres = reg_to_register_object($res$$reg);
2805 MacroAssembler _masm(&cbuf);
2806 __ mov(1, Rres);
2807 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2808 %}
2810 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2811 Register Rres = reg_to_register_object($res$$reg);
2813 MacroAssembler _masm(&cbuf);
2814 __ mov(1, Rres);
2815 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2816 %}
2818 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2819 MacroAssembler _masm(&cbuf);
2820 Register Rdst = reg_to_register_object($dst$$reg);
2821 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2822 : reg_to_DoubleFloatRegister_object($src1$$reg);
2823 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2824 : reg_to_DoubleFloatRegister_object($src2$$reg);
2826 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2827 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2828 %}
2831 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2832 Label Ldone, Lloop;
2833 MacroAssembler _masm(&cbuf);
2835 Register str1_reg = reg_to_register_object($str1$$reg);
2836 Register str2_reg = reg_to_register_object($str2$$reg);
2837 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2838 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2839 Register result_reg = reg_to_register_object($result$$reg);
2841 assert(result_reg != str1_reg &&
2842 result_reg != str2_reg &&
2843 result_reg != cnt1_reg &&
2844 result_reg != cnt2_reg ,
2845 "need different registers");
2847 // Compute the minimum of the string lengths(str1_reg) and the
2848 // difference of the string lengths (stack)
2850 // See if the lengths are different, and calculate min in str1_reg.
2851 // Stash diff in O7 in case we need it for a tie-breaker.
2852 Label Lskip;
2853 __ subcc(cnt1_reg, cnt2_reg, O7);
2854 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2855 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2856 // cnt2 is shorter, so use its count:
2857 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2858 __ bind(Lskip);
2860 // reallocate cnt1_reg, cnt2_reg, result_reg
2861 // Note: limit_reg holds the string length pre-scaled by 2
2862 Register limit_reg = cnt1_reg;
2863 Register chr2_reg = cnt2_reg;
2864 Register chr1_reg = result_reg;
2865 // str{12} are the base pointers
2867 // Is the minimum length zero?
2868 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2869 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2870 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2872 // Load first characters
2873 __ lduh(str1_reg, 0, chr1_reg);
2874 __ lduh(str2_reg, 0, chr2_reg);
2876 // Compare first characters
2877 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2878 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2879 assert(chr1_reg == result_reg, "result must be pre-placed");
2880 __ delayed()->nop();
2882 {
2883 // Check after comparing first character to see if strings are equivalent
2884 Label LSkip2;
2885 // Check if the strings start at same location
2886 __ cmp(str1_reg, str2_reg);
2887 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2888 __ delayed()->nop();
2890 // Check if the length difference is zero (in O7)
2891 __ cmp(G0, O7);
2892 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2893 __ delayed()->mov(G0, result_reg); // result is zero
2895 // Strings might not be equal
2896 __ bind(LSkip2);
2897 }
2899 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2900 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2901 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2903 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2904 __ add(str1_reg, limit_reg, str1_reg);
2905 __ add(str2_reg, limit_reg, str2_reg);
2906 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2908 // Compare the rest of the characters
2909 __ lduh(str1_reg, limit_reg, chr1_reg);
2910 __ bind(Lloop);
2911 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2912 __ lduh(str2_reg, limit_reg, chr2_reg);
2913 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2914 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2915 assert(chr1_reg == result_reg, "result must be pre-placed");
2916 __ delayed()->inccc(limit_reg, sizeof(jchar));
2917 // annul LDUH if branch is not taken to prevent access past end of string
2918 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2919 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2921 // If strings are equal up to min length, return the length difference.
2922 __ mov(O7, result_reg);
2924 // Otherwise, return the difference between the first mismatched chars.
2925 __ bind(Ldone);
2926 %}
2928 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2929 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2930 MacroAssembler _masm(&cbuf);
2932 Register str1_reg = reg_to_register_object($str1$$reg);
2933 Register str2_reg = reg_to_register_object($str2$$reg);
2934 Register cnt_reg = reg_to_register_object($cnt$$reg);
2935 Register tmp1_reg = O7;
2936 Register result_reg = reg_to_register_object($result$$reg);
2938 assert(result_reg != str1_reg &&
2939 result_reg != str2_reg &&
2940 result_reg != cnt_reg &&
2941 result_reg != tmp1_reg ,
2942 "need different registers");
2944 __ cmp(str1_reg, str2_reg); //same char[] ?
2945 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2946 __ delayed()->add(G0, 1, result_reg);
2948 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2949 __ delayed()->add(G0, 1, result_reg); // count == 0
2951 //rename registers
2952 Register limit_reg = cnt_reg;
2953 Register chr1_reg = result_reg;
2954 Register chr2_reg = tmp1_reg;
2956 //check for alignment and position the pointers to the ends
2957 __ or3(str1_reg, str2_reg, chr1_reg);
2958 __ andcc(chr1_reg, 0x3, chr1_reg);
2959 // notZero means at least one not 4-byte aligned.
2960 // We could optimize the case when both arrays are not aligned
2961 // but it is not frequent case and it requires additional checks.
2962 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2963 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2965 // Compare char[] arrays aligned to 4 bytes.
2966 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2967 chr1_reg, chr2_reg, Ldone);
2968 __ ba(Ldone);
2969 __ delayed()->add(G0, 1, result_reg);
2971 // char by char compare
2972 __ bind(Lchar);
2973 __ add(str1_reg, limit_reg, str1_reg);
2974 __ add(str2_reg, limit_reg, str2_reg);
2975 __ neg(limit_reg); //negate count
2977 __ lduh(str1_reg, limit_reg, chr1_reg);
2978 // Lchar_loop
2979 __ bind(Lchar_loop);
2980 __ lduh(str2_reg, limit_reg, chr2_reg);
2981 __ cmp(chr1_reg, chr2_reg);
2982 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2983 __ delayed()->mov(G0, result_reg); //not equal
2984 __ inccc(limit_reg, sizeof(jchar));
2985 // annul LDUH if branch is not taken to prevent access past end of string
2986 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2987 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2989 __ add(G0, 1, result_reg); //equal
2991 __ bind(Ldone);
2992 %}
2994 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
2995 Label Lvector, Ldone, Lloop;
2996 MacroAssembler _masm(&cbuf);
2998 Register ary1_reg = reg_to_register_object($ary1$$reg);
2999 Register ary2_reg = reg_to_register_object($ary2$$reg);
3000 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3001 Register tmp2_reg = O7;
3002 Register result_reg = reg_to_register_object($result$$reg);
3004 int length_offset = arrayOopDesc::length_offset_in_bytes();
3005 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3007 // return true if the same array
3008 __ cmp(ary1_reg, ary2_reg);
3009 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3010 __ delayed()->add(G0, 1, result_reg); // equal
3012 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3013 __ delayed()->mov(G0, result_reg); // not equal
3015 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3016 __ delayed()->mov(G0, result_reg); // not equal
3018 //load the lengths of arrays
3019 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3020 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3022 // return false if the two arrays are not equal length
3023 __ cmp(tmp1_reg, tmp2_reg);
3024 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3025 __ delayed()->mov(G0, result_reg); // not equal
3027 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3028 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3030 // load array addresses
3031 __ add(ary1_reg, base_offset, ary1_reg);
3032 __ add(ary2_reg, base_offset, ary2_reg);
3034 // renaming registers
3035 Register chr1_reg = result_reg; // for characters in ary1
3036 Register chr2_reg = tmp2_reg; // for characters in ary2
3037 Register limit_reg = tmp1_reg; // length
3039 // set byte count
3040 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3042 // Compare char[] arrays aligned to 4 bytes.
3043 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3044 chr1_reg, chr2_reg, Ldone);
3045 __ add(G0, 1, result_reg); // equals
3047 __ bind(Ldone);
3048 %}
3050 enc_class enc_rethrow() %{
3051 cbuf.set_insts_mark();
3052 Register temp_reg = G3;
3053 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3054 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3055 MacroAssembler _masm(&cbuf);
3056 #ifdef ASSERT
3057 __ save_frame(0);
3058 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3059 __ sethi(last_rethrow_addrlit, L1);
3060 Address addr(L1, last_rethrow_addrlit.low10());
3061 __ get_pc(L2);
3062 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3063 __ st_ptr(L2, addr);
3064 __ restore();
3065 #endif
3066 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3067 __ delayed()->nop();
3068 %}
3070 enc_class emit_mem_nop() %{
3071 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3072 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3073 %}
3075 enc_class emit_fadd_nop() %{
3076 // Generates the instruction FMOVS f31,f31
3077 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3078 %}
3080 enc_class emit_br_nop() %{
3081 // Generates the instruction BPN,PN .
3082 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3083 %}
3085 enc_class enc_membar_acquire %{
3086 MacroAssembler _masm(&cbuf);
3087 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3088 %}
3090 enc_class enc_membar_release %{
3091 MacroAssembler _masm(&cbuf);
3092 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3093 %}
3095 enc_class enc_membar_volatile %{
3096 MacroAssembler _masm(&cbuf);
3097 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3098 %}
3100 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3101 MacroAssembler _masm(&cbuf);
3102 Register src_reg = reg_to_register_object($src$$reg);
3103 Register dst_reg = reg_to_register_object($dst$$reg);
3104 __ sllx(src_reg, 56, dst_reg);
3105 __ srlx(dst_reg, 8, O7);
3106 __ or3 (dst_reg, O7, dst_reg);
3107 __ srlx(dst_reg, 16, O7);
3108 __ or3 (dst_reg, O7, dst_reg);
3109 __ srlx(dst_reg, 32, O7);
3110 __ or3 (dst_reg, O7, dst_reg);
3111 %}
3113 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3114 MacroAssembler _masm(&cbuf);
3115 Register src_reg = reg_to_register_object($src$$reg);
3116 Register dst_reg = reg_to_register_object($dst$$reg);
3117 __ sll(src_reg, 24, dst_reg);
3118 __ srl(dst_reg, 8, O7);
3119 __ or3(dst_reg, O7, dst_reg);
3120 __ srl(dst_reg, 16, O7);
3121 __ or3(dst_reg, O7, dst_reg);
3122 %}
3124 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3125 MacroAssembler _masm(&cbuf);
3126 Register src_reg = reg_to_register_object($src$$reg);
3127 Register dst_reg = reg_to_register_object($dst$$reg);
3128 __ sllx(src_reg, 48, dst_reg);
3129 __ srlx(dst_reg, 16, O7);
3130 __ or3 (dst_reg, O7, dst_reg);
3131 __ srlx(dst_reg, 32, O7);
3132 __ or3 (dst_reg, O7, dst_reg);
3133 %}
3135 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3136 MacroAssembler _masm(&cbuf);
3137 Register src_reg = reg_to_register_object($src$$reg);
3138 Register dst_reg = reg_to_register_object($dst$$reg);
3139 __ sllx(src_reg, 32, dst_reg);
3140 __ srlx(dst_reg, 32, O7);
3141 __ or3 (dst_reg, O7, dst_reg);
3142 %}
3144 %}
3146 //----------FRAME--------------------------------------------------------------
3147 // Definition of frame structure and management information.
3148 //
3149 // S T A C K L A Y O U T Allocators stack-slot number
3150 // | (to get allocators register number
3151 // G Owned by | | v add VMRegImpl::stack0)
3152 // r CALLER | |
3153 // o | +--------+ pad to even-align allocators stack-slot
3154 // w V | pad0 | numbers; owned by CALLER
3155 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3156 // h ^ | in | 5
3157 // | | args | 4 Holes in incoming args owned by SELF
3158 // | | | | 3
3159 // | | +--------+
3160 // V | | old out| Empty on Intel, window on Sparc
3161 // | old |preserve| Must be even aligned.
3162 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3163 // | | in | 3 area for Intel ret address
3164 // Owned by |preserve| Empty on Sparc.
3165 // SELF +--------+
3166 // | | pad2 | 2 pad to align old SP
3167 // | +--------+ 1
3168 // | | locks | 0
3169 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3170 // | | pad1 | 11 pad to align new SP
3171 // | +--------+
3172 // | | | 10
3173 // | | spills | 9 spills
3174 // V | | 8 (pad0 slot for callee)
3175 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3176 // ^ | out | 7
3177 // | | args | 6 Holes in outgoing args owned by CALLEE
3178 // Owned by +--------+
3179 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3180 // | new |preserve| Must be even-aligned.
3181 // | SP-+--------+----> Matcher::_new_SP, even aligned
3182 // | | |
3183 //
3184 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3185 // known from SELF's arguments and the Java calling convention.
3186 // Region 6-7 is determined per call site.
3187 // Note 2: If the calling convention leaves holes in the incoming argument
3188 // area, those holes are owned by SELF. Holes in the outgoing area
3189 // are owned by the CALLEE. Holes should not be nessecary in the
3190 // incoming area, as the Java calling convention is completely under
3191 // the control of the AD file. Doubles can be sorted and packed to
3192 // avoid holes. Holes in the outgoing arguments may be nessecary for
3193 // varargs C calling conventions.
3194 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3195 // even aligned with pad0 as needed.
3196 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3197 // region 6-11 is even aligned; it may be padded out more so that
3198 // the region from SP to FP meets the minimum stack alignment.
3200 frame %{
3201 // What direction does stack grow in (assumed to be same for native & Java)
3202 stack_direction(TOWARDS_LOW);
3204 // These two registers define part of the calling convention
3205 // between compiled code and the interpreter.
3206 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3207 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3209 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3210 cisc_spilling_operand_name(indOffset);
3212 // Number of stack slots consumed by a Monitor enter
3213 #ifdef _LP64
3214 sync_stack_slots(2);
3215 #else
3216 sync_stack_slots(1);
3217 #endif
3219 // Compiled code's Frame Pointer
3220 frame_pointer(R_SP);
3222 // Stack alignment requirement
3223 stack_alignment(StackAlignmentInBytes);
3224 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3225 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3227 // Number of stack slots between incoming argument block and the start of
3228 // a new frame. The PROLOG must add this many slots to the stack. The
3229 // EPILOG must remove this many slots.
3230 in_preserve_stack_slots(0);
3232 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3233 // for calls to C. Supports the var-args backing area for register parms.
3234 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3235 #ifdef _LP64
3236 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3237 varargs_C_out_slots_killed(12);
3238 #else
3239 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3240 varargs_C_out_slots_killed( 7);
3241 #endif
3243 // The after-PROLOG location of the return address. Location of
3244 // return address specifies a type (REG or STACK) and a number
3245 // representing the register number (i.e. - use a register name) or
3246 // stack slot.
3247 return_addr(REG R_I7); // Ret Addr is in register I7
3249 // Body of function which returns an OptoRegs array locating
3250 // arguments either in registers or in stack slots for calling
3251 // java
3252 calling_convention %{
3253 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3255 %}
3257 // Body of function which returns an OptoRegs array locating
3258 // arguments either in registers or in stack slots for callin
3259 // C.
3260 c_calling_convention %{
3261 // This is obviously always outgoing
3262 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3263 %}
3265 // Location of native (C/C++) and interpreter return values. This is specified to
3266 // be the same as Java. In the 32-bit VM, long values are actually returned from
3267 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3268 // to and from the register pairs is done by the appropriate call and epilog
3269 // opcodes. This simplifies the register allocator.
3270 c_return_value %{
3271 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3272 #ifdef _LP64
3273 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3274 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3275 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3276 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3277 #else // !_LP64
3278 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3279 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3280 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3281 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3282 #endif
3283 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3284 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3285 %}
3287 // Location of compiled Java return values. Same as C
3288 return_value %{
3289 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3290 #ifdef _LP64
3291 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3292 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3293 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3294 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3295 #else // !_LP64
3296 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3297 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3298 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3299 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3300 #endif
3301 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3302 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3303 %}
3305 %}
3308 //----------ATTRIBUTES---------------------------------------------------------
3309 //----------Operand Attributes-------------------------------------------------
3310 op_attrib op_cost(1); // Required cost attribute
3312 //----------Instruction Attributes---------------------------------------------
3313 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3314 ins_attrib ins_size(32); // Required size attribute (in bits)
3315 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3316 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3317 // non-matching short branch variant of some
3318 // long branch?
3320 //----------OPERANDS-----------------------------------------------------------
3321 // Operand definitions must precede instruction definitions for correct parsing
3322 // in the ADLC because operands constitute user defined types which are used in
3323 // instruction definitions.
3325 //----------Simple Operands----------------------------------------------------
3326 // Immediate Operands
3327 // Integer Immediate: 32-bit
3328 operand immI() %{
3329 match(ConI);
3331 op_cost(0);
3332 // formats are generated automatically for constants and base registers
3333 format %{ %}
3334 interface(CONST_INTER);
3335 %}
3337 // Integer Immediate: 8-bit
3338 operand immI8() %{
3339 predicate(Assembler::is_simm(n->get_int(), 8));
3340 match(ConI);
3341 op_cost(0);
3342 format %{ %}
3343 interface(CONST_INTER);
3344 %}
3346 // Integer Immediate: 13-bit
3347 operand immI13() %{
3348 predicate(Assembler::is_simm13(n->get_int()));
3349 match(ConI);
3350 op_cost(0);
3352 format %{ %}
3353 interface(CONST_INTER);
3354 %}
3356 // Integer Immediate: 13-bit minus 7
3357 operand immI13m7() %{
3358 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3359 match(ConI);
3360 op_cost(0);
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3366 // Integer Immediate: 16-bit
3367 operand immI16() %{
3368 predicate(Assembler::is_simm(n->get_int(), 16));
3369 match(ConI);
3370 op_cost(0);
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3375 // Unsigned (positive) Integer Immediate: 13-bit
3376 operand immU13() %{
3377 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3378 match(ConI);
3379 op_cost(0);
3381 format %{ %}
3382 interface(CONST_INTER);
3383 %}
3385 // Integer Immediate: 6-bit
3386 operand immU6() %{
3387 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3388 match(ConI);
3389 op_cost(0);
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3394 // Integer Immediate: 11-bit
3395 operand immI11() %{
3396 predicate(Assembler::is_simm(n->get_int(),11));
3397 match(ConI);
3398 op_cost(0);
3399 format %{ %}
3400 interface(CONST_INTER);
3401 %}
3403 // Integer Immediate: 5-bit
3404 operand immI5() %{
3405 predicate(Assembler::is_simm(n->get_int(), 5));
3406 match(ConI);
3407 op_cost(0);
3408 format %{ %}
3409 interface(CONST_INTER);
3410 %}
3412 // Integer Immediate: 0-bit
3413 operand immI0() %{
3414 predicate(n->get_int() == 0);
3415 match(ConI);
3416 op_cost(0);
3418 format %{ %}
3419 interface(CONST_INTER);
3420 %}
3422 // Integer Immediate: the value 10
3423 operand immI10() %{
3424 predicate(n->get_int() == 10);
3425 match(ConI);
3426 op_cost(0);
3428 format %{ %}
3429 interface(CONST_INTER);
3430 %}
3432 // Integer Immediate: the values 0-31
3433 operand immU5() %{
3434 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3435 match(ConI);
3436 op_cost(0);
3438 format %{ %}
3439 interface(CONST_INTER);
3440 %}
3442 // Integer Immediate: the values 1-31
3443 operand immI_1_31() %{
3444 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3445 match(ConI);
3446 op_cost(0);
3448 format %{ %}
3449 interface(CONST_INTER);
3450 %}
3452 // Integer Immediate: the values 32-63
3453 operand immI_32_63() %{
3454 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3455 match(ConI);
3456 op_cost(0);
3458 format %{ %}
3459 interface(CONST_INTER);
3460 %}
3462 // Immediates for special shifts (sign extend)
3464 // Integer Immediate: the value 16
3465 operand immI_16() %{
3466 predicate(n->get_int() == 16);
3467 match(ConI);
3468 op_cost(0);
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3474 // Integer Immediate: the value 24
3475 operand immI_24() %{
3476 predicate(n->get_int() == 24);
3477 match(ConI);
3478 op_cost(0);
3480 format %{ %}
3481 interface(CONST_INTER);
3482 %}
3484 // Integer Immediate: the value 255
3485 operand immI_255() %{
3486 predicate( n->get_int() == 255 );
3487 match(ConI);
3488 op_cost(0);
3490 format %{ %}
3491 interface(CONST_INTER);
3492 %}
3494 // Integer Immediate: the value 65535
3495 operand immI_65535() %{
3496 predicate(n->get_int() == 65535);
3497 match(ConI);
3498 op_cost(0);
3500 format %{ %}
3501 interface(CONST_INTER);
3502 %}
3504 // Long Immediate: the value FF
3505 operand immL_FF() %{
3506 predicate( n->get_long() == 0xFFL );
3507 match(ConL);
3508 op_cost(0);
3510 format %{ %}
3511 interface(CONST_INTER);
3512 %}
3514 // Long Immediate: the value FFFF
3515 operand immL_FFFF() %{
3516 predicate( n->get_long() == 0xFFFFL );
3517 match(ConL);
3518 op_cost(0);
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3524 // Pointer Immediate: 32 or 64-bit
3525 operand immP() %{
3526 match(ConP);
3528 op_cost(5);
3529 // formats are generated automatically for constants and base registers
3530 format %{ %}
3531 interface(CONST_INTER);
3532 %}
3534 #ifdef _LP64
3535 // Pointer Immediate: 64-bit
3536 operand immP_set() %{
3537 predicate(!VM_Version::is_niagara_plus());
3538 match(ConP);
3540 op_cost(5);
3541 // formats are generated automatically for constants and base registers
3542 format %{ %}
3543 interface(CONST_INTER);
3544 %}
3546 // Pointer Immediate: 64-bit
3547 // From Niagara2 processors on a load should be better than materializing.
3548 operand immP_load() %{
3549 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3550 match(ConP);
3552 op_cost(5);
3553 // formats are generated automatically for constants and base registers
3554 format %{ %}
3555 interface(CONST_INTER);
3556 %}
3558 // Pointer Immediate: 64-bit
3559 operand immP_no_oop_cheap() %{
3560 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3561 match(ConP);
3563 op_cost(5);
3564 // formats are generated automatically for constants and base registers
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568 #endif
3570 operand immP13() %{
3571 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3572 match(ConP);
3573 op_cost(0);
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3579 operand immP0() %{
3580 predicate(n->get_ptr() == 0);
3581 match(ConP);
3582 op_cost(0);
3584 format %{ %}
3585 interface(CONST_INTER);
3586 %}
3588 operand immP_poll() %{
3589 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3590 match(ConP);
3592 // formats are generated automatically for constants and base registers
3593 format %{ %}
3594 interface(CONST_INTER);
3595 %}
3597 // Pointer Immediate
3598 operand immN()
3599 %{
3600 match(ConN);
3602 op_cost(10);
3603 format %{ %}
3604 interface(CONST_INTER);
3605 %}
3607 // NULL Pointer Immediate
3608 operand immN0()
3609 %{
3610 predicate(n->get_narrowcon() == 0);
3611 match(ConN);
3613 op_cost(0);
3614 format %{ %}
3615 interface(CONST_INTER);
3616 %}
3618 operand immL() %{
3619 match(ConL);
3620 op_cost(40);
3621 // formats are generated automatically for constants and base registers
3622 format %{ %}
3623 interface(CONST_INTER);
3624 %}
3626 operand immL0() %{
3627 predicate(n->get_long() == 0L);
3628 match(ConL);
3629 op_cost(0);
3630 // formats are generated automatically for constants and base registers
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3635 // Integer Immediate: 5-bit
3636 operand immL5() %{
3637 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm((int)n->get_long(), 5));
3638 match(ConL);
3639 op_cost(0);
3640 format %{ %}
3641 interface(CONST_INTER);
3642 %}
3644 // Long Immediate: 13-bit
3645 operand immL13() %{
3646 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3647 match(ConL);
3648 op_cost(0);
3650 format %{ %}
3651 interface(CONST_INTER);
3652 %}
3654 // Long Immediate: 13-bit minus 7
3655 operand immL13m7() %{
3656 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3657 match(ConL);
3658 op_cost(0);
3660 format %{ %}
3661 interface(CONST_INTER);
3662 %}
3664 // Long Immediate: low 32-bit mask
3665 operand immL_32bits() %{
3666 predicate(n->get_long() == 0xFFFFFFFFL);
3667 match(ConL);
3668 op_cost(0);
3670 format %{ %}
3671 interface(CONST_INTER);
3672 %}
3674 // Long Immediate: cheap (materialize in <= 3 instructions)
3675 operand immL_cheap() %{
3676 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3677 match(ConL);
3678 op_cost(0);
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3684 // Long Immediate: expensive (materialize in > 3 instructions)
3685 operand immL_expensive() %{
3686 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3687 match(ConL);
3688 op_cost(0);
3690 format %{ %}
3691 interface(CONST_INTER);
3692 %}
3694 // Double Immediate
3695 operand immD() %{
3696 match(ConD);
3698 op_cost(40);
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3703 operand immD0() %{
3704 #ifdef _LP64
3705 // on 64-bit architectures this comparision is faster
3706 predicate(jlong_cast(n->getd()) == 0);
3707 #else
3708 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3709 #endif
3710 match(ConD);
3712 op_cost(0);
3713 format %{ %}
3714 interface(CONST_INTER);
3715 %}
3717 // Float Immediate
3718 operand immF() %{
3719 match(ConF);
3721 op_cost(20);
3722 format %{ %}
3723 interface(CONST_INTER);
3724 %}
3726 // Float Immediate: 0
3727 operand immF0() %{
3728 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3729 match(ConF);
3731 op_cost(0);
3732 format %{ %}
3733 interface(CONST_INTER);
3734 %}
3736 // Integer Register Operands
3737 // Integer Register
3738 operand iRegI() %{
3739 constraint(ALLOC_IN_RC(int_reg));
3740 match(RegI);
3742 match(notemp_iRegI);
3743 match(g1RegI);
3744 match(o0RegI);
3745 match(iRegIsafe);
3747 format %{ %}
3748 interface(REG_INTER);
3749 %}
3751 operand notemp_iRegI() %{
3752 constraint(ALLOC_IN_RC(notemp_int_reg));
3753 match(RegI);
3755 match(o0RegI);
3757 format %{ %}
3758 interface(REG_INTER);
3759 %}
3761 operand o0RegI() %{
3762 constraint(ALLOC_IN_RC(o0_regI));
3763 match(iRegI);
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3769 // Pointer Register
3770 operand iRegP() %{
3771 constraint(ALLOC_IN_RC(ptr_reg));
3772 match(RegP);
3774 match(lock_ptr_RegP);
3775 match(g1RegP);
3776 match(g2RegP);
3777 match(g3RegP);
3778 match(g4RegP);
3779 match(i0RegP);
3780 match(o0RegP);
3781 match(o1RegP);
3782 match(l7RegP);
3784 format %{ %}
3785 interface(REG_INTER);
3786 %}
3788 operand sp_ptr_RegP() %{
3789 constraint(ALLOC_IN_RC(sp_ptr_reg));
3790 match(RegP);
3791 match(iRegP);
3793 format %{ %}
3794 interface(REG_INTER);
3795 %}
3797 operand lock_ptr_RegP() %{
3798 constraint(ALLOC_IN_RC(lock_ptr_reg));
3799 match(RegP);
3800 match(i0RegP);
3801 match(o0RegP);
3802 match(o1RegP);
3803 match(l7RegP);
3805 format %{ %}
3806 interface(REG_INTER);
3807 %}
3809 operand g1RegP() %{
3810 constraint(ALLOC_IN_RC(g1_regP));
3811 match(iRegP);
3813 format %{ %}
3814 interface(REG_INTER);
3815 %}
3817 operand g2RegP() %{
3818 constraint(ALLOC_IN_RC(g2_regP));
3819 match(iRegP);
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3825 operand g3RegP() %{
3826 constraint(ALLOC_IN_RC(g3_regP));
3827 match(iRegP);
3829 format %{ %}
3830 interface(REG_INTER);
3831 %}
3833 operand g1RegI() %{
3834 constraint(ALLOC_IN_RC(g1_regI));
3835 match(iRegI);
3837 format %{ %}
3838 interface(REG_INTER);
3839 %}
3841 operand g3RegI() %{
3842 constraint(ALLOC_IN_RC(g3_regI));
3843 match(iRegI);
3845 format %{ %}
3846 interface(REG_INTER);
3847 %}
3849 operand g4RegI() %{
3850 constraint(ALLOC_IN_RC(g4_regI));
3851 match(iRegI);
3853 format %{ %}
3854 interface(REG_INTER);
3855 %}
3857 operand g4RegP() %{
3858 constraint(ALLOC_IN_RC(g4_regP));
3859 match(iRegP);
3861 format %{ %}
3862 interface(REG_INTER);
3863 %}
3865 operand i0RegP() %{
3866 constraint(ALLOC_IN_RC(i0_regP));
3867 match(iRegP);
3869 format %{ %}
3870 interface(REG_INTER);
3871 %}
3873 operand o0RegP() %{
3874 constraint(ALLOC_IN_RC(o0_regP));
3875 match(iRegP);
3877 format %{ %}
3878 interface(REG_INTER);
3879 %}
3881 operand o1RegP() %{
3882 constraint(ALLOC_IN_RC(o1_regP));
3883 match(iRegP);
3885 format %{ %}
3886 interface(REG_INTER);
3887 %}
3889 operand o2RegP() %{
3890 constraint(ALLOC_IN_RC(o2_regP));
3891 match(iRegP);
3893 format %{ %}
3894 interface(REG_INTER);
3895 %}
3897 operand o7RegP() %{
3898 constraint(ALLOC_IN_RC(o7_regP));
3899 match(iRegP);
3901 format %{ %}
3902 interface(REG_INTER);
3903 %}
3905 operand l7RegP() %{
3906 constraint(ALLOC_IN_RC(l7_regP));
3907 match(iRegP);
3909 format %{ %}
3910 interface(REG_INTER);
3911 %}
3913 operand o7RegI() %{
3914 constraint(ALLOC_IN_RC(o7_regI));
3915 match(iRegI);
3917 format %{ %}
3918 interface(REG_INTER);
3919 %}
3921 operand iRegN() %{
3922 constraint(ALLOC_IN_RC(int_reg));
3923 match(RegN);
3925 format %{ %}
3926 interface(REG_INTER);
3927 %}
3929 // Long Register
3930 operand iRegL() %{
3931 constraint(ALLOC_IN_RC(long_reg));
3932 match(RegL);
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3938 operand o2RegL() %{
3939 constraint(ALLOC_IN_RC(o2_regL));
3940 match(iRegL);
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3946 operand o7RegL() %{
3947 constraint(ALLOC_IN_RC(o7_regL));
3948 match(iRegL);
3950 format %{ %}
3951 interface(REG_INTER);
3952 %}
3954 operand g1RegL() %{
3955 constraint(ALLOC_IN_RC(g1_regL));
3956 match(iRegL);
3958 format %{ %}
3959 interface(REG_INTER);
3960 %}
3962 operand g3RegL() %{
3963 constraint(ALLOC_IN_RC(g3_regL));
3964 match(iRegL);
3966 format %{ %}
3967 interface(REG_INTER);
3968 %}
3970 // Int Register safe
3971 // This is 64bit safe
3972 operand iRegIsafe() %{
3973 constraint(ALLOC_IN_RC(long_reg));
3975 match(iRegI);
3977 format %{ %}
3978 interface(REG_INTER);
3979 %}
3981 // Condition Code Flag Register
3982 operand flagsReg() %{
3983 constraint(ALLOC_IN_RC(int_flags));
3984 match(RegFlags);
3986 format %{ "ccr" %} // both ICC and XCC
3987 interface(REG_INTER);
3988 %}
3990 // Condition Code Register, unsigned comparisons.
3991 operand flagsRegU() %{
3992 constraint(ALLOC_IN_RC(int_flags));
3993 match(RegFlags);
3995 format %{ "icc_U" %}
3996 interface(REG_INTER);
3997 %}
3999 // Condition Code Register, pointer comparisons.
4000 operand flagsRegP() %{
4001 constraint(ALLOC_IN_RC(int_flags));
4002 match(RegFlags);
4004 #ifdef _LP64
4005 format %{ "xcc_P" %}
4006 #else
4007 format %{ "icc_P" %}
4008 #endif
4009 interface(REG_INTER);
4010 %}
4012 // Condition Code Register, long comparisons.
4013 operand flagsRegL() %{
4014 constraint(ALLOC_IN_RC(int_flags));
4015 match(RegFlags);
4017 format %{ "xcc_L" %}
4018 interface(REG_INTER);
4019 %}
4021 // Condition Code Register, floating comparisons, unordered same as "less".
4022 operand flagsRegF() %{
4023 constraint(ALLOC_IN_RC(float_flags));
4024 match(RegFlags);
4025 match(flagsRegF0);
4027 format %{ %}
4028 interface(REG_INTER);
4029 %}
4031 operand flagsRegF0() %{
4032 constraint(ALLOC_IN_RC(float_flag0));
4033 match(RegFlags);
4035 format %{ %}
4036 interface(REG_INTER);
4037 %}
4040 // Condition Code Flag Register used by long compare
4041 operand flagsReg_long_LTGE() %{
4042 constraint(ALLOC_IN_RC(int_flags));
4043 match(RegFlags);
4044 format %{ "icc_LTGE" %}
4045 interface(REG_INTER);
4046 %}
4047 operand flagsReg_long_EQNE() %{
4048 constraint(ALLOC_IN_RC(int_flags));
4049 match(RegFlags);
4050 format %{ "icc_EQNE" %}
4051 interface(REG_INTER);
4052 %}
4053 operand flagsReg_long_LEGT() %{
4054 constraint(ALLOC_IN_RC(int_flags));
4055 match(RegFlags);
4056 format %{ "icc_LEGT" %}
4057 interface(REG_INTER);
4058 %}
4061 operand regD() %{
4062 constraint(ALLOC_IN_RC(dflt_reg));
4063 match(RegD);
4065 match(regD_low);
4067 format %{ %}
4068 interface(REG_INTER);
4069 %}
4071 operand regF() %{
4072 constraint(ALLOC_IN_RC(sflt_reg));
4073 match(RegF);
4075 format %{ %}
4076 interface(REG_INTER);
4077 %}
4079 operand regD_low() %{
4080 constraint(ALLOC_IN_RC(dflt_low_reg));
4081 match(regD);
4083 format %{ %}
4084 interface(REG_INTER);
4085 %}
4087 // Special Registers
4089 // Method Register
4090 operand inline_cache_regP(iRegP reg) %{
4091 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4092 match(reg);
4093 format %{ %}
4094 interface(REG_INTER);
4095 %}
4097 operand interpreter_method_oop_regP(iRegP reg) %{
4098 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4099 match(reg);
4100 format %{ %}
4101 interface(REG_INTER);
4102 %}
4105 //----------Complex Operands---------------------------------------------------
4106 // Indirect Memory Reference
4107 operand indirect(sp_ptr_RegP reg) %{
4108 constraint(ALLOC_IN_RC(sp_ptr_reg));
4109 match(reg);
4111 op_cost(100);
4112 format %{ "[$reg]" %}
4113 interface(MEMORY_INTER) %{
4114 base($reg);
4115 index(0x0);
4116 scale(0x0);
4117 disp(0x0);
4118 %}
4119 %}
4121 // Indirect with simm13 Offset
4122 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4123 constraint(ALLOC_IN_RC(sp_ptr_reg));
4124 match(AddP reg offset);
4126 op_cost(100);
4127 format %{ "[$reg + $offset]" %}
4128 interface(MEMORY_INTER) %{
4129 base($reg);
4130 index(0x0);
4131 scale(0x0);
4132 disp($offset);
4133 %}
4134 %}
4136 // Indirect with simm13 Offset minus 7
4137 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4138 constraint(ALLOC_IN_RC(sp_ptr_reg));
4139 match(AddP reg offset);
4141 op_cost(100);
4142 format %{ "[$reg + $offset]" %}
4143 interface(MEMORY_INTER) %{
4144 base($reg);
4145 index(0x0);
4146 scale(0x0);
4147 disp($offset);
4148 %}
4149 %}
4151 // Note: Intel has a swapped version also, like this:
4152 //operand indOffsetX(iRegI reg, immP offset) %{
4153 // constraint(ALLOC_IN_RC(int_reg));
4154 // match(AddP offset reg);
4155 //
4156 // op_cost(100);
4157 // format %{ "[$reg + $offset]" %}
4158 // interface(MEMORY_INTER) %{
4159 // base($reg);
4160 // index(0x0);
4161 // scale(0x0);
4162 // disp($offset);
4163 // %}
4164 //%}
4165 //// However, it doesn't make sense for SPARC, since
4166 // we have no particularly good way to embed oops in
4167 // single instructions.
4169 // Indirect with Register Index
4170 operand indIndex(iRegP addr, iRegX index) %{
4171 constraint(ALLOC_IN_RC(ptr_reg));
4172 match(AddP addr index);
4174 op_cost(100);
4175 format %{ "[$addr + $index]" %}
4176 interface(MEMORY_INTER) %{
4177 base($addr);
4178 index($index);
4179 scale(0x0);
4180 disp(0x0);
4181 %}
4182 %}
4184 //----------Special Memory Operands--------------------------------------------
4185 // Stack Slot Operand - This operand is used for loading and storing temporary
4186 // values on the stack where a match requires a value to
4187 // flow through memory.
4188 operand stackSlotI(sRegI reg) %{
4189 constraint(ALLOC_IN_RC(stack_slots));
4190 op_cost(100);
4191 //match(RegI);
4192 format %{ "[$reg]" %}
4193 interface(MEMORY_INTER) %{
4194 base(0xE); // R_SP
4195 index(0x0);
4196 scale(0x0);
4197 disp($reg); // Stack Offset
4198 %}
4199 %}
4201 operand stackSlotP(sRegP reg) %{
4202 constraint(ALLOC_IN_RC(stack_slots));
4203 op_cost(100);
4204 //match(RegP);
4205 format %{ "[$reg]" %}
4206 interface(MEMORY_INTER) %{
4207 base(0xE); // R_SP
4208 index(0x0);
4209 scale(0x0);
4210 disp($reg); // Stack Offset
4211 %}
4212 %}
4214 operand stackSlotF(sRegF reg) %{
4215 constraint(ALLOC_IN_RC(stack_slots));
4216 op_cost(100);
4217 //match(RegF);
4218 format %{ "[$reg]" %}
4219 interface(MEMORY_INTER) %{
4220 base(0xE); // R_SP
4221 index(0x0);
4222 scale(0x0);
4223 disp($reg); // Stack Offset
4224 %}
4225 %}
4226 operand stackSlotD(sRegD reg) %{
4227 constraint(ALLOC_IN_RC(stack_slots));
4228 op_cost(100);
4229 //match(RegD);
4230 format %{ "[$reg]" %}
4231 interface(MEMORY_INTER) %{
4232 base(0xE); // R_SP
4233 index(0x0);
4234 scale(0x0);
4235 disp($reg); // Stack Offset
4236 %}
4237 %}
4238 operand stackSlotL(sRegL reg) %{
4239 constraint(ALLOC_IN_RC(stack_slots));
4240 op_cost(100);
4241 //match(RegL);
4242 format %{ "[$reg]" %}
4243 interface(MEMORY_INTER) %{
4244 base(0xE); // R_SP
4245 index(0x0);
4246 scale(0x0);
4247 disp($reg); // Stack Offset
4248 %}
4249 %}
4251 // Operands for expressing Control Flow
4252 // NOTE: Label is a predefined operand which should not be redefined in
4253 // the AD file. It is generically handled within the ADLC.
4255 //----------Conditional Branch Operands----------------------------------------
4256 // Comparison Op - This is the operation of the comparison, and is limited to
4257 // the following set of codes:
4258 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4259 //
4260 // Other attributes of the comparison, such as unsignedness, are specified
4261 // by the comparison instruction that sets a condition code flags register.
4262 // That result is represented by a flags operand whose subtype is appropriate
4263 // to the unsignedness (etc.) of the comparison.
4264 //
4265 // Later, the instruction which matches both the Comparison Op (a Bool) and
4266 // the flags (produced by the Cmp) specifies the coding of the comparison op
4267 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4269 operand cmpOp() %{
4270 match(Bool);
4272 format %{ "" %}
4273 interface(COND_INTER) %{
4274 equal(0x1);
4275 not_equal(0x9);
4276 less(0x3);
4277 greater_equal(0xB);
4278 less_equal(0x2);
4279 greater(0xA);
4280 %}
4281 %}
4283 // Comparison Op, unsigned
4284 operand cmpOpU() %{
4285 match(Bool);
4287 format %{ "u" %}
4288 interface(COND_INTER) %{
4289 equal(0x1);
4290 not_equal(0x9);
4291 less(0x5);
4292 greater_equal(0xD);
4293 less_equal(0x4);
4294 greater(0xC);
4295 %}
4296 %}
4298 // Comparison Op, pointer (same as unsigned)
4299 operand cmpOpP() %{
4300 match(Bool);
4302 format %{ "p" %}
4303 interface(COND_INTER) %{
4304 equal(0x1);
4305 not_equal(0x9);
4306 less(0x5);
4307 greater_equal(0xD);
4308 less_equal(0x4);
4309 greater(0xC);
4310 %}
4311 %}
4313 // Comparison Op, branch-register encoding
4314 operand cmpOp_reg() %{
4315 match(Bool);
4317 format %{ "" %}
4318 interface(COND_INTER) %{
4319 equal (0x1);
4320 not_equal (0x5);
4321 less (0x3);
4322 greater_equal(0x7);
4323 less_equal (0x2);
4324 greater (0x6);
4325 %}
4326 %}
4328 // Comparison Code, floating, unordered same as less
4329 operand cmpOpF() %{
4330 match(Bool);
4332 format %{ "fl" %}
4333 interface(COND_INTER) %{
4334 equal(0x9);
4335 not_equal(0x1);
4336 less(0x3);
4337 greater_equal(0xB);
4338 less_equal(0xE);
4339 greater(0x6);
4340 %}
4341 %}
4343 // Used by long compare
4344 operand cmpOp_commute() %{
4345 match(Bool);
4347 format %{ "" %}
4348 interface(COND_INTER) %{
4349 equal(0x1);
4350 not_equal(0x9);
4351 less(0xA);
4352 greater_equal(0x2);
4353 less_equal(0xB);
4354 greater(0x3);
4355 %}
4356 %}
4358 //----------OPERAND CLASSES----------------------------------------------------
4359 // Operand Classes are groups of operands that are used to simplify
4360 // instruction definitions by not requiring the AD writer to specify separate
4361 // instructions for every form of operand when the instruction accepts
4362 // multiple operand types with the same basic encoding and format. The classic
4363 // case of this is memory operands.
4364 opclass memory( indirect, indOffset13, indIndex );
4365 opclass indIndexMemory( indIndex );
4367 //----------PIPELINE-----------------------------------------------------------
4368 pipeline %{
4370 //----------ATTRIBUTES---------------------------------------------------------
4371 attributes %{
4372 fixed_size_instructions; // Fixed size instructions
4373 branch_has_delay_slot; // Branch has delay slot following
4374 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4375 instruction_unit_size = 4; // An instruction is 4 bytes long
4376 instruction_fetch_unit_size = 16; // The processor fetches one line
4377 instruction_fetch_units = 1; // of 16 bytes
4379 // List of nop instructions
4380 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4381 %}
4383 //----------RESOURCES----------------------------------------------------------
4384 // Resources are the functional units available to the machine
4385 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4387 //----------PIPELINE DESCRIPTION-----------------------------------------------
4388 // Pipeline Description specifies the stages in the machine's pipeline
4390 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4392 //----------PIPELINE CLASSES---------------------------------------------------
4393 // Pipeline Classes describe the stages in which input and output are
4394 // referenced by the hardware pipeline.
4396 // Integer ALU reg-reg operation
4397 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4398 single_instruction;
4399 dst : E(write);
4400 src1 : R(read);
4401 src2 : R(read);
4402 IALU : R;
4403 %}
4405 // Integer ALU reg-reg long operation
4406 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4407 instruction_count(2);
4408 dst : E(write);
4409 src1 : R(read);
4410 src2 : R(read);
4411 IALU : R;
4412 IALU : R;
4413 %}
4415 // Integer ALU reg-reg long dependent operation
4416 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4417 instruction_count(1); multiple_bundles;
4418 dst : E(write);
4419 src1 : R(read);
4420 src2 : R(read);
4421 cr : E(write);
4422 IALU : R(2);
4423 %}
4425 // Integer ALU reg-imm operaion
4426 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4427 single_instruction;
4428 dst : E(write);
4429 src1 : R(read);
4430 IALU : R;
4431 %}
4433 // Integer ALU reg-reg operation with condition code
4434 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4435 single_instruction;
4436 dst : E(write);
4437 cr : E(write);
4438 src1 : R(read);
4439 src2 : R(read);
4440 IALU : R;
4441 %}
4443 // Integer ALU reg-imm operation with condition code
4444 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4445 single_instruction;
4446 dst : E(write);
4447 cr : E(write);
4448 src1 : R(read);
4449 IALU : R;
4450 %}
4452 // Integer ALU zero-reg operation
4453 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4454 single_instruction;
4455 dst : E(write);
4456 src2 : R(read);
4457 IALU : R;
4458 %}
4460 // Integer ALU zero-reg operation with condition code only
4461 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4462 single_instruction;
4463 cr : E(write);
4464 src : R(read);
4465 IALU : R;
4466 %}
4468 // Integer ALU reg-reg operation with condition code only
4469 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4470 single_instruction;
4471 cr : E(write);
4472 src1 : R(read);
4473 src2 : R(read);
4474 IALU : R;
4475 %}
4477 // Integer ALU reg-imm operation with condition code only
4478 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4479 single_instruction;
4480 cr : E(write);
4481 src1 : R(read);
4482 IALU : R;
4483 %}
4485 // Integer ALU reg-reg-zero operation with condition code only
4486 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4487 single_instruction;
4488 cr : E(write);
4489 src1 : R(read);
4490 src2 : R(read);
4491 IALU : R;
4492 %}
4494 // Integer ALU reg-imm-zero operation with condition code only
4495 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4496 single_instruction;
4497 cr : E(write);
4498 src1 : R(read);
4499 IALU : R;
4500 %}
4502 // Integer ALU reg-reg operation with condition code, src1 modified
4503 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4504 single_instruction;
4505 cr : E(write);
4506 src1 : E(write);
4507 src1 : R(read);
4508 src2 : R(read);
4509 IALU : R;
4510 %}
4512 // Integer ALU reg-imm operation with condition code, src1 modified
4513 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4514 single_instruction;
4515 cr : E(write);
4516 src1 : E(write);
4517 src1 : R(read);
4518 IALU : R;
4519 %}
4521 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4522 multiple_bundles;
4523 dst : E(write)+4;
4524 cr : E(write);
4525 src1 : R(read);
4526 src2 : R(read);
4527 IALU : R(3);
4528 BR : R(2);
4529 %}
4531 // Integer ALU operation
4532 pipe_class ialu_none(iRegI dst) %{
4533 single_instruction;
4534 dst : E(write);
4535 IALU : R;
4536 %}
4538 // Integer ALU reg operation
4539 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4540 single_instruction; may_have_no_code;
4541 dst : E(write);
4542 src : R(read);
4543 IALU : R;
4544 %}
4546 // Integer ALU reg conditional operation
4547 // This instruction has a 1 cycle stall, and cannot execute
4548 // in the same cycle as the instruction setting the condition
4549 // code. We kludge this by pretending to read the condition code
4550 // 1 cycle earlier, and by marking the functional units as busy
4551 // for 2 cycles with the result available 1 cycle later than
4552 // is really the case.
4553 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4554 single_instruction;
4555 op2_out : C(write);
4556 op1 : R(read);
4557 cr : R(read); // This is really E, with a 1 cycle stall
4558 BR : R(2);
4559 MS : R(2);
4560 %}
4562 #ifdef _LP64
4563 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4564 instruction_count(1); multiple_bundles;
4565 dst : C(write)+1;
4566 src : R(read)+1;
4567 IALU : R(1);
4568 BR : E(2);
4569 MS : E(2);
4570 %}
4571 #endif
4573 // Integer ALU reg operation
4574 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4575 single_instruction; may_have_no_code;
4576 dst : E(write);
4577 src : R(read);
4578 IALU : R;
4579 %}
4580 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4581 single_instruction; may_have_no_code;
4582 dst : E(write);
4583 src : R(read);
4584 IALU : R;
4585 %}
4587 // Two integer ALU reg operations
4588 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4589 instruction_count(2);
4590 dst : E(write);
4591 src : R(read);
4592 A0 : R;
4593 A1 : R;
4594 %}
4596 // Two integer ALU reg operations
4597 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4598 instruction_count(2); may_have_no_code;
4599 dst : E(write);
4600 src : R(read);
4601 A0 : R;
4602 A1 : R;
4603 %}
4605 // Integer ALU imm operation
4606 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4607 single_instruction;
4608 dst : E(write);
4609 IALU : R;
4610 %}
4612 // Integer ALU reg-reg with carry operation
4613 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4614 single_instruction;
4615 dst : E(write);
4616 src1 : R(read);
4617 src2 : R(read);
4618 IALU : R;
4619 %}
4621 // Integer ALU cc operation
4622 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4623 single_instruction;
4624 dst : E(write);
4625 cc : R(read);
4626 IALU : R;
4627 %}
4629 // Integer ALU cc / second IALU operation
4630 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4631 instruction_count(1); multiple_bundles;
4632 dst : E(write)+1;
4633 src : R(read);
4634 IALU : R;
4635 %}
4637 // Integer ALU cc / second IALU operation
4638 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4639 instruction_count(1); multiple_bundles;
4640 dst : E(write)+1;
4641 p : R(read);
4642 q : R(read);
4643 IALU : R;
4644 %}
4646 // Integer ALU hi-lo-reg operation
4647 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4648 instruction_count(1); multiple_bundles;
4649 dst : E(write)+1;
4650 IALU : R(2);
4651 %}
4653 // Float ALU hi-lo-reg operation (with temp)
4654 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4655 instruction_count(1); multiple_bundles;
4656 dst : E(write)+1;
4657 IALU : R(2);
4658 %}
4660 // Long Constant
4661 pipe_class loadConL( iRegL dst, immL src ) %{
4662 instruction_count(2); multiple_bundles;
4663 dst : E(write)+1;
4664 IALU : R(2);
4665 IALU : R(2);
4666 %}
4668 // Pointer Constant
4669 pipe_class loadConP( iRegP dst, immP src ) %{
4670 instruction_count(0); multiple_bundles;
4671 fixed_latency(6);
4672 %}
4674 // Polling Address
4675 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4676 #ifdef _LP64
4677 instruction_count(0); multiple_bundles;
4678 fixed_latency(6);
4679 #else
4680 dst : E(write);
4681 IALU : R;
4682 #endif
4683 %}
4685 // Long Constant small
4686 pipe_class loadConLlo( iRegL dst, immL src ) %{
4687 instruction_count(2);
4688 dst : E(write);
4689 IALU : R;
4690 IALU : R;
4691 %}
4693 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4694 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4695 instruction_count(1); multiple_bundles;
4696 src : R(read);
4697 dst : M(write)+1;
4698 IALU : R;
4699 MS : E;
4700 %}
4702 // Integer ALU nop operation
4703 pipe_class ialu_nop() %{
4704 single_instruction;
4705 IALU : R;
4706 %}
4708 // Integer ALU nop operation
4709 pipe_class ialu_nop_A0() %{
4710 single_instruction;
4711 A0 : R;
4712 %}
4714 // Integer ALU nop operation
4715 pipe_class ialu_nop_A1() %{
4716 single_instruction;
4717 A1 : R;
4718 %}
4720 // Integer Multiply reg-reg operation
4721 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4722 single_instruction;
4723 dst : E(write);
4724 src1 : R(read);
4725 src2 : R(read);
4726 MS : R(5);
4727 %}
4729 // Integer Multiply reg-imm operation
4730 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4731 single_instruction;
4732 dst : E(write);
4733 src1 : R(read);
4734 MS : R(5);
4735 %}
4737 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4738 single_instruction;
4739 dst : E(write)+4;
4740 src1 : R(read);
4741 src2 : R(read);
4742 MS : R(6);
4743 %}
4745 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4746 single_instruction;
4747 dst : E(write)+4;
4748 src1 : R(read);
4749 MS : R(6);
4750 %}
4752 // Integer Divide reg-reg
4753 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4754 instruction_count(1); multiple_bundles;
4755 dst : E(write);
4756 temp : E(write);
4757 src1 : R(read);
4758 src2 : R(read);
4759 temp : R(read);
4760 MS : R(38);
4761 %}
4763 // Integer Divide reg-imm
4764 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4765 instruction_count(1); multiple_bundles;
4766 dst : E(write);
4767 temp : E(write);
4768 src1 : R(read);
4769 temp : R(read);
4770 MS : R(38);
4771 %}
4773 // Long Divide
4774 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4775 dst : E(write)+71;
4776 src1 : R(read);
4777 src2 : R(read)+1;
4778 MS : R(70);
4779 %}
4781 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4782 dst : E(write)+71;
4783 src1 : R(read);
4784 MS : R(70);
4785 %}
4787 // Floating Point Add Float
4788 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4789 single_instruction;
4790 dst : X(write);
4791 src1 : E(read);
4792 src2 : E(read);
4793 FA : R;
4794 %}
4796 // Floating Point Add Double
4797 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4798 single_instruction;
4799 dst : X(write);
4800 src1 : E(read);
4801 src2 : E(read);
4802 FA : R;
4803 %}
4805 // Floating Point Conditional Move based on integer flags
4806 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4807 single_instruction;
4808 dst : X(write);
4809 src : E(read);
4810 cr : R(read);
4811 FA : R(2);
4812 BR : R(2);
4813 %}
4815 // Floating Point Conditional Move based on integer flags
4816 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4817 single_instruction;
4818 dst : X(write);
4819 src : E(read);
4820 cr : R(read);
4821 FA : R(2);
4822 BR : R(2);
4823 %}
4825 // Floating Point Multiply Float
4826 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4827 single_instruction;
4828 dst : X(write);
4829 src1 : E(read);
4830 src2 : E(read);
4831 FM : R;
4832 %}
4834 // Floating Point Multiply Double
4835 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4836 single_instruction;
4837 dst : X(write);
4838 src1 : E(read);
4839 src2 : E(read);
4840 FM : R;
4841 %}
4843 // Floating Point Divide Float
4844 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4845 single_instruction;
4846 dst : X(write);
4847 src1 : E(read);
4848 src2 : E(read);
4849 FM : R;
4850 FDIV : C(14);
4851 %}
4853 // Floating Point Divide Double
4854 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4855 single_instruction;
4856 dst : X(write);
4857 src1 : E(read);
4858 src2 : E(read);
4859 FM : R;
4860 FDIV : C(17);
4861 %}
4863 // Floating Point Move/Negate/Abs Float
4864 pipe_class faddF_reg(regF dst, regF src) %{
4865 single_instruction;
4866 dst : W(write);
4867 src : E(read);
4868 FA : R(1);
4869 %}
4871 // Floating Point Move/Negate/Abs Double
4872 pipe_class faddD_reg(regD dst, regD src) %{
4873 single_instruction;
4874 dst : W(write);
4875 src : E(read);
4876 FA : R;
4877 %}
4879 // Floating Point Convert F->D
4880 pipe_class fcvtF2D(regD dst, regF src) %{
4881 single_instruction;
4882 dst : X(write);
4883 src : E(read);
4884 FA : R;
4885 %}
4887 // Floating Point Convert I->D
4888 pipe_class fcvtI2D(regD dst, regF src) %{
4889 single_instruction;
4890 dst : X(write);
4891 src : E(read);
4892 FA : R;
4893 %}
4895 // Floating Point Convert LHi->D
4896 pipe_class fcvtLHi2D(regD dst, regD src) %{
4897 single_instruction;
4898 dst : X(write);
4899 src : E(read);
4900 FA : R;
4901 %}
4903 // Floating Point Convert L->D
4904 pipe_class fcvtL2D(regD dst, regF src) %{
4905 single_instruction;
4906 dst : X(write);
4907 src : E(read);
4908 FA : R;
4909 %}
4911 // Floating Point Convert L->F
4912 pipe_class fcvtL2F(regD dst, regF src) %{
4913 single_instruction;
4914 dst : X(write);
4915 src : E(read);
4916 FA : R;
4917 %}
4919 // Floating Point Convert D->F
4920 pipe_class fcvtD2F(regD dst, regF src) %{
4921 single_instruction;
4922 dst : X(write);
4923 src : E(read);
4924 FA : R;
4925 %}
4927 // Floating Point Convert I->L
4928 pipe_class fcvtI2L(regD dst, regF src) %{
4929 single_instruction;
4930 dst : X(write);
4931 src : E(read);
4932 FA : R;
4933 %}
4935 // Floating Point Convert D->F
4936 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4937 instruction_count(1); multiple_bundles;
4938 dst : X(write)+6;
4939 src : E(read);
4940 FA : R;
4941 %}
4943 // Floating Point Convert D->L
4944 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4945 instruction_count(1); multiple_bundles;
4946 dst : X(write)+6;
4947 src : E(read);
4948 FA : R;
4949 %}
4951 // Floating Point Convert F->I
4952 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4953 instruction_count(1); multiple_bundles;
4954 dst : X(write)+6;
4955 src : E(read);
4956 FA : R;
4957 %}
4959 // Floating Point Convert F->L
4960 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4961 instruction_count(1); multiple_bundles;
4962 dst : X(write)+6;
4963 src : E(read);
4964 FA : R;
4965 %}
4967 // Floating Point Convert I->F
4968 pipe_class fcvtI2F(regF dst, regF src) %{
4969 single_instruction;
4970 dst : X(write);
4971 src : E(read);
4972 FA : R;
4973 %}
4975 // Floating Point Compare
4976 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4977 single_instruction;
4978 cr : X(write);
4979 src1 : E(read);
4980 src2 : E(read);
4981 FA : R;
4982 %}
4984 // Floating Point Compare
4985 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4986 single_instruction;
4987 cr : X(write);
4988 src1 : E(read);
4989 src2 : E(read);
4990 FA : R;
4991 %}
4993 // Floating Add Nop
4994 pipe_class fadd_nop() %{
4995 single_instruction;
4996 FA : R;
4997 %}
4999 // Integer Store to Memory
5000 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5001 single_instruction;
5002 mem : R(read);
5003 src : C(read);
5004 MS : R;
5005 %}
5007 // Integer Store to Memory
5008 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5009 single_instruction;
5010 mem : R(read);
5011 src : C(read);
5012 MS : R;
5013 %}
5015 // Integer Store Zero to Memory
5016 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5017 single_instruction;
5018 mem : R(read);
5019 MS : R;
5020 %}
5022 // Special Stack Slot Store
5023 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5024 single_instruction;
5025 stkSlot : R(read);
5026 src : C(read);
5027 MS : R;
5028 %}
5030 // Special Stack Slot Store
5031 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5032 instruction_count(2); multiple_bundles;
5033 stkSlot : R(read);
5034 src : C(read);
5035 MS : R(2);
5036 %}
5038 // Float Store
5039 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5040 single_instruction;
5041 mem : R(read);
5042 src : C(read);
5043 MS : R;
5044 %}
5046 // Float Store
5047 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5048 single_instruction;
5049 mem : R(read);
5050 MS : R;
5051 %}
5053 // Double Store
5054 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5055 instruction_count(1);
5056 mem : R(read);
5057 src : C(read);
5058 MS : R;
5059 %}
5061 // Double Store
5062 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5063 single_instruction;
5064 mem : R(read);
5065 MS : R;
5066 %}
5068 // Special Stack Slot Float Store
5069 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5070 single_instruction;
5071 stkSlot : R(read);
5072 src : C(read);
5073 MS : R;
5074 %}
5076 // Special Stack Slot Double Store
5077 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5078 single_instruction;
5079 stkSlot : R(read);
5080 src : C(read);
5081 MS : R;
5082 %}
5084 // Integer Load (when sign bit propagation not needed)
5085 pipe_class iload_mem(iRegI dst, memory mem) %{
5086 single_instruction;
5087 mem : R(read);
5088 dst : C(write);
5089 MS : R;
5090 %}
5092 // Integer Load from stack operand
5093 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5094 single_instruction;
5095 mem : R(read);
5096 dst : C(write);
5097 MS : R;
5098 %}
5100 // Integer Load (when sign bit propagation or masking is needed)
5101 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5102 single_instruction;
5103 mem : R(read);
5104 dst : M(write);
5105 MS : R;
5106 %}
5108 // Float Load
5109 pipe_class floadF_mem(regF dst, memory mem) %{
5110 single_instruction;
5111 mem : R(read);
5112 dst : M(write);
5113 MS : R;
5114 %}
5116 // Float Load
5117 pipe_class floadD_mem(regD dst, memory mem) %{
5118 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5119 mem : R(read);
5120 dst : M(write);
5121 MS : R;
5122 %}
5124 // Float Load
5125 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5126 single_instruction;
5127 stkSlot : R(read);
5128 dst : M(write);
5129 MS : R;
5130 %}
5132 // Float Load
5133 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5134 single_instruction;
5135 stkSlot : R(read);
5136 dst : M(write);
5137 MS : R;
5138 %}
5140 // Memory Nop
5141 pipe_class mem_nop() %{
5142 single_instruction;
5143 MS : R;
5144 %}
5146 pipe_class sethi(iRegP dst, immI src) %{
5147 single_instruction;
5148 dst : E(write);
5149 IALU : R;
5150 %}
5152 pipe_class loadPollP(iRegP poll) %{
5153 single_instruction;
5154 poll : R(read);
5155 MS : R;
5156 %}
5158 pipe_class br(Universe br, label labl) %{
5159 single_instruction_with_delay_slot;
5160 BR : R;
5161 %}
5163 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5164 single_instruction_with_delay_slot;
5165 cr : E(read);
5166 BR : R;
5167 %}
5169 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5170 single_instruction_with_delay_slot;
5171 op1 : E(read);
5172 BR : R;
5173 MS : R;
5174 %}
5176 // Compare and branch
5177 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5178 instruction_count(2); has_delay_slot;
5179 cr : E(write);
5180 src1 : R(read);
5181 src2 : R(read);
5182 IALU : R;
5183 BR : R;
5184 %}
5186 // Compare and branch
5187 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5188 instruction_count(2); has_delay_slot;
5189 cr : E(write);
5190 src1 : R(read);
5191 IALU : R;
5192 BR : R;
5193 %}
5195 // Compare and branch using cbcond
5196 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5197 single_instruction;
5198 src1 : E(read);
5199 src2 : E(read);
5200 IALU : R;
5201 BR : R;
5202 %}
5204 // Compare and branch using cbcond
5205 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5206 single_instruction;
5207 src1 : E(read);
5208 IALU : R;
5209 BR : R;
5210 %}
5212 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5213 single_instruction_with_delay_slot;
5214 cr : E(read);
5215 BR : R;
5216 %}
5218 pipe_class br_nop() %{
5219 single_instruction;
5220 BR : R;
5221 %}
5223 pipe_class simple_call(method meth) %{
5224 instruction_count(2); multiple_bundles; force_serialization;
5225 fixed_latency(100);
5226 BR : R(1);
5227 MS : R(1);
5228 A0 : R(1);
5229 %}
5231 pipe_class compiled_call(method meth) %{
5232 instruction_count(1); multiple_bundles; force_serialization;
5233 fixed_latency(100);
5234 MS : R(1);
5235 %}
5237 pipe_class call(method meth) %{
5238 instruction_count(0); multiple_bundles; force_serialization;
5239 fixed_latency(100);
5240 %}
5242 pipe_class tail_call(Universe ignore, label labl) %{
5243 single_instruction; has_delay_slot;
5244 fixed_latency(100);
5245 BR : R(1);
5246 MS : R(1);
5247 %}
5249 pipe_class ret(Universe ignore) %{
5250 single_instruction; has_delay_slot;
5251 BR : R(1);
5252 MS : R(1);
5253 %}
5255 pipe_class ret_poll(g3RegP poll) %{
5256 instruction_count(3); has_delay_slot;
5257 poll : E(read);
5258 MS : R;
5259 %}
5261 // The real do-nothing guy
5262 pipe_class empty( ) %{
5263 instruction_count(0);
5264 %}
5266 pipe_class long_memory_op() %{
5267 instruction_count(0); multiple_bundles; force_serialization;
5268 fixed_latency(25);
5269 MS : R(1);
5270 %}
5272 // Check-cast
5273 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5274 array : R(read);
5275 match : R(read);
5276 IALU : R(2);
5277 BR : R(2);
5278 MS : R;
5279 %}
5281 // Convert FPU flags into +1,0,-1
5282 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5283 src1 : E(read);
5284 src2 : E(read);
5285 dst : E(write);
5286 FA : R;
5287 MS : R(2);
5288 BR : R(2);
5289 %}
5291 // Compare for p < q, and conditionally add y
5292 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5293 p : E(read);
5294 q : E(read);
5295 y : E(read);
5296 IALU : R(3)
5297 %}
5299 // Perform a compare, then move conditionally in a branch delay slot.
5300 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5301 src2 : E(read);
5302 srcdst : E(read);
5303 IALU : R;
5304 BR : R;
5305 %}
5307 // Define the class for the Nop node
5308 define %{
5309 MachNop = ialu_nop;
5310 %}
5312 %}
5314 //----------INSTRUCTIONS-------------------------------------------------------
5316 //------------Special Stack Slot instructions - no match rules-----------------
5317 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5318 // No match rule to avoid chain rule match.
5319 effect(DEF dst, USE src);
5320 ins_cost(MEMORY_REF_COST);
5321 size(4);
5322 format %{ "LDF $src,$dst\t! stkI to regF" %}
5323 opcode(Assembler::ldf_op3);
5324 ins_encode(simple_form3_mem_reg(src, dst));
5325 ins_pipe(floadF_stk);
5326 %}
5328 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5329 // No match rule to avoid chain rule match.
5330 effect(DEF dst, USE src);
5331 ins_cost(MEMORY_REF_COST);
5332 size(4);
5333 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5334 opcode(Assembler::lddf_op3);
5335 ins_encode(simple_form3_mem_reg(src, dst));
5336 ins_pipe(floadD_stk);
5337 %}
5339 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5340 // No match rule to avoid chain rule match.
5341 effect(DEF dst, USE src);
5342 ins_cost(MEMORY_REF_COST);
5343 size(4);
5344 format %{ "STF $src,$dst\t! regF to stkI" %}
5345 opcode(Assembler::stf_op3);
5346 ins_encode(simple_form3_mem_reg(dst, src));
5347 ins_pipe(fstoreF_stk_reg);
5348 %}
5350 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5351 // No match rule to avoid chain rule match.
5352 effect(DEF dst, USE src);
5353 ins_cost(MEMORY_REF_COST);
5354 size(4);
5355 format %{ "STDF $src,$dst\t! regD to stkL" %}
5356 opcode(Assembler::stdf_op3);
5357 ins_encode(simple_form3_mem_reg(dst, src));
5358 ins_pipe(fstoreD_stk_reg);
5359 %}
5361 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5362 effect(DEF dst, USE src);
5363 ins_cost(MEMORY_REF_COST*2);
5364 size(8);
5365 format %{ "STW $src,$dst.hi\t! long\n\t"
5366 "STW R_G0,$dst.lo" %}
5367 opcode(Assembler::stw_op3);
5368 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5369 ins_pipe(lstoreI_stk_reg);
5370 %}
5372 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5373 // No match rule to avoid chain rule match.
5374 effect(DEF dst, USE src);
5375 ins_cost(MEMORY_REF_COST);
5376 size(4);
5377 format %{ "STX $src,$dst\t! regL to stkD" %}
5378 opcode(Assembler::stx_op3);
5379 ins_encode(simple_form3_mem_reg( dst, src ) );
5380 ins_pipe(istore_stk_reg);
5381 %}
5383 //---------- Chain stack slots between similar types --------
5385 // Load integer from stack slot
5386 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5387 match(Set dst src);
5388 ins_cost(MEMORY_REF_COST);
5390 size(4);
5391 format %{ "LDUW $src,$dst\t!stk" %}
5392 opcode(Assembler::lduw_op3);
5393 ins_encode(simple_form3_mem_reg( src, dst ) );
5394 ins_pipe(iload_mem);
5395 %}
5397 // Store integer to stack slot
5398 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5399 match(Set dst src);
5400 ins_cost(MEMORY_REF_COST);
5402 size(4);
5403 format %{ "STW $src,$dst\t!stk" %}
5404 opcode(Assembler::stw_op3);
5405 ins_encode(simple_form3_mem_reg( dst, src ) );
5406 ins_pipe(istore_mem_reg);
5407 %}
5409 // Load long from stack slot
5410 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5411 match(Set dst src);
5413 ins_cost(MEMORY_REF_COST);
5414 size(4);
5415 format %{ "LDX $src,$dst\t! long" %}
5416 opcode(Assembler::ldx_op3);
5417 ins_encode(simple_form3_mem_reg( src, dst ) );
5418 ins_pipe(iload_mem);
5419 %}
5421 // Store long to stack slot
5422 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5423 match(Set dst src);
5425 ins_cost(MEMORY_REF_COST);
5426 size(4);
5427 format %{ "STX $src,$dst\t! long" %}
5428 opcode(Assembler::stx_op3);
5429 ins_encode(simple_form3_mem_reg( dst, src ) );
5430 ins_pipe(istore_mem_reg);
5431 %}
5433 #ifdef _LP64
5434 // Load pointer from stack slot, 64-bit encoding
5435 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5436 match(Set dst src);
5437 ins_cost(MEMORY_REF_COST);
5438 size(4);
5439 format %{ "LDX $src,$dst\t!ptr" %}
5440 opcode(Assembler::ldx_op3);
5441 ins_encode(simple_form3_mem_reg( src, dst ) );
5442 ins_pipe(iload_mem);
5443 %}
5445 // Store pointer to stack slot
5446 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5447 match(Set dst src);
5448 ins_cost(MEMORY_REF_COST);
5449 size(4);
5450 format %{ "STX $src,$dst\t!ptr" %}
5451 opcode(Assembler::stx_op3);
5452 ins_encode(simple_form3_mem_reg( dst, src ) );
5453 ins_pipe(istore_mem_reg);
5454 %}
5455 #else // _LP64
5456 // Load pointer from stack slot, 32-bit encoding
5457 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5458 match(Set dst src);
5459 ins_cost(MEMORY_REF_COST);
5460 format %{ "LDUW $src,$dst\t!ptr" %}
5461 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5462 ins_encode(simple_form3_mem_reg( src, dst ) );
5463 ins_pipe(iload_mem);
5464 %}
5466 // Store pointer to stack slot
5467 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5468 match(Set dst src);
5469 ins_cost(MEMORY_REF_COST);
5470 format %{ "STW $src,$dst\t!ptr" %}
5471 opcode(Assembler::stw_op3, Assembler::ldst_op);
5472 ins_encode(simple_form3_mem_reg( dst, src ) );
5473 ins_pipe(istore_mem_reg);
5474 %}
5475 #endif // _LP64
5477 //------------Special Nop instructions for bundling - no match rules-----------
5478 // Nop using the A0 functional unit
5479 instruct Nop_A0() %{
5480 ins_cost(0);
5482 format %{ "NOP ! Alu Pipeline" %}
5483 opcode(Assembler::or_op3, Assembler::arith_op);
5484 ins_encode( form2_nop() );
5485 ins_pipe(ialu_nop_A0);
5486 %}
5488 // Nop using the A1 functional unit
5489 instruct Nop_A1( ) %{
5490 ins_cost(0);
5492 format %{ "NOP ! Alu Pipeline" %}
5493 opcode(Assembler::or_op3, Assembler::arith_op);
5494 ins_encode( form2_nop() );
5495 ins_pipe(ialu_nop_A1);
5496 %}
5498 // Nop using the memory functional unit
5499 instruct Nop_MS( ) %{
5500 ins_cost(0);
5502 format %{ "NOP ! Memory Pipeline" %}
5503 ins_encode( emit_mem_nop );
5504 ins_pipe(mem_nop);
5505 %}
5507 // Nop using the floating add functional unit
5508 instruct Nop_FA( ) %{
5509 ins_cost(0);
5511 format %{ "NOP ! Floating Add Pipeline" %}
5512 ins_encode( emit_fadd_nop );
5513 ins_pipe(fadd_nop);
5514 %}
5516 // Nop using the branch functional unit
5517 instruct Nop_BR( ) %{
5518 ins_cost(0);
5520 format %{ "NOP ! Branch Pipeline" %}
5521 ins_encode( emit_br_nop );
5522 ins_pipe(br_nop);
5523 %}
5525 //----------Load/Store/Move Instructions---------------------------------------
5526 //----------Load Instructions--------------------------------------------------
5527 // Load Byte (8bit signed)
5528 instruct loadB(iRegI dst, memory mem) %{
5529 match(Set dst (LoadB mem));
5530 ins_cost(MEMORY_REF_COST);
5532 size(4);
5533 format %{ "LDSB $mem,$dst\t! byte" %}
5534 ins_encode %{
5535 __ ldsb($mem$$Address, $dst$$Register);
5536 %}
5537 ins_pipe(iload_mask_mem);
5538 %}
5540 // Load Byte (8bit signed) into a Long Register
5541 instruct loadB2L(iRegL dst, memory mem) %{
5542 match(Set dst (ConvI2L (LoadB mem)));
5543 ins_cost(MEMORY_REF_COST);
5545 size(4);
5546 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5547 ins_encode %{
5548 __ ldsb($mem$$Address, $dst$$Register);
5549 %}
5550 ins_pipe(iload_mask_mem);
5551 %}
5553 // Load Unsigned Byte (8bit UNsigned) into an int reg
5554 instruct loadUB(iRegI dst, memory mem) %{
5555 match(Set dst (LoadUB mem));
5556 ins_cost(MEMORY_REF_COST);
5558 size(4);
5559 format %{ "LDUB $mem,$dst\t! ubyte" %}
5560 ins_encode %{
5561 __ ldub($mem$$Address, $dst$$Register);
5562 %}
5563 ins_pipe(iload_mem);
5564 %}
5566 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5567 instruct loadUB2L(iRegL dst, memory mem) %{
5568 match(Set dst (ConvI2L (LoadUB mem)));
5569 ins_cost(MEMORY_REF_COST);
5571 size(4);
5572 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5573 ins_encode %{
5574 __ ldub($mem$$Address, $dst$$Register);
5575 %}
5576 ins_pipe(iload_mem);
5577 %}
5579 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5580 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5581 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5582 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5584 size(2*4);
5585 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5586 "AND $dst,$mask,$dst" %}
5587 ins_encode %{
5588 __ ldub($mem$$Address, $dst$$Register);
5589 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5590 %}
5591 ins_pipe(iload_mem);
5592 %}
5594 // Load Short (16bit signed)
5595 instruct loadS(iRegI dst, memory mem) %{
5596 match(Set dst (LoadS mem));
5597 ins_cost(MEMORY_REF_COST);
5599 size(4);
5600 format %{ "LDSH $mem,$dst\t! short" %}
5601 ins_encode %{
5602 __ ldsh($mem$$Address, $dst$$Register);
5603 %}
5604 ins_pipe(iload_mask_mem);
5605 %}
5607 // Load Short (16 bit signed) to Byte (8 bit signed)
5608 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5609 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5610 ins_cost(MEMORY_REF_COST);
5612 size(4);
5614 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5615 ins_encode %{
5616 __ ldsb($mem$$Address, $dst$$Register, 1);
5617 %}
5618 ins_pipe(iload_mask_mem);
5619 %}
5621 // Load Short (16bit signed) into a Long Register
5622 instruct loadS2L(iRegL dst, memory mem) %{
5623 match(Set dst (ConvI2L (LoadS mem)));
5624 ins_cost(MEMORY_REF_COST);
5626 size(4);
5627 format %{ "LDSH $mem,$dst\t! short -> long" %}
5628 ins_encode %{
5629 __ ldsh($mem$$Address, $dst$$Register);
5630 %}
5631 ins_pipe(iload_mask_mem);
5632 %}
5634 // Load Unsigned Short/Char (16bit UNsigned)
5635 instruct loadUS(iRegI dst, memory mem) %{
5636 match(Set dst (LoadUS mem));
5637 ins_cost(MEMORY_REF_COST);
5639 size(4);
5640 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5641 ins_encode %{
5642 __ lduh($mem$$Address, $dst$$Register);
5643 %}
5644 ins_pipe(iload_mem);
5645 %}
5647 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5648 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5649 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5650 ins_cost(MEMORY_REF_COST);
5652 size(4);
5653 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5654 ins_encode %{
5655 __ ldsb($mem$$Address, $dst$$Register, 1);
5656 %}
5657 ins_pipe(iload_mask_mem);
5658 %}
5660 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5661 instruct loadUS2L(iRegL dst, memory mem) %{
5662 match(Set dst (ConvI2L (LoadUS mem)));
5663 ins_cost(MEMORY_REF_COST);
5665 size(4);
5666 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5667 ins_encode %{
5668 __ lduh($mem$$Address, $dst$$Register);
5669 %}
5670 ins_pipe(iload_mem);
5671 %}
5673 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5674 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5675 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5676 ins_cost(MEMORY_REF_COST);
5678 size(4);
5679 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5680 ins_encode %{
5681 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5682 %}
5683 ins_pipe(iload_mem);
5684 %}
5686 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5687 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5688 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5689 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5691 size(2*4);
5692 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5693 "AND $dst,$mask,$dst" %}
5694 ins_encode %{
5695 Register Rdst = $dst$$Register;
5696 __ lduh($mem$$Address, Rdst);
5697 __ and3(Rdst, $mask$$constant, Rdst);
5698 %}
5699 ins_pipe(iload_mem);
5700 %}
5702 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5703 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5704 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5705 effect(TEMP dst, TEMP tmp);
5706 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5708 size((3+1)*4); // set may use two instructions.
5709 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5710 "SET $mask,$tmp\n\t"
5711 "AND $dst,$tmp,$dst" %}
5712 ins_encode %{
5713 Register Rdst = $dst$$Register;
5714 Register Rtmp = $tmp$$Register;
5715 __ lduh($mem$$Address, Rdst);
5716 __ set($mask$$constant, Rtmp);
5717 __ and3(Rdst, Rtmp, Rdst);
5718 %}
5719 ins_pipe(iload_mem);
5720 %}
5722 // Load Integer
5723 instruct loadI(iRegI dst, memory mem) %{
5724 match(Set dst (LoadI mem));
5725 ins_cost(MEMORY_REF_COST);
5727 size(4);
5728 format %{ "LDUW $mem,$dst\t! int" %}
5729 ins_encode %{
5730 __ lduw($mem$$Address, $dst$$Register);
5731 %}
5732 ins_pipe(iload_mem);
5733 %}
5735 // Load Integer to Byte (8 bit signed)
5736 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5737 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5738 ins_cost(MEMORY_REF_COST);
5740 size(4);
5742 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5743 ins_encode %{
5744 __ ldsb($mem$$Address, $dst$$Register, 3);
5745 %}
5746 ins_pipe(iload_mask_mem);
5747 %}
5749 // Load Integer to Unsigned Byte (8 bit UNsigned)
5750 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5751 match(Set dst (AndI (LoadI mem) mask));
5752 ins_cost(MEMORY_REF_COST);
5754 size(4);
5756 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5757 ins_encode %{
5758 __ ldub($mem$$Address, $dst$$Register, 3);
5759 %}
5760 ins_pipe(iload_mask_mem);
5761 %}
5763 // Load Integer to Short (16 bit signed)
5764 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5765 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5766 ins_cost(MEMORY_REF_COST);
5768 size(4);
5770 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5771 ins_encode %{
5772 __ ldsh($mem$$Address, $dst$$Register, 2);
5773 %}
5774 ins_pipe(iload_mask_mem);
5775 %}
5777 // Load Integer to Unsigned Short (16 bit UNsigned)
5778 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5779 match(Set dst (AndI (LoadI mem) mask));
5780 ins_cost(MEMORY_REF_COST);
5782 size(4);
5784 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5785 ins_encode %{
5786 __ lduh($mem$$Address, $dst$$Register, 2);
5787 %}
5788 ins_pipe(iload_mask_mem);
5789 %}
5791 // Load Integer into a Long Register
5792 instruct loadI2L(iRegL dst, memory mem) %{
5793 match(Set dst (ConvI2L (LoadI mem)));
5794 ins_cost(MEMORY_REF_COST);
5796 size(4);
5797 format %{ "LDSW $mem,$dst\t! int -> long" %}
5798 ins_encode %{
5799 __ ldsw($mem$$Address, $dst$$Register);
5800 %}
5801 ins_pipe(iload_mask_mem);
5802 %}
5804 // Load Integer with mask 0xFF into a Long Register
5805 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5806 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5807 ins_cost(MEMORY_REF_COST);
5809 size(4);
5810 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5811 ins_encode %{
5812 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5813 %}
5814 ins_pipe(iload_mem);
5815 %}
5817 // Load Integer with mask 0xFFFF into a Long Register
5818 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5819 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5820 ins_cost(MEMORY_REF_COST);
5822 size(4);
5823 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5824 ins_encode %{
5825 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5826 %}
5827 ins_pipe(iload_mem);
5828 %}
5830 // Load Integer with a 13-bit mask into a Long Register
5831 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5832 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5833 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5835 size(2*4);
5836 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5837 "AND $dst,$mask,$dst" %}
5838 ins_encode %{
5839 Register Rdst = $dst$$Register;
5840 __ lduw($mem$$Address, Rdst);
5841 __ and3(Rdst, $mask$$constant, Rdst);
5842 %}
5843 ins_pipe(iload_mem);
5844 %}
5846 // Load Integer with a 32-bit mask into a Long Register
5847 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5848 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5849 effect(TEMP dst, TEMP tmp);
5850 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5852 size((3+1)*4); // set may use two instructions.
5853 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5854 "SET $mask,$tmp\n\t"
5855 "AND $dst,$tmp,$dst" %}
5856 ins_encode %{
5857 Register Rdst = $dst$$Register;
5858 Register Rtmp = $tmp$$Register;
5859 __ lduw($mem$$Address, Rdst);
5860 __ set($mask$$constant, Rtmp);
5861 __ and3(Rdst, Rtmp, Rdst);
5862 %}
5863 ins_pipe(iload_mem);
5864 %}
5866 // Load Unsigned Integer into a Long Register
5867 instruct loadUI2L(iRegL dst, memory mem) %{
5868 match(Set dst (LoadUI2L mem));
5869 ins_cost(MEMORY_REF_COST);
5871 size(4);
5872 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5873 ins_encode %{
5874 __ lduw($mem$$Address, $dst$$Register);
5875 %}
5876 ins_pipe(iload_mem);
5877 %}
5879 // Load Long - aligned
5880 instruct loadL(iRegL dst, memory mem ) %{
5881 match(Set dst (LoadL mem));
5882 ins_cost(MEMORY_REF_COST);
5884 size(4);
5885 format %{ "LDX $mem,$dst\t! long" %}
5886 ins_encode %{
5887 __ ldx($mem$$Address, $dst$$Register);
5888 %}
5889 ins_pipe(iload_mem);
5890 %}
5892 // Load Long - UNaligned
5893 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5894 match(Set dst (LoadL_unaligned mem));
5895 effect(KILL tmp);
5896 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5897 size(16);
5898 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5899 "\tLDUW $mem ,$dst\n"
5900 "\tSLLX #32, $dst, $dst\n"
5901 "\tOR $dst, R_O7, $dst" %}
5902 opcode(Assembler::lduw_op3);
5903 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5904 ins_pipe(iload_mem);
5905 %}
5907 // Load Aligned Packed Byte into a Double Register
5908 instruct loadA8B(regD dst, memory mem) %{
5909 match(Set dst (Load8B mem));
5910 ins_cost(MEMORY_REF_COST);
5911 size(4);
5912 format %{ "LDDF $mem,$dst\t! packed8B" %}
5913 opcode(Assembler::lddf_op3);
5914 ins_encode(simple_form3_mem_reg( mem, dst ) );
5915 ins_pipe(floadD_mem);
5916 %}
5918 // Load Aligned Packed Char into a Double Register
5919 instruct loadA4C(regD dst, memory mem) %{
5920 match(Set dst (Load4C mem));
5921 ins_cost(MEMORY_REF_COST);
5922 size(4);
5923 format %{ "LDDF $mem,$dst\t! packed4C" %}
5924 opcode(Assembler::lddf_op3);
5925 ins_encode(simple_form3_mem_reg( mem, dst ) );
5926 ins_pipe(floadD_mem);
5927 %}
5929 // Load Aligned Packed Short into a Double Register
5930 instruct loadA4S(regD dst, memory mem) %{
5931 match(Set dst (Load4S mem));
5932 ins_cost(MEMORY_REF_COST);
5933 size(4);
5934 format %{ "LDDF $mem,$dst\t! packed4S" %}
5935 opcode(Assembler::lddf_op3);
5936 ins_encode(simple_form3_mem_reg( mem, dst ) );
5937 ins_pipe(floadD_mem);
5938 %}
5940 // Load Aligned Packed Int into a Double Register
5941 instruct loadA2I(regD dst, memory mem) %{
5942 match(Set dst (Load2I mem));
5943 ins_cost(MEMORY_REF_COST);
5944 size(4);
5945 format %{ "LDDF $mem,$dst\t! packed2I" %}
5946 opcode(Assembler::lddf_op3);
5947 ins_encode(simple_form3_mem_reg( mem, dst ) );
5948 ins_pipe(floadD_mem);
5949 %}
5951 // Load Range
5952 instruct loadRange(iRegI dst, memory mem) %{
5953 match(Set dst (LoadRange mem));
5954 ins_cost(MEMORY_REF_COST);
5956 size(4);
5957 format %{ "LDUW $mem,$dst\t! range" %}
5958 opcode(Assembler::lduw_op3);
5959 ins_encode(simple_form3_mem_reg( mem, dst ) );
5960 ins_pipe(iload_mem);
5961 %}
5963 // Load Integer into %f register (for fitos/fitod)
5964 instruct loadI_freg(regF dst, memory mem) %{
5965 match(Set dst (LoadI mem));
5966 ins_cost(MEMORY_REF_COST);
5967 size(4);
5969 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5970 opcode(Assembler::ldf_op3);
5971 ins_encode(simple_form3_mem_reg( mem, dst ) );
5972 ins_pipe(floadF_mem);
5973 %}
5975 // Load Pointer
5976 instruct loadP(iRegP dst, memory mem) %{
5977 match(Set dst (LoadP mem));
5978 ins_cost(MEMORY_REF_COST);
5979 size(4);
5981 #ifndef _LP64
5982 format %{ "LDUW $mem,$dst\t! ptr" %}
5983 ins_encode %{
5984 __ lduw($mem$$Address, $dst$$Register);
5985 %}
5986 #else
5987 format %{ "LDX $mem,$dst\t! ptr" %}
5988 ins_encode %{
5989 __ ldx($mem$$Address, $dst$$Register);
5990 %}
5991 #endif
5992 ins_pipe(iload_mem);
5993 %}
5995 // Load Compressed Pointer
5996 instruct loadN(iRegN dst, memory mem) %{
5997 match(Set dst (LoadN mem));
5998 ins_cost(MEMORY_REF_COST);
5999 size(4);
6001 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
6002 ins_encode %{
6003 __ lduw($mem$$Address, $dst$$Register);
6004 %}
6005 ins_pipe(iload_mem);
6006 %}
6008 // Load Klass Pointer
6009 instruct loadKlass(iRegP dst, memory mem) %{
6010 match(Set dst (LoadKlass mem));
6011 ins_cost(MEMORY_REF_COST);
6012 size(4);
6014 #ifndef _LP64
6015 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6016 ins_encode %{
6017 __ lduw($mem$$Address, $dst$$Register);
6018 %}
6019 #else
6020 format %{ "LDX $mem,$dst\t! klass ptr" %}
6021 ins_encode %{
6022 __ ldx($mem$$Address, $dst$$Register);
6023 %}
6024 #endif
6025 ins_pipe(iload_mem);
6026 %}
6028 // Load narrow Klass Pointer
6029 instruct loadNKlass(iRegN dst, memory mem) %{
6030 match(Set dst (LoadNKlass mem));
6031 ins_cost(MEMORY_REF_COST);
6032 size(4);
6034 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6035 ins_encode %{
6036 __ lduw($mem$$Address, $dst$$Register);
6037 %}
6038 ins_pipe(iload_mem);
6039 %}
6041 // Load Double
6042 instruct loadD(regD dst, memory mem) %{
6043 match(Set dst (LoadD mem));
6044 ins_cost(MEMORY_REF_COST);
6046 size(4);
6047 format %{ "LDDF $mem,$dst" %}
6048 opcode(Assembler::lddf_op3);
6049 ins_encode(simple_form3_mem_reg( mem, dst ) );
6050 ins_pipe(floadD_mem);
6051 %}
6053 // Load Double - UNaligned
6054 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6055 match(Set dst (LoadD_unaligned mem));
6056 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6057 size(8);
6058 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6059 "\tLDF $mem+4,$dst.lo\t!" %}
6060 opcode(Assembler::ldf_op3);
6061 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6062 ins_pipe(iload_mem);
6063 %}
6065 // Load Float
6066 instruct loadF(regF dst, memory mem) %{
6067 match(Set dst (LoadF mem));
6068 ins_cost(MEMORY_REF_COST);
6070 size(4);
6071 format %{ "LDF $mem,$dst" %}
6072 opcode(Assembler::ldf_op3);
6073 ins_encode(simple_form3_mem_reg( mem, dst ) );
6074 ins_pipe(floadF_mem);
6075 %}
6077 // Load Constant
6078 instruct loadConI( iRegI dst, immI src ) %{
6079 match(Set dst src);
6080 ins_cost(DEFAULT_COST * 3/2);
6081 format %{ "SET $src,$dst" %}
6082 ins_encode( Set32(src, dst) );
6083 ins_pipe(ialu_hi_lo_reg);
6084 %}
6086 instruct loadConI13( iRegI dst, immI13 src ) %{
6087 match(Set dst src);
6089 size(4);
6090 format %{ "MOV $src,$dst" %}
6091 ins_encode( Set13( src, dst ) );
6092 ins_pipe(ialu_imm);
6093 %}
6095 #ifndef _LP64
6096 instruct loadConP(iRegP dst, immP con) %{
6097 match(Set dst con);
6098 ins_cost(DEFAULT_COST * 3/2);
6099 format %{ "SET $con,$dst\t!ptr" %}
6100 ins_encode %{
6101 // [RGV] This next line should be generated from ADLC
6102 if (_opnds[1]->constant_is_oop()) {
6103 intptr_t val = $con$$constant;
6104 __ set_oop_constant((jobject) val, $dst$$Register);
6105 } else { // non-oop pointers, e.g. card mark base, heap top
6106 __ set($con$$constant, $dst$$Register);
6107 }
6108 %}
6109 ins_pipe(loadConP);
6110 %}
6111 #else
6112 instruct loadConP_set(iRegP dst, immP_set con) %{
6113 match(Set dst con);
6114 ins_cost(DEFAULT_COST * 3/2);
6115 format %{ "SET $con,$dst\t! ptr" %}
6116 ins_encode %{
6117 // [RGV] This next line should be generated from ADLC
6118 if (_opnds[1]->constant_is_oop()) {
6119 intptr_t val = $con$$constant;
6120 __ set_oop_constant((jobject) val, $dst$$Register);
6121 } else { // non-oop pointers, e.g. card mark base, heap top
6122 __ set($con$$constant, $dst$$Register);
6123 }
6124 %}
6125 ins_pipe(loadConP);
6126 %}
6128 instruct loadConP_load(iRegP dst, immP_load con) %{
6129 match(Set dst con);
6130 ins_cost(MEMORY_REF_COST);
6131 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6132 ins_encode %{
6133 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6134 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6135 %}
6136 ins_pipe(loadConP);
6137 %}
6139 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6140 match(Set dst con);
6141 ins_cost(DEFAULT_COST * 3/2);
6142 format %{ "SET $con,$dst\t! non-oop ptr" %}
6143 ins_encode %{
6144 __ set($con$$constant, $dst$$Register);
6145 %}
6146 ins_pipe(loadConP);
6147 %}
6148 #endif // _LP64
6150 instruct loadConP0(iRegP dst, immP0 src) %{
6151 match(Set dst src);
6153 size(4);
6154 format %{ "CLR $dst\t!ptr" %}
6155 ins_encode %{
6156 __ clr($dst$$Register);
6157 %}
6158 ins_pipe(ialu_imm);
6159 %}
6161 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6162 match(Set dst src);
6163 ins_cost(DEFAULT_COST);
6164 format %{ "SET $src,$dst\t!ptr" %}
6165 ins_encode %{
6166 AddressLiteral polling_page(os::get_polling_page());
6167 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6168 %}
6169 ins_pipe(loadConP_poll);
6170 %}
6172 instruct loadConN0(iRegN dst, immN0 src) %{
6173 match(Set dst src);
6175 size(4);
6176 format %{ "CLR $dst\t! compressed NULL ptr" %}
6177 ins_encode %{
6178 __ clr($dst$$Register);
6179 %}
6180 ins_pipe(ialu_imm);
6181 %}
6183 instruct loadConN(iRegN dst, immN src) %{
6184 match(Set dst src);
6185 ins_cost(DEFAULT_COST * 3/2);
6186 format %{ "SET $src,$dst\t! compressed ptr" %}
6187 ins_encode %{
6188 Register dst = $dst$$Register;
6189 __ set_narrow_oop((jobject)$src$$constant, dst);
6190 %}
6191 ins_pipe(ialu_hi_lo_reg);
6192 %}
6194 // Materialize long value (predicated by immL_cheap).
6195 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6196 match(Set dst con);
6197 effect(KILL tmp);
6198 ins_cost(DEFAULT_COST * 3);
6199 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6200 ins_encode %{
6201 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6202 %}
6203 ins_pipe(loadConL);
6204 %}
6206 // Load long value from constant table (predicated by immL_expensive).
6207 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6208 match(Set dst con);
6209 ins_cost(MEMORY_REF_COST);
6210 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6211 ins_encode %{
6212 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6213 __ ldx($constanttablebase, con_offset, $dst$$Register);
6214 %}
6215 ins_pipe(loadConL);
6216 %}
6218 instruct loadConL0( iRegL dst, immL0 src ) %{
6219 match(Set dst src);
6220 ins_cost(DEFAULT_COST);
6221 size(4);
6222 format %{ "CLR $dst\t! long" %}
6223 ins_encode( Set13( src, dst ) );
6224 ins_pipe(ialu_imm);
6225 %}
6227 instruct loadConL13( iRegL dst, immL13 src ) %{
6228 match(Set dst src);
6229 ins_cost(DEFAULT_COST * 2);
6231 size(4);
6232 format %{ "MOV $src,$dst\t! long" %}
6233 ins_encode( Set13( src, dst ) );
6234 ins_pipe(ialu_imm);
6235 %}
6237 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6238 match(Set dst con);
6239 effect(KILL tmp);
6240 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6241 ins_encode %{
6242 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6243 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6244 %}
6245 ins_pipe(loadConFD);
6246 %}
6248 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6249 match(Set dst con);
6250 effect(KILL tmp);
6251 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6252 ins_encode %{
6253 // XXX This is a quick fix for 6833573.
6254 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6255 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6256 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6257 %}
6258 ins_pipe(loadConFD);
6259 %}
6261 // Prefetch instructions.
6262 // Must be safe to execute with invalid address (cannot fault).
6264 instruct prefetchr( memory mem ) %{
6265 match( PrefetchRead mem );
6266 ins_cost(MEMORY_REF_COST);
6267 size(4);
6269 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6270 opcode(Assembler::prefetch_op3);
6271 ins_encode( form3_mem_prefetch_read( mem ) );
6272 ins_pipe(iload_mem);
6273 %}
6275 instruct prefetchw( memory mem ) %{
6276 match( PrefetchWrite mem );
6277 ins_cost(MEMORY_REF_COST);
6278 size(4);
6280 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6281 opcode(Assembler::prefetch_op3);
6282 ins_encode( form3_mem_prefetch_write( mem ) );
6283 ins_pipe(iload_mem);
6284 %}
6286 // Prefetch instructions for allocation.
6288 instruct prefetchAlloc( memory mem ) %{
6289 predicate(AllocatePrefetchInstr == 0);
6290 match( PrefetchAllocation mem );
6291 ins_cost(MEMORY_REF_COST);
6292 size(4);
6294 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6295 opcode(Assembler::prefetch_op3);
6296 ins_encode( form3_mem_prefetch_write( mem ) );
6297 ins_pipe(iload_mem);
6298 %}
6300 // Use BIS instruction to prefetch for allocation.
6301 // Could fault, need space at the end of TLAB.
6302 instruct prefetchAlloc_bis( iRegP dst ) %{
6303 predicate(AllocatePrefetchInstr == 1);
6304 match( PrefetchAllocation dst );
6305 ins_cost(MEMORY_REF_COST);
6306 size(4);
6308 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6309 ins_encode %{
6310 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6311 %}
6312 ins_pipe(istore_mem_reg);
6313 %}
6315 // Next code is used for finding next cache line address to prefetch.
6316 #ifndef _LP64
6317 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6318 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6319 ins_cost(DEFAULT_COST);
6320 size(4);
6322 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6323 ins_encode %{
6324 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6325 %}
6326 ins_pipe(ialu_reg_imm);
6327 %}
6328 #else
6329 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6330 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6331 ins_cost(DEFAULT_COST);
6332 size(4);
6334 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6335 ins_encode %{
6336 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6337 %}
6338 ins_pipe(ialu_reg_imm);
6339 %}
6340 #endif
6342 //----------Store Instructions-------------------------------------------------
6343 // Store Byte
6344 instruct storeB(memory mem, iRegI src) %{
6345 match(Set mem (StoreB mem src));
6346 ins_cost(MEMORY_REF_COST);
6348 size(4);
6349 format %{ "STB $src,$mem\t! byte" %}
6350 opcode(Assembler::stb_op3);
6351 ins_encode(simple_form3_mem_reg( mem, src ) );
6352 ins_pipe(istore_mem_reg);
6353 %}
6355 instruct storeB0(memory mem, immI0 src) %{
6356 match(Set mem (StoreB mem src));
6357 ins_cost(MEMORY_REF_COST);
6359 size(4);
6360 format %{ "STB $src,$mem\t! byte" %}
6361 opcode(Assembler::stb_op3);
6362 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6363 ins_pipe(istore_mem_zero);
6364 %}
6366 instruct storeCM0(memory mem, immI0 src) %{
6367 match(Set mem (StoreCM mem src));
6368 ins_cost(MEMORY_REF_COST);
6370 size(4);
6371 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6372 opcode(Assembler::stb_op3);
6373 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6374 ins_pipe(istore_mem_zero);
6375 %}
6377 // Store Char/Short
6378 instruct storeC(memory mem, iRegI src) %{
6379 match(Set mem (StoreC mem src));
6380 ins_cost(MEMORY_REF_COST);
6382 size(4);
6383 format %{ "STH $src,$mem\t! short" %}
6384 opcode(Assembler::sth_op3);
6385 ins_encode(simple_form3_mem_reg( mem, src ) );
6386 ins_pipe(istore_mem_reg);
6387 %}
6389 instruct storeC0(memory mem, immI0 src) %{
6390 match(Set mem (StoreC mem src));
6391 ins_cost(MEMORY_REF_COST);
6393 size(4);
6394 format %{ "STH $src,$mem\t! short" %}
6395 opcode(Assembler::sth_op3);
6396 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6397 ins_pipe(istore_mem_zero);
6398 %}
6400 // Store Integer
6401 instruct storeI(memory mem, iRegI src) %{
6402 match(Set mem (StoreI mem src));
6403 ins_cost(MEMORY_REF_COST);
6405 size(4);
6406 format %{ "STW $src,$mem" %}
6407 opcode(Assembler::stw_op3);
6408 ins_encode(simple_form3_mem_reg( mem, src ) );
6409 ins_pipe(istore_mem_reg);
6410 %}
6412 // Store Long
6413 instruct storeL(memory mem, iRegL src) %{
6414 match(Set mem (StoreL mem src));
6415 ins_cost(MEMORY_REF_COST);
6416 size(4);
6417 format %{ "STX $src,$mem\t! long" %}
6418 opcode(Assembler::stx_op3);
6419 ins_encode(simple_form3_mem_reg( mem, src ) );
6420 ins_pipe(istore_mem_reg);
6421 %}
6423 instruct storeI0(memory mem, immI0 src) %{
6424 match(Set mem (StoreI mem src));
6425 ins_cost(MEMORY_REF_COST);
6427 size(4);
6428 format %{ "STW $src,$mem" %}
6429 opcode(Assembler::stw_op3);
6430 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6431 ins_pipe(istore_mem_zero);
6432 %}
6434 instruct storeL0(memory mem, immL0 src) %{
6435 match(Set mem (StoreL mem src));
6436 ins_cost(MEMORY_REF_COST);
6438 size(4);
6439 format %{ "STX $src,$mem" %}
6440 opcode(Assembler::stx_op3);
6441 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6442 ins_pipe(istore_mem_zero);
6443 %}
6445 // Store Integer from float register (used after fstoi)
6446 instruct storeI_Freg(memory mem, regF src) %{
6447 match(Set mem (StoreI mem src));
6448 ins_cost(MEMORY_REF_COST);
6450 size(4);
6451 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6452 opcode(Assembler::stf_op3);
6453 ins_encode(simple_form3_mem_reg( mem, src ) );
6454 ins_pipe(fstoreF_mem_reg);
6455 %}
6457 // Store Pointer
6458 instruct storeP(memory dst, sp_ptr_RegP src) %{
6459 match(Set dst (StoreP dst src));
6460 ins_cost(MEMORY_REF_COST);
6461 size(4);
6463 #ifndef _LP64
6464 format %{ "STW $src,$dst\t! ptr" %}
6465 opcode(Assembler::stw_op3, 0, REGP_OP);
6466 #else
6467 format %{ "STX $src,$dst\t! ptr" %}
6468 opcode(Assembler::stx_op3, 0, REGP_OP);
6469 #endif
6470 ins_encode( form3_mem_reg( dst, src ) );
6471 ins_pipe(istore_mem_spORreg);
6472 %}
6474 instruct storeP0(memory dst, immP0 src) %{
6475 match(Set dst (StoreP dst src));
6476 ins_cost(MEMORY_REF_COST);
6477 size(4);
6479 #ifndef _LP64
6480 format %{ "STW $src,$dst\t! ptr" %}
6481 opcode(Assembler::stw_op3, 0, REGP_OP);
6482 #else
6483 format %{ "STX $src,$dst\t! ptr" %}
6484 opcode(Assembler::stx_op3, 0, REGP_OP);
6485 #endif
6486 ins_encode( form3_mem_reg( dst, R_G0 ) );
6487 ins_pipe(istore_mem_zero);
6488 %}
6490 // Store Compressed Pointer
6491 instruct storeN(memory dst, iRegN src) %{
6492 match(Set dst (StoreN dst src));
6493 ins_cost(MEMORY_REF_COST);
6494 size(4);
6496 format %{ "STW $src,$dst\t! compressed ptr" %}
6497 ins_encode %{
6498 Register base = as_Register($dst$$base);
6499 Register index = as_Register($dst$$index);
6500 Register src = $src$$Register;
6501 if (index != G0) {
6502 __ stw(src, base, index);
6503 } else {
6504 __ stw(src, base, $dst$$disp);
6505 }
6506 %}
6507 ins_pipe(istore_mem_spORreg);
6508 %}
6510 instruct storeN0(memory dst, immN0 src) %{
6511 match(Set dst (StoreN dst src));
6512 ins_cost(MEMORY_REF_COST);
6513 size(4);
6515 format %{ "STW $src,$dst\t! compressed ptr" %}
6516 ins_encode %{
6517 Register base = as_Register($dst$$base);
6518 Register index = as_Register($dst$$index);
6519 if (index != G0) {
6520 __ stw(0, base, index);
6521 } else {
6522 __ stw(0, base, $dst$$disp);
6523 }
6524 %}
6525 ins_pipe(istore_mem_zero);
6526 %}
6528 // Store Double
6529 instruct storeD( memory mem, regD src) %{
6530 match(Set mem (StoreD mem src));
6531 ins_cost(MEMORY_REF_COST);
6533 size(4);
6534 format %{ "STDF $src,$mem" %}
6535 opcode(Assembler::stdf_op3);
6536 ins_encode(simple_form3_mem_reg( mem, src ) );
6537 ins_pipe(fstoreD_mem_reg);
6538 %}
6540 instruct storeD0( memory mem, immD0 src) %{
6541 match(Set mem (StoreD mem src));
6542 ins_cost(MEMORY_REF_COST);
6544 size(4);
6545 format %{ "STX $src,$mem" %}
6546 opcode(Assembler::stx_op3);
6547 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6548 ins_pipe(fstoreD_mem_zero);
6549 %}
6551 // Store Float
6552 instruct storeF( memory mem, regF src) %{
6553 match(Set mem (StoreF mem src));
6554 ins_cost(MEMORY_REF_COST);
6556 size(4);
6557 format %{ "STF $src,$mem" %}
6558 opcode(Assembler::stf_op3);
6559 ins_encode(simple_form3_mem_reg( mem, src ) );
6560 ins_pipe(fstoreF_mem_reg);
6561 %}
6563 instruct storeF0( memory mem, immF0 src) %{
6564 match(Set mem (StoreF mem src));
6565 ins_cost(MEMORY_REF_COST);
6567 size(4);
6568 format %{ "STW $src,$mem\t! storeF0" %}
6569 opcode(Assembler::stw_op3);
6570 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6571 ins_pipe(fstoreF_mem_zero);
6572 %}
6574 // Store Aligned Packed Bytes in Double register to memory
6575 instruct storeA8B(memory mem, regD src) %{
6576 match(Set mem (Store8B mem src));
6577 ins_cost(MEMORY_REF_COST);
6578 size(4);
6579 format %{ "STDF $src,$mem\t! packed8B" %}
6580 opcode(Assembler::stdf_op3);
6581 ins_encode(simple_form3_mem_reg( mem, src ) );
6582 ins_pipe(fstoreD_mem_reg);
6583 %}
6585 // Convert oop pointer into compressed form
6586 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6587 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6588 match(Set dst (EncodeP src));
6589 format %{ "encode_heap_oop $src, $dst" %}
6590 ins_encode %{
6591 __ encode_heap_oop($src$$Register, $dst$$Register);
6592 %}
6593 ins_pipe(ialu_reg);
6594 %}
6596 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6597 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6598 match(Set dst (EncodeP src));
6599 format %{ "encode_heap_oop_not_null $src, $dst" %}
6600 ins_encode %{
6601 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6602 %}
6603 ins_pipe(ialu_reg);
6604 %}
6606 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6607 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6608 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6609 match(Set dst (DecodeN src));
6610 format %{ "decode_heap_oop $src, $dst" %}
6611 ins_encode %{
6612 __ decode_heap_oop($src$$Register, $dst$$Register);
6613 %}
6614 ins_pipe(ialu_reg);
6615 %}
6617 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6618 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6619 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6620 match(Set dst (DecodeN src));
6621 format %{ "decode_heap_oop_not_null $src, $dst" %}
6622 ins_encode %{
6623 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6624 %}
6625 ins_pipe(ialu_reg);
6626 %}
6629 // Store Zero into Aligned Packed Bytes
6630 instruct storeA8B0(memory mem, immI0 zero) %{
6631 match(Set mem (Store8B mem zero));
6632 ins_cost(MEMORY_REF_COST);
6633 size(4);
6634 format %{ "STX $zero,$mem\t! packed8B" %}
6635 opcode(Assembler::stx_op3);
6636 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6637 ins_pipe(fstoreD_mem_zero);
6638 %}
6640 // Store Aligned Packed Chars/Shorts in Double register to memory
6641 instruct storeA4C(memory mem, regD src) %{
6642 match(Set mem (Store4C mem src));
6643 ins_cost(MEMORY_REF_COST);
6644 size(4);
6645 format %{ "STDF $src,$mem\t! packed4C" %}
6646 opcode(Assembler::stdf_op3);
6647 ins_encode(simple_form3_mem_reg( mem, src ) );
6648 ins_pipe(fstoreD_mem_reg);
6649 %}
6651 // Store Zero into Aligned Packed Chars/Shorts
6652 instruct storeA4C0(memory mem, immI0 zero) %{
6653 match(Set mem (Store4C mem (Replicate4C zero)));
6654 ins_cost(MEMORY_REF_COST);
6655 size(4);
6656 format %{ "STX $zero,$mem\t! packed4C" %}
6657 opcode(Assembler::stx_op3);
6658 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6659 ins_pipe(fstoreD_mem_zero);
6660 %}
6662 // Store Aligned Packed Ints in Double register to memory
6663 instruct storeA2I(memory mem, regD src) %{
6664 match(Set mem (Store2I mem src));
6665 ins_cost(MEMORY_REF_COST);
6666 size(4);
6667 format %{ "STDF $src,$mem\t! packed2I" %}
6668 opcode(Assembler::stdf_op3);
6669 ins_encode(simple_form3_mem_reg( mem, src ) );
6670 ins_pipe(fstoreD_mem_reg);
6671 %}
6673 // Store Zero into Aligned Packed Ints
6674 instruct storeA2I0(memory mem, immI0 zero) %{
6675 match(Set mem (Store2I mem zero));
6676 ins_cost(MEMORY_REF_COST);
6677 size(4);
6678 format %{ "STX $zero,$mem\t! packed2I" %}
6679 opcode(Assembler::stx_op3);
6680 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6681 ins_pipe(fstoreD_mem_zero);
6682 %}
6685 //----------MemBar Instructions-----------------------------------------------
6686 // Memory barrier flavors
6688 instruct membar_acquire() %{
6689 match(MemBarAcquire);
6690 ins_cost(4*MEMORY_REF_COST);
6692 size(0);
6693 format %{ "MEMBAR-acquire" %}
6694 ins_encode( enc_membar_acquire );
6695 ins_pipe(long_memory_op);
6696 %}
6698 instruct membar_acquire_lock() %{
6699 match(MemBarAcquireLock);
6700 ins_cost(0);
6702 size(0);
6703 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6704 ins_encode( );
6705 ins_pipe(empty);
6706 %}
6708 instruct membar_release() %{
6709 match(MemBarRelease);
6710 ins_cost(4*MEMORY_REF_COST);
6712 size(0);
6713 format %{ "MEMBAR-release" %}
6714 ins_encode( enc_membar_release );
6715 ins_pipe(long_memory_op);
6716 %}
6718 instruct membar_release_lock() %{
6719 match(MemBarReleaseLock);
6720 ins_cost(0);
6722 size(0);
6723 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6724 ins_encode( );
6725 ins_pipe(empty);
6726 %}
6728 instruct membar_volatile() %{
6729 match(MemBarVolatile);
6730 ins_cost(4*MEMORY_REF_COST);
6732 size(4);
6733 format %{ "MEMBAR-volatile" %}
6734 ins_encode( enc_membar_volatile );
6735 ins_pipe(long_memory_op);
6736 %}
6738 instruct unnecessary_membar_volatile() %{
6739 match(MemBarVolatile);
6740 predicate(Matcher::post_store_load_barrier(n));
6741 ins_cost(0);
6743 size(0);
6744 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6745 ins_encode( );
6746 ins_pipe(empty);
6747 %}
6749 //----------Register Move Instructions-----------------------------------------
6750 instruct roundDouble_nop(regD dst) %{
6751 match(Set dst (RoundDouble dst));
6752 ins_cost(0);
6753 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6754 ins_encode( );
6755 ins_pipe(empty);
6756 %}
6759 instruct roundFloat_nop(regF dst) %{
6760 match(Set dst (RoundFloat dst));
6761 ins_cost(0);
6762 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6763 ins_encode( );
6764 ins_pipe(empty);
6765 %}
6768 // Cast Index to Pointer for unsafe natives
6769 instruct castX2P(iRegX src, iRegP dst) %{
6770 match(Set dst (CastX2P src));
6772 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6773 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6774 ins_pipe(ialu_reg);
6775 %}
6777 // Cast Pointer to Index for unsafe natives
6778 instruct castP2X(iRegP src, iRegX dst) %{
6779 match(Set dst (CastP2X src));
6781 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6782 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6783 ins_pipe(ialu_reg);
6784 %}
6786 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6787 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6788 match(Set stkSlot src); // chain rule
6789 ins_cost(MEMORY_REF_COST);
6790 format %{ "STDF $src,$stkSlot\t!stk" %}
6791 opcode(Assembler::stdf_op3);
6792 ins_encode(simple_form3_mem_reg(stkSlot, src));
6793 ins_pipe(fstoreD_stk_reg);
6794 %}
6796 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6797 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6798 match(Set dst stkSlot); // chain rule
6799 ins_cost(MEMORY_REF_COST);
6800 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6801 opcode(Assembler::lddf_op3);
6802 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6803 ins_pipe(floadD_stk);
6804 %}
6806 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6807 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6808 match(Set stkSlot src); // chain rule
6809 ins_cost(MEMORY_REF_COST);
6810 format %{ "STF $src,$stkSlot\t!stk" %}
6811 opcode(Assembler::stf_op3);
6812 ins_encode(simple_form3_mem_reg(stkSlot, src));
6813 ins_pipe(fstoreF_stk_reg);
6814 %}
6816 //----------Conditional Move---------------------------------------------------
6817 // Conditional move
6818 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6819 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6820 ins_cost(150);
6821 format %{ "MOV$cmp $pcc,$src,$dst" %}
6822 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6823 ins_pipe(ialu_reg);
6824 %}
6826 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6827 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6828 ins_cost(140);
6829 format %{ "MOV$cmp $pcc,$src,$dst" %}
6830 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6831 ins_pipe(ialu_imm);
6832 %}
6834 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6835 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6836 ins_cost(150);
6837 size(4);
6838 format %{ "MOV$cmp $icc,$src,$dst" %}
6839 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6840 ins_pipe(ialu_reg);
6841 %}
6843 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6844 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6845 ins_cost(140);
6846 size(4);
6847 format %{ "MOV$cmp $icc,$src,$dst" %}
6848 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6849 ins_pipe(ialu_imm);
6850 %}
6852 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6853 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6854 ins_cost(150);
6855 size(4);
6856 format %{ "MOV$cmp $icc,$src,$dst" %}
6857 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6858 ins_pipe(ialu_reg);
6859 %}
6861 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6862 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6863 ins_cost(140);
6864 size(4);
6865 format %{ "MOV$cmp $icc,$src,$dst" %}
6866 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6867 ins_pipe(ialu_imm);
6868 %}
6870 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6871 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6872 ins_cost(150);
6873 size(4);
6874 format %{ "MOV$cmp $fcc,$src,$dst" %}
6875 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6876 ins_pipe(ialu_reg);
6877 %}
6879 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6880 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6881 ins_cost(140);
6882 size(4);
6883 format %{ "MOV$cmp $fcc,$src,$dst" %}
6884 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6885 ins_pipe(ialu_imm);
6886 %}
6888 // Conditional move for RegN. Only cmov(reg,reg).
6889 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6890 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6891 ins_cost(150);
6892 format %{ "MOV$cmp $pcc,$src,$dst" %}
6893 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6894 ins_pipe(ialu_reg);
6895 %}
6897 // This instruction also works with CmpN so we don't need cmovNN_reg.
6898 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6899 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6900 ins_cost(150);
6901 size(4);
6902 format %{ "MOV$cmp $icc,$src,$dst" %}
6903 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6904 ins_pipe(ialu_reg);
6905 %}
6907 // This instruction also works with CmpN so we don't need cmovNN_reg.
6908 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6909 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6910 ins_cost(150);
6911 size(4);
6912 format %{ "MOV$cmp $icc,$src,$dst" %}
6913 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6914 ins_pipe(ialu_reg);
6915 %}
6917 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6918 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6919 ins_cost(150);
6920 size(4);
6921 format %{ "MOV$cmp $fcc,$src,$dst" %}
6922 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6923 ins_pipe(ialu_reg);
6924 %}
6926 // Conditional move
6927 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6928 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6929 ins_cost(150);
6930 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6931 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6932 ins_pipe(ialu_reg);
6933 %}
6935 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6936 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6937 ins_cost(140);
6938 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6939 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6940 ins_pipe(ialu_imm);
6941 %}
6943 // This instruction also works with CmpN so we don't need cmovPN_reg.
6944 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6945 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6946 ins_cost(150);
6948 size(4);
6949 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6950 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6951 ins_pipe(ialu_reg);
6952 %}
6954 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6955 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6956 ins_cost(150);
6958 size(4);
6959 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6960 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6961 ins_pipe(ialu_reg);
6962 %}
6964 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6965 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6966 ins_cost(140);
6968 size(4);
6969 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6970 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6971 ins_pipe(ialu_imm);
6972 %}
6974 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6975 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6976 ins_cost(140);
6978 size(4);
6979 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6980 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6981 ins_pipe(ialu_imm);
6982 %}
6984 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6985 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6986 ins_cost(150);
6987 size(4);
6988 format %{ "MOV$cmp $fcc,$src,$dst" %}
6989 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6990 ins_pipe(ialu_imm);
6991 %}
6993 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6994 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6995 ins_cost(140);
6996 size(4);
6997 format %{ "MOV$cmp $fcc,$src,$dst" %}
6998 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6999 ins_pipe(ialu_imm);
7000 %}
7002 // Conditional move
7003 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
7004 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
7005 ins_cost(150);
7006 opcode(0x101);
7007 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7008 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7009 ins_pipe(int_conditional_float_move);
7010 %}
7012 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7013 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7014 ins_cost(150);
7016 size(4);
7017 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7018 opcode(0x101);
7019 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7020 ins_pipe(int_conditional_float_move);
7021 %}
7023 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7024 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7025 ins_cost(150);
7027 size(4);
7028 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7029 opcode(0x101);
7030 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7031 ins_pipe(int_conditional_float_move);
7032 %}
7034 // Conditional move,
7035 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7036 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7037 ins_cost(150);
7038 size(4);
7039 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7040 opcode(0x1);
7041 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7042 ins_pipe(int_conditional_double_move);
7043 %}
7045 // Conditional move
7046 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7047 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7048 ins_cost(150);
7049 size(4);
7050 opcode(0x102);
7051 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7052 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7053 ins_pipe(int_conditional_double_move);
7054 %}
7056 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7057 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7058 ins_cost(150);
7060 size(4);
7061 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7062 opcode(0x102);
7063 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7064 ins_pipe(int_conditional_double_move);
7065 %}
7067 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7068 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7069 ins_cost(150);
7071 size(4);
7072 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7073 opcode(0x102);
7074 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7075 ins_pipe(int_conditional_double_move);
7076 %}
7078 // Conditional move,
7079 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7080 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7081 ins_cost(150);
7082 size(4);
7083 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7084 opcode(0x2);
7085 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7086 ins_pipe(int_conditional_double_move);
7087 %}
7089 // Conditional move
7090 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7091 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7092 ins_cost(150);
7093 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7094 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7095 ins_pipe(ialu_reg);
7096 %}
7098 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7099 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7100 ins_cost(140);
7101 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7102 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7103 ins_pipe(ialu_imm);
7104 %}
7106 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7107 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7108 ins_cost(150);
7110 size(4);
7111 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7112 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7113 ins_pipe(ialu_reg);
7114 %}
7117 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7118 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7119 ins_cost(150);
7121 size(4);
7122 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7123 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7124 ins_pipe(ialu_reg);
7125 %}
7128 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7129 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7130 ins_cost(150);
7132 size(4);
7133 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7134 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7135 ins_pipe(ialu_reg);
7136 %}
7140 //----------OS and Locking Instructions----------------------------------------
7142 // This name is KNOWN by the ADLC and cannot be changed.
7143 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7144 // for this guy.
7145 instruct tlsLoadP(g2RegP dst) %{
7146 match(Set dst (ThreadLocal));
7148 size(0);
7149 ins_cost(0);
7150 format %{ "# TLS is in G2" %}
7151 ins_encode( /*empty encoding*/ );
7152 ins_pipe(ialu_none);
7153 %}
7155 instruct checkCastPP( iRegP dst ) %{
7156 match(Set dst (CheckCastPP dst));
7158 size(0);
7159 format %{ "# checkcastPP of $dst" %}
7160 ins_encode( /*empty encoding*/ );
7161 ins_pipe(empty);
7162 %}
7165 instruct castPP( iRegP dst ) %{
7166 match(Set dst (CastPP dst));
7167 format %{ "# castPP of $dst" %}
7168 ins_encode( /*empty encoding*/ );
7169 ins_pipe(empty);
7170 %}
7172 instruct castII( iRegI dst ) %{
7173 match(Set dst (CastII dst));
7174 format %{ "# castII of $dst" %}
7175 ins_encode( /*empty encoding*/ );
7176 ins_cost(0);
7177 ins_pipe(empty);
7178 %}
7180 //----------Arithmetic Instructions--------------------------------------------
7181 // Addition Instructions
7182 // Register Addition
7183 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7184 match(Set dst (AddI src1 src2));
7186 size(4);
7187 format %{ "ADD $src1,$src2,$dst" %}
7188 ins_encode %{
7189 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7190 %}
7191 ins_pipe(ialu_reg_reg);
7192 %}
7194 // Immediate Addition
7195 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7196 match(Set dst (AddI src1 src2));
7198 size(4);
7199 format %{ "ADD $src1,$src2,$dst" %}
7200 opcode(Assembler::add_op3, Assembler::arith_op);
7201 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7202 ins_pipe(ialu_reg_imm);
7203 %}
7205 // Pointer Register Addition
7206 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7207 match(Set dst (AddP src1 src2));
7209 size(4);
7210 format %{ "ADD $src1,$src2,$dst" %}
7211 opcode(Assembler::add_op3, Assembler::arith_op);
7212 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7213 ins_pipe(ialu_reg_reg);
7214 %}
7216 // Pointer Immediate Addition
7217 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7218 match(Set dst (AddP src1 src2));
7220 size(4);
7221 format %{ "ADD $src1,$src2,$dst" %}
7222 opcode(Assembler::add_op3, Assembler::arith_op);
7223 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7224 ins_pipe(ialu_reg_imm);
7225 %}
7227 // Long Addition
7228 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7229 match(Set dst (AddL src1 src2));
7231 size(4);
7232 format %{ "ADD $src1,$src2,$dst\t! long" %}
7233 opcode(Assembler::add_op3, Assembler::arith_op);
7234 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7235 ins_pipe(ialu_reg_reg);
7236 %}
7238 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7239 match(Set dst (AddL src1 con));
7241 size(4);
7242 format %{ "ADD $src1,$con,$dst" %}
7243 opcode(Assembler::add_op3, Assembler::arith_op);
7244 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7245 ins_pipe(ialu_reg_imm);
7246 %}
7248 //----------Conditional_store--------------------------------------------------
7249 // Conditional-store of the updated heap-top.
7250 // Used during allocation of the shared heap.
7251 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7253 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7254 instruct loadPLocked(iRegP dst, memory mem) %{
7255 match(Set dst (LoadPLocked mem));
7256 ins_cost(MEMORY_REF_COST);
7258 #ifndef _LP64
7259 size(4);
7260 format %{ "LDUW $mem,$dst\t! ptr" %}
7261 opcode(Assembler::lduw_op3, 0, REGP_OP);
7262 #else
7263 format %{ "LDX $mem,$dst\t! ptr" %}
7264 opcode(Assembler::ldx_op3, 0, REGP_OP);
7265 #endif
7266 ins_encode( form3_mem_reg( mem, dst ) );
7267 ins_pipe(iload_mem);
7268 %}
7270 // LoadL-locked. Same as a regular long load when used with a compare-swap
7271 instruct loadLLocked(iRegL dst, memory mem) %{
7272 match(Set dst (LoadLLocked mem));
7273 ins_cost(MEMORY_REF_COST);
7274 size(4);
7275 format %{ "LDX $mem,$dst\t! long" %}
7276 opcode(Assembler::ldx_op3);
7277 ins_encode(simple_form3_mem_reg( mem, dst ) );
7278 ins_pipe(iload_mem);
7279 %}
7281 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7282 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7283 effect( KILL newval );
7284 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7285 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7286 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7287 ins_pipe( long_memory_op );
7288 %}
7290 // Conditional-store of an int value.
7291 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7292 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7293 effect( KILL newval );
7294 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7295 "CMP $oldval,$newval\t\t! See if we made progress" %}
7296 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7297 ins_pipe( long_memory_op );
7298 %}
7300 // Conditional-store of a long value.
7301 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7302 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7303 effect( KILL newval );
7304 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7305 "CMP $oldval,$newval\t\t! See if we made progress" %}
7306 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7307 ins_pipe( long_memory_op );
7308 %}
7310 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7312 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7313 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7314 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7315 format %{
7316 "MOV $newval,O7\n\t"
7317 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7318 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7319 "MOV 1,$res\n\t"
7320 "MOVne xcc,R_G0,$res"
7321 %}
7322 ins_encode( enc_casx(mem_ptr, oldval, newval),
7323 enc_lflags_ne_to_boolean(res) );
7324 ins_pipe( long_memory_op );
7325 %}
7328 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7329 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7330 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7331 format %{
7332 "MOV $newval,O7\n\t"
7333 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7334 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7335 "MOV 1,$res\n\t"
7336 "MOVne icc,R_G0,$res"
7337 %}
7338 ins_encode( enc_casi(mem_ptr, oldval, newval),
7339 enc_iflags_ne_to_boolean(res) );
7340 ins_pipe( long_memory_op );
7341 %}
7343 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7344 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7345 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7346 format %{
7347 "MOV $newval,O7\n\t"
7348 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7349 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7350 "MOV 1,$res\n\t"
7351 "MOVne xcc,R_G0,$res"
7352 %}
7353 #ifdef _LP64
7354 ins_encode( enc_casx(mem_ptr, oldval, newval),
7355 enc_lflags_ne_to_boolean(res) );
7356 #else
7357 ins_encode( enc_casi(mem_ptr, oldval, newval),
7358 enc_iflags_ne_to_boolean(res) );
7359 #endif
7360 ins_pipe( long_memory_op );
7361 %}
7363 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7364 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7365 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7366 format %{
7367 "MOV $newval,O7\n\t"
7368 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7369 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7370 "MOV 1,$res\n\t"
7371 "MOVne icc,R_G0,$res"
7372 %}
7373 ins_encode( enc_casi(mem_ptr, oldval, newval),
7374 enc_iflags_ne_to_boolean(res) );
7375 ins_pipe( long_memory_op );
7376 %}
7378 //---------------------
7379 // Subtraction Instructions
7380 // Register Subtraction
7381 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7382 match(Set dst (SubI src1 src2));
7384 size(4);
7385 format %{ "SUB $src1,$src2,$dst" %}
7386 opcode(Assembler::sub_op3, Assembler::arith_op);
7387 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7388 ins_pipe(ialu_reg_reg);
7389 %}
7391 // Immediate Subtraction
7392 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7393 match(Set dst (SubI src1 src2));
7395 size(4);
7396 format %{ "SUB $src1,$src2,$dst" %}
7397 opcode(Assembler::sub_op3, Assembler::arith_op);
7398 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7399 ins_pipe(ialu_reg_imm);
7400 %}
7402 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7403 match(Set dst (SubI zero src2));
7405 size(4);
7406 format %{ "NEG $src2,$dst" %}
7407 opcode(Assembler::sub_op3, Assembler::arith_op);
7408 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7409 ins_pipe(ialu_zero_reg);
7410 %}
7412 // Long subtraction
7413 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7414 match(Set dst (SubL src1 src2));
7416 size(4);
7417 format %{ "SUB $src1,$src2,$dst\t! long" %}
7418 opcode(Assembler::sub_op3, Assembler::arith_op);
7419 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7420 ins_pipe(ialu_reg_reg);
7421 %}
7423 // Immediate Subtraction
7424 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7425 match(Set dst (SubL src1 con));
7427 size(4);
7428 format %{ "SUB $src1,$con,$dst\t! long" %}
7429 opcode(Assembler::sub_op3, Assembler::arith_op);
7430 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7431 ins_pipe(ialu_reg_imm);
7432 %}
7434 // Long negation
7435 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7436 match(Set dst (SubL zero src2));
7438 size(4);
7439 format %{ "NEG $src2,$dst\t! long" %}
7440 opcode(Assembler::sub_op3, Assembler::arith_op);
7441 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7442 ins_pipe(ialu_zero_reg);
7443 %}
7445 // Multiplication Instructions
7446 // Integer Multiplication
7447 // Register Multiplication
7448 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7449 match(Set dst (MulI src1 src2));
7451 size(4);
7452 format %{ "MULX $src1,$src2,$dst" %}
7453 opcode(Assembler::mulx_op3, Assembler::arith_op);
7454 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7455 ins_pipe(imul_reg_reg);
7456 %}
7458 // Immediate Multiplication
7459 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7460 match(Set dst (MulI src1 src2));
7462 size(4);
7463 format %{ "MULX $src1,$src2,$dst" %}
7464 opcode(Assembler::mulx_op3, Assembler::arith_op);
7465 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7466 ins_pipe(imul_reg_imm);
7467 %}
7469 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7470 match(Set dst (MulL src1 src2));
7471 ins_cost(DEFAULT_COST * 5);
7472 size(4);
7473 format %{ "MULX $src1,$src2,$dst\t! long" %}
7474 opcode(Assembler::mulx_op3, Assembler::arith_op);
7475 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7476 ins_pipe(mulL_reg_reg);
7477 %}
7479 // Immediate Multiplication
7480 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7481 match(Set dst (MulL src1 src2));
7482 ins_cost(DEFAULT_COST * 5);
7483 size(4);
7484 format %{ "MULX $src1,$src2,$dst" %}
7485 opcode(Assembler::mulx_op3, Assembler::arith_op);
7486 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7487 ins_pipe(mulL_reg_imm);
7488 %}
7490 // Integer Division
7491 // Register Division
7492 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7493 match(Set dst (DivI src1 src2));
7494 ins_cost((2+71)*DEFAULT_COST);
7496 format %{ "SRA $src2,0,$src2\n\t"
7497 "SRA $src1,0,$src1\n\t"
7498 "SDIVX $src1,$src2,$dst" %}
7499 ins_encode( idiv_reg( src1, src2, dst ) );
7500 ins_pipe(sdiv_reg_reg);
7501 %}
7503 // Immediate Division
7504 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7505 match(Set dst (DivI src1 src2));
7506 ins_cost((2+71)*DEFAULT_COST);
7508 format %{ "SRA $src1,0,$src1\n\t"
7509 "SDIVX $src1,$src2,$dst" %}
7510 ins_encode( idiv_imm( src1, src2, dst ) );
7511 ins_pipe(sdiv_reg_imm);
7512 %}
7514 //----------Div-By-10-Expansion------------------------------------------------
7515 // Extract hi bits of a 32x32->64 bit multiply.
7516 // Expand rule only, not matched
7517 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7518 effect( DEF dst, USE src1, USE src2 );
7519 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7520 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7521 ins_encode( enc_mul_hi(dst,src1,src2));
7522 ins_pipe(sdiv_reg_reg);
7523 %}
7525 // Magic constant, reciprocal of 10
7526 instruct loadConI_x66666667(iRegIsafe dst) %{
7527 effect( DEF dst );
7529 size(8);
7530 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7531 ins_encode( Set32(0x66666667, dst) );
7532 ins_pipe(ialu_hi_lo_reg);
7533 %}
7535 // Register Shift Right Arithmetic Long by 32-63
7536 instruct sra_31( iRegI dst, iRegI src ) %{
7537 effect( DEF dst, USE src );
7538 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7539 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7540 ins_pipe(ialu_reg_reg);
7541 %}
7543 // Arithmetic Shift Right by 8-bit immediate
7544 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7545 effect( DEF dst, USE src );
7546 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7547 opcode(Assembler::sra_op3, Assembler::arith_op);
7548 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7549 ins_pipe(ialu_reg_imm);
7550 %}
7552 // Integer DIV with 10
7553 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7554 match(Set dst (DivI src div));
7555 ins_cost((6+6)*DEFAULT_COST);
7556 expand %{
7557 iRegIsafe tmp1; // Killed temps;
7558 iRegIsafe tmp2; // Killed temps;
7559 iRegI tmp3; // Killed temps;
7560 iRegI tmp4; // Killed temps;
7561 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7562 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7563 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7564 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7565 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7566 %}
7567 %}
7569 // Register Long Division
7570 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7571 match(Set dst (DivL src1 src2));
7572 ins_cost(DEFAULT_COST*71);
7573 size(4);
7574 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7575 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7576 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7577 ins_pipe(divL_reg_reg);
7578 %}
7580 // Register Long Division
7581 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7582 match(Set dst (DivL src1 src2));
7583 ins_cost(DEFAULT_COST*71);
7584 size(4);
7585 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7586 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7587 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7588 ins_pipe(divL_reg_imm);
7589 %}
7591 // Integer Remainder
7592 // Register Remainder
7593 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7594 match(Set dst (ModI src1 src2));
7595 effect( KILL ccr, KILL temp);
7597 format %{ "SREM $src1,$src2,$dst" %}
7598 ins_encode( irem_reg(src1, src2, dst, temp) );
7599 ins_pipe(sdiv_reg_reg);
7600 %}
7602 // Immediate Remainder
7603 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7604 match(Set dst (ModI src1 src2));
7605 effect( KILL ccr, KILL temp);
7607 format %{ "SREM $src1,$src2,$dst" %}
7608 ins_encode( irem_imm(src1, src2, dst, temp) );
7609 ins_pipe(sdiv_reg_imm);
7610 %}
7612 // Register Long Remainder
7613 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7614 effect(DEF dst, USE src1, USE src2);
7615 size(4);
7616 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7617 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7618 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7619 ins_pipe(divL_reg_reg);
7620 %}
7622 // Register Long Division
7623 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7624 effect(DEF dst, USE src1, USE src2);
7625 size(4);
7626 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7627 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7628 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7629 ins_pipe(divL_reg_imm);
7630 %}
7632 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7633 effect(DEF dst, USE src1, USE src2);
7634 size(4);
7635 format %{ "MULX $src1,$src2,$dst\t! long" %}
7636 opcode(Assembler::mulx_op3, Assembler::arith_op);
7637 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7638 ins_pipe(mulL_reg_reg);
7639 %}
7641 // Immediate Multiplication
7642 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7643 effect(DEF dst, USE src1, USE src2);
7644 size(4);
7645 format %{ "MULX $src1,$src2,$dst" %}
7646 opcode(Assembler::mulx_op3, Assembler::arith_op);
7647 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7648 ins_pipe(mulL_reg_imm);
7649 %}
7651 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7652 effect(DEF dst, USE src1, USE src2);
7653 size(4);
7654 format %{ "SUB $src1,$src2,$dst\t! long" %}
7655 opcode(Assembler::sub_op3, Assembler::arith_op);
7656 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7657 ins_pipe(ialu_reg_reg);
7658 %}
7660 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7661 effect(DEF dst, USE src1, USE src2);
7662 size(4);
7663 format %{ "SUB $src1,$src2,$dst\t! long" %}
7664 opcode(Assembler::sub_op3, Assembler::arith_op);
7665 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7666 ins_pipe(ialu_reg_reg);
7667 %}
7669 // Register Long Remainder
7670 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7671 match(Set dst (ModL src1 src2));
7672 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7673 expand %{
7674 iRegL tmp1;
7675 iRegL tmp2;
7676 divL_reg_reg_1(tmp1, src1, src2);
7677 mulL_reg_reg_1(tmp2, tmp1, src2);
7678 subL_reg_reg_1(dst, src1, tmp2);
7679 %}
7680 %}
7682 // Register Long Remainder
7683 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7684 match(Set dst (ModL src1 src2));
7685 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7686 expand %{
7687 iRegL tmp1;
7688 iRegL tmp2;
7689 divL_reg_imm13_1(tmp1, src1, src2);
7690 mulL_reg_imm13_1(tmp2, tmp1, src2);
7691 subL_reg_reg_2 (dst, src1, tmp2);
7692 %}
7693 %}
7695 // Integer Shift Instructions
7696 // Register Shift Left
7697 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7698 match(Set dst (LShiftI src1 src2));
7700 size(4);
7701 format %{ "SLL $src1,$src2,$dst" %}
7702 opcode(Assembler::sll_op3, Assembler::arith_op);
7703 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7704 ins_pipe(ialu_reg_reg);
7705 %}
7707 // Register Shift Left Immediate
7708 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7709 match(Set dst (LShiftI src1 src2));
7711 size(4);
7712 format %{ "SLL $src1,$src2,$dst" %}
7713 opcode(Assembler::sll_op3, Assembler::arith_op);
7714 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7715 ins_pipe(ialu_reg_imm);
7716 %}
7718 // Register Shift Left
7719 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7720 match(Set dst (LShiftL src1 src2));
7722 size(4);
7723 format %{ "SLLX $src1,$src2,$dst" %}
7724 opcode(Assembler::sllx_op3, Assembler::arith_op);
7725 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7726 ins_pipe(ialu_reg_reg);
7727 %}
7729 // Register Shift Left Immediate
7730 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7731 match(Set dst (LShiftL src1 src2));
7733 size(4);
7734 format %{ "SLLX $src1,$src2,$dst" %}
7735 opcode(Assembler::sllx_op3, Assembler::arith_op);
7736 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7737 ins_pipe(ialu_reg_imm);
7738 %}
7740 // Register Arithmetic Shift Right
7741 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7742 match(Set dst (RShiftI src1 src2));
7743 size(4);
7744 format %{ "SRA $src1,$src2,$dst" %}
7745 opcode(Assembler::sra_op3, Assembler::arith_op);
7746 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7747 ins_pipe(ialu_reg_reg);
7748 %}
7750 // Register Arithmetic Shift Right Immediate
7751 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7752 match(Set dst (RShiftI src1 src2));
7754 size(4);
7755 format %{ "SRA $src1,$src2,$dst" %}
7756 opcode(Assembler::sra_op3, Assembler::arith_op);
7757 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7758 ins_pipe(ialu_reg_imm);
7759 %}
7761 // Register Shift Right Arithmatic Long
7762 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7763 match(Set dst (RShiftL src1 src2));
7765 size(4);
7766 format %{ "SRAX $src1,$src2,$dst" %}
7767 opcode(Assembler::srax_op3, Assembler::arith_op);
7768 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7769 ins_pipe(ialu_reg_reg);
7770 %}
7772 // Register Shift Left Immediate
7773 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7774 match(Set dst (RShiftL src1 src2));
7776 size(4);
7777 format %{ "SRAX $src1,$src2,$dst" %}
7778 opcode(Assembler::srax_op3, Assembler::arith_op);
7779 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7780 ins_pipe(ialu_reg_imm);
7781 %}
7783 // Register Shift Right
7784 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7785 match(Set dst (URShiftI src1 src2));
7787 size(4);
7788 format %{ "SRL $src1,$src2,$dst" %}
7789 opcode(Assembler::srl_op3, Assembler::arith_op);
7790 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7791 ins_pipe(ialu_reg_reg);
7792 %}
7794 // Register Shift Right Immediate
7795 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7796 match(Set dst (URShiftI src1 src2));
7798 size(4);
7799 format %{ "SRL $src1,$src2,$dst" %}
7800 opcode(Assembler::srl_op3, Assembler::arith_op);
7801 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7802 ins_pipe(ialu_reg_imm);
7803 %}
7805 // Register Shift Right
7806 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7807 match(Set dst (URShiftL src1 src2));
7809 size(4);
7810 format %{ "SRLX $src1,$src2,$dst" %}
7811 opcode(Assembler::srlx_op3, Assembler::arith_op);
7812 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7813 ins_pipe(ialu_reg_reg);
7814 %}
7816 // Register Shift Right Immediate
7817 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7818 match(Set dst (URShiftL src1 src2));
7820 size(4);
7821 format %{ "SRLX $src1,$src2,$dst" %}
7822 opcode(Assembler::srlx_op3, Assembler::arith_op);
7823 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7824 ins_pipe(ialu_reg_imm);
7825 %}
7827 // Register Shift Right Immediate with a CastP2X
7828 #ifdef _LP64
7829 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7830 match(Set dst (URShiftL (CastP2X src1) src2));
7831 size(4);
7832 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7833 opcode(Assembler::srlx_op3, Assembler::arith_op);
7834 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7835 ins_pipe(ialu_reg_imm);
7836 %}
7837 #else
7838 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7839 match(Set dst (URShiftI (CastP2X src1) src2));
7840 size(4);
7841 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7842 opcode(Assembler::srl_op3, Assembler::arith_op);
7843 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7844 ins_pipe(ialu_reg_imm);
7845 %}
7846 #endif
7849 //----------Floating Point Arithmetic Instructions-----------------------------
7851 // Add float single precision
7852 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7853 match(Set dst (AddF src1 src2));
7855 size(4);
7856 format %{ "FADDS $src1,$src2,$dst" %}
7857 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7858 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7859 ins_pipe(faddF_reg_reg);
7860 %}
7862 // Add float double precision
7863 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7864 match(Set dst (AddD src1 src2));
7866 size(4);
7867 format %{ "FADDD $src1,$src2,$dst" %}
7868 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7869 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7870 ins_pipe(faddD_reg_reg);
7871 %}
7873 // Sub float single precision
7874 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7875 match(Set dst (SubF src1 src2));
7877 size(4);
7878 format %{ "FSUBS $src1,$src2,$dst" %}
7879 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7880 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7881 ins_pipe(faddF_reg_reg);
7882 %}
7884 // Sub float double precision
7885 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7886 match(Set dst (SubD src1 src2));
7888 size(4);
7889 format %{ "FSUBD $src1,$src2,$dst" %}
7890 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7891 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7892 ins_pipe(faddD_reg_reg);
7893 %}
7895 // Mul float single precision
7896 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7897 match(Set dst (MulF src1 src2));
7899 size(4);
7900 format %{ "FMULS $src1,$src2,$dst" %}
7901 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7902 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7903 ins_pipe(fmulF_reg_reg);
7904 %}
7906 // Mul float double precision
7907 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7908 match(Set dst (MulD src1 src2));
7910 size(4);
7911 format %{ "FMULD $src1,$src2,$dst" %}
7912 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7913 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7914 ins_pipe(fmulD_reg_reg);
7915 %}
7917 // Div float single precision
7918 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7919 match(Set dst (DivF src1 src2));
7921 size(4);
7922 format %{ "FDIVS $src1,$src2,$dst" %}
7923 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7924 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7925 ins_pipe(fdivF_reg_reg);
7926 %}
7928 // Div float double precision
7929 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7930 match(Set dst (DivD src1 src2));
7932 size(4);
7933 format %{ "FDIVD $src1,$src2,$dst" %}
7934 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7935 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7936 ins_pipe(fdivD_reg_reg);
7937 %}
7939 // Absolute float double precision
7940 instruct absD_reg(regD dst, regD src) %{
7941 match(Set dst (AbsD src));
7943 format %{ "FABSd $src,$dst" %}
7944 ins_encode(fabsd(dst, src));
7945 ins_pipe(faddD_reg);
7946 %}
7948 // Absolute float single precision
7949 instruct absF_reg(regF dst, regF src) %{
7950 match(Set dst (AbsF src));
7952 format %{ "FABSs $src,$dst" %}
7953 ins_encode(fabss(dst, src));
7954 ins_pipe(faddF_reg);
7955 %}
7957 instruct negF_reg(regF dst, regF src) %{
7958 match(Set dst (NegF src));
7960 size(4);
7961 format %{ "FNEGs $src,$dst" %}
7962 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7963 ins_encode(form3_opf_rs2F_rdF(src, dst));
7964 ins_pipe(faddF_reg);
7965 %}
7967 instruct negD_reg(regD dst, regD src) %{
7968 match(Set dst (NegD src));
7970 format %{ "FNEGd $src,$dst" %}
7971 ins_encode(fnegd(dst, src));
7972 ins_pipe(faddD_reg);
7973 %}
7975 // Sqrt float double precision
7976 instruct sqrtF_reg_reg(regF dst, regF src) %{
7977 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7979 size(4);
7980 format %{ "FSQRTS $src,$dst" %}
7981 ins_encode(fsqrts(dst, src));
7982 ins_pipe(fdivF_reg_reg);
7983 %}
7985 // Sqrt float double precision
7986 instruct sqrtD_reg_reg(regD dst, regD src) %{
7987 match(Set dst (SqrtD src));
7989 size(4);
7990 format %{ "FSQRTD $src,$dst" %}
7991 ins_encode(fsqrtd(dst, src));
7992 ins_pipe(fdivD_reg_reg);
7993 %}
7995 //----------Logical Instructions-----------------------------------------------
7996 // And Instructions
7997 // Register And
7998 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7999 match(Set dst (AndI src1 src2));
8001 size(4);
8002 format %{ "AND $src1,$src2,$dst" %}
8003 opcode(Assembler::and_op3, Assembler::arith_op);
8004 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8005 ins_pipe(ialu_reg_reg);
8006 %}
8008 // Immediate And
8009 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8010 match(Set dst (AndI src1 src2));
8012 size(4);
8013 format %{ "AND $src1,$src2,$dst" %}
8014 opcode(Assembler::and_op3, Assembler::arith_op);
8015 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8016 ins_pipe(ialu_reg_imm);
8017 %}
8019 // Register And Long
8020 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8021 match(Set dst (AndL src1 src2));
8023 ins_cost(DEFAULT_COST);
8024 size(4);
8025 format %{ "AND $src1,$src2,$dst\t! long" %}
8026 opcode(Assembler::and_op3, Assembler::arith_op);
8027 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8028 ins_pipe(ialu_reg_reg);
8029 %}
8031 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8032 match(Set dst (AndL src1 con));
8034 ins_cost(DEFAULT_COST);
8035 size(4);
8036 format %{ "AND $src1,$con,$dst\t! long" %}
8037 opcode(Assembler::and_op3, Assembler::arith_op);
8038 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8039 ins_pipe(ialu_reg_imm);
8040 %}
8042 // Or Instructions
8043 // Register Or
8044 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8045 match(Set dst (OrI src1 src2));
8047 size(4);
8048 format %{ "OR $src1,$src2,$dst" %}
8049 opcode(Assembler::or_op3, Assembler::arith_op);
8050 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8051 ins_pipe(ialu_reg_reg);
8052 %}
8054 // Immediate Or
8055 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8056 match(Set dst (OrI src1 src2));
8058 size(4);
8059 format %{ "OR $src1,$src2,$dst" %}
8060 opcode(Assembler::or_op3, Assembler::arith_op);
8061 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8062 ins_pipe(ialu_reg_imm);
8063 %}
8065 // Register Or Long
8066 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8067 match(Set dst (OrL src1 src2));
8069 ins_cost(DEFAULT_COST);
8070 size(4);
8071 format %{ "OR $src1,$src2,$dst\t! long" %}
8072 opcode(Assembler::or_op3, Assembler::arith_op);
8073 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8074 ins_pipe(ialu_reg_reg);
8075 %}
8077 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8078 match(Set dst (OrL src1 con));
8079 ins_cost(DEFAULT_COST*2);
8081 ins_cost(DEFAULT_COST);
8082 size(4);
8083 format %{ "OR $src1,$con,$dst\t! long" %}
8084 opcode(Assembler::or_op3, Assembler::arith_op);
8085 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8086 ins_pipe(ialu_reg_imm);
8087 %}
8089 #ifndef _LP64
8091 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8092 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8093 match(Set dst (OrI src1 (CastP2X src2)));
8095 size(4);
8096 format %{ "OR $src1,$src2,$dst" %}
8097 opcode(Assembler::or_op3, Assembler::arith_op);
8098 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8099 ins_pipe(ialu_reg_reg);
8100 %}
8102 #else
8104 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8105 match(Set dst (OrL src1 (CastP2X src2)));
8107 ins_cost(DEFAULT_COST);
8108 size(4);
8109 format %{ "OR $src1,$src2,$dst\t! long" %}
8110 opcode(Assembler::or_op3, Assembler::arith_op);
8111 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8112 ins_pipe(ialu_reg_reg);
8113 %}
8115 #endif
8117 // Xor Instructions
8118 // Register Xor
8119 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8120 match(Set dst (XorI src1 src2));
8122 size(4);
8123 format %{ "XOR $src1,$src2,$dst" %}
8124 opcode(Assembler::xor_op3, Assembler::arith_op);
8125 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8126 ins_pipe(ialu_reg_reg);
8127 %}
8129 // Immediate Xor
8130 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8131 match(Set dst (XorI src1 src2));
8133 size(4);
8134 format %{ "XOR $src1,$src2,$dst" %}
8135 opcode(Assembler::xor_op3, Assembler::arith_op);
8136 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8137 ins_pipe(ialu_reg_imm);
8138 %}
8140 // Register Xor Long
8141 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8142 match(Set dst (XorL src1 src2));
8144 ins_cost(DEFAULT_COST);
8145 size(4);
8146 format %{ "XOR $src1,$src2,$dst\t! long" %}
8147 opcode(Assembler::xor_op3, Assembler::arith_op);
8148 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8149 ins_pipe(ialu_reg_reg);
8150 %}
8152 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8153 match(Set dst (XorL src1 con));
8155 ins_cost(DEFAULT_COST);
8156 size(4);
8157 format %{ "XOR $src1,$con,$dst\t! long" %}
8158 opcode(Assembler::xor_op3, Assembler::arith_op);
8159 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8160 ins_pipe(ialu_reg_imm);
8161 %}
8163 //----------Convert to Boolean-------------------------------------------------
8164 // Nice hack for 32-bit tests but doesn't work for
8165 // 64-bit pointers.
8166 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8167 match(Set dst (Conv2B src));
8168 effect( KILL ccr );
8169 ins_cost(DEFAULT_COST*2);
8170 format %{ "CMP R_G0,$src\n\t"
8171 "ADDX R_G0,0,$dst" %}
8172 ins_encode( enc_to_bool( src, dst ) );
8173 ins_pipe(ialu_reg_ialu);
8174 %}
8176 #ifndef _LP64
8177 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8178 match(Set dst (Conv2B src));
8179 effect( KILL ccr );
8180 ins_cost(DEFAULT_COST*2);
8181 format %{ "CMP R_G0,$src\n\t"
8182 "ADDX R_G0,0,$dst" %}
8183 ins_encode( enc_to_bool( src, dst ) );
8184 ins_pipe(ialu_reg_ialu);
8185 %}
8186 #else
8187 instruct convP2B( iRegI dst, iRegP src ) %{
8188 match(Set dst (Conv2B src));
8189 ins_cost(DEFAULT_COST*2);
8190 format %{ "MOV $src,$dst\n\t"
8191 "MOVRNZ $src,1,$dst" %}
8192 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8193 ins_pipe(ialu_clr_and_mover);
8194 %}
8195 #endif
8197 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8198 match(Set dst (CmpLTMask src zero));
8199 effect(KILL ccr);
8200 size(4);
8201 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8202 ins_encode %{
8203 __ sra($src$$Register, 31, $dst$$Register);
8204 %}
8205 ins_pipe(ialu_reg_imm);
8206 %}
8208 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8209 match(Set dst (CmpLTMask p q));
8210 effect( KILL ccr );
8211 ins_cost(DEFAULT_COST*4);
8212 format %{ "CMP $p,$q\n\t"
8213 "MOV #0,$dst\n\t"
8214 "BLT,a .+8\n\t"
8215 "MOV #-1,$dst" %}
8216 ins_encode( enc_ltmask(p,q,dst) );
8217 ins_pipe(ialu_reg_reg_ialu);
8218 %}
8220 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8221 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8222 effect(KILL ccr, TEMP tmp);
8223 ins_cost(DEFAULT_COST*3);
8225 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8226 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8227 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8228 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8229 ins_pipe( cadd_cmpltmask );
8230 %}
8233 //-----------------------------------------------------------------
8234 // Direct raw moves between float and general registers using VIS3.
8236 // ins_pipe(faddF_reg);
8237 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8238 predicate(UseVIS >= 3);
8239 match(Set dst (MoveF2I src));
8241 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8242 ins_encode %{
8243 __ movstouw($src$$FloatRegister, $dst$$Register);
8244 %}
8245 ins_pipe(ialu_reg_reg);
8246 %}
8248 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8249 predicate(UseVIS >= 3);
8250 match(Set dst (MoveI2F src));
8252 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8253 ins_encode %{
8254 __ movwtos($src$$Register, $dst$$FloatRegister);
8255 %}
8256 ins_pipe(ialu_reg_reg);
8257 %}
8259 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8260 predicate(UseVIS >= 3);
8261 match(Set dst (MoveD2L src));
8263 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8264 ins_encode %{
8265 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8266 %}
8267 ins_pipe(ialu_reg_reg);
8268 %}
8270 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8271 predicate(UseVIS >= 3);
8272 match(Set dst (MoveL2D src));
8274 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8275 ins_encode %{
8276 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8277 %}
8278 ins_pipe(ialu_reg_reg);
8279 %}
8282 // Raw moves between float and general registers using stack.
8284 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8285 match(Set dst (MoveF2I src));
8286 effect(DEF dst, USE src);
8287 ins_cost(MEMORY_REF_COST);
8289 size(4);
8290 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8291 opcode(Assembler::lduw_op3);
8292 ins_encode(simple_form3_mem_reg( src, dst ) );
8293 ins_pipe(iload_mem);
8294 %}
8296 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8297 match(Set dst (MoveI2F src));
8298 effect(DEF dst, USE src);
8299 ins_cost(MEMORY_REF_COST);
8301 size(4);
8302 format %{ "LDF $src,$dst\t! MoveI2F" %}
8303 opcode(Assembler::ldf_op3);
8304 ins_encode(simple_form3_mem_reg(src, dst));
8305 ins_pipe(floadF_stk);
8306 %}
8308 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8309 match(Set dst (MoveD2L src));
8310 effect(DEF dst, USE src);
8311 ins_cost(MEMORY_REF_COST);
8313 size(4);
8314 format %{ "LDX $src,$dst\t! MoveD2L" %}
8315 opcode(Assembler::ldx_op3);
8316 ins_encode(simple_form3_mem_reg( src, dst ) );
8317 ins_pipe(iload_mem);
8318 %}
8320 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8321 match(Set dst (MoveL2D src));
8322 effect(DEF dst, USE src);
8323 ins_cost(MEMORY_REF_COST);
8325 size(4);
8326 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8327 opcode(Assembler::lddf_op3);
8328 ins_encode(simple_form3_mem_reg(src, dst));
8329 ins_pipe(floadD_stk);
8330 %}
8332 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8333 match(Set dst (MoveF2I src));
8334 effect(DEF dst, USE src);
8335 ins_cost(MEMORY_REF_COST);
8337 size(4);
8338 format %{ "STF $src,$dst\t! MoveF2I" %}
8339 opcode(Assembler::stf_op3);
8340 ins_encode(simple_form3_mem_reg(dst, src));
8341 ins_pipe(fstoreF_stk_reg);
8342 %}
8344 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8345 match(Set dst (MoveI2F src));
8346 effect(DEF dst, USE src);
8347 ins_cost(MEMORY_REF_COST);
8349 size(4);
8350 format %{ "STW $src,$dst\t! MoveI2F" %}
8351 opcode(Assembler::stw_op3);
8352 ins_encode(simple_form3_mem_reg( dst, src ) );
8353 ins_pipe(istore_mem_reg);
8354 %}
8356 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8357 match(Set dst (MoveD2L src));
8358 effect(DEF dst, USE src);
8359 ins_cost(MEMORY_REF_COST);
8361 size(4);
8362 format %{ "STDF $src,$dst\t! MoveD2L" %}
8363 opcode(Assembler::stdf_op3);
8364 ins_encode(simple_form3_mem_reg(dst, src));
8365 ins_pipe(fstoreD_stk_reg);
8366 %}
8368 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8369 match(Set dst (MoveL2D src));
8370 effect(DEF dst, USE src);
8371 ins_cost(MEMORY_REF_COST);
8373 size(4);
8374 format %{ "STX $src,$dst\t! MoveL2D" %}
8375 opcode(Assembler::stx_op3);
8376 ins_encode(simple_form3_mem_reg( dst, src ) );
8377 ins_pipe(istore_mem_reg);
8378 %}
8381 //----------Arithmetic Conversion Instructions---------------------------------
8382 // The conversions operations are all Alpha sorted. Please keep it that way!
8384 instruct convD2F_reg(regF dst, regD src) %{
8385 match(Set dst (ConvD2F src));
8386 size(4);
8387 format %{ "FDTOS $src,$dst" %}
8388 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8389 ins_encode(form3_opf_rs2D_rdF(src, dst));
8390 ins_pipe(fcvtD2F);
8391 %}
8394 // Convert a double to an int in a float register.
8395 // If the double is a NAN, stuff a zero in instead.
8396 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8397 effect(DEF dst, USE src, KILL fcc0);
8398 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8399 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8400 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8401 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8402 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8403 "skip:" %}
8404 ins_encode(form_d2i_helper(src,dst));
8405 ins_pipe(fcvtD2I);
8406 %}
8408 instruct convD2I_stk(stackSlotI dst, regD src) %{
8409 match(Set dst (ConvD2I src));
8410 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8411 expand %{
8412 regF tmp;
8413 convD2I_helper(tmp, src);
8414 regF_to_stkI(dst, tmp);
8415 %}
8416 %}
8418 instruct convD2I_reg(iRegI dst, regD src) %{
8419 predicate(UseVIS >= 3);
8420 match(Set dst (ConvD2I src));
8421 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8422 expand %{
8423 regF tmp;
8424 convD2I_helper(tmp, src);
8425 MoveF2I_reg_reg(dst, tmp);
8426 %}
8427 %}
8430 // Convert a double to a long in a double register.
8431 // If the double is a NAN, stuff a zero in instead.
8432 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8433 effect(DEF dst, USE src, KILL fcc0);
8434 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8435 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8436 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8437 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8438 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8439 "skip:" %}
8440 ins_encode(form_d2l_helper(src,dst));
8441 ins_pipe(fcvtD2L);
8442 %}
8444 instruct convD2L_stk(stackSlotL dst, regD src) %{
8445 match(Set dst (ConvD2L src));
8446 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8447 expand %{
8448 regD tmp;
8449 convD2L_helper(tmp, src);
8450 regD_to_stkL(dst, tmp);
8451 %}
8452 %}
8454 instruct convD2L_reg(iRegL dst, regD src) %{
8455 predicate(UseVIS >= 3);
8456 match(Set dst (ConvD2L src));
8457 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8458 expand %{
8459 regD tmp;
8460 convD2L_helper(tmp, src);
8461 MoveD2L_reg_reg(dst, tmp);
8462 %}
8463 %}
8466 instruct convF2D_reg(regD dst, regF src) %{
8467 match(Set dst (ConvF2D src));
8468 format %{ "FSTOD $src,$dst" %}
8469 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8470 ins_encode(form3_opf_rs2F_rdD(src, dst));
8471 ins_pipe(fcvtF2D);
8472 %}
8475 // Convert a float to an int in a float register.
8476 // If the float is a NAN, stuff a zero in instead.
8477 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8478 effect(DEF dst, USE src, KILL fcc0);
8479 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8480 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8481 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8482 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8483 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8484 "skip:" %}
8485 ins_encode(form_f2i_helper(src,dst));
8486 ins_pipe(fcvtF2I);
8487 %}
8489 instruct convF2I_stk(stackSlotI dst, regF src) %{
8490 match(Set dst (ConvF2I src));
8491 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8492 expand %{
8493 regF tmp;
8494 convF2I_helper(tmp, src);
8495 regF_to_stkI(dst, tmp);
8496 %}
8497 %}
8499 instruct convF2I_reg(iRegI dst, regF src) %{
8500 predicate(UseVIS >= 3);
8501 match(Set dst (ConvF2I src));
8502 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8503 expand %{
8504 regF tmp;
8505 convF2I_helper(tmp, src);
8506 MoveF2I_reg_reg(dst, tmp);
8507 %}
8508 %}
8511 // Convert a float to a long in a float register.
8512 // If the float is a NAN, stuff a zero in instead.
8513 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8514 effect(DEF dst, USE src, KILL fcc0);
8515 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8516 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8517 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8518 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8519 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8520 "skip:" %}
8521 ins_encode(form_f2l_helper(src,dst));
8522 ins_pipe(fcvtF2L);
8523 %}
8525 instruct convF2L_stk(stackSlotL dst, regF src) %{
8526 match(Set dst (ConvF2L src));
8527 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8528 expand %{
8529 regD tmp;
8530 convF2L_helper(tmp, src);
8531 regD_to_stkL(dst, tmp);
8532 %}
8533 %}
8535 instruct convF2L_reg(iRegL dst, regF src) %{
8536 predicate(UseVIS >= 3);
8537 match(Set dst (ConvF2L src));
8538 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8539 expand %{
8540 regD tmp;
8541 convF2L_helper(tmp, src);
8542 MoveD2L_reg_reg(dst, tmp);
8543 %}
8544 %}
8547 instruct convI2D_helper(regD dst, regF tmp) %{
8548 effect(USE tmp, DEF dst);
8549 format %{ "FITOD $tmp,$dst" %}
8550 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8551 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8552 ins_pipe(fcvtI2D);
8553 %}
8555 instruct convI2D_stk(stackSlotI src, regD dst) %{
8556 match(Set dst (ConvI2D src));
8557 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8558 expand %{
8559 regF tmp;
8560 stkI_to_regF(tmp, src);
8561 convI2D_helper(dst, tmp);
8562 %}
8563 %}
8565 instruct convI2D_reg(regD_low dst, iRegI src) %{
8566 predicate(UseVIS >= 3);
8567 match(Set dst (ConvI2D src));
8568 expand %{
8569 regF tmp;
8570 MoveI2F_reg_reg(tmp, src);
8571 convI2D_helper(dst, tmp);
8572 %}
8573 %}
8575 instruct convI2D_mem(regD_low dst, memory mem) %{
8576 match(Set dst (ConvI2D (LoadI mem)));
8577 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8578 size(8);
8579 format %{ "LDF $mem,$dst\n\t"
8580 "FITOD $dst,$dst" %}
8581 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8582 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8583 ins_pipe(floadF_mem);
8584 %}
8587 instruct convI2F_helper(regF dst, regF tmp) %{
8588 effect(DEF dst, USE tmp);
8589 format %{ "FITOS $tmp,$dst" %}
8590 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8591 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8592 ins_pipe(fcvtI2F);
8593 %}
8595 instruct convI2F_stk(regF dst, stackSlotI src) %{
8596 match(Set dst (ConvI2F src));
8597 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8598 expand %{
8599 regF tmp;
8600 stkI_to_regF(tmp,src);
8601 convI2F_helper(dst, tmp);
8602 %}
8603 %}
8605 instruct convI2F_reg(regF dst, iRegI src) %{
8606 predicate(UseVIS >= 3);
8607 match(Set dst (ConvI2F src));
8608 ins_cost(DEFAULT_COST);
8609 expand %{
8610 regF tmp;
8611 MoveI2F_reg_reg(tmp, src);
8612 convI2F_helper(dst, tmp);
8613 %}
8614 %}
8616 instruct convI2F_mem( regF dst, memory mem ) %{
8617 match(Set dst (ConvI2F (LoadI mem)));
8618 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8619 size(8);
8620 format %{ "LDF $mem,$dst\n\t"
8621 "FITOS $dst,$dst" %}
8622 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8623 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8624 ins_pipe(floadF_mem);
8625 %}
8628 instruct convI2L_reg(iRegL dst, iRegI src) %{
8629 match(Set dst (ConvI2L src));
8630 size(4);
8631 format %{ "SRA $src,0,$dst\t! int->long" %}
8632 opcode(Assembler::sra_op3, Assembler::arith_op);
8633 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8634 ins_pipe(ialu_reg_reg);
8635 %}
8637 // Zero-extend convert int to long
8638 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8639 match(Set dst (AndL (ConvI2L src) mask) );
8640 size(4);
8641 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8642 opcode(Assembler::srl_op3, Assembler::arith_op);
8643 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8644 ins_pipe(ialu_reg_reg);
8645 %}
8647 // Zero-extend long
8648 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8649 match(Set dst (AndL src mask) );
8650 size(4);
8651 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8652 opcode(Assembler::srl_op3, Assembler::arith_op);
8653 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8654 ins_pipe(ialu_reg_reg);
8655 %}
8658 //-----------
8659 // Long to Double conversion using V8 opcodes.
8660 // Still useful because cheetah traps and becomes
8661 // amazingly slow for some common numbers.
8663 // Magic constant, 0x43300000
8664 instruct loadConI_x43300000(iRegI dst) %{
8665 effect(DEF dst);
8666 size(4);
8667 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8668 ins_encode(SetHi22(0x43300000, dst));
8669 ins_pipe(ialu_none);
8670 %}
8672 // Magic constant, 0x41f00000
8673 instruct loadConI_x41f00000(iRegI dst) %{
8674 effect(DEF dst);
8675 size(4);
8676 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8677 ins_encode(SetHi22(0x41f00000, dst));
8678 ins_pipe(ialu_none);
8679 %}
8681 // Construct a double from two float halves
8682 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8683 effect(DEF dst, USE src1, USE src2);
8684 size(8);
8685 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8686 "FMOVS $src2.lo,$dst.lo" %}
8687 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8688 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8689 ins_pipe(faddD_reg_reg);
8690 %}
8692 // Convert integer in high half of a double register (in the lower half of
8693 // the double register file) to double
8694 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8695 effect(DEF dst, USE src);
8696 size(4);
8697 format %{ "FITOD $src,$dst" %}
8698 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8699 ins_encode(form3_opf_rs2D_rdD(src, dst));
8700 ins_pipe(fcvtLHi2D);
8701 %}
8703 // Add float double precision
8704 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8705 effect(DEF dst, USE src1, USE src2);
8706 size(4);
8707 format %{ "FADDD $src1,$src2,$dst" %}
8708 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8709 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8710 ins_pipe(faddD_reg_reg);
8711 %}
8713 // Sub float double precision
8714 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8715 effect(DEF dst, USE src1, USE src2);
8716 size(4);
8717 format %{ "FSUBD $src1,$src2,$dst" %}
8718 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8719 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8720 ins_pipe(faddD_reg_reg);
8721 %}
8723 // Mul float double precision
8724 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8725 effect(DEF dst, USE src1, USE src2);
8726 size(4);
8727 format %{ "FMULD $src1,$src2,$dst" %}
8728 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8729 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8730 ins_pipe(fmulD_reg_reg);
8731 %}
8733 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8734 match(Set dst (ConvL2D src));
8735 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8737 expand %{
8738 regD_low tmpsrc;
8739 iRegI ix43300000;
8740 iRegI ix41f00000;
8741 stackSlotL lx43300000;
8742 stackSlotL lx41f00000;
8743 regD_low dx43300000;
8744 regD dx41f00000;
8745 regD tmp1;
8746 regD_low tmp2;
8747 regD tmp3;
8748 regD tmp4;
8750 stkL_to_regD(tmpsrc, src);
8752 loadConI_x43300000(ix43300000);
8753 loadConI_x41f00000(ix41f00000);
8754 regI_to_stkLHi(lx43300000, ix43300000);
8755 regI_to_stkLHi(lx41f00000, ix41f00000);
8756 stkL_to_regD(dx43300000, lx43300000);
8757 stkL_to_regD(dx41f00000, lx41f00000);
8759 convI2D_regDHi_regD(tmp1, tmpsrc);
8760 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8761 subD_regD_regD(tmp3, tmp2, dx43300000);
8762 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8763 addD_regD_regD(dst, tmp3, tmp4);
8764 %}
8765 %}
8767 // Long to Double conversion using fast fxtof
8768 instruct convL2D_helper(regD dst, regD tmp) %{
8769 effect(DEF dst, USE tmp);
8770 size(4);
8771 format %{ "FXTOD $tmp,$dst" %}
8772 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8773 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8774 ins_pipe(fcvtL2D);
8775 %}
8777 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8778 predicate(VM_Version::has_fast_fxtof());
8779 match(Set dst (ConvL2D src));
8780 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8781 expand %{
8782 regD tmp;
8783 stkL_to_regD(tmp, src);
8784 convL2D_helper(dst, tmp);
8785 %}
8786 %}
8788 instruct convL2D_reg(regD dst, iRegL src) %{
8789 predicate(UseVIS >= 3);
8790 match(Set dst (ConvL2D src));
8791 expand %{
8792 regD tmp;
8793 MoveL2D_reg_reg(tmp, src);
8794 convL2D_helper(dst, tmp);
8795 %}
8796 %}
8798 // Long to Float conversion using fast fxtof
8799 instruct convL2F_helper(regF dst, regD tmp) %{
8800 effect(DEF dst, USE tmp);
8801 size(4);
8802 format %{ "FXTOS $tmp,$dst" %}
8803 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8804 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8805 ins_pipe(fcvtL2F);
8806 %}
8808 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8809 match(Set dst (ConvL2F src));
8810 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8811 expand %{
8812 regD tmp;
8813 stkL_to_regD(tmp, src);
8814 convL2F_helper(dst, tmp);
8815 %}
8816 %}
8818 instruct convL2F_reg(regF dst, iRegL src) %{
8819 predicate(UseVIS >= 3);
8820 match(Set dst (ConvL2F src));
8821 ins_cost(DEFAULT_COST);
8822 expand %{
8823 regD tmp;
8824 MoveL2D_reg_reg(tmp, src);
8825 convL2F_helper(dst, tmp);
8826 %}
8827 %}
8829 //-----------
8831 instruct convL2I_reg(iRegI dst, iRegL src) %{
8832 match(Set dst (ConvL2I src));
8833 #ifndef _LP64
8834 format %{ "MOV $src.lo,$dst\t! long->int" %}
8835 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8836 ins_pipe(ialu_move_reg_I_to_L);
8837 #else
8838 size(4);
8839 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8840 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8841 ins_pipe(ialu_reg);
8842 #endif
8843 %}
8845 // Register Shift Right Immediate
8846 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8847 match(Set dst (ConvL2I (RShiftL src cnt)));
8849 size(4);
8850 format %{ "SRAX $src,$cnt,$dst" %}
8851 opcode(Assembler::srax_op3, Assembler::arith_op);
8852 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8853 ins_pipe(ialu_reg_imm);
8854 %}
8856 // Replicate scalar to packed byte values in Double register
8857 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8858 effect(DEF dst, USE src);
8859 format %{ "SLLX $src,56,$dst\n\t"
8860 "SRLX $dst, 8,O7\n\t"
8861 "OR $dst,O7,$dst\n\t"
8862 "SRLX $dst,16,O7\n\t"
8863 "OR $dst,O7,$dst\n\t"
8864 "SRLX $dst,32,O7\n\t"
8865 "OR $dst,O7,$dst\t! replicate8B" %}
8866 ins_encode( enc_repl8b(src, dst));
8867 ins_pipe(ialu_reg);
8868 %}
8870 // Replicate scalar to packed byte values in Double register
8871 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8872 match(Set dst (Replicate8B src));
8873 expand %{
8874 iRegL tmp;
8875 Repl8B_reg_helper(tmp, src);
8876 regL_to_stkD(dst, tmp);
8877 %}
8878 %}
8880 // Replicate scalar constant to packed byte values in Double register
8881 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8882 match(Set dst (Replicate8B con));
8883 effect(KILL tmp);
8884 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8885 ins_encode %{
8886 // XXX This is a quick fix for 6833573.
8887 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8888 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8889 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8890 %}
8891 ins_pipe(loadConFD);
8892 %}
8894 // Replicate scalar to packed char values into stack slot
8895 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8896 effect(DEF dst, USE src);
8897 format %{ "SLLX $src,48,$dst\n\t"
8898 "SRLX $dst,16,O7\n\t"
8899 "OR $dst,O7,$dst\n\t"
8900 "SRLX $dst,32,O7\n\t"
8901 "OR $dst,O7,$dst\t! replicate4C" %}
8902 ins_encode( enc_repl4s(src, dst) );
8903 ins_pipe(ialu_reg);
8904 %}
8906 // Replicate scalar to packed char values into stack slot
8907 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8908 match(Set dst (Replicate4C src));
8909 expand %{
8910 iRegL tmp;
8911 Repl4C_reg_helper(tmp, src);
8912 regL_to_stkD(dst, tmp);
8913 %}
8914 %}
8916 // Replicate scalar constant to packed char values in Double register
8917 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8918 match(Set dst (Replicate4C con));
8919 effect(KILL tmp);
8920 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8921 ins_encode %{
8922 // XXX This is a quick fix for 6833573.
8923 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8924 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8925 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8926 %}
8927 ins_pipe(loadConFD);
8928 %}
8930 // Replicate scalar to packed short values into stack slot
8931 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8932 effect(DEF dst, USE src);
8933 format %{ "SLLX $src,48,$dst\n\t"
8934 "SRLX $dst,16,O7\n\t"
8935 "OR $dst,O7,$dst\n\t"
8936 "SRLX $dst,32,O7\n\t"
8937 "OR $dst,O7,$dst\t! replicate4S" %}
8938 ins_encode( enc_repl4s(src, dst) );
8939 ins_pipe(ialu_reg);
8940 %}
8942 // Replicate scalar to packed short values into stack slot
8943 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8944 match(Set dst (Replicate4S src));
8945 expand %{
8946 iRegL tmp;
8947 Repl4S_reg_helper(tmp, src);
8948 regL_to_stkD(dst, tmp);
8949 %}
8950 %}
8952 // Replicate scalar constant to packed short values in Double register
8953 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8954 match(Set dst (Replicate4S con));
8955 effect(KILL tmp);
8956 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8957 ins_encode %{
8958 // XXX This is a quick fix for 6833573.
8959 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8960 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8961 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8962 %}
8963 ins_pipe(loadConFD);
8964 %}
8966 // Replicate scalar to packed int values in Double register
8967 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8968 effect(DEF dst, USE src);
8969 format %{ "SLLX $src,32,$dst\n\t"
8970 "SRLX $dst,32,O7\n\t"
8971 "OR $dst,O7,$dst\t! replicate2I" %}
8972 ins_encode( enc_repl2i(src, dst));
8973 ins_pipe(ialu_reg);
8974 %}
8976 // Replicate scalar to packed int values in Double register
8977 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8978 match(Set dst (Replicate2I src));
8979 expand %{
8980 iRegL tmp;
8981 Repl2I_reg_helper(tmp, src);
8982 regL_to_stkD(dst, tmp);
8983 %}
8984 %}
8986 // Replicate scalar zero constant to packed int values in Double register
8987 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
8988 match(Set dst (Replicate2I con));
8989 effect(KILL tmp);
8990 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8991 ins_encode %{
8992 // XXX This is a quick fix for 6833573.
8993 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8994 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
8995 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8996 %}
8997 ins_pipe(loadConFD);
8998 %}
9000 //----------Control Flow Instructions------------------------------------------
9001 // Compare Instructions
9002 // Compare Integers
9003 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
9004 match(Set icc (CmpI op1 op2));
9005 effect( DEF icc, USE op1, USE op2 );
9007 size(4);
9008 format %{ "CMP $op1,$op2" %}
9009 opcode(Assembler::subcc_op3, Assembler::arith_op);
9010 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9011 ins_pipe(ialu_cconly_reg_reg);
9012 %}
9014 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
9015 match(Set icc (CmpU op1 op2));
9017 size(4);
9018 format %{ "CMP $op1,$op2\t! unsigned" %}
9019 opcode(Assembler::subcc_op3, Assembler::arith_op);
9020 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9021 ins_pipe(ialu_cconly_reg_reg);
9022 %}
9024 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
9025 match(Set icc (CmpI op1 op2));
9026 effect( DEF icc, USE op1 );
9028 size(4);
9029 format %{ "CMP $op1,$op2" %}
9030 opcode(Assembler::subcc_op3, Assembler::arith_op);
9031 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9032 ins_pipe(ialu_cconly_reg_imm);
9033 %}
9035 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
9036 match(Set icc (CmpI (AndI op1 op2) zero));
9038 size(4);
9039 format %{ "BTST $op2,$op1" %}
9040 opcode(Assembler::andcc_op3, Assembler::arith_op);
9041 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9042 ins_pipe(ialu_cconly_reg_reg_zero);
9043 %}
9045 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
9046 match(Set icc (CmpI (AndI op1 op2) zero));
9048 size(4);
9049 format %{ "BTST $op2,$op1" %}
9050 opcode(Assembler::andcc_op3, Assembler::arith_op);
9051 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9052 ins_pipe(ialu_cconly_reg_imm_zero);
9053 %}
9055 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
9056 match(Set xcc (CmpL op1 op2));
9057 effect( DEF xcc, USE op1, USE op2 );
9059 size(4);
9060 format %{ "CMP $op1,$op2\t\t! long" %}
9061 opcode(Assembler::subcc_op3, Assembler::arith_op);
9062 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9063 ins_pipe(ialu_cconly_reg_reg);
9064 %}
9066 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
9067 match(Set xcc (CmpL op1 con));
9068 effect( DEF xcc, USE op1, USE con );
9070 size(4);
9071 format %{ "CMP $op1,$con\t\t! long" %}
9072 opcode(Assembler::subcc_op3, Assembler::arith_op);
9073 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9074 ins_pipe(ialu_cconly_reg_reg);
9075 %}
9077 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
9078 match(Set xcc (CmpL (AndL op1 op2) zero));
9079 effect( DEF xcc, USE op1, USE op2 );
9081 size(4);
9082 format %{ "BTST $op1,$op2\t\t! long" %}
9083 opcode(Assembler::andcc_op3, Assembler::arith_op);
9084 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9085 ins_pipe(ialu_cconly_reg_reg);
9086 %}
9088 // useful for checking the alignment of a pointer:
9089 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9090 match(Set xcc (CmpL (AndL op1 con) zero));
9091 effect( DEF xcc, USE op1, USE con );
9093 size(4);
9094 format %{ "BTST $op1,$con\t\t! long" %}
9095 opcode(Assembler::andcc_op3, Assembler::arith_op);
9096 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9097 ins_pipe(ialu_cconly_reg_reg);
9098 %}
9100 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
9101 match(Set icc (CmpU op1 op2));
9103 size(4);
9104 format %{ "CMP $op1,$op2\t! unsigned" %}
9105 opcode(Assembler::subcc_op3, Assembler::arith_op);
9106 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9107 ins_pipe(ialu_cconly_reg_imm);
9108 %}
9110 // Compare Pointers
9111 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9112 match(Set pcc (CmpP op1 op2));
9114 size(4);
9115 format %{ "CMP $op1,$op2\t! ptr" %}
9116 opcode(Assembler::subcc_op3, Assembler::arith_op);
9117 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9118 ins_pipe(ialu_cconly_reg_reg);
9119 %}
9121 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9122 match(Set pcc (CmpP op1 op2));
9124 size(4);
9125 format %{ "CMP $op1,$op2\t! ptr" %}
9126 opcode(Assembler::subcc_op3, Assembler::arith_op);
9127 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9128 ins_pipe(ialu_cconly_reg_imm);
9129 %}
9131 // Compare Narrow oops
9132 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9133 match(Set icc (CmpN op1 op2));
9135 size(4);
9136 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9137 opcode(Assembler::subcc_op3, Assembler::arith_op);
9138 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9139 ins_pipe(ialu_cconly_reg_reg);
9140 %}
9142 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9143 match(Set icc (CmpN op1 op2));
9145 size(4);
9146 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9147 opcode(Assembler::subcc_op3, Assembler::arith_op);
9148 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9149 ins_pipe(ialu_cconly_reg_imm);
9150 %}
9152 //----------Max and Min--------------------------------------------------------
9153 // Min Instructions
9154 // Conditional move for min
9155 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9156 effect( USE_DEF op2, USE op1, USE icc );
9158 size(4);
9159 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9160 opcode(Assembler::less);
9161 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9162 ins_pipe(ialu_reg_flags);
9163 %}
9165 // Min Register with Register.
9166 instruct minI_eReg(iRegI op1, iRegI op2) %{
9167 match(Set op2 (MinI op1 op2));
9168 ins_cost(DEFAULT_COST*2);
9169 expand %{
9170 flagsReg icc;
9171 compI_iReg(icc,op1,op2);
9172 cmovI_reg_lt(op2,op1,icc);
9173 %}
9174 %}
9176 // Max Instructions
9177 // Conditional move for max
9178 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9179 effect( USE_DEF op2, USE op1, USE icc );
9180 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9181 opcode(Assembler::greater);
9182 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9183 ins_pipe(ialu_reg_flags);
9184 %}
9186 // Max Register with Register
9187 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9188 match(Set op2 (MaxI op1 op2));
9189 ins_cost(DEFAULT_COST*2);
9190 expand %{
9191 flagsReg icc;
9192 compI_iReg(icc,op1,op2);
9193 cmovI_reg_gt(op2,op1,icc);
9194 %}
9195 %}
9198 //----------Float Compares----------------------------------------------------
9199 // Compare floating, generate condition code
9200 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9201 match(Set fcc (CmpF src1 src2));
9203 size(4);
9204 format %{ "FCMPs $fcc,$src1,$src2" %}
9205 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9206 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9207 ins_pipe(faddF_fcc_reg_reg_zero);
9208 %}
9210 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9211 match(Set fcc (CmpD src1 src2));
9213 size(4);
9214 format %{ "FCMPd $fcc,$src1,$src2" %}
9215 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9216 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9217 ins_pipe(faddD_fcc_reg_reg_zero);
9218 %}
9221 // Compare floating, generate -1,0,1
9222 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9223 match(Set dst (CmpF3 src1 src2));
9224 effect(KILL fcc0);
9225 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9226 format %{ "fcmpl $dst,$src1,$src2" %}
9227 // Primary = float
9228 opcode( true );
9229 ins_encode( floating_cmp( dst, src1, src2 ) );
9230 ins_pipe( floating_cmp );
9231 %}
9233 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9234 match(Set dst (CmpD3 src1 src2));
9235 effect(KILL fcc0);
9236 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9237 format %{ "dcmpl $dst,$src1,$src2" %}
9238 // Primary = double (not float)
9239 opcode( false );
9240 ins_encode( floating_cmp( dst, src1, src2 ) );
9241 ins_pipe( floating_cmp );
9242 %}
9244 //----------Branches---------------------------------------------------------
9245 // Jump
9246 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9247 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9248 match(Jump switch_val);
9250 ins_cost(350);
9252 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9253 "LD [O7 + $switch_val], O7\n\t"
9254 "JUMP O7"
9255 %}
9256 ins_encode %{
9257 // Calculate table address into a register.
9258 Register table_reg;
9259 Register label_reg = O7;
9260 if (constant_offset() == 0) {
9261 table_reg = $constanttablebase;
9262 } else {
9263 table_reg = O7;
9264 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9265 __ add($constanttablebase, con_offset, table_reg);
9266 }
9268 // Jump to base address + switch value
9269 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9270 __ jmp(label_reg, G0);
9271 __ delayed()->nop();
9272 %}
9273 ins_pipe(ialu_reg_reg);
9274 %}
9276 // Direct Branch. Use V8 version with longer range.
9277 instruct branch(label labl) %{
9278 match(Goto);
9279 effect(USE labl);
9281 size(8);
9282 ins_cost(BRANCH_COST);
9283 format %{ "BA $labl" %}
9284 ins_encode %{
9285 Label* L = $labl$$label;
9286 __ ba(*L);
9287 __ delayed()->nop();
9288 %}
9289 ins_pipe(br);
9290 %}
9292 // Direct Branch, short with no delay slot
9293 instruct branch_short(label labl) %{
9294 match(Goto);
9295 predicate(UseCBCond);
9296 effect(USE labl);
9298 size(4);
9299 ins_cost(BRANCH_COST);
9300 format %{ "BA $labl\t! short branch" %}
9301 ins_encode %{
9302 Label* L = $labl$$label;
9303 assert(__ use_cbcond(*L), "back to back cbcond");
9304 __ ba_short(*L);
9305 %}
9306 ins_short_branch(1);
9307 ins_avoid_back_to_back(1);
9308 ins_pipe(cbcond_reg_imm);
9309 %}
9311 // Conditional Direct Branch
9312 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9313 match(If cmp icc);
9314 effect(USE labl);
9316 size(8);
9317 ins_cost(BRANCH_COST);
9318 format %{ "BP$cmp $icc,$labl" %}
9319 // Prim = bits 24-22, Secnd = bits 31-30
9320 ins_encode( enc_bp( labl, cmp, icc ) );
9321 ins_pipe(br_cc);
9322 %}
9324 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9325 match(If cmp icc);
9326 effect(USE labl);
9328 ins_cost(BRANCH_COST);
9329 format %{ "BP$cmp $icc,$labl" %}
9330 // Prim = bits 24-22, Secnd = bits 31-30
9331 ins_encode( enc_bp( labl, cmp, icc ) );
9332 ins_pipe(br_cc);
9333 %}
9335 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9336 match(If cmp pcc);
9337 effect(USE labl);
9339 size(8);
9340 ins_cost(BRANCH_COST);
9341 format %{ "BP$cmp $pcc,$labl" %}
9342 ins_encode %{
9343 Label* L = $labl$$label;
9344 Assembler::Predict predict_taken =
9345 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9347 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9348 __ delayed()->nop();
9349 %}
9350 ins_pipe(br_cc);
9351 %}
9353 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9354 match(If cmp fcc);
9355 effect(USE labl);
9357 size(8);
9358 ins_cost(BRANCH_COST);
9359 format %{ "FBP$cmp $fcc,$labl" %}
9360 ins_encode %{
9361 Label* L = $labl$$label;
9362 Assembler::Predict predict_taken =
9363 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9365 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9366 __ delayed()->nop();
9367 %}
9368 ins_pipe(br_fcc);
9369 %}
9371 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9372 match(CountedLoopEnd cmp icc);
9373 effect(USE labl);
9375 size(8);
9376 ins_cost(BRANCH_COST);
9377 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9378 // Prim = bits 24-22, Secnd = bits 31-30
9379 ins_encode( enc_bp( labl, cmp, icc ) );
9380 ins_pipe(br_cc);
9381 %}
9383 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9384 match(CountedLoopEnd cmp icc);
9385 effect(USE labl);
9387 size(8);
9388 ins_cost(BRANCH_COST);
9389 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9390 // Prim = bits 24-22, Secnd = bits 31-30
9391 ins_encode( enc_bp( labl, cmp, icc ) );
9392 ins_pipe(br_cc);
9393 %}
9395 // Compare and branch instructions
9396 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9397 match(If cmp (CmpI op1 op2));
9398 effect(USE labl, KILL icc);
9400 size(12);
9401 ins_cost(BRANCH_COST);
9402 format %{ "CMP $op1,$op2\t! int\n\t"
9403 "BP$cmp $labl" %}
9404 ins_encode %{
9405 Label* L = $labl$$label;
9406 Assembler::Predict predict_taken =
9407 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9408 __ cmp($op1$$Register, $op2$$Register);
9409 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9410 __ delayed()->nop();
9411 %}
9412 ins_pipe(cmp_br_reg_reg);
9413 %}
9415 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9416 match(If cmp (CmpI op1 op2));
9417 effect(USE labl, KILL icc);
9419 size(12);
9420 ins_cost(BRANCH_COST);
9421 format %{ "CMP $op1,$op2\t! int\n\t"
9422 "BP$cmp $labl" %}
9423 ins_encode %{
9424 Label* L = $labl$$label;
9425 Assembler::Predict predict_taken =
9426 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9427 __ cmp($op1$$Register, $op2$$constant);
9428 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9429 __ delayed()->nop();
9430 %}
9431 ins_pipe(cmp_br_reg_imm);
9432 %}
9434 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9435 match(If cmp (CmpU op1 op2));
9436 effect(USE labl, KILL icc);
9438 size(12);
9439 ins_cost(BRANCH_COST);
9440 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9441 "BP$cmp $labl" %}
9442 ins_encode %{
9443 Label* L = $labl$$label;
9444 Assembler::Predict predict_taken =
9445 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9446 __ cmp($op1$$Register, $op2$$Register);
9447 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9448 __ delayed()->nop();
9449 %}
9450 ins_pipe(cmp_br_reg_reg);
9451 %}
9453 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9454 match(If cmp (CmpU op1 op2));
9455 effect(USE labl, KILL icc);
9457 size(12);
9458 ins_cost(BRANCH_COST);
9459 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9460 "BP$cmp $labl" %}
9461 ins_encode %{
9462 Label* L = $labl$$label;
9463 Assembler::Predict predict_taken =
9464 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9465 __ cmp($op1$$Register, $op2$$constant);
9466 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9467 __ delayed()->nop();
9468 %}
9469 ins_pipe(cmp_br_reg_imm);
9470 %}
9472 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9473 match(If cmp (CmpL op1 op2));
9474 effect(USE labl, KILL xcc);
9476 size(12);
9477 ins_cost(BRANCH_COST);
9478 format %{ "CMP $op1,$op2\t! long\n\t"
9479 "BP$cmp $labl" %}
9480 ins_encode %{
9481 Label* L = $labl$$label;
9482 Assembler::Predict predict_taken =
9483 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9484 __ cmp($op1$$Register, $op2$$Register);
9485 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9486 __ delayed()->nop();
9487 %}
9488 ins_pipe(cmp_br_reg_reg);
9489 %}
9491 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9492 match(If cmp (CmpL op1 op2));
9493 effect(USE labl, KILL xcc);
9495 size(12);
9496 ins_cost(BRANCH_COST);
9497 format %{ "CMP $op1,$op2\t! long\n\t"
9498 "BP$cmp $labl" %}
9499 ins_encode %{
9500 Label* L = $labl$$label;
9501 Assembler::Predict predict_taken =
9502 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9503 __ cmp($op1$$Register, $op2$$constant);
9504 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9505 __ delayed()->nop();
9506 %}
9507 ins_pipe(cmp_br_reg_imm);
9508 %}
9510 // Compare Pointers and branch
9511 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9512 match(If cmp (CmpP op1 op2));
9513 effect(USE labl, KILL pcc);
9515 size(12);
9516 ins_cost(BRANCH_COST);
9517 format %{ "CMP $op1,$op2\t! ptr\n\t"
9518 "B$cmp $labl" %}
9519 ins_encode %{
9520 Label* L = $labl$$label;
9521 Assembler::Predict predict_taken =
9522 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9523 __ cmp($op1$$Register, $op2$$Register);
9524 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9525 __ delayed()->nop();
9526 %}
9527 ins_pipe(cmp_br_reg_reg);
9528 %}
9530 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9531 match(If cmp (CmpP op1 null));
9532 effect(USE labl, KILL pcc);
9534 size(12);
9535 ins_cost(BRANCH_COST);
9536 format %{ "CMP $op1,0\t! ptr\n\t"
9537 "B$cmp $labl" %}
9538 ins_encode %{
9539 Label* L = $labl$$label;
9540 Assembler::Predict predict_taken =
9541 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9542 __ cmp($op1$$Register, G0);
9543 // bpr() is not used here since it has shorter distance.
9544 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9545 __ delayed()->nop();
9546 %}
9547 ins_pipe(cmp_br_reg_reg);
9548 %}
9550 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9551 match(If cmp (CmpN op1 op2));
9552 effect(USE labl, KILL icc);
9554 size(12);
9555 ins_cost(BRANCH_COST);
9556 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9557 "BP$cmp $labl" %}
9558 ins_encode %{
9559 Label* L = $labl$$label;
9560 Assembler::Predict predict_taken =
9561 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9562 __ cmp($op1$$Register, $op2$$Register);
9563 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9564 __ delayed()->nop();
9565 %}
9566 ins_pipe(cmp_br_reg_reg);
9567 %}
9569 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9570 match(If cmp (CmpN op1 null));
9571 effect(USE labl, KILL icc);
9573 size(12);
9574 ins_cost(BRANCH_COST);
9575 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9576 "BP$cmp $labl" %}
9577 ins_encode %{
9578 Label* L = $labl$$label;
9579 Assembler::Predict predict_taken =
9580 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9581 __ cmp($op1$$Register, G0);
9582 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9583 __ delayed()->nop();
9584 %}
9585 ins_pipe(cmp_br_reg_reg);
9586 %}
9588 // Loop back branch
9589 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9590 match(CountedLoopEnd cmp (CmpI op1 op2));
9591 effect(USE labl, KILL icc);
9593 size(12);
9594 ins_cost(BRANCH_COST);
9595 format %{ "CMP $op1,$op2\t! int\n\t"
9596 "BP$cmp $labl\t! Loop end" %}
9597 ins_encode %{
9598 Label* L = $labl$$label;
9599 Assembler::Predict predict_taken =
9600 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9601 __ cmp($op1$$Register, $op2$$Register);
9602 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9603 __ delayed()->nop();
9604 %}
9605 ins_pipe(cmp_br_reg_reg);
9606 %}
9608 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9609 match(CountedLoopEnd cmp (CmpI op1 op2));
9610 effect(USE labl, KILL icc);
9612 size(12);
9613 ins_cost(BRANCH_COST);
9614 format %{ "CMP $op1,$op2\t! int\n\t"
9615 "BP$cmp $labl\t! Loop end" %}
9616 ins_encode %{
9617 Label* L = $labl$$label;
9618 Assembler::Predict predict_taken =
9619 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9620 __ cmp($op1$$Register, $op2$$constant);
9621 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9622 __ delayed()->nop();
9623 %}
9624 ins_pipe(cmp_br_reg_imm);
9625 %}
9627 // Short compare and branch instructions
9628 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9629 match(If cmp (CmpI op1 op2));
9630 predicate(UseCBCond);
9631 effect(USE labl, KILL icc);
9633 size(4);
9634 ins_cost(BRANCH_COST);
9635 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9636 ins_encode %{
9637 Label* L = $labl$$label;
9638 assert(__ use_cbcond(*L), "back to back cbcond");
9639 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9640 %}
9641 ins_short_branch(1);
9642 ins_avoid_back_to_back(1);
9643 ins_pipe(cbcond_reg_reg);
9644 %}
9646 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9647 match(If cmp (CmpI op1 op2));
9648 predicate(UseCBCond);
9649 effect(USE labl, KILL icc);
9651 size(4);
9652 ins_cost(BRANCH_COST);
9653 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9654 ins_encode %{
9655 Label* L = $labl$$label;
9656 assert(__ use_cbcond(*L), "back to back cbcond");
9657 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9658 %}
9659 ins_short_branch(1);
9660 ins_avoid_back_to_back(1);
9661 ins_pipe(cbcond_reg_imm);
9662 %}
9664 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9665 match(If cmp (CmpU op1 op2));
9666 predicate(UseCBCond);
9667 effect(USE labl, KILL icc);
9669 size(4);
9670 ins_cost(BRANCH_COST);
9671 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9672 ins_encode %{
9673 Label* L = $labl$$label;
9674 assert(__ use_cbcond(*L), "back to back cbcond");
9675 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9676 %}
9677 ins_short_branch(1);
9678 ins_avoid_back_to_back(1);
9679 ins_pipe(cbcond_reg_reg);
9680 %}
9682 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9683 match(If cmp (CmpU op1 op2));
9684 predicate(UseCBCond);
9685 effect(USE labl, KILL icc);
9687 size(4);
9688 ins_cost(BRANCH_COST);
9689 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9690 ins_encode %{
9691 Label* L = $labl$$label;
9692 assert(__ use_cbcond(*L), "back to back cbcond");
9693 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9694 %}
9695 ins_short_branch(1);
9696 ins_avoid_back_to_back(1);
9697 ins_pipe(cbcond_reg_imm);
9698 %}
9700 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9701 match(If cmp (CmpL op1 op2));
9702 predicate(UseCBCond);
9703 effect(USE labl, KILL xcc);
9705 size(4);
9706 ins_cost(BRANCH_COST);
9707 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9708 ins_encode %{
9709 Label* L = $labl$$label;
9710 assert(__ use_cbcond(*L), "back to back cbcond");
9711 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9712 %}
9713 ins_short_branch(1);
9714 ins_avoid_back_to_back(1);
9715 ins_pipe(cbcond_reg_reg);
9716 %}
9718 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9719 match(If cmp (CmpL op1 op2));
9720 predicate(UseCBCond);
9721 effect(USE labl, KILL xcc);
9723 size(4);
9724 ins_cost(BRANCH_COST);
9725 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9726 ins_encode %{
9727 Label* L = $labl$$label;
9728 assert(__ use_cbcond(*L), "back to back cbcond");
9729 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9730 %}
9731 ins_short_branch(1);
9732 ins_avoid_back_to_back(1);
9733 ins_pipe(cbcond_reg_imm);
9734 %}
9736 // Compare Pointers and branch
9737 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9738 match(If cmp (CmpP op1 op2));
9739 predicate(UseCBCond);
9740 effect(USE labl, KILL pcc);
9742 size(4);
9743 ins_cost(BRANCH_COST);
9744 #ifdef _LP64
9745 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9746 #else
9747 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9748 #endif
9749 ins_encode %{
9750 Label* L = $labl$$label;
9751 assert(__ use_cbcond(*L), "back to back cbcond");
9752 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9753 %}
9754 ins_short_branch(1);
9755 ins_avoid_back_to_back(1);
9756 ins_pipe(cbcond_reg_reg);
9757 %}
9759 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9760 match(If cmp (CmpP op1 null));
9761 predicate(UseCBCond);
9762 effect(USE labl, KILL pcc);
9764 size(4);
9765 ins_cost(BRANCH_COST);
9766 #ifdef _LP64
9767 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9768 #else
9769 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9770 #endif
9771 ins_encode %{
9772 Label* L = $labl$$label;
9773 assert(__ use_cbcond(*L), "back to back cbcond");
9774 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9775 %}
9776 ins_short_branch(1);
9777 ins_avoid_back_to_back(1);
9778 ins_pipe(cbcond_reg_reg);
9779 %}
9781 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9782 match(If cmp (CmpN op1 op2));
9783 predicate(UseCBCond);
9784 effect(USE labl, KILL icc);
9786 size(4);
9787 ins_cost(BRANCH_COST);
9788 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9789 ins_encode %{
9790 Label* L = $labl$$label;
9791 assert(__ use_cbcond(*L), "back to back cbcond");
9792 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9793 %}
9794 ins_short_branch(1);
9795 ins_avoid_back_to_back(1);
9796 ins_pipe(cbcond_reg_reg);
9797 %}
9799 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9800 match(If cmp (CmpN op1 null));
9801 predicate(UseCBCond);
9802 effect(USE labl, KILL icc);
9804 size(4);
9805 ins_cost(BRANCH_COST);
9806 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9807 ins_encode %{
9808 Label* L = $labl$$label;
9809 assert(__ use_cbcond(*L), "back to back cbcond");
9810 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9811 %}
9812 ins_short_branch(1);
9813 ins_avoid_back_to_back(1);
9814 ins_pipe(cbcond_reg_reg);
9815 %}
9817 // Loop back branch
9818 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9819 match(CountedLoopEnd cmp (CmpI op1 op2));
9820 predicate(UseCBCond);
9821 effect(USE labl, KILL icc);
9823 size(4);
9824 ins_cost(BRANCH_COST);
9825 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9826 ins_encode %{
9827 Label* L = $labl$$label;
9828 assert(__ use_cbcond(*L), "back to back cbcond");
9829 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9830 %}
9831 ins_short_branch(1);
9832 ins_avoid_back_to_back(1);
9833 ins_pipe(cbcond_reg_reg);
9834 %}
9836 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9837 match(CountedLoopEnd cmp (CmpI op1 op2));
9838 predicate(UseCBCond);
9839 effect(USE labl, KILL icc);
9841 size(4);
9842 ins_cost(BRANCH_COST);
9843 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9844 ins_encode %{
9845 Label* L = $labl$$label;
9846 assert(__ use_cbcond(*L), "back to back cbcond");
9847 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9848 %}
9849 ins_short_branch(1);
9850 ins_avoid_back_to_back(1);
9851 ins_pipe(cbcond_reg_imm);
9852 %}
9854 // Branch-on-register tests all 64 bits. We assume that values
9855 // in 64-bit registers always remains zero or sign extended
9856 // unless our code munges the high bits. Interrupts can chop
9857 // the high order bits to zero or sign at any time.
9858 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9859 match(If cmp (CmpI op1 zero));
9860 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9861 effect(USE labl);
9863 size(8);
9864 ins_cost(BRANCH_COST);
9865 format %{ "BR$cmp $op1,$labl" %}
9866 ins_encode( enc_bpr( labl, cmp, op1 ) );
9867 ins_pipe(br_reg);
9868 %}
9870 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9871 match(If cmp (CmpP op1 null));
9872 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9873 effect(USE labl);
9875 size(8);
9876 ins_cost(BRANCH_COST);
9877 format %{ "BR$cmp $op1,$labl" %}
9878 ins_encode( enc_bpr( labl, cmp, op1 ) );
9879 ins_pipe(br_reg);
9880 %}
9882 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9883 match(If cmp (CmpL op1 zero));
9884 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9885 effect(USE labl);
9887 size(8);
9888 ins_cost(BRANCH_COST);
9889 format %{ "BR$cmp $op1,$labl" %}
9890 ins_encode( enc_bpr( labl, cmp, op1 ) );
9891 ins_pipe(br_reg);
9892 %}
9895 // ============================================================================
9896 // Long Compare
9897 //
9898 // Currently we hold longs in 2 registers. Comparing such values efficiently
9899 // is tricky. The flavor of compare used depends on whether we are testing
9900 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9901 // The GE test is the negated LT test. The LE test can be had by commuting
9902 // the operands (yielding a GE test) and then negating; negate again for the
9903 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9904 // NE test is negated from that.
9906 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9907 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9908 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9909 // are collapsed internally in the ADLC's dfa-gen code. The match for
9910 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9911 // foo match ends up with the wrong leaf. One fix is to not match both
9912 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9913 // both forms beat the trinary form of long-compare and both are very useful
9914 // on Intel which has so few registers.
9916 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9917 match(If cmp xcc);
9918 effect(USE labl);
9920 size(8);
9921 ins_cost(BRANCH_COST);
9922 format %{ "BP$cmp $xcc,$labl" %}
9923 ins_encode %{
9924 Label* L = $labl$$label;
9925 Assembler::Predict predict_taken =
9926 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9928 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9929 __ delayed()->nop();
9930 %}
9931 ins_pipe(br_cc);
9932 %}
9934 // Manifest a CmpL3 result in an integer register. Very painful.
9935 // This is the test to avoid.
9936 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9937 match(Set dst (CmpL3 src1 src2) );
9938 effect( KILL ccr );
9939 ins_cost(6*DEFAULT_COST);
9940 size(24);
9941 format %{ "CMP $src1,$src2\t\t! long\n"
9942 "\tBLT,a,pn done\n"
9943 "\tMOV -1,$dst\t! delay slot\n"
9944 "\tBGT,a,pn done\n"
9945 "\tMOV 1,$dst\t! delay slot\n"
9946 "\tCLR $dst\n"
9947 "done:" %}
9948 ins_encode( cmpl_flag(src1,src2,dst) );
9949 ins_pipe(cmpL_reg);
9950 %}
9952 // Conditional move
9953 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9954 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9955 ins_cost(150);
9956 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9957 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9958 ins_pipe(ialu_reg);
9959 %}
9961 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9962 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9963 ins_cost(140);
9964 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9965 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9966 ins_pipe(ialu_imm);
9967 %}
9969 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9970 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9971 ins_cost(150);
9972 format %{ "MOV$cmp $xcc,$src,$dst" %}
9973 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9974 ins_pipe(ialu_reg);
9975 %}
9977 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9978 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9979 ins_cost(140);
9980 format %{ "MOV$cmp $xcc,$src,$dst" %}
9981 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9982 ins_pipe(ialu_imm);
9983 %}
9985 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9986 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9987 ins_cost(150);
9988 format %{ "MOV$cmp $xcc,$src,$dst" %}
9989 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9990 ins_pipe(ialu_reg);
9991 %}
9993 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9994 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9995 ins_cost(150);
9996 format %{ "MOV$cmp $xcc,$src,$dst" %}
9997 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9998 ins_pipe(ialu_reg);
9999 %}
10001 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
10002 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
10003 ins_cost(140);
10004 format %{ "MOV$cmp $xcc,$src,$dst" %}
10005 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
10006 ins_pipe(ialu_imm);
10007 %}
10009 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
10010 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
10011 ins_cost(150);
10012 opcode(0x101);
10013 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
10014 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
10015 ins_pipe(int_conditional_float_move);
10016 %}
10018 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
10019 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
10020 ins_cost(150);
10021 opcode(0x102);
10022 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
10023 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
10024 ins_pipe(int_conditional_float_move);
10025 %}
10027 // ============================================================================
10028 // Safepoint Instruction
10029 instruct safePoint_poll(iRegP poll) %{
10030 match(SafePoint poll);
10031 effect(USE poll);
10033 size(4);
10034 #ifdef _LP64
10035 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
10036 #else
10037 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
10038 #endif
10039 ins_encode %{
10040 __ relocate(relocInfo::poll_type);
10041 __ ld_ptr($poll$$Register, 0, G0);
10042 %}
10043 ins_pipe(loadPollP);
10044 %}
10046 // ============================================================================
10047 // Call Instructions
10048 // Call Java Static Instruction
10049 instruct CallStaticJavaDirect( method meth ) %{
10050 match(CallStaticJava);
10051 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
10052 effect(USE meth);
10054 size(8);
10055 ins_cost(CALL_COST);
10056 format %{ "CALL,static ; NOP ==> " %}
10057 ins_encode( Java_Static_Call( meth ), call_epilog );
10058 ins_pipe(simple_call);
10059 %}
10061 // Call Java Static Instruction (method handle version)
10062 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
10063 match(CallStaticJava);
10064 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
10065 effect(USE meth, KILL l7_mh_SP_save);
10067 size(16);
10068 ins_cost(CALL_COST);
10069 format %{ "CALL,static/MethodHandle" %}
10070 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
10071 ins_pipe(simple_call);
10072 %}
10074 // Call Java Dynamic Instruction
10075 instruct CallDynamicJavaDirect( method meth ) %{
10076 match(CallDynamicJava);
10077 effect(USE meth);
10079 ins_cost(CALL_COST);
10080 format %{ "SET (empty),R_G5\n\t"
10081 "CALL,dynamic ; NOP ==> " %}
10082 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
10083 ins_pipe(call);
10084 %}
10086 // Call Runtime Instruction
10087 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10088 match(CallRuntime);
10089 effect(USE meth, KILL l7);
10090 ins_cost(CALL_COST);
10091 format %{ "CALL,runtime" %}
10092 ins_encode( Java_To_Runtime( meth ),
10093 call_epilog, adjust_long_from_native_call );
10094 ins_pipe(simple_call);
10095 %}
10097 // Call runtime without safepoint - same as CallRuntime
10098 instruct CallLeafDirect(method meth, l7RegP l7) %{
10099 match(CallLeaf);
10100 effect(USE meth, KILL l7);
10101 ins_cost(CALL_COST);
10102 format %{ "CALL,runtime leaf" %}
10103 ins_encode( Java_To_Runtime( meth ),
10104 call_epilog,
10105 adjust_long_from_native_call );
10106 ins_pipe(simple_call);
10107 %}
10109 // Call runtime without safepoint - same as CallLeaf
10110 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10111 match(CallLeafNoFP);
10112 effect(USE meth, KILL l7);
10113 ins_cost(CALL_COST);
10114 format %{ "CALL,runtime leaf nofp" %}
10115 ins_encode( Java_To_Runtime( meth ),
10116 call_epilog,
10117 adjust_long_from_native_call );
10118 ins_pipe(simple_call);
10119 %}
10121 // Tail Call; Jump from runtime stub to Java code.
10122 // Also known as an 'interprocedural jump'.
10123 // Target of jump will eventually return to caller.
10124 // TailJump below removes the return address.
10125 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10126 match(TailCall jump_target method_oop );
10128 ins_cost(CALL_COST);
10129 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10130 ins_encode(form_jmpl(jump_target));
10131 ins_pipe(tail_call);
10132 %}
10135 // Return Instruction
10136 instruct Ret() %{
10137 match(Return);
10139 // The epilogue node did the ret already.
10140 size(0);
10141 format %{ "! return" %}
10142 ins_encode();
10143 ins_pipe(empty);
10144 %}
10147 // Tail Jump; remove the return address; jump to target.
10148 // TailCall above leaves the return address around.
10149 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10150 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10151 // "restore" before this instruction (in Epilogue), we need to materialize it
10152 // in %i0.
10153 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10154 match( TailJump jump_target ex_oop );
10155 ins_cost(CALL_COST);
10156 format %{ "! discard R_O7\n\t"
10157 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10158 ins_encode(form_jmpl_set_exception_pc(jump_target));
10159 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10160 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10161 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10162 ins_pipe(tail_call);
10163 %}
10165 // Create exception oop: created by stack-crawling runtime code.
10166 // Created exception is now available to this handler, and is setup
10167 // just prior to jumping to this handler. No code emitted.
10168 instruct CreateException( o0RegP ex_oop )
10169 %{
10170 match(Set ex_oop (CreateEx));
10171 ins_cost(0);
10173 size(0);
10174 // use the following format syntax
10175 format %{ "! exception oop is in R_O0; no code emitted" %}
10176 ins_encode();
10177 ins_pipe(empty);
10178 %}
10181 // Rethrow exception:
10182 // The exception oop will come in the first argument position.
10183 // Then JUMP (not call) to the rethrow stub code.
10184 instruct RethrowException()
10185 %{
10186 match(Rethrow);
10187 ins_cost(CALL_COST);
10189 // use the following format syntax
10190 format %{ "Jmp rethrow_stub" %}
10191 ins_encode(enc_rethrow);
10192 ins_pipe(tail_call);
10193 %}
10196 // Die now
10197 instruct ShouldNotReachHere( )
10198 %{
10199 match(Halt);
10200 ins_cost(CALL_COST);
10202 size(4);
10203 // Use the following format syntax
10204 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10205 ins_encode( form2_illtrap() );
10206 ins_pipe(tail_call);
10207 %}
10209 // ============================================================================
10210 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10211 // array for an instance of the superklass. Set a hidden internal cache on a
10212 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10213 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10214 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10215 match(Set index (PartialSubtypeCheck sub super));
10216 effect( KILL pcc, KILL o7 );
10217 ins_cost(DEFAULT_COST*10);
10218 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10219 ins_encode( enc_PartialSubtypeCheck() );
10220 ins_pipe(partial_subtype_check_pipe);
10221 %}
10223 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10224 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10225 effect( KILL idx, KILL o7 );
10226 ins_cost(DEFAULT_COST*10);
10227 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10228 ins_encode( enc_PartialSubtypeCheck() );
10229 ins_pipe(partial_subtype_check_pipe);
10230 %}
10233 // ============================================================================
10234 // inlined locking and unlocking
10236 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
10237 match(Set pcc (FastLock object box));
10239 effect(KILL scratch, TEMP scratch2);
10240 ins_cost(100);
10242 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
10243 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10244 ins_pipe(long_memory_op);
10245 %}
10248 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
10249 match(Set pcc (FastUnlock object box));
10250 effect(KILL scratch, TEMP scratch2);
10251 ins_cost(100);
10253 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
10254 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10255 ins_pipe(long_memory_op);
10256 %}
10258 // The encodings are generic.
10259 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10260 predicate(!use_block_zeroing(n->in(2)) );
10261 match(Set dummy (ClearArray cnt base));
10262 effect(TEMP temp, KILL ccr);
10263 ins_cost(300);
10264 format %{ "MOV $cnt,$temp\n"
10265 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10266 " BRge loop\t\t! Clearing loop\n"
10267 " STX G0,[$base+$temp]\t! delay slot" %}
10269 ins_encode %{
10270 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10271 Register nof_bytes_arg = $cnt$$Register;
10272 Register nof_bytes_tmp = $temp$$Register;
10273 Register base_pointer_arg = $base$$Register;
10275 Label loop;
10276 __ mov(nof_bytes_arg, nof_bytes_tmp);
10278 // Loop and clear, walking backwards through the array.
10279 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10280 __ bind(loop);
10281 __ deccc(nof_bytes_tmp, 8);
10282 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10283 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10284 // %%%% this mini-loop must not cross a cache boundary!
10285 %}
10286 ins_pipe(long_memory_op);
10287 %}
10289 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10290 predicate(use_block_zeroing(n->in(2)));
10291 match(Set dummy (ClearArray cnt base));
10292 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10293 ins_cost(300);
10294 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10296 ins_encode %{
10298 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10299 Register to = $base$$Register;
10300 Register count = $cnt$$Register;
10302 Label Ldone;
10303 __ nop(); // Separate short branches
10304 // Use BIS for zeroing (temp is not used).
10305 __ bis_zeroing(to, count, G0, Ldone);
10306 __ bind(Ldone);
10308 %}
10309 ins_pipe(long_memory_op);
10310 %}
10312 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10313 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10314 match(Set dummy (ClearArray cnt base));
10315 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10316 ins_cost(300);
10317 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10319 ins_encode %{
10321 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10322 Register to = $base$$Register;
10323 Register count = $cnt$$Register;
10324 Register temp = $tmp$$Register;
10326 Label Ldone;
10327 __ nop(); // Separate short branches
10328 // Use BIS for zeroing
10329 __ bis_zeroing(to, count, temp, Ldone);
10330 __ bind(Ldone);
10332 %}
10333 ins_pipe(long_memory_op);
10334 %}
10336 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10337 o7RegI tmp, flagsReg ccr) %{
10338 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10339 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10340 ins_cost(300);
10341 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10342 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10343 ins_pipe(long_memory_op);
10344 %}
10346 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10347 o7RegI tmp, flagsReg ccr) %{
10348 match(Set result (StrEquals (Binary str1 str2) cnt));
10349 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10350 ins_cost(300);
10351 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10352 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10353 ins_pipe(long_memory_op);
10354 %}
10356 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10357 o7RegI tmp2, flagsReg ccr) %{
10358 match(Set result (AryEq ary1 ary2));
10359 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10360 ins_cost(300);
10361 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10362 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10363 ins_pipe(long_memory_op);
10364 %}
10367 //---------- Zeros Count Instructions ------------------------------------------
10369 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10370 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10371 match(Set dst (CountLeadingZerosI src));
10372 effect(TEMP dst, TEMP tmp, KILL cr);
10374 // x |= (x >> 1);
10375 // x |= (x >> 2);
10376 // x |= (x >> 4);
10377 // x |= (x >> 8);
10378 // x |= (x >> 16);
10379 // return (WORDBITS - popc(x));
10380 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10381 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10382 "OR $dst,$tmp,$dst\n\t"
10383 "SRL $dst,2,$tmp\n\t"
10384 "OR $dst,$tmp,$dst\n\t"
10385 "SRL $dst,4,$tmp\n\t"
10386 "OR $dst,$tmp,$dst\n\t"
10387 "SRL $dst,8,$tmp\n\t"
10388 "OR $dst,$tmp,$dst\n\t"
10389 "SRL $dst,16,$tmp\n\t"
10390 "OR $dst,$tmp,$dst\n\t"
10391 "POPC $dst,$dst\n\t"
10392 "MOV 32,$tmp\n\t"
10393 "SUB $tmp,$dst,$dst" %}
10394 ins_encode %{
10395 Register Rdst = $dst$$Register;
10396 Register Rsrc = $src$$Register;
10397 Register Rtmp = $tmp$$Register;
10398 __ srl(Rsrc, 1, Rtmp);
10399 __ srl(Rsrc, 0, Rdst);
10400 __ or3(Rdst, Rtmp, Rdst);
10401 __ srl(Rdst, 2, Rtmp);
10402 __ or3(Rdst, Rtmp, Rdst);
10403 __ srl(Rdst, 4, Rtmp);
10404 __ or3(Rdst, Rtmp, Rdst);
10405 __ srl(Rdst, 8, Rtmp);
10406 __ or3(Rdst, Rtmp, Rdst);
10407 __ srl(Rdst, 16, Rtmp);
10408 __ or3(Rdst, Rtmp, Rdst);
10409 __ popc(Rdst, Rdst);
10410 __ mov(BitsPerInt, Rtmp);
10411 __ sub(Rtmp, Rdst, Rdst);
10412 %}
10413 ins_pipe(ialu_reg);
10414 %}
10416 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10417 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10418 match(Set dst (CountLeadingZerosL src));
10419 effect(TEMP dst, TEMP tmp, KILL cr);
10421 // x |= (x >> 1);
10422 // x |= (x >> 2);
10423 // x |= (x >> 4);
10424 // x |= (x >> 8);
10425 // x |= (x >> 16);
10426 // x |= (x >> 32);
10427 // return (WORDBITS - popc(x));
10428 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10429 "OR $src,$tmp,$dst\n\t"
10430 "SRLX $dst,2,$tmp\n\t"
10431 "OR $dst,$tmp,$dst\n\t"
10432 "SRLX $dst,4,$tmp\n\t"
10433 "OR $dst,$tmp,$dst\n\t"
10434 "SRLX $dst,8,$tmp\n\t"
10435 "OR $dst,$tmp,$dst\n\t"
10436 "SRLX $dst,16,$tmp\n\t"
10437 "OR $dst,$tmp,$dst\n\t"
10438 "SRLX $dst,32,$tmp\n\t"
10439 "OR $dst,$tmp,$dst\n\t"
10440 "POPC $dst,$dst\n\t"
10441 "MOV 64,$tmp\n\t"
10442 "SUB $tmp,$dst,$dst" %}
10443 ins_encode %{
10444 Register Rdst = $dst$$Register;
10445 Register Rsrc = $src$$Register;
10446 Register Rtmp = $tmp$$Register;
10447 __ srlx(Rsrc, 1, Rtmp);
10448 __ or3( Rsrc, Rtmp, Rdst);
10449 __ srlx(Rdst, 2, Rtmp);
10450 __ or3( Rdst, Rtmp, Rdst);
10451 __ srlx(Rdst, 4, Rtmp);
10452 __ or3( Rdst, Rtmp, Rdst);
10453 __ srlx(Rdst, 8, Rtmp);
10454 __ or3( Rdst, Rtmp, Rdst);
10455 __ srlx(Rdst, 16, Rtmp);
10456 __ or3( Rdst, Rtmp, Rdst);
10457 __ srlx(Rdst, 32, Rtmp);
10458 __ or3( Rdst, Rtmp, Rdst);
10459 __ popc(Rdst, Rdst);
10460 __ mov(BitsPerLong, Rtmp);
10461 __ sub(Rtmp, Rdst, Rdst);
10462 %}
10463 ins_pipe(ialu_reg);
10464 %}
10466 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
10467 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10468 match(Set dst (CountTrailingZerosI src));
10469 effect(TEMP dst, KILL cr);
10471 // return popc(~x & (x - 1));
10472 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10473 "ANDN $dst,$src,$dst\n\t"
10474 "SRL $dst,R_G0,$dst\n\t"
10475 "POPC $dst,$dst" %}
10476 ins_encode %{
10477 Register Rdst = $dst$$Register;
10478 Register Rsrc = $src$$Register;
10479 __ sub(Rsrc, 1, Rdst);
10480 __ andn(Rdst, Rsrc, Rdst);
10481 __ srl(Rdst, G0, Rdst);
10482 __ popc(Rdst, Rdst);
10483 %}
10484 ins_pipe(ialu_reg);
10485 %}
10487 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10488 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10489 match(Set dst (CountTrailingZerosL src));
10490 effect(TEMP dst, KILL cr);
10492 // return popc(~x & (x - 1));
10493 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10494 "ANDN $dst,$src,$dst\n\t"
10495 "POPC $dst,$dst" %}
10496 ins_encode %{
10497 Register Rdst = $dst$$Register;
10498 Register Rsrc = $src$$Register;
10499 __ sub(Rsrc, 1, Rdst);
10500 __ andn(Rdst, Rsrc, Rdst);
10501 __ popc(Rdst, Rdst);
10502 %}
10503 ins_pipe(ialu_reg);
10504 %}
10507 //---------- Population Count Instructions -------------------------------------
10509 instruct popCountI(iRegI dst, iRegI src) %{
10510 predicate(UsePopCountInstruction);
10511 match(Set dst (PopCountI src));
10513 format %{ "POPC $src, $dst" %}
10514 ins_encode %{
10515 __ popc($src$$Register, $dst$$Register);
10516 %}
10517 ins_pipe(ialu_reg);
10518 %}
10520 // Note: Long.bitCount(long) returns an int.
10521 instruct popCountL(iRegI dst, iRegL src) %{
10522 predicate(UsePopCountInstruction);
10523 match(Set dst (PopCountL src));
10525 format %{ "POPC $src, $dst" %}
10526 ins_encode %{
10527 __ popc($src$$Register, $dst$$Register);
10528 %}
10529 ins_pipe(ialu_reg);
10530 %}
10533 // ============================================================================
10534 //------------Bytes reverse--------------------------------------------------
10536 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10537 match(Set dst (ReverseBytesI src));
10539 // Op cost is artificially doubled to make sure that load or store
10540 // instructions are preferred over this one which requires a spill
10541 // onto a stack slot.
10542 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10543 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10545 ins_encode %{
10546 __ set($src$$disp + STACK_BIAS, O7);
10547 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10548 %}
10549 ins_pipe( iload_mem );
10550 %}
10552 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10553 match(Set dst (ReverseBytesL src));
10555 // Op cost is artificially doubled to make sure that load or store
10556 // instructions are preferred over this one which requires a spill
10557 // onto a stack slot.
10558 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10559 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10561 ins_encode %{
10562 __ set($src$$disp + STACK_BIAS, O7);
10563 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10564 %}
10565 ins_pipe( iload_mem );
10566 %}
10568 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10569 match(Set dst (ReverseBytesUS src));
10571 // Op cost is artificially doubled to make sure that load or store
10572 // instructions are preferred over this one which requires a spill
10573 // onto a stack slot.
10574 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10575 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10577 ins_encode %{
10578 // the value was spilled as an int so bias the load
10579 __ set($src$$disp + STACK_BIAS + 2, O7);
10580 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10581 %}
10582 ins_pipe( iload_mem );
10583 %}
10585 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10586 match(Set dst (ReverseBytesS src));
10588 // Op cost is artificially doubled to make sure that load or store
10589 // instructions are preferred over this one which requires a spill
10590 // onto a stack slot.
10591 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10592 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10594 ins_encode %{
10595 // the value was spilled as an int so bias the load
10596 __ set($src$$disp + STACK_BIAS + 2, O7);
10597 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10598 %}
10599 ins_pipe( iload_mem );
10600 %}
10602 // Load Integer reversed byte order
10603 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10604 match(Set dst (ReverseBytesI (LoadI src)));
10606 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10607 size(4);
10608 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10610 ins_encode %{
10611 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10612 %}
10613 ins_pipe(iload_mem);
10614 %}
10616 // Load Long - aligned and reversed
10617 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10618 match(Set dst (ReverseBytesL (LoadL src)));
10620 ins_cost(MEMORY_REF_COST);
10621 size(4);
10622 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10624 ins_encode %{
10625 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10626 %}
10627 ins_pipe(iload_mem);
10628 %}
10630 // Load unsigned short / char reversed byte order
10631 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10632 match(Set dst (ReverseBytesUS (LoadUS src)));
10634 ins_cost(MEMORY_REF_COST);
10635 size(4);
10636 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10638 ins_encode %{
10639 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10640 %}
10641 ins_pipe(iload_mem);
10642 %}
10644 // Load short reversed byte order
10645 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10646 match(Set dst (ReverseBytesS (LoadS src)));
10648 ins_cost(MEMORY_REF_COST);
10649 size(4);
10650 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10652 ins_encode %{
10653 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10654 %}
10655 ins_pipe(iload_mem);
10656 %}
10658 // Store Integer reversed byte order
10659 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10660 match(Set dst (StoreI dst (ReverseBytesI src)));
10662 ins_cost(MEMORY_REF_COST);
10663 size(4);
10664 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10666 ins_encode %{
10667 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10668 %}
10669 ins_pipe(istore_mem_reg);
10670 %}
10672 // Store Long reversed byte order
10673 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10674 match(Set dst (StoreL dst (ReverseBytesL src)));
10676 ins_cost(MEMORY_REF_COST);
10677 size(4);
10678 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10680 ins_encode %{
10681 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10682 %}
10683 ins_pipe(istore_mem_reg);
10684 %}
10686 // Store unsighed short/char reversed byte order
10687 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10688 match(Set dst (StoreC dst (ReverseBytesUS src)));
10690 ins_cost(MEMORY_REF_COST);
10691 size(4);
10692 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10694 ins_encode %{
10695 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10696 %}
10697 ins_pipe(istore_mem_reg);
10698 %}
10700 // Store short reversed byte order
10701 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10702 match(Set dst (StoreC dst (ReverseBytesS src)));
10704 ins_cost(MEMORY_REF_COST);
10705 size(4);
10706 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10708 ins_encode %{
10709 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10710 %}
10711 ins_pipe(istore_mem_reg);
10712 %}
10714 //----------PEEPHOLE RULES-----------------------------------------------------
10715 // These must follow all instruction definitions as they use the names
10716 // defined in the instructions definitions.
10717 //
10718 // peepmatch ( root_instr_name [preceding_instruction]* );
10719 //
10720 // peepconstraint %{
10721 // (instruction_number.operand_name relational_op instruction_number.operand_name
10722 // [, ...] );
10723 // // instruction numbers are zero-based using left to right order in peepmatch
10724 //
10725 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10726 // // provide an instruction_number.operand_name for each operand that appears
10727 // // in the replacement instruction's match rule
10728 //
10729 // ---------VM FLAGS---------------------------------------------------------
10730 //
10731 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10732 //
10733 // Each peephole rule is given an identifying number starting with zero and
10734 // increasing by one in the order seen by the parser. An individual peephole
10735 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10736 // on the command-line.
10737 //
10738 // ---------CURRENT LIMITATIONS----------------------------------------------
10739 //
10740 // Only match adjacent instructions in same basic block
10741 // Only equality constraints
10742 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10743 // Only one replacement instruction
10744 //
10745 // ---------EXAMPLE----------------------------------------------------------
10746 //
10747 // // pertinent parts of existing instructions in architecture description
10748 // instruct movI(eRegI dst, eRegI src) %{
10749 // match(Set dst (CopyI src));
10750 // %}
10751 //
10752 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10753 // match(Set dst (AddI dst src));
10754 // effect(KILL cr);
10755 // %}
10756 //
10757 // // Change (inc mov) to lea
10758 // peephole %{
10759 // // increment preceeded by register-register move
10760 // peepmatch ( incI_eReg movI );
10761 // // require that the destination register of the increment
10762 // // match the destination register of the move
10763 // peepconstraint ( 0.dst == 1.dst );
10764 // // construct a replacement instruction that sets
10765 // // the destination to ( move's source register + one )
10766 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10767 // %}
10768 //
10770 // // Change load of spilled value to only a spill
10771 // instruct storeI(memory mem, eRegI src) %{
10772 // match(Set mem (StoreI mem src));
10773 // %}
10774 //
10775 // instruct loadI(eRegI dst, memory mem) %{
10776 // match(Set dst (LoadI mem));
10777 // %}
10778 //
10779 // peephole %{
10780 // peepmatch ( loadI storeI );
10781 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10782 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10783 // %}
10785 //----------SMARTSPILL RULES---------------------------------------------------
10786 // These must follow all instruction definitions as they use the names
10787 // defined in the instructions definitions.
10788 //
10789 // SPARC will probably not have any of these rules due to RISC instruction set.
10791 //----------PIPELINE-----------------------------------------------------------
10792 // Rules which define the behavior of the target architectures pipeline.